MULTI-PROCESSING CACHE COHERENCY PROTOCOL ON A LOCAL BUS

Abstract: A computer system maintaining cache coherency among a plurality of caching devices (210, 220) coupled across a local bus (200) includes a bus master (270), a memory (250), and a plurality of cache complexes (210, 220), all coupled to the local bus (200). When the bus master (270) requests a read or write with the memory (250), the cache complexes (210, 220) snoop the transaction. Each cache complex (210, 220) asserts a busy signal during the snooping process. A detection circuit (260) detects when the busy signals have been de-asserted and asserts a done signal. If one of the snoops results in a cache hit to a dirty line, the respective cache complex (210, 220) asserts a dirty signal. If one of the snoops results in a cache hit to a clean line, the respective cache complex asserts a clean signal. If the memory (250) detects a simultaneous assertion of the dirty signal and the done signal, it halts the transaction request from the bus master (270).

Description: MULTI-PROCESSING CACHE COHERENCY PROTOCOL ON A LOCAL BUS FIELD OF THE INVENTION The present invention relates to the field of computer buses. More particularly, the present invention relates to a multi-processing cache coherency protocol for use on a local processor bus. BACKGROUND OF THE INVENTION In many computer systems, a processor is coupled to an internal or external cache, and possibly an additional external memory device, over a high speed memory bus. This local conglomeration is sometimes termed a processor / cache / memory "complex." (hereinafter denoted as a "cache complex.") Figure 1 illustrates a prior art computer system containing one such cache complex 140. The peripheral devices, such as graphics controllers, hard drives, and add-in boards communicate on a local peripheral bus 100, as shown in Figure 1. A bus bridge 130 may be used to facilitate communication between the local peripheral bus 100 and the processor 110 and cache 120. In many computer systems, part or all of the system memory may be coupled to the local peripheral bus. In these computer systems, peripheral devices, or "bus agents" request transactions with memory 150 across the local peripheral bus. While the bus agents are initiating a read or write transaction with memory 150, they are referred to as bus masters. One such bus master 160 is displayed in Figure 1. When the bus master has initiated a transaction request with the memory, the other cache complexes may monitor, or "snoop," the transaction. This is because a cache complex holds a subset of data elements from the memory that may be altered by the transaction. During the snooping process, the cache complex searches its cache for the data element requested by the bus master. The cache complex maintains coherency by using one of several well-known protocols. One such protocol is the write-through protocol, where a write cycle always writes through to memory, so that the memory always has the latest copy of the data element. Another protocol is a write-back protocol. The write-back protocol is a deferred writing process where each data element in the cache is assigned an invalid, exclusive, or modified state. The modified state indicates that the data element within the cache is "dirty," or different from (more up to date than) the copy stored in the memory. The exclusive state indicates that the data element within the cache is "clean," or the same as the copy stored in the memory. The invalid state indicates that the data element in the cache has been deallocated. Another embodiment of a deferred writing protocol is sometimes referred to as the "MESI" protocol, where four states are assigned to the data elements within the cache: modified, exclusive, shared, or invalid. Similar to the write-back protocol, the modified state indicates the data element is dirty and the exclusive state indicates the data element is clean. The shared state indicates that the data element is clean, and it is found in more than one cache. These cache coherency protocols and variations thereof are discussed in U.S. patent number 4,755,930. For one type of bus cache coherency protocol specific to advanced processor systems manufactured by Intel Corporation, three signals are employed. The first signal is asserted by the cache complex when a cache hit to a dirty line occurs. This signal is illustrated as SBO# (Snoop Back Off) in Figure 1. The second signal is asserted by the cache complex when the cache complex completes snooping. This signal is shown as SDONE (Snoop Done). The third signal is asserted by the memory when the memory witnesses a cache hit to a dirty line. The memory monitors both the SBO# and SDONE signals and when both are asserted concurrently, the memory asserts the third signal, STOP#. The bus master 160 detects the STOP# signal and halts the , memory transaction so that the dirty line from the cache 120 can be updated in the memory 150. One example of a bus protocol employing the above three signals is the Peripheral Component Interconnect (PCI) bus. PCI memory transaction protocol and cache coherency signals are disclosed in the PCI Local Bus Specification, Rev. 2.0, published by the PCI Special Interest Group (SIG), Hillsboro, Oregon. Because SBO#, SDONE, and STOP# are defined for single cache systems, this three-signal protocol is not typically used to communicate between caching processors and system memories in a multi-processing system. SUMMARY OF THE INVENTION A computer system employing a protocol for maintaining cache coherency amongst multiple cache complexes coupled across a local bus is described. For one embodiment, the computer system includes a data element stored in a cacheable memory, and a bus master that initiates a transaction request to operate on the data element. A local bus is coupled between the bus master and the cacheable memory for communicating transaction requests from the bus master to the cacheable memory. A plurality of cache complexes are also coupled to the local bus. Each cache complex comprises a cache for storing a subset of data elements from the cacheable memory, cache controlling logic, and a processor. When the bus master initiates a transaction request, the cache complexes snoop the request and search for the requested data element within their caches. If a first cache complex finds the data element and it is marked dirty, the first cache complex asserts a dirty signal on to the local bus. If the first cache complex finds the data element and it is marked clean, the first cache complex asserts a clean signal on to the local bus. During the snooping of the first cache complex, a first busy signal is asserted. Similarly, a second cache complex asserts second dirty, clean, and busy signals. A detection circuit monitors the assertion of the first and second busy signals, detects the simultaneous de-assertion of all of the busy signals, and delivers a done signal to the cacheable memory. The cacheable memory detects when there is a simultaneous assertion of the ' first or second dirty signal and the done signal and subsequently halts the transaction request from the bus master. Other features, and advantages of the present invention will be apparent from the accompanying drawings and the detailed description that follows. BRIEF DESCRIPTION OF THE DRAWINGS The present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements and in which: Figure 1 is a block diagram of a prior art computer system. Figure 2 is a block diagram of a computer system employing a multi-processing cache coherency protocol in accordance with one embodiment of the present invention. Figure 3 is a circuit diagram of a snoop busy detection circuit. Figure 4 is a timing diagram of a memory read with a hit to a modified cache line. Figure 5 is a timing diagram of a memory read with a hit to a shared or exclusive cache line. DETAILED DESCRIPTION A multi-processor local bus cache coherency protocol and implementation for a computer system is described. The cache coherency protocol provides a method by which multiple caching devices coupled to a local bus may maintain coherency during system memory reads and writes. The cache coherency protocol described below is incorporated in a multi-processor computer system. The computer system includes a local bus coupled to a plurality of caching processors and a system memory device. For one embodiment of the computer system, the local bus is a PCI bus. Any number of caching processors and system memory devices can be coupled to the local bus. For one embodiment, a caching processor contains an internal cache. For an alternative embodiment, a caching processor is coupled to an external cache. The computer system and method of employing the cache coherency protocol will be described in more detail herein below. Figure 2 illustrates a block diagram of one embodiment of a computer system. The system shown in Figure 2 includes cache complexes 210 and 220 coupled to a PCI bus 200. For one embodiment, the cache complexes 210 and 220 each include a processor coupled to a cache and a PCI bridge, as shown in the cache complex 140 in Figure 1. Alternative embodiments of the cache complex include dual processors coupled locally to each other with only one interface to the PCI bus 200, a single processor with an internal cache, and simply a cache with a cache controller and PCI interface logic. For one embodiment of the computer system, the cache within each cache complex 210 and 220 maintains coherency by using the MESI protocol. Alternative embodiments include write-through caches, write-back caches, and write-def erred caches employing various coherency protocols. The bus master 270 illustrated in Figure 2 represents any bus agent coupled to the PCI bus 200, capable of initiating a read from or write to memory 250. One embodiment of bus master 270 is a cache complex similar to cache complexes 210 and 220. Alternative embodiments may include processors, graphics controllers, local area network (LAN) controllers, or other peripheral devices capable of processing data stored in memory. A memory transaction is initiated by the bus master 270 when the bus master 270 desires to operate on a data element stored in the memory 250. The bus master 270 initiates the transaction by asserting an address associated with the data element on to the PCI bus 200. Each of the cache complexes 210 and 220 snoop the transaction by searching for the data element within its cache. From the time the cache complex 210 receives the address to be snooped until it completes its snoop and determines whether or not to indicate a "hit", it asserts an active signal on the SBSY(1 )# line 272. Outside this time frame, SBSY(1 )# is driven inactive. Similarly, the cache complex 220 asserts an active signal on SBSY(2)# line 274. If either of the cache complexes 210 or 220 contain a copy of the data element, there has been a cache "hit." When a cache hit results, and the data element within the cache is in the modified state, the cache complex asserts an active signal on line 266 (labeled SBO#). The cache complex must assert the SBO# signal until it detects that the snoop cycle is completed (SDONE is active). For one embodiment of the invention, SBO# 266 is a sustained tristate line. A sustained tristate line must only be driven by one device at a time. The line is first driven to its active state, and then driven to its inactive state for at least one clock cycle. A pull-up enables the line to sustain the inactive value until the line is driven again. Either one of the cache complexes 210 or 220 may assert a signal on to the SBO# 266 line, overriding the sustained value of the line. A cache complex that is not indicating a hit to a modified line will not drive the SBO# 266 line to either the active or inactive state. For another embodiment the SBO# line 266 is a conventional tristate line. Alternative embodiments include other forms of shared signal lines that are designed to be driven by multiple devices. The modified state is defined such that only one cache contains the latest copy of the data element. Therefore, only one cache complex, 210 or 220, asserts a signal on SBO# line 266 during a given transaction. In another embodiment of the invention, one or more of the cache complexes 210 and 220 employ a write-through cache coherency protocol. Because a write-through cache always contains the latest version of a data element in memory 250, a write-through cache does not drive the SBO# line 266. Memory 250 is coupled to the PCI bus 200. An embodiment of memory 250 consists of dynamic random access memory (DRAM), and a memory controller for interfacing with the PCI bus. For an alternative embodiment, the memory controller is incorporated with the memory array on the same silicon die. Alternative embodiments of the memory 250 include any known memory design used to store data elements. The memory 250 senses the assertion of the active signal on SBO# line 266 and on SDONE line 262. Because the SBO# signal 266 is active low, a logical zero (0) indicates that a cache hit to a modified line has occurred. SDONE signal 262 is a logical high signal, so a logical one (1 ) indicates that the cache complexes 210 and 220 have completed snooping. The following is a table indicating the possible states detected by the memory 250: Table 1 SDONE SBO# State 0 X standby 1 0 dirty 1 1 clean The standby mode indicates that the cache complexes 210 and 220 are currently snooping and have not yet finished. When the memory 250 detects the standby mode, it waits for the snoop results. The clean state indicates that there is no cache hit to a modified entry and the memory read or write transaction can proceed. The clean state can arise in two different ways. One is when there is not a cache hit in either cache complex 210 or 220. The other is when there is a cache hit in either or both of cache complexes 210 and 220, but the hit data element was not in the modified state. Instead the data element was in one of the clean states; exclusive or shared. The dirty state indicates that there was a cache hit in one of the cache complexes 210 and 220, and the hit data element is modified, or more recent than the one in memory 250. When the memory 250 detects the dirty state via the SBO# 266 and SDONE 262 signals, it will assert the STOP# signal on line 264. The STOP# signal is detected by the bus master 270, and the memory transaction is halted in order to allow the dirty data element to be written back to the memory 250. For an embodiment, one or more of cache complexes 210 and 220 use a write-through protocol. Because a write-through cache always has the latest version of the data element kept in memory, there is no reason to halt a memory transaction by asserting STOP# on line 264. For the embodiment in which the cache complexes 210 and 220 employ a write-back or MESI cache coherency protocol, the cache complexes 210 and 220 may drive the SH# signal on line 268 during memory read operations. If a snoop to one of the cache complexes 210 or 220 results in a hit to a data element in the shared or exclusive state, then the cache complex will assert an active signal on the SH# line 268. For one embodiment, SH# is an active low signal, so a logical zero (0) indicates a cache hit to a shared or exclusive line. There is a possibility that more than one of cache complexes 210 and 220 may have the data element in the shared state, so the SH# line 268 may be driven by more than one source. For one embodiment, the SH# line 268 is a sustained tristate signal, as explained above in reference to the SBO# signal line 266 above. For alternative embodiments, the SH# signal line 268 is implemented using one of the other well-known designs that allow multiple devices to drive a shared signal. An embodiment of the bus master 270 contains a cache employing a write-back or MESI protocol, and is structured similar to the cache complexes 210 and 220. For this embodiment, the bus master 270 monitors the state of the SH# line 268 during memory read transactions. When the bus master 270 detects an active assertion on the SH# line 268 and SDONE line 262, the bus master 270 knows that the data element being read from memory 250 is also located within at least one cache complex, 210 or 220. The bus master 270 therefore puts the data element into the shared state within its cache when received from the memory 250, or causes the cache complex that has the line to transition to the invalid state. Because the bus master 270 only monitors the SH# line 268 during memory read operations, the ability to drive a signal on the SH# line 268 during memory write operations is optional. Therefore, for an alternative embodiment, a cache complex does assert a signal on SH# 268 during memory write operations. For one embodiment, the caches contained within the caching complexes 210 and 220 employ a write-through cache coherency protocol. If the write-through cache contains a data element in the shared or exclusive state, it will drive the SH# signal 268 in a similar manner to the write-back cache complex. As mentioned above, the cache complexes 210 and 220 assert signals SBSY(1 )# on line 272, and SBSY(2)# on line 274. These signals are fed into the detection circuitry 260, which detects when both of the signals on lines 272 and 274 have been de-asserted. Figure 3 includes a circuit schematic of the detection circuitry 260. The SBSY(1 )# line 272 and SBSY(2)# line 274 are fed into an AND gate 300. Because SBSY(1 )# and SBSY(2)# are both active low, a value of logical zero (0) indicates the cache complex 210 or 220 is still busy. When both lines 272 and 274 are logical one (1 ), indicating that the snooping has been completed by both of the cache complexes 210 and 220, then the AND gate 300 asserts a signal on line 322. This signal in turn is fed into the latch 310, which is clocked by the PCI clock 324. The latch 310 is employed for synchronization, since the PCI bus protocol is synchronized with the rising edge of every PCI clock. When the signal 322 is latched, it is asserted on the SDONE line 262. The signal on SDONE line 262 is then sent to the cache complexes 210 and 220, the memory 250, and the bus master 270, to indicate that the snooping has completed. Figure 4 is a timing diagram representing one example of a memory read with a cache hit to a modified line. Each of the signals in Figure 4 is active on the rising edge of the PCI clock 400. Therefore, each clock period will separately be examined to illustrate the timing and synchronization of the relevant signals. The timing diagram of Figure 4 will be explained with reference to the computer system of Figure 2. During the first PCI clock cycle 401 , the FRAME# signal 410 is pulled low to its active state for one clock cycle by the bus master 270. This initiates the read transaction with the memory 250. At the same time, the address 421 on AD 420 is asserted by the bus master 270. In the next clock, 402, the address 421 is received by the cache complexes 210 and 220, and the memory 250. During clock 403, the cache complexes snoop the read transaction request by searching for the address 421 in their caches. For the embodiment shown in Figure 4, the cache complexes employ a write-back or MESI coherency protocol. The cache complex 210 asserts SBSY(1 )# 440 by pulling it low during clock 403. At the same time, cache complex 220 asserts SBSY(2)# 450. The signal IRDY# 430 is also pulled low during clock 403, indicating that the bus master is now prepared to accept the requested data from the memory 250. For the embodiment illustrated in Figure 4, cache complex 210 completes snooping in one clock. Hence, SBSY(1 )# 440 is pulled high in clock 404. In contrast, cache complex 220 takes two clocks to snoop, so SBSY(2)# 450 is pulled high in clock 405. The detection circuitry 260 detects when SBSY(1 )# 440 and SBSY(2)# 450 have both been pulled high, and asserts SDONE 470 in clock 406. For the particular embodiment displayed in Figure 4, cache complex 220 contains the data element associated with address 421 , and it is in the modified state. Hence, in clock 406, cache complex 220 asserts a low signal on SBO# 480 in the clock cycle after SBSY(2)# is de-asserted. The signal SBO# 480 can be pulled low by either of the cache complexes 210 or 220, but recall that only one cache complex, 210 or 220, may have the data in the "modified" or dirty state and hence only one cache complex may drive the SBO# signal 480 at a time. Also in clock 406, the memory 250 detects the assertion of the SBO# signal 480 and the SDONE signal 470 at the same time. Because the SBO# signal 480 indicates that memory 250 does not contain the latest copy of the data element, the read transaction between the bus master 270 and the memory 250 is not completed as scheduled. The bus master 270 instead acquires the latest version of the data element. The memory 250 therefore asserts the STOP# signal 490 in clock 407 in order to halt the memory read request from the bus master 270. For one embodiment, when the read transaction has been halted, the modified data element from cache complex 220 is written to memory 250 and subsequently the bus master 270 re-initiates the read request from the memory 250. Alternative embodiments use other methods of passing the latest copy of the data element from the cache complex 220 to the bus master 270 and updating the memory 250. Figure 5 illustrates a timing diagram of a memory read transaction request with a hit to an exclusive or shared line. The diagram of Figure 5 will be explained with reference to the computer system of Figure 2. The bus master 270 requests a memory read by using the same steps as in Figure 4. Therefore, the timing diagram of Figure 5 for clocks 501 -505 is identical to the timing diagram of Figure 4 for clocks 401 -405. For the embodiment shown in Figure 5, cache complex 220 contains the data element associated with address 521 in the exclusive state. The exclusive state indicates that the data element in cache complex 220 is the same as the copy kept in the memory 250. The timing diagram of Figure 5 looks the same for the case where the data element within cache complex 220 is in the shared state. In clock 506, the SDONE signal 570 is asserted to signify that the cache complexes 210 and 220 have finished snooping. At the same time, SH# 560 is asserted, or pulled low, by cache complex 220. The bus master 270 detects the simultaneous assertion of SH# 560 and SDONE 570 in clock 507. For an embodiment of the invention, the bus master 270 contains a cache employing a write-back or MESI coherency protocol. For this embodiment, the simultaneous assertion of SH# 560 and SDONE 570 alerts the bus master 270 that it should place the data element read from memory 250 in the shared state within the bus master's cache. In the transaction shown in Figure 5, the read request does not need to be halted as in the transaction shown in Figure 4. Therefore, the SBO# signal 580 and STOP# signal 590 are not asserted. For an alternative embodiment of the invention, bus master 270 does not have a cache. Therefore, the SH# signal 560 is not monitored by the bus master 270. For yet another embodiment, the bus master 270 contains a cache employing a coherency protocol that does not include a shared state. Once again, the bus master 270 is not required to monitor the SH# signal 560. Thus, in the foregoing detailed description a computer system and method of maintaining cache coherency in a multi-processor system across a local peripheral bus have been described. The computer system described may employ a PCI bus, or other types of local busses for communication between cache complexes. The computer system may contain an unlimited plurality of caching complexes, employing various cache coherency protocols. Moreover, the computer system described may employ a plurality of system memory devices coupled to the local bus. The method described allows the cache complexes to maintain cache coherency between the plurality of cache complexes and system memory devices coupled to the local bus. In the foregoing specification, the invention has been described with reference to specific exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Claims: CLAIMS What is claimed is: 1. A computer system, comprising: a local bus; memory means, coupled to the local bus, for storing a first plurality of data elements; processing means, coupled to the local bus, for requesting access to a first data element stored in the memory means; first caching means, coupled to the local bus, for storing a first subset of data elements from the memory means, including a first snooping means for monitoring the request from the processing means and searching for the first data element within the first caching means; second caching means, coupled to the local bus, for storing a second subset of data elements from the memory means, including a second snooping means for monitoring the request from the processing means and searching for the first data element within the second caching means; and sensing means for determining when the first and second snooping means have completed searching for the first data element and subsequently communicating the completion to the memory means. 2. A computer system, comprising: a first memory, a bus, coupled to the first memory, for communicating transaction requests to and from the first memory; a bus master, coupled to the bus, for requesting transactions with the first memory; first caching circuitry, coupled to the bus, that snoops the transaction request and simultaneously asserts a first busy signal; second caching circuitry, coupled to the bus, that snoops the transaction request and simultaneously asserts a second busy signal; detection circuitry for detecting when the first and second busy signals are de-asserted and subsequently sending a done signal to the first memory. 3. The computer system of claim 2, wherein the bus comprises a Peripheral Component Interconnect (PCI) bus. 4. The computer system of claim 2, wherein the first caching circuitry further comprises a first processor coupled to a first cache, and the second caching circuitry further comprises a second processor coupled to a second cache. 5. The computer system of claim 2 wherein when the snooping of the first caching circuitry results in a cache hit to a dirty line, the first caching circuitry asserts a dirty signal. 6. The computer system of claim 5 wherein the first memory monitors the dirty signal and the done signal, and when both the dirty signal and the done signal are asserted, the first memory cancels the transaction request. 7. The computer system of claim 2 wherein when the snooping of the first caching circuitry results in a cache hit to a clean line, the first caching circuitry asserts a clean signal. 8. The computer system of claim 7 wherein the bus master further comprises third caching circuitry. 9. The computer system of claim 8 wherein the transaction request is a request to read a data element from the first memory. 10. The computer system of claim 8 wherein when the clean signal is asserted the bus master stores the data element within the third caching circuitry and marks the data element as clean. 1 1. A computer system, comprising: a first memory; a bus master for issuing a transaction request to the first memory; a data bus, coupled to the first memory and the bus master, for communicating the transaction request from the bus master to the first memory; a first caching complex, coupled to the data bus, having a first processor and a first cache coupled to the first processor, wherein when the transaction request is initiated, the first caching complex snoops the transaction request, asserts a first busy signal until the snooping is completed, and asserts a first clean signal if the snoop results in a cache hit to a first clean line, or asserts a first dirty signal if the snoop results in a cache hit to a first dirty line; a second caching complex, coupled to the data bus, having a second processor, and a second cache coupled to the second processor, wherein when the transaction request is initiated, the second caching complex snoops the transaction request, asserts a second busy signal until the snooping is completed, and asserts a second clean signal if the snoop results in a cache hit to a second clean line, or asserts a second dirty signal if the snoop results in a cache hit to a second dirty line; and a first circuit for sensing the de-assertion of both the first and second busy signals, and sending a done signal to the first memory. 12. The computer system of claim 11 , wherein the data bus is a peripheral component interconnect (PCI) bus. 13. The computer system of claim 11 , wherein the first memory detects the simultaneous assertion of the done signal and one of the first and second dirty signals and cancels the transaction request. 14. In a computer system having a first memory, a first and second caching complex, each caching complex having a processor and a cache locally coupled to the processor, and a bus coupling the first and second caching complexes to the first memory, a means for ensuring cache coherency between the first and second caching complex, comprising: initiating means, coupled to the bus, for issuing a request to operate on a first data element from the first memory; first snooping means for searching the first cache for the first data element and asserting a first dirty signal on a first line if the first data element is found dirty, and asserting a first clean signal on a second line if the first data element is found clean; second snooping means for searching the second cache for the first data element and asserting a second dirty signal on the first line if the first data element is found dirty and asserting a second clean signal on the second line if the first data element is found clean; sensing means for determining when the searching by the first and second snooping means has completed and subsequently delivering a finish signal to the first memory; and halting means, coupled to the first memory, for halting the request to operate on the data element when the finish signal and one of the first and second dirty signals are simultaneously asserted. 15. In a computer system having a first memory, an initiating agent, a first and second cache complex, and a bus connecting the initiating agent to the first and second cache complexes and the first memory, a method of snooping a transaction on the bus comprising the steps of: (a) initiating the transaction by asserting a first address, corresponding to a data element to be operated on, on to the bus; (b) delivering the first address to the first memory and the first and second cache complexes; (c) searching the first cache complex for the data element; (d) asserting a first busy signal during the searching of the first cache complex; (e) searching a second cache complex for the data element; (f) asserting a second busy signal during the searching of the second cache complex; and (g) sensing the simultaneous de-assertion of the first and second busy signals and subsequently delivering a finish signal to the first memory. 16. The method of claim 15, further comprising the steps of: (h) asserting a first dirty signal if the data element is found in the first cache complex and is in a dirty state; (i) asserting a first clean signal if the data element is found in the first cache complex and is in a clean state; (j) asserting a second dirty signal if the data element is found in the second cache complex and is in the dirty state; (k) asserting a second clean signal if the data element is found in the second cache complex and is in the clean state; and (I) halting the transaction when the finish signal is simultaneously asserted with one of the first and second dirty signals. 17. The method of claim 16, wherein the transaction is a request to read the data element from the first memory. 18. The method of claim 17, wherein the initiating agent further comprises a third cache complex. 19. The method of claim 18, further comprising the step of: (m) storing the data element in the third cache complex and marking the data element as clean when one of the first and second clean signals is asserted.

Inventors: BHAT KETAN S, MATHEWS GREGORY S, BHAT, KETAN, S., MATHEWS, GREGORY, S.
Applicants: INTEL CORP, INTEL CORPORATION
Application year: 1996
Main classification: G06F13
IPC codes: G06F12