Data reproduction method and apparatus

Abstract: A system for reproducing data recorded in an optical disk as a signal obtained by modulating the data in accordance with a predetermined partial response characteristic, includes an optical head for reproducing the signal from the optical disk, a VCO for generating a clock, an A/D converter for obtaining a sampling value from the reproduction signal in synchronism with the clock, a maximum likelihood decoder for detecting a maximum likelihood decode data on the basis of the sampling value in synchronism with the clock, a demodulator for demodulating the decode data from the maximum likelihood decoder, wherein the maximum likelihood decoder includes a phase error detecting unit for detecting a phase error between the clock and a point of time when the reproduction signal is sampled, and a phase error correcting unit for correcting the detected phase error.

Description: The present invention relates to a method and apparatus for reproducing data stored in an optical disk. Recent accelerating development of multi-media is spotlighting the utility of optical disks as external storage devices, and in line with an increase in the amount of record data, each disk is required to have a large storage capacity. The storage of data in an optical disk is closely related to the storage density therein, and in order to increase the storage density, an edge-position recording system, wherein record data correspond to both ends of record pit, is in common use. As a method for reproducing record data recorded under the edge-position recording system, a partial response maximum likelihood (PRML) data reproduction method is used. This PRML method uses a maximum likelihood method (Viterbi decoding) so as to demodulate the information modulated in accordance with a partial response characteristic and recorded in an optical disk . First, a signal is obtained after it is subjected to run-length limitation and demodulated in accordance with a partial response characteristic, and is recorded in an optical disk. A reproduction signal is obtained from the optical disk, and sampled by an analog/digital converter (A/D converter). The transition of a maximum likelihood signal is fixed from the sampling values in accordance with a predetermined algorithm. A reproduction data is determined on the basis of the fixed transition of the signal, and from the determined reproduction data the original record data is demodulated. The inventors have already completed a maximum likelihood decoding system, which is filed in Japanese Patent Application No. 6-225433. Now, referring to FIG. 1, the system will be described. The reference numeral 1 designates an optical disk which stores record data modulated in accordance with a partial response class 1 (PR (1, 1) in which, for example, 1/7 run-length limitation is made. Under the optical disk 1 is provided an optical head 2 from which a reproduction signal is obtained corresponding to the record data in the optical disk 1. The optical head 2 outputs the reproduction signal to an amplifier 3 which amplifies the input reproduction signal and outputs it to an equalizer 4. The equalizer 4 shapes the waveform of the amplified reproduction signal and delivers it to a low-pass filter (LPF) 5 which cuts off a high-frequency portion of the reproduction signal beyond a predetermined frequency and outputs a low-frequency portion to an A/D converter 6. The A/D converter 6 samples the shaped reproduction signal, and outputs the sampling value to a maximum likelihood decoder 7. The maximum likelihood decoder 7 generates a maximum likelihood decode data d k and a phase error data dT k (described below), and outputs the maximum likelihood decode data d k to a demodulator 8, and the phase error data dT k to a D/A converter 11. The demodulator 8 demodulate the maximum likelihood decode data d k so as to relieve the 1/7 run-length limitation and generates a final reproduction signal. The D/A converter 11 converts the phase error data dT k into a phase error signal (rectangular waveform signal), and delivers it to a low-pass filter (LPF) 12. The LPF 12 converts the phase error signal to a voltage level, and outputs it to a voltage control oscillator (VCO) 13. The VCO 13 generates a reference clock signal which is a clock signal identical to a synchronous signal used for data recording, and after controlling the phase of the reference clock signal in accordance with the input voltage level, outputs the controlled clock signal to the A/D converter 6 and the maximum likelihood decoder 7. The A/D converter 6 and the maximum likelihood decoder 7 are operated in synchronism with the clock signal from the VCO 13. FIG. 2 shows the internal structure of the maximum likelihood decoder 7 which includes a merge determining unit 21, a central value calculating unit 22, a reference value calculating unit 23, a merge detecting unit 24 and a phase error detecting unit 25. Prior to describing each parts, the merge is defined as follows: The maximum likelihood decoder 7 decode a sampling value determined by the A/D converter 6 into a record data. When the decoder 7 detects a maximum likelihood data from an input signal, it fixes the transition path of a maximum likelihood data around the detected data, and fix the data on the path as a record data. The record data corresponds to the characteristic of the partial response class 1. Therefore, between the record data "+1" and "0" , the data transition path from "1" to "1", from "0" to "0", from "1" to "0", and "0" to "1" can be respectively obtained. A data transition containing the data transition path from "1" to "1" is defined as +merge. A data transition containing the data transition path from "0" to "0" is defined as -merge. A data transition containing the data transition path from "0" to "1" or from "1" to "0" is defined as no merge. FIGS. 3 to 7 are respectively flowcharts showing the sequence of operating the merge determining unit 21, the central value calculating unit 22, the reference value calculating unit 23, the merge detecting unit 24 and the phase error detecting unit 25. The merge determining unit 21 judges the merge of the sampling data y k by using a sampling data y k from the A/D converter 6 and a reference value Δ k from the reference value calculating unit 23, and outputs the determination value M k . The merge determining unit 21 processes in accordance with the flowchart of FIG. 3. When a new sampling data (input data) y k is inputted to the merge determining unit 21 from the A/D converter 6 (Step S1), Z k is calculated as Z k = y k - Δ k (Step S2). +merge, -merge and no merge are respectively judged depending upon the value of Z k (Step S3). When it is -merge (Z k <-1), the determination value M k = (m k1 , m k2 ) = 10 is set (Step S4). When it is no merge (-1≦Z k ≦1), the determination value M k = 00 is set (Step S5). When it is +merge (Z k >1), the determination value M k = 01 is set (Step S6). Then, the set determination value M k is outputted to the reference value calculating unit 23 and the merge detecting unit 24 (Step S7). The central value calculating unit 22 calculates a central value C kave , which is the central level of the reproduction signal, by using a sampling data y k from the A/D converter 6 and Z k from the merge determining unit 21. The central value calculating unit 22 is operated in accordance with the flowchart of FIG. 4. When a new sampling data (input data y k ) is inputted from the A/D converter 6 (Step S11), the value of Z k is judged (Step S12), and the central value data C kd is calculated depending upon the value of Z k . In the case of Z k <-2, the central value data C kd is calculated in accordance with C kd = y k + 2 (Step S13). In the case of -2 ≦ Z k ≦2, the central value data C kd is calculated in accordance with C kd = C k-lave (Step S14). In the case of Z k > 2, the central value data C kd is calculated in accordance with C kd = y k - 2 (Step S15). In the case of Z k > 2, since the input data y k is certainly in the state of +merge, the central value C kd is determined by deducting an ideal amplitude value "2" from the input data y k . In the case of Z k <-2, since the input data y k is certainly in the state of - merge, the central value C kd is determined by deducting an ideal negative amplitude value "-2" from the input data y k . The case of -2 ≦ Z k ≦ 2 is a case where since it is impossible to judge it either as +merge or -merge (including no merge), the previous calculated central value C k-lave is used as the central value data C kd . In this way, the current central value C kave is calculated in accordance with C kave = [(n-1)C k-lave + C kd ] /n (Step S16). The central value C kave obtained in this way corresponds to an average value of n lumber of central value data C kd . A curve depicted with the central values C kave represents the central level of the reproduction signal. The reference value calculating unit 23 calculates a reference value Δ k-1 by using a sampling data y k from the A/D converter 6, a determination value M k from the merge determining unit 21, and a central value C kave from the central value calculating unit 22. The reference value calculating unit 23 processes in accordance with the flowchart of FIG. 5. When a new sampling data (input data) y k is inputted (Step S21), the reference value calculating unit 23 judges the determination value M k (Step S22), and calculates a reference value Δ k-1 in accordance with the determination value M k . In the case of M k = 10 (Z k < -1: - merge), the reference value Δ k-1 = 2C kave - y k -1 is calculated (Step S23), and in the case of M k = 00 (-1 ≦ Z k ≦ 1: no merge), the reference value Δ k-1 = 2C kave - Δ k is calculated (Step S24). In the case of M k = 01 (Z k > 1: +merge), the reference value Δ k-1 = 2C kave - y k +1 is calculated (Step S25). The calculated reference value Δ k+1 is outputted to the merge determining unit 21 (Step S26). The merge detecting unit 24 detects a change in the sampling data y k from -merge to +merge, and from +merge to - merge on the basis of the determination value M k from the merge determining unit 21. The merge detecting unit 24 processes in accordance with the flowchart of FIG. 6. When a new determination value M k is inputted from the merge determining unit 21 (Step S31), the merge detecting unit 24 defines a variable A k = (a k1 , a k2 ) ≠ (0,0), (1, 1), and judges the value of M k (Step S32). In the case of M k = A k (+merge or -merge with no change) or M k = 00 (no merge), A k-1 = A k is maintained without changing the previous variable A k (Step S33). In the case of M k ≠ A k (a change from +merge to -merge or a change from -merge to +merge), A k-1 = M k is maintained by setting the variable A k+1 to the previous determination value M k (Step S34). Then, a maximum likelihood decode data d k is calculated by the following equation (1), and outputs the result to the demodulator 8 (Step S35): d k = def k + der k = (a k1 • a k2 • m k1 • m k2 ) + ( a k1 • a k2 • m k1 m k2 ) When no merge, +merge or -merge is maintained without any change, d k = 0 is obtained from the equation (1). If a sampling data y k changes from +merge to -merge or from -merge to +merge, d k =1 is obtained from the equation (1). The phase error detecting unit 25 calculates a phase error data dT k on the basis of a sampling data y k from the A/D converter 6, a central value C kave from the central value calculating unit 22, and a maximum likelihood decode data d k from the merge detecting unit 24. The phase error detecting unit 25 processes in accordance with the flowchart of FIG. 7. When a new maximum likelihood decode data d k (a leading-edge maximum likelihood decode data def k ( "1" or "0" ) and a trailing-edge maximum likelihood decode data der k ( "1" or "0" )] is inputted from the merge detecting unit 24 by a clock timing k (Step S41), the phase error detecting unit 25 calculates the leading-edge phase error data dTf k by putting the central value C k-lave, the sampling data y k-1 and the leading-edge maximum likelihood decode data def k in dTf k = (C k-lave - y k-1 ) • def k , and also calculates the trailing-edge phase error data dTr k by putting the central value C k-lave , the sampling data y k-1 , and the trailing-edge maximum likelihood decode data der k in dTr k = (y k-1 - C k-lave) • der k (Step S42), the central value C k-lave and the sampling data y k-1 being obtained by the previous clock timing k-1. The leading-edge maximum likelihood decode data def k becomes "1" at the leading-edge point (the ascending point), and as a result, the leading-edge phase error data dTf k corresponds to a difference between the central value of the reproduction signal and the sampling data at the leading-edge point. Likewise, the trailing-edge phase error data dTr k corresponds to a difference between the central value of the reproduction signal and the sampling data at the trailing-edge point (the descending point). The phase error data dT k is obtained by adding the leading-edge phase error data dTf k to the trailing-edge phase error data dTr k (Step S43), and the resulting phase error data dT k is outputted to the D/A converter 11 (Step S44). The operation will be described. A reproduction signal having a partial response characteristic corresponding to a maximum likelihood decoding obtained by the optical head 2 from the optical disk 1 is delivered to the A/D converter 6 through the amplifier 3, the equalizer 4 and the LPF 5. The A/D converter 6 obtains a sampling value of the reproduction signal in synchronism with a clock signal from the VCO 13, and outputs it to the maximum likelihood decoder 7 where the merge determining unit 21, the central value calculating unit 22, the reference value calculating unit 23 and the merge detecting unit 24 process in accordance with the flowchart of FIGS. 3, 4, 5 and 6, respectively, and produces a maximum likelihood decode data d k . The maximum likelihood decode data d k is outputted to the demodulator 8. The maximum likelihood decoder 7 is operated in synchronism with a clock signal from the VCO 13. In the maximum likelihood decoder 7 the phase error detecting unit 25 processes in accordance with the flowchart of FIG. 7, and produces a phase error data dT k and outputs it to the D/A converter 11. The phase error data dT k is converted into a phase error signal by the D/A converter 11. The phase error signal is converted into a voltage level by the LPF 12. The VCO 13 adjusts the phase of the reference clock signal in accordance with the voltage level, and delivers the adjusted clock signal to the A/D converter 6 and the maximum likelihood decoder 7. FIGS. 8A and 8B are views each exemplifying the generation of the phase error control voltage. FIG. 8A shows a case where a phase error dτ between the "phase of an actual cluck signal" () and the "ideal sampling point of the reproduction signal" (○) is positive (+). In this case, the D/A converter 11 outputs a phase error signal representing a positive (+) amplitude which matches with the phase error dτ at every timing corresponding to the edge points, and the phase error signal is filtered by the LPF 12, and becomes an input signal to the VCO 13. FIG. 8B shows a case where a phase error d τ between the "phase of an actual clock signal" () and the "ideal sampling point of the reproduction signal" (○) is negative (-). In this case, the D/A converter 11 outputs a phase error signal representing a negative (-) amplitude which matches with the phase error dτ at every timing corresponding to the edge points, and the phase error signal is filtered by the LPF 12, and becomes an input signal to the VCO 13. In this way a phase error signal at the point of a maximum likelihood decode data is detected through the maximum likelihood decoding, and an error is corrected by using the phase error. Synchronizing with the clock signal, the A/D converter 6 executes the sampling, and the maximum likelihood decoder 7 detects the maximum likelihood decode data d k and the phase error data dT k . The maximum likelihood decode data d k is delivered to the demodulator 8 whereby it is relieved of the 1/7 run-length limitation, and the original record data is reproduced. The structure shown in FIG. 1 is a reproduction system in which a leading-edge (corresponding to the ascending edge of a reproduction signal) and a trailing-edge (corresponding to the descending edge of a reproduction signal) are detected in a mixing stage. In contrast, another reproduction system independently detects signals corresponding to the leading-edge and trailing-edge of a reproduction waveform, and generates a clock signal independently reproduced from each detection, and data is reproduced on the basis of each clock signal. This independent detection system is also proposed in Japanese Patent Application No. 6-225433. FIG. 9 is a view illustrating the structure of the independent data reproduction system, wherein like reference numerals designate like elements and components to those in FIG. 1. An A/D converter 6a, a maximum likelihood decoder 7a, a D/A converter 11a, an LPF 12a and a VCO 13a constitute a leading-edge maximum likelihood data detecting system. An A/D converter 6b, a maximum likelihood decoder 7b, a D/A converter 11b, an LPF 12b and a VCO 13b constitute a trailing-edge maximum likelihood data detecting system. The A/D converters 6a, 6b, the D/A converters 11a, 11b, the LPFs 12a, 12b and the VCOs 13a, 13b have substantially the same structure as that of the A/D converter 6, the D/A converter 11, the LPF 12 and the VCO 13 shown in FIG. 1, respectively. The maximum likelihood decoders 7a and 7b have the same structure as that of the maximum likelihood decoder 7 shown in FIG. 1 (Refer to FIG. 2). In the example shown in FIG. 9 the maximum likelihood decoder 7a for the leading-edge and the maximum likelihood decoder 7b for the trailing-edge are independently provided. As a result, the leading-edge maximum likelihood decoder 7a outputs a leading-edge maximum likelihood decode data def k from the merge detecting unit 24, and a leading-edge phase error data dTf k from the phase error detecting unit 25. The trailing-edge maximum likelihood decoder 7b outputs a trailing-edge maximum likelihood decode data der k from the merge detecting unit 24, and a trailing-edge phase error data dTr k from the phase error detecting unit 25. FIGS. 10A and 10B are flowcharts illustrating the sequence of operating the phase error detecting units 25 for the leading-edge and the trailing-edge, respectively. As shown in FIG. 10A, when a new leading-edge maximum likelihood decode data def k is inputted (Step S51), the leading-edge phase error detecting unit 25 calculates a leading-edge phase error data dTf k by using the equation dTf k = (C k-lave - y k-1 )· def k (Step S52), and outputs the calculated value dTf k to the D/A converter 11a (Step S53). As shown in FIG. 10B, when a new trailing-edge maximum likelihood decode data der k is inputted (Step S61), the trailing-edge phase error detecting unit 25 calculates a trailing-edge phase error data dTr k by using the equation dTr k = (y k-1 - C k- l ave ) · der k (Step S62), and outputs the calculated value dTr k to the D/A converter 11b (Step S63). The leading-edge maximum likelihood decode data def k and the trailing-edge maximum likelihood decode data der k from the maximum likelihood decoders Ta and 7b are inputted to a synthesizer 9, which is constituted with, for example, an FIFO (First-In First-Out) memory, wherein the leading-edge maximum likelihood decode data def k synchronizes with a leading-edge clock signal from the VCO 13a, and the trailing-edge maximum likelihood decode data der k synchronizes with a clock signal from the VCO 13b. The leading-edge maximum likelihood decode data def k and the trailing-edge maximum likelihood decode data der k are alternately read out from the synthesizer 9 while they synchronize with either the leading-edge clock signal or the trailing-edge clock signal, and become a synthesized maximum likelihood decode data d k . The maximum likelihood decode data d k is demodulated into the original record signal by the demodulator 8 similarly to the example shown in FIG. 1. The reproduction system proposed in Japanese Patent Application No. 6-225433 determines the transition of the data to be reproduced on the basis of the relative level association between the sampling value y k and the reference value Δ k calculated by using the central value representing a change in the reproduction signal. As a result, the data is accurately reproduced irrespective of any change in the reproduction signal. The phase error detecting unit 25 of the maximum likelihood decoder 7 (7a, 7b), the D/A converter 11 (11a, 11b), the LPF 12 (12a, 12b) and the VCO 13 (13a, 13b) constitute a PLL circuit, and generates a clock signal in exact synchronism with the reproduction signal. As to the production of a clock signal used for operating the A/D converter and the maximum likelihood decoder, there is a further method which produces a clock signal by slicing an analog reproduction signal in a binary circuit and passing the resulting synchronous signal through a PLL circuit. However, this method has a problem of a phase shift in the clock signal to be delivered to the A/D converter and the maximum likelihood decoder caused by a variation in the slicing level or a delay in the circuit elements, thereby preventing A/D conversion in an optimum phase. In the first-mentioned example where a phase error is detected from the sampling data, the maximum likelihood decode data, and the central value of the reproduction signal, and the PLL circuit using the phase error compensates a phase shift. In this way the phase of a clock signal is adjusted such that an error between the phase of the clock signal and a sampling point of the reproduction signal is negated. As a result, even if any error occurs between the clock signal and the sampling point of the reproduction signal, owing to a time lag in the circuits, the phase error is corrected, thereby securing an accurate reproduction of data. However, under this reproduction system if any error occurs owing to noise, edge shift or faulty medium at the maximum likelihood decoding time, the error unfavorably affects the synchronous clock signal. FIGS. 11A to 11C illustrate examples of the problems arising therefrom. FIG. 11A shows a normal cancellation of the phase error of the clock signal by the phase error signal. As shown in FIG. 11A, the phase error signal increases by the clock shift, and thereafter, it diminishes as the phase shift is compensated. FIG. 11B shows the occurrence of a detection error. If a detection error occurs, the detected maximum likelihood decode data shifts by one bit, the phase error signal is generated in opposite phase. If the phase error signal in opposite phase is large, the control voltage in the VCO is drifted, whereby the clock signal is shifted and the error propagation occurs. Document JP-A-06 195 892 & US-A-5 455 813 discloses a digital signal reproducing device in which the phase error of a synchronous clock is corrected on the basis of a mean value obtained from a plurality of sampling values. It does not disclose judging whether the phase error is useable for compensating the phase shift of the synchronous clock signal, which is a feature of the present invention. Document US-A-4 672 597 discloses a clock signal reproducing circuit in which a phase error signal is used to control a VCO by increasing the oscillation frequency when the polarity of the phase error signal is negative, maintaining the oscillation frequency when the phase error signal is zero, and decreasing the oscillation frequency when the polarity of the phase error signal is positive thereby synchronising a clock signal with an input signal. Although the polarity of the phase error signal is used to compensate for the phase shift of the clock signal in this document there is no mention of the phase error signal being judged as to whether it is useable for compensating for the phase shift of a synchronous clock signal, as in the present invention. It is desirable to provide a data reproduction method and apparatus for an optical disk which, even if any error occurs during the maximum likelihood decoding, can prevent the phenomenon that the error affects a synchronous clock signal to operate an A/D converter and a maximum likelihood decoder so as to propagate the maximum likelihood decode error. According to one aspect of the present invention there is provided a method for reproducing the data recorded in an optical disk as a signal obtained by modulating the data in accordance with a predetermined partial response characteristic, the method including the sequence of: reproducing a signal from the optical disk; generating a synchronous clock signal from the reproduction signal; obtaining a sampling value from the reproduction signal in synchronism with the synchronous clock signal; detecting maximum likelihood decode data on the basis of the sampling value in synchronism with the synchronous clock signal; detecting a phase error at a time between a point of time when the synchronous clock signal is generated and a point of time when the reproduction signal is sampled on the basis of the sampling value, the maximum likelihood decode data and a central value of the reproduction signal; judging whether the detected phase error is useable for compensating a phase shift of the synchronous clock signal based on the polarity of the phase error; and correcting the detected phase error so as to compensate for the phase shift of the synchronous clock signal. According to another aspect of the present invention there is provided an apparatus for performing the above method. In an embodiment of the present invention a phase error between the phase of a synchronous clock and a point of time when a reproduction signal is sampled is detected, and if no error occurs in the maximum likelihood decoding, the phase error is used as it is, and if an error occurs, a corrected phase error is used, so as to compensate a phase shift of a synchronous clock which controls the operation of obtaining a sampling value and maximum likelihood decode data. According to a phase error signal detecting system of the present invention, even if detected maximum likelihood decode data is erroneous, the phase shift of the synchronous clock is automatically corrected, thereby reducing the possibility of error propagation and decreasing an error rate. In this case, the occurrence of any error at the maximum likelihood decoding time is determined on the basis of the polarity and/or amplitude of the phase error, that is, the necessity of correcting a phase error is determined. It is also possible to detect a phase error by combining an ascending edge (leading-edge) and a descending edge (trailing-edge) or alternatively to detect the leading-edge phase error and the trailing-edge phase error independently. Reference will now be made by way of example, to the accompanying drawings in which: FIG. 1 is a block diagram illustrating a reproduction system (a leading-edge and trailing-edge combination type) in an optical disk according to a maximum likelihood decoding method; FIG. 2 is a block diagram illustrating the internal structure of a maximum likelihood decoder; FIG. 3 is a flowchart showing the sequence of operating a merge determining unit of the maximum likelihood decoder; FIG. 4 is a flowchart showing the sequence of operating a central value calculating unit of the maximum likelihood decoder; FIG. 5 is a flowchart showing the sequence of operating a reference value calculating unit of the maximum likelihood decoder; FIG. 6 is a flowchart showing the sequence of operating a merge detecting unit of the maximum likelihood decoder; FIG. 7 is a flowchart showing the prior art sequence of operating a phase error detecting unit of the maximum likelihood decoder; FIGS. 8A and 8B are views showing examples of generating a phase error control voltage; FIG. 9 is a block diagram illustrating a reproduction system (a leading-edge and trailing-edge independence type) in an optical disk according to a maximum likelihood decoding method; FIGS. 10A and 10B are flowcharts each showing the prior art sequence of leading-edge phase and trailing-edge phase detection by a phase error detecting unit; FIGS. 11A, 11B and 11C are views exemplifying the problems arising in previously-considered phase error control; FIG. 12 is a flowchart showing the sequence of operating a phase error detecting unit of a maximum likelihood decoder in a method embodying the present invention; FIG. 13 is a table showing the determination of the polarity of a phase error; FIG. 14 is a view showing an example of neighboring phase error data in a time sequence; FIG. 15 is a block diagram illustrating the internal structure of a phase error detecting unit of a maximum likelihood decoder; FIG. 16 is a view showing an input/output relationship in a comparator of the phase error detecting unit; FIGS. 17A to 17D inclusive are views showing the patterns selected by a selector of the phase error detecting unit; FIG. 18 is a table showing the logical values of the determined polarities of a phase error; FIG. 19 is a flowchart showing the sequence of operating a phase error detecting unit in a method embodying the present invention; and FIG. 20 is a flowchart showing the sequence of operating a phase error detecting unit in a method embodying another aspect of the present invention. Embodiments of the present invention will be described more particularly by way of example by reference to the accompanying drawings: The entire structure of data reproduction apparatus of a first embodiment (leading-edge and trailing-edge combination detection system) and the internal structure of the maximum likelihood decoder 7 used therein are basically the same as those shown in FIGS. 1 and 2, which are filed in Japanese Patent Laid-Open Publication No. 6-225433. The differences are in the sequence of operating a maximum likelihood decoder 7, especially the phase error detecting unit 25. The optical disk 1 stores a record data which is subjected to a 1/7 run-length limitation and is modulated in accordance with a partial response class 1 characteristic. Under the optical disk 1 is provided an optical head 2 for obtaining a reproduction signal corresponding to the record data. The optical head 2 outputs the reproduction signal to an amplifier 3 which amplifies it and outputs the amplified reproduction signal to an equalizer 4. The equalizer 4 shapes the waveform of the amplified reproduction signal and delivers it to an LPF 5 which cuts off a high-frequency portion of the reproduction signal beyond a predetermined frequency, and outputs a low-frequency portion of the reproduction signal to an A/D converter 6. The A/D converter 6 samples the shaped reproduction signal and outputs the sampling data y k to the maximum likelihood decoder 7. The maximum likelihood decoder 7 generates a maximum likelihood decode data d k and a phase error data dT k , and outputs the maximum likelihood decode data d k to a demodulator 8, and the phase error data dT k to a D/A converter 11. The demodulator 8 demodulates the maximum likelihood decode data d k so as to relieve the 1/7 run-length limitation. In this way a final reproduction signal is obtained. The D/A converter 11 converts the phase error data dT k into a phase error signal (rectangular waveform signal), and delivers it to an LPF 12 which, after converting it to a voltage level, outputs it to a VCO 13. The VCO 13 generates a reference clock signal which is a clock signal identical to a synchronous signal used for data recording, and controls the phase of the reference clock signal in accordance with the input voltage level. The controlled clock signal is outputted to the A/D converter 6 and the maximum likelihood decoder 7. The A/D converter 6 and the maximum likelihood decoder 7 are operated in synchronism with the clock signal. As described above by reference to FIG. 2, the maximum likelihood decoder 7 includes the merge determining unit 21, central value calculating unit 22, reference value calculating unit 23, merge detecting unit 24, and phase error detecting unit 25. The merge determining unit 21, the central value calculating unit 22, the reference value calculating unit 23, and the merge detecting unit 24 are basically operated in the same manner as in the prior art referred to above. The phase error detecting unit 25 is operated in a different manner. FIGS. 3, 4, 5, 6, and 12 are flowcharts showing the sequences of operating the merge determining unit 21, the central value calculating unit 22, the reference value calculating unit 23, the merge detecting unit 24 and the phase error detecting unit 25, respectively. In FIG. 3, the merge determining unit 21 judges the merge of the sampling data y k by using a sampling data y k from the A/D converter 6 and a reference value Δ k from the reference value calculating unit 23, and outputs the determination value M k . A new sampling data (input data) y k from the A/D converter 6 is inputted (Step S1). Z k is calculated as Z k = y k - Δ k by using the input data y k and the reference value Δ k (Step S2). +merge, -merge or no merge are respectively judged depending upon the value of Z k (Step S3). When it is -merge (Z k < -1), the determination value M k = (m k1 , m k2 ) is set to 10 (Step S4). When it is no merge (-1 ≦ Z k ≦ 1), the determination value M k is set to 00 (Step S5). When it is +merge (Z k > 1), the determination value M k is set to 01 (Step S6). And, the set determination value M k is outputted to the reference value calculating unit 23 and the merge detecting unit 24 (Step S7). In FIG. 4 the central value calculating unit 22 calculates a central value C kave , which is the central level of the reproduction value. When a new sampling data (input data y k ) is inputted (Step S11), the value of Z k is judged (Step S12), and the central value data C kd is calculated depending upon the value of Z k . In the case of Z k < -2, the central value data C kd is calculated in accordance with C kd = y k + 2 (Step S13), in the case of -2 ≦Z k ≦2, the central value data C kd is calculated in accordance with C kd = C k -lave (Step S14), and in the case of Z k >2, the central value data C kd is calculated in accordance with C kd = y k-2 (Step S15). The calculated central value data C kd and the previous calculated central value C k-lave are used to calculate the current central value C kave in accordance with C kave = [(n - 1)C k-lave + C kd ] /n (Step S16). In FIG. 5 the reference value calculating unit 23 calculates a reference value Δ k-1 by using the sampling data y k from the A/D converter 6, a determination value M k from the merge determining unit 21, and a central value C kave from the central value calculating unit 22. When a new sampling data (input data) y k is inputted from the A/D converter 6 (Step S21), the determination value M k is judged (Step S22), and the reference value Δ k-1 is calculated in accordance with the determination value M k . In the case of M k = 10(Z k < -1 : - merge), the reference value Δ k-1 = 2C kave - y k - 1 is calculated (Step S23). In the case of M k = 00(-1≦Z k ≦1 : no merge), the reference value Δ k-1 =2C kave - Δ k is calculated (Step S24). In the case of M k = 01(Z k > 1 : +merge), the reference value Δ k-1 = 2C kave - y k +1 is calculated (Step S25). The calculated reference value Δ k-1 is outputted to the merge determining unit 21 (Step S26). In FIG. 6, the merge detecting unit 24 detects a change in the sampling data y k from -merge to +merge and from +merge to -merge on the basis of the determination value M k from the merge determining unit 21. When a new determination value M k is inputted from the merge determining unit 21 (Step S31), a variable A k = (a k1 , a k2 ) ≠ (0, 0), (1, 1) is defined, and the value of M k is judged (Step S32). In the case of M k = A k (in the +merge or -merge with no change) or M k = 00 (no merge), A k+1 = A k is maintained without changing the previous variable A k (Step S33). In the case of M k ≠ A k (a change from +merge to -merge or a change from -merge to +merge), the variable A k-l is set to the previous determination value M k , and A k-1 = M k is maintained (Step S34). In this way a maximum likelihood decode data d k is calculated in accordance with the following equation, and is outputted to the demodulator 8 (Step S35). d k = def k + der k = (a k1 • a k2 • m k1 • m k2 ) + ( a k1 • a k2 • m k1 • m k2 ) The phase error detecting unit 25 is operated in accordance with the flowchart shown in FIG. 12, and 5 calculates a phase error data dT k on the basis of a sampling data y k from the A/D converter 6, a central value C kave from the central value calculating unit 22, and a maximum likelihood decode data d k from the merge detecting unit 24. When a new maximum likelihood decode data d k [leading-edge 0 maximum likelihood decode data der k ( "1" or "0" ) and trailing-edge maximum likelihood decode data d efk ( "1" or "0" )] is inputted from the merge detecting unit 24 by a clock timing k (Step S71), the leading-edge phase error data dTf k is calculated in accordance with dTf k = (C k-lave - y k-1 )· def k by using the central value C k-lave and the sampling data y k-1 obtained by the previous clock timing k-1 and the leading-edge maximum likelihood decode data def k , and the trailing-edge phase error data dTr k is calculated in accordance with dTr k = (y k-1 - C k-lave ) · der k by using the central value C k-lave and the sampling data y k-1 obtained by the previous clock timing k-1 and the trailing-edge maximum likelihood decode data der k (Step S72). Since the leading-edge maximum likelihood decode data def k becomes "1" at the leading-edge point (ascending point) of the reproduction signal, the leading-edge phase error data dTf k corresponds to the difference between the central value of the reproduction signal and the sampling data at the leading-edge point. Likewise, the trailing-edge phase error data dTr k corresponds to the difference between the central value of the reproduction signal and the sampling data at the trailing-edge point (descending point). The phase error data dT k is calculated from the sum of the leading-edge phase error data dTf k and the trailing-edge phase error data dTr k (Step S73). The polarity Po k of the obtained phase error data dT k is determined by using a SIGN function (Step S74). A polarity change in the phase error data is obtained by multiplying the polarity Po k by the one-clock previous polarity Po k-1 , and it is judged whether the product is not less than "0" (Step S75). FIG. 13 is a table showing the pattern of truth values of the polarity change. When the product is not less than "0" , the obtained phase error data dT k is outputted to the D/A converter 11 (Step S78). When the product is less than "0" , the absolute value of the obtained phase error data dT k and a predetermined threshold level dT 0 are compared (Step S76). When the absolute value of the phase error data dT k is equal to or below the threshold level dT 0 , the obtained phase error data dT k is outputted to the D/A converter 11 (Step S78). When it is larger than the threshold level dT 0 , the current polarity Po k is set to the previous polarity Po k-1 (Po k = Po k-1 ) (Step S77), and the sequence is returned without outputting the phase error data dT k . In FIG. 12 the combination of the current phase error data and the previous phase error data is classified into three kinds of patterns depending upon the code of the code (Po k × Po k-1 ) and the magnitude of the phase error data dT k . FIG. 14 shows the three kinds of patterns. FIG. 14(a) shows a pattern where the judgement is NO (Po k × Po k-1 < 0) at Step S75, and again is NO ( dTk| > dT 0 ) at Step S76. In this pattern the polarity changes when the clock timing changes from k-1 to k, and the phase error data dT k exceeds the threshold level. This corresponds to a case where a shift in the detected maximum decode likelihood decode data occurs owing to an error. In this case the polarity Po k by the clock timing k is substituted by the polarity Po k-1 by the clock timing k-1, and the sequence advances to the next clock processing step without outputting the phase error data. As a result, if an error occurs in the detection data, the error is prevented from propagating to the next detection data. FIG. 14(b) shows a pattern where the judgement is NO (Po k × Po k-1 < 0) at Step S75, and is YES (|dTk| ≦dT 0 ) at Step S76. In this pattern the polarity does not change but the phase error data dT k does not exceed the threshold level, and the phase error data dT k is outputted and the sequence advances to the next clock. FIG. 14(c) shows a pattern where the judgement is YES (Po k × Po k-1 ≧ 0) at Step S75. In this pattern, since the polarities are the same, the phase error date dT k is outputted, and the sequence advances to the next clock. As is evident from the foregoing description, the first embodiment also described above detects a phase error dT k from the sampling value y k , the maximum likelihood decode data d k , and the central value C kave of the reproduction signal, and compensates a phase shift of a synchronous clock in the PLL-base system by using the detected phase error data dT k , but this embodiment is different from the prior art in that it controls whether the detected phase error data dT k is delivered to the PLL-base system or not, on the basis of a change in the polarity of the phase error data dT k and the amplitude thereof. Referring to FIG. 15, which illustrates a structure of a phase error detecting unit 25 for use in an embodiment of the present invention, the phase error detecting unit 25 will be described: The phase error detecting unit 25 includes a first shift register 251, a second shift register 252, a constant value setting unit 253, a first subtracter 254, a second subtracter 255, a first selector 256, a first comparator 257, a second comparator 258, a second selector 259, a third selector 260, a third shift register 261, an EXOR circuit 262, four AND circuits 263, 264, 265, and 266, a fourth selector 267, and a data bit extractor 268. Referring to FIG. 16, the input/out characteristics in the first comparator 257 and the second comparator 258 will be described: When two input values a and b are respectively inputted to the first and second comparators 257 and 258, these values a and b are compared, and 1-bit data c, d or e is outputted depending upon a dimensional relationship therebetween. The first shift register 251 holds a central values C kave from the central value calculating unit 22 until the next clock timing. The second shift register 252 holds a sampling value y k obtained by the A/D converter 6 until the next clock timing. The first subtracter 254 subtracts a sampling value y k-1 from the second shift register 252 from the central value C k-lave from the first shift register 251. The value outputted from the first subtracter 254 by a clock timing corresponding to the leading-edge becomes a calculated leading-edge phase error data dTf k at Step S72 as shown in FIG. 12. The second subtracter 255 subtracts the central value C k-lave from the first shift register 251 from the sampling value y k-1 from the second shift register 252. The value outputted from the second subtracter 255 by a clock timing corresponding to the trailing-edge becomes a calculated trailing-edge phase error data dTr k at Step S72 as shown in FIG. 12. The constant value setting unit 253 has a previously set constant value "0". The first selector 256 includes three input terminals A, B and C. The constant value "0" set at the constant value setting unit 253 is inputted to the input terminal A, a value from the first subtracter 254 is inputted to the input terminal B, and a value from the second subtracter 255 is inputted to the input terminal C. The first selector 256 selects an input terminal corresponding to a leading-edge maximum likelihood decode data def k and a trailing-edge maximum likelihood decode data der k . in accordance with the table shown in FIG. 17A. More specifically, the first selector 256 outputs the leading-edge phase error data dTf k by a clock timing (def k = "1" , der k = "0" ) corresponding to a leading-edge point of the reproduction signal, the trailing-edge phase error data dTr k by a clock timing (def k = "0" , der k = "1" ), and the constant value "0" by a clock timing (def k = "0" , der k = "0" ) corresponding to other points except the leading-edge point and the trailing-edge point of the reproduction signal. The output value of the first selector 256 is inputted to the fourth selector 267, the first comparator 257 and the data bit extractor 268. The fourth selector 267 includes two input terminals H and I, and a constant value "0" set at the constant value setting unit 253 is inputted to the input terminal H, and an output value from the first selector 256 is inputted to the input terminal I. In addition, an output value from the AND circuit 266 referred to below is inputted to the fourth selector 267. In accordance with the table shown in FIG. 17D, an input value to be inputted to the input terminal H is selected when the output value of the AND circuit 266 is "1" , and the input value to be inputted to the input terminal I is selected when the output value is "0" , and the selected value is outputted to the D/A converter 11. The first comparator 257 receives an output value from the first selector 256 as an input value a, and the constant value "0" as an input value b. The two values are compared, and depending upon the result of comparison, 1-bit output value d is outputted to the second selector 259 and the EXOR circuit 262 or 1-bit output value e is outputted to the third selector 260 and the AND circuit 263. FIG. 18 is a table corresponding to FIG. 13 which shows a pattern of truth values of the polarity change occurring in the phase error data, with respect of output values e and d from the first comparator 257. The second selector 259 has two input terminals D and E, and a 1-bit output value d from the first comparator 257 is inputted to the input terminal D, and an output value d from the third shift register 261 at the rear stage is inputted to the input terminal E. The output value of the AND circuit 266 is inputted to the second selector 259, and in accordance with the table shown in FIG. 17B, when the output value of the AND circuit 266 is "0" , the input value to the input terminal D is selected, and when the output value thereof is "1" , the input value to the input terminal E is selected, and the selected value is outputted to the third shift register 261. Likewise, the third selector 260 includes two input terminals F and G, and a 1-bit output value e from the first comparator 257 is inputted to the input terminal F and an output value e from the third shift register 261 at the rear stage is inputted to the input terminal G. An output value of the AND circuit 266 is inputted to the third selector 260. In accordance with the table shown in FIG. 17C, when the output value of the AND circuit 266 is "0", the input value to the input terminal F is selected, and when it is "1" , the input value to the input terminal G is selected, and the selected value is outputted to the third shift register 261. The EXOR circuit 262 determines an EXOR of the output value d from the first comparator 257 and the output value d from the third shift register 261, and outputs it to the AND circuit 264. The AND circuit 263 determines an AND of the output value e from the first comparator 257 and the output value e from the third shift register 261, and outputs it to the AND circuit 265. If, for example, the first selector 256 outputs an 8-bit output value, wherein the most significant bit (MSB) represents a code (positive, negative), and the other seven bits represent the amplitude of the level. The data bit extractor 268 extracts the 7-bit data bits except the MSB from an output value of 8-bit from the first selector 256, and outputs it to the second comparator 258 to which an input value from the data bit extractor 268 is inputted as an input value a, and the threshold level dT 0 is inputted as an input value b. The two values are compared, and depending upon the result of comparison, a 1-bit output value c is outputted to the AND circuit 264, and a 1-bit output value d is outputted to the AND circuit 265. The AND circuit 264 determines the AND of the output value from the EXOR circuit 262 and the output value c from the second comparator 258, and outputs it to the AND circuit 266. The AND circuit 265 determines the AND of the output value from the AND circuit 263 and the output value d from the second comparator 258, and outputs it to the AND circuit 266. The AND circuit 266 determines the AND of the output from the AND circuit 264 and the output from the AND circuit 265, and outputs it to the second selector 259, the third selector 260 and the fourth selector 267. The operation of the first embodiment will be described: A reproduction signal having a partial response characteristic corresponding to a maximum likelihood decoding obtained by the optical head 2 from the optical disk 1 is delivered to the A/D converter 6 through the amplifier 3, the equalizer 4 and the LPF 5. The A/D converter 6 obtains a sampling value of the reproduction signal in synchronism with a clock signal from the VCO 13, and delivers it to the maximum likelihood decoder 7. The maximum likelihood decoder 7 processes the sampling value in the merge determining unit 21, the central value calculating unit 22, the reference value calculating unit 23 and the merge detecting unit 24 in accordance with the flowcharts shown in FIG. 3, FIG. 4, FIG. 5 and FIG. 6, and the maximum likelihood decode data d k is obtained. The obtained maximum likelihood decode data d k is outputted to the demodulator 8. The maximum likelihood decoder 7 is operated in synchronism with a clock signal from the VCO 13. The maximum likelihood decoder 7 processes at the phase error detecting unit 25 as shown in FIG. 12 and a phase error data dT k is obtained. The phase error data dT k is outputted to the D/A converter 11 where the data dT k is converted into a phase error signal. This phase error signal is converted into a voltage level by the LPF 12. The phase of the reference clock signal is adjusted by the VCO 13 in accordance with the converted voltage level, and the adjusted clock signal is delivered to the A/D converter 6 and the maximum likelihood decoder 7. Synchronizing with the clock signal, the A/D converter 6 performs the sampling and the maximum likelihood decoder 7 performs the detection of the maximum likelihood decode data d k and the phase error data dT k . The maximum likelihood decode data d k delivered to the demodulator 8 is relieved of the 1/7 run-length limitation. In this way the original record data is reproduced. A second embodiment (a front and trailing-edge independent system) has basically the same structure as that shown in FIG. 9, which is proposed in Japanese Patent Application No. 6-225433, but the second embodiment is different from previously proposed systems in the maximum likelihood decoder 7a and 7b, especially the phase error detecting unit 25. FIG. 9 illustrates the overall structure of a data reproduction apparatus of the second embodiment, wherein like reference numerals designate like elements and components to those in FIG. 1. Referring to FIG. 9, the reproduction of a signal under the front and trailing-edge independent system of the second embodiment will be described: The A/D converter 6a, the maximum likelihood decoder 7a, the D/A converter 11a, the LPF 12a and the VCO 13a constitute a maximum likelihood decode data detecting system for a leading-edge, and the A/D converter 6b, the maximum likelihood decoder 7b, the D/A converter 11b, the LPF 12b and the VCO 13b constitute a maximum likelihood decode data detecting system for a trailing-edge. The A/D converter 6a, 6b, D/A converter 11a, 11b, LPF 12a, 12b, and VCO 13a, 13b have the same structure as those of the A/D converter 6, D/A converter 11, LPF 12 and VCO 13 shown in FIG. 1. Each of the maximum likelihood decoders 7a and 7b has the same structure as that of the maximum likelihood decoder 7 (refer to FIG. 2) shown in FIG. 1. In FIG. 9, however, the leading-edge system and the trailing-edge system are independently provided. In the leading-edge maximum likelihood decoder 7a, the merge detecting unit 24 outputs a leading-edge maximum likelihood decode data def k , and the phase error detecting unit 25 outputs a leading-edge phase error data dTf k . In the trailing-edge maximum likelihood decoder 7b, the merge detecting unit 24 outputs a trailing-edge maximum decode data der k , and the phase error detecting unit 25 outputs a trailing-edge phase error data dTr k . FIGS. 19 and 20 respectively show the sequences of operating the leading-edge and trailing-edge phase error detecting units 25. In the leading-edge phase error detection shown in FIG. 19, when a new leading-edge maximum likelihood decode data def k is inputted (Step S81), the leading-edge phase error data dTf k is calculated by reference to dTf k = (C k-lave - y k-1 ) • def k (Step S82). Then, the polarity Pof k of the leading-edge phase error data dTf k is determined (Step S83) by using a SIGN function. The polarity Pof k is multiplied by the one-clock previous polarity Pof k-1 so as to determine a polarity change, and judge whether the product is not less than 0 (zero) (Step S84). When it is not less than 0, the obtained leading-edge phase error data dTf k is outputted to the D/A converter 11a (Step S87). If the product is less than 0, the absolute value of the leading-edge phase error data dTf k and a predetermined threshold level dT 0 are compared (Step S85). If the absolute value of the leading-edge phase error data dTf k is not more than the threshold level dT 0 , the leading-edge phase error data dTf k is outputted to the D/A converter 11a (Step S87). If it is larger than dT 0 , the current polarity Pof k is substituted by the former polarity Pof k-1 (Pof k = Pof k-1 ) (Step S86) and the sequence is returned without outputting the leading-edge phase error data dTf k . In the trailing-edge phase error detection shown in FIG. 20, when a new trailing-edge maximum likelihood decode data der k is inputted (Step S91), the trailing-edge phase error data dTr k is calculated with dTr k = (y k-1 - C k-lave ) • der k (Step S92). Then, the polarity Pork of the trailing-edge phase error data dTr k is determined by using a SIGN function (Step S93). The polarity Por k is multiplied by the one-clock previous polarity Por k-1 so as to determine a polarity change, and judge whether the product is not less than 0 (zero) (Step S94). When it is not less than 0, the obtained trailing-edge phase error data dTr k is outputted to the D/A converter 11b (Step S97). If the product is less than 0, the absolute value of the trailing-edge phase error data dTr k and a predetermined threshold level dT 0 are compared (Step S95). If the absolute value of the trailing-edge phase error data dTr k is not more than the threshold level dT 0 , the trailing-edge phase error data dTr k is outputted to the D/A converter 11b (Step S97). If it is larger than dT 0 , the current polarity Por k is substituted by the former polarity Por k-1 (Por k = Por k-1 ) (Step S96) and the sequence is returned without outputting the trailing-edge phase error data dTr k . The leading-edge maximum likelihood decode data def k and the trailing-edge maximum likelihood decode data der k from the maximum likelihood decoders 7a and 7b are inputted to a synthesizer 9, which is constituted with an FIFO memory or the like, while the former synchronizes with a leading-edge clock signal from the VCO 13a, and the latter synchronizes with a trailing-edge clock signal from the VCO 13b. The leading-edge maximum likelihood decode data def k and the trailing-edge maximum likelihood decode data der k are alternately read out from the synthesizer 9 in synchronism with either the leading-edge clock signal or the trailing-edge clock signal. In this way a synthesized maximum likelihood decode data d k is obtained. The synthesized data d k is demodulated into the original record signal by the demodulator 8 similarly to the example shown in FIG. 1. The embodiments described above are constructed such that if an error occurs during the maximum likelihood decoding time, the phase error detecting unit 25 outputs no phase error data so as to prevent a possible propagation of the decoding error. Alternatively, it is possible to ensure that if an error occurs in a maximum likelihood decode, the former phase error data can be again outputted so as to prevent the propagation of the decoding error. In this case, a shift register is provided in the circuit shown in FIG. 15 so as to hold the output from the fourth selector 267 until the next clock timing, and the output value of the shift register is inputted to the input terminal H of the fourth shift register 267 instead of the constant value "0" of the constant value setting unit 253. Under this arrangement either the input terminal H or I of the fourth selector 267 is selected in accordance with the output value of the AND circuit 266 in the same manner as described above. In the embodiments described above, reference has been made to a case where a phase shift of a synchronous clock signal is compensated exclusively on the basis of the detected phase error data. In addition, embodiments of the present invention can be used in every case where phase error data is utilized. For example, an embodiment can be used in a reproduction system under which a phase shift of a clock signal is compensated by a signal obtained by adding a detected phase error signal to a synchronous signal obtained by slicing an analog reproduction signal in a binary circuit. An embodiment may also be used in a reproduction system under which either of the synchronous signal obtained by slicing an analog reproduction signal in a binary circuit and the detected phase error signal is selected, and the selected signal is used to compensate the phase shift of a clock signal. As is evident from the foregoing description, even if a phase error occurs at a sampling point ideal for a synchronous clock signal, it is canceled by the PLL circuit, thereby ensuring that a reproduction signal is constantly sampled at an optimum position. As a result, the maximum likelihood decoding is accurately performed. Even if an error occurs during maximum likelihood decoding time, the decoding error is prevented from affecting the clock signal and propagating. In previously-considered systems, if an error occurs in the decode data due to noise, edge shift, or defective medium, the phase error signal is likely to amplify the phase shift and allow the error to propagate. In such cases, embodiments of the present invention can automatically correct a phase shift of the clock signal, thereby reducing the possibility of error propagation, improving in the error rate, and enhancing the mass-productivity because of having no necessity of phase adjustment.

Claims: A method for reproducing data recorded in an optical disk as a signal obtained by modulating the data in accordance with a predetermined partial response characteristic, comprising the steps of: reproducing a signal from the optical disk; generating a synchronous clock signal from the reproduction signal; obtaining a sampling value from the reproduction signal in synchronism with the synchronous clock signal; detecting maximum likelihood decode data on the basis of the sampling value in synchronism with the synchronous clock signal; detecting a phase error at a time between a point of time when the synchronous clock signal is generated and a point of time when the reproduction signal is sampled on the basis of the sampling value, the maximum likelihood decode data and a central value of the reproduction signal; judging whether the detected phase error is useable for compensating a phase shift of the synchronous clock signal based on the polarity of the phase error; and correcting the detected phase error so as to compensate for the phase shift of the synchronous clock signal. The method according to claim 1, wherein the phase error includes a leading-edge phase error and a trailing-edge phase error which are independently detected and corrected. The method according to claim 1, wherein the phase error is corrected on the basis of the amplitude thereof. The method according to claim 2, wherein the phase errors are corrected on the basis of the amplitudes thereof. The method according to claim 1, wherein the phase error is corrected on the basis of the polarity and amplitude thereof. The method according to claim 2, wherein the phase errors are corrected on the basis of the polarities and amplitudes thereof. An apparatus for reproducing data recorded in an optical disk as a signal obtained by modulating the data in accordance with a predetermined partial response characteristic, comprising: means for reproducing a signal from the optical disk; means for generating a synchronous clock signal from the reproduction signal; sampling means for obtaining a sampling value from the reproduction signal in synchronism with the synchronous clock signal; maximum likelihood decoding means for detecting maximum likelihood decode data on the basis of the sampling value in synchronism with the synchronous clock signal; phase error detecting means for detecting a phase error at a time between a point of time when the synchronous clock signal is generated and a point of time when the reproduction signal is sampled on the basis of the sampling value, the maximum likelihood decode data and a central value of the reproduction signal; a judging means for judging whether the detected phase error is useable for compensating a phase shift of the synchronous clock signal based on the polarity of the phase error; and phase error correcting means for correcting the phase error detected by said phase error detecting means so as to compensate for the phase shift of the synchronous clock signal. The apparatus according to claim 7, wherein said phase error detecting means independently detects a leading-edge phase error and a trailing-edge phase error, and said phase error correcting means independently corrects these phase errors. The apparatus according to claim 7, wherein said phase error correcting means sets a threshold level whereby the amplitude of the phase error is recognized. The apparatus according to claim 8, wherein said phase error correcting means sets a threshold level whereby the amplitude of the phase errors is recognized.

Inventors: IZUMI HARUHIKO, TAGUCHI MASAKAZU, IZUMI, HARUHIKO, TAGUCHI, MASAKAZU
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1996
Main classification: G11B20
IPC codes: G11B20, G11B7