Programmable reference voltage source, particulary for analog memories

Abstract: The programmable reference voltage source (1) includes a nonvolatile memory cell (2), the floating-gate region (3) of which stores electric charges determining a memorized threshold value. The drain terminal (4) of the cell is biased at a constant voltage (D r ), and the source terminal (14) is connected to a constant-current source (21) and to the inverting input of an operational amplifier (21) having the noninverting input connected to a reference voltage (V r ) and the output (10) connected to the gate terminal (8) of the cell (2). By defining the threshold of the cell (2) as the gate voltage (measured with respect to ground) capable of causing the cell (2) to be flown by the current (I s ) set by the current source (22), the output voltage (V o ) of the operational amplifier (21) equals the threshold and may be used as a programmable reference in analog memories.

Description: The present invention relates to a programmable reference voltage source, particularly for analog memories. As is known, for performing complex processing functions, analog memories with cells capable of memorizing analog or digital multibit values are currently being studied, for which use is advantageously made of nonvolatile floating-gate cells, particularly flash-EEPROMs, in which the value to be memorized is related to the threshold voltage of the cell. To read the cells and/or perform calculating operations, a number of voltage references are required; the references must be programmable to achieve a high degree of flexibility as regards use of the memories, to enable uniform design of memories to be used for various applications and in particular for various analog values to be stored, and to enable the reference voltages to be modified even during operation of the memory, according to the functions to be performed. According to one known solution described in US Patent US-A-5,126,967, the reference (and data) cells are read via a sample-and-hold circuit, this solution, however, fails to provide for fast read times when memorizing a large number of voltage levels. US-A-5, 289, 401 discloses an analog storage device for artificial neural network system, wherein an electrically erasable programmable transistor is employed as one memory cell. The memory cell is read via a reading circuit comprising a monitoring transistor and an operational amplifier, the monitoring transistor having its floating gate formed integral with that of the memory cell transistor for monitoring a change in the threshold voltage of the memory cell transistor, and its source electrode coupled to a constant current source, and the operational amplifier having its inverting input coupled to the source electrode of the monitoring transistor, non-inverting input coupled to receive an externally applied voltage of a given magnitude, and an output coupled to the control gate electrode of the monitoring transistor and supplying a constant voltage independent of variations of the threshold voltage of the monitoring transistor. US-A-4,181,980 discloses a method and apparatus for the acquisition and storage of analog signals, wherein an MOS device with a floating gate and a conductively connected gate is operated in that pulses are applied to the latter gate to capacitively charge the floating gate, the drain potential is compared in-between pulses with the analog signal, and pulse application is stopped when agreement has been reached. It is an object of the present invention to provide a reference voltage source capable of supplying programmable reference voltages with a high degree of precision and low access time. According to the present invention, there is provided a programmable reference voltage source, particularly for analog memories, as claimed in Claim 1. A preferred, non-limiting embodiment of the present invention will be described by way of example with reference to the accompanying drawings, in which: Figure 1 shows a simplified electric diagram of the reference source according to the present invention; Figure 2 shows one possible application, in an analog memory, of the source according to the invention. In the Figure 1 circuit, indicated as a whole by 1, a nonvolatile memory cell 2 - more specifically, a flash cell - comprises a floating-gate region 3 (shown schematically) in which is stored an electric charge defining the threshold voltage V th of the cell; a drain terminal 4 connected to a switch 5, which connects drain terminal 4, in a first position, to a reference potential line 6 at voltage D r , and, in a second position, to a first programming line 7 at voltage V PD ; a gate terminal 8 connected to a switch 9, which connects gate terminal 8, in a first position, to a node 10, and, in a second position, to a second programming line 11 at voltage V PG ; and a source terminal 14 connected to a switch 15, which connects source terminal 14, in a first position, to a node 16, and, in a second position, to a voltage V PS , which, in the case of programming, equals 0 V (ground line). The control terminals of switches 5, 9, 15 (shown only schematically in Figure 1) are controlled by a control logic circuit 20. Node 16 is connected to the inverting input of a first operational amplifier 21, and to one terminal of a current source 22; first operational amplifier 21 has the noninverting input connected to a reference line 24 at voltage V r (e.g. ground), and the output connected to node 10 at voltage V o ; the output of first operational amplifier 21 is connected to the noninverting input of a second full-feedback operational amplifier 26 (inverting input connected to output 27) operating as a buffer; and current source 22 - generating current I s - has the second terminal connected to a reference line 28 at voltage S r lower than voltage V r . More specifically, if voltage V r is 0 V (ground line), voltage S r is negative, e.g. -250 mV. The Figure 1 circuit operates as follows. To begin with, switches 5, 9 and 15 are assumed to be in the positions shown; and the gate voltage (measured with respect to ground) able to cause the cell 2 to draw the current I s set by current source 22 is defined as the threshold V TH of cell 2. The current I D circulating in cell 2 is approximately given by the equation: I D = K(V gs -V th ) 2 where K is a constant depending on the fabrication method, V gs is the gate-source voltage drop, and V th is the threshold voltage at which the cell starts turning on (at theoretically zero current). In the circuit shown, as current I D in the cell must equal the current I s set by source 22 (I D = I s ), the overdrive voltage V ov = V gs -V th of the cell is fixed. Moreover, when V r = 0 V and in equilibrium, voltage V s at source terminal 14 of the cell, set by the closed-loop connection of operational amplifier 21, is also zero, so that output voltage V o of first operational amplifier 21 - equal to the gate voltage of cell 2 measured with respect to ground - equals voltage drop V gs of the cell, i.e. threshold voltage V th of the cell plus the overdrive voltage V ov determined in (1). As such: V o = V ov + V th so that, according to the above definition of threshold V TH , it follows that V o = V TH . Second operational amplifier 26 supplies voltage V o at output 27, and is capable of driving even high resistive/capacitive loads, so that output 27 presents an analog voltage of a value equal to the programmed threshold V TH of the cell, which may be set and modified by altering the amount of charge stored in floating-gate region 3 of cell 2. Programming of cell 2 is controlled by control logic circuit 20, which determines program pulse duration by controlling the position of switches 5, 9, 15, and decides when programming is to be interrupted. More specifically, to program cell 2, control logic circuit 20 connects its drain, gate and source terminals 5, 8 and 14 respectively to line 7, line 11 and V PS (ground) for a predetermined time interval; then switches switches 5, 9 and 15 to the positions shown in Figure 1; reads the voltage V o reached by cell 2 at node 10 or output 27 (as shown in Figure 1) and compares it with the desired programming value to determine whether the programming procedure is to be terminated or whether a further programming step is to be performed by again switching switches 5, 9, 15. An example of application of the source according to the invention in an analog memory for calculating the distance between vectors comprising a number of input values and vectors comprising a number of stored values is shown in Figure 2, the general architecture of which is known to experts in the field (see, for example, "Ultra-Low-Power Analog Associative Memory Core Using Flash-EEPROM-Based Programmable Capacitors," by A. Kramer, R. Canegallo, M. Chinosi, D. Doise, G. Gozzini, P.L. Rolandi, M. Sabatini, P. Zabberoni, ISLPD '95 Symposium Proceedings, p. 203-208). The Figure 2 configuration, which provides for calculating euclidean distance, shows a reference array 30 comprising a number of circuits 1, each comprising a respective cell 2 memorizing a different threshold value, and each formed as shown in Figure 1, except that, to prevent undesired soft writing phenomena, the switches (here indicated 9') connected to the gate terminals of cells 2 have a third position for grounding the gate terminals of the cells not meant for programming (only one cell being programmed at a time). The outputs of circuits 1 - supplying voltages V 1 , V 2 , ..., V n equal to the different memorized thresholds V TH - are supplied to any type of switching array 31 (e.g. as described in a co-pending patent application filed concurrently and entitled " Input structure, in particular for analog or digital associative memories") which, on the basis of a control signal T generated by control logic circuit 20 (not shown in Figure 2), connects one or more nodes 27 to one or more word lines 33 of a memory array 34 comprising flash cells 35 of the same type as cells 2, and each memorizing a different threshold voltage. More specifically, cells 35 are arranged in rows and columns; the cells in the same row have the gate terminals connected to the same word line 33, all the drain terminals connected together to an adding element 36, all the source terminals grounded together; and adding nodes 36 (formed in known manner (not shown), e.g. by means of an operational amplifier fedback through a resistor) are connected to a known "winner-take-all" circuit 38 in turn connected at the output to a decoding circuit 39. In the Figure 2 device, the output voltages V 1 -V n at nodes 27 are selectively supplied by switching array 31 to the gate terminals of cells 35 to determine the difference between the value of the vector supplied over word lines 33 and the vectors stored in cells 35; nodes 36 add the currents flowing in all of cells 35 in the same row; "winner-take-all" circuit 38 selects the row corresponding to the minimum value at adding nodes 36; and decoder 39 outputs the digital decoding of the selected row. The advantages of the circuit described are as follows. In particular, it provides for analog references programmable according to a specific application by means of a simple, easy-to-integrate structure formed using the same technology as the analog circuits using the references; and programmability of the cell threshold voltage provides for freely and repeatedly modifying the output reference. Moreover, if the output voltage is used as a reference for memory cells of the same type as the circuit cell, the voltage supplied is temperature-compensated. That is, any variation in threshold voltage V th of cell 2 due to temperature is supplied, via operational amplifiers 21, 26, to the memory cells to be read (35 in Figure 2). As these, however, present the same variation in threshold voltage, the overdrive remains substantially constant. More specifically, if V t is the threshold voltage, and V i the gate-source voltage of the i-th cell 35, its overdrive voltage equals V ov = V i - V t . If threshold V t of cells 35 increases by ΔV due to a variation in temperature (V t ' = V t + ΔV), threshold V th of cells 2 also increases by ΔV. Since the overdrive voltage of cells 2 is fixed by current I s , the output voltage to circuits 1, applied to the gate terminals of cells 35, increases by the same amount, i.e.: V i' = V i + ΔV, so that the overdrive voltage V ov ' of cells 35 may be expressed as follows: V ov' = V i' - V t' = V i + ΔV - (V t + ΔV) = V i - V t = V ov The circuit described is highly precise, and, should precision be impaired by drift, may easily be reprogrammed to maintain predetermined levels of precision. Moreover, consumption is low (in the order of µA) and the circuit may also be used in low-power (e.g. portable) electronic devices. Cells 2 may be programmed and erased using the same configuration as in Figure 1, by appropriately biasing the terminals. Clearly, changes may be made to the circuit as described and illustrated herein without, however, departing from the scope of the present invention, as defined in the appended claims. In particular, the biasing value of the drain terminal of the cell may be selected as required, and the noninverting terminal of amplifier 21 may be biased at any constant voltage, while the ground connection preventing the body effect (which, as is known, causes the threshold value of the cell to depend also on the voltage between the source and body regions of the cell). Changes may be made to the programming procedure and programming circuit, which do not form part of the invention. The current source may be formed in any known manner (e.g. by means of MOS transistors or current mirrors), and the circuit may be used for any application requiring on-chip programmable voltage references. In the case of a reference array, and if only one reference voltage at a time is required, as opposed to forming a number of separate circuits 1, only cells 2 need be duplicated using a single operational amplifier 21 and respective buffer 26 with appropriate switching devices.

Claims: A programmable reference voltage source (1), in particular for analog memories, comprising a nonvolatile memory cell (2) having a drain terminal (4), a gate terminal (8), a source terminal (14), and a floating gate region (3) storing electric charges determining a threshold value programmed in said nonvolatile memory cell (2); and programming means (5, 9, 15) connected to said drain, source and gate terminals (4, 8, 14) of said nonvolatile memory cell (2) to program a desired threshold value; characterized by reading means (21, 26) connected to said gate and source terminals (8, 14) of said nonvolatile memory cell (2) to read the threshold value programmed therein, said reading means (21, 26) comprising an operational amplifier (21) having a first input connected, during reading of said memory cell (2), to said source terminal (14) of said nonvolatile memory cell (2), a second input connected to a first constant voltage line (24), and an output connected, during reading of said memory cell (2), to said gate terminal (8) of said nonvolatile memory cell (2) and configured to provide the threshold value programmed therein; and by control means (20) configured to receive the threshold value programmed in said nonvolatile memory cell (2) from said operational amplifier (21) and to control operation of said programming means (5, 9, 15) based on said programmed threshold value, so as to program said desired threshold value in said nonvolatile memory cell (2). A programmable reference voltage source as claimed in claim 1, wherein said programming means (5, 15) comprise first switching means (5) for selectively connecting said drain terminal (4) of said nonvolatile memory cell (2) to a second constant voltage line (6) or to a first programming voltage line (7); second switching means (9) for selectively connecting said gate terminal (8) of said nonvolatile memory cell (2) to said output (10) of said operational amplifier (21) or to a second programming voltage line (11); and third switching means (15) for selectively connecting said source terminal (14) of said nonvolatile memory cell (2) to said first input (16) of said operational amplifier (21) or to a reference potential line (V PS ); said control means (20) being configured to generate control signals for said first, second and third switching means (5, 9, 15). A programmable reference voltage source as claimed in claim 2, further comprising first and second biasing means (6, 22) for biasing said drain terminal (4) and, respectively, said source terminal (14) of said nonvolatile memory cell (2). A programmable reference voltage source as claimed in claim 3, wherein said first biasing means comprise said second constant voltage line (6), and said second biasing means comprise a constant current source (22). A programmable reference voltage source as claimed in claim 4, wherein said constant current source (22) has a first terminal connected to said first input (16) of said operational amplifier (21), and a second terminal connected to a third constant voltage line (28) set at a lower potential than that of said first constant voltage line (24). A programmable reference voltage source as claimed in any one of the foregoing claims, wherein said nonvolatile memory cell (2) is a flash-EEPROM cell. A programmable reference voltage source as claimed in any one of the foregoing claims 2 to 6, further comprising a buffer element (26) connected to said output of said operational amplifier (21). A programmable reference voltage source as claimed in claim 7, wherein said buffer element comprises a full-feedback operational amplifier (26).

Inventors: CANEGALLO ROBERTO, CHINOSI MAURO, GOZZINI GIOVANNI, KRAMER ALAN, ROLANDI PIER LUIGI, SABATINI MARCO, CANEGALLO, ROBERTO, CHINOSI, MAURO, GOZZINI, GIOVANNI, KRAMER, ALAN, ROLANDI, PIER LUIGI, SABATINI, MARCO, Kramer, Alan c/o STMicroelectronics S.r.l.
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1996
Main classification: G11C27
IPC codes: G11C16, G05F1, G11C27