Matched filter circuit

Abstract: An object of the present invention is to provide a matched filter circuit of small size and consuming low electric power. Paying attention that a spreading code is a 1 bit data string, an input signal is sampled and held as an analog signal along the time sequence, classified into "1" and "- 1" and the classified signals are added in parallel by capacitive coupling in a matched filter circuit according to the present invention.

Description: The present invention relates to a matched filter circuit, especially to a matched filter effective for a spread spectrum communication system for the mobile cellular radio and wireless LAN. A matched filter is a filter for judging the identification between two signals. In the spread spectrum communication system, each user who receives a signal processes a received signal by a matched filter using a spreading code allocated for the user so as to find a correlation peak for acquisition and holding. Here, assuming that a spreading code is d(i), sampling interval is Δ t, a length of diffusion code is N, a received signal before a time t is x(t-i Δ t), a correlation output y(t) of matched filter is as in formula (1). In formula (1), d(i) is a data string of 1 bit data. It is necessary to perform double sampling or higher order of sampling for acquisition. In this case, the operation in the formula (1) is performed at the same time in a plurality of systems. Conventionally, a digital circuit of SAW device (surface acoustic wave device) is used for the processing. However, there are problems that when a digital circuit is used, the size of the circuit is large and hence, the power consumption is also large which makes it not suitable for mobile radio communication devices. When the SAW device is used, the total circuit cannot be incorporated within one LSI and the S/N ratio is low. US-A-4 507 746 discloses a programmable digital device designed to perform a matched filtering operation on arbitrary binary phase-coded signals. The device comprises a first and a second half adder each having two inputs and sum and carry outputs, a network for summing the outputs of the adders and means for connecting the carry output of the first adder to an OR gate. Further, there are provided means for connecting the sum output of the second half adder to the other input of said OR gate. Finally, the device comprises means for utilizing the sum output of the first half adder, the output of said OR gate and the carry output of said second half adder as the outputs of said network. An object of the present invention is to solve the above problems and to provide a matched filter circuit of small size and consuming low electric power. This object is solved by the features of claim 1. Paying attention that a spreading code is a I bit data string, an input signal is sampled and held as an analog signal along the time sequence, classified into "1" and "-1" and the classified signals are added in parallel by capacitive coupling in a matched filter circuit. It is possible to process in high speed by a LSI of small size and low electric power by the matched filter circuit. Figure 1 shows a block diagram of an embodiment of the matched filter circuit according to the present invention. Figure 2 shows a sampling and holding circuit in the embodiment in Figure 1. Figure 3 shows a switch in the embodiment in Figure 1. Figure 4 shows a multi-plexer in the embodiment in Figure 1. Figure 5 shows the first addition portion in the embodiment in Figure 1. Figure 6 shows the second addition portion in the embodiment in Figure 1. Figure 7 shows the third addition portion in the embodiment in Figure 1. Figure 8 shows the reference voltage generating circuit in Figure 1. Figure 9 shows the plan view of a capacitance in Figure 1. Hereinafter, the embodiment of a filter circuit according to the present invention is described with referring to the drawings. In Figure 1, the matched filter circuit according to the present invention includes a plurality of sampling and holding circuits S/H for parallelly receiving an input voltage Vin. Two types of outputs of H (high) and L (low) are generated from each sampling and holding circuit. A control circuit CTRL is connected to the sampling and holding circuit so as to control Vin to be input to one of the sampling and holding circuits, successively. The sampling and holding circuit introduces the input voltage Vin to either H side or L side according to the control of the control circuit CTRL. A reference voltage Vr is connected by the control circuit to the other side. This route selection performed according to 1 bit spreading code and a multiplication of input voltage by the code is completed only by this selection. A sampling and holding circuit S/H is structured as in Figure 2 in which an input voltage Vin is connected to a switch SW. An output of switch SW is connected to capacitance C1, and three stages of serial MOS inverters I1, I2 and I3 are connected to an output of capacitance C1. An output of MOS inverter 13 of the last stage is connected to an input of I1 through feedback capacitance C2. Consequently, an inversion of Vin is generated at the output of 13 with a good linearity. An output of 13 is input to two multi-plexers MUX1 and MUX2. A common reference voltage Vr is connected to the multi-plexers. When SW is closed, C1 is charged by an electric change corresponding to Vin, and the linearity of an output is guaranteed by a feed-back function of I1 to I3. When a switch SW is open after it, sampling and holding circuit S/H holds Vin. Switch SW, multi-plexers MUX1 and MUX2 are controlled by control signals S1, S2 and S3. After S1 is once closed, SW1 is opened at the timing of sampling the input voltage. S2 and S3 are inverted signals. When one of the multi-plexers outputs Vin, the other outputs Vr. MUX1 generates an outputs of H (high type) above and MUX2 generates an output of L (low type). H and L correspond to each bit of the spreading codes "1" and "-1". When the code "1" is to be multiplied to an input voltage at a timing, Vin is output from MUX1, and when the code "-1" is to be multiplied, Vin is output from MUX2. The output from I3 of the last stage is connected to the ground through the grounded capacitance CG1. The output of 12 of the second stage is connected to the supply voltage Vdd and the ground through a pair of balancing resistances RE21 and RE22. Unstable oscillations of an inverted amplifying circuit including feedback circuit is prevented by such a structure. As shown in Figure 3, the switch SW includes a transistor circuit T1 in which a source and a drain of a n-type MOS transistor are connected to a drain and a source of a p-type MOS transistor, respectively. Vin is connected to a terminal of a drain of the nMOS of the transistor circuit and a terminal of a source of nMOS is connected to an output terminal TO1 through a dummy transistor DT similar to the nMOS. S1 is input to the gate of the nMOS transistor of the transistor circuit T1, and an inverted signal of S1 by an inverter I4 is input to the gate of pMOS transistor. When S1 is high level, T1 is conductive and when it is low level, T1 is cut off. In Figure 4, there are provided transistor circuits T2 and T3 each consisting of nMOS and pMOS, a source of nMOS and drain of pMOS are connected to each other and to a common output terminal TO2. As shown in Figure 4, in multi-plexer MUX1, the terminal of the source of nMOS of transistor circuits T2 and T3 is connected to the common output terminal TO2. An output of the MOS inverter I3 ("V1" in Figure 4) is connected to a terminal of a drain of the nMOS of T2, and the reference voltage Vr is connected to a drain of T3. The signal S2 is input to a gate of the nMOS transistor of transistor circuit T2 and gate of the pMOS transistor of transistor circuit T3. The signal S2 inverted by inverter 15 is input to a gate of the pMOS of T2 and nMOS of T3. When S2 is high level, T2 is conductive and T3 is cut off, and when low level, T3 is conductive and T2 is cut off. That is, MUX1 can alternatively output V1 or Vr in response to the control signal S2. Though it is not shown in the figure, multi-plexer MUX2 is structured in the same way as MUX1 and V1 and Vr are connected inversely. Vr and V1 of figure 4 are connected to T2 and T3, respectively, contrary to the construction of Figure 4. Consequently, MUX2 output inversely to MUX1; that is, when MUX1 outputs V1, MUX2 outputs Vr and when MUX1 output Vr, MUX 2 outputs V1. Signal S2 corresponds to spreading code and outputs 1 × V1=V1 to AD1p when S2=1. At this time, S3 is -1 and Vr corresponding 0 is output to AD1m. When S2=-1, Vr corresponding to 0 is output to AD1p. Here, S3=+1 and outputs 1 × V1 = V1to AD1m. Expressing a receiving signal on a timing t as Vin(t) using input signal Vin, and X(t) in formula (1) as Vin(t), formula (1) can be expressed as in formula (2). The Vin(t-i Δ t) is an input voltage held in each sampling and holding circuit, and d( i ) is the signal S to be input to each sampling and holding circuit at a time. The spreading code is given in the predetermined order to the signals held. When a new signal is taken, the oldest signal is substituted by the newest signal. It causes change in relationship between S/H and d(i) , d( i ) is shifted with respect to S/H by the control circuit. When a code shift is not performed, code transfer is performed between successive S/Hs and some errors will be generated due to data transfer. It will be understood that the code shift is effective to prevent the error during data transfer. The accumulation in formula (2) is performed in the addition portions from AD1 to AD3, VH and VL of output voltages of each sampling and holding circuit are accumulated in AD3 and AD2, respectively. This accumulation is not performed directly. S/H are divided into a plurality to groups, outputs VH and VL are accumulated in AD1 by each group. All of the outputs of Adp1 for accumulating VH are input to AD2, and all of the outputs of AD1m for accumulating VL are input to AD3. In Figure 1, six (S/H)s are shown and divided into two groups by three. Generally a spreading code includes from 100 to several hundreds or more bits. (S/H)s are set by the number corresponding to the number of bits. As shown in Figure 5, the addition portion AD1 includes a capacitive coupling CP1 constructed by capacitances C3, C4 and C5 of the number equal to the number of S/H in one group. An output of CP1 is connected to three serial stages of MOS inverters 16, 17 and 18. An output of MOS inverter I3 of the last stage is connected to an input of I6 through a feedback capacitance C6. An output of CP1 is generated at an output of I8 with a good linearity. Assuming input voltages of capacitances C3, C4 and C5 to be V3, V4 and V5, an output V6 of I8 can be expressed by the formula (3). V6=-(C3V3+C4V4+C5V5)/C6 Here, V3, V4 and V5 are voltages referencing the reference voltage Vr. Also it is defined that C3=C4=C5=C6/3. A normalized output of inverted addition value can be obtained as in formula (4). V6=-(V3+V4+V5)/3 By the normalization, the maximum voltage is limited under the supply voltage. An output of the last stage inverter 18 is connected to the ground through a grounded capacitance CG2. An output of the second stage inverter I7 is connected to the supply voltage Vdd and the ground through a pair of balancing resistances RE51 and RE52, respectively. The unstable oscillation of inverted amplifying circuit including feedback line is prevented by the structure. As shown in Figure 6, the addition portion AD2 includes a capacitive coupling CP2 which includes capacitances C7 and C8 of corresponding number to the number of the addition portions AD1. The output of CP2 is connected to three stages serial MOS inverters 19, I10 and I11. An output of MOS inverter I11 of the last stage is connected to an input of 19 through a feedback capacitance C9. An output of CP2 is generated at an output of I11 with a good linearity. Assuming input voltages of capacitances C7 and C8 to be V7 and V8, an output V9of I11 can be expressed by the formula (5). V9=-(C7V7+C8V8)/C9 Here, V7 and V8 are voltages referencing the reference voltage Vr. C7=C8=C9/2. Then, a normalized output of an inverted addition is obtained as in formula (6). V6=-(V7+V8)/2 By the normalization, the maximum voltage is limited under the supply voltage. An output of the last stage inverter I11 is connected to the ground through grounded capacitance CG3. An output of the second stage inverter I10 is connected to the supply voltage Vdd and the ground through a pair of balancing resistances RE61 and RE62. The unstable oscillation of inverted amplifying circuit including feedback line is prevented. As shown in Figure 7, addition portion AD3 includes capacitive coupling CP3 which includes capacitances C10, C11 and C12 of the number corresponding to the number of connected AD1s and AD2s, and an output of CP3 is connected to three stages serial MOS inverters I12, I13 and I14. An output of MOS inverter 114 of the last stage is connected to an input of I12 through a feedback capacitance C13. An output of CP3 is generated at an output of I14 with a good linearity. Assuming input voltages of capacitances C10, C11 and C12 (the voltage referencing Vr) to be V10, V11 and V12, an output V13 of I14 (the voltage referencing Vr) can be expressed by the formula (7) V13=-(C10V10+C11V11+C12V12)/C13 It is defined that C10=C11=C12/2=C13/2. A normalized output of inverted addition value can be obtained as in formula (8). V13=-(V10+V11+2V12)/2 Here, the weight of C12 is defined as the twice of C10 and C11 so as to cancel the influence of the normalization by AD2 and to agree to unnormalized V10 and V11. By the normalization, the maximum voltage is limited under the supply voltage. An output of the last stage inverter I14 is connected to the ground through a grounded capacitance CG4. An output of the second stage inverter I13 is connected to the supply voltage Vdd and the ground through a pair of balancing resistances RE71 and RE72, respectively. The unstable oscillation is prevented. Generalizing the operations of AD1, AD2 and AD3, the output V9 of AD2 is as in formula (9), in which the signal S2 for i-th S/H is assumed to be S2(i) and the inverted signal of it is assumed to be IS2(i). For obtaining V13 of the output of AD3, the operations in the formulas (10) and (11) are performed. Here, it is defined as below. S2(i)=1 or -1 when S2(i)=1, IS2(i)=-1 when S2(i)=-1, IS2(i)=1 The reference voltage Vr is generated by a reference voltage generating circuit Vref in Figure 8. The reference voltage generating circuit includes three stages serial inverters I15, I16 and I17, and an output of the last stage is fed back to the first stage input. Similar to the inverted amplifying portions, unstable oscillation is prevented by a grounded capacitance CG5 and balancing resistances RE81 and RE82. The output of the reference voltage circuit converges to a stable point on which an input and output voltages are equal to each other, and any reference voltage can be generated by changing the threshold of each inverter. Generally, in many cases, it is set that Vr=Vdd/2 in order to keep dynamic range enough large in both directions of plus an minus. Here, Vdd is the supply voltage of MOS inverter. Concerning to the matched filter circuit above, the size of the circuit is largely reduced compared with a digital one, and processing speed is high because of parallel addition. As the inputs and outputs of the sampling and holding circuits and addition portions are all voltage signals, consuming electric power is low. The accuracy of an output of an addition portion depends on the dispersion in characteristics of MOS inverters and in capacity ratio of capacitances. The dispersion of inverters can be minimized by placing them closely to one another. The accuracy of the capacity ratio of a capacitance can be improved by dispersively connecting a plurality of unit capacitances as shown in Figure 9. In the Figure, lines from S1 to S16 are provided for connecting unit capacitances of 16 numbers of capacitances. L1 and L2 are connected to every other unit capacitances among unit capacitances aligned on one straight line. In the same way, L3 and L4 are connected to every other unit capacitances among one alignment of capacitances. It is possible to control the dispersion of a pattern on forming a unit capacitance by placing unused unit capacitances around the arrangement. As mentioned above, an input signal is sampled and held as an analog signal along the time sequence and classified into "1" and "-I". The classified signals are added in parallel by capacitive couplings in a matched filter circuit. Therefore, it is possible to realize a small size and low electric power of matched filter circuit.

Claims: A matched filter circuit comprising: a plurality of sampling and holding circuits (S/H) comprising: a switch (SW) connected to an input voltage (Vin), a first capacitance (C1) connected to an output of said switch (SW), a first inverted amplifying portion (11-13) comprised of an odd number of stages of MOS inverters connected to said first capacitance (C1), a first feedback capacitance (C2) for connecting the output of said first inverted amplifying portion (11-13) to an input thereof, a first multiplexer (MUX2) for alternatively outputting an output of said first inverted amplifying portion (I1-I3) or a reference voltage (Vr), a second multiplexer (MUX1) for alternatively outputting said output of said first inverted amplifying portion (11-13) or said reference voltage (Vr) in inverse relationship to said output from said first multiplexer (MUX2); a first addition portion (AD2) comprising: a plurality of second capacitances (C7, C8) each being coupled to an output of said first multiplexer (MUX2) of each said sampling and holding circuits (S/H), the outputs of said second capacitances (C7, C8) being connected with one another as a common output; a second inverted amplifying portion (I9-I11) comprised of an odd number of stages of MOS inverters connected to said common output of said second capacitances (C7, C8), a second feedback capacitance (C9) for connecting the output of said second inverted amplifying portion (I9-I11) to its input; a second addition portion (AD3) comprising: a plurality of third capacitances (C10-C12) each being coupled to an output of said second multiplexer (MUX1) of each said sampling and holding circuits and an output of said first addition portion (AD2), the outputs of said third capacitances (C10-C12) being connected with one another as a common output, a third inverted amplifying portion (112-114) having an odd number of stages of MOS inverters connected to said common output of said third capacitances (C10-C12), a third feedback capacitance (C13) for connecting the output of said third inverted amplifying portion (112-114) to its input, a control circuit (CTRL) for closing said switch (SW) of one of said sampling and holding circuits (S/H), opening the other switches and switching said first and second multiplexer of each said sampling and holding circuits by a predetermined combination. A matched filter circuit as claimed in claim 1, wherein said sampling and holding circuits (S/H) are classified into a plurality of groups, said filter circuit further comprising: a third addition portion (AD1m) to which said outputs of said first multiplexer (MUX2) of one said groups are connected, the outputs of said third addition portion (AD1m) of all of said groups being inputted to said second addition portion (AD3), said third addition portion comprising a plurality of fourth capacitances (C3-C5) each connected with one of said output of said first multiplexer (MUX2), a fourth inverted amplifying portion (16-18) having an odd number of stages of MOS inverters commonly receiving said outputs of said fourth capacitances (C3-C5) and a fourth feedback capacitance (C6) connecting an output of said fourth inverted amplifying portion to its input, a fourth addition portion (AD1p) to which said outputs of said second multiplexer (MUX1) of one of said groups are connected, outputs of said fourth addition portion of all of said groups being inputted to said first addition portion (AD2), said fourth addition portion comprising a plurality of fifth capacitances (C3-C5) each connected with one of said output of said second multiplexer, a fifth inverted amplifying portion (16-18) having an odd number of stages of MOS inverters commonly receiving said outputs of said fifth capacitances and a fifth feedback capacitance (C6) connecting an output of said fifth inverted amplifying portion to its input. The matched filter circuit according to claim 1 or 2, wherein said reference voltage is generated by a reference voltage generating circuit comprising a sixth inverted amplifying portion (115-117) whereby an output of said sixth inverted amplifying portion is coupled with its input. The matched filter circuit according to claims 1, 2 or 3, comprising a grounded capacitance (CG1-CG5) between an output and the ground, and a pair of balancing resistances (RE21, RE22, RE51, RE52, RE61, RE62, RE71, RE72, RE81, RE82) connected to an output of one of said MOS inverters other than that of the last stage, a supply voltage (Vdd) and the ground are connected to one of said balancing resistances, respectively. The matched filter circuit according to claim 3, wherein a threshold voltage of said MOS inverter is determined so that said reference voltage (Vr) is the half of the supply voltage (Vdd). The matched filter circuit according to one of claims 1 to 5 wherein said sampling and holding circuits (S/H) are controlled so as to hold said input voltage circulatingly in the predetermined combination.

Inventors: LIN SHENGMIN, MOTOHASHI KAZUNORI, QUIN XIAOLING, SHOU GUOLIANG, TAKATORI SUNAO, YAMAMOTO MAKOTO, ZHOU CHANGMING, LIN, SHENGMIN, MOTOHASHI, KAZUNORI, QUIN, XIAOLING, SHOU, GUOLIANG, TAKATORI, SUNAO, YAMAMOTO, MAKOTO, ZHOU, CHANGMING
Applicants: SHARP KK, YOZAN INC, SHARP KABUSHIKI KAISHA, YOZAN INC.
Application year: 1996
Main classification: H03H11
IPC codes: H03H17, H03H19, H03M1, H03M3, H03H11, H04B1