Method of fabricating flat field emission display screens and flat screen obtained thereby

Abstract: The microtips (14) of charge emitting material, which define the cathode of the flat FED screen and face the grid of the screen, are tubular and have portions (16) with a small radius of curvature. The microtips (14) are obtained by forming openings (10) in the dielectric layer (6) separating the cathode connection layer (3, 5) from the grid layer (8), depositing a conducting material layer (11, 12) to cover the walls of the openings, and anisotropically etching the layer of conducting material to remove it, i.a., from the upper edge of the portion covering the walls, so as to form inwardly-inclined surfaces (15) with emitting tips (16). Subsequently, the portions of the dielectric layer surrounding the microtips are removed (18).

Description: The present invention relates to a method of fabricating flat FED (Field Emission Display) screens, and to a flat screen obtained thereby. As is known, the continual trend towards portable electronic equipment (laptop computers, personal organizers, pocket TVs, electronic games) has brought about an enormous demand for small monochromatic or colour screens of reduced depth, light weight and low dissipation. As requirements in terms of size and depth cannot be met using traditional cathode tubes, various techniques are currently being studied, the most interesting of which - besides LCD (Liquid Crystal Display) technology - for the particular application in question is the FED technique, which affords the advantages of low dissipation, same colour quality as CRTs, and visibility from any angle. The FED technique (object, for example, of US Patents 3,665,241; 3,755,704; 3,812,559; 5,064,369 in the name of C.A. Spindt, and 3,875,442 in the name of K. Wasa et al.) is similar to the conventional CRT technique, in that light is emitted by exciting phosphors deposited on a glass screen by vacuum-accelerated electron bombardment. The main difference between the two techniques lies in the method of generating and controlling the electron beam: the conventional CRT technique employs a single cathode (or cathode per colour), and the electron beam is controlled by electric fields to scan the whole screen; whereas the FED technique employs a number of cathodes comprising microtips, each controlled by a grid, arranged parallel to and at a small distance from the screen, and the screen is scanned by sequentially exciting the microtips by an appropriate combination of grid and cathode voltages. The cathode connections, forming the columns of a matrix, comprise a first low-resistivity conducting layer in the form of strips; over the first conducting layer, and isolated electrically by a dielectric layer, a second conducting layer forming the grid of the system is provided in the form of parallel strips, perpendicular to the former and forming the rows of the matrix; the second conducting layer (grid) and the dielectric layer comprise openings extending up to the first conducting layer and accommodating microtips electrically contacting the first conducting layer. Electron emission occurs through the microtips, which are roughly conical to exploit intensification of the electric field at the tips and so reduce the barrier between the tip material (e.g. metal) and the vacuum. As electron emission, however, substantially depends on the small radius of curvature of the emitter, efficient emission is theoretically also possible using prism- or double-cone-shaped electrodes as referred to in literature. Methods of forming the cathode and microtips are described, for example, in the above Spindt patents and in US Patents 4,857,161; 4,940,916 and 5,194,780. More specifically, the method described in US-A-4,857,161 comprises the following steps: 1. the first conducting layer (cathode) is deposited on an insulating substrate (glass); 2. the first conducting layer is masked and etched to form the columns of the matrix (cathode connections); 3. the dielectric layer is deposited; 4. the second conducting layer (grid) is deposited; 5. in the second conducting layer and the dielectric layer, circular openings of 1.2-1.5 mm in diameter and extending up to the first conducting layer are defined by masking; 6. over the structure so formed, a layer of nickel is deposited by high angle sputtering to prevent the nickel from entering the openings; 7. a metal (e.g. molybdenum) is then deposited by sputtering; the metal, at the openings, directly contacts the first conducting layer to form the tips. This step is performed by vertical or almost vertical sputtering, and the shielding effect of the walls of the openings and the nickel layer causes the deposited metal, at the bottom of the openings, to assume a conical shape with the tip roughly level with the grid electrode; 8. the nickel layer over the second conducting layer is removed by electrochemical etching to lift off the metal deposited over the grid without damaging the conical tips formed in the openings; 9. peripheral portions of the second conducting layer and of the dielectric layer are etched to free the ends of the cathode connections; 10. the second conducting layer is masked and etched to form the rows of the matrix (grid connections); 11. a coating of conducting material operating as an anode is deposited on a second glass substrate; a cathodoluminescent layer is deposited; and the second substrate is placed over the grid, with spacers arranged randomly between the cathodoluminescent layer and the grid connections. The above method presents the following drawbacks. High-angle nickel deposition in step 6 is extremely difficult on account of the considerable size (about 27x36 cm) of the substrates of flat screens of the type in question; the need to ensure even deposition over the entire substrate; and the fact that the substrate is rotated during deposition to ensure isotropic coverage. As such, the above step requires the use of specially designed equipment, which is complex, bulky and expensive. US-A-5 315 206 discloses a number of embodiments of an electron emission elements integrated substrate made from an insulating substrate wherein holes are formed; on one side of the substrate an electron emission electrode is formed by rotating the substrate at an angle; an insulating layer is formed on the electron emission electrode; then the substrate is turned over upside down for forming electron drawing electrodes, in case with the substrate inclined by an angle and rotated. Thus, the manufacturing method is complex and costly and requires a number of depositions at an angle. It is an object of the present invention to provide a fabrication method enabling formation of the microtips using common microelectronic techniques and facilities and therefore at much lower cost, which provides for greater reliability of the results achievable. According to the present invention, there are provided a method of fabricating flat FED screens, and a flat screen obtained thereby, as claimed respectively in Claims 1 and 15. In practice, according to the invention, tubular microtips featuring portions with a small radius of curvature are obtained by forming openings in the dielectric layer, depositing a layer of conducting material covering the walls of the openings, and anisotropically etching the layer of conducting material to remove it, among other places, from the upper edge of the portion covering the walls, and so form tubular microtips with a tapered upper edge. Subsequently, the dielectric layer about the microtips is etched selectively. Two preferred, non-limiting embodiments of the present invention will be described by way of example with reference to the accompanying drawings, in which: Figures 1-5 show cross sections in perspective of a wafer of semiconductor material at various fabrication steps according to a first embodiment; Figures 6-13 show similar cross sections relative to a second embodiment. With reference to Figure 1, to begin with a first conducting layer 3 (e.g. of chromium, molybdenum, aluminium, niobium, tungsten, tungsten silicide, titanium silicide, doped amorphous or monocrystalline silicon) is deposited on a substrate 1 of insulating material (e.g. ceramic or glass); and first conducting layer 3 is then masked and etched to form the columns of the matrix (cathode connections) and obtain the structure shown in Figure 1. Subsequently, a high-resistivity layer 5, e.g. comprising one or more layers of doped silicon, is deposited over layer 3 to limit and better distribute the current in the microtips; a dielectric (e.g. silicon oxide) layer 6 is then deposited to insulate the cathode from the grid conductor; a second conducting layer 8 (e.g. of the same material as first conducting layer 3) is deposited to act as a grid electrode; and, by masking and subsequent etching, openings 10 are defined in second conducting layer 8 and in dielectric layer 6 to form vertical-walled (e.g. circular, 0.8-1.5 µm diameter) wells extending up to high-resistivity layer 5, as shown in Figure 2. Subsequently, a conducting layer 12 for eventually forming the microtips is deposited by CVD. Conducting layer 12 is advantageously of metal, preferably tungsten, which may easily be deposited by CVD from WF 6 , H 2 and SiH 4 at temperatures of around 400-500°C, therefore compatibly even with glass substrates. In this case, after forming openings 10 and before depositing conducting layer 12, a thin layer of titanium/titanium-nitride 11 (shown only in Figure 3 for the sake of simplicity) is preferably deposited by sputtering or CVD to assist deposition and adhesion of conducting layer 12. Alternatively, monocrystalline or amorphous silicon may be used for conducting layer 12. The total thickness of conducting layer 12 (including layer 11, if provided) preferably ranges between 400 and 800 nm, and must be roughly less than half the diameter of openings 10. CVD ensures fairly even coverage of the walls and bottom of circular openings 10. The Figure 3 structure is thus obtained. Subsequently, conducting layer 12 is etched to form the microtips. More specifically, an anisotropic R.I.E. (Reactive Ion Etching) step is performed, e.g. if conducting layer 12 is made of tungsten, in a mixture of SF 6 , Ar and O 2 to remove all the tungsten from the flat surface of the grid electrode (layer 8) and from the bottom of openings 10. By forming the cathode (first conducting layer 3 and resistive layer 5) and the grid electrode (second conducting layer 8) from doped amorphous silicon and conducting layer 12 from tungsten or, in general, materials with a different sensitivity to etching, conducting layer 12 may be etched selectively without damaging layers 3, 5 and 8. As conducting layer 12 is thicker on the walls of openings 10, etching leaves a residue of layer 12 on the walls to form a cylindrical structure with an inward-tapering upper edge, while layer 12 is removed, or almost removed, from the bottom of the openings. In general, the amount of tungsten remaining at the bottom of the openings depends on the ratio between the thickness deposited and the diameter of the opening, and on the amount of etching performed. Given the deposition and etching conditions, the upper edge of the cylindrical structure assumes a high-angle profile forming, with the outer wall of the cylindrical structure, a portion with a small radius of curvature (tip) suitable for emission. Advantageously, etching is continued to achieve a certain amount of overetching, e.g. equal to 20-30% of the basic etching time, both to ensure complete removal of any tungsten residue from second conducting layer 8 and from the bottom of openings 10, and to lower the edge of the cylindrical structure below the level of the grid conductor (second conducting layer 8). This therefore gives the structure shown in Figure 4, in which the cylindrical structures obtained are indicated at 14, the tapered edge below the level of second conducting layer 12 is indicated at 15, and the portion with the small radius of curvature and constituting the emitting surface is indicated at 16. Subsequently, the portions of dielectric layer 6 surrounding cylindrical structures 14 are removed by isotropic etching. For example, if layer 6 is of silicon oxide, etching is performed in a diluted HF solution. Alternatively, isotropic (e.g. indirect plasma) etching may be performed to obtain the Figure 5 structure, which shows cavities 18 formed by isotropic etching in dielectric layer 6. This step is useful for safely eliminating any problems of surface conduction between cylindrical structures 14 (microtips) and second conducting layer 8 (cathode). Fabrication continues with the known steps for forming the grid connections, by masking and etching second conducting layer 8 to form the outer contact areas of the cathode, and to form the anode and luminescent structures. Figures 6-13 show a second slightly more complex embodiment, which provides for better controlling the distance between the upper emitting edge of the microtips and the grid, and so reducing the voltage required to control the screen. In the second embodiment, as already described, first conducting layer 3 is deposited; etching is performed to define the columns of the matrix; and high-resistivity layer 5, dielectric layer 6 and second conducting layer 8 are deposited. At this point, a resist mask 21 (Figure 6) is deposited, and first openings 22 are formed extending only in second conducting layer 8. To this end, selective anisotropic reactive ion etching is performed of the material of layer 8 - which is easily done if, for example, second conducting layer 8 is of amorphous silicon and dielectric layer 6 of silicon oxide - to obtain the structure shown in Figure 6. After removing resist mask 21, a spacing layer 23 is deposited, the preferably dielectric material of which is so selected as to permit selective etching with respect to the material of both second conducting layer 8 (grid conductor) and underlying dielectric layer 6. For example, spacing layer 23 may be made of silicon nitride deposited by CVD, possibly with the assistance of plasma (PECVD) to reduce the deposition temperature. The thickness of spacing layer 23 depends on the diameter of circular openings 22, and may be roughly 200-400 nm, to give the structure shown in Figure 7. Spacing layer 23 is then anisotropically etched by RIE up to second conducting layer 8 and, in openings 22, up to dielectric layer 6 to form spacers 25 on the walls of openings 22 (Figure 8). If the etching of spacing layer 23 poses selectivity problems as regards both the materials of layers 8 and 6, a thin protective layer of silicon oxide (not shown) may be deposited prior to depositing mask 21 for forming openings 22. Using the second conducting layer and spacers 25 as shields, dielectric layer 6 at openings 22 is then anisotropically etched by RIE up to high-resistivity layer 5 to form openings 27 (Figure 9). This is then followed by the steps for forming the microtips, as described with reference to Figures 3 and 4. More specifically, a titanium/titanium nitride layer 28 (shown only in Figure 10 for the sake of simplicity) is preferably first deposited, and then a conducting layer 29 (e.g. of tungsten, Figure 10). Subsequently, layers 28 and 29 are anisotropically etched by RIE to remove them from the surface of second conducting layer 8 and from the bottom of openings 27. In this case, however, in view of the presence of spacers 25, etching time is determined solely by the necessity to remove layers 28, 29 from the surface of second conducting layer 8. This results in the Figure 11 structure in which the microtips (cylindrical structures 30) show a tapered edge 31 with a portion 32 with a small radius of curvature, as in the first embodiment. Spacers 25 are then removed by anisotropic etching, e.g. in a solution of hot phosphoric acid or in indirect plasma (Figure 12). As described with reference to Figure 5, portions of dielectric layer 6 surrounding cylindrical structures 30 are removed by isotropic etching to obtain cavities 18 (Figure 13). Second conducting layer 8 is masked and etched to form the rows of the matrix (grid connections), and the final operations performed to obtain the screen. The advantages of the method described are as follows. Firstly, it provides for forming cathode microtips using known techniques and standard microelectronic facilities, and hence at must lower cost as compared with techniques so far proposed for FED screens. Moreover, using known techniques ensures a high degree of controllability and reliability of the method and results. The steps required also give good results in the case of large-size screens. The emission efficiency of the resulting screen is good, due to the extensive high-angle emission surface of the microtips, which facilitates electron emission. The method described is fairly insensitive to the diameter of the openings or the thickness of the deposited layers, and, especially in the second embodiment, provides for accurately controlling the distance between the grid and the microtips, thus reducing the voltages required to control the screen and providing for more uniform emission. Clearly, changes may be made to the method and screen as described and illustrated herein without, however, departing from the scope of the present invention. In particular, materials other than those described may advantageously be used. In particular, an organic material (polyimide) may be used as a dielectric and etched in oxygen plasma. The conducting layers (cathode and grid) may be made of different material from the microtips (e.g. the conducting layers of tungsten, tungsten silicide, chromium or niobium, the microtips of amorphous silicon) or of the same material (e.g. doped amorphous silicon), using a protective layer such as silicon oxide for the second conductor, and selectively covering the microtips with a layer of metal, such as tungsten. Moreover, the two conducting layers may be made of different materials, e.g. selected from those indicated.

Claims: A method of fabricating flat field emission display (FED) screens, comprising the steps of: forming a first conducting layer (3, 5); forming an insulating layer (6) over said first conducting layer; forming a second conducting layer (8) over said insulating layer; forming openings (10; 27) having walls in said second conducting layer and in said insulating layer; characterized by the further steps of: covering said walls of said openings with portions (14; 30) of a charge emitting material; and anisotropically etching said portions of charge emitting material so as to form emitting structures. A method as claimed in Claim 1, characterized in that said step of anisotropically etching is followed by a step of removing selective regions of said insulating layer (6) surrounding said portions (14; 30) of charge emitting material. A method as claimed in Claim 2, characterized in that said step of removing comprises the step of isotropically etching said insulating layer (6) selectively with respect to said first and second conducting layer (3, 5, 8) and said portions (14; 30) of charge emitting material. A method as claimed in any one of the foregoing Claims, characterized in that said step of covering comprises the steps of forming a conducting material layer (12; 29) over said insulating layer (6) and in said openings (10; 27), and said step of anisotropically etching comprises the step of removing portions of said conducting material layer from the surface of said second conducting layer (8), from the bottom of said openings, and partly from an upper edge of said portions (14; 30) of charge emitting material to form an upper surface (15; 31) of said portions (14; 30) of charge emitting material which is inclined in relation to said walls of said openings, and portions (16; 32) with a small radius of curvature. A method as claimed in Claim 4, characterized in that said step of forming a conducting material layer (12; 29) is performed by chemical vapor deposition. A method as claimed in Claim 4 or 5, characterized in that said conducting material is selected from the group comprising tungsten, doped monocrystalline silicon and doped amorphous silicon. A method as claimed in any one of the foregoing Claims, characterized in that said first and second conducting layer (3, 8) are formed from a material selected from the group comprising chromium, molybdenum, aluminium, niobium, tungsten, tungsten silicide, titanium silicide, and doped amorphous and monocrystalline silicon. A method as claimed in any one of the foregoing Claims from 4 to 7, characterized in that , prior to said step of forming a conducting material layer (12; 29), an adhesion layer (11; 28) is deposited. A method as claimed in Claim 8, characterized in that said conducting material is tungsten, and said adhesion layer is of titanium/titanium nitride. A method as claimed in any one of the foregoing Claims from 4 to 9, characterized in that said step of anisotropically etching comprises an overetching step to reduce the height of said portions (14; 30) of charge emitting material. A method as claimed in any one of the foregoing Claims, characterized in that said step of forming openings (27) comprises the step of forming first cavities (22) in said second conducting layer, said first cavities defining lateral walls; forming spacers (25) surrounding said lateral walls of said first cavities; and forming, in said insulating layer (6), second cavities masked by said spacers. A method as claimed in Claim 11, characterized in that said step of forming spacers (25) comprises the step of forming a spacing layer (23) over said second conducting layer (8) and in said first cavities (22), and anisotropically etching said spacing layer. A method as claimed in Claim 12, characterized in that said spacing layer (23) is of nitride. A method as claimed in any one of the foregoing Claims from 11 to 13, characterized in that said step of anisotropically etching said spacing layer (23) is followed by a step of removing said spacers (25). A flat field emission display (FED) screen comprising a cathode region (3, 5); an insulating region (6) over said cathode region; a grid region (8) over said insulating region; a number of openings (18) in said insulating region; and a number of emitting structures (14; 30) in said openings; said emitting structures being connected electrically to said cathode region (3, 5) and facing and being spaced from said grid region (8); characterized in that said emitting structures (14; 30) are tubular with an edge surface (15; 31) facing said grid region; said edge surface being inclined inwards and having a portion (16; 32) with a small radius of curvature. A screen as claimed in Claim 15, characterized in that said emitting structures (14; 30) are cylindrical.

Inventors: BALDI LIVIO, MARANGON MARIA SANTINA, BALDI, LIVIO, MARANGON, MARIA SANTINA
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1996
Main classification: H01J9
IPC codes: H01J31, H01J9, H01L29, H01J29, H01J1