Liquid crystal display driver with improved data transfer

Abstract: An apparatus for supplying data to a plurality of source drivers (13, 15, 17, 19) classified into a plurality of groups, each of the source drivers driving a part of a LCD panel (21), comprising: a plurality of memory blocks (7, 9), each block supplying data to one of the groups of the source driver (13, 15, 17, 19) and allowing itself to be read out and be written into simultaneously; control means (5) for switching the memory blocks (7, 9) to be written when data of pixels drawn by one source driver when one line in the LCD panel is drawn written from the frame buffer (1) into one memory block (7, 9); and wherein while writing data into the memory block (7, 9), the written data is read from the memory block (7, 9) at a lower speed than the writing, simultaneously.

Description: Field of the Invention The present invention relates to a liquid crystal display apparatus; and in particular, to a method and device for supplying data to a data driver for a liquid crystal display panel. Background art The resolution of the display region of a liquid crystal display apparatus has recently been increasing; compared to conventional video graphic arrays (VGA) that have allowed display with 640 × 480 pixels, super VGAs (SVGAs) or extended graphic arrays (XGAs) allow display with 800 × 600 or 1024 × 768 pixels. with such a high resolution display, a source driver for supplying data to each pixel has a large operating frequency or is very expensive, or a new source driver must be developed. Higher operating frequency also prevents EMC regulations from being met. Furthermore, since an increase in resolution requires the size of the display region to be increased, the length of a signal transmission path and the impedance are accordingly increased, thereby preventing accurate signals from being transmitted at a high speed. Attempts have been made to reduce the operating frequency of the source driver. For example, Japanese Patent Unexamined Published Application No. 5-100632 discloses a method for writing a data signal to four memories and then supplying the data from these memories to four source drivers. Since four source drivers drive a single liquid crystal display panel, the operation frequency of a single source driver is one-fourth of a conventional source driver. The capacity of each of these memories, however, must be twice the number of those pixels for which a source driver is responsible when it drives a single line. That is, a single memory stores data corresponding to those pixels contained in a single line for which the source driver is responsible. This data is subsequently read from the memory, while the data in the next line is written to that memory. A similar method is described in Japanese Patent Unexamined Published Application No. 5-181431. Japanese Patent Unexamined Published Application No. 5-232898 also describes a method for providing four memories for two data drive circuits and using a switch to switch these memories to obtain similar effects. European Patent Application 0 457 329 discloses a liquid crystal display (LCD) including apparatus for supplying data to a plurality of source drivers, a plurality of memory blocks, each memory block supplying data to only one source driver and arranged to be read out and be written into simultaneously and a control part for writing into each memory block data for the source drivers associated with that memory block. European Patent Application 0 368 572 discloses an LCD driver having memory blocks supplying data to a group of source drivers, each input of the source driver being directly connected to the output of one memory block. Although the above conventional techniques indeed enable the operation frequency of the source driver to be reduced, the resultant increase in the number of source drivers may require the total capacities of the memories to be increased, or the control circuit may be complicated due to the use of the switch in the case of the method described in Japanese Patent Unexamined Published Application No. 5-232898. It is thus an object of this invention to reduce the operating frequency of source drivers using memories of small capacities. It is another object of this invention to reduce the operating frequency of source drivers using a simple circuit. Disclosure of the invention To achieve the above objects, this invention provides an apparatus for supplying data to a plurality of source drivers, the source drivers being divided into a plurality of groups, each of said source drivers driving a part of a LCD panel, comprising: a plurality of memory blocks, the output of each of said memory blocks being linked to the data inputs of a respective one of said groups of said source drivers, wherein each group has one common data input linked to the data inputs of all source drivers of said group and wherein the memory blocks are capable of being read out and of being written into simultaneously; and control means arranged to write into each memory block data for said source drivers of which the memory block is in charge, wherein the control means is arranged to switch the writing of data between said memory blocks interleavedly, such that after data corresponding to a first source driver is supplied to one of said plurality of memory blocks associated with said source driver, next data corresponding to a source driver linked to another of said memory blocks is supplied to the corresponding another one of said plurality of memory blocks. The invention is characterised in that: the capacity of each of said memory blocks is smaller than the maximum number of column outputs of each of said source drivers with which the memory blocks are linked. This configuration enables the reduction of the total capacity of the memory blocks and the drive frequency of the source drivers. In addition, if each number of the above groups and the memory blocks is n, a capacity of each memory block is (n-1)/n or less of a number of pixels of which one source driver is in charge when driving a single line, and a reading speed may be 1/N or more of the writing speed. The (n) may be 2. In this case, the total memory capacity corresponds to a single source driver, and a single memory block corresponds to half the source driver. The memory block may be a FIFO memory, but may be anything as long as it allows itself to be read out and be written into simultaneously. Brief Description of the Drawings The invention will now be described, by way of example only, with reference to the accompanying drawings, in which: Figure 1 is a block diagram showing an apparatus according to this invention; Figure 2 is a chart describing the operation of a FIFO-O 9 and a FIFO-E 7; and Figure 3 is a chart describing the amount of memory consumed when three FIFOs are used. Detailed Description of the Invention Source drivers for a liquid crystal display apparatus are classified into a plurality of sets. A plurality of memory blocks are provided for each of these sets of source drivers. Data corresponding to those pixels for which a source driver is responsible when it drives a single line is written to a single memory block, and the written data is then immediately read from the memory block and supplied to the source driver. Once the data has been written to the single memory block, the writing is switched to another memory block, the above operation is repeated. The reading, however, is carried out at a lower speed than the writing so that while data is being written to a memory block, all of the data that has been written will have been supplied to the source driver. Embodiment Figure 1 shows one embodiment of this invention. An image memory 1 stores data to be displayed in a digital form, and is connected to a memory control part 3. The memory control part 3 reads data stored in the image memory 1 in the order that the data is displayed on a liquid crystal display panel 21, and is connected to a FIFO-E 7 and a FIFO-O 9. The order of display refers to the direction from the left to the right end of the panel as shown by the arrow in the liquid crystal display panel 21. The image memory 1 and the memory control part 3 are contained within a computer system. The FIFO-E 7 and FIFO-O 9 temporarily store data read by the memory control part 3, and are contained in a liquid crystal display apparatus. The FIFO-E 7 is connected to source drivers 15, 19, and is controlled by a control part 5. FIFO-O 9 is connected to source drivers 13, 17, and is controlled under a control section 5. The control section 5 controls the source drivers 13, 15, 17, and 19 and a gate driver 11. The source drivers 13, 15, 17, and 19 each drive one fourth of the liquid crystal display panel 21. The operation of this apparatus is described below. As described above, the memory control part 3 reads data stored in the image memory 1 in the order described above. The control part 5 enables writes to the FIFO-O 9, and data for those pixels for which a source driver is responsible when it drives a single line is written to the FIFO-O 9. First, the data for the source driver 13 is written to the FIFO-O 9. The control part 5, however, simultaneously enables reads from the FIFO-O 9 to start reading the written data therefrom. The control part 5 uses a control line to cause the source driver 13 to receive the data. Once the write to the FIFO-O 9 has been finished, the control part 5 stops enabling writes to the FIFO-O 9, and then enables writes to the FIFO-E 7. The data for the source driver 15 is written to the FIFO-E 7. The control part 5 also simultaneously enables reads from the FIFO-E 7 to start reading the written data therefrom. The control part 5 uses the control line to cause the source driver 15 to receive the data. The control part 5 subsequently enables writes to the FIFO-O 9 to enable the data for the source driver 17 to be written to the FIFO-O 9. It simultaneously enables reads from the FIFO-O 9 to read the written data therefrom. The control part 5 also uses the control line to cause the source driver 17 to receive the data. Once the write to the FIFO-O 9 has been finished, the control part 5 stops enabling writes to the FIFO-O 9, and then enables writes to the FIFO-E 7. The data for the source driver 19 is then written to the FIFO-E 7. The control part 5 also simultaneously enables reads from the FIFO-E 7 to start reading the written data therefrom. It uses the control line to cause the source driver 19 to receive the data. The same operation is continuously repeated. Each source driver converts digital signals into analog signals, and outputs the signals to a source line to which its output is directed. The gate driver 11 activates a gate line with an appropriate timing so as to drive the liquid crystal in the liquid crystal display panel using the analog signals output to the source line. The required capacities of FIFOs can thus be reduced because reads from the FIFO-O and FIFO-E are finished while a write to another FIFO is being executed. This is shown in Figure 2. It is assumed here that the speed at which data is written to a FIFO is twice the speed at which data is read from a FIFO. Figure 2(a) shows writes to and reads from the FIFO-O 9. Although a write to the FIFO-O 9 and a read from the FIFO-O 9 are simultaneously carried out, the amount of memory consumed increases over the period of time (t) within the period of time 2t during which the data for the source driver 13 is processed because the writing speed is twice the reading speed. Since the read and the write are executed at the same time, however, the required memory capacity is reduced to half compared to the case in which no read is executed. Between points of time (t) and 2t, the data stored in the FIFO-O 9 is read to reduce to zero the amount of memory used in the FIFO-O 9. Figure 2(b) shows writes to and reads from the FIFO-E 7. Between points of time (t) and 2t, a write to the FIFO-E 7 and a read therefrom are executed simultaneously, and the writing speed is twice the reading speed. Thus, during this period of time when the data for the driver 15 is processed, the amount of memory used in the FIFO-E 7 increases. Similarly, the memory capacity used is only half the amount of data corresponding to those pixels for which the driver is responsible when it drives a single line. Between points of time 2t and 3t, only reads from the FIFO-E 7 are carried out to reduce to zero the amount of memory used in the FIFO-E 7. Referencing Figure 2(a) again, the data for the driver 17 is written and read between points of time 2t and 3t. Between points of time 3t and 4t, the data written to the FIFO-O 9 is read out. Returning to Figure 2(b), the data for the driver 19 is written and read between points of time 3t and 4t. Between points of time 4t and 5t, the data written to the FIFO-O 9 is read out. This configuration enables a single line of data to be written to each source driver at half the maximum writing speed. Although this writing speed can be somewhat increased, the operating frequency of the source driver is preferably as low as possible, and this apparatus enables the operating speed of the source driver to be reduced. Even in the case of two FIFOs, the required memory capacity is equal to only the amount of data for those pixels for which a single driver is responsible when it drives a single line, thereby enabling costs to be reduced. Although this invention has been described in conjunction with the case of two FIFOs, it is also applicable to three or more FIFOs. For example, the use of three FIFOs provides a reading speed that is one-third of the maximum writing speed. The total memory capacity of the FIFOs, however, is twice the amount of data for those pixels for which the driver is responsible when it drives a single line (two-thirds of that amount for a single FIFO). Such a memory usage is shown in Figure 3. As described above, by writing data to a FIFO and then immediately reading the written data therefrom, both the memory capacity of the FIFO and the drive frequency of a source driver can be reduced. If, however, the drive frequency of the source driver is not significantly reduced, this invention can be implemented with a smaller memory capacity. For example, in Figure 2, if the reading speed is higher than half the writing speed, the peak of the amount of memory used in a FIFO becomes lower and this amount decreases to zero before point of time 2t. In addition, although this implementation has been described in conjunction with the use of a single bus for inputting data to each FIFO and the write to the FIFO-O 9 and the write to the FIFO-E 7 are thus executed at different points of time, different pieces of data for respective FIFOs may be supplied to different buses. Figure 1 separately shows the configurations of the computer system and the liquid crystal display apparatus, this boundary between the computer system and the liquid crystal display apparatus has arbitrarily been set, and it can be assumed that there is no boundary therebetween. That is, it can be assumed that all the components reside in the computer system.

Claims: An apparatus for supplying data to a plurality of source drivers (13 15, 17, 19), the source drivers being divided into a plurality of groups, each of said source drivers driving a part of a LCD panel (21), comprising: a plurality of memory blocks (7, 9), the output of each of said memory blocks being linked to the data inputs of a respective one of said groups of said source drivers, wherein each group has one common data input linked to the data inputs of all source drivers of said group and wherein the memory blocks are capable of being read out and of being written into simultaneously; and control means (5) arranged to write into each memory block data for said source drivers of which the memory block is in charge; wherein the control means (5) is arranged to switch the writing of data between said memory blocks (7, 9) interleavedly, such that after data corresponding to a first source driver (15, 19) is supplied to one (7) of said plurality of memory blocks associated with said source driver (15, 19), next data corresponding to a source driver linked to another (9) of said memory blocks is supplied to the corresponding another one of said plurality of memory blocks (9); and characterised in that : the capacity of each of said memory blocks (7, 9) is smaller than the maximum number of column outputs of each of said source drivers (13, 15, 17, 19) with which the memory blocks are linked. An apparatus as claimed in claim 1, wherein the number of groups of source drivers and the number of said memory blocks (7, 9) is n, a capacity of each said memory block is (n-1)/n or less of the number of column outputs of each of the source drivers (13, 15, 17, 19), and a reading speed is 1/n or more of the writing speed. An apparatus as claimed in claim 2, wherein said n is 2. An apparatus as claimed in any one of claim 1 to claim 3, wherein said memory block (7, 9) is a FIFO memory. A liquid crystal display apparatus, comprising: a LCD panel (21) ; a plurality of source drivers (13, 15, 17, 19) being divided into a plurality of groups, wherein each group has one common data input linked to the data inputs of all source drivers of said group, each of said source drivers driving a part of the LCD panel; and apparatus for supplying data to the LCD panel, as claimed in any one of claim 1 to claim 4.

Inventors: NISHI SATORU, YAMASHITA HIROSHI, YOSHIKAWA HIROSHI, NISHI, SATORU, YAMASHITA, HIROSHI, YOSHIKAWA, HIROSHI
Applicants: IBM, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1996
Main classification: G09G3
IPC codes: G09G3, H04N5