Input structure, in particular for analog or digital associative memories

Abstract: An input structure (1) for associative memories, including an array of elementary cells (2), a number of input lines (20), a number of output lines (30), a number of address lines (40), and a number of enabling lines (50). Each elementary cell (2) is formed by a D type latch (3) having a data input connected to one of the address lines (40) and an enabling input connected to one of the enabling lines (50), and by a switch (4) connected between an input line and an output line, and having a control input connected to the output of a respective latch to selectively connect the respective input line (20) and output line (30) according to the data stored in the latch.

Description: The present invention relates to an input structure, in particular for analog or digital associative memories. As is known, for performing complex processing functions, associative memories with cells capable of memorizing a number of analog or digital multibit values are currently being studied, and for which use is advantageously made of nonvolatile floating-gate cells, particularly flash-EEPROMs, in which the value to be memorized is related to the threshold voltage of the cell. To read the cells, memorize the analog data and perform the processing operations, the cells must therefore be supplied through a specific input circuit with a number of appropriately memorized analog voltages. According to one known solution (Patent US-A-4,232,302), the input circuit comprises a sample-and-hold circuit having one input, N outputs and N+1 temporary storage paths; and a control circuit provides for cyclically connecting the input to the temporary storage paths to load all the analog input values sequentially on to the temporary storage paths and supply them cyclically to the output. In view of the time taken to load the analog voltages and supply them to the output, the above circuit is unsuitable for applications involving the storage and/or reading of a large number of multilevel analog or digital signals. It is an object of the present invention to provide a multiple-output input structure capable of supplying multilevel analog or digital signals to a user device such as an analog or digital associative memory. According to the present invention, there is provided an input structure, in particular for analog or digital associative memories, as claimed in Claim 1. A preferred, non-limiting embodiment of the present invention will be described by way of example with reference to the accompanying drawings, in which: Figure 1 shows a multilevel multiple-output voltage source featuring the input structure according to the present invention; Figure 2 shows a time plot of a number of signals of the Figure 1 structure. Figure 1 shows a multilevel voltage source having a number of outputs - each supplying an analog or digital voltage selected from a number of values - and featuring the present input structure, indicated as a whole by 1. Structure 1 comprises a switching array in turn comprising K input lines 20; N output lines 30; a number of elementary cells 2 arranged in K rows and N columns; K address lines 40; and N enabling lines 50. Input lines 20 and address lines 40 extend along the rows of matrix 1; output lines 30 and enabling lines 50 extend along the columns of the matrix; address lines 40 present signals ADD1, ADD2...ADDK generated by an address decoder 7; enabling lines 50 present enabling signals CK1, CK2...CKN generated by a gate decoder 8; the input lines present different analog input voltages V1, V2...VK; and the output lines present different analog output voltages O1, O2...ON. Each elementary cell 2 comprises a latch 3 in the form of a D type flip-flop, and a switch 4. Each latch 3 has a data input D connected to one of the address lines; an enabling input CK connected to one of enabling lines 50; and an output Q. All the latches 3 of cells 2 in the same row are connected to the same address line 40; all the latches 3 of cells 2 in the same column are connected to the same enabling line 50; and the output Q of each latch is connected to the control input of a respective switch 4. Switches 4 (e.g. comprising CMOS devices for ensuring a high dynamic range) have a first terminal connected to input lines 20, and a second terminal connected to output lines 30. More specifically, the first terminals of switches 4 of cells 2 in the same row are connected to the same input line 20, and the second terminals of switches 4 of cells 2 in the same column are connected to the same output line 30. As shown in Figure 1, input lines 20 are connected to a programmable multilevel voltage source 9 comprising a number of source circuits 10 - each for generating a different programmable analog voltage and formed, for example, as described in a co-pending patent application filed concurrently and entitled "Programmable reference voltage source, particularly for analog memories" - and supply analog input voltages V1, V2...VK; and output lines 30 are connected to an associative memory 15 of any known type. Address decoder 7 is formed in known manner, and comprises an input 11 supplied with a digital value specifying which of the K address lines is to assume a predetermined logic state (e.g. "1"). Gate decoder 8 is also formed in known manner, and comprises an input 12 supplied with a digital value specifying which of the N enabling lines is to assume a predetermined logic state (e.g. "1"); and an input 13 receiving clock pulses CKK. In structure 1, when one of analog input voltages V1-VK is to be supplied to one or more of output lines 30, address decoder 7 is supplied with the digital address of the row of cells 2 connected to the input line 20 of the required voltage, and switches the corresponding address signal to logic level "1". Gate decoder 8 is supplied with the digital address of the column/s of cells 2 connected to the output line/s 30 to be supplied with the required voltage, and, on receiving clock pulse CKK, supplies a "1" to the corresponding enabling line/s 50. The latch/es 3 receiving two "1" at inputs D and CK switch the corresponding output Q to "1", thus closing the corresponding switch 4 and connecting the input line 20 of the required voltage to the selected output line 30. As the connection request is memorized inside the relative latch 3, the connection remains even at the end of the enabling pulse, unless it is disabled or switched to a different voltage by address and gate decoders 7, 8. By way of example, Figure 2 shows the connection for supplying voltage V2 to the second output line (output voltage 02). As can be seen, to begin with, switches 4 are all open, and the output lines and signals ADD1-ADDN, CK1-CKN are all floating. At instant t 1 , signal ADD2 switches to 1; at instant t 2 , signal CK2 also switches to 1, thus switching the latch supplied with both the signals, and closing the relative switch 4; and, after a brief transient, voltage 02 reaches the value V2 present on the connected input line, which situation remains unaffected even when signals CK2 and ADD2 are subsequently switched to zero. Connection data is normally loaded into cells 2 in direct-access manner by columns, at the maximum speed at which enabling signals CK1-CKN are generated, and there are no analog limits to said speed. Each output line 30 may of course be connected to only one input line, i.e. to only one analog input voltage, whereas the same input line may be connected to and supply different output lines with the same analog voltage. Each output line may be left floating, or may be connected to one of the various input lines without affecting the others. The advantages of the structure described are as follows. In particular, by permitting direct access, different analog or digital voltage values may be supplied rapidly to a number of outputs, so that the structure is particularly suitable for use in devices employing different rapidly varying voltages, e.g. telephone answering machines comprising nonvolatile memories for storing voice samples. Moreover, the structure may be used as a digital/analog converter for supplying predetermined analog output voltages from the digital address data supplied to decoders 7, 8. The structure according to the present invention is also cheap and easy to integrate in complex electronic devices, and is highly flexible and reliable. Clearly, changes may be made to the structure as described and illustrated herein without, however, departing from the scope of the present invention. In particular, the logics for addressing and selecting the elementary cells may be other than as described; latches 3 and switches 4 may be formed in any appropriate manner; and any procedure may be employed for loading and modifying the switching data in latches 3.

Claims: An input structure (1), particularly for associative memories, characterized by an array of elementary cells (2), a number of input lines (20), a number of output lines (30), and a number of address lines (40, 50); each elementary cell (2) comprising a memory element (3) connected to a said address line, and a switching element (4) controlled by a respective memory element to connect one of said input lines (20) to one of said output lines (30). A structure as claimed in Claim 1, characterized in that said elementary cells (2) are arranged in rows and columns, said output lines (30) extending perpendicularly to said input lines (20); and in that each said switching element (4) has a first terminal connected to one of said input lines, a second terminal connected to one of said output lines, and a control terminal connected to an output of a respective memory element (3). A structure as claimed in Claim 1 or 2, characterized in that said address lines (40, 50) comprise a number of address lines (40) and a number of enabling lines (50); said enabling lines extending perpendicularly to said address lines; and each memory element (3) comprising a first input (D) connected to one of said address lines (40), and a second input connected to one of said enabling lines (50). A structure as claimed in Claim 3, characterized in that said memory elements each comprise a latch (3). A structure as claimed in Claim 4, characterized in that said latch (3) is a D type flip-flop. A structure as claimed in Claim 5, characterized in that each said latch (3) has a data input (D) connected to an address line (40), a clock input (CK) connected to an enabling line (50), and an output (Q) connected to a control terminal of a respective switching element (4). A structure as claimed in any one of the foregoing Claims from 3 to 6, characterized in that said address lines are connected to a first decoder, and said enabling lines are connected to a second decoder; said first decoder having a digital input receiving a digital address signal specifying one of said address lines; and said second decoder having a clock input receiving a clock signal, and a digital input receiving a digital selection signal specifying one of said enabling lines. A structure as claimed in any one of the foregoing Claims, characterized in that said input lines are connected to a multiple-output analog voltage source. An analog memory, characterized by an input structure as claimed in any one of the foregoing Claims.

Inventors: CANEGALLO ROBERTO, CHINOSI MAURO, GOZZINI GIOVANNI, KRAMER ALAN, ROLANDI PIER LUIGI, SABATINI MARCO, CANEGALLO, ROBERTO, CHINOSI, MAURO, GOZZINI, GIOVANNI, KRAMER, ALAN, ROLANDI, PIER LUIGI, SABATINI, MARCO, Kramer, Alan c/0 SGS-Thomson Microelectr. S.r.l.
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1996
Main classification: G11C15
IPC codes: G11C15