ECC protected memory organization with pipelined read-modify-write accesses

Abstract: A system and method providing ECC protection for all data block sizes for which a computer system supports store (ST) accesses includes an access control logic unit which converts store accesses for small data block (≦ 64-bits) into read-modify (merge)-write accesses and a data merge logic unit which merges 64-bit data blocks retrieved by the load access with the small data block of the store access to create a new 64-bit data block. An ECC generation logic unit processes the merged 64-bit data block, including the new small data block.

Description: The subject matter of this application is related to the subject matter of the following applications: European paten No. EP-A-0 727 738; European patent No. EP-A-0 727 739; European patent No. EP-A-0 727 736; European patent No. EP-A-0 727 735; the European patent No. EP-A-0 730 225 entitled "RECLAMATION OF PROCESSOR RESOURCES IN A DATA PROCESSOR" ; the European patent No. EP-A-0 730 224 entitled "METHOD AND APPARATUS FOR SELECTING INSTRUCTIONS FROM ONES READY TO EXECUTE" ; the European patent No. EP-A-0 730 221 entitled "METHOD AND APPARATUS FOR ACCELERATING CONTROL TRANSFER RETURNS" ; the European patent No. EP-A-0 730 222 entitled "METHODS FOR UPDATING FETCH PROGRAM COUNTER"; the European patent No. EP-A-0 730 220 entitled "METHOD AND APPARATUS FOR RAPID EXECUTION OF CONTROL TRANSFER INSTRUCTIONS"; the European patent No, EP-A-0 730 230 entitled "METHOD AND APPARATUS FOR PRIORITIZING AND HANDLING ERRORS IN A COMPUTER SYSTEM"; the European patent No. EP-A-730 226 entitled "HARDWARE SUPPORT FOR FAST SOFTWARE EMULATION OF UNIMPLEMENTED INSTRUCTIONS"; and the European patent No. EP-A-0 730 219 entitled "METHOD AND APPARATUS FOR GENERATING A ZERO BIT STATUS FLAG IN A MICROPROCESSOR", the latter eight of which are filed simultaneously with this application. EP-A-0 418 457 teaches a structure in which constant data block sizes are merged. This reference discloses a multi-stage ECC system having two ECC stages in which the first ECC stage generates error flags and corrected data for a single error whereas the second ECC stage generates check bits. EP-A-0 540 450 discloses an ECC system having a parity/ECC protocol interface selecting a code that contains groupings of data bits corresponding to a desired parity scheme. Background of the Invention Technical Field This invention relates to the field of computer architecture and in particular to methods and systems for providing error correction code (ECC) protected cache memory without encumbering data accesses to cache memory. Related Art High performance computer systems often use pipelined cache systems with write-back designs to reduce store latency. These same systems use redundancy in the form of ECC protection to handle errors generated during data transfer and by memory damage due, for example, to alpha particle collisions. However, the requirements of ECC protection can interfere with cache data accesses, slowing down system operations and generating pipeline stalls. ECC protection is normally designed for 64 bit or larger data blocks, while many computers implement store accesses for data block sizes ranging from 8 bits to 64 bits. Conventional systems, therefore, do not typically provide ECC generation for each data block size for which the computer supports store access. Some systems generate additional, i.e. non-64-bit ECC, bits for redundancy checking on data blocks smaller than 64-bits, but this approach requires additional memory space. Moreover, ECC generation methods generally require two memory accesses, which slows down system operations. Therefore, there is a need for a system and method for providing ECC protection efficiently to all data block sizes for which a computer system supports store accesses. Summary of the Invention The present invention, which is defined in detail on the appended claims 1 and 2, is a system and method for organizing cache memory accesses to provide ECC protection for store accesses of all supported data block sizes without creating additional pipeline stalls or otherwise interfering with cache accesses. A system in accordance with the present invention comprises a cache random access memory (RAM) core, access control logic coupled to the RAM core for controlling cache accesses to the RAM core, and data merging logic and ECC generating logic which are also coupled to the RAM core. Cache load (read) and store (write) accesses are pipelined, with the load accesses given default priority over the store accesses. The target address of a pending store is maintained in a separate register that is monitored by the access control logic. A subsequent load access to this target address is detected by the access control logic, which forces the store access to complete immediately to avoid reading stale data. When a small data block store (write) access is initiated, the access control logic treats the store access as an atomic read-modify-write access at the target address of the 64-bit data block that includes the small data block. The old memory image of the 64-bit data block is provided to the data merge logic by the read (load) access. The data merge logic includes multiplexers driven by a programmable logic array to combine (modify) the old 64-bit data block with the small data block provided to the data merge logic by the write (store) access of the atomic access. ECC generation for the resulting 64-bit data block, which includes the new small data block, proceeds by 64-bit ECC generation methods, and the modified 64-bit data block is written to the target address when the store access completes. A read-modify-write access with a 64-bit data block provides ECC generation in an efficient manner. Brief Summary of the Drawings Fig. 1 is a block diagram of a bank of cache RAM including access control logic and data merging and ECC generating logic. Fig. 2A is a block diagram of the data merge/ECC logic of Fig. 1 Fig. 2B is a representation of the look-up table in the programmable logic array included in the data merge/ECC logic of Fig. 1. Fig. 3 is a timing diagram representing RAM access timing without the access control logic of Fig. 1 Fig. 4 is a timing diagram representing system access timing using the access control logic of Fig. 1. Fig. 5 is a detailed diagram of the access control logic of Fig. 1 Fig. 6 is a flow chart of the method in accordance with the present invention. Fig. 7 shows ECC generation equations suitable for the disclosed implementation. Detailed Description of the Invention Referring to Fig. 1, there is shown a block diagram of a bank of a cache memory system 100 in accordance with the present invention. System 100 comprises a RAM core 110 , access control logic 120, data merge logic 150 and ECC generation logic 180. RAM core 110 includes RAM access enable (CS), write enable (WE), address (A), and data input (DI) registers 112 , 114 , 116, 118 , respectively, and a data output register (DO) 119 . In the figure, buffers are labeled in accordance with their corresponding inputs. Access control logic 120 regulates access to RAM core 110 by means of control lines to CS and WE registers 112 , 114 . Access control logic 120 is driven by LD and ST accesses from a processor (not shown) through ld and st signals, respectively. Store enable (SE) register 130 and store pending (SP) register 132 are coupled to access control logic 120 and are set and reset according to the sequence and target addresses of LD and ST signals. These signals are discussed below in conjunction with Fig. 2. An address select multiplexer 140 has one input coupled to an address bus 142 and a second input coupled to a store-address (SA) register 144. When st is asserted (ST access) the target address on address bus 142 is loaded into SA register 144 and SP register 132 is set. A select enable (sel_sa) control signal is applied to multiplexer select input 146 by access control logic 120 to pass either the target address on address bus 142 or the target address in SA register 144 to address register 146 . Access control logic 120 sets and resets sel_sa according to the sequence of LD and ST accesses, as described in greater detail below. In addition, access control logic 120 compares the target addresses in SA register 144 and on address bus 142 . If the address are the same, access control logic 120 forces the pending ST access to complete to preclude reading a dirty data block, i.e. a data block that has been modified by an earlier but still pending ST access. Data merge logic 150 includes a first input 154 coupled to DO 119 of RAM core 110 through an output data line 172 and a second input 156 coupled to an input data line 174 for receiving data from the processor. An output of data merge logic 150 is coupled to DI register 118 through ECC generating logic 180 . This configuration allows data merge logic 150 to modify data read from RAM core 110 by a LD access using data written to RAM core 110 by a ST access. The resulting merged data is coupled to ECC generation logic 180 which performs standard 64-bit-ECC generation on the merged data prior to completing the ST access through DI register 118 . Referring now to Fig. 2A, there is shown a block diagram of data merge logic 150 in accordance with the present invention. Data merge logic 150 comprises eight dual input multiplexers 252, the inputs of which form inputs 154 , 156 of data merge logic 150. The multiplexer select inputs 258 of multiplexers 252 are driven by a programmable logic array (PLA) 260, which receives data block size information from the processor through an input 261 . Referring to Fig. 2B, there is shown a look up table 262 included in PLA 260. Look up table 262 includes a set of 8-bit merge codes 264 indexed by a set 266 of data sizes and a set 268 of data offsets, for driving select inputs 258 of multiplexers 252. For ST accesses involving small data blocks (< 64 bits) or for atomic accesses such as read-modify-write accesses, the processor couples data block size and offset information to PLA 260 though input 261 . PLA 260 uses look-up table 262 to determine an appropriate merge code 266 and couples this merge code 266 to multiplexers 252. Multiplexers 252 merge the read, 64-bit data block at input 154 with the new data block at input 156 responsive to merge code 266 to form a new 64-bit data block. The new, merged 64-bit.data block is coupled to ECC logic 180 where 64-bit ECC generation for the new 64-bit data block, including the small data block, is done. For a read-modify-write access, the new data block is 64 bits and the merge is effectively an overwriting of the data at input 154 with the data at input 156. Referring now to Fig. 3, there is shown a typical timing diagram 300 for accessing RAM core 110 , independent of timing modifications introduced by access control logic 120. For example, when a target address is coupled to A register 116 and CS register 112 is set at the start of a clock cycle 310, the data is available at DO 119 at the second half of the clock cycle. Similarly, when CS 112 is set and a target address and data are coupled to A register 116 and DI register 118 , respectively, at the start of clock cycle 310, data is written to the target address when WE 114 is asserted at the second half of the clock cycle. In order to ensure that the CPU is used efficiently, the default condition for system 100 is that LD (read) accesses are performed before ST (write) accesses. This default condition is overridden under circumstances described in detail below. In order to implement both the default and override conditions, the basic timing diagram of Fig. 3 is altered by access control logic 130 as described below. Referring now to Fig. 4, there is shown a timing diagram 400 for system access to cache system 100 through access control logic 130. As indicated, both CS 112 and WE 114 are set at the start of a clock cycle 410 and LD 117 is set at the start of next clock cycle 420. Under access control logic 130, LD (read) access to RAM core 110 occurs one full clock cycle (430) after LD 117 is set and the data is available at DO 119 in that same cycle (Fig. 3). On the other hand, ST (write) access to RAM core 110 occurs at least two full clock cycles following assertion of ST 115 at 440. As indicated in Fig. 3, the data is written in the same cycle that ST access is granted. Moreover, because of the default condition described above, ST access to RAM core 110 may be postponed for additional clock cycles if addition LD accesses are asserted before the ST access is granted. Referring now to Fig. 5, there is shown a schematic diagram of access control logic 120 for prioritizing and implementing LD and ST accesses to RAM core 110 (Fig. 1). Throughout the specification, signals are indicated in small letters and the registers to which they are applied are indicated by corresponding capital letters. The LD/ST default priority discussed above is implemented by AND gate 530 and OR gate 534. For example, ST access is granted (we is asserted) when st_in is asserted (SA 130 is set) and ld is not asserted (no LD access pending). The timing delays for ST accesses indicated in Fig. 4 are implemented by first and second latches 510 , 512 as follows. When ST is set, st is asserted at the input of first latch 510, which asserts st_q on the next clock cycle to the input of second latch 512 . Second latch 512 asserts st_qq on the subsequent clock cycle, producing st_in at the output of AND gate 514 two clock cycles after st is asserted. In the absence of a LD access, st_qq thus causes the ST access to complete at the target address in SA register 144 by means of AND gate 530 and OR gate 540 . The other inputs of AND 514 are se, which is asserted when SE 130 is set, and sp_in negated. The output of AND 514 , st_in, is applied to one input of OR 516. The output of OR 516, sp_out, is used to set and clear SP register 132. Thus, when spin is asserted, sp_out, resets SP register 132 when 1d is not asserted and compare logic 538 is not asserted. If ld is asserted, however, sp-out sets SP register 132 since a ST access will be delayed by the priority scheme. An OR gate 550 ensures that CS register 112 is set (RAM access enabled) whenever the processor requests a LD access (ld asserted) or a ST access (st_in two clock cycles after st) or when a ST access is pending (sp_in asserted). OR gate 540 asserts sel_sa to pass the target address in SA register 144 to A register 116 in RAM core 110 in the case of a ST access or when sp_out is asserted. The ST access will complete as long as we remains asserted. However, if a LD access intervenes, the ST access will remain pending. The default priority of LDs may create a condition in which a LD access is issued to a target address after a pending ST access modifying the contents of the address is generated. In order to prevent LD accesses of stale data, compare logic 538 , AND 532, and OR 534 operate to force a pending ST access to complete when the target address asserted on bus 142 equals the target address in SA register 144 . As a result, ST accesses to a target address will complete before a subsequent LD access to the same target address is processed. For this purpose, SP register 132 is set and sp_in is asserted whenever a ST access is received. By applying sp_in and the output of compare logic 536 to AND gate 532, WE is enabled immediately, allowing the ST access to complete to the target address without waiting one or two clock cycle for st_qq. Note that a LD access does not disable WE when sp_in is asserted and the address compare is true, i.e. the output of compare logic 538 is asserted, as it does when st_in is asserted. Since each cache memory bank system 100 (Fig. 1) can store only a single target address in SA register 144 , control access logic 120 also provides a way to force a ST access if a ST access is received while an earlier ST access is still pending. For this purpose, AND gate 560 force an LD access to be repeated (retry asserted) when ld is asserted at the same time different target addresses are on bus 142 and in SA register 144 and either st_qq or sp_out is asserted. When, for example, the target addresses are the same, the LD access proceeds with the target address in SA register 144. Referring now to Fig. 6, there is shown a flow chart of method 600 for ECC generation implemented by the combination of access control logic 120, address select 140, merge data logic 150, ECC logic 180, and RAM core 110. Process 600 is initiated when a ST access request for a small data block is received 610. Responsive to the ST access, the 64-bit data block currently stored at the target address of the ST access is retrieved 620, using a LD access. Small data block of the ST access is then merged 620 with the 64-bit data block retrieved by the LD access from the target address to form a new, 64-bit data block. 64-bit ECC is then generated 640 for the merged, 64-bit data block that now includes the small data block. Referring now to Fig. 7, there are shown ECC generation equations suitable for the disclosed 64-bit system. It is understood that while the invention has been disclosed for a system employing 64-bit data blocks, it can be readily altered to accommodate 8, 16, 32, 128, et seq bit data. Thus, a method and system have been presented for providing ECC protection to all data block sizes for which a system supports store accesses, using a single ECC generation scheme. The method uses data merge logic coupled to the input and output buffers of the RAM core of a memory system in combination with a type of read-modify-write access to combine small block data (≤ 64-bit data block) from a ST access with 64-bit block data retrieved by a LD access to memory. The merged data, including the small block data, is then ECC protected using standard 64-bit ECC logic. The method naturally supports atomic read-write-modify accesses, when the ST access data block is a 64-bit data block.

Claims: A cache memory system including ECC protection for all supported data store accesses, the system comprising: a RAM core memory (110) having control registers, an address input, a data input and a data output; an access control logic unit (120) having inputs for receiving load and store access signals and coupled to the control registers of the RAM core memory (110), for controlling access to the RAM core memory responsive to the received load and store access signals; a programmable logic array (260) having an input for receiving data store access information, an output, and including a look-up table for providing a merge code at the output responsive to the received data store access information; a data merge logic unit (150) having a first data input (154) coupled to the data output of the RAM core memory (110), a second data input (156) coupled to receive input data, a select input coupled to the output of the programmable logic array (260), and a data output for combining data received from the RAM core data output at the first data input (154) with the received data at the second data input (156) responsive to the merge code received from the programmable logic array (260); and an ECC generation logic unit (180) having a data input coupled to the data output of the data merge logic unit (150) for receiving the data combined from the RAM core data output received at the first data input (154) and the input data received at the second data input (156), and a data output coupled to the data input of the RAM core memory (110), for performing standard ECC generation on the received combined data. A method for handling ECC generation for all data block size store accesses supported in a cache memory system (260) including a look-up table that has a selected data block size and an ECC generating process suited to the selected data block size, the method comprising the steps of: receiving (610) a store access request including data store access information at a target address in the memory system for a data block having a size less than the selected data block size; generating a load access request at the target address of said received store access request to retrieve (620) a stored memory image at said target address having the selected data block size; determining an appropriate merge code for the data block having a size less than the selected data block size from the look-up table on the basis of data store access information; combining (630), through the use of said determined appropriate merge code, the data block from the store access request with the retrieved data block having the selected data block size to form a new data block having the selected data block size; and generating (640) ECC for the new data block having the selected data block size using the ECC generation process suited to the selected data block size. The cache memory system of claim 1, wherein the data store accesses are data block size store accesses, the ECC generation unit (180) is adapted to receive a selected block size, and the look-up table provides a merge code selected so that the received combined data is of the selected block size. The cache memory system of claim 3, wherein the merge codes of the look-up table are indexed by a set of data sizes and a set of data offsets for the first and second data inputs received by the merge data logic unit.

Inventors: CHEN CHIEN, LU YIZHI, CHEN, CHIEN, LU, YIZHI
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1996
Main classification: G06F11
IPC codes: G06F11