METHOD OF PLATING THROUGH HOLES OF A PRINTED CIRCUIT BOARD

Abstract: Through holes (18) of a printed circuit board (10, 12) are plated by electroless metal deposition. A plating mask (22) has openings (24) which are larger than the conductive areas (19) around the through holes. Shielding portions (28), which may be of a solder resist material, prevent undesired deposition of metal on the substrate (10) and can be accurately positioned by screen printing.

Description: DESCRIPTION METHOD OF PLATING THROUGH HOLES OF A PRINTED CIRCUIT BOARD This invention relates to a method of plating the through holes of a double sided plated through hole printed circuit board. Plated through hole (PTH) boards have conducting patterns formed on both sides and have holes which pass through the board which connect conductive elements on one side of the board to conductive elements on the opposite side of the board. The inner walls of the through holes are plated with a metal layer to ensure electrical connection between opposite sides of the board. PTH boards have conventionally been manufactured by a process in which the through holes are initially formed through a copper clad board and the board then undergoes an electroless copper plating stage. Thus, the through holes are plated before the conductive pattern is etched onto the sides of the board. This has been the conventional practice because, once the conductive pattern is etched onto the sides of the board, it is no longer possible to plate the through holes by electro-plating since they are not interconnected. Electroless copper plating was also not considered desirable because it would involve plating the entire board a second time. For the manufacture of a single sided printed circuit board, an image of the circuit pattern to be produced is formed on the board in an etch resist material. This can be carried out by a screen printing process or by using photo-sensitive resist material. The resist image protects the underlying copper surface of the board, and the remaining copper surface is etched away. However, for the manufacture of plated through hole boards, this form of positive resist image is not frequently used because the etch-resistant mask may not provide a reliable unbroken film of resist through all of the plated holes, so that the plated holes may be etched away in the subsequent etching process. Therefore, the usual process is to form the resist image on the areas of the copper which are to be etched away, to plate all the tracks and the barrels of the holes with gold or tin-lead, and then to use this protective plated layer as the etch resist. Because a negative resist image is required, the use of screen printing is not practical, and dry film techniques are typically used. Furthermore, the use of a negative resist image clearly imposes additional processing steps and increases the complexity and cost of the manufacturing procedure. US-3269861 discloses a method for electroless copper plating for a plated through hole board, in which the two sides of the board are etched to form the conductive pattems before the holes are drilled or punched. As a result, any form of conventional etching may be employed because the through holes are not yet present at the time of the etching process. The method of US-3269861 involves coating both sides of the previously patterned board with a resist coating. Holes are then punched or drilled in the board and the panel is then sensitised. This means that the portions of the board not protected by the resist coating are made susceptible to the deposition of an electroless layer. Thus, the only portions of the board which are sensitised are the surfaces of the through holes. The resist coating can then be removed and the panel is subjected to electroless metal deposition. The electroless deposition takes place at the sensitised insulating areas of the board and at the conductive areas of the board, namely within the through holes and on the tracks. US-3269861 therefore overcomes many of the problems associated with the more conventional method of producing plated through hole boards. However, US 3269861 suffers from the drawback that any deposition of metal between the conductive tracks may lead to short circuits between the tracks. Although the electroless solution adheres principally to the sensitised areas of the board and to the metal conductive portions, some deposition of metal will take place on the non-conducting portions of the board. Also, the tracks are plated twice in the method of US 3269861 which increases the quantity of copper required, and introduces inaccuracies into the selection of the thickness of the copper tracks. It is possible to apply a plating mask to the board before the electroless plating procedure. This mask can have openings corresponding to the through holes to be plated. Since the through holes represent a small proportion of the area of the board, this mask almost entirely covers the board, with the result that the application of the mask may be difficult. For example, if a screen printing process is to be used, the large quantity of ink may result in the screen fabric adhering to the substrate and resisting removal from the substrate. This can lead to problems in correct alignment of the mask, thus reducing the accuracy of the pattern. If the openings in the mask are very small then this inaccuracy may result in incorrect positioning of the opening. In order to overcome this problem, it is possible to utilise openings significantly larger than the diameter of the hole to be plated, so that any offset of the opening does not prevent the through hole from being plated. However, the use of larger * openings may still result in non-conductive areas of the board receiving metal plating, still leading to the possibility of electrical shorts. The present invention provides a method of plating the through holes of a printed circuit board according to which the holes may be drilled after the conductive pattern is etched onto the surfaces of the board, but which eliminates the possibility that the electroless plating may produce short circuits. According to the present invention there is provided a method of plating the through holes of a printed circuit board, the printed circuit board comprising conducting pattems on opposite sides of the board with through holes extending through the board, each through hole having an inner wall which has been treated to render it receptive to the action of a metallic plating solution and having a conducting region disposed around each opening of the through hole, the method comprising the steps of: applying a shielding pattern to the printed circuit board, the shielding pattern comprising portions extending around the conducting regions of respective through holes, and applying a plating mask to the surfaces of the board, the plating mask comprising openings, each opening corresponding to a through hole and the respective conducting region, the inner edge of the opening being spaced from the outer edge of the conducting region; and treating the board with a metallic plating solution to deposit conductive material in the through holes and on the conducting regions. Preferably, the shielding pattern comprises a solder resist pattern. The portions of the solder resist pattern may be annular in shape, centred on the axis of the respective through hole, and the annular shape may be discontinuous, having openings which correspond to conducting patterns which communicate with the conducting region of the respective through hole. The invention also provides a method of producing plated through hole printed circuit boards, comprising the steps of: forming conducting pattems on opposite sides of an insulating substrate to form a printed circuit board; applying a de-sensitising layer to opposite sides of the board; * forming through holes extending between opposite faces of the board, such that each through hole has a conducting region of a conducting pattern disposed around each opening of the through hole; treating the board so that the inner wall of each through hole is receptive to the action of a metallic plating solution; and plating the through holes using the plating method of the invention. According to a second aspect of the present invention, there is provided a plated through hole printed circuit board comprising an insulating substrate having conducting pattems on opposite sides of the board, and through holes extending between opposite sides of the board, a conducting region of the conducting pattern being disposed around the openings of each through hole, in which the thickness of the conducting region is greater than the thickness of the remainder of the conducting patterns, and a shielding region extends substantially around the conducting regions on at least areas of the board not covered by the conducting pattern. These and other features of the present invention, and their advantages, are illustrated specifically in embodiments of the invention now to be described by way of example, with reference to the accompanying drawings, in which: Figure 1 shows a known process for plating through holes after etching the conducting pattern onto the two sides of a double sided printed circuit board; 5 Figure 2 illustrates the problems associated with known plating masks used during the electrolysis plating operation; Figure 3 illustrates schematically the masks used in the method of plating according to the invention; Figure 4 shows a modification to a shielding mask shown in Figure 3; o and Figure 5 shows the steps involved in plating the through holes using the method according to the invention. This invention provides a method, as illustrated in Figure 3, of plating through holes 18 of a plated through hole printed circuit board in which a 5 " plating resist mask 22 is provided with an aperture 24 which is larger than a conducting portion 19 surrounding the through hole 18. The provision of a shielding region 28 ensures that the electroless plating procedure does not deposit metal on the insulating portions of the board surrounding the conducting portion 19. o Turning now to Figure 1 , a known method of producing a plated through hole printed circuit board is shown. It is to be noted that steps A to E shown in Figure 1 can also be employed for producing a plated through hole printed circuit board having through holes plated in accordance with the invention. In part A of Figure 1 is shown an insulating substrate 10 which is clad 5 on both surfaces with metal foil 12, preferably copper. The insulating substrate 10 may of course be made from a variety of substances, as will be appreciated by those skilled in the art. For example, the substrate may comprise bonded layers of glass or paper material. As shown in part B of Figure 1 , a positive resist mask 14 is deposited o on both sides of the board. The resist mask 14 may be formed on the laminate in a variety of ways: A photographic technique involves applying a light sensitive enamel to the entire surface of the board which is then dried. A pattern is printed on the light sensitive enamel for example using light emitted from a carbon arc. After exposure, the image is developed by immersing the board in a tank of 5 developing solution which dissolves those portions of the light sensitive coating which were not exposed to light. The remaining light- exposed coating provides a hard enamel which protects the metal foil beneath during a subsequent etching procedure. Following etching, the exposed light sensitive enamel may be stripped from the panel by immersion in a suitable solvent. ι o The photographic system of printing is relatively slow and expensive, and the resist mask 14 may alternatively be produced by a printing process, for example by screen printing. In screen printing, a circuit pattern is defined on the woven mesh of a screen fabric. A liquid resist material is forced through the open areas of the is * screen mesh not protected by a stencil onto the substrate, by the pressure of a squeegee which is wiped across the top surface of the screen. Any conventional print and etched technique may, however, be used to provide the circuit pattern on opposite sides of the board. The skilled addressee will also appreciate that a positive or negative 20 resist image may be utilised, although a positive image may be preferred since the required number of steps is lower than those required for a negative resist image. Shown in Figure 1 , part C is the circuit pattern on both sides of the board after etching. As shown, the copper layers 12 have been etched away 25 apart from those areas protected by the positive resist mask 14. Subsequently, the resist mark 14 is removed using a suitable solvent. For example, the resist image 14 may be alkali-soluble, and be removed by dipping the board into an alkali solution. In Figure 1 , part D, both sides of the board are coated with a resist 30 coating 16 which is provided as a desensitising solution as will be explained in the following. Holes 18 are then drilled or punched through the substrate shown in Figure 1 , part E and the panel is then sensitised. Sensitisation involves depositing a layer which adheres to the insulator surface within the through holes so as to render the surface receptive to a metal plating layer during an electroless plating process. Catalysts are used for this purpose, for example a neutral or acid solution of palladium and tin, which deposits a thin layer of surface-active palladium in the holes 18. The resist coating 16 prevents the catalyst adhering to the substrate 10 on the surface of the board. The next stage in the procedure in the known method involves removing the resist coating 16. The only portion of the board which has been made receptive to the electroless plating solution is the inner portion of the through hole 18. The removal of the resist coating may be carried out by dissolving the coating 16 in an alkali solution, for example caustic soda. Of course, the method of removing the resist coating depends upon the type of resist used. Before the electrolysis plating is carried out, it is possible to apply a so- called accelerator solution which has the effect of removing tin from the catalyst layer, and this improves the plating during the subsequent electroless plating operation. Electroless plating is then carried out in order to deposit a thin copper layer (or other metal - for example nickel, or a combination of metal layers) to the required thickness within the holes. The copper layer 20 shown in Figure 1 , part F and covers all of the conducting regions of both sides of the board as well as the inner surface of the through hole 18. As the substrate 10 between the tracks had not been subjected to the catalyst solution, the copper layer is not deposited on those portions of the board. However, one problem encountered in the process of electroless deposition is that some metallic plating can in fact be deposited over the substrate 10 between the conducted portions 12. This can result in undesired conducting paths between the tracks, leading to short circuits. One possible way envisaged by the applicant to reduce this problem is to provide a resist mask 22 (Figure 2) which resists the deposition of the metal and shields the portions of the circuit which are not to be plated. As shown in Figure 2 part A, the resist mask 22 could include an opening 24 which corresponds to the band 19 of copper around the through hole 18. In this case, the remainder of the circuit is protected from plating. Clearly, if the mask is to cover all the exposed areas of the substrate, the opening must be very close to the pad that is to be plated. However, a mask of this type must almost entirely cover the board and this introduces problems in applying the mask to the board. For example, if a screen printing process is to be used, the screen fabric may not lift evenly from the substrate during printing and this may result in stretching or distortion of the screen fabric. This is a result of the tack of the ink used. As a result, errors in alignment may occur such as shown (exaggerated) in Figure 2 part B. As shown, the mask no longer exposes the through hole. A lesser degree of misalignment will result in areas of the exposed substrate being revealed to * the plating solution. In order to overcome this problem, it may be necessary to employ a larger opening 24 as shown in Figure 2 part C. However, in this case the area of the substrate 10 surrounding the conducting portion 19 of through hole 18 is still exposed to metal plating and deposits 26 may therefore form. In the method according to the invention, a mask 22 is used having an opening 24 which is greater in size than the conducting band 19 around the opening of the through hole 18. However, as well as the application of the mask 22, a shielding layer is applied comprising shielding portions 28(Figure 3) which resist electroless plating and thereby prevent the formation of deposits 26 on the substrate 10 exposed between conducting tracks. The shielding layer is preferably applied before the mask 22. The mask according to the invention is shown in Figure 3 part A. The shielding portion 28 prevents the two conducting tracks shown from short circuiting, because the substrate area between them is protected from electroless deposits. As shown in Figure 3 part B, misalignment of the mask 22 can not result in exposure of any insulating portion of the substrate 10 surrounding the through hole 18 during the electroless plating. The shielding portions 28 may be applied as a resist mask which is preferably applied by a screen printing process. Since the area to be printed is relatively small, an accurate mask may be printed using the screen printing process, and the problems associated with lifting of the screen fabric are no longer present. Because there are few open areas of the screen fabric, low pressures can be employed for the printing process, and the screen fabric is stable. The shielding portions 28 preferably form a solder resist layer. Such layers are known and typically comprise a heat resistant epoxy or acrylic resin. Such layers have conventionally been applied to conducting pads on the board which do not require to be soldered, and have the advantage of very good adherence to the board. The shielding portions 28 shown in Figure 3 are annular in shape surrounding the conducting band 19 of the through hole 18. A channel 30 is provided which enables the conducting track leading to the through hole 18 to remain exposed. However, the shielding portion 28 may comprise a closed annular ring as shown in Figure 4 or may be in a variety of other shapes. The shielding portion 28 may overlap the edge of the conducting portion 19 of the through hole 18, or it may lie adjacent that conducting portion as shown in the drawings. The precise shape of the shielding portion 28 is not critical, provided it shields the insulating portion between tracks which lies adjacent the conducting band 19. Also, the openings 24 of the resist mask 22 may be sized to meet the edge of the shielding solder resist portions 28, or the mask 22 may overlap a part of the shielding portions 28. The process steps required to implement the shielding and masking procedure of the invention are shown in Figure 5. Figure 5 part E corresponds to Figure 1 part E and represents the board having both sides coated with a resist coating 16, and with the through holes 18 drilled or punched. As in the case of Figure 1 , the inner surface of the through hole has been sensitised using a catalyst solution and the resist coating 16 is then removed. Figure 5 part F shows the subsequent application of the shielding portion 28 forming a solder resist layer and which, in the case shown in Figure 2, is positioned outside the conducting band 19 associated with the through 5 hole 18, and overlies the insulating region adjacent the conducting band 19. After the solder resist layer has been applied, the resist mask 22, which protects the board against electroless plating, is applied. As can be seen in Figure 5 part G, the opening 24 in the resist mask 22 is larger in size than the conducting band 19 so that the positioning of the mask 22 is not critical. The ι o openings of the resist mask 22 correspond to the outer edge of the solder resist portions 28. However, the resist mask 22 may overlap the solder resist portions (as shown in dotted Iines in Figure 5 part G) so that movement of the resist mask 22 does not result in exposure of the substrate 10 between conducting tracks. However, the solder resist portions 28 prevent 15 * communication between tracks whether or not there is such overlap. Acceleration may have been carried out when the resist coating 16 is removed, or alternatively an additional accelerating step may be desired, as is known in the art. Following this, the electroless copper plating is carried out to produce the copper layer 20 as shown in Figure 5 part H. 2o Finally, the resist mask 22 is removed to reveal the circuit tracks (Figure 5 part I). The resist coating may for example be acid- or alkali-soluble or removable using a solvent. The use of a mask during the electroless plating results in the saving of copper or other metal when compared to the prior art shown in Figure 1 , in 25 which all tracks are plated by the electroless solution. Additionally, the problems which could be associated with masking are avoided with the process of the invention. The shielding portions 28 do not need to be removed and may in fact prevent solder flowing beyond the conducting band 19. It is also to be noted 30 that the resist mask 22 may itself also comprise a solder resist layer which leaves exposed the through holes and those pads of the board which are to be subsequently soldered. In this case, the removal of the resist mask 22 is not required. In such a case, the solder resist mask carries out the conventional function of a solder resist mask as well as providing an electroless plating resist mask. In the specific embodiment, the shielding portions 28 have been described as being deposited before the resist mask 22. However, it is equally possible to deposit the two masks in the reverse order. This is particularly evident when both masks comprises solder resist and are not to be removed. When two solder resist masks are used, both prints will become integral. Even if the plate resist mask 22 is a different form of mask, and is removed, a further solder resist mask may be desired, as is conventionally applied, and this mask could also integrate with the solder resist of the shielding layer. Although the invention has been described in connection with a double sided single layer board, the process described is clearly suitable for plating * through holes in multi-layer boards. From reading the present disclosure, other modifications will be apparent to persons skilled in the art. Such modifications may involve other method steps which are already known in the manufacture of printed circuit boards and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure of the present application also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation thereof, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention. The applicants hereby give notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.

Claims: CLAIMS 1. A method of plating the through holes of a printed circuit board, the printed circuit board comprising conducting patterns on opposite sides of the board with through holes extending through the board, each through hole having an inner wall which has been treated to render it receptive to the action of a metallic plating solution and having a conducting region disposed around each opening of the through hole, the method comprising the steps of: applying a shielding pattern to the printed circuit board, the shielding pattern comprising portions extending around the conducting regions of respective through holes, and applying a plating mask to the surfaces of the board, the plating mask comprising openings, each opening corresponding to a through hole and the respective conducting region, the inner edge of the opening being spaced from the outer edge of the conducting region; and " treating the board with a metallic plating solution to deposit conductive material in the through holes and on the conducting regions. 2. A method as claimed in claim 1 , in which the shielding pattern is applied before the plating mask. 3. A method as claimed in claim 2, in which the spacing of the opening from the conducting region of a through hole corresponds to a shielding pattern portion. 4. A method as claimed in any preceding claim, wherein the shielding pattern comprises a solder resist pattern. 5. A method as claimed in any preceding claim, wherein the portions of the shielding pattern are annular in shape centred on the axis of the respective through hole. 6. A method as claimed in claim 5, wherein the annular portions of the shielding pattern include openings such that the annular shape is discontinuous, the openings corresponding to conducting patterns which communicate with the conducting region of the respective through hole. 7. A method as claimed in any preceding claim, in which the shielding pattern is applied by a silk screen printing process. 8. A method as claimed in any preceding claim, in which the plating mask comprises a solder resist mask. 9. A method as claimed in claim 8, in which the solder resist plating mask is deposited by a screen printing process. 10. A method as claimed in any preceding claim, in which the metallic plating solution is an electroless plating solution. 11. A method as claimed in claim 10, in which the plating solution is an electroless copper plating solution. 12. A printed circuit board having plated through holes, the through holes being plated in accordance with the method claimed in any one of claims 1 to 11. 13. A method of producing plated through hole printed circuit boards, comprising the steps of: forming conducting patterns on opposite sides of an insulating substrate to form a printed circuit board; applying a de-sensitising layer to opposite sides of the board; forming through holes extending between opposite faces of the board, such that each through hole has a conducting region of a conducting pattern disposed around each opening of the through hole; treating the board so that the inner wall of each through hole is receptive to the action of a metallic plating solution; and plating the through holes using a method in accordance with any preceding claim. 14. A printed circuit board manufactured in accordance with the method claimed in claim 13. 15. A plated through hole printed circuit board comprising an insulating substrate having conducting patterns on opposite sides of the board, and through holes extending between opposite sides of the board, a conducting region of the conducting patterns being disposed around the openings of each through hole, in which the thickness of the conducting region is greater than the * thickness of the remainder of the conducting patterns, and a shielding region extends substantially around the conducting regions on at least areas of the board not covered by the conducting pattern.

Inventors: FRIEND STEPHEN D E J, ROBERTS JOHN W J W, FRIEND, STEPHEN, D., E., J., ROBERTS, JOHN, W., J., W.
Applicants: PHILIPS ELECTRONICS NV, PHILIPS NORDEN AB, PHILIPS ELECTRONICS N.V.
Application year: 1996
Main classification: H05K3
IPC codes: H05K3