Current digital-analog converter using insulated gate MOS transistors

Abstract: The present invention relates to a digital-to-analog converter having a plurality of inputs (B0,B1,B2,B3) for digital signals and an output (OUT) for an analog signal, and comprising a current amplification circuit (AMP) having an input (ND) and an output coupled to the converter output; and a plurality of floating gate MOS transistors (M01, M11, M21, M31) corresponding to the plurality of converter inputs and having their source terminals coupled together and to a first reference (GND) of potential, drain terminals coupled together and to the input (ND) of the amplification circuit (AMP), and control terminals coupleable, under control from the inputs of the plurality, to different references (GND,VCC) of potential having selected fixed values.

Description: The present invention relates to a digital-to-analog converter according to the preamble of Claim 1. Such converters are widely utilized in the field of circuit electronics as implemented with either discrete or integrated elements. Abundant literature is available on the subject. A known D/A converting circuit comprising a plurality of control circuits consisting of IGFETs in parallel is described in the Patent Abstracts of Japan No. JP56021415 in the name of NEC Corp. Also known from the article entitled: "Flash-Based Programmable Nonlinear Capacitor for Switched-Capacitor Implementations of Neural Networks "to Kramer et al. IEDM, Dec. 1994, p. 449-452, is the use of floating gate transistors for long-term analog storage, especially in neural network implementations. Finally, US Patent No. 5,376,935 to Seligson describes D/A and A/D converters using electrically programmable floating gate transistors. It is the object of this invention to provide a circuit which can be readily integrated and programmed, and exhibits good accuracy. This object is achieved by a digital-to-analog converter having the features set forth in Claim 1. Further advantageous aspects of the invention are set forth in the subclaims. By using a plurality of floating gate MOS transistors whose threshold voltage is programmable, as is well known, and which can be activated by the inputs of the converter and of a current amplification circuit to which the transistors are connected, a circuit can be provided which is readily integratable using MOS or mixed technology, is programmable, and exhibits an accuracy which can be well controlled, also on account of the transistor programmability. The invention will be more clearly apparent from the following description, to be read in conjunction with the accompanying drawings, in which: Figure 1 is a circuit diagram of a converter according to the invention; Figure 2 illustrates possible characteristics of gate-source voltage vs. drain current of the floating gate MOS transistors in the circuit of Figure 1; Figure 3 is a detail view of a modified embodiment of the circuit in Figure 1; Figure 4 illustrates possible characteristics of gate-source voltage vs. drain current of the MOS transistors in the circuit of Figure 3; and Figure 5 shows an embodiment of the current amplification circuit in Figure 3. As is known, floating gate MOS transistors are MOS transistors wherein, in the channel area beneath the control or gate terminal, another gate is provided which is isolated from the former and the channel. The threshold voltage of such transistors depends on the amount of charge present at their floating gate. Several ways of programming these transistors, that is of injecting/extracting charge into/from the floating gate, are known from the literature. In view of the widespread utilization of these transistors in semiconductor digital storage circuits, e.g. of the UV_EPROM, EEPROM, FLASH_EPROM types, reference can be had to the abundant literature on the subject for any enlightenment on technology and circuit design. Referring to Figure 1, the digital-to-analog converter of this invention has plural inputs, only four being shown at B0, B1, B2, B3 in the example of Figure 1, for digital signals, and one output OUT for an analog signal, and comprises: a) a current amplification circuit AMP having at least one input ND and an output coupled to the converter output; and b) a plurality of floating gate MOS transistors M01, M11, M21, M31 corresponding to the set of inputs B0, B1, B2, B3 of the converter and having their source terminals coupled together and to a first reference of potential, in particular the ground GND, drain terminals coupled together and to the input ND of the amplification circuit AMP, and control terminals coupleable, under control from the inputs B0, B1, B2, B3 to different references of potential having selected fixed values. The current amplification circuit AMP comprises, as shown in Figure 1, an operational amplifier OA having its non-inverting (+) input connected to a voltage reference VR which may have an intermediate value to the ground GND and the power supply VCC, and a feedback resistor RF connected between the output of the amplifier OA and its own inverting input (-), the output of the amplifier OA being also connected to the output of the circuit AMP, that is to the converter output OUT. For simplicity, all the control terminals may be coupleable alternatively to a second reference of potential, specifically the ground GND, or to a third reference of potential, specifically the power supply VCC. This can be achieved, as shown in Figure 1, by connecting, between the control terminal of the transistor M01 and the supply VCC, a controlled switch S01H, e.g. a traditional type of MOS transistor, and between it and the ground, a controlled switch S01L, e.g. a traditional type of MOS transistor. The input B0 could control the switch S01H directly, and the switch S01L through an inverter I31, for example. The same holds for the transistors M11, M21, M31, the inverters I11, I21, I31, and the switches S11H, S11L, S21H, S21L, S31H, S31L. However, if the logic levels being supplied to the inputs B0, B1, B2, B3 already correspond naturally to the values of potential of the second and third references, these inputs may be connected directly to the control terminals of the floating gate MOS transistors. In this case, the two references of potential are external of the converter, in a sense. In operation, all the control terminals are at first coupled to the second reference, the ground GND in Figure 1. Thus, the drain current developed by all the MOS transistors will be zero because the gate-source voltage is below their threshold voltage, and zero will be the converter output OUT as well. Subsequently in operation, the control terminals of the transistors that correspond to inputs at an active logic state are coupled to the third reference, the supply VCC in Figure 1, and the control terminals of the transistors that correspond to inputs at an inactive logic state remain coupled to the second reference. In this way, some MOS transistors will develop currents which, once added to the input ND and amplified by the circuit AMP, will produce at the output OUT an analog signal whose width is tied to the digital signals to the inputs B0, B1, B2, B3. It often occurs that the inputs of a digital-to-analog converter must have different weights from the output, which weights are typically tied to powers of two. In this case, the value of the threshold voltage of one transistor, e.g. M21, in the set that corresponds to one input, e.g. B2, is such that, for a given gate-source voltage, its drain current is substantially twice as large as the drain current of the transistor M11 corresponding to the next lower weight input B1. This is clearly illustrated by Figure 2, where plots of gate-source voltage VGS vs. drain current ID show possible characteristics of the transistors M01, M11, M21, M31 in a saturated, and hence parabolic, condition, along with their respective threshold voltages Vth0, Vth1, Vth2, Vth3 and drain currents ID0, ID1, ID2, ID3 at a gate-source voltage equal to the supply voltage VCC. A circuit of this type is easy to implement in the integrated form, both alone and in combination with further circuitry, as shown best in Figure 1. It is highly versatile in that the type of the conversion is dictated by the values of the threshold voltages of the floating gate MOS transistors, which can be readily changed by "programming". It is accurate because, especially in the integrated implementation, the performance of the MOS transistors is nearly the same, and any types of errors can be corrected by acting on the threshold voltage values. A further advantage, namely compensation for temperature variations and charge leakage from the floating gates, for example, can be provided by the circuit embodiment discussed below. Referring to Figures 1 and 3, a converter according to this invention may also comprise an additional plurality of floating gate MOS transistors M02, M12, M22, M32 corresponding to the first M01, M11, M21, M31 and having . their source terminals coupled together and to the first reference of potential, the ground GND in the example of Figure 3, their drain terminals coupled together and to inputs ND+ and ND- of the circuit AMP such that the current contributed by this additional plurality of transistors is opposite in sign from the first transistor plurality, and control terminals coupleable, under control by the inputs, to the second and third references, the ground GND and supply VCC, respectively, in the example of Figure 3. Only the last transistor M31 in the first plurality and last transistor M32 in the additional plurality are shown in Figure 3. In this case, the circuit AMP is slightly different from the instance of Figure 1, and has two inputs, a non-inverting input ND+ and inverting input ND-. The drain terminals of the first plurality of transistors are, in this example, connected to the input ND+, and the drain terminals of the additional plurality of transistors are connected to the input -ND, in this example. The control terminals are connected together in pairs, that is, the control terminal of transistor M31 is paired with the control terminal of transistor M32, and so forth, so that the inputs will have the same effect on the corresponding transistors in the two sets. The circuit AMP supplies on the output OUT a signal whose width corresponds to the amplification of the current differential at its inputs. Shown in Figure 4 is a plot of gate-source voltage VGS vs. drain current ID illustrating possible characteristics of the transistors M31 and M32 in the linear or straight condition, along with their respective threshold voltages Vth31 and Vth32, and respective drain currents ID31 and ID32 at a voltage VGS equal to the supply voltage VCC. The activation of the transistor pair M31, M32 by the corresponding input B3 has a contribution on the output OUT which is proportional to the difference between ID31 and ID32. It can be seen that any changes in the voltage VGS and the threshold voltages Vth31 and Vth32 will, so long as equal in magnitude, bear no influence on this contribution. Among the possible sources of changes to the threshold voltages are temperature variations and charge leakage from the floating gates; in addition, any perturbation on either lines connecting the drain terminals to the inputs of the circuit AMP would be suppressed likewise. To maximise the above advantages, it is necessary that all the transistors, M01, M11, M21, M31, M02, M12, M22, M32 in this example, of both pluralities operate within the linear range, and accordingly, that their characteristics be straight lines. As is known, this occurs if the drain-source voltages VDS of all the transistors are lower than the minimum difference between the voltages VGS and the voltages Vth, e.g. of 100 mV. This condition is to be ensured by the circuit AMP. A circuit-wise implementation of the circuit AMP in Figure 3 which meets these requirements is shown in Figure 5. It comprises an operational amplifier OA1 having an inverting input connected to the input ND+, a non-inverting input connected to a reference of potential, VR, and a resistor R1 connected in negative feedback relationship between the output of the amplifier OA1 and its inverting input, an operational amplifier OA2 having an inverting input connected to the input ND-, a non-inverting input connected to a reference of potential, VR, and a resistor R2 connected in negative feedback relationship between the output of the amplifier OA2 and its inverting input, an operational amplifier OA3 having an inverting input connected to the output of the amplifier OA1 through a resistor R3, a non-inverting input connected to the output of the amplifier OA2 through a resistor R4, a resistor R5 connected in negative feedback relationship between the output of the amplifier OA3 and its inverting input, and a resistor R6 connected between its non-inverting input and the ground GND. As is known, the potential at the inverting inputs of the amplifiers OA1 and OA2 is the same as at their non-inverting inputs, namely VR. To provide a voltage VDS of 100 mV for the MOS transistors of both pluralities, it will suffice, therefore, that this value of potential be selected for the reference VR. A suitable simple choice for the values of the threshold voltages of the transistors M02, M12, M22, M32 is the following: all substantially identical, higher than the maximum value of the threshold voltages of the transistors M01, M11, M21, M31 of the first plurality, and lower than the value of the third reference, the supply VCC in this example. It will be possible, of course, to select the value of the threshold voltage of each transistor of the first plurality such that, for a given gate-source voltage, its drain current is substantially twice as large as the drain current of the transistor in the first plurality that corresponds to the next lower input, but both drain currents should be considered as reduced by the drain current of the corresponding MOS transistor in the other plurality. The operation of the converter in Figure 3 is similar to that illustrated by Figure 1. At an initial stage of its operation, the control terminals of the transistors of both pluralities are all coupled to the second reference, and at a subsequent stage of its operation, the control terminals of the corresponding transistors to inputs at the active logic state are coupled to the third reference, and the control terminals of the corresponding transistors to inputs at the inactive logic state remain coupled to the second reference. As previously mentioned, the floating gate MOS transistors can be programmed. For the converter to provide this feature, it is necessary that it also includes program circuitry for the floating gate MOS transistors which can controllably uncouple them from one another and from the amplification circuit, and couple them to references of program potential.

Claims: A digital-to-analog converter having a plurality of inputs (B0,B1,B2,B3) for digital signals and an output (OUT) for an analog signal, and comprising: a) a current amplification circuit (AMP) having at least one input (ND) and an output coupled to the converter output; and b) a plurality of floating gate MOS transistors (M01, M11, M21, M31) corresponding to said plurality of converter inputs and having their source terminals coupled together and to a first reference (GND) of potential, drain terminals coupled together and to said at least one input (ND) of said amplification circuit (AMP), and control terminals coupleable, under control from the inputs in said plurality to different references (GND,VCC) of potential having selected fixed values characterized in that it further comprises: c) another plurality of floating gate MOS transistors (M02,M12,M22,M32) corresponding to said first plurality (M01,M11,M21,M31) and having source terminals all coupled together and to the first reference (GND) of potential, drain terminals all coupled together and to inputs (MD+,ND-) of the amplification circuit (AMP) such that the current contributed by the transistors of said another plurality is opposite in sign from the transistors of said first plurality, and control terminals coupleable, under control by the inputs of said plurality, to the second (GND) and third (VCC) references. A converter according to Claim 1, wherein said different references correspond to second (GND) and third (VCC) references of potential, wherein the values of said first (GND) and second (GND) references correspond to the ground potential, and the value of said third reference (VCC) corresponds to the supply potential. A converter according to either Claim 1 or 2, wherein the value of the threshold voltage of one transistor in said first plurality corresponding to one input is such that, for a given gate-source voltage, its drain current is substantially twice as large as the drain current of the transistor corresponding to the next lower weight input. A converter according to Claim 1, wherein said amplification circuit (AMP) is arranged to operate all of the MOS transistors (M01,M11,M21,M31,M02,M12,M22,M32) of said pluralities in the linear range. A converter according to Claim 1, wherein the values of the threshold voltages of the transistors in said another plurality (M02,M12,M22,M32) are all substantially identical, higher than the maximum value of the threshold voltages of the transistors in said first plurality (M01,M11,M21,M31), and lower than the value of said third reference (VCC). A converter according to one of the preceding claims, wherein, at an initial stage of its operation, all the control terminals are coupled to a second reference (GND), and at a subsequent stage of its operation, the control terminals of the transistors corresponding to inputs at the active logic state are coupled to a third reference (VCC) and the control terminals of the transistors corresponding to inputs at the inactive logic state remain coupled to the second reference (GND). A converter according to Claim 1, further comprising program circuitry for the floating gate MOS transistors operative to controllably uncouple them from one another and from the inputs of the amplification circuit and to couple them to references of program potential.

Inventors: CANEGALLO ROBERTO, CHINOSI MAURO, GOZZINI GIOVANNI, KRAMER ALAN, LEONG PHILIP, ROLANDI PIER LUIGI, SABATINI MARCO, CANEGALLO, ROBERTO, CHINOSI, MAURO, GOZZINI, GIOVANNI, KRAMER, ALAN, LEONG, PHILIP, ROLANDI, PIER LUIGI, SABATINI, MARCO, Kramer, Alan, c/o SGS-Thomson Microelec. S.r.l., Leong, Philip, c/o SGS-Thomson Microelec. S.r.l., Sabatini, Marco, c/o SGS-Thomson Microelec. S.r.l.
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1996
Main classification: H03M1
IPC codes: H03M1