BARREL SHIFTER

Abstract: A barrel shifter comprising: an n-bit by n-bit transistor array arranged into n rows an n colums, wherein the source of a transistor in one row is connected to the source of a transistor in the next row; a first plurality of multiplexors, each having a first and a second input and an output, wherein the first input is coupled to a corresponding bit of an operand, the second input is coupled to a first control signal, and the output is coupled to one transistor in each row of the array beginning with a transistor in a corresponding bit position in the first row and continuing with transistors in ascending bit positions for each subsequent row; a second plurality of multiplexors each having inputs and an output, each multiplexor selecting one of three inputs depending on the data length; and a third plurality of multiplexors, each having a first and a second input and an output, wherein the first input is coupled to a corresponding bit output of the second multiplexor, the second input is coupled to a second control signal, and the output is coupled to one transistor in each row of the array beginning with a transistor in a corresponding bit position in the second row and continuing with transistors in ascending bit positions.

Description: BARREL SHIFTER BACKGROUND OF THE INVENTION The present invention relates to the design of a barrel shifter utilizable in a microprocessor execution unit architecture. SUMMARY OF THE INVENΗON A barrel shifter is disclosed which can shift or rotate data of various sizes, such as 8-bit, 16-bit or 32- bit. A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description of the invention and accompanying drawings which set forth an illustrative embodiment in which the principles of the invention are utilized. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a functional block diagram of a barrel shifter. Figure 2 is a schematic diagram of a barrel shifter. DETAILED DESCRIPTION OF THE INVENΗON A generalized block diagram of a barrel shifter 10 according to the present invention is illustrated in Figure 1. An operand is presented to the barrel shifter on input 20 and the result is presented on output 22. Signals which control how much the operand is rotated are presented to the barrel shifter at input 24, and these signals are translated from a binary encoded value of the rotate amount received at input 26 of decoder 25. The barrel shifter 10 performs multi-bit shift and rotate operations compatible with the x86 instruction set. Referring now to Figure 2, a more detailed schematic diagram of barrel shifter 10 is illustrated. In die preferred embodiment, the barrel shifter includes a 32 by 32 transistor array, but in Figure 1, only a 4 by 4 portion of the transistor array 100 is shown. Further, the preferred embodiment performs left shifts only, therefore, a shift right instruction will be translated to a complementary shift left instruction. Each bit inO, inl, in2, in3 of the operand is presented to a 32 bit 2:1 multiplexor, respresented schematically as a collection of 2:1 input gates 102a, 102b, 102c, 102d, respectively. Each input gate has a second input CRTL-A, which is a control signal from a control logic unit in the microprocessor system (not shown) that provides a value for the barrel shifter to shift into the most significant bit of the operand. The enable signal SELECT-A for each input gate is determined according to which microcoded instruction is being executed by the control logic, such as SAR, SHR, or RRC. Each output bit from the multiplexor is connected to one transistor in each of the 32 rows of array 100 in ascending bit positions, thereby forming a connnection diagonally across the array, i.e., in the second row, the bit is moved left one place, in the third row, the bit is moved left two places, and so on. The operand is also connected to respective inputs of a 31 bit 3:1 multiplexor 104. The most significant bit is either in7, inl5, in31, depending on the data type which is indicated by control signals ROTATE_BYTE, ROTATE_WORD, OR ROTATE_DWORD. As used herein, a byte is 8 bits of data, a word is 16 bits of data, and a dword is 32 bits of data. Bytes and words have their data shifted left to the most significant places and die less significant bits are filled with zeros. The most significant bit is output on line 106a. Likewise, the second most significant bit is selected from the group of three inputs in6, inl4, in30, and so forth for all bit positions. A second multiplexor group is formed by input gates 106a, 106b, 106c. Each input gate has a second input CRTL-B which provides a value from the control logic for the barrel shifter to shift into the least significant bit of the operand. The enable signal SELECT- B for each input gate is determined according to which microcoded instruction is being executed by the control logic, such as SHR, SHL, or RLC. Each output bit from the multiplexor is connected to one transistor in each of 31 rows (starting with the second row) of array 100 in ascending bit positions, thereby forming a connnection diagonally across the array, i.e., in the third row, the bit is moved left one place, in the fourth row, the bit is moved left two places, and so on. The barrel shifter 10 may be used to carry out multi-bit shift and rotate operations. For example, an instruction to shift an operand "FEDCBA98" 12 places to the right will be executed as a shift left of 20 places. The operand is placed into both multiplexors 101, 104 and shifted left 20 places. This results in the most significant 12 bits of the output 22 coming from the least significant 12 bits which are input to multiplexor 101, and the least significant 20 bits of the output 22 coming from the most significant 20 bits of the data coming from multiplexor 104. The correct answer "000FEDCB" is thus obtained. The invention embodiments described herein have been implemented in an integrated circuit which includes a number of additional functions and features which are described in die following co-pending, commonly assigned patent applications, the disclosure of each of which is incorporated herein by reference: U.S. patent application Serial No.08/ , entitled "DISPLAY CONTROLLER CAPABLE OF ACCESSING AN EXTERNAL MEMORY FOR GRAY SCALE MODULATION DATA" (atty. docket no. NSC1-62700); U.S. patent application Serial No. 08/ , entitled "SERIAL INTERFACE CAPABLE OF OPERATING IN TWO DIFFERENT SERIAL DATA TRANSFER MODES" (atty. docket no. NSC1-62800); U.S. patent application Serial No. 08/ , entitled "HIGH PERFORMANCE MULTIFUNCΗON DIRECT MEMORY ACCESS (DMA) CONTROLLER" (atty. docket no. NSC1- 62900); U.S. patent application Serial No. 08/ , entitled "OPEN DRAIN MULTI-SOURCE CLOCK GENERATOR HAVING MIMMUM PULSE WIDTH" (atty. docket no. NSC 1-63000); U.S. patent application Serial No.08/ , entitled "INTEGRATED CIRCUIT WITH MULTIPLE FUNCTIONS SHARING MULTIPLE INTERNAL SIGNAL BUSES ACCORDING TO DISTRIBUTED BUS ACCESS AND CONTROL ARBITRAΗON" (atty. docket no. NSC1-63100); U.S. patent application Serial No. 08/ , entitled "EXECUTION UNIT ARCHITECTURE TO SUPPORT x86 INSTRUCTION SET AND x86 SEGMENTED ADDRESSING" (atty. docket no. NSC1-63300); U.S. patent application Serial No. 08/ , entitled "BARREL SHIFTER" (atty. docket no. NSC1- 63400); U.S. patent application Serial No. 08/ , entitled "BIT SEARCHING THROUGH 8, 16, OR 32-BIT OPERANDS USING A 32-BIT DATA PATH" (atty. docket no. NSC 1-63500); U.S. patent application Serial No. 08/ , entitled "DOUBLE PRECISION (64-BIT) SHIFT OPERATIONS USING A 32-BIT DATA PATH" (atty. docket no. NSC1-63600); U.S. patent application Serial No. 08/ , entitled "METHOD FOR PERFORMING SIGNED DIVISION" (atty. docket no. NSC1- 63700); U.S. patent application Serial No. 08/ , entitled "METHOD FOR PERFORMING ROTATE THROUGH CARRY USING A 32-BIT BARREL SHIFTER AND COUNTER" (atty. docket no. NSC1-63800); U.S. patent application Serial No. 08/ , entitled "AREA AND TIME EFFICIENT FIELD EXTRACTION CIRCUIT" (atty. docket no. NSC1-63900); U.S. patent application Serial No. 08/ entitled "NON-ARTTHMETICAL CIRCULAR BUFFER CELL AVAILABILITY STATUS INDICATOR CIRCUIT" (atty. docket no. NSC1-64000); U.S. patent application Serial No. 08/ , entitled "TAGGED PREFETCH AND INSTRUCTION DECODER FOR VARIABLE LENGTH INSTRUCTION SET AND METHOD OF OPERATION" (atty. docket no. NSC1-64100); U.S. patent application Serial No. 08/ , entitled "PARTITIONED DECODER CIRCUIT FOR LOW POWER OPERATION" (atty. docket no. NSC1-64200); U.S. patent application Serial No. 08/ entitled "CIRCUIT FOR DESIGNATING INSTRUCTION POINTERS FOR USE BY A PROCESSOR DECODER" (atty. docket no. NSC 1-64300); U.S. patent application Serial No.08/ , entided "CIRCUIT FOR GENERATING A DEMAND-BASED GATED CLOCK" (atty. docket no. NSC1-64500); U.S. patent application Serial No.08/ , entided "INCREMENTOR/DECREMENTOR" (atty. docket no. NSC1-64700); U.S. patent application Serial No.08/ , entitled "A PIPELINED MICROPROCESSOR THAT PIPELINES MEMORY REQUESTS TO AN EXTERNAL MEMORY" (atty. docket no. NSC1-64800); U.S. patent application Serial No. 08/ , entitled "CODE BREAKPOINT DECODER" (atty. docket no. NSC 1-64900); U.S. patent application Serial No. 08/ , entided "TWO TIER PREFETCH BUFFER STRUCTURE AND METHOD WITH BYPASS" (atty. docket no. NSC1-65000); U.S. patent application Serial No. 08/ , entided "D STRUCΗON LIMIT CHECK FOR MICROPROCESSOR" (atty. docket no. NSC1-65100); U.S. patent application Serial No. 08/ , entided "A PIPELINED MICROPROCESSOR THAT MAKES MEMORY REQUESTS TO A CACHE MEMORY AND AN EXTERNAL MEMORY CONTROLLER DURING THE SAME CLOCK CYCLE" (atty. docket no. NSC 1-65200); U.S. patent application Serial No. 08/ , entided "APPARATUS AND METHOD FOR EFFICIENT COMPUTATION OF A 486™ MICROPROCESSOR COMPATIBLE POP INSTRUCTION" (atty. docket no. NSC 1-65700); U.S. patent application Serial No.08/ , entitled "APPARATUS AND METHOD FOR EFFICIENTLY DETERMINING ADDRESSES FOR MISALIGNED DATA STORED IN MEMORY" (atty. docket no. NSC 1-65800); U.S. patent application Serial No. 08/ , entitled "METHOD OF IMPLEMENTING FAST 486™ MICROPROCESSOR COMPATIBLE STRING OPERATION" (atty. docket no. NSC1-65900); U.S. patent application Serial No. 08/ , entided "A PIPELINED MICROPROCESSOR THAT PREVENTS THE CACHE FROM BEING READ WHEN THE CONTENTS OF THE CACHE ARE INVALID" (atty. docket no. NSC 1-66000); U.S. patent application Serial No. 08/ , entitled "DRAM CONTROLLER THAT REDUCES THE TIME REQUIRED TO PROCESS MEMORY REQUESTS" (atty. docket no. NSC1-66300); U.S. patent application Serial No. 08/ , entided "INTEGRATED PRIMARY BUS AND SECONDARY BUS CONTROLLER WITH REDUCED PIN COUNT" (atty. docket no. NSC 1-66400); U.S. patent application Serial No. 08/ , entitled "SUPPLY AND INTERFACE CONFIGURABLE INPUT/OUTPUT BUFFER" (atty. docket no. NSC 1-66500); U.S. patent application Serial No. 08/ , entitled "CLOCK GENERATION CIRCUIT FOR A DISPLAY CONTROLLER HAVING A FINE TUNEABLE FRAME RATE" (atty. docket no. NSC1-66600); U.S. patent application Serial No. 08/ , entitled "CONFIGURABLE POWER MANAGEMENT SCHEME" (atty. docket no. NSC1-66700); U.S. patent application Serial No. 08/ , entitled "BIDIRECTIONAL PARALLEL SIGNAL INTERFACE" (atty. docket no. NSC 1-67000); U.S. patent application Serial No. 08/ , entitled "LIQUID CRYSTAL DISPLAY (LCD) PROTECTION CIRCUIT" (atty. docket no. NSC1-67100); U.S. patent application Serial No. 08/ , entitled "DSf-CIRCUIT EMULATOR STATUS INDICATOR CIRCUIT" (atty. docket no. NSCl-67400); U.S. patent application Serial No. 08/ , entitled "DISPLAY CONTROLLER CAPABLE OF ACCESSING GRAPHICS DATA FROM A SHARED SYSTEM MEMORY" (atty. docket no. NSC1-67500); U.S. patent application Serial No.08/ , entided "INTEGRATED CIRCUIT WITH TEST SIGNAL BUSES AND TEST CONTROL CIRCUITS" (atty. docket no. NSC1-67600); U.S. patent application Serial no. 08/ , entitled "DECODE BLOCK TEST METHOD AND APPARATUS" (atty. docket no. NSCl-68000). It should be understood tiiat the invention is not intended to be limited by the specifics of the above- described embodiment, but rather defined by die accompanying claims.

Claims: WHAT IS CLAIMED IS: 1. A barrel shifter, comprising: an n-bit by n-bit transistor array arranged into n rows and n columns, wherein the source of a transistor in one row is connected to the source of a transistor in the next row; a first plurality of multiplexors, each having a first and a second input and an output, wherein the first input is coupled to a corresponding bit of an operand, the second input is coupled to a first control signal, and the output is coupled to one transistor in each row of the array beginning with a transistor in a corresponding bit position in the first row and continuing with transistors in ascending bit positions for each subsequent row; a second plurality of multiplexors each having inputs and an output, each multiplexor selecting one of tiiree inputs depending on die data length; and a third plurality of multiplexors, each having a first and a second input and an output, wherein the first input is coupled to a corresponding bit output of the second multiplexor, the second input is coupled to a second control signal, and the output is coupled to one transistor in each row of the array beginning with a transistor in a corresponding bit position in die second row and continuing with transistors in ascending bit positions.

Inventors: TAM HONAKI J, THOMSON THOMAS W, TAM, HONAKI, J., THOMSON, THOMAS, W.
Applicants: NAT SEMICONDUCTOR CORP, NATIONAL SEMICONDUCTOR CORPORATION
Application year: 1996
Main classification: G06F5
IPC codes: G06F5