Drive system for a brushless motor employing predefined profiles of driving currents stored in a nonvolatile memory

Abstract: The torque characteristic of an electrically driven brushless motor may be optimized by driving the phase windings of the motor with predefined, digitized and stored current or voltage profiles. Appropriate sequences of digital samples of the predefined driving profile are sequentially read from a nonvolatile memory where they are permanently stored to drive, through a DAC, the relative winding of the motor in synchronism with a signal representative of the rotor position.

Description: The present invention relates to techniques for driving an electronically switched DC motor, commonly referred to as "brushless". Electronically switched DC motors are used in innumerable control and regulation applications and also as mass memory drive systems in the case of rotating supports such as hard disks, floppy disks, optical disks, CD-ROMs as well as in case of linear supports such as tape streamers and the like. Commonly these motors are polyphase motors in a "star" configuration. Quite common is the case of a motor having three phase windings connected in a star configuration and defining six different switching phases and a P number of poles. In this case, there will be a number 3*P of equilibrium points in a complete revolution of the rotor. In the present text, each excitation phase will be indicated according to a standard rotation by two capital letters. The first capital letter (for example, A, B or C) defines the winding through which the current conventionally flows from the respective supply terminal towards the star center (CT) and the second capital letter, preceded by the sign (!), designates the winding through which the current, conventionally coming from the star center, flows toward the supply terminal of the relative winding. For instance, the scheme of the excitation phase A!B is shown in Fig. 1. These brushless motors are commonly driven using an integrated circuit whose output stage is represented by a polyphase full-wave bridge circuit, which in the case of a three-phase motor may employ six bipolar (BJT) or field effect transistors (MOS) power transistors. The motor current is linearly controlled through a transconductance loop. During a certain switching phase of the motor, the "sourcing" power transistor is forced into full conduction (that is to saturation in case of an MOS device) whereas the "sinking" power transistor operates as an element of transconductance, according to the scheme of Fig. 2, which refers to the use of MOS type power devices. With reference to Fig. 2, the motor current may be expressed as follows: Im otor = Vref Gv * Rs where Vref is the control voltage supplied by the motor's speed regulation loop, Gv is the voltage gain of the sensing amplifier while Rs is the current sensing resistor. In the prior art, the voltage Vref is regulated at a certain level by the regulation loop in order to regulate the current absorbed by the motor in maintaining a certain speed. Of course, the regulation loop acts on the Vref value by varying its instantaneous value about a certain mean value to compensate for instantaneous load-torque variations. For this reason, during each excitation phase, the motor current is regulated to a certain level, substantially to a constant level (± Imotor) as shown in the diagram of Fig. 3. Fig. 4A shows the torque curves for a constant Imotor current for the six different excitation phases of the case taken into consideration. By increasing the current, the peak level of the torque curves increases but their form remains substantially unchanged. Fig. 4B shows the torque characteristics of the motor when the phase switchings take place at the optimal instants, identified as T1, T2, ..., T6. These optimal switching instants may be determined by using the signals generated by dedicated rotor position sensors for example Hall effect cells or by monitoring the well known cyclic effect of the generation of back-electromotive-forces (BEMF) in the windings of the motor, sensing the crossing instants of a certain reference level, for example by the use of zero-crossing comparators. It is evident from the diagram of Fig. 4B that by forcing a constant current through the motor windings, a torque "ripple" cannot be avoided. In practice, the diagram of Fig. 4B represents the best possible driving condition in this respect, that is where the phase switching occur at the optimal instants. EP-A-0 324 396 discloses a system for driving a brushless motor according to a drive profile reconstructed from a digitized halfwave, the sample values of which are stored in a memory. The system resets and resynchronizes every electric revolution of the motor. US-A-5,469,215 discloses a system for reducing the torque ripple in driving a brushless motor by employing a "look-up table" of predefined compensation values to be summed or subtracted to the requested torque value in function of the elaboration of the data representative of the position, speed and requested torque. The main objective of the present invention is that of providing a driving technique capable of reducing and minimizing the torque "ripple". This object is achieved with a method as claimed in claim 1. The technique of the invention consists essentially in modelling current profiles (as opposed to constant current levels) to be forced through the motor windings during the succession of excitation phases to eliminate or minimize the resulting torque "ripple". According to an aspect of the invention such predefined current profiles are digitized and stored in a nonvolatile memory and the forcing of a current corresponding to the selected profile, through the respective motor winding, occurs by reading the digitized values from the memory synchronously with the instantaneous position. According to an important embodiment of the invention, the following description refers to a system as claimed in claim 11, wherein as many profiles as there are motor windings are stored. This permits to adapt independently each profile to the relative winding in order to compensate any residual torque discrepancy as generated by each excitation phase as may be due to mechanical asymmetries occurred during the construction. If such a requisite is not indispensable as in many applications it would be then only one profile can be stored or even just a quarter of the entire period of the required profile and the full profile and/or out-of-phase identical profiles for the various windings be reconstructed by symmetry using a dedicated reconstruction logic circuitry. Therefore, according to a fundamental aspect of the invention, the current flowing in each phase winding of the motor is forced therethrough according to a respective profile which is predefined and stored, by substantially synchronizing the scanning of the digitized profile with a timing signal representative of the rotor position. Such a timing signal may be obtained according to any of the known techniques, for example using one or more position sensors, for instance Hall-effect sensors, or a dedicated circuitry capable of monitoring and sensing certain significative instants of the cyclic (roughly sinusoidal) evolution of the BEMF signals that are induced on the phase windings of the motor. Of course the invention assumes that the power stages that force the current through the motor windings be able to produce an output that is a perfect replica of the wave form of a certain driving input signal corresponding to the instantaneous value of one of said predefined and nonvolatily stored profiles, as read from the memory (according to a typical current mode driving and controlling scheme). As evident to a person skilled in the art, the system of the invention will be useful even when there is no need of exerting a current control in the final output stage. In this case reference would not longer be made to current profiles but rather to voltage profiles which are forced across the two ends of each motor winding (according to a typical voltage mode driving scheme). A voltage-mode driving scheme will presume a knowledge of the ratios V MI /I MI where V MI is the voltage measured on a winding while IMI is the resulting current. Of course, in this case, predefined voltage profiles will be stored in lieu of the current profiles, in order to produce currents that minimize or eliminate the torque ripple. In the ensuing description, reference will be made, for simplicity, to current profiles and to a current-mode control taking for granted the above mentioned interchangeability between a driving current profile and a driving voltage profile and also between a current-mode control and a voltage-mode control. According to an important embodiment of the present invention, the driving current or voltage profiles, stored in a digital form in the memory, are profiles that can be represented as a sum of Fourier harmonics of a main frequency and that the sum of the instantaneous values of the distinct profiles is substantially constant to prevent current recirculation phenomena in the output power stages that drive the motor windings, which recirculation may cause a loss of control of the regulation. According to an architectural aspect, each output power stage is driven by the signal output by a digital-to-analog converter (DAC) at the input of which are sequentially applied the digital values corresponding to as many samples of the predefined and digitized current profile, stored generally in a buffer or in a nonvolatile memory, in function of a certain excitation phase of the motor. In the case the final stage be substantially represented by the DAC, the analog level corresponding to the digital sample of the current profile is forced directly through the respective winding. Conversely, if a PWM type control must be implemented in the final stage, then the architecture of the invention may include a BYTE-to-PWM signal converter that generates a PWM signal from the digital value corresponding to the current profile sample. In practice, in the case of a three phase motor, that is a motor having three phase windings, three current profiles may be predefined and stored. These current profiles produce through the respective DACs, three analog signals, out of phase by 120°, that drive the three output power stages that force the respective currents through the three windings of the motor, according to a six-phase switching scheme of the motor. The possibility of modelling with a relatively high freedom of choice the profiles of the currents that are forced through the windings of the motor permits to eliminate or minimize any residual "ripple" amplitude of the torque characteristic of the motor. The various aspects and advantages of the invention will become even clearer through the following description of some important embodiments and by referring to the attached drawings, wherein: Figure 1 shows the meaning of the notation used in the present context; Figure 2 is a prior art scheme of a transconductance current control loop as described above; Figure 3 shows the waveforms of the currents that flow in the three phase windings under control of the respective current regulation loops, according to a known technique; Figure 4A shows the torque curves relative to the six switching phases of the motor in correspondence with the currents waveforms of Fig. 3; Figure 4B highlights the torque characteristic of the motor when the phase switchings occur at optimal instants; Figure 5 shows a sinusoidal current profile subdivided into six sequences of N samples each, stored in a nonvolatile memory; Figure 6 is a layout of the circuit that synchronizes the reading of each of the six sequences of N samples each into which is subdivided a certain current profile, digitized and stored in a nonvolatile memory, with a signal indicative of the position of the motor's rotor; Figure 7 is a detailed circuit diagram of the block that generates the synchronization signals of the diagram of Fig. 6; Figures 8A and 8B illustrate some significative operation conditions of the system of the invention; Figures 9A and 9B show the input and output signals of the block of Fig. 7 in relation to the two cases of Figures 8A and 8B; Figure 10 is a diagram showing the diagram of the current in a motor winding when the control is taken over, at the end of a start-up routine, by the driving system of the invention. The following description of important practical embodiments of the invention has the only purpose of illustrating some ways in which the invention can be produced. A more general definition of the invention is defined in the claims 1 and 11 attached to the present description. One of the main aspects of the invention is that of forcing through the windings of the motor a current whose profile or waveform follows exactly a certain preestablished profile that is stored in a digitized form in a nonvolatile memory, like for example an EPROM or EEPROM memory. The sum of the instantaneous values of the forced currents (that is of the profiles relative to the distinct windings) is constant. As a consequence, one of the main problems of so driving the motor is that of ensuring a perfect synchronism of the driving process and in practice of the scanning of each sequence of stored values along with the instantaneous position of the rotor, in order to ensure the production of the maximum torque and in maintaining this synchronism during each phase of operation, that is during phases of acceleration, revolution at a constant speed and deceleration. Satisfaction of such a stringent requisite is ensured by a circuit capable of reading from the memory the instantaneous value of the current to be forced through the motor windings and of effectively forcing such currents through the windings synchronously with a signal representative of the position of the rotor. This signal may be generated by a decoding and processing circuitry of signals generated by dedicated transducers or sensors, for instance by Hall-effect sensors, or by a circuit able to derive an information of the rotor's position by monitoring the BEMFs induced on the motor's windings. DESCRIPTION OF PREFERRED EMBODIMENTS Let us consider, by way of example, the case of a motor having three phase windings connected in a star configuration, for which a complete switching cycle includes six different excitation phases, and the driving of which be effected according to a current control mode. Therefore, the preestablished wave profile of the current to be forced through the phase windings of the motor which, by way of exemplification may be chosen to be substantially sinusoidal, as shown in Fig. 5, is subdivided into six portions of equal "duration" in terms of the arc of circumference travelled by the rotor or, in other words, into six successive sequences Sx(x=1,6), each composed of a number N of samples. That is to say, each of the six portions into which is subdivided the entire sinusoidal profile is practically sampled in a number N of samples, whose value expressed in digital form, that is in words of a certain number of bits (for example 8 or more bits), can be stored in a nonvolatile manner in a dedicated register or nonvolatile memory. Obviously, the setting of the number N of samples that are stored for each of the sequences into which is subdivided the entire current profile is an important factor because from it depends the behavior of the other functional blocks that constitute the driving system of the invention, as will become evident through the ensuing description. According to the embodiment of Fig. 6, the ZCSSB block represents a logic circuit capable of sequentially produce a "zero crossing" ZC signal from each of the three analog BEMF signals, induced in the three motor windings by the rotor's rotation or otherwise produced by Hall-effect sensors. The circuit sequentially selects one of the three inputs and, upon recognizing the significative instant, forces to a high logic state the output ZC signal. Upon assertion of the switching to a high logic stage of the ZC signal, the ZC signal is forced back to a low logic state as here-in-below described and as shown in the diagrams of Figures 9A and 9B. Tc is the time interval between two successive assertions of the switching to a high state of the ZC signal and the TTC signal is a signal with the same period of the ZC signal but with a 50% duty-cycle. The ZCSSB block may have any of the suitable known architectures that are commonly used in brushless motor for driving systems. For example, the European Patent No. 0 429 412, in the name of the same applicant, discloses a circuit suitable to be used in the ZCSSB block of the present system. Each of the six sequences Sx(x=1,6), of N samples each, that make up each of the three profiles stored in the respective nonvolatile memory buffers, as shown in Fig. 6 by the blocks M1, M2 and M3, must match, on a time base, the last time interval Tc measured. In other words, the system should theoretically have the capacity of ensuring that the time lapsing between the instant of forcing the first sample of the sequence Sx(x=1,6) and the instant of ending the forcing of the last sample of the same sequence, matches the time Tc taken by the scanning of the preceding sequence. By defining as T SAMPLE the forcing time of each sample of a sequence, then N*T SAMPLE =Tc . By referring to Fig. 5, when the last sample (i.e. the sample 6N-1) of the last sequence is forced, the circuit is reset in a way that the next sample that is going to be forced is again the first sample of the whole stored profile. An important aspect of the driving system of the invention consists in that the synchronizing of the scanning of a sequence with the position signal ZC takes place at the end of each sequence. An alternative possibility would be that of resynchronizing the scanning not at the end of each sequence but rather every K sequences (K=1,6). In the ensuing description it is assumed to force the synchronization at the end of each sequence (K=1). Therefore, when the forcing time of the last sample of each sequence has elapsed, the first sample of the next sequence is forced in synchronism with the ZC signal. Two conditions may occur: 1) According to a first condition, at the end of the forcing time of the last sample of a certain sequence, the ZC signal has not been asserted yet. This means that the relative sequence of N samples (x=1,6) has terminated too early if compared to the optimal switching instant corresponding to the rising front of the new ZC pulse. This condition occurs when the motor decelerates so that the interval Tc between two consecutive switching events must increase, compared to the preceding interval. This condition is schematically represented in Fig. 8A. In this case the driving system of the invention maintains the same current corresponding to the last sample Sx of the current sequence until a new ZC signal is asserted. When a new rising front occurs and a new ZC pulse is eventually asserted, the circuit is reset by the LB block and the successive sequence S(x+1) of samples is started beginning from its first sample. 2) According to another operation condition, when the motor is accelerating and the current Tc interval is shorter than the preceding one, the new rising front and eventual assertion of a new ZC pulse occur before all the N samples of the current sequence Sx are "discharged". This situation is represented in the diagram of Fig. 8B. In this case, the ZC signal is reset to a low logic state by the LB block and the successive sequence of N samples is made to begin not from the first stored sample of the sequence, rather one or more initial samples of the sequence are skipped so to begin forcing a current in the relative windings of the motor corresponding to a certain M th sample of the new sequence of N samples, where M corresponds to the content of a write/read register.Therefore, the new sequence of N samples will be composed in practice of a N-M number of samples in order to adapt the driving to a shorter Tc time interval than that last measured and relative to the last discharged sequence of samples.In this way the system of the invention automatically resynchronizes itself with the instants of assertion of a new ZC pulse. An alternative embodiment could require that M instead of identifying the number of samples of the next sequence to be skipped identify a percentage of the last determined time interval Tc and that the corrected time into which effect the scanning of the successive sequence be: T c = Tc - M • Tc 100 In this case, initial samples are no longer skipped, instead a faster ( Tc 〈 Tc ) scanning of the next sequence is performed. Other embodiments could be based on recognizing that M may be assumed as dependent on the rotation speed of the rotor and on the measured Tc, that is: T c = Tc - M ( Tc )• Tc 100 This because during a quick acceleration M(Tc) must be relatively high to ensure a quick recovery of the sequence duration whereas, during steady state operation, M(Tc) should be relatively small because the Tc variations to be compensated would be small. A typical M(Tc) characteristic is shown in Fig. 11. A further possibility may imply that upon the occurrence of a "zero crossing" event in advance, the coming of the current sequence be interrupted and the scanning of the successive sequence be immediately started. By reference again to the diagram of Fig. 6, each of the three buffers (nonvolatile memories) M1, M2 and M3 contains the 6*N samples that constitute the respective entire profile. The three profiles may be stored in the respective registers M1, M2 and M3 so as to be read as if spaced by 120° from each other and the three buffers M1, M2 and M3 may be addressed in parallel by the AØ-A7 signals originating from the LATCH L2. This LATCH L2 provides the row addresses. When the LE1 signal is high, the LATCH L2 is "transparent" and the signals present on the PAØ-PA7 lines are transferred to the AØ-A7 lines. At power-on, the LE1 signal is forced high for a short period of time, sufficient for the LATCH L2 to set itself in a first configuration (00h) to be forced on the AØ-A7 lines. C1 constitutes the addresses counter. To each rising front of the CLOCK signal the address is incremented by a unit. At the end of each of the Sx th sequences (x=1,6), the !LOAD signal is forced low by the LB block to permit a parallel loading of the counter with the data present on the PPAØ-PPA7 lines, that is with the first sample of the successive sequence S(x+1) th . At power-on, the signal NOTINIT resets the contents of the counter C1, forcing the datum 00h on the PAØ-PA7 lines. The counter C1 is also reset by the comparator COMP2 when the latter recognizes the last sample of the last sequence, that is when it recognizes the relative datum on the PAØ-PA7 lines. Really, the last sample of the last sequence would be 6*N-1 because the first sample of the first sequence is identified by Ø. The comparator COMP1 forces low the signal !(P=N) when the current datum on the PAØ-PA7 lines is equal to the datum present on the lines NAØ-NA7. In practice, this signal goes low at each last sample of each of the six sequences. The LATCH L1 triggers when the signal LE2 generated by the LB block is high, that is, on occasion of the first sample of a sequence that follows the one just completed. The adder S1 adds the data present on the NNØ-NN7 lines to the data present on the PAØ-PA7. The adder S2 adds the data present on the NAØ-NA7 lines to the data present on the MØ-M7. The data MØ-M7 are enabled only when the control signal MEN, produced by the LB block, is high. The circuital block PLL has the task of multiplying by a factor of 2*N the frequency, using as reference signals the TTC signal together with the signal produced by a frequency divider block by a factor 2*N, to which the output signal PLLOUT produced by the block PLL is fed. Thus, the output signal PLLOUT is equivalent to 2*N times the frequency of the TTC signal. In practice, by forcing a new sample of the stored current profile at each assertion of the output signal PLLOUT, a number 2*N of samples will turn out to have been forced within the time interval Tc, being the TTc period equal to Tc. In the embodiment shown in the figure, the system requires a division by 2*N rather than by N, in order to implement the necessary signals synchronization in a way that the frequency that really feeds the system of the invention is generated by the LB block and given by: CLOCK = PLLCLK/2 in which PLLCLK is equal to PLLOUT when the START signal is low. The block PS contains the power stages that drive the three windings of the motor. Each of the three output power stages may be realized with a power MOS or with a bipolar junction transistor and provided with a current control loop circuit, according to any of the known configurations, as for example the one depicted Fig. 2. Each transconductance output stage practically translates the three analog driving signals VREF1, VIREF2 and VREF3, output by the respective digital/analog converters DAC1, DAC2 and DAC3, forcing corresponding currents I1, I2 and I3 through the motor's windings. The DAC1, DAC2 and DAC3 are three converters that translate into corresponding analog values VREF1, VREF2 and VREF3 the samples, expressed in words of n bit, as read from the respective buffers M1, M2 and M3. The three converters DAC1, DAC2 and DAC3 are controlled by the CONTROL signal supplied by the SPEED CONTROL block that implements a speed regulation loop. The control signal acts upon the input reference level of the three converters. The other control signal START forces the output of the three converters to a predefined starting value in function of a certain start-up routine of the motor, according to one of the many known techniques that are commonly used. An external assertion (switching) of the GO command enables the execution of a starting routine of the motor. This routine maintains control of the three converters DAC1, DAC2 and DAC3 by asserting the START signal. During the start-up routine, the motor is accelerated (of course the start-up routine may be defined in function of the operator requirements) while the PLL block is locking itself. Once locking is attained, the PLL block sends the LOCKED signal to the START UP block that is carrying out the start-up routine. From that moment the START UP block is enabled to switch the system lines DxO, Dx7 (where x=1,3) to the corresponding inputs of the three DAC1, DAC2 and DAC3 converters. Fig. 10 is a diagram showing the moment in which the circuit that supervises the execution of the start-up routine transfers the control to the DAC1, DAC2 and DAC3 converters. By associating the phase winding A to the DAC1 and VREF1, the phase winding B to the DAC2 and to VREF2 and phase winding C to the DAC3 and VREF3, upon the sensing of the "zero crossing" of the BEMF induced on the winding C, the counter C1 is enabled to count by increments because the LB block begins to output the timing CLOCK signal. This occurs because the START signal goes low thus making AND1 transparent so that the PLLCLK signal is equal to the PLLOUT signal. When the PAØ-PA7 lines reach the decimal value N, the comparator COMP1 forces low the signal !( P=N). The LB block forces low the signal !LOAD, which allows, at the successive rising front of the CLOCK signal, the loading in the counter C1 of the data currently present on the PPAØ-PPA7 lines. In the case the motor be braking when the signal !LOAD goes low, the ZC signal will not yet be asserted, as shown in the diagram of Fig. 9A. In this case, the signal MEN remains low and the decimal value N is down-loaded in the counter C1. When the motor is accelerating, in the precise moment in which the signal !LOAD goes low, the signal ZC is already high, as highlighted in the diagram of Fig. 9B. In this case, the signal MEN is asserted by the LB Block and the decimal value N+M is down-loaded into the counter C1. During the time in which the signal !LOAD is low, the signal LE1 is forced low so that the converters DAC1, DAC2 and DAC3 are not updated. In both cases, upon the assertion of the ZC signal, the signal !LOAD is set by the successive pulse LE which is internally generated and used by the LB block. When !LOAD is asserted, the LE1 signal tracks the LE signal, allowing the updating of the DAC1, DAC2 and DAC3 converters. Finally, the signal LE2 is also forced high at first and then forced low, in order to store in LATCH L1 the first value of the new sequence of samples that will be 2N or 2N+M (according to what has already been described above in relation to the diagrams of Figures 8A and 8B). This situation repeats itself until the last sample is transferred onto the PAØ-PA7 lines. At this point, the comparator COMP2 resets the system to the first sample of the first sequence of samples. The LB block generates all synchronization and control signals required by the system, according to the functioning above illustrated. A viable circuital embodiment of the LB block is shown in Fig. 7, using a standard notation; that is one of immediate understanding for a person ordinarily skilled in the art. Of course, the necessary synchronization and control signals of the system could also be generated by using a circuit or logic circuits equivalent to those illustrated, by way of example, in Fig. 7.

Claims: A method of driving a polyphase brushless motor consisting in defining, digitizing and storing in a nonvolatile memory a current or voltage drive profile for each phase winding of the motor, in the form of digital words of a certain number of bits representing sample values of said profiles, and forcing a current in conformity with said stored profiles, read from said nonvolatile memory, through the respective phase windings of the motor, characterized in that it comprises storing said profiles in the form of a number of sequences of N samples, equal to the number of switching phases of the motor; commanding each phase switching of the motor and the switching of the reading of samples from said memory to the next sequence of each profile in synchronism with a synchronization signal representative of the rotor position. The method according to claim 1, characterized in that said profiles correspond to a sum of harmonics Fourier of a main frequency and the sum of instantaneous values of the distinct profiles is constant. The method according to claim 1, characterized in that each sequence is scanned in a time Tc that corresponds to the time interval that occurred between the last two preceding assertions of said synchronization signal representative of the rotor position The method according to claim 1, characterized in that said profile has a period corresponding to a complete electric revolution of the rotor. The method according to claim 1, characterized in that said synchronization signal representative of the rotor position is asserted in coincidence with the respective optimal phase switching positions assumed by the rotor under current operation condition. The method according to claim 5, characterized in that during an acceleration phase of the motor, the number of samples utilized of any one of said sequences of N samples is proportionally decreased of M samples by skipping the first M samples of the sequence in case the assertion of a new synchronization signal upon the passage of the rotor through a phase switching position has occurred before completion of the reading of all the samples of the preceding sequence. The method according to claim 5, characterized in that during an acceleration phase of the motor, the scanning of the next sequence is effected in a time T C obtained from the measured scanning time Tc of the preceding sequence, minus a percentage M% thereof and where M is the programmable content of a register. The method according to claim 5, characterized in that during an acceleration phase of the motor, the scanning of the next sequence is effected in a time obtained from the measured scanning time T C of the preceding sequence, minus a percentage M% thereof, where M is a function of the scanning time Tc of the last sequence. The method according to claim 5, characterized in that during an acceleration phase of the motor, the scanning of the ongoing sequence is interrupted upon the assertion of said synchronization signal giving immediate start to the scanning of the successive sequence. The method according to claim 5, characterized in that during a deceleration phase of the motor, the current is maintained through the phase windings of the motor, at a constant level corresponding to the last sample of the respective profiles until the occurrence of a new synchronization signal that signifies the crossing by the rotor of a phase switching position. A driving system for a polyphase brushless motor (MOTOR) comprising a plurality of output power stages (PS) driving as many phase windings of the motor, nonvolatile memory means (M1, M2, M3) for storing preset driving current profiles for each phase winding, a plurality of digital/analog or nbits/PWM converters (DAC1, DAC2, DAC3) capable of converting the digital value of each sample (D10-D17, D20-D27, D30-D37) of a respective stored drive profile read from said memory means into a driving analog signal (VREF1, VREF2, VREF3) of the relative power stage, characterized in that it comprises logic means of synchronization (ZCSSB, LB, S1, S2, L1, L2, C1, R2, COMP1, COMP2) of said conversions with a signal (Zc) representative of the rotor's position, including frequency multiplying means (PLL, 2N Divider) for the reading of N samples of a sequence in a time interval corresponding to the interval between the last two preceding assertions of said signal (Zc), each of said stored drive profiles being composed of a number of sequences of N samples equal to the number of switching phases of the motor, and said logic means comprise first logic means (LB) determining whether the reading of the last sample of the currently read sequence of N samples has been read or not at the time of assertion of said signal (ZC); second logic means (PLL, 2N Divider) increasing the time interval (Tc) between two successive phase switchings by any lead time of the reading of said last sample of sequence and the actual assertion of said signal (Zc); third logic means (LB, R2, S2, L1, L2, C1, R1, S1, COMP1, COMP2) commanding the skipping of a certain number of samples in reading a successive sequence of samples from said memory upon an intervening phase switching or the skipping of the remaining number of samples yet to be read of the sequence being read if assertion of said signal (Zc) has occurred before completing the reading of the last sample of the sequence of samples being currently read.

Inventors: MAIOCCHI GIUSEPPE, MAIOCCHI, GIUSEPPE
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1996
Main classification: H02P6
IPC codes: H03L7, H02P6, H03B28, H02P23