ELECTRONIC COMPUTER WITH A MAGNETIC PERIPHERAL UNIT

Abstract: An electronic computer comprising a central processing unit (CPU) (12), a random access memory (RAM) (15), a magnetic peripheral unit (30), a local channel (45) for the transfer of data between the RAM (15) and the peripheral unit (30), and a control circuit (DMA) (13) for driving of the direct data transfer between the RAM (15) and the peripheral unit (30). In order to speed up the transfer of data between the peripheral unit (30) and the RAM (15), the peripheral unit (30) is equipped with a low capacity, sequential access memory (FIFO) (37). Under the control of the DMA (13), the data to be recorded on the disk (31) are transferred directly from the RAM (15) to the FIFO (37) and from the latter to the read/write head (33); similarly, the data read by the head (33) are transferred to the FIFO (37) and from the latter directly to the RAM (15).

Description: "ELECTRONIC COMPUTER WITH A MAGNETIC PERIPHERAL UNIT" TECHNICAL FIELD This invention concerns an electronic computer comprising a central processing unit (CPU), a random access memory (RAM), a magnetic pe pheral unit, a local channel for the transfer of data between the memory and the pe pheral unit, and control means (DMA) for driving of the transfer of the data between the memory and the peripheral unit. BACKGROUND ART In known electronic computers, particularly personal computers of both the desk-top and portable types, the magnetic peripheral units connectable to the motherboard, on which the central processing unit is mounted, are standard modules having, in addition to the analog circuitry for controlling relative position between magnetic medium and read and write heads, a microprocessor, an intermediate, fast access memory called the "cache" and logic interfacing circuitry for error correction and control of the data transfer between the cache memory and the system memory (RAM). Accordingly, in these modules, for example in known type hard disk units (HDU), it is the microprocessor mounted on the peripheral unit that controls and manages reading/writing of data, storage in the cache memory of the data read and/or to be written, and transfer of the data from or to the RAM. Use of a cache memory, generally with a capacity of 256 Kbytes, and a peripheral microprocessor, which manages the flow of data between the peripheral and the motherboard, means that state-of-the-art magnetic peripherals in general, and hard disk units in particular, are rather expensive. Additionally, in known peripheral units the transfer of data between the peripheral unit and the RAM takes place using standard interfaces, typical examples being "ATA", through a known type local channel, "IDE" and "EIDE". The data transfer rate at the moment is about 16 megabytes/second, which is considerably lower than the rate of data transfer between the components of the motherboard, which is 133 megabytes/second. Thus the transfer of data to and from the peripheral unit constitutes a considerable limitation on speed of the work operations performed by the electronic computer, especially in cases where the central processing units (CPU) are very fast, as in the case of the 486 or Pentium class CPUs produced by the Intel Corporation. SUMMARY OF THE INVENTION The technical problem that this invention proposes solving is that of providing an electronic computer in which the data are transferred to and from the peripheral unit at the same rate and with the same throughput as those of the data transfers between the various components inside the computer, and which at the same time is very reliable and inexpensive. This technical problem is solved by the electronic computer according to this invention, which is characterized by the fact that the peripheral unit comprises a sequential access memory (FIFO) connected to the system memory (RAM) through the local channel, that the data from or to be recorded in the peripheral unit are capable of being stored temporarily in the sequential access memory (FIFO), and that the control means (DMA) are capable of controlling the direct transfer of data between the sequential access memory (FIFO) and the system memory (RAM). BRIEF DESCRIPTION OF DRAWINGS A better understanding of this and other characteristics of the present invention can be had when the following description of a preferred embodiment, provided by way of a non-exhaustive example, is considered in conjunction with the accompanying drawings, in which: FIG. 1 is a block diagram of the electronic computer according to the present invention. PREFERRED MODE FOR CARRYING OUT THE INVENTION With reference to FIG. 1 , the electronic computer of the present invention comprises a processing unit 10, constituted for example by the motherboard of a personal computer, to which a magnetic type peripheral unit 30, for example a hard disk unit, is connected. The processing unit 10 comprises a central processing unit (CPU) 12, for example a class 486 or Pentium microprocessor of the INTEL Inc. company, a known type of random access memory (RAM) 15, suitable for storing data, a logic circuit for management and control of the direct data transfer (DMA) 13, and a read only memory (ROM) 14, suitable for storing the firmware programs, which are developed in the processing unit 10 design stages. The CPU 12, the ROM 14, the DMA 13 and the RAM 15 are connected in a known way to a system channel for the transfer of data and commands 16 through local data and command channels, 18, 20, 19 and 21 respectively. The system channel 16 and the local channels 18, 19, 20 and 21 are of a known type and are suitable for transferring data and commands between the internal elements of the unit 10 at a rate of at least 133 megabytes per second. The peripheral unit 30 includes a hard type magnetic disk 31 connected to an electric motor 32, suitable for setting it in rotation. A magnetic head 33, suitable for reading and/or writing data on the magnetic disk 31 , is driven in a known way by a second electric motor 34, and thereby positioned on the different concentric tracks of the disk 31. The motors 32 and 34 are commanded by a control unit 35, also of a known type. The head 33 is connected to a known type of logic circuit for amplification and coding 36 which, during the read operations on the magnetic disk 31, is suitable for amplifying the analog signals read, for converting them into digital form and correcting instantaneously any read errors, is also suitable for converting the digital type data to analog form and for instantaneously verifying that the data thus converted are written correctly on the magnetic disk 31. Connected to the circuit 36 through a command channel 40 is a logic interface circuit 38 and, through a data channel 42, a sequential access, read and write memory (FIFO), which is connected in turn to the circuit 38 through a data channel 41. The sequential memory 37, of low capacity, for example of around 1 Kbyte, is suitable for storing in sequence the data to be exchanged between the circuit 36 and the interfacing circuit 38. The latter-named is in turn suitable for exchanging data and commands with the processing unit 10, through a local channel 45, connected to system channel 16. The local channel 45 is of a type commonly known as PCI (Peripheral Component Interconnect) and is suitable for transferring data at a rate of 133 megabytes/second. To obtain a user-selected configuration, other peripheral units 50, of a known type or similar to the peripheral unit 30, may also be connected to the processing unit 10 through other data and command channels 51, to be connected to the system channel 16. The electronic computer described up to this point operates in the following way. When the CPU 12, on the basis of the program currently being processed, has to read data from the peripheral unit 30 and transfer them to the RAM 15, it first of all reads from the ROM 14 the instructions concerning how to activate the transfer. The CPU 12 then transmits the motor control logic unit 35, through system channel 16 and interfacing circuit 38, the commands to activate or maintain rotation of the magnetic disk 31 and to position the head 33 on a track of the magnetic disk 31 corresponding to the location of the data to be retrieved. The CPU 12 also sends instructions to the DMA circuit 13 telling the latter to start reading and transferring a predetermined amount of data from the magnetic disk 31 to an area of the RAM 15, defined by the CPU 12. The DMA circuit 13 then transmits, through the system channel 16 and the interfacing circuit 38, commands to the amplification and encoding circuit 36 to activate reading by head 33 of the data recorded on the magnetic disk 31. The data read by the head 33 are amplified, instantaneously corrected and encoded in binary format by the amplification circuit 36 and transmitted to the FIFO memory 37 which transfers its contents in sequential manner to the RAM 15, through the interfacing circuit 38, the local channel 45 and the system channel 16, at the rate of 133 megabytes per second, since system channel 16 and local channel 45 have essentially the same characteristics. Following transfer of the predetermined amount of data, the DMA circuit 13 transmits in a known way the end of transfer signal to the CPU 12. As the data read and written in the RAM 15 in this way are not yet filtered of the control information, the amplification logic circuitry 36 in the peripheral unit 30 being suitable for digital coding of the analog signals coming from the head 33 but not for filtering them, the CPU 12, upon receiving the end of transfer signal from the DMA circuit 13, processes the data written in the RAM 15, removing the control information and putting the accordingly filtered data at the disposal of those processes requiring them. The method of operation in recording data on the magnetic disk 31 is similar to, but the inverse of, that employed in reading described up to this point. In point of fact, under the control of the CPU 12 and the DMA circuit 13, the data to be recorded on the disk 31 are first retrieved from the RAM 15 and then transferred in sequence to the FIFO 37 of the magnetic unit 30 and from here to the head 33 through the circuit 36. It will thus be clear that in the computer described in this invention the transfer of data between the peripheral unit 30 and the processing unit 10 takes place at the maximum speed and with the maximum throughput possible, without the interfacing circuit 38 or the local channel 45 slowing down the flow of data. It will also be evident that both the peripheral unit 30 and accordingly the electronic computer as a whole are more economical, without the microprocessor (and associated cache memory) for management of the data inside the peripheral unit 30 before they are transferred to the processing unit 10 (or before they are recorded on the disk 31 ). It is obvious that changes may be made, or parts added, to the electronic computer described in the foregoing disclosure, without exiting from the scope of the present invention.

Claims: CLAIMS 1. An electronic computer comprising a central processing unit (CPU), a random access system memory (RAM), a magnetic peripheral unit, a local channel for the transfer of digital data between said system memory and said peripheral unit, and control means (DMA) for controlling the transfer of said digital data between said system memory and said peripheral unit, characterized in that said peripheral unit comprises a sequential access memory (FIFO) connected to said system memory (RAM) through said local channel for temporarily storing said digital data read from, or to be recorded in said peripheral unit, whereby said digital data are directly transferred between said sequential access memory (FIFO) and said system memory (RAM). 2. An electronic computer according to claim 1 , wherein said peripheral unit comprises a hard disk memory unit (HDU) having a magnetic disk, at least one write and/or read head for writing and/or reading analog signals to/from said disk, rotating means for rotating said disk and positioning means for selectively positioning said head with respect to said disk, characterized in that said hard disk memory unit comprises amplifying means for amplifying said analog signals, analog-digital conversion means for converting said analog signals to said digital data, and transmitting means for directly transmitting said digital data to said sequential access memory (FIFO). 3. An electronic computer according to claim 1 or 2, characterized in that said sequential access memory (FIFO) is of low capacity. 4. An electronic computer according to claim 3 characterized in that said sequential access memory (FIFO) has the capacity of 1 Kbytes. 5. An electronic computer according to claim 1 or 2, comprising a system channel for connecting said central processing unit (CPU) to said random access system memory (RAM) and to said control means (DMA), characterized in that said local channel and said system channel have substantially the same data transmission capacity per unit of time (bytes/second). 6. An electronic computer according to claim 5, characterized in that said local channel is of the type commonly known as PCI, whereby said data transmission capacity is of 133 megabytes per second. 7. A magnetic peripheral unit for an electronic computer having a central processing unit (CPU), a random access system memory (RAM), a local channel for the transfer of digital data between said system memory and said peripheral unit, and control means (DMA) for controlling the transfer of said digital data between said system memory (RAM) and said peripheral unit characterized in that said peripheral unit comprises a sequential access memory (FIFO) for temporarily storing said digital data read from, or to be recorded in said peripheral unit, and an interfacing circuit for connecting said sequential access memory (FIFO) to said local channel whereby said digital data are directly transferred between said sequential access memory (FIFO) and said system memory (RAM). 8. A magnetic peripheral unit according to claim 7, comprising a magnetic disk, at least one write and/or read head for writing and/or reading analog signals to/from said disk, rotating means for rotating said disk and positioning means for selectively positioning said head with respect to said disk, characterized in that said disk unit comprises amplifying means for amplifying said analog signals, analog-digital conversion means for converting said analog signals to said digital data, and transmitting means for directly transmitting said digital data to said sequential access memory (FIFO).

Inventors: SARTORI GABRIELE, SARTORI, GABRIELE
Applicants: OLIVETTI & CO SPA, SARTORI GABRIELE, ING. C. OLIVETTI & C., S.P.A., SARTORI, GABRIELE
Application year: 1996
Main classification: G06F3
IPC codes: G06F3