Pulse generation circuit for synchronized data loading in an output pre-buffer,particularly for memory devices

Abstract: In a memory device that comprises an internal bus for the transfer of data and reporting signals from and to the memory and output pre-buffers (1 L , 1 H ) for the transfer of data to output terminals (2 L , 2 H ) of said memory, a pulse generation circuit for the synchronized loading of data in an output pre-buffer, which has the particularity that it comprises: synchronization generation means (7); means (5) for reproducing the propagation delays of the data transmitted to the output terminals (2 L , 2 H ); and means (6) for reproducing the propagation delays of the output pre-buffers (1 L , 1 H ); the synchronization means (7) are adapted to synchronize the generation of at least one pulse that is synchronized with the propagation delays reproduced by the data propagation delay reproduction means (5), and the pulse is adapted to enable the loading of the data in the output pre-buffers (1 L , 1 H ); the synchronization is provided as a consequence of the assured presence of the data, and the synchronous pulse is restored after a time that is equal to the delay introduced by the means (6) for reproducing the propagation delays of the output pre-buffers, so as to update the configuration of the output pre-buffers (1 L , 1 H ) in the time interval determined by the synchronous pulse.

Description: The present invention relates to a pulse generation circuit for data loading in an output pre-buffer, particularly for memory devices. It is known that in a memory device the data present inside said memory must, during the reading step, be transferred to the output terminals to make them available to the outside world. Usually, said output terminals are not directly connected to the memory and they present to the outside world the data related to the last reading operation performed on the memory device. When a reading operation is performed, it is therefore necessary to activate the connecting path between the inside of the memory and the output terminals for data transmission. A drawback that can often be observed is that noise, which is either present on the supply lines or generated by the switching of the memory outputs, may be superimposed on the data that have just been transmitted, with possibly oscillating characteristics. When the data are loaded into an output pre-buffer, said pre-buffer switches and assumes the mode dictated by the data. Once the data have been loaded into the output pre-buffer for discharge onto the output terminal, any other possible switching that occurs at the input node of the pre-buffer and is not a switching produced by an actual address transition, and therefore a new data reading operation, can undesirably alter the configuration of said pre-buffer, thus corrupting the data produced by the reading operation. Even more so, introducing in the architecture of a memory device an internal bus that is used for multiple functions, which in any case must remain transparent with respect to the outside world, arises the problem of determining the right moment for synchronization of the data arriving from the memory, over the internal bus, which must be visualized externally. European Patent application EP-A-0 526 433 wherein the preamble of claim 1 is based discloses a memory device provided with output pre-buffers which transfer data to output terminals upon activation of a load signal. The memory device further comprises a load signal generator which, upon detection of the arrival of data at the internal data bus, generates said load signal which loads said data in said output pre-buffers, and further comprises reset circuitry which resets said load signal to inhibit further variations of the data loaded in said output pre-buffers. The aim of the present invention is therefore to provide a pulse generation circuit for the synchronized loading of data in an output pre-buffer, particularly for memory devices, that allows to generate pulses that are synchronized with the production and natural propagation of the data, for the subsequent loading of the data into the output pre-buffer without additional delays. Within the scope of this aim, an object of the present invention is to provide a pulse generation circuit for the synchronized loading of data in an output pre-buffer, particularly for memory devices, that allows to inhibit the modification of the output pre-buffer in the shortest possible time, so as to prevent noise from adding to the data. Another object of the present invention is to provide a pulse generation circuit for the synchronized loading of data in an output pre-buffer that allows to link the minimum duration of the pulse to the various power supply, technology, and temperature conditions that occur. Another object of the present invention is to provide a pulse generation circuit for the synchronized loading of data in an output pre-buffer that allows to control the minimum duration of the generated pulses that ensures the certain configuration of the output pre-buffer. Another object of the present invention is to provide a pulse generation circuit for the synchronized loading of data in an output pre-buffer in which the duration of the pulses is strictly limited to the time for loading the data in the output pre-buffer. Another object of the present invention is to provide a pulse generation circuit for the synchronized loading of data in an output pre-buffer that allows to maintain a decoupling between the internal bus and the memory device, so as to preserve bus independence. Another object of the present invention is to provide a pulse generation circuit for the synchronized loading of data in an output pre-buffer that allows to generate the pulses asynchronously for data loading operations that do not require a full reading cycle. Another object of the present invention is to provide a pulse generation circuit for the synchronized loading of data in a pre-buffer that allows to provide a mode for the forced generation of the loading pulses. Another object of the present invention is to provide a pulse generation circuit for the synchronized loading of data in an output pre-buffer, particularly for non-volatile memories, that allows to generate a plurality of said pulses. Another object of the present invention is to provide a pulse generation circuit for the synchronized loading of data in an output pre-buffer, particularly for non-volatile memories, that allows to preset the duration of the pulses so as to closely match the loads and impedances of the data propagation path. Another object of the present invention is to provide a circuit that is highly reliable and relatively easy to produce at competitive costs. This aim and these objects are achieved by a pulse generation circuit for the synchronized loading of data in an output pre-buffer according to claim 1. Further characteristics and advantages of the invention will become apparent from the description of a preferred but not exclusive embodiment of the circuit according to the invention, illustrated only by way of non-limitative example in the accompanying drawings, wherein: figure 1 is a block diagram of the circuit according to the invention; and figure 2 is a circuit diagram of a detail of the circuit according to the invention, shown in figure 1. With reference to the above figures, the circuit according to the invention comprises storage means, advantageously constituted by latch structures that form output pre-buffers 1 L and 1 H . Said latch structures are connected to output buffers that constitute the output terminals 2 L and 2 H . Due to the symmetry of the circuit, since a memory matrix divided into two half-matrices L and H is being considered, for the sake of simplicity in description only the portion of the circuit that relates to the connecting path between the internal bus that carries the data of the half-matrix L and the output terminals 2 L is described. Identical reference numerals are assigned to identical elements in the two identical circuit portions. As mentioned, therefore, the internal bus 3 L carries the data from the memory matrix (not shown) to the "outside world" for the reading of said data. The path followed by the data is characterized by intrinsic delays, represented by the circuits 4 L . Said data path delays are reproduced by transmission path delay reproduction means 5 (which are provided once for both circuit portions H and L). The intrinsic delays of the output pre-buffers 1 L and 1 H are instead reproduced by means 6 for reproducing the delays of the output pre-buffers 1 H and 1 L . In this case, too, the means 6 are provided once for both circuit portions H and L. The circuit also comprises synchronization means 7 that are adapted to synchronize short pulses, referenced as LOAD pulses, with the appearance of the data to load the data present on the internal bus in the output pre-buffers 1 L and 1 H . The block diagram of figure 1 is completed by means 8 for selecting the word or byte read mode. In detail, the various functional blocks shown in figure 1 are mutually connected as follows. The synchronization means 7 receive in input a signal D-STROBE that is adapted to determine the moment that is adapted for data sampling and synchronization of the synchronization pulses LOAD (since the signal D-STROBE is also a signal for capturing the matrix data item). Said means 7 also receive in input a signal for disabling/enabling the pulses LOAD and emit in output a synchronization signal SYNC. The synchronization signal SYNC is sent to the circuit 4 L , which determines the delay of the path for the transmission of the data to the output pre-buffer 2 L , and to the means 5 for reproducing the delays of the transmission path. The transmission path delay reproduction means 5 emit a signal OS-P for producing the synchronous pulse LOAD, which is in turn sent respectively to logic control means. Said logic control means comprise two AND logic gates 9 H and 9 L that receive as their other input, in addition to the signal OS-P, a signal WDmode and a signal BYmode, respectively, that originate from the mode selection means 8. The signal WDmode indicates selection of the data path for the half-matrix H, whereas the signal BYmode indicates selection of the data path for the half-matrix L. The selection means 8 receive in input a control signal CNT that indicates the desired type of selection (word or byte). The output of the AND logic gates 9 H and 9 L is sent respectively to two NOR logic gates 10 H and 10 L that receive, as their other input, a signal for producing pulses asynchronously (forced pulse production mode). This signal is designated by HARD LOAD. The outputs of the logic gates 10 H and 10 L are sent respectively through two inverters 11 H and 11 L for generating the pulses LOAD H and LOAD L for synchronously loading the data in the output pre-buffers 1 H and 1 L respectively. The pulse LOAD L is fedback to the means 6 for reproducing the delays of the output pre-buffers. These means also receive two additional signals: a signal PRESET, which is adapted to preset the condition for generating the pulse LOAD that is produced at the appropriate time; and a signal ASYNC-PRESET that allows to preset the generation of a pulse LOAD, which however in this case is asynchronous and has immediate propagation. The output of the means 6 for reproducing the delays of the output pre-buffers is a signal OS-RS for restoring the line for generating the pulses LOAD. The block diagram of figure 1 is shown in its circuital details in figure 2. The synchronization means 7 comprise in detail means 12 for generating a synchronization control signal SYNC-CNT. This signal is sent to a pass transistor 13 that is constituted by a P-type transistor and by an N-type transistor. An inverted memory read address transition signal ATDn is sent in input to an inverter 14, whose output is the input on the gate terminal of the P-type transistor of the pass transistor 13. The signal ATDn is also sent in input to the gate terminal of the N-type transistor of the pass transistor 13 and to the gate terminal of an additional P-type transistor that is interposed between the supply and the output of the pass transistor 13, which constitutes the synchronization disabling signal SYNC-dis. The signal SYNC-dis, together with the signal D-STROBE (explained earlier), is sent in input to a NOR logic gate, whose output passes through an inverter 16. The output of the inverter 16 is the signal SYNC. With reference now in detail to the circuit 4 L for reproducing the delays of the path for the propagation of the data toward the output buffers 1 L , said circuit comprises a first inverter 17 L , which receives in input the synchronization signal SYNC, and a second inverter 18 L , which receives in input the data that are present on the internal bus 3 L and is interposed between the output of the inverter 17 L and the inverted signal SYNC. A P-type transistor 19 L is interposed between the supply voltage and the output of the inverter 18 L and receives in input at its gate terminal the output of the inverter 17 L . A third inverter 20 L is cascade-connected to the inverter 18 L and receives in input the inverted signal SYNC. A capacitor 21 L connected between the output of the inverter 20 L and the ground represents the capacitance of the path for transmitting the data to the output terminals 2 L . The above described circuit 4 L represents the delay that affects the data that are present on the internal bus 3 L as a consequence of their transmission to the output terminals 2 L . The circuit 5 L represents the reproduction of said delay and is therefore constituted by the same elements as the circuit 4 L (and of the circuit 4 H ), which are assigned the same reference numerals but without the addition of any suffix. Since the two circuits are identical, in order to avoid redundancies in the explanation the circuit 5 will not be explained further in detail. With respect to the circuit 4 L , the circuit 5 comprises in addition an N-type transistor 22 that is connected between the output of the inverter 20 and the ground and receives the signal SYNC at its gate terminal. The logic means 9, 10, and 11 respectively for the half-matrices H and L, which are cascade-connected to the circuit 5, have already been described with reference to figure 1. The logic gates 9 H and 9 L receive respectively in input the signals for selecting the read mode (word or byte), designated by WDmode for selecting word-type reading and by BYmode for selecting the byte-type read mode. The output pre-buffers 1 L and 1 H include the actual storage means, which are constituted by latch circuits, and means for driving said latch circuits. The driving means are constituted by a pass transistor 23 L' by two inverters 24 L and 25 L , and by two N-type transistors 26 L and 27 L . The driving means receive in input the data that are present on the internal bus in addition to the synchronization pulse LOADL for loading the data in the output pre-buffers 1 L . An output enabling signal OEL is indicated in the latch structure of the means 1 L (likewise, there is a similar signal OEH for the means 1 H ). The lines designated by A L and B L represent the connection to a P-type transistor and to an N-type transistor, respectively, of the output terminals 2 L . The means 6 for reproducing the propagation delays of the pre-buffer therefore comprise a latch structure that is similar to the one shown with reference to the means 1 L . As regards the means 6, two nodes of the latch, designated by UP and DW, are indicated. The reproduction of the driving means, designated by the reference numeral 31, is constituted in this case by two inverters 28 and 29 and by a transistor 30 that are connected as shown in figure 2 (the connection is similar to the one shown for the driving means related to the means 1 L ). The inverter 29 is connected to the ground. The reproduced driving means 31 therefore have, with respect to the actual driving means, a pass transistor and one transistor less, since they are not necessary for propagation. The driving means 31 receive in input the synchronization pulse LOADL and emit in output the signal OS-SL, which is fed to the gate terminal of a transistor 32 of the N-type that is part of the reproduced latch structure, which is similar to the latch structure of the means 1 L . An additional N-type transistor 33 is interposed between the node UP of the latch structure and the ground. A signal DIS is sent to the gate terminal of the transistor 33 and originates from latch enabling logic control means, which comprise a NOR logic gate 41, whose two inputs are constituted by the inverted synchronization signal SYNCn and by the signal PRESET, both of which have been described above. The signal PRESET is sent to the gate terminal of an N-type transistor 45 that is interposed between the node DW of the latch structure and an additional transistor 34 of the N type that receives as input, at its gate terminal, the synchronization signal SYNC. The transistor 34 is interposed between the transistor 33 and the ground. Capacitive means 35 and 36 are included in the latch structure as shown in figure 2 to represent the capacitance of the P- and N-type transistors, respectively, of the output terminals 2 L (not shown in figure 2). The output enabling signals OE are not sent to the gate terminals of the transistors 37 and 38 of the reproduced latch structure, as occurs instead for the latch structure of the means 1 L , but the gate terminals are connected to the supply voltage. An N-type transistor 39 is instead connected between the node DW of the latch structure and the ground, in a symmetrical position with respect to the transistor 32. The signal ASYNC-PRESET is sent to the gate terminal of the transistor 39. Finally, an inverter 40 connected as shown in figure 2 is inserted on the feedback line that carries the signal OS-RL to the inverter 18 that belongs to the means 5 for reproducing the data propagation delays. To summarize, the control lines of the circuit according to the invention are essentially the following: SYNC-dis: controls the disabling/enabling of the pulses LOAD (L/H) for loading the data of the memory, which are present on the internal bus, in the output pre-buffers 1 L and 1 H ; ATDn and SYNC-CNT: together, they determine the duration of the pulses LOAD; D-STROBE: a sensing signal that determines the moment that is adapted for the sampling of the data and the synchronization of the pulses LOAD; PRESET: allows to preset the condition of the pulse LOAD that will be produced at the appropriate time; ASYNC-PRESET: like PRESET, it allows to preset the condition of the pulse LOAD, but asynchronously and with immediate propagation; HARD LOAD: allows to produce pulses asynchronously, with immediate propagation and with any duration. It is used for example during inspection of the memory device. With reference to the above figures, the operation of the circuit according to the invention is as follows. For the circuit according to the invention it is possible to identify various steps, each of which is characterized by a particular configuration of the various signals of the circuit (high state or low state). Let us consider first of all the disabling step, during which the possibility to produce synchronization pulses for loading the data in the output pre-buffers 1 L and 1 H is inhibited. During this step, only forced pulses HARD-LOAD are possible for inspection of the memory device, as explained previously. This disabling step is characterized in that the signal DIS that leaves the NOR logic gate 41 is high; this entails that the node UP of the latch structure is low, and in this manner the entire latch structure is blocked and no loading of the data present on the internal bus occurs. In detail, during this disabling step the various signals that are present in the circuit according to the invention assume the following states: SYNC-CNT = 1 SYNC-dis = 1 (by means of SYNC-CNT = 1) SYNC = 1 SYNCn = 0 D-STROBE = 0 OS-P = 0 PRESET = 0 DIS = 1 UP = 0 DW = 1 OS-SL = 0 OS-RL = 0 As a consequence of a variation of the address transition detection signal ATD, which indicates the need to read the memory matrix, a step for generating synchronous pulses is entered; this step is divided into three steps: a presetting step, which is characterized in that it has the following conditions for the various signals of the circuit: SYNC-CNT = 0 SYNC-dis = 1 (by means of the signal ATDn) SYNC = 1 SYNCn = 0 D-STROBE = 1 OS-P = 0 PRESET = 1 DIS = 0 UP = 1 DW = 0 OS-SL = 0 OS-RL = 1 During this presetting step, the conditions that allow to produce the pulses LOAD at the appropriate time are set; * a step for generating synchronous pulses, characterized in that it has the following conditions for the various signals of the circuit: SYNC-CNT = 0 SYNC-dis = 0 SYNC = 0 SYNCn = 1 D-STROBE = 0 OS-P = 1 PRESET = 1 DIS = 0 UP = 1 DW = 0 OS-SL = 0 OS-RL = 1 During this step, the pulses LOADH related to the half-matrix H (if the corresponding control signal WDmode is 1) and the pulses LOADL are produced; * a step for restoring the pulses LOAD, characterized in that it has the following conditions for the various signals of the circuit: SYNC-CNT = 0 SYNC-dis = 0 SYNC = 0 SYNCn = 1 D-STROBE = 0 OS-P = 0 PRESET = 1 UP = 0 DW = 1 OS-SL = 1 OS-RL = 0 In this manner, the pulses LOADL and LOADH are self-reset and cannot be produced again until a new cycle is started; this cycle is always established by the signal D-STROBE that is meant to trigger the entire timing. In order to generate the data loading pulses, it is also possible to produce an asynchronous pulse, i.e., a pulse that is independent of the data propagation delays on the output path when a full memory read cycle is not to be performed, for example in the case in which one is in the byte read mode and therefore the data that are present on the internal bus related to the half-matrix H are rerouted on the internal bus related to the half-matrix L so as to be loaded in the output pre-buffers 1 L and then sent to the output terminals 2 L . Said asynchronous pulse is produced by the signal ASYNC-PRESET, which becomes high. The asynchronous pulse has a shorter duration than the synchronous pulse LOAD. Finally, there is an inactive step that is characterized in that it has the same conditions as the disabling step, except for the following signals: SYMC-CNT = 0 SYNC-dis = 0 (by means of SYNC-CNT = 0) SYNC = 0 SYNCn = 1 DIS = 0 This step occurs, for example, at the end of a memory read or in any case when the memory device still has to begin a reading operation. The charts of the timings of the various signals shown in figures 1 and 2 visually summarize the above listed behaviors. Therefore, to summarize, as a consequence of the signal D-STROBE that switches from high to low and activates the entire subsequent timing, the signal SYNC also switches from high to low and the data present on the internal bus, designated by L/H DATA, are acquired with certainty by the internal bus for transmission to the output terminals 2 L and 2 H . Simultaneously with the switching of the data, the signal SYNC is produced; this signal switches from high to low, triggering, at its falling edge, the generation of the pulses LOAD L/H that have a short duration and are synchronous with the data, since the delays of the propagations of the data along the transmission path have been taken into account (with the means 5) for the synchronous and timed loading of the data in the output pre-buffers 1 L and 1 H . The loading of the data in said pre-buffers is indicated by the signal referenced by L/H DATA OUT, which switches within the duration of the pulse. Then the pulse, which is formed by repeating the same delays as the output pre-buffers 1 H , 1 L , is restored to zero and cannot be reproduced until a new cycle, timed by the signal ATD that varies and by the signal D-STROBE, begins. In practice it has been observed that the circuit according to the invention fully achieves the intended aim, since it allows to produce a synchronized pulse by repeating the propagation of the data along the path for transmission to the output pre-buffers for loading said data in said pre-buffers, thus avoiding any further delay, regardless of the operating voltages, of the temperature, and of the technological parameters. The pulse is immediately reset once loading has been performed, in order to avoid harmful interference on the data caused by noise. The step for restoring the pulse to zero is also performed by taking into account the data propagation delays in the output pre-buffers and therefore intrinsically determines a duration thereof that truly matches the propagation of a correct loading. This duration is "minimal" and this property is conserved regardless of the operating condition and of the technology. Therefore, the data in the pre-buffer are modified only in extremely short time intervals, marked by the synchronous pulses, so as to avoid alterations thereof. The duration of the pulses is thus closely linked to the loads and to the impedance of the paths that the data must perform for reading from the memory. Furthermore, it is possible to produce pulses asynchronously for data loads that do not require a full memory read cycle. The possibility of producing a forced asynchronous pulse allows to perform a whole series of memory inspection operations, reading the auxiliary reporting data rerouted on the internal bus; in this case, the duration of the pulse can be changed at will without being tied to the propagations of the data of the memory along the transmission paths. Finally, it should be noted that it is possible to produce a plurality of synchronous pulses. Said plurality of synchronous pulses is always generated by a single simulation of the paths for the propagation of the data toward the output terminals and of the propagations of the output pre-buffers. The circuit thus conceived is susceptible of numerous modifications and variations, all of which are within the scope of the inventive concept; all the details may furthermore be replaced with other technically equivalent elements. In practice, the materials employed, so long as they are compatible with the specific use, as well as the dimensions, may be any according to the requirements and the state of the art. Where technical features mentioned in any claim are followed by reference signs, those reference signs have been included for the sole purpose of increasing the intelligibility of the claims and accordingly such reference signs do not have any limiting effect on the interpretation of each element identified by way of example by such reference signs.

Claims: A memory device comprising an internal bus (3) for the transfer of data and reporting signals from and to the memory, output pre-buffers (1) for the transfer of data to output terminals (2) of said memory, a pulse generation circuit for the synchronized loading of data in said output pre-buffers, synchronization generation means (7, 8, 9, 10, 11) and means (5) for reproducing the propagation delays of the data transmitted to said output pre-buffers (1); characterized by means (6) for reproducing the propagation delays of said output pre-buffers; said synchronization generation means (7, 8, 9, 10, 11) being adapted to synchronize the generation of at least one synchronous pulse (LOAD) that is synchronized with the propagation delays reproduced by said data propagation delay reproduction means (5), said synchronous pulse (LOAD) being adapted to enable the loading of the data in said output pre-buffers, said synchronization being provided as a consequence of the assured presence of the data, said synchronous pulse being reset after a time that is equal to the delay introduced by said means (6) for reproducing the propagation delays of the output pre-buffers (1), so as to update the data in said output pre-buffers (1) in the time interval determined by said synchronous pulse (LOAD). Circuit according to claim 1, characterized in that said means (5) for reproducing the propagation delays of the data transmitted to the output pre-buffers (1) structurally reproduce the configuration of the paths for the transfer of the data to the output pre-buffers, so as to match their delays. Circuit according to claim 1, characterized in that said means (6) for reproducing the propagation delays of the output pre-buffers (1) structurally reproduce the configuration of the output pre-buffers (1) so as to match their delays. Circuit according to claim 1, characterized in that said means (5) for reproducing the propagation delays of the data transmitted to the output pre-buffers receive in input a synchronization signal (SYNC) that is produced by said synchronization generation means (7), said synchronization signal (SYNC) being also sent in input to the path for the transmission of data to the output pre-buffers (1). Circuit according to claim 4, characterized in that said synchronization signal (SYNC) is fedback to said means (6) for reproducing the propagation delays of said output pre-buffers (1). Circuit according to claim 5, characterized in that said means (6) for reproducing the propagation delays of said output pre-buffers receive in input a signal (ASYNC-PRESET) for asynchronously presetting said at least one synchronous pulse (LOAD) and a signal (PRESET) for presetting the condition for generating said at least one synchronous pulse (LOAD), the output of said means (6) for reproducing the propagation delays of said output pre-buffers being sent as input to said means (5) for reproducing the propagation delays of the data transmitted to said output pre-buffers (1). Circuit according to claim 1, characterized in that it also comprises means (8) for selecting the read mode of said memory, said means emitting a read mode selection signal (Wdmode, BYmode). Circuit according to claim 1, characterized in that it comprises logic control means (9, 10, 11) for generating said at least one synchronous pulse (LOAD), said logic means 9, 10, 11) being controlled by the output of said means (5) for reproducing the delays in the propagation of the data transmitted to said output pre-buffers (1). Circuit according to claim 8, characterized in that said logic control means (9, 10, 11) comprise, in cascade, at least one AND gate (9), a NOR gate (10), and an inverter (11). Circuit according to claim 9, characterized in that said AND gate (9) receives as input the output of said means (5) for reproducing the delays in the propagation of the data toward said output pre-buffers (1) and said read mode selection signal (Wdmode, BYmode). Circuit according to claim 9, characterized in that said NOR logic gate (10) receives in input the output of said AND gate (9) and a signal for producing said pulse asynchronously (HARD LOAD), the output of said NOR gate (10) being sent through said inverter (11) for subsequent transmission of said pulse to said output pre-buffers (1) to enable loading of the data therein. Circuit according to claim 11, characterized in that said signal (HARD LOAD) for producing said pulse asynchronously is adapted to produce pulses of a freely selected duration. Circuit according to claim 1, characterized in that said synchronization generation means (7) comprise driving means (13, 14) that receive in input an inverted read address transition detection signal (ATDn) and a synchronization control signal (SYNC-CNT), and logic means (15, 16) adapted to emit said synchronization signal (SYNC) to generate said synchronous pulses (LOAD) for loading the data in said output pre-buffers (1). Circuit according to claim 13, characterized in that said driving means (13, 14) of said synchronization means comprise an inverter (14), a pass transistor (13), and a P-type transistor. Circuit according to claim 13, characterized in that said logic means (15, 16) of said synchronization means (7) comprise a NOR gate (15) with a cascade-connected inverter (16). Circuit according to claim 15, characterized in that said NOR gate (15) receives as input a signal (SYNC-dis) for disabling/enabling said pulses and a data sampling signal (D-STROBE), said data sampling signal (D-STROBE) indicating the moment of certain acquisition of said data. Method for loading the data of a memory matrix, during a step for reading the memory, in output pre-buffers (1) to send the data to output terminals (2), particularly for non-volatile memories, said method comprising the steps: as a consequence of a read address transition of said memory, and of the acquisition of the data on an internal bus (3) of said memory, presetting the conditions for the generation of at least one synchronous pulse (LOAD) that is synchronous with the propagation of the data; generating said at least one synchronous pulse (LOAD) to enable the loading of said data in said output pre-buffers (1), said step for generating said at least one synchronization pulse (LOAD) comprising the correlation of the generation of said synchronous pulse (LOAD) to the data propagation delays on the paths for transmission to said output pre-buffers (1); loading said data in said output pre-buffers (1); and resetting said at least one synchronous pulse (LOAD) to inhibit further variations of the data loaded in said output pre-buffers (1), characterized in that said step for resetting said at least one synchronous pulse (LOAD) being performed by correlating said resetting to the data propagation delays in said output pre-buffers (1), in order to allow assured loading of the data in said output pre-buffers(1). Method according to claim 17, characterized in that said at least one synchronous pulse (LOAD) has a duration that is strictly limited to the time for loading the data in said output pre-buffers (1). Method according to claim 17, characterized in that it also comprises a step for generating an asynchronous pulse (ASYNC-PRESET) for operations for loading data in said output pre-buffers (1) that do not require an entire read cycle. Method according to claim 17, characterized in that it furthermore comprises a step for generating a forced pulse (HARD LOAD) for reading reporting signals that are rerouted onto the internal bus (3) of said memory, said forced pulse (HARD LOAD) being asynchronous.

Inventors: PASCUCCI LUIGI, PASCUCCI, LUIGI
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1996
Main classification: G11C7
IPC codes: G11C7