FILTERED SERIAL EVENT CONTROLLED COMMAND PORT FOR FLASH MEMORY

Abstract: A filtered command port architecture for a memory array is disclosed. A command controller is directly connected to the memory array and receives command instructions from an external microprocessor via a data bus. A command clock is used to latch commands from the data bus into a command decoder. A timing signal is used tofilter incoming control signals which are asserted for less than a predetermined amount of time. A state decoder then tracks a sequence of commands from the command decoder and performs an appropriate action in response to the commands.

Description: FILTERED SERIAL EVENT CONTROLLED COMMAND PORT FOR FLASH MEMORY Field of the Invention The present invention generally relates to the field of electrically programmable and electrically erasable read-only memory, and more particularly to a filtered serial-event-controlled command port for a flash memory device. Background of the Invention The power and flexibility of personal computers have increased dramatically since their introduction in the marketplace. As a result, the use of computers has risen significantly and has had a tremendous impact in society. In essence, personal computers typically comprise a microprocessor chip, random access memory, and non-volatile memory. Non¬ volatile memory is memory that retains its previously stored information even when power is no longer supplied to the chip. One type of non-volatile memory is read¬ only flash memory, which can be erased electrically rather than by exposure to ultra-violet light. Read¬ only flash memories are also electrically programmable. A variety of conceived memory-command interfaces has simplified reading and writing information to non-volatile memories coupled to microprocessors. With such an interface, a microprocessor can issue a command such as "erase" or "program" through data lines connecting the microprocessor to the memory chip. The chip typically contains logic circuitry for decoding and executing these commands. The prior art employs different methods for implementing this logic circuitry. Figure 1 depicts an example of one implementation, disclosed in U.S. Pat. No. 5,222,076. To request the execution of a command, the control lines of the microprocessor externally generates an asynchronous clock signal by bringing lines CE and WE low. Typically, a clock signal lasts approximately 50 nanoseconds (ns) , and the time between successive clock signals is even shorter, approaching 10 nanoseconds (ns) . Such a short duration, however, can potentially disrupt the logic circuitry of a memory device from properly executing a desired command. Typically, data latches into the command and state registers incident to the externally generated asynchronous clock signal. The state decoder block then decodes the output of the registers and directs execution of the proper command. However, the parasitic capacitance associated with the chip typically delays movement of data through the data bus to the registers. Before the data reaches the registers, the microprocessor may generate another clock signal asking for a second command to be performed on different data. Potentially, this may confuse the decoder block, causing it to direct execution of the second command on the wrong data, and to fail to execute the first command. For example, the microprocessor may request execution of a first command on a first data. The state decoder block will receive this command, and begin waiting for the first data to move through the data bus to the state and command registers. Before the data reaches the registers, however, the microprocessor may request execution of a second command on a second data. The decoder block may receive this second command before the first data has reached the registers. When the first data does arrive, the block will direct execution of the second command on the first data, thus directing performance of the wrong command on the first data. Therefore, a drawback to the approach employed by the prior art is that extreme care must be taken in designing a non-volatile memory device chip so as to prevent this problem from occurring. It should be noted, however, that typically once a command is received by the command architecture, it latches therein such that subsequent data received by the architecture will have the last received command performed upon it. For example, in the sequence C0MMAND-DATA1-DATA2, both DATAl and DATA2 will have COMMAND performed upon them. In other words, each sent data does not require a separate sent command -- the command COMMAND-DATAl-COMMAND-DATA2 is not necessary, for example, to perform COMMAND on both DATAl and DATA2. Furthermore, where the command architecture has initially powered up and no command has yet been sent to it, typically the default command in such an instance is a read command. This parallel approach to command architecture also poses a problem because of the simultaneous nature of the command and state processing inherent in a parallel approach. The state register must read and process data off the bus concurrent to the command register reading and processing a command off the bus. The registers must output to the state decoder block the results of their processing nearly simultaneously, or the state decoder will not direct execution of the command upon the data correctly. In using a non- volatile memory employing the prior art approach to command architecture, a designer must take proper precaution to avoid this situation from occurring. In addition, the approach taken by the prior art is highly sensitive to noise on the WE and CE lines. The internal logic circuitry of a non-volatile memory device may potentially perceive even a brief burst of simultaneous noise on the WE and CE lines as an asynchronous clock signal generated externally by the microprocessor. This would erroneously cause the state and command registers to latch, and the state decoder block to decode. The decoder block would then direct execution of a command upon data in the device that the microprocessor had not actually requested. Therefore, a drawback to the approach employed by the prior art is that it is vulnerable to noise on the CE and WE lines inciting erroneous commands to be executed upon data in the memory device. This problem is exasperated in many systems where the CE line is typically tied low. Noise on the WE line is then sufficient to incite erroneous execution of a command. A command architecture might divide execution of an erase command into two parts: an erase- setup command for directing the command to occur, and an erase-confirm command for verifying that the command has executed. Even if the erase-setup command executes properly, noise on the WE line before the command register has received the erase-confirm command will frustrate proper execution of the operation. This is because after handling the erase-setup command, the state register expects to receive a erase-confirm command. When it does not, it signals an error, even if the next command on the bus is a erase-confirm command. A prior-art memory device operating in such a noisy environment may thus encounter curtailed performance. Summary of the Invention The present invention provides a circuit to filter any signals asserted on lines WE and CE less than a predetermined duration, and to execute processing of a command and state within the command architecture in a serial manner. The invention eliminates the potential for the state block decoder to direct execution of a wrong command because the duration is necessarily longer than the delay in data moving through the data bus to the register. The invention also eliminates the potential for erroneous execution because a single register handles both data and command information off the bus, processing it in a serial manner. Further, the invention eliminates vulnerability to noise that may cause the decoder to direct execution of an erroneous command, because typically such noise is shorter in duration than that which the invention allows to pass. These and other advantages and features that characterize the present invention are described with particularity in the claims appended hereto and forming a further part hereto. For better understanding of the invention, its advantages and objectives, reference should be made to the drawings, which form a further part hereto, and to the accompanying descriptive matter, which illustrates and describes a preferred embodiment of the present invention. Brief Description of the Drawings Figure 1 is a block diagram showing a prior art command interface means for flash memory. Figure 2 is a block diagram of a filtered command port architecture compatible with the present invention. Figure 3 is a timing diagram showing the operation of the filtered command port architecture shown in Figure 2. Figure 4 is a block diagram of a typical computer that may incorporate the present invention. Detailed Description of the Preferred Embodiments In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the present invention. For instance, the present invention has application in connection with non-volatile erasable programmable read¬ only memory (EPROM) and electrically erasable programmable read-only memory (EEPROM) chips. In addition, the circuits for filtering incoming commands from an external microprocessor may be implemented using various forms of active or passive circuits, and the respective circuits providing the input and output signals to the state decoder may be implemented in a number of modified forms. The preferred circuits depicted in Figure 2 show an exemplary arrangement and use a filtering means in accordance with the present invention, but it should be recognized that other circuits may be implemented within the scope of the present invention without loss of generality. Figure 2 describes a typical filtered command port architecture which may be used with the present invention. External signal lines WE and CE 210 and 200 are coupled to a block 51. When WE and CE line signals 210 and 200 are low, a signal 105 is asserted signifying the existence of legal conditions for a command or data load instruction. Signal 105 is then coupled to a main clock generator circuit 52. If the duration of signal 105 is less than a predetermined filter duration, the signal is prevented from continuing, and none of the outputs of main clock generator circuit 52 are asserted. The invention takes a new and novel approach to interpreting the command cycling commonly used by non-volatile memory devices. A typical specification for a non-volatile memory device stipulates the assertion of a command for 50 nanoseconds (ns) , followed by a period of "dead" time lasting 10 ns. Whereas the prior art incites simultaneous latching of the state and command registers immediately upon the beginning of a new cycle, the invention first delays any latching by 20 ns while a clock generation circuit 52 ensures that the assertion of the WE and CE lines 210 and 200 is not due to noise. In the remaining 30 ns of the cycle, a command register 53 first reads the command off the data bus and processes it. The same register then reads the data off the bus and processes it. Therefore, the present invention effectively reapportions the typical 60 ns clock cycle consisting of 50 ns command-assertion time and 10 ns "dead" time into a command-assertion time of 30 ns and "dead" time of 30 ns. The 20 ns increase in "dead" time results from the delay imposed by the filtering effect of clock generator circuit 52. Figure 3 describes a typical timing diagram of a filtered command signal which may be used with the present invention. When an externally provided command or data signal is filtered, the high going edge of clock signals 107, 104 and 110 are delayed by the same amount as the predetermined filter duration, typically 20 ns. With further reference to Figure 2, signal 107 is then typically coupled to a command clock generator 55 which in turn generates signal 103. Signal 103 is coupled to command register 53, which is used to latch commands placed on a data bus 106 into command register 53. A signal 102 represents the typical output of command register 53, and is normally coupled to a command decode logic circuit 54 and a state latches and logic 57 through a signal 109. Signal 109 represents the current state of the state machine interpreting commands and executing instructions in the memory array. State latches and logic 57 will consider some legal commands as illegal if they are received out of sequence, depending on the current state. Figure 2 also depicts command decode logic 54 being coupled to command register 53 and state latches and logic 57, and generating an appropriate legal code 101. Command decode logic 54 decodes the signal received as signal 102, only if the current state does not prohibit the command for being out of sequence or some other reason. For example, a hexadecimal code 0x90h represents a read intelligent identifier command instruction. If this code is received during a normal read sequence, the output of command decode logic 54 is asserted to signal the control circuitry via a line 113 to perform the necessary tasks for the command. However, if the same code is received in the middle of a program cycle, command decode logic 54 detects that the code is not valid during the program cycle operation, and the output of command decode logic 54 will not assert the signal for the operation. A state clock generator 56 is coupled to command clock generator 55 through a line 112. On a high going edge of either CE or WE, a line 105 will typically be deasserted, and as a result signals 107, 104 and 110 will also typically be deasserted. Upon the deassertion of line 107, a line 112 is asserted and state clock generator 56 is activated. Upon activation, state clock generator 56 generates a pulse on a line 108 of a predetermined duration. State latches and logic 57 are coupled to state clock generator 56 through line 108. Because of the serial clocking nature of lines 103 and 108, and the fact that by the time line 108 is asserted, a line 101 is valid, state latches and logic 57 does not need to be coupled to the data bus as described in prior art inventions. Instead, the state is received off data bus 106 by command register 53. State latches and logic 57, depending upon the low going edge of line 108, the current state, and the valid decoded command on line 101, transitions to the next appropriate state. The control logic of the chip is coupled to state latches and logic 57 through line 113. A state transition is reflected on line 113, and the control logic generates the necessary signals to effect the change of state. State latches and logic 57 is also typically coupled to an address clock generator 59 and a data clock generator 58 through a line 111. Address clock generator 59 and data clock generator 58 are further normally coupled to clock generator circuit 52 through lines 110 and 104. Upon receiving a signal from lines 110 and 104, address clock generator 59 and data clock generator 58, depending on line 111 which signifies whether latching of address and data is necessary, send strobe timing signals to address and data latches. In the preferred embodiments of the present invention, any pulses shorter than 20 ns are filtered. This enables the memory array to work in noisy systems. It will be recognized that other durations may be substituted for the 20 ns duration in the present system without loss of generality. In a specific memory array which embodies the present invention, the memory array operates at a cycle time of 60 ns, of which 50 ns is the amount of the time that CE or WE is typically held low. This leaves state clock generator 56 only 10 ns to latch a signal on line 108, which is typically not sufficient for reliable operation. However, the present invention provides clock generator circuit 52, which delays the output signal on line 107 by 20 ns. This 20 ns delay, when added to the existing 10 ns time period, provides a latch duration of 30 ns, which is normally sufficient for reliable operation. This present invention is able to turn the parallel design approach of the prior art, as described in Figure 1, into a serial event driven command port architecture, as shown in Figure 2. This results directly from the incorporation of the glitch filter implemented in clock generator circuit 52. The present invention eliminates the need to couple the data bus directly to the state machine, and also eliminates incorrect opcodes, or commands, before they are received by state latches and logic 57. Because it is known that incorrect or invalid opcodes, or commands, are eliminated before reaching the state machine, the design of the state machine can be simplified. Figure 4 is a block diagram of an exemplary computer 45 that may incorporate the present invention. The computer 45 includes a microprocessor 46 and corresponding clock 48. The microprocessor 46 contains the central processing unit (CPU) and associated control circuitry. The microprocessor 46 is connected to a motherboard 49. An I/O interface module 47 is connected to the motherboard 49 and interfaces the microprocessor 46 with peripheral devices such as a monitor and printer. The motherboard 49 also contains a plurality of memory modules for storing data, such as single in¬ line memory modules (SIMMs) 50A-50N. The motherboard 49 is typically implement with a printed circuit board, and the SIMMs 50A-50N are typically implemented with integrated circuit chips which "plug into" the motherboard 49. A non-volatile memory is usually used on the motherboard 49, SIMMs 50A-50N, or through the I/O interface module 47. The foregoing description, which has been disclosed by way of the above examples and discussion, addresses preferred embodiments of the present invention encompassing the principles of the present invention. The embodiments may be changed, modified, or implemented using various circuit types and arrangements. Those skilled in the art will readily recognize that modifications and changes may be made to the present invention without strictly following the exemplary embodiments and applications illustrated and described herein, without departing from the true spirit and scope of the present invention which is set forth in the following claims.

Claims: What is claimed is: 1. An internal command architecture for an electrically erasable and programmable memory having a memory array composed of a number of selectively ordered floating gate memory devices, comprising: a filtering and clock generation circuit for preventing an asserted control signal or signals less than a predetermined duration of time from initiating direction of execution of a command upon data associated with a particular memory device in the memory array; a data bus operatively coupled to the memory array for transferring within the command architecture an externally generated command and a series of data, each data in the series associated with a particular memory device in the memory array; and a command register operatively coupled to said data bus and said filtering and clock generation circuit for serially reading off said data bus the externally generated command and the series of data and directing execution of the command upon each data in the series incident to receiving for each data a signal from said filtering and clock generation circuit. 2. The internal command architecture of claim 1, wherein the series of data comprises of a single data associated with a particular memory device in the memory array. 3. The internal command architecture of claim 1, wherein the series of data comprises of a plurality of data, each data associated with a particular memory device in the memory array. 4. The internal command architecture of claim 1, further comprising an enable control circuit operatively coupled to said filtering and clock generation circuit for asserting the control signal to said filtering and clock generation circuit incident to receiving an externally generated enable signal or signals. 5. The internal command architecture of claim 1, wherein said filtering and clock generation circuit prevents a control signal less than substantially 20 nanoseconds (ns) in duration from initiating direction of execution of a command upon data associated with a particular memory device in the memory array. 6. The internal command architecture of claim 1, wherein said data bus comprises a plurality of control and data pins. 7. The internal command architecture of claim 4, wherein said enable control circuit asserts the control signal to said filtering and clock generation means incident to receiving an externally generated write- enable (WE) signal and an externally generated chip- enable (CE) signal. 8. The internal command architecture of claim 4, wherein said enable control circuit asserts the control signal to said filtering and clock generation means incident to receiving a high-voltage programming voltage. 9. The internal command architecture of claim 4, wherein said enable control circuit asserts the control signal to said filtering and clock generation means incident to receiving a high-voltage erasure voltage. 10. An electrically erasable and programmable memory device comprising: a memory array comprised of a plurality of selectively ordered floating gate memory devices; a filtering and clock generation circuit for preventing an asserted control signal or signals less than a predetermined duration of time from initiating direction of execution of a command upon data associated with a particular memory device in the memory array; a data bus operatively coupled to the memory array for transferring within the command architecture an externally generated command and a series of data, each data in the series associated with a particular memory device in the memory array; and a command register operatively coupled to said data bus and said filtering and clock generation circuit for serially reading off said data bus the externally generated command and the series of data and directing execution of the command upon each data in the series incident to receiving for each data a signal from said filtering and clock generation circuit. 11. The memory device of claim 10, wherein the memory device comprises a flash EPROM. 12. A computer, comprising: a microprocessor; a timing unit; an I/O interface module; a volatile memory array; a non-volatile memory array comprised of a plurality of selectively ordered floating gate memory devices; a filtering and clock generation circuit for preventing an asserted control signal or signals less than a predetermined duration of time from initiating direction of execution of a command upon data associated with a particular memory device in the memory array; a data bus operatively coupled to the non¬ volatile memory array for transferring within the command architecture an externally generated command and a series of data, each data in the series associated with a particular memory device in the non-volatile memory array; and a command register operatively coupled to said data bus and said filtering and clock generation circuit for serially reading off said data bus the externally generated command and the series of data and directing execution of the command upon each data in the series incident to receiving for each data a signal from said filtering and clock generation circuit. 13. A method for administering the execution of commands in an electrically erasable and programmable memory having a memory array composed of a number of selectively ordered floating gate memory devices, comprising the steps: asserting a control signal or signals to initiate execution of a command upon data associated with a particular memory device in the memory array; filtering the control signal or signals to prevent unintended direction of execution of a command upon data associated with a particular memory device in the memory; and transferring serially an externally generated command and a series of data, each data associated with a particular memory device in the memory array. 14. The method of claim 13, further comprising the step of directing execution of the externally generated command upon each data in the series. 15. An electrically erasable and programmable memory device fabricated on a silicon substrate, comprising: a memory array; a command controller coupled to the memory array which performs a memory operation with respect to the memory array; a plurality of address pins and data pins coupled to the memory array which receives an address from an external processor via the address pins and supplying data from the memory array to the external processor via the data pins; command latching means coupled to the plurality of data pins for receiving a command from the external processor via the data pins; a command decoder coupled to the command latching means which decodes the command from the external processor; a command clock generator coupled to the command latching means for generating a command timing signal for latching the command from the external processor into the command latching means; a state clock generator coupled to the command clock generator which generates a state timing signal after the command timing signal has completed latching the command from the external processor into the command latching means; and state latching means coupled to the command decoder and state clock generator for tracking a sequence of commands and for sending a predetermined control signal to the command controller. 16. The memory device of claim 15, wherein the memory operation comprises a read operation, a programming operation and an erasure operation. 17. The memory device of claim 15, wherein the memory device comprises a flash EPROM. 18. The memory device of claim 15, wherein the state latching means selectively inhibits the decoding of a command from the external processor according to a predetermined state. 19. The memory device of claim 18, further comprising: data latching means coupled to the data pins which receives data from the external processor; a data clock generator coupled to the data latching means which generates a data timing signal for latching the data from the external processor into the data latching means; address latching means coupled to the address pins for receiving the address from the external processor; and an address clock generator coupled to the address latching means which latches the address from the external processor into the address latching means. 20. An electrically erasable and programmable memory device fabricated on a silicon substrate, comprising: a memory array; a command controller coupled to the memory array which performs a memory operation with respect to the memory array; a plurality of address pins and data pins coupled to the memory array which receives an address from an external processor via the address pins and supplying data from the memory array to the external processor via the data pins; void detection means coupled to the control pins for detecting a void condition and for generating a first enable signal; and pulse width detection means coupled to the void detection means for generating a second enable signal if the duration of the first enable signal is greater than a predetermined duration. 21. The electrically erasable and programmable memory device of claim 20, wherein the first enable signal comprises a first voltage level and a second voltage level; and wherein the second enable signal comprises a third voltage level and a fourth voltage level, the second enable signal being adapted to change from the third voltage level to the fourth voltage level when the first enable signal changes from the first voltage level to second voltage level, the second enable signal further being delayed by a predetermined duration from changing from the fourth voltage level to the third voltage level when the first enable signal changes from the second voltage level to the first voltage level. 22. The electrically erasable and programmable memory device of claim 21, further comprising: command latching means coupled to the plurality of data pins for receiving a command from the external processor via the data pins; a command decoder coupled to the command latching means which decodes the command from the external processor; a command clock generator coupled to the command latching means which generates a command timing signal for latching the command from the external processor into the command latching means; a state clock generator coupled to the command clock generator which generates a state timing signal after the command timing signal has completed latching the command from the external processor into the command latching means; and state latching means coupled to the command decoder and state clock generator for tracking a sequence of commands and for sending a predetermined control signal to the command controller. 23. The electrically erasable and programmable memory device of claim 22, further comprising: data latching means coupled to the data pins for receiving data from the external processor; a data clock generator coupled to the data latching means and the pulse width detection means which generates a data timing signal for latching the data from the external processor into the data latching means; address latching means coupled to the address pins for receiving the address from the external processor; and an address clock generator coupled to the address latching means and the pulse width detection means which latches the address from the external processor into the address latching means. 24. The electrically erasable and programmable memory device of claim 22, wherein the memory operation comprises a read operation, a programming operation and an erasure operation. 25. The electrically erasable and programmable memory device of claim 15, wherein the command controller is enabled when the command controller receives a high voltage programming voltage. 26. The electrically erasable and programmable memory device of claim 15, further comprising means for enabling the command controller when the command controller receives a high voltage erasure voltage. 27. The electrically erasable and programmable memory device of claim 22, wherein the command controller is enabled when the command controller receives a high voltage programming voltage. 28. The electrically erasable and programmable memory device of claim 22, wherein the command controller is enabled when the command controller receives a high voltage erasure voltage. 29. The electrically erasable and programmable memory device of claim 22, wherein the memory device comprises a flash erasable and programmable read-only memory. 30. The electrically erasable and programmable memory device of claim 20, wherein the pulse width detecting means comprises a plurality of serially coupled buffers, and wherein an input to a first stage of the serially coupled buffers and an output from a second stage of the serially coupled buffers are coupled as separate inputs to a gate, such that a delay caused by the serially coupled buffers determines a minimum pulse width. 31. The electrically erasable and programmable memory device of claim 21, wherein the delay of the second enable means is generated by a plurality of serially coupled buffers, wherein an input to a first stage of the serially coupled buffers and an output from a second stage of the serially coupled buffers are coupled as separate inputs to a gate, such that a delay caused by the serially coupled buffers determines the delay of the second enable means.

Inventors: ROOHPARVAR FRANKIE FARIBORZ, ROOHPARVAR, FRANKIE, FARIBORZ
Applicants: MICRON QUANTUM DEVICES INC, MICRON QUANTUM DEVICES, INC.
Application year: 1996
Main classification: G11C16
IPC codes: G06F12, G11C16