Circuit for the generation of a voltage as a function of the conductivity of an elementary cell, particularly for non-volatile memories

Abstract: A circuit for the generation of a voltage as a function of the conductivity of an elementary cell, particularly for non-volatile memories, comprising a non-volatile element (1) that is substantially identical to a generic cell of a memory matrix; a structure (2) for biasing the drain terminal of the non-volatile element (1); a branch for sensing the current that flows through the non-volatile element; and a branch for mirroring the current sensed by the current sensing branch, the mirroring branch containing at least one transistor (8) the gate terminal whereof is controlled by a first output voltage (V=f(Icell)) . The mirroring branch produces the first output voltage, the value whereof is a function of the current (Icell) that flows through the non-volatile element and is sensed by the current sensing branch, and the biasing structure (2) produces a second voltage that is substantially constant (Vref) and is used as a reference voltage for the first voltage (V=f(Icell)) .

Description: The present invention relates to a circuit for the generation of a voltage as a function of the conductivity of an elementary cell, particularly for non-volatile memories. In the execution of non-volatile memory cells, there are often circuit parts which require, for their correct operation, a close correlation to the conductivity of the elementary cell of the memory. For example, in non-volatile memories using dynamic or latch data sensing structures, this correlation with the conductivity of the elementary cell is very important. When such sensing structures are used, it becomes very important to be able to determine with certainty both the right moment for evaluating the data of the memory (for reading) and the subsequent timing to achieve data capture. Generally, the evaluation step comes after an initial step for precharging the nodes involved in the reading operation in order to bring said nodes to the active level and to equalize the lines to which the memory cells are connected. After the equalization step, these lines must be given the time to set themselves to the reading values, so as to allow correct data reading. The possibility of using a given time structure by presetting beforehand a minimum wait time before reading the data has the drawback that it does not flexibly adapt to the dynamic characteristics of the various memory cells provided by possible different supply voltages, operating temperatures, different technologies used in the execution of the cells, etcetera. In particular, the fixed timing for the events linked to the reading of a memory cell penalizes both the case in which the cell has a low conductivity and the case in which it has a high conductivity. In the first case, in fact, the timing should be expanded, since certainty of the capture of the data item for reading is achieved with longer times than in the case of a cell having higher conductivity. On the other hand, in the second case, the higher conductivity of a cell is not utilized with a fixed timing, since the possibility of shortening the read time of said cell is not offered by the conventional circuitry. This static nature of the various reading steps entails useless delays during reading, when the current flowing through the memory cell is high and it would be possible to shorten its reading, since certainty of data capture is achieved in a shorter time; moreover, this forces to set the periods of the timing to a value that is long enough to ensure cell reading even in the worst case of the conductivity of said cell. Another crucial problem for reading is the first reading operation, if it is performed in a transient state of the power supply, i.e., when the level of the supply voltage has not reached a steady state but reading is nonetheless attempted. This reading operation can therefore occur too early (before reaching the actual conductivity conditions of the non-volatile memory cell, which are notoriously higher than in normal CMOS devices) and therefore be unreliable with no possibility of recovery. US-4 954 990 discloses a programming voltage control circuit for EPROMS that compensate for variations in the applied programming voltage to maintain the actual programming voltage substantially constant. A principal aim of the present invention is therefore to provide a circuit for the generation of a voltage as a function of the conductivity of an elementary cell, particularly for non-volatile memories, that allows to generate a first voltage and a second voltage, said first voltage acting as a reference for the second voltage, as a function of the conductivity of the elementary memory cell. Within this aim, an object of the present invention is to provide a circuit for the generation of a voltage as a function of the conductivity of an elementary cell that allows to adapt the read timing of a memory cell to the conductivity of said cell. Another object of the present invention is to provide a circuit for the generation of a voltage as a function of the conductivity of an elementary memory cell that allows to block the memory data reading stream if the memory cell fails to reach the conductivity conditions. Another object of the present invention is to provide a circuit for the generation of a voltage as a function of the conductivity of an elementary memory cell that allows to appropriately modulate the sensitivity of the sense amplifiers that capture the data from the memory cells. Another object of the present invention is to provide a circuit for the generation of a voltage as a function of the conductivity of an elementary cell that allows to provide delays that are correlated to the conductivity of the cell. Another object of the present invention is to provide a circuit for the generation of a voltage as a function of the conductivity of an elementary cell that can also be used in the presence of boost voltages. Another object of the present invention is to provide a circuit for the generation of a voltage as a function of the conductivity of an elementary memory cell that allows to produce a reference voltage and as a function of the conductivity of a memory cell, so as to generate, more generally, any delay function, level function, etcetera, correlated to the conductivity of the memory cell. Another object of the present invention is to provide a circuit for the generation of a voltage as a function of the conductivity of an elementary memory cell that allows to configure a plurality of voltage states that are correlated to the conductivity and allow to provide a plurality of classes of performance for memory devices. Another object of the present invention is to provide a circuit that is highly reliable and relatively easy to produce at competitive costs. This aim, these objects, and others which will become apparent hereinafter are achieved by a circuit for the generation of a voltage as a function of the conductivity of an elementary cell, as defined in claim 1. Further characteristics and advantages of the invention will become apparent from the description of a preferred but not exclusive embodiment of the device according to the invention, illustrated only by way of non-limitative example in the accompanying drawings, wherein: figure 1 is an exemplifying circuit diagram of a first embodiment of the circuit according to the invention; figure 2 is an exemplifying circuit diagram of a second embodiment of the circuit according to the invention; figure 3 is a detailed circuit diagram of the circuit shown in figure 1; figure 4 is a detailed circuit diagram of the circuit shown in figure 2; figure 5 is a detailed circuit diagram of a third embodiment of the circuit according to the invention; and figure 6 is a chart plotting the voltages generated by the circuit according to the invention in case of different conductivity values of the elementary memory cell. With reference to figures 1 and 3, which illustrate a first embodiment of the circuit according to the invention, said circuit comprises: an elementary cell, identical to a generic matrix cell and designated by the reference numeral 1, which is provided by means of a floating gate transistor; a branch for "following" the current of the generic cell 1, which acts as a mirroring branch; a branch for mirroring the current of the generic cell 1; means 2 for biasing the drain terminal of the elementary cell 1; and level adapting means 3 that allow to use the circuit according to the invention in the presence of mixed supply voltages, i.e., when there is also a boost voltage. The elementary cell 1 is chosen among a matrix of cells, taking the central cell as sample so that it is fully identical to a generic memory cell. The means 2 for biasing the drain terminal of the elementary cell 1 comprise a structure that is for example of the cascode type. In greater detail, a disable signal DIS is sent in input to the cascode structure 2 and to the level adapting means 3, which are connected to the ground and the output whereof is sent to the gate terminal of the elementary cell 1. The level adapting means 3, which comprise a booster structure, are supplied with a voltage that varies between the supply voltage V DD and the boost voltage. The branch for following the current Icell of the cell 1 (mirroring branch) comprises a first transistor 4 for sensing the current Icell of the cell 1, advantageously of the P-channel type, the source terminal whereof is connected to the supply voltage V DD and the drain terminal whereof is feedback-connected to the gate terminal and also connected to the drain terminal of a second biasing transistor 5, which is advantageously of the native low-threshold type. The transistor 5 is connected, by means of its source terminal, to the drain terminal of the elementary cell 1 and also receives, at its gate terminal, the output of the cascode structure 2. The branch for mirroring the current Icell of the elementary cell 1 in turn comprises a third transistor 6, advantageously of the P type, which is identical to the transistor 4 of the mirroring branch. Said transistor 6 is connected to the drain terminal of the transistor 4 by means of its gate terminal, to the supply voltage V DD by means of its source terminal, and to the drain terminal of a fourth biasing transistor 7 by means of its drain terminal; said biasing transistor 7 receives, at its gate terminal, the output of the cascode structure 2, and its source terminal is connected to a fifth transistor 8, the gate terminal whereof is controlled by the output voltage V=f(Icell), which is a function of the current flowing through the elementary cell 1. The voltage that is present on the gate terminal of the transistor 7 is taken as reference voltage Vref=f(Icell). The fourth transistor 7, like the transistor 5, is advantageously also a low-threshold native transistor. Additional transistors 9, 10, and 11, all of which receive in input the output voltage of the circuit V=f(Icell) , are programmable, by means of respective programming means advantageously provided by fuses 12 and 13, for their activation so as to lower the output voltage V=f(Icell). Said additional transistors 9, 10, and 11 are fully similar to the transistor 8 (of the N-channel type) and are connected as shown in figure 1. Respective transistors 12' and 13' are connected to the fuses 12 and 13. Figure 3 is a more detailed circuit diagram of figure 1. In this figure, and in all subsequent figures, the same reference numerals used in figure 1 are assigned to identical elements. In particular, figure 3 shows in detail the voltage adapting means constituted by a booster structure 3. The individual transistors 12' and 13', shown for the sake of simplicity in figure 1, are here shown explicitly in their real configuration. Therefore, the block designated by the reference numeral 12' in figure 3 comprises a pair of pass transistors 14, formed by a P-type transistor and by an N-type transistor, and an N-channel transistor 15, the gate terminal whereof receives the output signal from the programming means 12 and the source terminal whereof is connected to the ground. The pair of pass transistors 14 is connected to the voltage V=f(Icell) on one side and to the drain terminal of the transistor 15. The output signal from the programming means 12 reaches the gate terminal of the P-type transistor and, after being inverted in an inverter 16, the gate terminal of the N-type transistor of the pair of pass transistors 14. Likewise, the block designated by 13' comprises the same elements as the above-described block 12'. The elements of said block designated by 17, 18, and 19 correspond to the elements designated by 14, 15, and 16, respectively, in the block 12'. The cascode structure 2 is shown explicitly in its components in figure 3. It comprises a NOR gate with two inputs. A first input of the NOR gate is connected to the enable/disable line DIS, whereas the second input is connected to the drain terminal of the elementary cell 1. The output of the NOR gate is connected to the line that connects the gate terminals of the transistors 5 and 7 with a regulating function. An N-type transistor 21 is connected to the second input of the NOR gate by means of its drain terminal, is connected to the ground by means of its source terminal, and is connected to the line carrying the signal DIS by means of its gate terminal. The disable/enable line DIS is furthermore input to an inverter 22, the output whereof drives the gate terminal of a P-channel transistor 23. The transistor 23 is connected to the supply voltage by means of its source terminal and is connected to the drain terminal of the transistor 7 by means of its drain terminal. A further transistor 30 receives the signal DIS in input to its gate terminal; its source terminal is connected to the ground and its drain terminal is connected to the line that connects the source terminal of the transistor 7 and the drain terminal of the transistor 8. Figure 2 illustrates a second embodiment of the circuit according to the invention, in which means for limiting the output voltage V=f(Icell) are provided. Said means comprise a P-channel transistor 20 of the native type with a high threshold (approximately 1.6 V). In said transistor 20, the source terminal is connected to the supply voltage V DD , the gate terminal is connected to the gate terminal of the transistor 4 (and is therefore also connected to the drain terminal of the same transistor) and the drain terminal is connected to the gate terminal of the transistor 6. The insertion of the transistor 20 is also shown in figure 4, which illustrates in detail the circuit of figure 2. Therefore, the only difference between figure 3 and figure 4 is indeed constituted by the addition of this transistor 20. Figure 5 illustrates a third embodiment of the circuit according to the invention, in which means 31 for limiting the supply voltage (V DD /boost) in input to the gate terminal of the elementary cell 1 are provided. Said means 30 comprise four P-type transistors 24, 25, 26, and 27, which are connected between the supply voltage V DD /boost and the ground; the drain terminal of each transistor is connected to the source terminal of the next transistor. The drain terminal of the transistor 24 is connected to the gate terminal of the elementary cell 1. The transistor 25 is of the native high-threshold type. The gate terminal of the transistor 24 is connected to the output of the level adapting means 3, the gate terminal of the transistor 25 is connected to its drain terminal, the gate terminal of the transistor 26 is connected to its drain terminal, and the gate terminal of the transistor 27 is connected to the source terminal of a further fifth N-type transistor 28, the gate terminal whereof is connected to the output of the level adapting means 3. The drain terminal of the transistor 28 is connected to the drain terminal of the transistor 24. Figure 6 plots the two voltages generated by the circuit according to the invention in two different cases of conductivity of the elementary cell 1 and will be explained with reference to the operation of the circuit. With reference to the above figures, and particularly to figures 1 and 3, the operation of the circuit according to the invention is as follows. When the signal DIS is high, the transistor 21 is on, the transistor 30 is on, and the transistor 23 is also on. Therefore, the node B is connected to the ground and the output of the NOR gate is low, the transistors 7 and 5 are off, and there is no flow of current, since the node C is also connected to the ground. When the signal DIS in input to the cascode structure 2 and to the level adapting means changes from high to low, indicating the enabling of the circuit according to the invention, the condition is the opposite of the previous one: a voltage equal to the supply voltage that is present at that given time is supplied to the gate terminal of the cell 1. Therefore, the voltage is either V DD or the boost voltage. The cascode structure 2 (the NOR gate) and the transistor 5 bias the drain terminal of the cell 1, supplying said terminal with a voltage that is approximately equal to 1 V (node B). At this point, a voltage equal to approximately 1 V plus a threshold voltage given by the threshold voltage of the transistor 5 is present at the gate terminal of the transistor 5. Therefore, a current Icell determined by the voltage that is present at the gate terminal of the elementary cell 1 flows in said cell. The P-channel transistor 4 delivers the current that the cell 1 requires according to the value of the voltage that is present at its gate terminal. The transistor 4 then mirrors the value of the current Icell on the mirroring transistor 6 according to a preset mirroring ratio. The mirroring ratio can be smaller than, greater than, or equal to one, according to the requirements. The current that flows in the transistor 8 at this point is therefore correlated to the mirroring ratio and is I specchio /n, where n is the number of transistors similar to the transistor 8. If the transistor 8 is the only transistor that is on, the mirroring ratio is one. The current I specchio is the current that flows through the transistor 6 and is mirrored by the transistor 4 that senses the conductivity of the elementary cell 1. The node A thus reaches a voltage value that is correlated, according to the mirroring ratio, to the current flowing in the mirroring branch. An output voltage V=f(Icell) is thus obtained which is proportional to the current Icell that flows through the elementary cell 1. If the mirroring ratio is 1:1, then the voltage level at the node A is such that the current of the mirroring branch is equal to the current that is present on the mirroring branch. The voltage that is present at the gate terminal of the transistor 7 is substantially constant, and is scarcely affected by the variation in the conductivity of the elementary cell 1. In this manner, there is a second output voltage that can be taken as reference voltage Vref, since it substantially depends on the supply voltage and not on the conductivity of the elementary cell 1. If the transistors 9, 10, and 11 are also switched on because they are appropriately programmed, the mirroring ratio changes according to the number of said transistors that add themselves to the transistor 8. The transistors 9, 10, and 11 are identical to the transistor 8 and receive, at their gate terminals, the output voltage V=f(Icell) . The number of these transistors is of course not restricted to three, as shown in figure 1, but in theory it is possible to have a number n of identical transistors; i.e., the mirroring ratio is n = 1 ... m. The voltage at the node A, by virtue of the switching on of additional transistors, decreases according to the number of on transistors, since the current that flows through the mirroring transistor 6 also flows in a number of transistors that can vary according to requirements. The voltage V=f(Icell) can thus be configured through the appropriate switching on of transistors that are similar to the transistor 8. The possibility of producing a voltage V=f(Icell) that is a function of the conductivity of the elementary cell 1 and can be modulated according to the number of transistors 9, 10, 11, ... that are on, allows to "center" the output voltage of the circuit according to the operating requirements that said voltage must meet. The possibility of configuring the transistors that determine the mirroring ratio causes the fact that once the number of said transistors that must be on has been determined, the output voltage V=f(Icell) is only a function on the conductivity of the memory cell 1. With reference to the practical circuital embodiment of the block 12' (and of the similar block 13') in figure 3, operation is as follows. When the programming means 12 carry a high signal in input to the block 12', which indicates a virgin condition of the transistors, the P transistor of the pair of pass transistors 14 is off and so is the N transistor of said pair 14; the transistor 15 is instead on. In this manner, the transistors 10 and 11 (likewise for the transistor 9) are not enabled, i.e., the voltage V=f(Icell) does not reach their gate terminals, the current I specchio that is present on the mirroring branch does not distribute in the branch of the two transistors 10 and 11 as well, and the voltage V=f(Icell) does not decrease. On the contrary, if the programming means 12 (and 13) carry a low signal in input to the block 12' (and to the block 13'), the pair of pass transistors 14 is activated and the path to the ground provided by the transistor 15 is interrupted. In this case, the current I specchio also redistributes on the branch comprising the transistors 10 and 11 and the output voltage V=f(Icell) decreases. The transistors 9 and 10-11 can, as shown, be enabled separately or together according to the requirements, in order to lower the value of the voltage V=t(Icell) that can be obtained in output. The transistor 8 instead has the purpose of setting the maximum value of the voltage V=f(Icell) that can be obtained in output, as a function of the conductivity of the elementary cell. With reference to figures 2 and 4, the means for limiting the output voltage V=f(Icell) constituted by the transistor 20 allow to limit the output voltage when said voltage, which is a function of the conductivity of the cell 1, would be too high. The transistor 20 modulates V=f(Icell) in a controlled manner. Until the transistor 20 intervenes, the mirroring ratio between the transistors 4 and 6 is maintained. As the current increases, the transistor 20 intervenes, limiting the output voltage. With reference to figure 5, the means 31 for limiting the supply voltage set a maximum voltage value to be carried to the gate terminal of the elementary cell 1. Said value is set by the thresholds of the transistors 25, 26, and 27. In fact, when a low level is present in output from the voltage adapting means 3, the transistor 28 is off, the transistor 24 is on, and therefore the voltage at the gate terminal of the elementary cell 1 is limited by the thresholds of the transistors 25, 26, and 27. The chart of figure 6 plots various behaviors of the output voltage V=f(Icell) with respect to the reference voltage Vref, as a function of the conductivity of the elementary cell 1. It is in fact evident that the output voltage V=f(Icell) differs increasingly from Vref as the conductivity of the elementary cell 1 increases or decreases. The curves in the chart of figure 6, from the uppermost one to the lowermost one, represent decreasing values of cell conductivity. The lowest curve represents the case in which the conductivity of the memory cell is zero and the voltage drops to the threshold of the transistor 8, which accordingly is not affected by any current. In practice it has been observed that the circuit according to the invention fully achieves the intended aim, since it allows to generate, starting from an elementary memory cell, two voltages, one whereof is highly correlated to the conductivity of the cell. The first voltage acts as reference for the second voltage and is intrinsically weakly dependent on the conductivity of the cell, whereas the second voltage is closely correlated to said conductivity. These two voltages thus obtained can be used for example to optimize the timings of a data read cycle of a memory cell: the timings thus become dependent on the actual conductivity of the memory cell, overcoming the drawback of having to preset standard timings that can adapt to the different operating conditions so as to always ensure correct data reading. These voltages obtained from the circuit according to the invention can furthermore be used to appropriately modulate the sensitivity of the sense amplifiers meant to capture the data for reading. Finally, the possibility of having two voltages, one whereof is a reference voltage, linked to the conductivity of a memory cell, is useful in all those cases in which it is necessary to provide functions or operations that are closely correlated to the dynamics of a memory cell, including the suppression of the reading of the cell in case of zero conductivity thereof. The circuit thus conceived is susceptible of numerous modifications and variations, all of which are within the scope of the inventive concept. Thus, for example, the natural transistors 5 and 7 of the N type can be replaced with normal N-type transistors, LVS transistors, with a slightly higher threshold. Finally, all the details may be replaced with other technically equivalent elements. In practice, the materials employed, so long as they are compatible with the specific use, as well as the dimensions, may be any according to the requirements and the state of the art. Where technical features mentioned in any claim are followed by reference signs, those reference signs have been included for the sole purpose of increasing the intelligibility of the claims and accordingly such reference signs do not have any limiting effect on the interpretation of each element identified by way of example by such reference signs.

Claims: A read circuit for the generation of a first output voltage (V=f(Icell)) as a function of the conductivity of an elementary cell, particularly for non-volatile memories, to adapt the read timing of a memory cell to the conductivity of said cell, comprising a non-volatile elementary cell (1) that is substantially identical to said memory cell; a structure (2) for biasing the drain terminal of said non-volatile elementary cell (1); a branch (4) for sensing the current that flows through said non-volatile elementary cell; and a branch (6) for mirroring the current sensed by said current sensing branch, said mirroring branch containing at least one transistor (8) the gate terminal whereof is controlled by a first output voltage (V=f(Icell)), said mirroring branch producing said first output voltage, the value whereof is a function of the current (Icell) that flows through said non-volatile elementary cell, sensed by said current sensing branch, said biasing structure (2) producing a second voltage (Vref) that is substantially constant and is used as a reference voltage for said first voltage (V=f(Icell)). The circuit according to claim 1, characterized in that it comprises means (3) for adapting the level of the supply voltage (Vdd) for said non-volatile elementary cell, said adapting means being interposed between said non-volatile elementary cell and the ground. The circuit according to claim 2, characterized in that said biasing structure (2) and said level adapting means (3) are driven by a disable/enable signal. The circuit according to claim 1, characterized in that it comprises means (20) for limiting said first output voltage (V=f(Icell)) that are connected between said current sensing branch (4) and said mirroring branch (6). The circuit according to claim 1, characterized in that it comprises means (31) for limiting the supply voltage to said non-volatile elementary cell, said means being connected between said means (3) for adapting the level of the supply voltage and said non-volatile elementary cell. The circuit according to claim 1, characterized in that said branch for sensing the current that flows through said non-volatile elementary cell comprises a first transistor (4) of a first polarity and a second transistor (5) of a second polarity. The circuit according to claim 6, characterized in that in said first transistor (4) of a first polarity, the source terminal is connected to the supply voltage, the drain terminal is connected to the drain terminal of said second transistor (5) of a second polarity, and the gate terminal is connected to its drain terminal. The circuit according to claim 6, characterized in that said second transistor (5) of a second polarity is driven, at its gate terminal, by said biasing structure (2) and in that its source terminal is connected to the drain terminal of said non-volatile elementary cell (1). The circuit according to claim 1, characterized in that said mirroring branch comprises a third transistor (6) of a first polarity, a fourth transistor (7) of a second polarity, and said at least one transistor (8), the gate terminal whereof is controlled by said first output voltage, said at least one transistor setting the maximum level of said output voltage. The circuit according to claim 9, characterized in that said third transistor (6) of a first polarity is connected to the supply voltage by means of its source terminal, to the drain terminal of said first transistor (4) by means of its gate terminal, and to the drain terminal of said fourth transistor (7) of a second polarity by means of its source terminal. The circuit according to claim 10, characterized in that said third transistor (6) is equal to said first transistor (4). The circuit according to claim 10, characterized in that said fourth transistor (7) is connected, by means of its gate terminal, to the output of said voltage level adapting means (3) and, by means of its source terminal, to the drain terminal of said at least one transistor (8), the gate terminal whereof is controlled by said first output voltage. The circuit according to one or more of the preceding claims, characterized in that said second (5) and fourth (7) transistors are native high-threshold transistors. The circuit according to claim 1, characterized in that it comprises a plurality of transistors (9, 10, 11) that are identical to said at least one transistor (8), the gate terminal whereof is controlled by said first output voltage, the gate terminals of said plurality of transistors being likewise controlled by said first output voltage (v=f(Icell)), so as to lower said first output voltage as a function of the number of said plurality of transistors that are present. The circuit according to claim 14, characterized in that said plurality of transistors (9, 10, 11) is driven by means for enabling/disabling said plurality of transistors. The circuit according to claim 4, characterized in that said means (20) for limiting said first output voltage comprise a transistor of a first polarity, of the native type, which has a high threshold, in which the source terminal is connected to the supply voltage, the drain terminal is connected to said current sensing branch and to said mirroring branch, and the gate terminal is connected to said current sensing branch. The circuit according to claim 1, characterized in that said non-volatile elementary cell (1) is a floating-gate transistor of a second polarity. The circuit according to one or more of the preceding claims, characterized in that said transistors of a first polarity are P-channel transistors. The circuit according to one or more of the preceding claims, characterized in that said transistors of a second polarity are N-channel transistors. The circuit according to claim 1, characterized in that said voltage level adapting means (3) receive in input a voltage that can be switched between the supply voltage and a boost voltage.

Inventors: PASCUCCI LUIGI, PASCUCCI, LUIGI
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1996
Main classification: G11C16
IPC codes: G11C16, G05F3