Switching circuit and composite arrangement

Abstract: A switching circuit further decreasing the insertion loss. The first capacitor is connected between the drain terminal of the field effect transistor and the ground and/or the second capacitor is connected between the source terminal of the field effect transistor and the ground, and the capacitances of the first and/or second capacitors are set in accordance with the signal characteristic. Accordingly, the switching circuit can be easily obtained which is low in insertion loss at a desired frequency. Besides, since a bias circuit for generating bias voltage from control voltage which is applied to the two control terminals of a switching circuit using a field effect transistor is provided, a switching circuit which does not need exclusive bias terminals and is superior in isolation property can be realized.

Description: BACKGROUND OF THE INVENTION FIELD OF THE INVENTION The present invention relates to a switching circuit and a composite switching circuit, and more particularly relates to a switching circuit and a composite switching circuit suitable for switching input/output of a high frequency signal. DESCRIPTION OF THE RELATED ART At present, mobile communication systems such as a mobile telephone, a portable telephone, or the like have been developed as business on a large scale. On the other hand, shortage of communication lines is getting more and more serious in city areas, and various mobile communication systems having been put into practical use in various countries. In many cases, not analog communication systems but digital communication systems are adopted as these mobile communication systems. Further, in such mobile communication systems, a submicrowave band which is on the higher frequency side than the communication frequency band of current mobile communication systems is used as the communication frequency band. In such a communication system which transmits and receives signals of a submicrowave band, semiconductor field-effect transistors (FETs) are often used in a signal processing portion of a portable terminal. Particularly, in the case of a portable terminal in which portability is regarded as important, it is regarded as important to develop a monolithic microwave IC (hereinafter referred to as MMIC) using a GaAs FET which makes it possible to make the portable terminal small in size, low in driving voltage and low in power consumption. Particularly, a high-frequency switch for switching a high-frequency signal in a portable terminal is coming into one of key devices. Operation of an FET will be explained in the case where the FET is used as a switching device. In the case of using the FET in an ON state, a bias voltage sufficiently higher than the pinch-off voltage of the FET is applied to the gate of the FET. In contrast, in the case of using the FET in an OFF state, a bias voltage sufficiently lower than the pinch-off voltage of the FET is applied to the gate of the FET. In this state, when a bias voltage sufficiently higher than the pinch-off voltage of the FET is applied to the gate of the FET, an impedance between the source and the drain of the FET can be made low, so that the FET can be turned on. Further, in this state, when a bias voltage sufficiently lower than the pinch-off voltage of the FET is applied to the gate of the FET, an impedance between the source and the drain of the FET can be made high, so that the FET can be turned off. In the case of a GaAs FET commercially available at present, the FET can be approximated to a resistance component connected between the drain and the source thereof when the FET is in an ON state, while the FET can be approximated to a capacitive component connected between the drain and the source thereof when the FET is in an OFF state. In this case, the resistance and the capacitance of the FET can be made several [Ω/mm] and several hundred [fF/mm] per unit gate width (Wg) of the FET, respectively. The resistance Ron and the capacitance Coff are 2 [Ω/mm] and 300 [fF/mm], for example, respectively. In the case of constituting an FET switch by using such an FET described above, when an FET having a gate width Wg of about 1 [mm] is used, the loss of the FET in an ON state is considered to be suppressed to a small value of about 0.2 [dB] at the time of dealing with a signal of several [GHz] or less. However, when the aforesaid FET switch is used in a portable telephone terminal or the like, a switch IC using the FET or the FET switch is often mounted in a cheap package such as a plastic mold package etc. in order to lower the cost thereof. Such a plastic mold package influences to the insertion loss to an innegligible degree when the signal frequency is a submicrowave band or more. In particular, when bonding wires or the like formed of gold or the like are used to connect between a semiconductor chip and signal pins of the package, there arises a problem that the inductance of the bonding wires greatly influences to the insertion loss of the switch. In fact, this loss is a reflection loss due to the impedance mismatching. For example, when an inductance of 2 [nH] due to the bonding wires or the like is added to each of the input and output terminals of an FET having a gate width Wg of 1 [mm] and a resistance Ron of 2[Ω], the insertion loss increases from 0.2 [dB] to 1.1 [dB] at the frequency of 2 [GHz], for example, as shown by a dotted line in Fig. 6. Thus, it is necessary to decrease an inductance of the bonding wires or the like in order to lower the insertion loss of the switch IC. Further, since the mold package is small in degree of freedom in the mounting condition thereof, it is not easy to decrease the inductance. The inductance may be decreased to some extent when many bonding wires are used in parallel to connect the signal terminals between the semiconductor chip and the package. However, this method may not be preferable since there is such a large defect that a chip area becomes larger. As a method of avoiding such a problem, there is a proposal to decrease the loss due to the bonding wire by using resonance phenomenon caused by an inductance of the bonding wire and a parasitic capacitance existing between a signal path and the ground. In this case, however, each of the parasitic capacitance and the parasitic inductance of the bonding wire is a subsidiary parameter and hence is not a parameter capable of being controlled easily. For example, it is considered to control the parasitic capacitance by adjusting a gate width of the FET formed on an IC chip. However, at the time of employing such a control method, the suitable configuration of the switching circuit may not necessarily be formed and consequently the insertion loss may be raised or the isolation property may be deteriorated. In this manner, there was a problem that it is very difficult to set the inductance of the bonding wires and the parasitic capacitance suitably so as to decrease the insertion loss. As described above, at the time of employing an FET as a switch, it is required to apply the ON bias voltage which is sufficiently larger than the pinch-off voltage and capable of making the ON resistance sufficiently small and to apply the OFF bias voltage capable of completely turning off the FET to the gate terminal of the FET. In most cases, since the pinch-off voltage Vp is set to be 0 [V] or less, a negative voltage is required as the off bias voltage generally. However, since a DC-DC converter or the like is required for a negative power source, it is not preferable to use the negative power source in view of cost, size and power consumption. In order to avoid such a problem due to the negative power source, it is preferable to operate the switch circuit only by a positive power source. In fact, a relative voltage of the gate with respect to the source and the drain can be made negative even when a positive bias voltage (V bias ) is applied to the drain and the source terminals of the FET and a voltage of 0 [V] or more (in general, 0 [V]) is applied to the gate of the FET. In this case, the FET can be controlled in an OFF state (pinch-off state). In this case, however, there arises a problem that a bias terminal for applying the bias voltage (V bias ) is additionally required. Further, the wiring of a bias line extending from the bias (V bias ) terminal may result in the increase of the occupying area of the switching circuit and further the increase of the semiconductor chip size of the IC and the IC package size. Furthermore, the bias terminal causes the deterioration of the isolation property or the like. In addition, at the time of applying the bias voltage (V bias ), the bias voltage (V bias ) is required to be set lower than the ON bias voltage of the gate by almost the built-in voltage V bi in order to obtain a sufficiently low ON resistance. To this purpose, the bias voltage (V bias ) is required to be changed in accordance with the control voltage (ON bias) of the FET. However, such a changing operation is troublesome for a user using a switching IC for controlling a positive power source or the like. Prior art document GB-A-2 157 521 discloses a circuit for driving switches, such as field effect transistors switches. A bias voltage generating means disclosed in this document has first and second control terminals to which first and second voltages having different values are alternatively applied, for generating a bias voltage on the basis of said first and second voltages applied to said first and second control terminals, said bias voltage being applied to the output terminals of said means. Furthermore, it teaches also to apply said bias voltage to a field effect transistor since it discloses to use the output of said means to control a semiconductor switch comprising field effect transistors. SUMMARY OF THE INVENTION It is an object of the present invention to provide a switching circuit driven by a positive power source which is capable of realizing a high isolation property and a composite switching circuit using such switching circuits. To solve this object, the present invention provides a switching circuit as specified in claim 1. Preferred embodiments of the invention are described in the subclaims. A switching includes: a field effect transistor having a signal path formed between a drain and a source thereof; a high-impedance element connected to a gate terminal of the field effect transistor; and a first capacitor connected between the drain terminal of the field effect transistor and a ground or a second capacitor connected between the source terminal of the field effect transistor and the ground. Another switching circuit includes: a bias voltage generating means, having first and second control terminals to which first and second voltages having different values are alternately applied, for generating a bias voltage on the basis of the first and second voltages applied to the first and second control terminals; a field effect transistor having a signal path formed between a drain and a source thereof; and a high-impedance element connected between a gate terminal of the field effect transistor and the first control terminal. Further, a composite switching circuit is formed by combining a plurality of the aforesaid switching circuits. The matching characteristic determined by parasitic inductances existing on the signal path is adjusted by varying the capacitances of the first capacitor which is connected between the drain terminal of the field effect transistor and the ground and/or the second capacitor which is connected between the source terminal of the field effect transistor and the ground. Accordingly, the insertion loss can be further decreased at a desired frequency. Since the bias voltage is generated on the basis of the two kinds of voltages applied to the first and second control terminals, a terminal dedicated for biasing can be eliminated even when a positive power source is employed. Thus, the package and the chip can be further miniaturized by a space corresponding to the bias dedicated terminal. Further, the leakage of the signal through a bias line can be eliminated with the elimination of the bias dedicated line to thereby improve the isolation property. The nature, principle and utility of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings in which like parts are designated by like reference numerals or characters. BRIEF DESCRIPTION OF THE DRAWINGS In the accompanying drawings: Fig. 1 is a connection diagram showing an embodiment of a switching circuit according to the present invention; Fig. 2 is a connection diagram showing an equivalent circuit of a biasing circuit portion in a state where different voltages are applied to two control terminals thereof; Fig. 3 is a connection diagram showing an equivalent circuit of a signal path in a state where the switching circuit is controlled in an ON state; Fig. 4 is a characteristic curvilinear diagram explaining the improvement of the insertion loss by the matching circuit portion; Fig. 5 is a connection diagram explaining a composite switching circuit; and Fig. 6 is a characteristic curvilinear diagram explaining the insertion loss due to a parasitic inductance. DETAILED DESCRIPTION OF THE EMBODIMENT Preferred embodiments of the present invention will be described with reference to the accompanying drawings: (1) Basic Configuration Fig. 1 shows a basic configuration of a switching circuit 1. The switching circuit 1 is characterized by including a bias voltage generating portion 2 for generating a bias voltage on the basis of two kinds of voltages applied to two control terminals CTL1 and CTL2 and a matching circuit portion 3 formed by capacitors C1 and C2 each arranged to ground a signal path therethrough. The explanation will be made at first as to the biasing circuit portion 2, then the explanation will be made as to the matching circuit portion 3. (2) Biasing Circuit Portion The biasing circuit portion 2 is formed by diodes D1, D2 and resistors R4, R5 connected between the two control terminals CTL1, CTL2. The control terminals CTL1 and CTL2 are supplied with two kinds of voltages V (high) and V (low) (V (high) > V (low)) alternately in a manner, for example, that the control terminal CTL2 is supplied with the voltage of 0 [V] (3 [V]) when the control terminal CTL1 is supplied with the voltage of 3 [V] (0 [V]), respectively. Supposing that the voltage V CTL1 of the control terminal CTL1 is higher than the voltage V CTL2 of the control terminal CTL2 (that is, V CTL1 > V CTL2 ), the operation of the biasing circuit portion 2 will be explained at the time of generating the bias voltage therefrom. In this case, the diode D1 is forward-biased and the diode D2 is reverse-biased. As a consequence, the diode D1 is placed in a state of a low impedance Zd (Low) and the diode D2 is placed in a state of a high impedance Zd (High). When the following expression: |Zd (Low)|<<|R4|,|R5|<<|Zd (High)| is satisfied, the equivalent circuit of the biasing circuit portion 2 will be represented as shown in Fig. 2. Thus, a bias terminal V bias corresponding to a connection center point of the diode D1 and the resistor R5 is supplied with a voltage V (High) - V bi which is lower than the voltage V (High) by a junction built-in voltage V bi of the diode. This fact is the same as a case where the voltage V CTL2 of the control terminal CTL2 is higher than the voltage V CTL1 of the control terminal CTL1 (that is, V CTL2 > V CTL1 ). The control terminal CTL1 is connected to the gate terminal of a field effect transistor FET1 through a high-impedance resistor R1, and the bias terminal V bias is connected to the drain and source terminals of the FET1 through high-impedance resistors R2 and R3. The gate terminal is DC-biased by the DC voltage V CTL1 applied to the control terminal CTL1, and the drain and source terminals are also DC-biased by the voltage V (High) - V bi applied to the bias terminal V bias , whereby a high-frequency signal is prevented from being leaked from a signal path. As a consequence, the relative voltage of the gate terminal with respect to the drain terminal (source terminal) becomes V bi when V CTL1 = V (High) and V (Low) - V (High) + V bi when V CTL1 = V (Low). In general, the resistance between the drain and the source of the FET tends to saturate when the bias voltage applied to the gate terminal of the FET becomes almost the built-in voltage. Accordingly, it is preferable to set the ON bias voltage applied to the gate terminal of the FET used as a switch to almost the built-in voltage. This is because, even when a voltage not less than the built-in voltage is tried to be applied to the gate terminal, a leak current flows in the gate terminal to cause the voltage drop by the resistor connected to the gate terminal, and hence a voltage not less than built-in voltage is hardly applied to the gate. Accordingly, even if the FET is controlled by such a large control voltage as described above (in this case, however, the voltage difference between V (Low) and V (High) is required to be not less than the built-in voltage), the relative voltage of the gate terminal in an ON state relative to the drain terminal (source terminal) will be the built-in voltage V bi which is optimum for the FET used as a switch. As described above, since a bias terminal for connecting to an external circuit can be eliminated by providing the biasing circuit portion 2, the package and the chip can be made smaller in size. Further, since a bias line can be eliminated, the leakage of a signal through the bias line can also be eliminated, so that the efficiency of the switching circuit can be improved. Further, the switching circuit 1 can be controlled only by a positive power source. Furthermore, even when the control voltage is changed, the ON bias voltage of the FET used in an IC can be maintained at an optimum value. (3) Matching Circuit Portion The matching circuit portion 3 serves to perform the impedance matching with a transmission system to realize the decrease in the loss by the capacitors C1, C2 arranged to ground the signal path therethrough and the parasitic inductances L1, L2 on the signal path. Fig. 3 shows an equivalent circuit of the matching circuit portion when the switching circuit is in an ON state. In this figure, parasitic inductances such as bonding wires or the like existing at portions of input and output terminals RF1, RF2 for a high-frequency signal are represented by L1, L2, respectively, and the ON resistance of the FET is supposed to be 0 for simplifying the explanation. A capacitance C total1 represents a composite capacitance of the capacitance C1 and a parasitic capacitance C', and a capacitance C total2 represents a composite capacitance of the capacitance C2 and a parasitic capacitance C''. In Fig. 3, supposing that a value of each of the parasitic inductances L1 and L2 is L, a value of each of the composite capacitances C total1 and C total2 is C/2, an angular frequency is ω, and a characteristic impedance of the transmission system is R, an input impedance Z in can be represented by the following expression: Z in = jωL + jωL+R)/jωC (1/jωC+jωL+R) = jω(L-ω 2 L 2 C+L-CR 2 ) (1-ω 2 LC+jωCR) + R Thus, a matching frequency f will be represented by the following expression: f = 1/(2πL)((2L-CR 2 )/C) 0.5 When L is 2 [nH] and C is 1 [pF], for example, the matching frequency f will be 3.1 [GHz] from this expression. Then, a simulation result of the frequency characteristic of the insertion loss will be shown in Fig. 4 in the case where the parasitic inductance L of the switching circuit 1 is 1 [nH] and the value C is changed. This simulation result is an example where a GaAs field junction type FET (JFET) having a gate width of 1 [mm] and a gate length 0.5 [µm] is employed as an FET. It will be clear from this figure that there is a frequency range where the insertion loss is smaller than the case of C = 0 when C = 250 [fF] and 500 [fF]. Accordingly, it will be understood that this effect is due to the matching capacitors. It will be understood from Fig. 4 and the expression of the matching frequency that the insertion loss can be decreased in the frequency range of several [GHz] even when the matching capacitance is 1 [pF] at most. In this case, the parasitic inductance of the bonding wire or the like is several [nH]. When a metal-insulator-metal (MIM) capacitor using a nitride silicon insulation film formed in the usual GaAs FET fabricating process is used as the matching capacitor, the capacitance of about 1 [pF] can be realized by a square capacitor each side being about 100 [µm]. Accordingly, an area of the matching capacitor on a semiconductor chip can be made very small. Further, since very small capacitance is formed on a chip, the insertion loss can be decreased at a desired frequency. (4) Other Embodiments The present invention may be applied to the switching circuit 1 having both the biasing circuit portion 2 and the matching circuit portion 3. While, in the above-described embodiments, the capacitor C1 is connected between the drain terminal of the FET1 and the ground and the capacitor C2 is connected between the source terminal of the FET1 and the ground. However, application of the present invention is not limited thereto but it may be applied to a case where only one capacitor is connected between the ground and one of the drain and source terminals of the FET1. While, in the above-described embodiments, a single gate FET is used as the FET1. However, the present invention is not limited thereto but may be widely applied to a case where a dual gate FET or a multi-gate FET is used as the FET1. While, in the above-described embodiments, a junction type FET is used as the FET1. However, the present invention is not limited thereto but may be applied to a case where a metal semiconductor junction (MES) FET is used as the FET1. While, in the above-described embodiments, the present invention is applied to the basic switching circuit 1. However, the present invention is not limited thereto but may be applied to a composite type switching circuit formed by combining a plurality of the switching circuits 1. For example, as shown in Fig. 5, the present invention may be applied to a composite type switching circuit in which the switching circuit 1 is arranged in series with a signal path and the other switching circuit 1 is arranged between the signal path and the ground. As described above, according to an embodiment of the present invention, the first capacitor is connected between the drain terminal of the field effect transistor and the ground and/or the second capacitor is connected between the source terminal of the field effect transistor and the ground, and the capacitances of the first and/or second capacitances are set in accordance with the signal characteristic. Accordingly, there can be realized a switching circuit which is low in insertion loss at a desired frequency. Further, according to the present invention, since the biasing circuit for generating the bias voltage from the control voltage applied to the two control terminals is provided in addition to the switching circuit using the field effect transistor, the switching circuit can be realized which is able to eliminate a dedicated bias terminal even at the case of using a positive power source and is excellent in isolation property.

Claims: A switching circuit comprising: a field effect transistor (FET1) having a drain and a source, and bias voltage generating means (2), wherein: said bias voltage generating means (2) has first and second control terminals (CTL1, CTL2) to which first and second voltages having different values are alternately applied, for generating a bias voltage on the basis of said first and second voltages applied to said first and second control terminals (CTL1, CTL2), and said bias voltage is applied to said field effect transistor (FET1), characterized in that a path between said drain and said source of said field effect transistor (FET1) serves as a signal path; a high-impedance element (R1) is connected between a gate terminal of said field effect transistor (FET1) and said first control terminal (CTL1), and said switching circuit further includes a second high-impedance element (R2) connected between said drain terminal (D) of said field effect transistor (FET1) and an output terminal of said bias voltage generating means (2) and a third high-impedance element (R3) connected between said source terminal (S) of said field effect transistor (FET1) and said output terminal of said bias voltage generating means (2). The switching circuit according to claim 1, wherein said bias voltage generating means (2) includes: a first diode (D1) connected between said first control terminal (CTL1) and an output terminal of said bias voltage generating means (2) in a manner that first diode (D1) is disposed in a forward direction from said first control terminal (CTL1) toward said output terminal; a first resistor (R4) connected in parallel to said first diode (D1) between said first control terminal (CTL1) and said output terminal; a second diode (D2) connected between said second control terminal (CTL2) and said output terminal in a manner that said second diode is disposed in a forward direction from said second control terminal (CTL2) toward said output terminal; and a second resistor (R5) connected in parallel to said second diode (D2) between said second control terminal (CTL2) and said output terminal. The switching circuit according to claim 1 or 2, wherein said field effect transistor (FET1) is a multigate field effect transistor. The switching circuit according to anyone of claims 1 to 3, wherein said field effect transistor (FET1) is a junction type field effect transistor. The switching circuit according to anyone of claims 1 to 4, further comprising a first capacitor (C1) connected between said drain terminal (D) of said field effect transistor (FET1) and a ground or a second capacitor (C2) connected between said source terminal (S) of said field effect transistor (FET1) and said ground. A composite switching circuit formed by combining a plurality of said switching circuits according to any one of claims 1 to 5.

Inventors: KOHAMA KAZUMASA, KOHAMA, KAZUMASA, KOHAMA, KAZUMASA, C/O SONY CORPORATION
Applicants: SONY CORP, SONY CORPORATION
Application year: 1996
Main classification: H03K17
IPC codes: H04B1, H03K17