A PMOS flash memory cell capable of multi-level threshold voltage storage

Abstract: A P-channel flash EEPROM cell (40) has P+ source (50) and P+ drain (52) regions, and a channel (51) extending therebetween, formed in an N-type well (42). A thin layer of tunnel oxide (62) is provided over the channel (51). A poly-silicon floating gate (56) and poly-silicon control gate (58), separated by a dielectric layer (57), overlie the tunnel oxide (62). Programming is accomplished via hot electron injection while erasing is realized by electron tunneling. The threshold voltage of the cell may be precisely controlled by the magnitude of voltage coupled to the floating gate (56) during programming. Since the injection of hot electrons into the floating gate (56) is independent of variations in the thickness of the tunnel oxide layer (62) and the coupling ratio between the floating gate (56) and the control gate (58), programming operations and data retention are not affected by process variations. In addition, PMOS devices conduct a gate current via hot electron injection over a narrow range of gate voltages, thereby allowing for precise control over the gate current and thus over the charging of the floating gate. This control over the gate current, as well as the independence of the cell's threshold voltage of process parameters, advantageously allows the threshold voltage of the cell to be more accurately controlled, thereby resulting in a more reliable cell capable of storing a greater number of bits of data.

Description: The present invention relates to operating a semiconductor memory cell having an N-type well region having formed therein a P+ source, a P+ drain and a channel region extending between the P+ source and the P+ drain. A conventional EEPROM cell 10 is shown in Figure 1, in which more than two binary states may be represented by programming the threshold voltage of cell 10 to one of many predetermined levels. When cell 10 is read, the current level conducted therein is dependent upon the threshold voltage thereof. Cell 10 includes a storage transistor 12 and a select transistor 14 formed in a P- substrate 16. N+ diffusion region 18 serves as the source of storage transistor 12, N+ diffusion region 20 serves as the drain of storage transistor 12 as well as the source for select transistor 14, and N+ diffusion region 22 serves as the drain of select transistor 14. A bit line BL of an associated memory array (not shown) is coupled to drain 22 of select transistor 14. A high impedance resistor 32 is coupled between drain 22 of select transistor 14 and ground potential. A voltage sensing circuit 34 coupled to drain 22 measures the voltage at drain 22 to determine the threshold voltage V t , and thus the multiple-bit data stored in cell 10. Storage transistor 12 has a floating gate 24 and a control gate 26, and select transistor 14 has a select gate 28. A tunnel window (not shown) is formed within tunnel oxide 30 layer to facilitate electron tunneling between floating gate 24 and drain 20. Floating gate 24 is charged by applying an erase voltage V c between 16 to 20 V to control gate 26 and 16 to 20 volts to select gate 26, while zero volts is applied to bit line BL and source 18. Electrons tunnel from drain 20 to floating gate 24, thereby increasing the threshold voltage V t of storage transistor 12g. Cell 10 may be programmed by applying a program voltage V p between 13 to 20 volts to bit liné BL and select gate 28 while control gate 26 is grounded and source 18 is in a high impedance state. The resultant electric field causes electrons to tunnel from floating gate 24 to drain 20, thereby discharging floating gate 24 and decreasing the threshold voltage V t of cell 10. The resultant V t of storage transistor 12, and thus the current conducted by cell 10 during the read operation, may be controlled by adjusting the program voltage V p . Consequently, more than one bit of information may be stored in cell 10 be altering the threshold voltage V t of cell 10 to one of many possible values. Typically, the threshold voltage of cell 10 is approximately zero volts in its uncharged stated and approximately -2 volts and 4 volts in its fully positive and fully negative charges states, respectively. The range of V t for multi-level applications is approximately 2.5 volts. However, variations in the thickness of the tunneling oxide layer 30, as well as the coupling ration between floating gate 24 and control gate 26, make it difficult to manipulate the threshold voltage V t of storage transistor 12. However, cell 10 suffers from read disturb problems which may adversely affect the reliability of cell 10. Furthermore, the relatively high voltages across the P/N junctions within cell 10 during erasing and programming undesirably limit the extent to which the size of cell 10 may be reduced. While earlier N-channel devices use high programming and erase voltages, such as disclosed in EP 0 618 621, some more recent N-channel devices have been fabricated using lower program and erase voltages, such as disclosed in IEE Electron Device Letters, Volume 14, Number 8 of August 1993 entitled "Improved Floating Gate Devices Using Standard SEMOS Technology" by Montalvo and Paulos. More recently, P-channel memory cells have been manufactured and used where programming and erasing of the cell occur in the enhancement mode, such as the P-channel NVRAM cell disclosed in IBM Technical Disclosure Bulletin volume 35, number 35 of October 1992, pages 339 to 340 and in the P-channel MOS device disclosed in European patent publication 0 255 489. However, given that these types of memory cells are programmed in the enhancement mode, the amount of programming control for the cell, as well as the current available for read operations, are limited. Such limitations can be important considerations, especially when working in a multi-level programming environment. It would thus be desirable for a flash EEPROM cell in which the threshold voltage V t may be controlled independently of process variations. It would be desirable for a flash EEPROM cell that not only uses low programming and erasing voltages but is also immune from read disturb problems. According to an aspect of the present invention, there is provided a method of operating a semiconductor memory cell having an N-type well region (42) having formed therein a P+ source (50), a P+ drain (52), and a channel region (51) extending between said P+ source and said P+ drain; a first insulating layer (62) overlying said well region; a floating gate (56) overlying said first insulating layer; a second insulating layer (57) overlying said floating gate; a control gate (58) overlying said second insulating layer, said cell being programmed, in response to a program voltage applied to said control gate, by hot electron injection from a junction of said N-type well region and said P+ drain into said floating gate, the threshold voltage of said cell being programmable to any one of a plurality of program levels, wherein said threshold voltage is determined by a magnitude of said program voltage; and a select transistor (48) formed in said N-type well region, said select transistor having a P+ drain (54) coupled to a bit line, a P+ source coupled to said P+ drain (52) of said cell, and a bit line select gate (60), said method characterised by programming said cell by applying said program voltage to said control gate (58), applying a first voltage to said P+ source (50) of said cell and to said N-type well region (42) while grounding said bit line and said bit line select gate (60), said program voltage being between 5 and 15 volts depending upon to which of said plurality of program levels it is desired to program said threshold voltage, said first voltage being between approximately 5 and 15 volts. The invention will now be described by way of example only, with reference to the accompanying drawings, of which: Figure 1 is a cross-sectional view of a prior art EEPROM cell which may be programmed and erased to one of many levels of threshold voltage; Figure 2 is a cross-section view of a multi-level threshold voltage cell as used in accordance with the present invention; Figure 3 is a cross-sectional view of the cell of Figure 2 as used in accordance with another embodiment of the present invention; and Figure 4 is a cross-sectional view of the cell of Figure 2 as used in accordance with yet another embodiment of the present invention. A PMOS EEPROM cell 40 is shown in Figure 2 which, as used in accordance with the present invention, is capable of storing numerous bits of binary data. Cell 40 is formed in a N-well 42 provided within a P- substrate 44 and includes a P-channel MOS stacked gate storage transistor 42 and a P-channel MOS select transistor 48. P+ diffusion region 50 serves as the source of storage transistor 46, P+ diffusion region 52 serves as the drain of storage transistor 46 and the source of select transistor 48, and P+ diffusion region 54 serves as the drain of select transistor 48. A bit line BL is coupled to drain 54 of select transistor 48. Storage transistor 46 has a floating gate 56 and a control gate 58, and select transistor 48 has a select gate 60. A layer of tunnel oxide 62 approximately 80-130 Å thick is provided between floating gate 56 and the surface of N-well 42. In one embodiment, oxide layer 62 extends over the entire length of channel 51 and substantial portions of P+ source 50 and P+ drain 52 of storage cell 46. A dielectric layer 57 approximately 180-350 Å thick is provided between floating gate 56 and control gate 58. Note that although shown in the context of CMOS fabrication technology, cell 40 may be fabricated using PMOS technology. To program cell 40, approximately 8 V is applied to P+ source 50 and N- well 42 while bit line BL and select gate 60 are held at ground potential. When a program voltage V p is applied to control gate 58, positively charged holes are attracted to the less positive voltage on P+ drain 52 and accelerate through channel region 51 towards P+ drain 52. These holes collide with electrons in the drain depletion region proximate the drain 52/N-well 42 junction, thereby resulting in impact ionization. The high energy electrons generated from impact ionization are attracted by the positive voltage on control gate 58 and are injected from the depletion region into floating gate 56. The resultant negative charge on floating gate 22 depletes channel region 51 and increases the threshold voltage V t of cell 40 in the positive direction. In its natural state, cell 40 has a threshold voltage V t between approximately -3 and -6 V and when fully charged has a threshold voltage V t of approximately 3 V. During normal operation of cell 40's host chip (not shown), cell 40 may be programmed so as to have a V t between approximately -5 V and +1 V, thereby allowing a range of approximately 6 V for the threshold voltage V t . In one embodiment, the program voltage V p may be between 5-15 V, depending upon the predetermined threshold voltage V t of cell 40. In another embodiment, the program voltage V p may be a ramped voltage from V cc to approximately 15 V. To erase cell 40, an erase voltage V e between 15-22 V is applied to P+ source 50, N- well 42, and select gate 60 while control gate 26 is grounded (bit line BL is floating). Electrons tunnel from floating gate 56 through the entire length of tunneling oxide layer 62 into channel 51, source 50, and drain 52, thereby rendering the threshold voltage V t of storage transistor 46 more negative. Note that cell 40 is capable of page or bulk erasing by the application of appropriate voltages to control gate 58 during erase. Cell 40 may be read in two ways. Using the first option, approximately V cc - 2V is applied to control gate 58, select gate 60 is grounded, and V cc is applied to source 50 and N-well 42. A read voltage V r less than V cc is applied to bit line BL. The current through cell 40 is dependent upon the threshold voltage V t of cell 40 and is thus indicative of the multi-bit data stored within cell 40. This read current is converted to a voltage and measured by voltage sense circuit 34. In a second option, bit line BL and N-well 42 are precharged to V cc and control gate 58, select gate 60, and source 50 are held at ground potential. Select transistor 48 is then turned on and the multi-bit data of cell 40 is detected by voltage sense circuit 34. Acceptable bias condition ranges for erasing, programming, and reading cell 40 are provided below in Table 1. Control Gate Source Bit line Select Gate N-well program 5-15 V or ramped from V cc to 15V 5-15 V 0 V 0 V 5-15 V erase option 1 0 for selected row; 8-10V for unselect row 15-22 V Floating 15-22 V 15-22V erase option 2 0 for selected row; -15 to -3V for unselected row 3-15V Floating 3-15V 3-15V read option 1 0-V cc V cc less than V cc 0 V cc read option 2 0 0 precharge to V cc 0 V cc The resultant V t of storage transistor 46, and thus the current conducted by cell 40 during a subsequent read operation, may by controlled by manipulating the program voltage V p . The injection of hot electrons, as discussed above with respect to charging floating gate 56, is affected only by the voltage applied to control gate 58 and is independent of variations in the thickness of oxide layer 62 and the coupling ratio between floating gate 56 and control gate 58. Further, PMOS devices conduct a gate current via hot electron injection over a narrow range of gate voltages. In this manner, the charging of floating gate 56 may be controlled with great accuracy. Precise control over the gate current, as well as the lack of dependence of cell 40's threshold voltage V t upon process parameters, thus advantageously allows the threshold voltage V t of storage transistor 46 to be more accurately controlled than that of conventional N-channel EEPROM cells such as cell 10 of Figure 1. Taking advantage of the superior control of the threshold voltage V t of storage transistor 46, the threshold voltage V t is accurately programmable in increments of only 5 mV. Since the range of threshold voltage V t for storage transistor 46 is approximately 7 V, the threshold voltage V t cell 10 may programmed to any one of approximately 1400 levels. Thus, cell 40 is capable of accurately storing up to 10 bits of binary data (2 10 = 1024). As described above, the gate current controllability of a P-channel structure and the lack of dependence of hot electron injection upon process variations as discussed above not only allows cell 40 to store more bits of binary data but also does so with increased accuracy. Further, unlike conventional N-channel EEPROM cells, P-channel cell 40 does not require high voltage biases across its P+/N- junctions during programming and erasing. As a result, the size of cell 40 may be reduced to a greater extent than those of N-channel EEPROM cells without incurring destructive junction stress. Note that since whether or not charged floating gate 56 will be of a lower voltage than N-well 42, source 50, and drain 52, inadvertent hot electron injection during reading operations is prevented. In this manner, read disturb problems are eliminated from the operation of cell 40. In another embodiment shown in Figure 3, a source select transistor 72 having a control gate 74 may be added to the structure of Figure 2 to provide a bit-selectable erase cell 70. A P+ diffusion region 76 serves as the source of source select transistor 72, while P+ diffusion region 50 serves as the drain. The programming, erasing, and reading operations of cell 70, the bias conditions for which are listed below in Table 2, are similar to those described above with respect to Figure 2. Note that when programming storage transistor 46 of cell 70, bit line BL is precharged to a voltage the precise value of which is dependent upon the threshold voltage V t of cell 70 after programming, as indicated by the "variable" notation in Table 2. Note that cell 70 may be programmed and erased bit-by-bit. BL BL select gate 60 control gate 58 source select gate 74 source 76 N-well program option 1 variable 0V -15 to -3V 3-15V 3-15V 3-15V program option 2 variable 0V 0V 16-22V 16-22V 16-22V erase option 1 0V 0V 3-12V 0V 5-15V 5-15V erase option 2 0V 0V V cc ramped to 12V 0V 5-15V 5-15V read option 1 less than V cc 0V 0-V cc 0V V cc V cc read option 2 pre-charge to V cc then detect voltage 0V 0V 0V 0V V cc In another embodiment shown in Figure 4, cell 80 includes storage transistor 46 and source select transistor 72, where bit line BL is coupled directly to drain 52 of storage transistor 46. The programming, erasing, and reading operations of cell 80, the bias conditions for which are listed below in Table 3, are similar to those described above with respect to Figure 2. Cell 80 is bit-programmable and may be sector erased. When programming cell 80, the resultant threshold voltage V t and thus the resultant multiple-bit data stored therein depends upon the particular program voltage V p applied to control gate 56. In a first option, for example, option 1, the program voltage V p is ramped from approximately 3 volts to its final value, while in a second option the variable program voltage V p is simply applied to control gate 56. Note that cell 80 may be column or bulk erased. Bit Line BL Control Gate Select Gate Source N-Well program option 1 OV ramped (variable) OV 5-15V 5-15V program option 2 OV variable OV 5-15V 5-15V erase option 1 16-22V for selected column; 8-12V for unselected column OV 16-22V 16-22V 16-22V erase option 2 3-15V for selected column; OV for unselected column -15 to-3V 3-15V 3-15V 3-15V read option 1 pre-charge to V cc OV-V cc OV V cc V cc read option 2 less than V cc OV OV OV V cc

Claims: A method of operating a semiconductor memory cell having an N-type well region (42) having formed therein a P+ source (50), a P+ drain (52), and a channel region (51) extending between said P+ source and said P+ drain; a first insulating layer (62) overlying said well region; a floating gate (56) overlying said first insulating layer; a second insulating layer (57) overlying said floating gate; a control gate (58) overlying said second insulating layer, said cell being programmed, in response to a program voltage applied to said control gate, by hot electron injection from a junction of said N-type well region and said P+ drain into said floating gate, the threshold voltage of said cell being programmable to any one of a plurality of program levels, wherein said threshold voltage is determined by a magnitude of said program voltage; and a select transistor (48) formed in said N-type well region, said select transistor having a P+ drain (54) coupled to a bit line, a P+ source coupled to said P+ drain (52) of said cell, and a bit line select gate (60), said method characterised by programming said cell by applying said program voltage to said control gate (58), applying a first voltage to said P+ source (50) of said cell and to said N-type well region (42) while grounding said bit line and said bit line select gate (60), said program voltage being between 5 and 15 volts depending upon to which of said plurality of program levels it is desired to program said threshold voltage, said first voltage being between approximately 5 and 15 volts. A method of operating a semiconductor memory cell having an N-type well region (42) having formed therein a P+ source (50), a P+ drain (52), and a channel region (51) extending between said P+ source and said P+ drain; a first insulating layer (62) overlying said well region; a floating gate (56) overlying said first insulating layer; a second insulating layer (57) overlying said floating gate; a control gate (58) overlying said second insulating layer, said cell being programmed, in response to a program voltage applied to said control gate, by hot electron injection from a junction of said N-type well region and said P+ drain into said floating gate, the threshold voltage of said cell being programmable to any one of a plurality of program levels, wherein said threshold voltage is determined by a magnitude of said program voltage; and a select transistor (48) formed in said N-type well region, said select transistor having a P+ drain (54) coupled to a bit line, a P+ source coupled to said P+ drain (52) of said cell, and a bit line select gate (60), said method characterised by programming said cell by ramping said program voltage from a first voltage to a second voltage, applying between approximately 5 and 15 volts to said P+ source (50) of said cell and to said N-type well region (42) and applying a third voltage to said bit line select gate (60) while grounding said bit line, wherein said second voltage determines to which of said plurality of program levels said threshold voltage is to be programmed. The method of Claim 2 wherein said first voltage is approximately 5 volts and said second voltage is approximately 15 volts. A method of operating a semiconductor memory cell having an N-type well region (42) having formed therein a P+ source (50), a P+ drain (52), and a channel region (51) extending between said P+ source and said P+ drain; a first insulating layer (62) overlying said well region; a floating gate (56) overlying said first insulating layer; a second insulating layer (57) overlying said floating gate; a control gate (58) overlying said second insulating layer, said cell being programmed, in response to a program voltage applied to said control gate, by hot electron injection from a junction of said N-type well region and said P+ drain into said floating gate, the threshold voltage of said cell being programmable to any one of a plurality of program levels, wherein said threshold voltage is determined by a magnitude of said program voltage; and a select transistor (48) formed in said N-type well region, said select transistor having a P+ drain (54) coupled to a bit line, a P+ source coupled to said P+ drain (52) of said cell, and a bit line select gate (60), said method characterised by erasing said cell by applying between approximately 15 and 22 volts to said P+ source (50) of said cell, to said bit line select gate (60), and to said N-type well region (42), while grounding said control gate (58) and coupling said bit line to a floating potential. A method of operating a semiconductor memory cell having an N-type well region (42) having formed therein a P+ source (50), a P+ drain (52), and a channel region (51) extending between said P+ source and said P+ drain: a first insulating layer (62) overlying said well region; a floating gate (56) overlying said first insulating layer; a second insulating layer (57) overlying said floating gate; a control gate (58) overlying said second insulating layer, said cell being programmed, in response to a program voltage applied to said control gate, by hot electron injection from a junction of said N-type well region and said P+ drain into said floating gate, the threshold voltage of said cell being programmable to any one of a plurality of program levels, wherein said threshold voltage is determined by a magnitude of said program voltage; and a select transistor (48) formed in said N-type well region, said select transistor having a P+ drain (54) coupled to a bit line, a P+ source coupled to said P+ drain (52) of said cell, and a bit line select gate (60), said method characterised by erasing said cell by applying between approximately 3 and 15 volts to said P+ source (50) of said cell, to said bit line select gate (60), and to said N-type well region (42), while applying between approximately -3 and -15 volts to said control gate (58) and coupling said bit line to a floating potential. The method of Claim 1 wherein said cell further comprises a second select transistor (72) formed in said N-type well region (42) and having a P+ drain coupled to said P+ source (50) of said cell and having a source select gate (74) and a P+ source (76) and modified by the fact that said cell is programmed by applying approximately -15 to -3 volts to said control gate (58), applying between approximately 3 and 15 volts to said source select gate (74), to said P+ source (76) of said second select transistor (72), and to said N-type well region (42) while grounding said bit line select gate (60) and applying a second voltage to said bit line. The method of Claim 6, modified by the fact that said cell is programmed by applying between approximately 16 to 22 volts to said source select gate (74), to said P+ source (76) of said second select transistor, and to said N-type well region (42) while grounding said bit line select gate (60) and said control gate (58) and applying a second voltage to said bit line. The method of Claim 4, wherein said cell further comprises a second select transistor (72) formed in said N-type well region (42) and having a P+ drain coupled to said P+ source (50) of said cell and having a source select gate (74) and a P+ source (76) and modified by the fact that said cell is erased by applying between approximately 5 to 15 volts to said P+ source (76) of said second transistor and to said N-type well region (42), applying approximately 3 to 12 volts to said control gate (58), and grounding said bit line, said source select gate (74), and said bit line select gate (60). The method of claim 8, modified by the fact that, instead of applying approximately 3 to 12 volts to said control gate (58), applying a ramping voltage from the supply voltage to 12 volts to said control gate (58).

Inventors: CHANG SHANG-DE T, CHANG, SHANG-DE T.
Applicants: PROGRAMMABLE MICROELECTRONICS, PROGRAMMABLE MICROELECTRONICS CORPORATION
Application year: 1996
Main classification: H01L29
IPC codes: G11C16, H01L21, G11C11, H01L29, H01L27, G11C17