Input interface using multiplex type input circuit

Abstract: An input interface (50) using a multiplex type input circuit (10) for selecting a desired one, as its output, of a plurality of input power signals (20) in accordance with a control signal generated by a CPU (30) and for supplying the selected input power signal to an electronic element unit (40).

Description: The present invention relates to an input interface using a multiplex type input circuit according to claim 1. Conventionally, for example, that which is illustrated in Fig. 9 is known as an input interfaces of this type. That is, as shown in the diagrams (a) to (c) of Fig. 9, individual input interfaces are provided for switching elements (an ON switch in the diagram (a) of Fig. 9 and an ON-ON switch in the diagram (b) of Fig. 9) and a variable resistance element (a potentiometer in the diagram (c) of Fig. 9), respectively. In the ON switch, a charge voltage generated by a charge current flowing into a capacitor from a power supply (Vbat) through a resistor is measured at a first input port of a CPU to thereby detect the closed state of the ON switch. Also in the ON-ON switch, respective charge currents of capacitors are measured at a second and third input ports of the CPU in the same manner as in the ON switch to thereby detect which one of terminal a and terminal b in the ON-ON switch is closed. In the potentiometer, a charge current of a capacitor based on a partial potential generated by the proportion between a resistor connected to a power supply (5 V) and the potentiometer is measured at an A/D port to thereby measure the resistance value of the potentiometer. Further, information of the respective addresses of the first, second, third and A/D ports is stored in the memory of the CPU. In such a conventional input interface, however, individual input interfaces are provided for switching elements and a variable resistance element, respectively. There arises a problem that the scale of the circuit becomes large and therefore the cost increases correspondingly. Furthermore, information of the respective addresses of the first, second, third and A/D ports is stored in the memory of the CPU. Accordingly, there arises a problem that the memory requires a large capacity. From US-A-5,376,834 a circuit is known for automatically establishing a reference output value for an analogue circuit. For this purpose, it is described to use a multiplexer which provides a plurality of voltages. The output of the multiplexer is controlled by a control signal which is derived from the analogue output of the analogue circuit in relation to a reference voltage. In US-A-4,810,948 a multiplexer in a constant-voltage regulated power supply circuit is described, wherein each input of the multiplexer is connected to a tap point of a divider network and one of the tap points is selected by the multiplexer as an output to a comparator input. An address input of the multiplexer is supplied from a microcomputer. It is the object of the invention to provide a common input interface for various kinds of electronic element units for simplifying the configuration and reducing the costs of a corresponding circuit. This object is achieved by the features of claim 1. A multiplex type input circuit provided in an input interface according to the present invention can select, as its output, a desired one of a plurality of input power signals so as to supply the selected input power signal to an electronic element unit. The electronic element unit performs predetermined electric conversion on the input power signal supplied thereto so that the input power signal thus subjected to the electric conversion can be supplied as a switching output to a CPU. That is, a switching element which is a kind of the electronic element unit performs ON/OFF electric conversion, as the predetermined electric conversion, on the supplied input power signal so that the input power signal thus subjected to the electric conversion can be supplied, as a switching output, to the CPU (specifically, to a first input port or a second input port). Further, a variable resistance element which is a kind of the electronic element unit performs electric potential division of the supplied input power signal, as the predetermined electric conversion, so that the input power signal thus subjected to the electric potential division can be outputted as a switching output to be supplied to the CPU 30 (specifically, to an A/D port). That is, because the input interface can be attained to be common to various kinds of electronic element units such as the switching element, the variable resistance element, and so on, the input interface can be simplified in configuration and reduced in cost. Furthermore, because the number of input ports used can be reduced and the capacity of memory for storing information of the addresses of the ports can be reduced by sharing the input ports, the input interface can be simplified in configuration and reduced in cost. The operation of the multiplex type input circuit according to the present invention will be described more in detail. The input power signal is supplied to the collector of the first transistor Q1. When a signal for turning on the second transistor Q2 is supplied from the output port of the CPU, the first transistor is turned on by a bias voltage generated by the second transistor Q2 in ON-state. As a result, the input power signal can be supplied to the electronic element unit. The electronic element unit performs predetermined electric conversion on the supplied input power signal, so that the input power signal thus subjected to the electric conversion can be outputted as a switching output to be supplied to the CPU. As described above, in the input interface using the multiplex type input circuit according to the present invention, the input interface can be attained to be common to various kinds of electronic element units such as the switching element, the variable resistance element, and so on. Accordingly, the input interface can be simplified in configuration and therefore reduced in cost. Furthermore, because the number of input ports used can be reduced and the capacity of memory for storing information of the addresses of the ports can be reduced by sharing the input ports, the input interface can be simplified in configuration and reduced in cost. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a functional block diagram showing an input interface using a multiplex type input circuit according to an embodiment of the present invention. Fig. 2 is a diagram of arrangement of the input interface using the multiplex type input circuit according to the embodiment of the present invention. Fig. 3 is a circuit diagram of the input interface using the multiplex type input circuit according to the embodiment of the present invention. Figs. 4 (a) to (c) are circuit diagrams of various electronic element units according to the embodiment of the present invention. Figs. 5 (a) and (b) are circuit diagrams of the input interface using the multiplex type input circuit according to the embodiment of the present invention in the case where an output port is turned on by using an ON switch. Figs. 6 (a) and (b) are circuit diagrams of the input interface using the multiplex type input circuit according to the embodiment of the present invention in the case where an output port is turned on by using an ON-ON switch. Figs. 7 (a) and (b) are circuit diagrams of the input interface using the multiplex type input circuit according to the embodiment of the present invention in the case where an output port is turned off by using a volume switch. Fig. 8 is a flow chart of the input interface using the multiplex type input circuit according to the embodiment of the present invention. Fig. 9 is a functional block diagram for explaining conventional input interfaces. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. Fig. 1 is a functional block diagram showing an input interface 50 using a multiplex type input circuit 10 according to an embodiment of the present invention; Fig. 2 is a diagram of arrangement of the input interface 50 using the multiplex type input circuit 10 according to the embodiment of the present invention; Fig. 3 is a circuit diagram of the input interface 50 using the multiplex type input circuit 10 according to the embodiment of the present invention; and Fig. 4 is a circuit diagram of various electronic element units 40 according to the embodiment of the present invention. As shown in Fig. 1, the input interface 50 in this embodiment has a multiplex type input circuit 10 for selecting, as its output, a desired one 20a of input power signals 20a generated respectively by a plurality of power supplies 20, .., 20 as signal sources, in accordance with a control signal 30a. In this embodiment, the power supplies 20, ..., 20 are a first power supply 20b (Va) and a second power supply 20c (Vb) which are stabilized DC power supplies. Further, as shown in Figs. 1 and 2, the multiplex type input circuit 10 in this embodiment is connected both to a CPU 30 and to an electronic element unit 40 so that a desired one 10a of a plurality of input power signals 20a is selected, as its output, in accordance with a control signal 30a generated by the CPU 30, and the selected input power signal 10a is supplied to the electronic element unit 40. A specific example of the multiplex type input circuit 10 in this embodiment shown in Figs. 1 and 2 is a circuit surrounded by the broken line in Fig. 3. The specific example of the multiplex type input circuit 10 includes a first transistor (Q1) 12, and a second transistor (Q2) 14. The first transistor (Q1) 12 has an emitter 12a connected to the power supplies 20, ..., 20, a collector 12c connected to an electronic element unit 40 to supply input power signals 20a to the latter, and a base 12b connected to a collector 14c of the second transistor (Q2) 14. The emitter 12a and the base 12b are connected to each other. The second transistor (Q2) 14 has an emitter 14a connected to the ground, a base 14b connected to the CPU 30 through a resistor, and a collector 14c connected to the base 12b of the first transistor (Q1) 12. As shown in Figs. 1 and 2, the CPU 30 is connected to the multiplex type input circuit 10 so as to supply a control signal 30a to the multiplex type input circuit 10, and so as to accelerate the selection of a desired input power signal 10a, as its output, of the plurality of input power signals 20a. As shown in Fig. 1, the electronic element unit 40 is connected to the multiplex type input circuit 10 and the CPU 30 so that the supplied input power signal 10a is subjected to predetermined electric conversion, and the input power signal 10a thus subjected to electric conversion can be outputted as a switching output 40c to be supplied to the CPU 30. Specifically, as shown in Fig. 2, a switching element 40a which is a kind of the electronic element unit 40 is connected to the multiplex type input circuit 10 and the CPU 30 so that ON/OFF electric conversion is performed as the predetermined electric conversion, on the supplied input power signal 10a, and the input power signal 10a thus subjected to the electric conversion can be outputted as a switching output 40c to supplied to the CPU 30. As shown in the diagrams (a) and (b) of Fig. 4, examples of the switching element 40a in this embodiment include an ON switch 40a-1, an ON-ON switch 40a-2, etc. Similarly, a variable resistance element 40b which is a kind of the electronic element unit 40 is connected to the multiplex type input circuit 10 and the CPU 30 so that electric potential division of the supplied input power signal 10a is performed as the predetermined electric conversion, and the input power signal 10a thus subjected to the electric potential division can be outputted as a switching output 40c to be supplied to the CPU 30. As shown in the diagram (c) of Fig. 4, examples of the variable resistance element 40b in this embodiment include a potentiometer, etc. The operation of this embodiment will be described below. Fig. 5 is a circuit diagram of the input interface 50 using the multiplex type input circuit 10 according to the embodiment of the present invention in the case where the output port 32a is turned on by using the ON switch 40a-1; Fig. 6 is a circuit diagram of the input interface 50 using the multiplex type input circuit 10 according to the embodiment of the present invention in the case where the output port 32a is turned on by using the ON-ON switch 40a-2; and Fig. 7 is a circuit diagram of the input interface 50 using the multiplex type input circuit 10 according to the embodiment of the present invention in the case where the output port 32a is turned off by using a volume switch 40b. Fig. 8 is a flow chart of the input interface 50 using the multiplex type input circuit 10 according to the embodiment of the present invention. Referring first to Fig. 4, the operation of the electronic element unit 40 in the embodiment will be described. In this embodiment, the ON switch 40a-1, the ON-ON switch 40a-2 and the potentiometer 40b are used as the electronic element unit 40. In this embodiment, the input power signal 10a is a DC voltage supplied from either one of the first and second power supplies 20b (Va) and 20c (Vb) which are stabilized DC power supplies. The voltage of the first power supply 20b (Va) or the voltage of the second power supply 20c (Vb) is determined on the basis of the switching characteristic of the electronic element unit 40 connected and the input/output condition of the CPU 30. Particularly in this embodiment, the voltage of the first power supply 20b (Va) is set to be DC 5 V taking into account the A/D conversion input condition of the CPU 30, whereas the voltage of the second power supply 20c (Vb) is set to be DC 24 V taking into account the switching characteristics of the ON switch 40a-1 and the switching characteristic of the ON-ON switch 40a-2. As shown in the diagram (a) of Fig. 4, the ON switch 40a-1 performs predetermined electric conversion on the supplied input power signal 10a (that is, Va or Vb) (in a closed state or in an opened state), so that the input power signal 10a thus subjected to the electric conversion can be outputted as a switching output 40c to be supplied to the CPU 30. As shown in the diagram (b) of Fig. 4, the ON-ON switch 40a-2 performs predetermined electric conversion on the supplied input power signal 10a (that is, Va or Vb) (in a closed state or in an opened state), so that the input power signal 10a thus subjected to the electric conversion can be outputted as a switching output 40c (that is, a signal indicating which one of terminals a and b is in a closed/opened state) to be supplied to the CPU 30. That is, the switching element 40a which is a kind of the electronic element unit 40 performs ON/OFF electric conversion on the supplied input power signal 10a as predetermined electric conversion, so that the input power signal 10a thus subjected to the electric conversion can be outputted as a switching output 40c to be supplied to the CPU 30 (specifically, to the first and second input ports 32b and 32c). As shown in the diagram (c) of Fig. 4, the potentiometer 40b performs predetermined electric conversion (that is, potential dividing conversion, for example, conversion into a desired voltage value in a range of from 0 V to Va (5 V)) on the supplied input power signal 10a, so that the input power signal 10a thus subjected to the electric conversion can be outputted as a switching output 40c (for example, a desired voltage value in a range of from 0 V to Va (5 V)) to be supplied to the CPU 30. That is, the variable resistance element 40b which is a kind of the electronic element unit 40 performs electric potential division on the supplied input power signal 10a as predetermined electric conversion, so that the input power signal 10a thus subjected to the electric potential division can be outputted as a switching output 40c to be supplied to the CPU 30 (specifically, to the A/D port 32d). Referring next to Fig. 8, the operation of the input interface 50 using the multiplex type input circuit 10 according to the embodiment of the present invention will be described. The CPU 30 provided in the input interface 50 in this embodiment identifies the kind of the electronic element unit 40 in order to select a desired input power signal 10a, as the output of the multiplex type input circuit 10, of the plurality of input power signals 20a (in this embodiment, the DC voltage supplied from the first power supply 20b (Va) and the DC voltage supplied from the second power supply 20c (Vb)) (step S1). In the case where the ON switch 40a-1 is connected, the selected input power signal 10a can be supplied to the electronic element unit 40 (that is, the ON switch 40a-1) by supplying an ON signal (in this embodiment, a high-level signal) to the output port 32a (stop S2). Succeedingly, the input power signal 10a is inputted from the first input port 32b (step S3) and then the situation of the routine goes back to the step S1. In the case where the ON-ON switch 40a-2 is connected, the selected input power signal 10a can be supplied to the electronic element unit 40 (that is, the ON-ON switch 40a-2) by supplying an ON signal (in this embodiment, a high-level signal) to the output port 32a (step S4). Succeedingly, the input power signal 10a is inputted from the first or second input port 32b or 32c (step S3) and then the situation of the routine goes back to the step S1. In the case where the potentiometer 40b is connected, the selected input power signal 10a can be supplied to the electronic element unit 40 (that is, the potentiometer 40b) by supplying an OFF signal (in this embodiment, a low-level signal) to the output port 32a (step S6). Succeedingly, the input power signal 10a (for example, a desired partial potential in a range of from DC 0 V to DC 5 V) is inputted from the A/D port 32d (step S7) and then the situation of the routine goes back to the step S1. That is, because the input interface 50 can be attained to be common to various kinds of electronic element units 40 such as a switching element 40a, a variable resistance element 40b, and so on, the input interface 50 can be simplified in configuration and reduced in cost. Furthermore, because the number of input ports used can be reduced and the capacity of memory for storing information of the addresses of the ports can be reduced by sharing the input ports 32b, 32c and 32d, the input interface 50 can be simplified in configuration and reduced in cost. Referring next to Figs. 5 through 7, the operation of the multiplex type input circuit 10 of the input interface 50 in this embodiment will be described more in detail. Fig. 5 is a circuit diagram of the input interface 50 using the multiplex type input circuit 10 according to the embodiment of the present invention in the case where the output port 32a is turned on by using the ON switch 40a-1. The CPU 30 supplies a control signal 32a (ON) (in this embodiment, a signal for turning on a transistor) to the output port 32a. When the output port 32a is turned on, the second power supply (Vb) 20c is selected so that the input power signal 20a is supplied to the collector 12c of the first transistor (Q1) 12 as shown in the diagram (a) of Fig. 5. When a signal for turning on the second transistor (Q2) 14 is given from the output port 32a of the CPU 30, the first transistor 12 is turned on by a bias voltage generated by the second transistor (Q2) 14 in ON-state. As a result, the input power signal 10a (in this embodiment, the DC voltage of the second power supply 20c) can be supplied to the electronic element unit 40 (in this embodiment, the ON switch 40a-1). As shown in the diagram (b) of Fig. 5, the electronic element unit 40 (in this embodiment, the ON switch 40a-1) performs predetermined electric conversion (opening/closing) on the supplied input power signal 10a (in this embodiment, the DC voltage of the second power supply 20c), so that the input power signal 10a (in this embodiment, 0 (ground potential) or Vb (the DC voltage value of the second power supply 20c)) thus subjected to the electric conversion can be outputted as a switching output 40c to be supplied to the CPU 30. Fig. 6 is a circuit diagram of the input interface 50 using the multiplex type input circuit 10 according to the embodiment of the present invention in the case where the output port 32a is turned on by using the ON-ON switch 40a-2. The CPU 30 supplies a control signal 32a (ON) (in this embodiment, a signal for turning on a transistor) to the output port 32a. When the output port 32a is turned on, the second power supply (Vb) 20c is selected so that the input power signal 20a is supplied to the collector 12c of the first transistor (Q1) 12 as shown in the diagram (a) of Fig. 6. When a signal for turning on the second transistor (Q2) 14 is given from the output port 32a of the CPU 30, the first transistor 12 is turned on by a bias voltage generated by the second transistor (Q2) 14 in ON-state. As a result, the input power signal 10a (in this embodiment, the DC voltage of the second power supply 20c) can be supplied to the electronic element unit 40 (in this embodiment, the ON-ON switch 40a-2). As shown in the diagram (b) of Fig. 6, the electronic element unit 40 (in this embodiment, the ON-ON switch 40a-2) performs predetermined electric conversion (opening/closing) on the supplied input power signal 10a (in this embodiment, the DC voltage of the second power supply 20c), so that the input power signal 10a thus subjected to the electric conversion can be outputted as a switching output 40c (that is, a signal indicating which one of the terminals a and b is in an opened/closed state) to be supplied to the CPU 30. Next, Fig. 7 is a circuit diagram of the input interface 50 using the multiplex type input circuit 10 according to the embodiment of the present invention in the case where the output port 32a is turned off by using the volume switch 40b. The CPU 30 supplies a control signal 32a (OFF) (in this embodiment, a signal for turning off a transistor) to the output port 32a. When the output port 32a is turned off, both the first transistor (Q1) 12 and the second transistor (Q2) 14 are turned off so that the first power supply (Vb) 20b is selected as shown in the diagram (a) of Fig. 7. When both the first transistor (Q1) 12 and the second transistor (Q2) 14 are turned off so that the first power supply (Va=DC 5 V) 20b is selected, the input power signal 10a (in this embodiment, the DC voltage of the first power supply 20b) can be supplied to the electronic element unit 40 (in this embodiment, the potentiometer 40b). As shown in the diagram (b) of Fig. 7, the electronic element unit 40 (in this embodiment, the potentiometer 40b) performs predetermined electric conversion (that is, potential dividing conversion, for example, into a desired voltage value in a range of from 0 V to Va (5 V)), on the supplied input power signal 10a, so that the input power signal 10a (in this embodiment, the DC voltage value of the first power supply 20b) thus subjected to the electric conversion can be outputted as a switching output 40c (for example, a desired partial potential in a range of from 0 V to Va (5 V)) to be supplied to the CPU 30. As described above, in the input interface 50 using the multiplex type input circuit 10 according to this embodiment, the input interface 50 can be attained to be common to various kinds of electronic element units 40 such as the switching element 40a, the variable resistance element 40b, and so on. Accordingly, the input interface 50 can be simplified in configuration and reduced in cost. Furthermore, because the number of input ports used can be reduced and the capacity of memory for storing information of the addresses of the ports can be reduced by sharing the input ports 32b, 32c and 32d, the input interface 50 can be simplified in configuration and reduced in cost. In the input interface using the multiplex type input circuit according to the present invention, because the input interface is provided with the multiplex type input circuit for selecting, as its output, a desired one of a plurality of input power signals in accordance with a control signal generated by a CPU and for supplying the thus selected input power signal to an electronic element unit, the input interface can be attained to be common to various kinds of electronic element units such as a switching element, a variable resistance element, and so on. Accordingly, the input interface can be simplified in configuration and reduced in cost. Furthermore, because the number of input ports used can be reduced and the capacity of memory for storing information of the addresses of the A/D ports can be reduced by sharing the input ports, the input interface can be simplified in configuration and reduced in cost.

Claims: An input interface (50) for use with one of various kinds of electronic element unit (40) comprising a multiplex type input circuit (10) for selecting, as its output (10a), a desired one from a plurality of input power signals (20a) in accordance with a control signal (30a), wherein said electronic element unit (40) performs a predetermined electric conversion on said supplied input power signal and supplies the input power signal subjected to the electric conversion as an output signal (40c) to a CPU (30); and said control signal (30a) which is provided from said CPU selects said desired input power signal (20a) depending on the output signal from the electronic element unit (40). An input interface according to claim 1 characterised in that said electronic element unit (40) is a switching element (40a) or a variable resistance element (40b), wherein said switching element performs ON/OFF electric conversion on said supplied input power signal (10a) as said predetermined electronic conversion, and supplies the output power signal subjected to the electric conversion as a switching input signal (40c) to said CPU (30) and said variable resistance element (40b) performs electric potential division on said supplied input power signal as said predetermined electric conversion and supplies the input power signal subjected to the electric potential division as a switching output signal (40c) to said CPU (30). An input interface according to claim 1 or 2 characterised in that said multiplex type input circuit (10) includes a first transistor (Q1) and a second transistor (Q2), said first transistor (Q1) has an emitter connected to said power supplies (20), a collector connected to said electronic element unit (40) to supply said input power signal (10a) to said electronic element unit (40), and a base connected to a collector of said second transistor (Q2), said emitter and base of said first transistor being connected to each other and said second transistor has an emitter connected to the ground, a base connected to said CPU through a resistor, and said collector connected to said base of said first transistor (Q1).

Inventors: IMAIZUMI NOBUHIRO, RYU KAZUNORI, IMAIZUMI, NOBUHIRO, RYU, KAZUNORI
Applicants: YAZAKI CORP, YAZAKI CORPORATION
Application year: 1996
Main classification: G05F1
IPC codes: H03K17, G05F1