DISCHARGE LAMP BALLAST

Abstract: A gas discharge lamp dimming ballast has a two wire input for connection to the hot dimmed and neutral leads of a phase control dimmer. The ballast has an improved topology in which a pre-conditioner supplies a substantially constant DC voltage to a ballast stage including an inverter. A dimming interface circuit derives a dimming signal having a voltage equal to the average value of the rectified output voltage of the phase control dimmer. The gas discharge dimming ballast allows easy installation and dimming over a wide range making use of the phase control dimmer.

Description: Discharge lamp ballast. The invention relates to a discharge lamp ballast for use with a phase angle dimmer, said discharge lamp ballast comprising: - a pair of mains input terminals for receiving a phase angle controlled AC mains voltage; - ballasting means for providing electrical power to a discharge lamp, said ballasting means including (i) a DC input at which a substantially constant DC voltage is received, (ii) a dim input separate from said DC input for receiving a dimming signal and (iii) first control means for controlling the electrical power supplied to the discharge lamp at a level corresponding to a characteristic of the dimming signal; - power supply means connected to said mains input terminals for supplying the substantially constant DC voltage to said DC input of said ballasting means; and - dim signal deriving means for deriving the dimming signal from the phase angle controlled AC mains voltage and for supplying the dimming signal to said dim input of said ballasting means. Such a discharge lamp ballast (further also referred to as ballast) is known from USP 5, 101 , 142. During lamp operation the ballasting means of the known ballast generate a high frequency lamp current. The amount of power consumed by the discharge lamp is controlled at a level corresponding to a characteristic of the dimming signal. This dimming signal in turn is derived from the phase angle controlled AC mains voltage by the dim signal deriving means. The known ballast also receives power from said phase angle controlled AC mains voltage. For these reasons the known ballast only needs to be connected via said pair of mains input terminals to the output terminals of a phase angle dimmer supplying said phase angle controlled AC mains voltage that both functions as a supply voltage and as a signal from which the dimming signal is derived. As a consequence the installation of the known ballast is relatively simple on the one hand while on the other hand it is possible to control the light output of a discharge lamp operated by the known ballast making use of a phase angle dimmer, that is otherwise only suited for dimming incandescent lamps. An important disadvantage of the known ballast, however, is that, in case the conduction angle of the phase angle controlled AC mains voltage is changed by means of the phase angle dimmer, not only the dimming signal but also the substantially constant DC voltage changes. The effective dimming range is therefore limited at low conduction angles by reason of the DC voltage at the DC input dropping to low levels. Since the compliance voltage (i.e. the voltage needed to keep the lamp lit) increases with increased dimming, the lowering of the DC voltage at low conduction angles renders it impossible for the ballasting means to maintain the compliance voltage. Thus, at low conduction angles the discharge lamp will tend to extinguish. It is an object of the present invention to provide a discharge lamp ballast that is easy to install and allows control of the light output of a discharge lamp operated by the ballast over a relatively wide range making use of a phase angle dimmer. A ballast as described in the opening paragraph is therefore according to the invention characterized in that said power supply means comprises feedback means for maintaining said DC-voltage at a substantially constant level independent of the conduction angle of the phase angle controlled AC mains voltage. Since the amplitude of the DC-voltage present at the DC input remains substantially unchanged the ballasting means can maintain the compliance voltage over a relatively wide range of the conduction angle of the phase angle controlled AC mains voltage. As a consequence the ballast according to the invention allows the light output of a discharge lamp operated by this ballast to be controlled over a relatively wide range. It was found that a ballast according to the invention can be realized in a relatively simple and dependable way in case the characteristic of the dim signal is the dim signal voltage. Preferably the ballast further comprises rectifier means connected to said mains input terminals for providing a full-wave rectified DC output voltage to said power supply means and said dim signal deriving means, and wherein said dim signal deriving means is equipped with filter means for generating a dimming signal that is substantially proportional to the average value of the rectified DC voltage from said rectifier means. It has been found that such a ballast functions smoothly and dependably both in case the said filter means comprises a two-pole filter as well as in case the said filter comprises a three pole filter. Preferably the ballast includes further filter means for suppressing high frequency harmonics entering the mains supply, said further filter means including a filter capacitor coupled to an output of said rectifier means and charged by said rectified output voltage and wherein said power supply means include (i) a controllable switching means switchable between a conductive and a non-conductive switching state and providing a discharge path for said filter capacitor, and (ii) control means for controlling the switching state of said switching means, said control means switching said switching state of said switching means at frequencies substantially higher than said mains frequency to control the DC supply voltage, and wherein said control means of said power supply means includes means for maintaining said high frequency switching of said switching means so as to discharge said filter capacitor when said phase controlled rectified output voltage is at or near zero. Because the filter capacitor is rapidly discharged when the phase controlled rectified output voltage is at or near zero, the shape of the voltage that is present over this filter capacitor is substantially identical to the rectified phase angle controlled AC mains voltage. The filter means comprised in the dim signal deriving means is coupled to the filter capacitor and can relatively easily derive from the voltage over the filter capacitor a signal that is substantially proportional to the average value of the rectified DC voltage from said rectifier means. For this reason the filter means comprised in the dim signal deriving means can be realized in a relatively simple way. It has been found that power imbalances during the adjustment of the light output level of the discharge lamp operated on the ballast according to the invention can be largely suppressed in case the ballast is so dimensioned that the characteristic response time of the first control means is substantially shorter than the characteristic response time of said feedback means and that the characteristic response time of said means for deriving said dimming signal has a characteristic response time that is shorter than the characteristic response time of said feedback means and longer than the characteristic response time of said first control means. The characteristic response time of a circuit is meant to be the time it takes for its output to reach 90% of its final value due to a changed input. It has also been found that the crest factor of the lamp current of a discharge lamp operated on a ballast according to the invention can be maintained at a relatively low level in case said dim signal deriving means comprises means for suppressing the ripple, present in the dim signal at twice the frequency of the phase angle controlled AC mains voltage. These means are preferably realized by means of an electronic filter that attenuates said ripple. Embodiments of the invention will be further explained with reference to a drawing. In the drawing, Figure 1 is a block diagram of the ballast according to the invention; Figure 2-3 show part of the circuitry of the ballast of Fig. 1 in more detail, and Figure 5 shows a phase angle dimmer. The fluorescent lamp controller shown in Figure 1 includes a filter "A" connected to fiill bridge input rectifier "B", which together convert an AC power line voltage into a rectified, filtered DC voltage at an output thereof. The pre-conditioner circuit "C" includes circuitry for active power factor correction, as well as for increasing and controlling the DC voltage from the rectifier circuit B, which DC voltage is provided across a pair of DC rails RL1 , RL2. Circuit "D" is a ballasting means for controlling operation of the lamp and includes a DC-AC converter or inverter, "E", a resonant tank output circuit "F" , and a controller "G" which controls the inverter. A lamp La is connected to an output of resonant tank output circuit F. The inverter E is a half-bridge configuration which under control of the half-bridge controller, or driver, circuit G provides a high frequency substantially square wave output voltage to the output circuit F. The resonant tank output circuit F converts the substantially square wave output of the half-bridge into a sinusoidal lamp current. The safety circuit "H" provides a back-up stop function which prevents an output voltage from being present at the lamp terminals when one or both of the fluorescent lamps has failed or has been removed from its socket. The safety circuit also restarts the controller G when its senses that both filament electrodes in each lamp are good. A dimming interface circuit "I" is coupled to an output of the rectifier circuit B and connected to a dim input of the ballast circuit present at the controller G to control dimming of the lamp. The dimming interface circuitry provides a dimming voltage signal to the controller G which is proportional to the setting of the phase angle dimmer. Filter Circuit A (Fig. 2) includes a pair of input terminals l',2' for receiving an ordinary alternating current power line voltage, for example, of 120 volts AC. First and second choke coils L1,L2 each have a first end connected to a respective terminal l ',2' and a second end connected to a respective input node 12, 17 of the full bridge rectifier B, consisting of diodes D1-D4, via input lines 1,2. A fuse Fl is in series between the choke coil LI and input terminal 1'. A transient-surge-suppressing metal oxide varistor VI bridges the lines 1,2. The varistor conducts little at line voltage but conducts readily at higher voltages to protect the ballast from high transient surge voltages. The rectifier provides a full wave rectified output voltage on a pair of DC rails RLl, RL2 via nodes 13, 18, respectively. The cathode of diode D2 and the anode of diode Dl are connected to line 2 at node 17 and the cathode of diode D4 and the anode of diode D3 are connected to line 1 at node 12. The anodes of diodes D2 and D4 are connected to DC rail RL2 at node 18 and the cathodes of diodes Dl and D3 are connected to the DC rail RLl at node 13. For a 120 V, 60 Hz AC input at terminals l ',2' the bridge rectifier outputs a pulsed 120 Hz DC, 170 V peak across rails RLl , RL2. The output of the bridge rectifier also carries phase control information from an external phase control dimmer, to be further discussed. Series capacitors Cl and C2, having their midpoint connected to ground, each have a relatively small capacitance and form a common mode filter which prevents very high frequency components from the ballast from entering the power line. The chokes LI, L2 and the capacitors C3, C4 form an EMI filter which has a low impedance at line frequencies and a high impedance at the much higher ballast operating frequency to reduce conduction of EMI back into the power lines. The operation of the EMI filter will be discussed in greater detail along with the interface and pre-conditioner circuits. The pre-conditioner circuit C (Fig. 2) includes the primary components of an integrated circuit ("IC") control chip Ul, in this instance a Linfinity LX1563, a boost inductor in the form of a transformer Tl, a storage capacitor CIO and a boost switch Ql , which together form a switched mode power supply ("SMPS"). The controller Ul controls the switching of switch Ql to (i) control the power factor of the current drawn from the power lines and (ii) to control and increase the DC voltage across the capacitor CIO, and rails RLl , RL2, to about 300 V DC. Boost inductor Tl includes a primary coil 52 having one end connected to node 13 and another end connected to the anode of a diode D6. The cathode of the diode D6 is connected to an output 80 of the pre-conditioner circuit C. The anode of diode D6 is also connected to the drain of the mosfet switch Ql, the gate of which is connected to ground via a resistor R13. The control gate of switch Ql is connected to the "OUT" pin (pin 7) of the IC Ul via a resistor R10. The OUT pin provides a pulse width modulated signal at the control gate of the boost switch to control the switching thereof. The multiplier input "MULT_IN" pin (pin 3) is connected to a node between the resistors R5 and R6 and senses the full wave rectified AC voltage on rail RLl, scaled by the voltage divider formed by the resistors R5, R6. The scaled voltage is one input of a multiplier stage within IC Ul. The other input of the multiplier stage is internal and is the difference of an internal error amplifier output and an internal reference voltage. The output of the multiplier stage controls the peak inductor current in the primary of transformer Tl by influencing the timing of the switching of switch Ql . A capacitor C6 is in parallel with the resistor R6 and serves as a noise filter. The "V m " pin (pin 8) receives the input supply voltage for the IC Ul from the output of the inverter circuit E via line 150. Since the output of the inverter is at high frequency, the bypass capacitor C30 provides a stable voltage supply. The "V " pin is also connected to a node between the resistors R5 and R6 via the resistor R8. This provides a small offset voltage to the MULT IN pin, which will be discussed in greater detail with reference to the EMI input filter. The secondary winding 54 of the booster choke Tl has one end connected to ground and its other end connected to the I DCT pin (pin 5) via a resistor Rl l. The I DET pin senses the flyback voltage on the secondary winding 54 associated with the zero crossing of the inductor current through the primary winding 52. The GND pin (pin 6)is connected to ground via line 65 and rail RL2. The C.S. pin (pin 4) senses the current through the boost switch Ql by sensing the voltage drop across the resistor R13 through the resistor R12. A filter capacitor C8, tied between the rail RL2 and the C.S. pin, filters any voltage spikes which occur may upon the switching of the switch Ql from its non-conductive to its conductive state due to the drain-to-source capacitance of mosfet Ql . A second voltage divider including the resistors R14 and R15 is connected between the rails RLl and RL2. The "INV" pin (pin 1) is connected to a node between the resistors R14 and R15 via a resistor R9 and senses the output voltage of the preconditioner stage. The "COMP" pin (pin 2) is connected to the output of the internal error amplifier within IC U4. A feedback compensation network consisting of a resistor R7 and a capacitor C7 connects the COMP pin to the INV pin, thereby providing internal feedback and further control of the switch Ql . The full-wave rectified positive DC voltage from the output 13 of the input rectifier, which may also carry phase control information from a remote dimming controller, enters the pre-conditioner circuit on rail RLl to the voltage divider of resistors R5, R6 and to the booster choke Tl. The DC component divides at lead 44 establishing a reference voltage to the multiplier input MULT_IN pin. When the switch Ql conducts, the resulting current through the primary winding 52 of transformer Tl and switch Ql causes a voltage drop across the resistor R13 that is effectively applied through the resistor R12 to input C.S. This voltage at pin C.S. represents the peak inductor current and is compared with the voltage output by the internal multiplier stage, which multiplier output voltage is proportional to the product of the rectified AC line voltage and the output of the error amplifier internal to IC Ul. When the peak inductor current sensed at pin C.S. exceeds the multiplier output voltage, the switch Ql is turned off and stops conducting. The energy stored in the primary winding 52 is now transferred and stored in the boost capacitor CIO, causing the current through the primary winding 52 to ramp down. When the primary winding 52 runs out of energy, the current through winding 52 reaches zero and the boost diode D6 stops conducting. At this point, the drain to source capacitance of the mosfet switch Ql in combination with the primary winding 52 forms an LC tank circuit which causes the drain voltage on mosfet Ql to resonate. This resonating voltage is sensed by the I DET pin through the secondary winding 54. When the resonating voltage swings negative, the IC Ul turns the switch Ql ON, rendering it conductive. This conduction, non-conduction of switch Ql occurs for the entire cycle of the rectified input and at a high frequency on the order of hundreds of times the frequency of the AC voltage entering the input rectifier. The inductor current through winding 52 has a high frequency content which is filtered by the input capacitor C4, resulting in a sine wave input current in phase with the AC line voltage. Essentially, the pre-conditioner stage makes the ballast look resistive to the power lines to maintain a high power factor. For a 120 V AC input, without phase cutting, the voltage at output 80, the positive side of buffer capacitor CIO, is on the order of 300 V DC with a small alternating DC component present. It is this voltage which is supplied to the ballast stage D, and in particular, to the inverter E. Output voltage regulation is accomplished by the sensing of the scaled output voltage, from the divider formed by the resistors R14, R15, by the internal error amplifier at the INV pin. The internal error amplifier compares the scaled output voltage to an internal reference voltage, and generates an error voltage. This error voltage controls the amplitude of the multiplier output, which adjusts the peak inductor current in winding 52 to be proportional to load and line variations, thereby maintaining a well regulated output voltage for the inverter circuit E. Dimming of the lamp is accomplished through the closed loop control of the average lamp power. A signal representing the average lamp power is compared to the dimming reference voltage generated by dimming interface circuit I. A high gain error amplifier comprised in the controller G drives the conduction time of the switching elements comprised in the halfbridge circuit. This drive is continued until the difference between these two inputs is reduced to near zero, resulting in a linear and proportional control of the lamp power with the dimming reference voltage. The range of this dimming reference voltage is between a maximum level of 3V, and a minimum level of 0.3V. Voltages greater than 3V have the same effect as the maximum, and voltages less than 0.3V are equivalent to the minimum. Figure 3 shows an embodiment of the dimming interface I. The dimming interface provides the dimming reference voltage. The dimming reference voltage output by the dimming interface circuit is the averaged value of the rectified line voltage. The averaged rectified line voltage decreases monotonically as the conduction angle of the AC input signal is decreased with a phase angle dimmer from a maximum to a minimum setting and thus is a good indicator of the setting of the dimmer. The average rectified line voltage is a function of conduction angle. Several factors must be taken into account in supplying the dimming reference voltage. As discussed previously, the dimming reference voltage is compared to a signal representing the averaged lamp power. The lamp control loop changes the conduction time of the switching elements comprised in the inverter until the difference between the signal and the dimming reference voltage is reduced to nearly zero. The lamp control loop is very fast, having a cycle time of about 16 μs. When the dimming reference voltage is changed, the control loop will close generally within about five iterations, so the lamp current is changed to the new level in about 100 μs. Consequently, any change in the dimming reference voltage results in a nearly instantaneous change in the lamp current. In other words, the lamp current will essentially mirror changes in the dim signal. Since the dim signal is derived from the 120 HZ rectifier output and the lamp current mirrors the dim signal, it should have a very low 120 Hz ripple component so as to maintain a good crest factor (i.e. the ratio of the peak to rms value of the lamp current). A good crest factor is important for maintaining the rated life of tubular fluorescent lamps, since a poor crest factor reduces the life of the electrodes. The rectified line voltage signal, however, has an AC ripple component which becomes larger in proportion to the average DC value of the rectified line voltage at lower conduction phase angles. To maintain a good crest factor, the rectified line voltage needs substantial filtering before being input to the DIM input of controller G. In the current embodiment the desired crest factor is 1.6. The response time of the dimming interface must also be fast enough to avoid power imbalances, which affects the bus voltage on RLl across the buffer capacitor CIO, which should be maintained substantially constant (i.e., the average of the DC bus voltage staying within about +/- 10%) for proper operation of the inverter. As mentioned above, the power control loop responds almost instantaneously to changes at the DIM input. The dimming reference voltage must react to changes in the input conduction angle with a speed at least of the same order of magnitude as that of the pre-conditioner. If the reaction time is slower, then when the conduction angle is decreased rapidly by the phase control dimmer, the controller G will lag behind the pre-conditioner. The controller G will still try to operate the lamps at a high light level, and the inverter will be drawing a relatively high power from the pre-conditioner, while the average input voltage to the pre-conditioner has already dropped. By selecting the dimming interface to respond as fast or faster than the output of the pre-conditioner to increases in the conduction angle, this power imbalance situation is avoided. Another consideration, important for the user, is that the change in light level should not noticeably lag behind changes in the setting of the phase control dimmer. In experiments conducted by the inventors, it was determined that the setting of dimmers now commercially available can be changed by a user from the highest to the lowest level, by movement of a slide controller for example, in about 50 ms. The above requirements can be met with a dimming interface circuit having a filter which has a characteristic response time of approximately 50 ms and which has an attenuation of about 30 dB at 120 Hz. The first factor satisfies the requirement for avoiding power imbalances while the latter provides the desired crest factor of 1.6. Another function of the interface circuit is to scale the 120 HZ rectified line signal to provide a dimming voltage at the DIM input of the controller G which varies between a minimum level of 0.3 V and a maximum level of 3V for the minimum and maximum conduction angles from the phase control dimmer. The dim interface circuit shown in Figure 3 includes a switch Q6 connected in series with resistors Rl and R2. The base of switch Q6 is connected to a 5V output of the voltage regulator U3 and is always conductive when the inverter is oscillating. The interface circuit has a two-pole filter which includes a first RC filter formed by the resistors Rl , R4, R27 and the capacitor C5 and a second RC filter formed by the resistor R17 and the capacitor C14. When a phase cut signal such is applied to the inputs l ',2' the voltage on rail RLl is full wave rectified, with the phase cut preserved. The pre-conditioner offset makes the load look purely resistive to input capacitor C4, thereby preserving the phase cut information. Without the pre-conditioner, the capacitor C4 would hold up the input voltage, thereby essentially destroying the phase cut information. The current through the resistor Rl is proportional to the rectified line voltage on rail RLl. The switch Q6 performs the scaling function. The voltage at the top of resistor R2 is constant at about 4.4 V and is equal to the 5V supply from the regulator U3 minus the base-emitter voltage "Vbe" across the switch Q6. The current through the voltage divider network of the resistor R4 and the resistor R27 equals the current through the resistor Rl minus the fixed current through the resistor R2. Since the current through the resistor R2 is constant, the voltage at the top of the resistor R4 is scaled but proportional to the rectified line voltage on rail RLl. The voltage divider formed by the resistors R4 and R27 further scales the dim signal, which is applied to the DIM input of controller G via filter FI. Figure 4 illustrates a second embodiment of the interface circuit. The phase controlled AC signal is derived from the AC side of the rectifier through the voltage divider formed by the resistors R50, R51. The voltage signal at node VI represents the average value of the rectified line voltage scaled down to signal voltage levels. (The divider is taken from the AC side of the bridge so as to slightly minimize the effect of capacitive hold-up of this voltage under light loading conditions). The voltage VI is scaled with a reference voltage V3, resistor R55, R56 and an Opamp 60 to generate voltage signal V2. This voltage is proportional to the lamp current required at the set phase angle. The scaling factors can be altered to give the desired range of dimming characteristics with the phase angle and to compensate for line variations. The three pole filter is formed by the three RC pairs R52, C52, R53, C53 and R54, C54. A further advantage of the three pole filter is that the small amount of ripple voltage at node V 1 helps in obtaining a better lamp current crest factor by compensating for the ripple on the boost capacitor (CIO) voltage. With the given preconditioner topology, the ripple on the boost capacitor voltage lags the AC component of the rectified line voltage by approximately 90°. With the three-pole-filter, the ripple voltage at node VI lags the AC component of the rectified line voltage by approximately 270°. Thus the ripple on the commanding dim signal is approximately 180° out of phase with the ripple on the bus voltage at the boost capacitor. This helps with the crest factor, especially at the current levels where the lamp tank network exhibits a high gain for the lamp current with respect to the 120 Hz ripple on the bus voltage. This implementation gives a -3 dB frequency of about 9 Hz (0-90% response time of about 60 milliseconds for a pulse input) and -30 dB attenuation of the 120 Hz ripple for the averaging filter. The response time of 60 mSEC to reach 90% is about three times faster compared to a single pole filter giving the same 120 Hz attenuation. Under non-dimming conditions, the disclosed ballast maintains a power factor of approximately 0.99, a THD smaller than 10%, and a crest factor smaller than 1.6, so the circuit satisfies both the need for a triac dimmable ballast while also providing a high power factor ballast for non-dimming use. The phase angle dimmer shown in Figure 5 is provided with a triac connected in the power supply line 1". A series circuit consisting of a variable resistor 216 and a capacitor 218 is connected in parallel with the triac 214 for firing the triac 214 at an arbitrarily selected angle for phase conduction. A diac 200 is connected between a node of the variable resistor 216 and the capacitor 218, and the gate of the triac 14. By varying the resistance of the variable resistor 216, the phase controller supplies a voltage whose phase angle is controlled to the ballast input terminals 1' and 2.

Claims: CLAIMS: 1. A discharge lamp ballast for use with a phase angle dimmer, said discharge lamp ballast comprising: - a pair of mains input terminals for receiving a phase angle controlled AC mains voltage; - ballasting means for providing electrical power to a discharge lamp, said ballasting means including (i) a DC input at which a substantially constant DC voltage is received, (ii) a dim input separate from said DC input for receiving a dimming signal and (iii) first control means for controlling the electrical power supplied to the discharge lamp at a level corresponding to a characteristic of the dimming signal; - power supply means connected to said mains input terminals for supplying the substantially constant DC voltage to said DC input of said ballasting means; and - dim signal deriving means for deriving the dimming signal from the phase angle controlled AC mains voltage and for supplying the dimming signal to said dim input of said ballasting means, characterized in that said power supply means comprises feedback means for maintaining said DC-voltage at a substantially constant level independent of the conduction angle of the phase angle controlled AC mains voltage. 2. A discharge lamp ballast according to claim 1 , wherein said characteristic of the dim signal is the dim signal voltage. 3. A discharge lamp ballast according to claim 1 or 2, further comprising rectifier means connected to said mains input terminals for providing a full-wave rectified DC output voltage to said power supply means and said dim signal deriving means, and wherein said dim signal deriving means is equipped with filter means for generating a signal that is substantially proportional to the average value of the rectified DC voltage from said rectifier means. 4. A discharge lamp ballast according to claim 3, wherein said filter means comprises a two-pole filter. 5. A discharge lamp ballast according to claim 3, wherein said filter means comprises a three-pole filter. 6. A discharge lamp ballast according to one or more of the previous claims so dimensioned that the characteristic response time of the first control means is substantially shorter than the characteristic response time of said feedback means and that the characteristic response time of said means for deriving said dimming signal has a characteristic response time that is shorter than the characteristic response time of said feedback means and longer than the characteristic response time of said first control means. 7. A discharge lamp ballast according to claim 3, 4 or 5, including further filter means for suppressing high frequency harmonics entering the mains supply, said further filter means including a filter capacitor coupled to an output of said rectifier means and charged by said rectified output voltage and wherein said power supply means include (i) a controllable switching means switchable between a conductive and a non-conductive switching state and providing a discharge path for said filter capacitor, and (ii) control means for controlling the switching state of said switching means, said control means switching said switching state of said switching means at frequencies substantially higher than said mains frequency to control the DC supply voltage, and wherein said control means of said power supply means includes means for maintaining said high frequency switching of said switching means so as to discharge said filter capacitor when said phase controlled rectified output voltage is at or near zero. 8. A discharge lamp ballast according to claim 3, 4, 5, 6 or 7, wherein said dim signal deriving means comprise means for suppressing the ripple present in the dim signal at twice the frequency of the phase angle controlled AC mains voltage.

Inventors: FARKAS THOMAS, JAYARAMAN RAJ, VENKITASUBRAHMANIAN SREERAMAN, XIA YONGPING, FARKAS, THOMAS, JAYARMAN, RAJ, VENKITASUBRAHMANIAN, SREERAMAN, XIA, YONGPING
Applicants: PHILIPS ELECTRONICS NV, PHILIPS NORDEN AB, PHILIPS ELECTRONICS N.V.
Application year: 1996
Main classification: H05B41
IPC codes: H05B37, H05B41