VOLTAGE CONTROLLED CRYSTAL OSCILLATOR AND LOOP FILTER

Abstract: A controllable crystal oscillator, producing a clock signal at a desired frequency, includes a voltage controlled crystal oscillator (110) producing a signal at a subharmonic of the desired frequency. The voltage controlled crystal oscillator is coupled to a first duty cycle corrector (120), which produces a signal having substantially a desired duty cycle. The first duty cycle corrector is coupled to a frequency multiplier (130), which produces a signal at substantially the desired frequency. The frequency multiplier, in turn, is coupled to a second duty cycle corrector (140). The second duty cycle corrector produces the clock signal at the desired frequency and having the desired duty cycle.

Description: VOLTAGE CONTROLLED CRYSTAL OSCILLATOR AND LOOP FILTER The present application relates to a voltage control crystal oscillator (VCXO) and loop filter for generating relatively high frequency digital clock signals. In current high speed modem applications, such as digital satellite broadcast systems, it is necessary to have a controllable clock signal of around 40MHz, in which the duty cycle is maintained at substantially 50%. Fundamental crystals in this frequency range do not have sufficient pull range to provide adequate signal locking capability, and compensation for varying crystal parameters. Thus, prior art VCXOs have used third overtone crystals. However proper VCXO operation in this fre¬ quency range using third overtone crystals is not obtainable without using significant adjustments. Another approach has been to use a fundamental at an appropriate subharmonic of the desired clock frequency, and use frequency multipli¬ cation to produce the clock signal. Such frequency multipliers are typically phase locked loops (PLL). However, PLLs introduce phase jitter into the clock signal and can have lock-up problems during operations such as frequency scanning operations. Furthermore, the output from a typical integrated circuit (IC) oscillator does not have a duty cycle of 50%. Instead, the leading and trailing edges of the clock signal produced by such oscillators is skewed due to the varying rise and fall times of the IC gate used as the oscillator amplifier. A simple controllable crystal oscillator in this relatively high frequency range, which has a stable duty cycle and relatively low phase jitter, is desirable for use in high speed equipment such as the digital satellite high speed modems. In accordance with principles of the present invention, a controllable crystal oscillator, producing a clock signal at a desired frequency, includes a voltage controlled crystal oscillator producing a signal at a subharmonic of the desired frequency. The voltage controlled crystal oscillator is coupled to a first duty cycle corrector, which produces a signal having substantially a desired duty cycle. The first duty cycle corrector is coupled to a frequency multiplier, which produces a signal at substantially the desired frequency. The frequency multiplier, in turn, is coupled to a second duty cycle corrector. The second duty cycle corrector produces the clock signal at the desired frequency and having the desired duty cycle In the drawing: Fig. 1 is a block diagram of a portion of a digital satellite system high speed modem incorporating the present invention; Fig. 2 is a more detailed block diagram of a controlled crystal oscillator according to the present invention; Fig. 3 is a more detailed block diagram of a loop filter according to the present invention; and Fig. 4 is a schematic diagram of the controlled oscillator illustrated in Fig. 2. Fig. 1 is a block diagram of a portion of a digital satellite system high speed demodulator incorporating the present invention. Only those elements necessary for or useful in understanding the present invention are illustrated in the drawing. One skilled in the art will understand what other elements are required in such a system, how to design and imple¬ ment those other elements, and how to interconnect those other elements with the elements illustrated in the drawing. In a ground station of a digital satellite system, a data signal (for example, representing a television program) is formed into a sequence of symbols in a known manner. A signal representing this symbol sequence is modulated onto a carrier and transmitted to the satellite, which broad¬ casts the modulated symbol sequence to terrestrial receivers. These receivers demodulate signal representing the symbol sequence, recover the symbol sequence, and recreate the data signal, all in a known manner. Part of the processing performed by the receivers is to recover the symbol timing so that the symbols may be extracted accurately. While the transmitted symbol timing is generally stable, there may be slight differences in timing among symbol sequences representing different data signals (for example, from different satellites or ground stations), or the timing may shift slightly due to propagation effects, component parameter variation, or switching transponders within a satellite. Thus, the clock used to recover the symbol timing in the receiver must be stable, but controllable to compensate for slight variations in symbol timing. In Fig. 1 , an input terminal is coupled to a source (not shown) of samples of the received signal representing the symbol sequence. The sample data input terminal is coupled to a first input terminal of a symbol timing recovery circuit 300. A second input terminal of the symbol timing recovery circuit 300 is coupled to an output terminal of a controlled oscillator 100, which provides the timing clock signal necessary to recover the symbol sequence. A first output terminal of the symbol timing recovery circuit 300 produces a signal representing the recovered symbol sequence. The symbol data output terminal is coupled to further utilization circuitry (not shown) which processes the recovered symbol sequence to recover the transmitted data, and operates on that data (for example, generating the television program image and sound), all in a known manner. A second output terminal of the symbol timing recovery circuit 300, producing a timing error signal, e, in the form of a binary rate multiplier (BRM) signal (described in more detail below), is coupled to an input terminal of a BRM filter 200. An output terminal of the BRM filter 200 is coupled to a control input terminal of the controlled oscillator 100. In operation, the symbol timing recovery circuit 300 recovers the transmitted symbol sequence from the samples supplied to it based on the timing of the clock signal supplied to it by the controlled oscillator 100 in a known manner. As described above, in current digital satellite systems, the nominal frequency of the clock signal is 40MHz. In addition, in order to accurately recover the symbol sequence, this clock signal must have a duty cycle of substantially 50%. Because the timing of the transmitted symbol sequence is relatively stable, the controlled oscillator 100 clock signal is based on a crystal oscillator. The symbol timing recovery circuit 300 also analyzes the received samples, and generates the error signal, e, which represents the error in timing between the transmitted symbol sequence, and the current clock signal from the controlled oscillator 100. In the illustrated embodiment of the symbol timing recovery circuit 300, the error signal, e, is in the form of a binary rate multiplier signal, which is a pulse train having an average analog value equal to the value of the timing error. The timing error signal, e, is filtered by the BRM filter 200, and the filtered error signal used to control the output frequency of the controlled oscillator 100 to attempt to make this error signal zero, all in a known manner. Fig. 2 is a more detailed block diagram of a controlled crystal oscillator 100 according to the present invention. In Fig. 2, a control signal from the BRM filter 200 (of Fig. 1) is coupled to a control input terminal of a voltage controlled crystal oscillator (VCXO) 110. An output terminal of the VCXO 110 is coupled to an input terminal of a first duty cycle corrector 120. And output terminal of the first duty cycle corrector 120 is coupled to an input terminal of a frequency doubler circuit 130. An output terminal of the frequency doubler circuit 130 is coupled to an input terminal of a second duty cycle corrector 140. An output terminal of the second duty cycle corrector 140 produces the clock signal and is coupled to the clock signal input terminal of the symbol timing recovery circuit 300 (of Fig. 1). In operation, the VCXO 110 operates at 20MHz, which is one-half the desired clock frequency of 40MHz. In a preferred embodiment, the VCXO 1 10 is fabricated as an IC oscillator. However, as described above, an IC oscillator does not provide stable 50% duty cycle clock signals. If such a signal were doubled in frequency, it would be impossible to generate a phase and duty cycle stable clock signal. The first duty cycle corrector 120 operates to correct for the varying duty cycle, and produces a clock signal having a substantially 50% duty cycle. This signal may be frequency doubled with minimized phase jitter. The frequency doubler 130 operates in a known manner to produce a 40 MHz clock signal. The second duty cycle corrector 140 corrects for any phase jitter introduced by the frequency doubling operation, and produces a 40 MHz clock signal having minimal phase jitter and a duty cycle of substantially 50%. Fig. 3 is a more detailed block diagram of a symbol timing recovery loop according to the present invention. In Fig. 3, elements which are the same as those illustrated in Fig. 1 are designated by the same reference number, and are not described in detail below. In Fig. 3, the BRM filter 200 consists of the serial connection of a discrete low pass filter (LPF) 210 and DC amplifier 220 coupled between the symbol error signal output terminal of the symbol timing recovery circuit 300 and the control input terminal of the controllable oscillator 100. As described above, circuitry (not shown) in the symbol timing recovery circuit 300 extracts the symbol sequence from the samples sup¬ plied to it at its input terminal, and produces those symbols at its output terminal, all in a known manner. In addition, the symbol timing recovery circuit 300 produces a binary rate multiplier (BRM) output signal whose analog average value represents the error signal, e. To this end, the symbol timing recovery circuit comprises the serial connection of a symbol timing recovery (STR) error estimator 310, an STR loop filter 320 and a BRM signal generator 330. These elements are implemented as digital logic circuits, and are designed and operate in a known manner. The BRM error signal, e, from the BRM generator 330 must be fil- tered to eliminate the BRM pulse frequency components and leave only the error signal component - that is, the average value of the BRM pulse signal. A low pass filter is necessary to perform this function. In prior art circuits, low cost operational amplifiers, configured to form an active low pass filter have been used to perform the low pass filtering. However, it has been found that an active low pass filter can transmit some portion of the input signal to it's output signal, thereby distorting the output signal, a condition termed feedthrough. To overcome this problem, it has been discovered that a discrete low pass filter, made up of passive components, placed before the DC voltage translating/amplifying amplifier eliminates this problem. In operation, the discrete LPF 210 is constructed of an RC low pass filter, or a plurality cascade RC low pass filter stages (described in more detail below). Such a network provides the same low pass filtering characteristics as an active filter, without feedthrough. The output signal from the discrete LPF 210 is processed by the DC amplifier 220 to produce the control signal for the controllable oscillator 100. The DC amplifier 220 provides the voltage level shifting, and error signal amplification necessary to produce the appropriate control signal for the controllable oscillator 100, all in a known manner. Fig. 4 is a schematic diagram of the symbol timing recovery loop illustrated in Fig. 3. In Fig. 4, a first electrode of a crystal XI is coupled to an input terminal of an integrated circuit (IC) gate 10, and to respective first electrodes of a first resistor Rl , and a first capacitor Cl . A second electrode of the crystal XI is coupled to respective first electrodes of a second resistor R2 and a second capacitor C2. An output terminal of the first IC gate 10 is coupled to respective second electrodes of the first resistor Rl and the second resistor R2, and to a first electrode of a third resistor R3. A second electrode of the first capacitor Cl is coupled to a first electrode of a first varactor VI . A second electrode of the second capacitor C2 is coupled to a first electrode of the second varactor V2. Respective second electrodes of the first varactor VI and the second varactor V2 are coupled to a source of a reference potential (ground). The combination of the logic gate 10, the crystal XI , the first and second resistors, Rl and R2, the first and second capacitors, Cl and C2, and the first and second varactors, V I and V2, respectively, is a logic gate version of an isolated Pierce oscillator, and forms the VCXO 110 (of Fig. 2). The crystal XI is a fundamental mode crystal having a center frequency of 20MHz. In a preferred embodiment, the crystal XI has a nominal load capacitance of 8pf and a range of at least ± lOOppm within a load capacitance range of from 5pf to 14pf. The logic gate 10 is a standard IC logic gate, and in a preferred embodiment is one of four exclusive-OR gates fabricated in a single IC package (such as an industry standard 74AC86). Gates 30, 50 and 60 (de- scribed in more detail below), illustrated in Fig. 4, are formed from the remaining three exclusive-OR gates in that IC package. In such an embodiment, only one input terminal of the exclusive-OR gates 10, 30 and 60, receives input signals, and the respective second input terminals of these gates are coupled to a source of a logic ' 1 ' signal in a known manner (not shown). Resistor Rl biases the input of the logic gate 10 in the active region. Resistor R2 limits the crystal current, and allows for phase shifts and frequency roll off under control of the second varactor V2. In Fig. 4, the first and second varactors, VI and V2, respectively, have a range of capacitance from 25.5pf at a DC voltage of 1 volt to 6pf at a DC voltage of 10.5 volts. In a preferred embodiment, the varactors are manufactured by Sony Corp., and have a Thomson Consumer Electronics, Inc. part number 445-480. A first tuned circuit, comprising a parallel connection of a third capacitor C3 and a first inductor LI , in series with a fourth capacitor C4, is coupled between a second electrode of the third resistor R3 and ground. The third resistor R3 provides isolation and current limiting for the first tuned circuit. The first tuned circuit is designed to have a resonant frequency of substantially 20 MHz, the output frequency of the VCXO 1 10. The first tuned circuit has a high impedance at the resonant frequency, and a low impedance at other frequencies. In this manner all other frequency components of the output clock signal from the VCXO 1 10 are shunted to ground, leaving only the component of the VCXO 1 10 output signal near the 20MHz resonant frequency of the first tuned circuit. The signal at the second electrode of resistor R3, therefore, is a sinewave at the frequency of the VCXO 110. A fifth capacitor C5 is coupled from the junction of the second electrode of the third resistor R3 and the first tuned circuit, to an input terminal of the second logic gate 30, and to respective first electrodes of a fourth resistor R4 and a fifth resistor R5. A second electrode of the fourth resistor R4 is coupled to a source of an operating potential V cc , and a second electrode of the fifth resistor R5 is coupled to ground. An output terminal of the second logic gate 30 is coupled to the input terminal of the logic gate 30 by a sixth resistor R6. The combination of the fourth and fifth resistors, R4 and R5, provide a discharge path for the fifth capacitor C5, and a rough DC bias for the input terminal of the second logic gate, and the sixth resistor R6 biases the second logic gate 30 in the active region. The fifth capacitor C5 AC couples the nominally 20MHz sine wave from the first tuned circuit to the input terminal of the second logic gate 30. A logic gate connected in this manner operates as a high gain amplifier. When a sinewave signal is AC coupled to an input terminal of a logic gate, it normalizes to the middle bias point. The sine wave input signal, therefore, will produce a substantially 50% duty cycle clock signal at the output terminal of the second logic gate 30. The combination of the first tuned circuit (C3, LI , C4) and the second logic gate 30 with its biasing components (R4, R5, R6) forms the duty cycle correction circuit 120 (of Fig. 1 ). The output terminal of the second logic gate is coupled to a first input terminal of an exclusive-OR gate 50, and to an input terminal of a delay circuit 40. An output terminal of the delay circuit 40 is coupled to a second input terminal of the exclusive-OR gate 50. The delay circuit 40 may, for example, be a discrete low pass RC filter having a resistor coupled between its input and output terminals, and a capacitor coupled between its output terminal and ground. The combination of the exclu¬ sive-OR gate 50 and the delay circuit 40 produces a train of pulses at each transition of the 20MHz input signal, or at a 40MHz rate, in a known manner. Thus, they form a frequency doubler 130 (of Fig. 1 ). The output terminal of the exclusive-OR gate 50 is also coupled to a first electrode of a seventh resistor R7. A second tuned circuit, comprising a parallel connection of a sixth capacitor C6 and a second inductor L2 in series with a seventh capacitor C7, is coupled between a second electrode of the seventh resistor R7 and ground. The seventh resistor R7 provides isolation and current limiting to the second tuned circuit. The second tuned circuit has a resonant frequency of twice the frequency of the VCXO 110, or 40MHz. The second tuned circuit also has a high impedance at the resonant frequency and a low impedance for other frequencies. Thus, other frequencies are shunted to ground, leaving only the component of the output signal of the exclusive-OR gate 50 around the resonant frequency of the second tuned circuit, i.e. 40MHz. The signal at the junction of the second electrode of the seventh resistor R7 and the second tuned circuit, thus, is a sinewave at twice the frequency of the VCXO 1 10. An eighth capacitor C8 is coupled from the junction of the second electrode of the seventh resistor R7 and the second tuned circuit to an input terminal of a third logic gate 60, and to respective first electrodes of an eighth resistor R8 and a ninth resistor R9. A second electrode of the eighth resistor R8 is coupled to the source of operating potential V cc and a second electrode of the ninth resistor R9 is coupled to ground. An output terminal of the third logic gate 60 is coupled to the input terminal of the third logic gate 60 through a tenth resistor RIO. In a similar manner to the second logic gate 30, the eighth and ninth resistors, R8 and R9, respectively, provide a discharge path for the eighth capacitor C8 and a rough DC bias for the input terminal of the third logic gate 60, and the tenth resistor R10 biases the third logic gate 60 in the active region. The eighth capacitor C8 AC coupled the nominally 40MHz sinewave signal from the second tuned circuit to the input terminal of the third logic gate 60. Because the sinewave AC coupled to the input terminal normalizes to the middle bias point, the third logic gate produces a clock signal having twice the frequency of the VCXO 110 and a duty cycle of substantially 50%. The combination of the second tuned circuit (C6, L2, C7) and the third logic gate 60 with its biasing components (R8, R9, R10) form the duty cycle correction circuit 140 (of Fig. 1). The output terminal of the third logic gate 60 is coupled to a first electrode of an eleventh resistor Rl l . A second electrode of the eleventh resistor Rl l produces the desired 40MHz controlled clock signal having a duty cycle of substantially 50%, and is coupled to a first electrode of a ninth capacitor C9, and to the input terminal of the symbol timing recovery (STR) circuit 300 (of Fig. 1). The eleventh resistor Rl l and ninth capacitor C9 form an RC network for rolling off the high harmonic content of the clock signal produced by the third logic gate 60. The output terminal of the symbol timing recovery (STR) circuit 300 is coupled to a first electrode of a twelfth resistor R12. A second electrode of the twelfth resistor R12 is coupled to respective first electrodes of a tenth capacitor CIO and a thirteenth resistor R13. A second electrode of the thirteenth resistor R13 is coupled to respective first electrodes of an eleventh capacitor Cl l and a fourteenth resistor R14. A second electrode of the fourteenth resistor R14 is coupled to respective first electrodes of a twelfth capacitor C 12 and a fifteenth resis- tor R15. A second electrode of the fifteenth resistor R15 is coupled to respective first electrodes of a thirteenth capacitor C 13 and a sixteenth resistor R16. A second electrode of the sixteenth resistor R16 is coupled to an input terminal of a DC amplifier 220. As described above, the symbol timing recovery circuit 300 uses the 40MHz clock produced by the controlled oscillator 100, to recover the transmitted symbols, and produces an error signal, e, representing the error between the clock signal from the controlled oscillator 100 and the timing of the received symbols. In the preferred embodiment this error signal is in the form of a binary rate multiplier (BRM) signal whose average value is the value of the error. This BRM signal is filtered by discrete filter 210 to extract the average value. The twelfth resistor R12 and tenth capacitor CIO form a first low-pass RC filter stage; the thirteenth resistor R13 and the eleventh capacitor Cl l for a second low- pass RC filter stage; the fourteenth resistor R14 and the twelfth capacitor C12 for a third low-pass RC filter state; and the fifteenth resistor R15 and the thirteenth capacitor C13 form a fourth low-pass RC filter stage. The first, second, third and fourth low-pass filter stages, in combination, form the discrete low-pass filter (LPF) 210 (of Fig. 3). The discrete low-pass filter 210 generates a signal representing the average value of the BRM error signal, e, from the symbol timing recovery circuit 300. The discrete low-pass filter 210 is coupled to the input terminal of the DC amplifier 220 through a sixteenth resistor R16. The output terminal of the DC amplifier 220 is coupled to a first electrode of a fourteenth capacitor C14 and to the respective first electrodes of the first varactor VI and the second varactor V2 through a seventeenth resistor R17, and as eighteenth resistor R18. A second electrode of the fourteenth capacitor C14 is coupled to ground. The DC amplifier 220 generates a DC control signal for the first and second varactors, VI and V2, respectively. The seventeenth and eighteenth resistors, R17 and R18, respectively, operate to isolate the DC amplifier 220 from each of the first and second varactors, VI and V21 , respectively, and the first and second varactors, VI and V2, respectively, from each other. The fourteenth capacitor C 14 provides additional filtering for the varactor control signals. Table I, below, gives preferred values for the components illus- trated in Fig. 4. While the present invention is illustrated as embodied in a digital satellite system, one skilled in the art will understand that a controllable oscillator according to the present invention may be used wherever a controllable crystal oscillator having a relatively high frequency, and closely controlled duty cycle is required. TABLE I COMPONENT VALUES

Claims: CLAIMS 1 . A controllable oscillator for producing a clock signal at a desired frequency, comprising: a voltage controlled crystal oscillator generating an oscillato¬ ry signal at a subharmonic of the desired frequency; a first duty cycle corrector, coupled to the voltage controlled crystal oscillator; a frequency multiplier, coupled to the first duty cycle corrector, for generating an oscillatory signal at the desired fre¬ quency; and a second duty cycle corrector, coupled to the frequency multiplier, for producing the clock signal at the desired frequency. 2. The controlled oscillator of claim 1 wherein the voltage controlled crystal oscillator comprises an isolated Pierce oscillator. 3. The controlled oscillator of claim 2 wherein the voltage controlled crystal oscillator comprises a logic gate isolated Pierce oscillator. 4. The controlled oscillator of claim 2 wherein the voltage controlled crystal oscillator comprises a fundamental mode crystal. 5. The controlled oscillator of claim 2 wherein the desired frequency is substantially 40 MHz and the subharmonic of the desired frequency is substantially 20 MHz. 6. The controlled oscillator of claim 1 wherein the first duty cycle corrector corrects the duty cycle to substantially 50%, and comprises: a tuned circuit, having a resonant frequency of substantially the subharmonic of the desired frequency, coupled to the voltage controlled crystal oscillator; a high gain amplifier, having an input terminal biased to its midpoint, and an output terminal producing a duty cycle corrected oscillatory signal; and circuitry for AC coupling the tuned circuit to the input terminal of the high gain amplifier. 7. The controlled oscillator of claim 6 wherein the high gain amplifier comprises a logic gate biased in the active region. 8. The controlled oscillator of claim 6 wherein: the voltage controlled oscillator has an output terminal coupled to the first duty cycle corrector; and the tuned circuit is coupled between the output terminal of the voltage controlled oscillator and a source of a reference potential, and exhibits a high impedance at its resonant frequency and a low impedance otherwise. 9. The controlled oscillator of claim 1 wherein the frequency multiplier comprises: an exclusive-OR gate, having a first input terminal coupled to the first duty cycle corrector and a second input terminal, and producing the oscillatory signal at the desired frequency; and a delay circuit coupled between the first duty cycle corrector and the second input terminal of the exclusive-OR gate. 10. The controlled oscillator of claim 1 wherein the second duty cycle corrector comprises: a tuned circuit having a resonant frequency of substantially the desired frequency; a high gain amplifier, having an input terminal biased to its midpoint, and an output terminal producing the clock signal; and circuitry for AC coupling the tuned circuit to the input terminal of the high gain amplifier. 1 1 . The controlled oscillator of claim 10 wherein the high gain amplifier comprises a logic gate biased in the active region. 1 2. The controlled oscillator of claim 10 wherein: the frequency multiplier has an output terminal coupled to the second duty cycle corrector; and the tuned circuit is coupled between the output terminal of the frequency multiplier and a source of a reference potential and exhibits a high impedance at its resonant frequency and a low impedance otherwise. 1 3. A signal processing system, comprising: a controllable oscillator for producing a clock signal at a desired frequency, comprising: a voltage controlled crystal oscillator generating an oscillatory signal at a subharmonic of the desired frequency in response to a control signal; a first duty cycle corrector, coupled to the voltage controlled crystal oscillator; a frequency multiplier, coupled to the first duty cycle corrector, for generating an oscillatory signal at the desired frequency; and a second duty cycle corrector, coupled to the frequency multiplier for producing the clock signal at the desired frequency ; a signal processing circuit, responsive to the clock signal, for processing an input data signal and producing an output data signal, and a clock timing error signal; a discrete filter, responsive to the clock timing error signal; circuitry, coupled between the discrete filter and the voltage controlled oscillator, for generating the control signal to minimize the clock timing error signal. 14. The system of claim 13 wherein: the signal processing circuit comprises circuitry for generating the clock timing error signal in the form of a binary rate multiplier signal; the discrete filter comprises a discrete low pass filter; and the control signal generating circuitry comprises a DC amplifier. 1 5. The system of claim 14 wherein the discrete filter comprises an RC low pass filter.

Inventors: PITSCH ROBERT ALAN, RAMASWAMY KUMAR, STEWART JOHN SIDNEY, WAGNER PAUL KELLY, PITSCH, ROBERT, ALAN, RAMASWAMY, KUMAR, STEWART, JOHN, SIDNEY, WAGNER, PAUL, KELLY
Applicants: THOMSON CONSUMER ELECTRONICS, THOMSON CONSUMER ELECTRONICS, INC.
Application year: 1996
Main classification: H03K3
IPC codes: H03B5, H03J9, H03K3, H03K5, H03K17, H03L7, H04L7, H04M1