INTEGRATED CIRCUIT FULL-WAVE RECTIFIER

Abstract: An integrated circuit full-wave rectifier which can be implemented in CMOS technology comprises a first pair of N channel transistors (104, 106) arranged to switch on opposing half cycles of an a.c. input signal and having their gates connected to receive opposing half cycles; and a second pair of N channel transistors (102, 108) also arranged to switch on opposing half cycles and being connected in common drain mode. The circuit may also be provided with a voltage limiter circuit comprising a third pair (112, 114) and a fourth pair (118, 120) of N channel transistors arranged to operate on opposing half cycles, a first transistor (114, 120) of each pair being connected in common drain mode and the gates of the other transistor (112, 118) of each pair being supplied from a P channel transistor (110), the P channel transistor having its gate supplied with a reference voltage.

Description: INTEGRATED CIRCUIT FULL-WAVE RECTIFIER This invention relates to rectifiers, especially to rectifiers implemented in integrated circuit form, and more especially to integrated circuits implemented in CMOS technology. Conventionally, rectification is provided by use of diodes, but in some types of integrated circuit technology, notably CMOS, diodes do not exist. If a complex circuit is to be implemented in integrated form, it is inconvenient if a rectifier circuit must be provided in an alternative technology. It is an object of the invention to provide a rectifier circuit capable of implementation in CMOS. Further, it is known that in integrated circuits including CMOS circuits, the applied voltage level must be limited to avoid damage. CMOS circuits can operate at a maximum of 40 volts, and often a much lower voltage maximum, such as 3 volts, is required. It is a further object of the invention to provide a voltage limiter circuit associated with a rectifier circuit and also implementable in CMOS technology. An integrated circuit rectification circuit is disclosed in Patent Abstracts of Japan, volume 012, No. 287 (E-643), 5 August 1988 and JP-A-63 064572, Tamura Electric Works Limited, but not all the transistors are of the same type, with the inconvenience that they cannot all be placed in the same silicon well, so that voltage protection cannot be maximised. In FR 2 520950 Ates. a transistor bridge rectifier circuit is disclosed, but the circuit cannot be implemented in integrated circuit form. According to the invention, an integrated full wave rectifier comprises a first pair of transistors arranged to switch on opposing half cycles of an a.c. input signal, and a second pair of transistors of the same type as the first pair and arranged in current limiting mode and which also operate on opposing half cycles of said signal. Preferably the transistors are all N channel transistors with the first pair having their gates connected to receive opposing half cycles of said a.c. input signal, and with the second pair connected in common drain mode. Preferably the circuit is implemented in CMOS technology. Preferably there is also provided a voltage limiter circuit connected to the aforesaid full wave rectifier comprising a depletion transistor arranged to connect the gates of the current limiter transistors to ground when the voltage applied by the secondary coil exceeds a predetermined level. It is an advantage of a CMOS full wave rectifier and voltage limiter according to the invention that an integrated circuit can be connected through such circuitry to mains voltage without the need for a transformer. The circuit may even be used at voltages up to 1 100 volts, and may be used at the 600 volts conventionally used for train and tram supplies. It is an advantage of the invention that i.e. control circuits for applications as diverse as a liquid crystal display driver, a lift or elevator control, and an a.c. engine, can all be connected directly to the apparatus to be controlled without the need for a transformer. When applied to thyristor control, e.g. of train or tram 600v power supplies, it is a further advantage that the thyristors can operate on only two pins, as the thyristor gate is tied to the integrated circuit. This is in contrast to the arrangement disclosed in IEEE Transactions on Industrial Electronics, Vol. 42. No. 5, October 1995 in the paper 'Safe and Time-Optimized Power Transfer Between Two Induction Loads Supplied by a Single Generator', by M.-L Bendaas et al. The arrangement according to the invention is also markedly more simple than the prior art circuit, which requires transformers and related power supplies to operate the control computer and interface boxes for the galvanic separation of the control computer and the gates of the thyristors. Another application is in meters for electricity supply. In another application, when d.c. power from e.g. a solar cell is to be connected to a.c. power, the inventive circuit can be used without the use of a transformer and its associated power loss. While other applications are technically possible, safety regulations on voltage separation may apply commercial restraints. The invention will now be described by way of example only with reference to the accompanying drawings in which:- Figure 1 is a schematic diagram of an electronic identification system, Figure 2 is a more detailed diagram of such a system. Figure 3(a) illustrates a solid state full wave rectifier and over voltage protection circuit which can be implemented in CMOS technology, Figures 3(b) and 3(c) illustrate the voltage cycles at various parts of the circuit of Figure 3(a), Figures 3(d) and 3(e) illustrate the relative voltage magnitudes during operation of the circuits of Figure 3(a) and Figure 4 illustrates application of the invention in a thyristor-controlled power supply. Figure 1 illustrates an electronic identification system comprising an interrogator 10 and a passive transponder 12. The interrogator transmits power to the transponder, as indicated at 14, for example at 150 to 250 kHz. and the transponder utilises the power to transmit an identification signal 16, for example at a few hundred MHz, by amplitude, frequency or phase modulation introduced by known techniques. Figure 2 shows in more detail a transponder 12 according to a first aspect of the invention. The transponder has three antennae 18, 20, 22, each in the form of an LC circuit; antenna 18 comprises a power antenna; antenna 20 comprises a data receive antenna; and antenna 22 comprises a data transmit antenna. Typically the number of windings in the respective coils of antennae 18, 20 and 22 is 120:30:60. The power antenna 18 is connected to a power storage capacitor 24 through a full wave rectification circuit 26; the circuit 26 is indicated here by four diodes and will be described in more detail subsequently with reference to Figure 3. The data receive antenna 20 is connected to a data input circuit 28, and the data transmit antenna 22 is connected to a data output circuit 30. All four integers are supplied with power from the power capacitor 24 and, as illustrated, the capacitor 24 and the data input and output circuits 28, 30 are formed as an integrated circuit (i.e.) 32. Figure 2 also indicates part of the interrogator 10 having a transmitting antenna 34 connected to an i.e. 36 connected by a conventional serial or parallel data line 38 to signal processing circuitry (not shown). -_•- In operation, antenna 34 radiates an alternating magnetic field which induces energy in the coils of the three antennae 18, 20, 22; as power antenna 18 contains substantially the largest number of coils, it receives the largest amount of energy which is rectified by circuit 26 and stored by capacitor 24 which then acts as the power source for all components of the transponder 12. The data receive antenna 20 receives a smaller amount of energy, and the modulated signal is inteφreted by its associated circuit 28. In response, circuit 30 provides an identification signal which is transmitted by data transmit antenna 22 and received by antenna 34, then decoded to identify the transponder 12. In the interrogator 10, integrated circuit 36 comprises a microprocessor 40 connected through a data line interface 42 to the data line 38 and to a data buffer 44; buffer 44 is connected to a digital signal analysing unit 46 which in turn is connected through an output transmitter 48 to the microprocessor 40 and to one side of antenna 34; there is also provided an integrated local oscillator 49 connected to the antenna 34. In operation, data received from data line 38 for transmission by antenna 34, or data received by antenna 34, are stored in buffer 44; for data transmission, the antenna 34 is modulated accordingly; data received is analysed by the digital signal analysis unit 46. It is a major feature of a transponder as illustrated in Figure 2 that it can be implemented in CMOS. The power supplied to the power antenna 18 is a.c, which must be rectified. Further, CMOS technology operates only at low voltages, frequently at 5 volts. If a higher voltage is received by the IC, it will be seriously damaged. This can easily occur as the distance from the interrogator 10 to the transponder 12 can vary considerably in practical use. A voltage limiter is therefore required. A suitable circuit providing both of these functions and capable of implementation in CMOS is illustrated in Figure 3. A full wave rectifier (shown schematically in Figure 2 at reference 26) can be implemented in CMOS. It comprises four N channel transistors 102. 104. 106. 108 substituted for the diodes of the bridge 26. Transistors 104, 106 have their gates connected to opposite ends of the secondary winding 18a of power antenna 18 and therefore act as switches. Transistors 102, 108 are connected in common drain mode. The four transistors together form a rectifier circuit. In one half cycle, e.g. when the left hand side of coil 18a is positive, current flows through transistor 102 to one side of power capacitor 24: current cannot pass through transistor 104 because the voltage on its gate keeps it closed, while transistor 106 is open; power capacitor 24 therefore receives charging current. In the other half cycle, a mirror image arrangement applies. The voltage variations are shown in Figure 3(b); the loading voltage V joacj applied to capacitor 24 is initially high, then rapidly reduces as the capacitor charges up, as shown by V- j - gj -g g . The voltage difference between the gates of transistors 104 and 108 is cyclical, and on start-up quickly reaches stability. As is well known, CMOS technology is voltage sensitive, and voltage limiting means must be introduced. The circuit therefore comprises additional transistor pairs 1 12, 1 14. and 1 18, 120. one pair being connected to each end of the coil 18a. and the transistors 1 14, 120 being also connected in common drain mode. The gates of transistors 1 12. 1 18 are supplied from a transistor of opposite type, i.e. a P channel transistor. 1 10. whose gate is supplied with a reference voltage from capacitor 24. The arrangement is such that when the voltage from coil 18a is too high for the CMOS components, transistor pairs 112, 114 or 1 18, 120, operating on opposite half cycles, short the current from the coil to the substrate, indicated as reference 1 16. The required relative magnitudes of V cnar p e , the voltage on capacitor 24. and the reference voltage V ^ e , is shown in Figure 3(c). Setting the gate voltages is critical. For operation at start-up mode. i.e. before power capacitor 24 is loaded so that no local power is available, a depletion transistor 124 is provided, connected to the gates of transistors 1 12 and 118. In one half cycle, transistor 1 12 is connected to substrate 1 16 through depletion transistor 124, and the rectifier circuit is protected. In the opposite half cycle, transistor 118 operates in similar fashion. The relative changes of the voltages and currents at various parts of the circuit are shown in Figure 3(d). The voltage on transistor 102 is initially zero, then increases to about 6 volts. The voltage V j on the gate of transistor 1 18 is initially zero, then after a delay increases to about 2 volts, so that the transistor then operates, causing the current through transistor 118 to reduce, when all current passes into the current limiting circuit and none into the capacitor 24. shown by coincidence of the drain current and the total current of 1 12; the current limiter circuit is now in full operation, while capacitor 24 (IC joacj ) holds a stable voltage V joacj , providing a stable reference voltage V re f. Figure 3(e) shows the voltages on the various transistors of the circuit, i.e. on the gates of transistors 104 and 108. the reference voltage, the voltage on the drain of 120. and on the gate of 112; the voltage on transistor 112 indicates operation of the current limiting circuit, when the voltage is sufficient to operate it. The characteristics of the various transistors will be determined by the expected voltage from the secondary coil 18a and the maximum current the CMOS circuit can tolerate. If the resistance of the secondary coil 18a is too low, an additional resistor (not shown) may be connected in series with it, and is preferably manufactured from polycrystalline silicon. Since the majority of the transistors are N-type, they may all be placed in the same silicon well, which has the advantage of maximised voltage protection. Figure 4 shows a thyristor-controlled power supply. A three phase 380v/50Hz input 50 is connected to six thyristors 52, 54, 56, 58, 60. 62 arranged as a rectifier bridge 63. The gates of the six thyristors are connected to a semiconductor chip 64 on which the full-wave rectifier and voltage limiter circuits illustrated in Figure 3a are implemented in CMOS. The chip 64 is also connected to the input 50. and to the gates of two pairs of thyristors 66,-68, 70, 72 and a further thyristor 74 which, together with a first inductance 76. form a thyristor bridge inverter 77. The bridge inverter 77 is connected across the rectifier bridge 63 through a second inductance 78. The output of the bridge inverter 77 is connected to a load 80 operating at 380 volts. Inspection of Figure 4 will show that the chip 64 is supplied directly by the three-phase input, and directly controls the gates of the thyristors. The circuit illustrated in Figure 4 can be implemented on a single hybrid without any additional power supplies or transformers, and may be used in circumstances when digital processing power is required to control a mains power or other high power supply. The application of the circuit according to the invention is not limited to either of the examples, and may be used in any CMOS chip requiring rectification and embedded over-voltage protection. It may have application also in any i.e. technology in which diodes cannot be provided.

Claims: CLAIMS 1. An integrated circuit full-wave rectifier characterised by comprising a first pair of transistors (104. 106) arranged to switch on opposing half cycles of an a.c. input signal, and a second pair of transistors (102. 108) arranged in current limiting mode and also operating on opposing half cycles of said signal. 2. An integrated circuit full-wave rectifier according to Claim 1 implemented in CMOS. 3. A full-wave rectifier according to Claim 1 characterised in that the transistors (102. 104, 106, 108) are all N channel transistors with the first pair (104, 106) having their gates connected to receive opposing half cycles of said a.c. input signal, and with the second pair (102. 108) connected in common drain mode. 4. A full-wave rectifier according to Claim 3 characterised by comprising means to provide a direct connection to a source of voltage between 40 and 1 100 volts. 5. A full-wave rectifier according to Claim 3 characterised by further comprising a voltage limiter circuit having a third pair of transistors (1 12, 1 14) and a fourth pair of transistors (118, 120) and a depletion transistor (124) arranged to connect the gates of the current limiter transistors (102. 108) to ground when the input voltage to the rectifier exceeds a predetermined level. 6. A full-wave rectifier according to Claim 5 characterised in that the third pair (112. 114) and the fourth pair (118. 120) are arranged to operate on opposing half cycles. a first transistor from each pair being connected in common drain mode, and the gates of the second transistor from each pair being supplied from a transistor (110) of opposite type, said transistor of opposite type having its gate supplied with a reference voltage. 7. A full-wave rectifier according to Claim 6 characterised in that the first, second. third and fourth pairs of transistors (104,106: 102,108: 1 12.1 14: 1 18,120) are N channel transistors and the transistor of opposite type (1 10) is a P channel transistor. 8. A passive transponder for an electronic identification system characterised by comprising:- a power antenna (18) connected to an integrated circuit full-wave rectifier comprising a first pair of transistors ( 104. 106) arranged to switch on opposing half cycles of an a.c. input signal, and a second pair of transistors (102, 108) arranged in current limiting mode and also operating on opposing half cycles of said signal; connected to the full-wave rectifier a power storage means (24) for storing power and supplying it to operate the transponder: a data receive antenna (20) and means (28) to extract a data signal from radiation impinging on said transponder; a transmit antenna (22) for transmitting a data output signal, and data storage means (62) responsive to said data signal, said data storage means supplying a response signal to the data transmit antenna (22) which response signal identifies the transponder. 9. A passive transponder according to Claim 8 characterised by further comprising a voltage limiter circuit having a third pair of transistors (1 12. 1 14) and a fourth pair of transistors (118, 120) and a depletion transistor (124) arranged to connect the gates of the current limiter transistors (102, 108) to ground when the input voltage to the rectifier exceeds a predetermined level, said voltage limiter circuit being connected to said full-wave rectifier. 10. A thyristor-controlled power supply characterised by comprising a three-phase thyristor rectifier bridge (63) connectable to a three-phase power supply (50); an integrated circuit full-wave rectifier comprising a first pair of transistors (104, 106) arranged to switch on opposing half cycles of an a.c. input signal, and a second pair of transistors (102. 108) arranged in current limiting mode and also operating on opposing half cycles of said signal, connected on an input side to said three-phase power supply (50) and on an output side to the gates of the thyristors of the rectifier bridge, the rectifier being further connected to the gates of two pairs of thyristors (66. 68. 70. 72) a further thyristor (74) and an inductance arranged as a thyristor bridge inverter (77): and means to connect the output of the thyristor bridge inverter (77) to a load (80) operable at the voltage of the three-phase power supply. 11. A thyristor-controlled power supply according to Claim 10 characterised by further comprising a voltage limiter circuit having a third pair of transistors (112, 1 14) and a fourth pair of transistors (118, 120) and a depletion transistor (124) arranged to connect the gates of the current limiter transistors ( 102, 108) to ground when the input voltage to the rectifier exceeds a predetermined level, said voltage limiter circuit being connected to said full-wave rectifier.

Inventors: SCHEELEN JOS, SCHEELEN, JOS
Applicants: BRITISH TECH GROUP INT, SCHEELEN JOS, BRITISH TECHNOLOGY GROUP INTER-CORPORATE LICENSING, SCHEELEN, JOS
Application year: 1996
Main classification: H02M7
IPC codes: G01S13, G06K19, H01L21, H01L27, H02M7, H04B1