FLEXIBLE IMPLEMENTATION OF A SYSTEM MANAGEMENT MODE (SMM) IN A PROCESSOR

Abstract: A system management mode (SMM) (900) of operating a processor (120) includes only a basic set of hardwired hooks or mechanisms in the processor for supporting SMM. Most of SMM functionality, such as the processing actions performed when entering and exiting SMM, is "soft" and freely defined. A system management interrupt (SMI) pin (960) is connected to the processor so that a signal on the SMI pin causes the processor to enter SMM mode. SMM is completely transparent to all other processor operating software. SMM handler code and data is stored in memory that is protected and hidden from normal software access.

Description: FLEXIBLE IMPLEMENTAΗON OF A SYSTEM MANAGEMENT MODE (SMM) IN A PROCESSOR TECHNICAL FIELD This invention relates to processors. More specifically, this invention relates to processors implementing a system management mode of operation. BACKGROUND ART System management mode (SMM) is a processor operating mode for performing high level systems functions such as power management or security functions. Different microprocessor manufacturers have implemented SMM systems differently so that some SMM functionality is standard or semi-standard and other functionality is very different. A pnmary constant feature in different SMM implementations is that the high level functions operating under SMM, and the underlying SMM operations, are transparent both to operating systems and application software. Another common charactenstic of vaπous SMM implementations is that SMM functionality is hardcoded into the processor integrated circuit chip and, thus, is permanently fixed. One problem with the conventional, hardcoded SMM implementation is that differences in SMM implementations by various processor manufacturers give πse to incompatibilities in functionality for processor chips that are otherwise designed for compatibility. A second problem is that the hardcoded SMM implementation may be highly advantageous for some applications, but disadvantageous for other applications. For example, a full-functionality but high overhead SMM implementation may be desired in some applications while a reduced-functionality, low overhead implementation is better suited in other applications. Another problem is that some computer system integrators wish to implement special -purpose or proprietary SMM functionality DISCLOSURE OF THE INVENTION In accordance with the present invention, a system management mode (SMM) of operating a processor includes only a basic set of hardwired hooks or mechanisms in the processor for supponing SMM Most of SMM functionality, such as the processing actions performed when entering and exiting SMM, is "soft" and freely defined. A system management interrupt (SMI) pin is connected to the processor so that a signal on the SMI pin causes the processor to enter SMM mode SMM is completely transparent to all other processor operating software. SMM handler code and data is stored in memory that is protected and hidden from normal software access. An embodiment of a RISC superscalar processor havmg a conventional hardwired system management mode (SMM) functionality, including SMM entry and exit processing and other nonconventional x86 instnictions that support SMM software, is implemented in on-chip ROM resident RISC operation sequences. This hardwired implementation of SMM requires exact definition of SMM functionality to satisfy system requirements for multiple various vendors of computer systems which incoφorate the RISC superscalar processor. An embodiment of a RISC superscalar processor in accordance with the present invention instead fetches SMM RISC operation sequences, when needed, from an external memory. In one embodiment, the SMM RISC operation sequences are stored in an area of address space where system BIOS resides (addresses EOOOO-FFFFF). As a result, each system vendor of multiple vendors can freely define much of the SMM functionality exactly as desired. For example, SMM entry and the associated state saving performed by the processor can be streamlined or extended, as desired. In accordance with the present invention, system management mode is a "soft" implementation, having a definition in external RISC instruction code residing within BIOS. In this soft implementation, nearly all aspects of SMM are freely defined. A separate SMM entry slot is reserved for each SMM entry mechanism. Exit from SMM is furnished by a special "SMM exit" instruction. I/O trap filtering and checking are also defined. Furthermore, additional x86 SMM support instructions are defined, including instructions to save and restore segment descπptors. In accordance with a first embodiment of the present invention, a computer system for operating in a system management mode (SMM) includes a processor having an instruction decoder, means connected to the processor for activating a system management activation signal and an instruction memory connected to the processor for supplying instructions to the processor. The instruction memory stores a software program including an SMM initialization routine, a routine for redirecting SMM operations to an external memory and an SMM termination routine. In accordance with a second embodiment of the present invention, a computer system includes a processor and a memory connected to the processor. The memory includes a BIOS area of memory address space. A method of operating a computer system in a system management mode (SMM) includes the steps of receiving an SMM activating signal, recognizing the received SMM activating signal, initializing a SMM entry sequence by vectoring to a RISC instruction in a BIOS area of the memory address space, initializing the SMM, redirecting SMM operations to an external memory and terminating the SMM. Several advantages are achieved by the descnbed invention One advantage is that the system management mode (SMM) operation is transparent to the operation of all other software so that other software operates identically whether SMM is active or inactive. Similarly. SMM operation is transparent to the operation of all normal CPU operating modes. Another advantage is that the functional definition of SMM is fully-defined, and therefore modifiable, by operating software. These advantages are attained while system management interrupts (SMI) and I/O access trapping are fully suppoπed and SMM may be implemented to be compatible with conventional SMM operation. BRIEF DESCRIPTION OF THE DRAWINGS The features of the invention believed to be novel are specifically set foπh in the appended claims. However, the invention itself, both as to its structure and method of operation, may best be understood by referring to the following description and accompanying drawings. Figure 1 is a block diagram which illustrates a computer system in accordance with one embodiment of the present invention. Figure 2 is a block diagram illustrating one embodiment of processor for usage in the computer system shown in Figure 1. Figure 3 is a timing diagram which illustrates pipeline timing for an embodiment of the processor shown in Figure 2. Figure 4 is a schematic block diagram showing an embodiment of an instruction decoder used in the processor shown in Figure 2. Figure 5 is a schematic block diagram which depicts a stmcture of an emulation code sequencer and an emulation code memory of the instmction decoder shown in Figure 4. Figures 6A through 6E are pictorial illustrations showing a plurality of operation (Op) formats generated by the instmction decoder shown in Figure 4. Figure 7 is a pictorial depiction of an OpSeq field format employed in the emulation code memory shown in Figure 5. Figure 8 is a memory map which illustrates processor memory assignments including assignment of a separate system management RAM (SMRAM) area. Figure 9 is a flowchaπ which illustrates system management mode (SMM) functionality. Figure 10 is a schematic block diagram which illustrates various SMM stmctures implemented in processor circuits. Figure 11 is a block diagram of a personal computer incoφorating a processor having an instmction decoder which implements an adaptable system management mode (SMM) in accordance with an embodiment of the present invention. MODE(S) FOR CARRYING OUT THE INVENTION Referring to Figure 1, a computer system 100 is used in a variety of applications, including a personal computer application. The computer system 100 includes a computer motherboard 110 containing a processor 120 in accordance with an embodiment of the invention. Processor 120 is a monolithic integrated circuit which executes a complex instmction set so that the processor 120 may be termed a complex instmction set computer (CISC). Examples of complex instmction sets are the x86 instmction sets implemented on the well known 8086 family of microprocessors. The processor 120 is connected to a level 2 (L2) cache 122, a memory controller 124 and local bus controllers 126 and 128. The memory controller 124 is connected to a main memory 130 so that the memory controller 124 forms an interface between the processor 120 and the main memory 130. The local bus controllers 126 and 128 are connected to buses including a PCI bus 132 and an ISA bus 134 so that the local bus controllers 126 and 128 form interfaces between the PCI bus 132 and the ISA bus 134. Referring to Figure 2. a block diagram of an embodiment of processor 120 is shown. The core of the processor 120 is a RISC superscalar processing engine. Common x86 instmctions are convened by instmction decode hardware to operations in an intemal RISC instmction set. Other x86 instmctions, exception processing, and other miscellaneous functionality is implemented as RISC operation sequences stored in on-chip ROM. Processor 120 has interfaces including a system interface 210 and an L2 cache control logic 212. The system interface 210 connects the processor 120 to other blocks of the computer system 100. The processor 120 accesses the address space of the computer system 100, including the main memory 130 and devices on local buses 132 and 134 by read and write accesses via the system interface 210. The L2 cache control logic 212 forms an interface between an extemal cache, such as the L2 cache 122, and the processor 120. Specifically, the L2 cache control logic 212 interfaces the L2 cache 122 and to an instmction cache 214 and a data cache 216 in the processor 120. The instmction cache 214 and the data cache 216 are level 1 (Ll) caches which are connected through the L2 cache 122 to the address space of the computer system 100. Instmctions from main memory 130 are loaded into instmction cache 214 via a predecoder 270 for anticipated execution. The predecoder 270 generates predecode bits that are stored in combination with instmction bits in the instmction cache 214. The predecode bits, for example 3 bits, are fetched along with an associated instmction byte (8 bits) and used to facilitate multiple instmction decoding and reduce decode time. Instmction bytes are loaded into instmction cache 214 thirty-two bytes at a time as a burst transfer of four eight- byte quantities. Logic of the predecoder 270 is replicated eight times for usage four times in a cache line so that predecode bits for all eight instmction bytes are calculated simultaneously immediately before being written into the instmction cache 214. A predecode operation on a byte typically is based on information in one, two or three bytes so that predecode information may extend beyond an eight-byte group Accordingly, the latter two bytes of an eight-byte group are saved for processing with the next eight-byte group in case of predecode information that overlaps two eight-byte groups. Instmctions in instmction cache 214 are CISC instmctions, referred to as macroinstmctions. An instmction decoder 220 converts CISC instmctions from instmction cache 214 into operations of a reduced instmction set computing (RISC) architecture instmction set for execution on an execution engine 222. A single macroinstmction from instmction cache 214 decodes into one or multiple operations for execution engine 222. Instmction decoder 220 has interface connections to the instmction cache 214 and an instmction fetch control circuit 218 (shown in Figure 4) Instmction decoder 220 includes a macroinstmction decoder 230 for decoding most macroinstmctions, an instmction decoder emulation circuit 231 including an emulation ROM 232 for decoding a subset of instmctions such as complex instmctions. and a branch unit 234 for branch prediction and handling. Macroinstmctions are classified according to the general type of operations into which the macroinstmctions are convened. The general types of operations are register operations (RegOps), load -store operations (LdStOps), load immediate value operations (LIMMOps), special operations (SpecOps) and floating point operations (FpOps). Execution engine 222 has a scheduler 260 and six execution units including a load unit 240. a store unit 242. a first register unit 244. a second register unit 246. a floating point unit 248 and a multimedia unit 250 The scheduler 260 distributes operations to appropnate execution units and the execution units operate in parallel . Each execution unit executes a panicuiar type of operation In pamcular, the load unit 240 and the store unit 242 respectively load (read) data or store (wπte) data to the data cache 216 (Ll data cache), the L2 cache 122 and the ma memory 130 while executing a load/store operation (LdStOp). A store queue 262 temporanly stores data from store unit 242 so that store unit 242 and load unit 240 operate in parallel without conflicting accesses to data cache 216. Register umts 244 and 246 execute register operations (RegOps) for accessing a register file 290. Floating point unit 248 executes floating point operations (FpOps). Multimedia unit 250 executes arithmetic operations for multimedia applications. Scheduler 260 is partitioned into a plurality of, for example, 24 entries where each entry contains storage and logic. The 24 entnes are grouped into six groups of four entnes, called Op quads. Infoπnation in the storage of an entry describes an operation for execution, whether or not the execution is pending or completed. The scheduler monitors the entnes and dispatches information from the entπes to information- designated execution units. Referπng to Figure 3. processor 120 employs five and six stage basic pipeline timing. Instmction decoder 220 decodes two instmctions in a single clock cycle. Dunng a first stage 310, the instmction fetch control circuit 218 fetches CISC mstmctions into instmction cache 214. Predecoding of the CISC instmctions dunng stage 310 reduces subsequent decode time. During a second stage 320, mstmction decoder 220 decodes instmctions from mstmction cache 214 and loads an Op quad mto scheduler 260. Durmg a third stage 330, scheduler 260 scans the entnes and issues operations to conespondmg execution units 240 to 252 if an operation for the respective types of execution units is available. Operands for the operations issued dunng stage 330 are forwarded to the execution units in a fourth stage 340 For a RegOp, the operation generally completes in the next clock cycle which is stage 350, but LdStOps require more time for address calculation 352, data access and transfer of the results 362 For branch operations, stmction decoder 220 perfoπns a branch prediction 324 dunng an initial decoding of a branch operation A branch unit 252 evaluates conditions for the branch at a later stage 364 to determine whether the branch prediction 324 was correct A two level branch prediction algorithm predicts a direction of conditional branching, and fetching CISC instmctions in stage 310 and decoding the CISC instmctions in stage 320 continues in the predicted branch direction Scheduler 260 determines when all condition codes required for branch evaluation are valid, and directs the branch umt 252 to evaluate the branch instmction If a branch was incoπectly predicted, operations in the scheduler 260 which should not be executed are flushed and decoder 220 begins loadmg new Op quads from the correct address after the branch A time penalty is incurred as instmctions for the conect branching are fetched Instmction decoder 220 either reads a previously-stored predicted address or calculates an address using a set of parallel adders If a previously- predicted address is stored, the predicted address is fetched in stage 326 and instmctions located at the predicted address are fetched in stage 328 without a delay for adders Otherwise, parallel adders calculate the predicted address. In branch evaluation stage 364, branch unit 252 determines whether the predicted branch direction is correct If a predicted branch is correct, the fetching, decoding, and instruction-executing steps continue without interruption For an inconect prediction, scheduler 260 is flushed and instmction decoder 220 begins decoding macroinstmctions from the conect program counter subsequent to the branch Refemng to Figure 4. a schematic block diagram illustrates an embodiment of an instmction preparation circuit 400 which is connected to the main memory 130 The mstmction preparation circuit 400 mcludes the instmction cache 214 that is connected to the main memory 130 via the predecoder 270 The mstmction decoder 220 is connected to receive instmction bytes and predecode bits from three alternative sources, the instmction cache 214, a branch target buffer (BTB) 456 and an mstmction buffer 408. The instmction bytes and predecode bits are supplied to the mstmction decoder 220 through a plurality of rotators 430, 432 and 434 via instmction registers 450. 452 and 454 The macroinstmction decoder 230 has input connections to the instmction cache 214 and mstmction fetch control circuit 218 for receivmg instmction bytes and associated predecode information. The macroinstruction decoder 230 buffers fetched mstmction bytes m an instruction buffer 408 connected to the mstmction fetch control circuit 218 The mstmction buffer 408 is a sixteen byte buffer which receives and buffers up to 16 bytes or four aligned words from the mstmction cache 214, loading as much data as allowed by the amount of free space in the instmction buffer 408. The instmction buffer 408 holds the next instmction bytes to be decoded and contmuously reloads with new mstmction bytes as old ones are processed by the macroinstmction decoder 230. Instmctions both the instmction cache 214 and the mstmction buffer 408 are held in "extended" bytes, containmg both memory bits (8) and predecode bits (5), and are held in the same alignment. The predecode bits assist the macroinstmction decoder 230 to perform multiple instmction decodes within a single clock cycle Instmction bytes addressed using a decode program counter (PC) 420, 422. or 424 are transfeπed from the mstmction buffer 408 to the macroinstmction decoder 230. The instmction buffer 408 is accessed on a byte basis by decoders in the macroinstmction decoder 230. However on each decode cycle, the instmction buffer 408 is managed on a word basis for tracking which of the bytes in the mstmction buffer 408 are valid and which are to be reloaded with new bytes from the mstmction cache 214 The designation of whether an mstmction byte is valid is maintained as the mstmction byte is decoded. For an invalid instmction byte, decoder invalidation logic (not shown), which is connected to the macroinstmction decoder 230, sets a "byte invalid" signal. Control of updating of the cuπent fetch PC 426 is synchronized closely with the validity of instmction bytes in the mstmction buffer 408 and the consumption of the instmction bytes by the mstmction decoder 220. The macroinstmction decoder 230 receives up to sixteen bytes or four aligned words of instmction bytes fetched from the mstmction fetch control circuit 218 at the end of a fetch cycle. Instmction bytes from the mstmction cache 214 are loaded into a 16-byte mstmction buffer 408. The mstmction buffer 408 buffers mstmction bytes, plus predecode information associated with each of the mstmction bytes, as the instmction bytes are fetched and/or decoded. The instmction buffer 408 receives as many instmction bytes as can be accommodated by the instmction buffer 408 free space, holds the next instmction bytes to be decoded and continually reloads with new instmction bytes as previous instruction bytes are transfened to individual decoders withm the macroinstmction decoder 230 The mstmction predecoder 270 adds predecode information bits to the instruction bytes as the mstmction bytes are transferred to the instruction cache 214 Therefore, the instmction bytes stored and transfeπed by the instmction cache 214 are called extended bytes. Each extended byte mcludes eight memory bits plus five predecode bits. The five predecode bits include three bits that encode instmction length, one D-bit that designates whether the instruction length is D-bit dependent, and a HasModRM bit that mdicates whether an instmction code includes a modrm field The thmeen bits are stored in the instmction buffer 408 and passed on to the macroinstmction decoder 230 decoders The instmction buffer 408 expands each set of five predecode bits into six predecode bits. Predecode bits enable the decoders to quickly perform multiple mstmction decodes with one clock cycle. The instmction buffer 408 receives mstmction bytes from the mstmction cache 214 in the memory- aligned word basis of instmction cache 214 storage so that instmctions are loaded and replaced with word granulanty. Thus, the mstmction buffer 408 byte location 0 always holds bytes that are addressed in memory at an address of 0 (mod 16). Instmction bytes are transfeπed from the instmction buffer 408 to the macroinstmction decoder 230 with byte granulanty. Dunng each decode cycle, the sixteen extended mstmction bytes within the mstmction buffer 408 , mcluding associated implicit word valid bits, are transfeπed to the plurality of decoders withm the macroinstmction decoder 230. This method of transfernng instmction bytes from the instmction cache 214 to the macroinstmction decoder 230 via the mstmction buffer 408 is repeated with each decode cycle as long as instmctions are sequentially decoded. When a control transfer occurs, for example due to a taken branch operation, the mstmction buffer 408 is flushed and the method is restarted. The cuπent decode PC has an arbitrary byte alignment in that the instruction buffer 408 has a capacity of sixteen bytes but is managed on a four-byte word basis in which all four bytes of a word are consumed before removal and replacement or the word with four new oytes in the instmction buffer 408. An mstmction has a length of one to eleven bytes and multiple bytes are decoded so that the alignment of an instmction in the mstmction buffer 408 is arbitrary. As stmction bytes are transfened from the instmction buffer 408 to the macroinstmction decoder 230, the instmction buffer 408 is reloaded from the instmction cache 214 Instmction bytes are stored in the mstmction buffer 408 with memory alignment rather than a sequential byte alignment that is suitable for application of consecutive mstmction bytes to the macroinstmction decoder 230 Therefore, a set of byte rotators 430. 432 and 434 are inteφosed between the instmction buffer 408 and each of the decoders of the macroinstmction decoder 230. Four instmction decoders, including three short decoders SDecO 410, SDecl 412 or SDec2 414, and one combined long and vectonng decoder 418, share the byte rotators 430, 432 and 434. In particular, the short decoder SDecO 410 and the combined long and vectonng decoder 418 share byte rotator 430. Short decoder SDecl 412 is associated with byte rotator 432 and short decoder SDec2 414 is associated with byte rotator 434. A plurality of pipeline registers, specifically instmction registers 450, 452 and 454, are inteφosed between the byte rotators 430, 432 and 434 and the mstmction decoder 220 to temporanly hold the mstmction bytes, predecode bits and other information, thereby shortening the decode timing cycle. The other information held in the instmction registers 450. 452 and 454 includes vanous infoπnation for assisting instmction decoding, including prefix (e.g OF) status, immediate size (8-bιt or 32-bit), displacement and long decodable length designations Although a circuit is shown utilizing three rotators and three short decoders, in other embodiments, different numbers of circuit elements may be employed. For example, one circuit includes two rotators and two short decoders. Instmctions are stored in memory alignment, not mstmction alignment, in the mstmction cache 214, the branch target buffer (BTB) 456 and the instmction buffer 408 so that the location of the first instmction byte is not known. The byte rotators 430, 432 and 434 find the first byte of an instmction. The macroinstmction decoder 230 also performs vaπous instmction decode and exception decode operations, including validation of decode operations and selection between different types of decode operations. Functions performed during decode operations include prefix byte handling, suppoπ for vectoring to the emulation code ROM 232 for emulation of instmctions, and for branch unit 234 operations, branch unit interfacing and return address prediction. Based on the instruction bytes and associated information, the macroinstmction decoder 230 generates operation information in groups of four operations correspondmg to Op quads. The macroinstmction decoder 230 also generates instmction vectonng control information and emulation code control information. The macroinstmction decoder 230 also has output connections to the scheduler 260 and to the emulation ROM 232 for outputting the Op quad information, stmction vectoring control information and emulation code control information. The macroinstmction decoder 230 does not decode instmctions when the scheduler 260 is unable to accept Op quads or is accepting Op quads from emulation code ROM 232. The macroinstmction decoder 230 has five distinct and separate decoders, including three "short" decoders SDecO 410, SDecl 412 and SDec2 414 that function in combination to decode up to three "shon" decode operations of instmctions that are defined within a subset of simple instmctions of the x86 instmction set. Generally, a simple instmction is an instmction that translates to fewer than three operations. The short decoders SDecO 410, SDecl 412 and SDec2 414 each typically generate one or two operations, although zero operations are generated in certain cases such as prefix decodes. Accordingly for three short decode operations, from two to six operations are generated in one decode cycle. The two to six operations from the three short decoders are subsequently packed together by operation packing logic 438 into an Op quad since a maximum of four of the six operations are valid. Specifically, the three short decoders SDecO 410, SDecl 412 and SDec2 414 each attempt to decode two operations, potentially generating six operations. Only four operations may be produced at one time so that if more than four operations are produced, the operations from the short decoder SDec2 414 are invalidated. The five decoders also include a single "long" decoder 416 and a single "vectoring" decoder 418. The long decoder 416 decodes instmctions or forms of instmctions having a more complex address mode form so that more than two operations are generated and short decode handling is not available. The vectoring decoder 418 handles instmctions that cannot be handled by operation of the short decoders SDecO 410. SDecl 412 and SDec2 414 or by the long decoder 416. The vectoring decoder 418 does not actually decode an instmction, but rather vectors to a location of emulation ROM 232 for emulation of the instmction. Various exception conditions that are detected by the macroinstmction decoder 230 are also handled as a special form of vectoring decode operation. When activated, the long decoder 416 and the vectoring decoder 418 each generates a full Op quad. An Op quad generated by short decoders SDecO 410, SDecl 412 and SDec2 414 has the same format as an Op quad generated by the long and vectoring decoders 416 and 418. The short decoder and long decoder Op quads do not include an OpSeq field. The macroinstmction decoder 230 selects either the Op quad generated by the short decoders 410. 412 and 414 or the Op quad generated by the long decoder 416 or vectoring decoder 418 as an Op quad result of the macroinstmction decoder 230 are each decode cycle. Short decoder operation, long decoder operation and vectoring decoder operation function in parallel and independently of one another, although the results of only one decoder are used at one time. Each of the short decoders 410, 412 and 414 decodes up to seven instmction bytes, assuming the first byte to be an operation code (opcode) byte and the instmction to be a short decode instmction. Two operations (Ops) are generated with coπesponding valid bits. Appropriate values for effective address size, effective data size, the cuπent x86-standard B-bit, and any override operand segment register are supplied for the generation of operations dependent on these parameters. The logical address of the next "sequential" instmction to be decoded is supplied for use in generating the operations for a CALL instmction. Note that the word sequential is placed in quotation marks to indicate that, although the "sequential" address generally points to an instmction which immediately precedes the present instmction, the "sequential" address may be set to any addressed location. The current branch prediction is supplied for use in generating the operations for conditional transfer control instmctions. A short decode generates control signals including indications of a transfer control instmction (for example, Jcc, LOOP, JMP, CALL), an unconditional transfer control instmction (for example, JMP, CALL), a CALL instmction, a prefix byte, a cc-dependent RegOp, and a designation of whether the instmction length is address or data size dependent. Typically one or both operations are valid, but prefix byte and JMP decodes do not generate a valid op. Invalid operations appear as valid NOOP operations to pad an Op quad. The first short decoder 410 generates operations based on more than decoding of the instmction bytes. The first short decoder 410 also determines the presence of any prefix bytes decoded during preceding decode cycles. Various prefix bytes include OF, address size override, operand size oveπide, six segment oveπide bytes, REP/REPE, REPNE and LOCK bytes. Each prefix byte affects a subsequent instmction decode in a defined way. A count of prefix bytes and a count of consecutive prefix bytes are accumulated during decoding and furnished to the first short decoder SDecO 410 and the long decoder 416. The consecutive prefix byte count is used to check whether an instmction being decoded is too long. Prefix byte count information is also used to control subsequent decode cycles, including checking for certain types of instmction-specific exception conditions. Prefix counts are reset or initialized at the end of each successful non-prefix decode cycle in preparation for decoding the prefix and opcode bytes of a next instmction. Prefix counts are also reinitialized when the macroinstmction decoder 230 decodes branch condition and write instmction pointer (WRIP) operations. Prefix bytes are processed by the first short decoder 410 in the manner of one-byte short decode instmctions. At most, one prefix byte is decoded in a decode cycle, a condition that is enforced through invalidation of all short decodes following the decode of a prefix byte. Effective address size, data size, operand segment register values, and the cuπent B-bit, are supplied to the first short decoder 410 but can decode along with preceding opcodes. T e address size prefix affects a decode of a subsequent instmction both for decoding of instmctions for which the generated operation depends on effective address size and for decoding of the address mode and instmction length of modr/m instmctions. The default address size is specified by a cuπently-specified D-bit, which is effectively toggled by the occurrence of one or more address size prefixes. The operand size prefix also affects the decode of a subsequent instmction both for decoding of instmctions for which the generated operation depends on effective data size and for decoding of the instmction lengm. The default operand size is specified by a cuπently-specified x86-standard D-bit. which is effectively toggled by the occuπence of one or more operand size prefixes. The segment override prefixes affect the decode of a subsequent instmction only in a case when the generation of a load-store operation (LdStOps) is dependent on the effective operand segment of the instmction. The default segment is DS or SS, depending on the associated general address mode, and is replaced by the segment specified by the last segment override prefix. The REP/REPE and REPNE prefixes do not affect the decode of a subsequent instmction. If the instmction is decoded by the macroinstmction decoder 230, rather than the emulation code ROM 232, then any preceding REP prefixes are ignored. However, if the instmction is vectored, then the generation of the vector address is modified in some cases. Specifically, if a string instmction or particular neighboring opcode is vectored, then an indication of the occurrence of one or more of the REP prefixes and designation of the last REP prefix encountered are included in the vector address. For all other instmctions the vector address is not modified and the REP prefix is ignored. A LOCK prefix inhibits all short and long decoding except the decoding of prefix bytes, forcing the subsequent instmction to be vectored. When the vector decode cycle of this subsequent instmction occurs, so long as the subsequent instmction is not a prefix, the opcode byte is checked to ensure that the instmction is within a "lockable" subset of the instmctions. If the instmction is not a lockable instmction, an exception condition is recognized and the vector address generated by the vectoring decoder 418 is replaced by an exception entry point address. Instmctions decoded by the second and third short decoders 412 and 414 do not have prefix bytes so that decoders 412 and 414 assume fixed default values for address size, data size, and operand segment register values. Typically, the three short decoders generate four or fewer operations because three consecutive short decodes are not always performed and instmctions often short decode into only a single operation. However, for the rare occunence when more than four valid operations are generated, operation packing logic 438 inhibits or invalidates the third short decoder 414 so that only two instmctions are successfully decoded and at most four operations are generated for packing into an Op quad. When the first short decoder 410 is unsuccessful, the action of the second and third short decoders 412 and 414 are invalidated. When the second short decoder 412 is unsuccessful, the action of the third short decoder 414 is invalidated. When even the first short decode is invalid, the decode cycle becomes a long or vectoring decode cycle. In general, the macroinstmction decoder 230 attempts one or more short decodes and, if such short decodes are unsuccessful, attempts one long decode. If the long decode is unsuccessful, the macroinstmction decoder 230 performs a vectoring decode. Multiple conditions cause the short decoders 410, 412 and 414 to be invalidated. Most generally, short decodes are invalidated when the instmction operation code (opcode) or the designated address mode of a modr/m instmction does not fall within a defined short decode or "simple" subset of instmctions. This condition typically restricts short decode instmctions to those operations that generate two or fewer operations. Short decodes are also invalidated when not all of the bytes in the instmction buffer 408 for a decoded instmction are valid. Also, "cc -dependent" operations, operations that are dependent on status flags, are only generated by the first short decoder 410 to ensure that these operations are not preceded by and " .cc" RegOps. A shoπ decode is invalidated for a second of two consecutive short decodes when the immediately preceding short decode was a decode of a transfer control instmction, regardless of the direction taken. A short decode is invalidated for a second of two consecutive short decodes when the first shoπ decode was a decode of a prefix byte. In general, a prefix code or a transfer control code inhibits further decodes in a cycle. Furthermore, no more than sixteen instmction bytes are consumed by the macroinstmction decoder 230 since the instmction buffer 408 only holds sixteen bytes at one time. Also, at most four operations can be packed into an Op quad. These constraints only affect the third short decoder 414 since the length of each short decoded instmction is at most seven bytes and operations in excess of four only arise in the third short decoder 414. In a related constraint, if the cuπent D-bit value specifies a 16-bit address and data size default, then an instmction having a length that is address and/or data dependent can only be handled by the first short decoder 410 since the predecode information is probably incoπect. Also, when multiple instmction decoding is disabled, only the first short decoder 410 is allowed to successfully decode instmctions and prefix bytes. Validation tests are controlled by short decoder validation logic (not shown) in the macroinstmction decoder 230 and are independent of the operation of short decoders 410. 412 and 414. However, each of the short decoders 410, 412 and 414 does set zero, one or two valid bits dependmg on the number of operations decoded These valid bits, a total of six for the three short decoders 410. 412 and 414, are used by the operation packing logic 438 to determine which operations to pack into an Op quad and to force invalid operations to appear as NOOP (no operation) operations The operation packing logic 438 operates without shoπ decoder validation information smce valid short decodes and associated operations are preceded only by other valid short decodes and associated operations The short decoders 410, 412 and 414 also generate a plurality of signals representing vanous special opcode or modr/m address mode decodes These signals indicate whether a certain form of instmction is cuπently bemg decoded by the mstmction decoder 220 These signals are used by short decode validation logic to handle shoπ decode validation situations The instmction bytes, which are stored unaligned in the instmction buffer 408, are aligned by byte rotators 430, 432 and 434 as the instmction bytes are transfeπed to the decoders 410-418 The first shoπ decoder SDecO 410. the long decoder 416 and the vectoring decoder 418 share a first byte rotator 430 The second and third shoπ decoders SDecl 412 and SDec2 414 use respective second and third byte rotators 432 and 434 During each decode cycle, the three shoπ decoders SDecO 410. SDecl 412 and SDec2 414 attempt to decode what are. most efficiently, three shoπ decode operations using three independently-operating and parallel byte rotators 430, 432 and 434 Although the multiplexing by the byte rotators 430. 432 and 434 of appropriate bytes in the instmction buffer 408 to each respective decoder SDecO 410, SDecl 412 and SDec2 414 is conceptually dependent on the preceding instmction decode operation, instmction length lookahead logic 436 uses the predecode bits to enable the decoders to operate substantially in parallel The long and vectonng decoders 416 and 418, in combination, perform two parallel decodes of eleven instmction bytes, taking the first byte to be an opcode byte and generating either a long instmction decode Op quad or a vectonng decode Op quad Infoπnation analyzed by the long and vectonng decoders 416 and 418 includes effective address size, effective data size, the cuπent B-bit and DF-bit, any oveπide operand segment register, and logical addresses of the next sequential and target instmctions to be decoded The long and vectonng decoders 416 and 418 generate decode signals including an instmction length excluding preceding prefix bits, a designation of whether the instmction is within the long decode subset of instmctions, a RET instmction, and an effective operand segment register, based on a default implied by the modr/m address mode plus any segment oveπide Dunng a decode cycle in which none of the shoπ decoders SDecO 410, SDecl 412 and SDec2 414 successfully decodes a short instmction, the macroinstmction decoder 230 attempts to perform a long decode usmg the long decoder 416 If a long decode cannot be performed, a vectoring decode is performed In some embodiments, the long and vectonng decoders 416 and 418 are conceptually separate and mdependent decoders, just as the long and vectonng decoders 416 and 418 are separate and independent of the short decoders 410, 412 and 414 Physically, however, the long and vectonng decoders 416 and 418 share much logic and generate similar Op quad outputs Instmctions decoded by the long decoder 416 are generally included withm the short decode subset of instmctions except for an address mode constraint such as that the instmction cannot be decoded by a short decoder because the instmction length is greater than seven bytes or because the address has a large displacement that would require generation of a third operation to handle to displacement The long decoder 416 also decodes certam additional modr/m instmctions that are not in the shoπ decode subset but are sufficiently common to waπant hardware decodmg. Instmction bytes for usage or decodmg by the long decoder 416 are supplied from the instmction buffer 408 by the first byte rotator 430, the same mstmction multiplexer that supplies mstmction bytes to the first short decoder SDecO 410 However, while the first short decoder SDecO 410 receives only seven bytes, the long decoder 416 receives up to eleven consecutive instmction bytes, coπesponding to the maximum length of a modr/m instmction excluding prefix bytes Thus, the first byte rotator 430 is eleven bytes wide although only the first seven bytes are connected to the first short decoder SDecO 410 The long decoder 416 only decodes one instmction at a time so that associated predecode information within the instmction buffer 408 is not used and is typically invalid The first byte of the first byte rotator 430 is fully decoded as an opcode byte and, m the case of a modr/m instmction, the second mstmction byte and possibly the third are fully decoded as modr/m and sib bytes, respectively The existence of a OF prefix is considered in decoding of the opcode byte The OF prefix byte inhibits all short decodmg smce all shoπ decode instmctions are non-OF or "one-byte opcodes Because all prefix bytes are located within the "one-byte" opcode space, decoding of a OF prefix forces the next decode cycle to be a two- byte opcode instmction, such as a long or vectonng decode mstmction In addition to generating operations based on the decodmg of modr/m and sib bytes, the first byte rotator 430 also determines the length of the mstmction for usage by vanous program counters, whether the instmction is a modr/m instmction for inhibiting or invalidating the long decoder, and whether the mstmction is an instmction within the long decode subset of operation codes (opcodes). The long decoder 416 always generates four operations and, like the shoπ decoders 410, 412 and 141, presents the operations m the foπn of an emulation code-like Op quad, excluding an OpSeq field The long decoder 416 handles only relatively simple modr/m instmctions A long decode Op quad has two possible forms that differ only in whether the third operation is a load operation (LdOp) or a store operation (StOp) and whether the fourth operation is a RegOp or a NOOP A first long decode Op quad has the form LIMM t2, < ιmm32 > LIMM tl , <dιsp32 > LD b/d t8L/t8.@( < gam > )OS a < RegOp > A second long decode Op quad has the form LIMM t2, < ιmm32 > LIMM tl , <dιsp32 > ST b/d @( <gam> ),t2L/t2,OS a NOOP The @( <gam >) address mode specification represents an address calculation coπesponding to that specified by the modr/m and/or sib bytes of the instmction. for example @(AX + BX*4 + LD) The < ιmm32 > and <dιsp32 > values are four byte values contammg the immediate and displacement instmction bytes when the decoded instruction contains such values The long decoder 416, like the first short decoder 410, generates operations taking into account the presence of any prefix bytes decoded by the short decoders dunng preceding decode cycles Effective address size. data size, operand segment register values, and the cuπent B-bit are supplied to the long decoder 416 and are used to generate operations No indirect size or segment register specifiers are included withm the final operations generated by the long decoder 416 Only a few conditions inhibit or invalidate an otherwise successful long decode. One such condition is an instruction operation code (opcode) that is not included in the long decode subset of instmctions. A second condition is that not all of the instmction buffer 408 bytes for the decoded instmction are valid. The vectoring decoder 418 handles instructions that are not decoded by either the short decoders or the long decoder 416. Vectoring decodes are a default case when no shoπ or long decoding is possible and sufficient valid bytes are available. Typically, the instmctions handled by the vectoring decoder 418 are not included in the short decode or long decode subsets but also result from other conditions such as decoding being disabled or the detection of an exception condition. During normal operation, only non-shoπ and non-long instmctions are vectored. However, all instmctions may be vectored. Undefined opcodes are always vectored. Only prefix bytes are always decoded. Prefix bytes are always decoded by the shoπ decoders 410, 412 and 414. When an exception condition is detected during a decode cycle, a vectoring decode is forced, generally overriding any other form of decode without regard for instmction byte validity of the decoded instmction. When a detected exception condition forces a vectoring decode cycle, the generated Op quad is undefined and the Op quad valid bit for presentation to the scheduler 260 is forced to zero. The Op quad valid bit informs the scheduler 260 that no operations are to be loaded to the scheduler 260. As a result, no Op quad is loaded into the scheduler 260 during an exception vectoring decode cycle. Few conditions inhibit or invalidate a vectoring decode. One such condition is that not all of the bytes in the instmction buffer 408 are valid. When an instmction is vectored, control is transfened to an emulation code entry point. An emulation code entry point is either in intemal emulation code ROM 232 or in extemal emulation code RAM 236. The emulation code starting from the entry point address either emulates an instmction or initiates appropriate exception processing. A vectoring decode cycle is properly considered a macroinstmction decoder 230 decode cycle. In the case of a vectoring decode, the macroinstmction decoder 230 generate the vectonng quad and generate the emulation code address into the emulation code ROM 232. Following the initial vectonng decode cycle, the macroinstmction decoder 230 remains inactive while instmctions arc generated by the emulation code ROM 232 or emulation code RAM 236 until a retum from emulation (ERET) OpSeq is encountered. The retum from emulation (ERET) sequencing action transitions back to macroinstmction decoder 230 decoding. During the decode cycles following the initial vectoring decode cycle, the macroinstmction decoder 230 remains inactive, continually attempting to decode the next "sequential" instmction but having decode cycles repeatedly invalidated until after the ERET is encountered, thus waiting by default to decode the next "sequential" instmction. Instruction bytes for usage or decoding by the vectoring decoder 418 are supplied from the instmction buffer 408 by the first byte rotator 430, the same instmction multiplexer that supplies instmction bytes to the first shoπ decoder SDecO 410 and to the long decoder 416. The vectonng decoder 418 receives up to eleven consecutive instmction bytes, coπesponding to the maximum length of a modr/m instmction excluding prefix bytes. Thus, the full eleven byte width of the first byte rotator 430 is distributed to both the long decoder 416 and the vectoring decoder 418. The predecode information within the instmction buffer 408 is not used by the vectoring decoder 418. As in the case of the long decoder 416, the first byte of the first byte rotator 430 is fully decoded as an opcode byte and, in the case of a modr/m instmction, the second instmction byte and possibly the third are fully decoded as modr/m and sib bytes, respectively. The vectoring decoder 418 generates operations taking into account the presence of any prefix bytes decoded by the shoπ decoders dunng preceding decode cycles The existence of a OF prefix is considered in decoding of the opcode byte In addition to generating operations based on the decodmg of modr/m and sib bytes, the first byte rotator 430 also determines the length of the mstmction for usage by vaπous program counters, whether the mstmction is a modr/m mstmction for inhibiting or invalidating the long decoder, and whether the instmction is an mstmction withm the long decode subset of operation codes (opcodes) If not, a vectoring decode is initiated Effective address size, data size and operand segment register values are supplied to the vectoring decoder 418 and are used to generate operations No indirect size or segment register specifiers are included wiϋiin the final operations generated by the vectonng decoder 418 Dunng a vectonng decode cycle, the vectonng decoder 418 generates a vectonng Op quad, generates an emulation code entry point or vector address, and mitializes an emulation environment The vectonng Op quad is specified to pass vaπous infoπnation to initialize emulation environment scratch registers The value of the emulation code entry point or vector address is based on a decode of the first and second mstmction bytes, for example the opcode and modr/m bytes, plus other information such as the presence of an OF prefix, a REP prefix or the like In the case of vectoring caused by an exception condition, the entry point or vector address is based on a simple encoded exception identifier The emulation environment is stored for resolving environment dependencies All of the shoπ decoders 410, 412 and 414 and long decoder 416 directly resolve environmental dependencies, such as dependencies upon effective address and data sizes, as operations are generated so that these operations never contain indirect size or register specifiers However, emulation code operations do refer to such effective address and data size values for a panicuiar instance of the mstmction being emulated The emulation environment is used to store this additional information relating to the particular mstmction that is vectored This information mcludes general register numbers, effective address and data sizes, an effective operand segment register number, the prefix byte count, and a record of the existence of a LOCK prefix The emulation environment also loads a modr/m reg field and a modr/m regm field are loaded into Reg and Reg registers The emulation environment is initialized at the end of a successful vectonng decode cycle and remains at the initial state for substantially the duration of the emulation of an mstmction by emulation code, until an ERET code is encountered The vectonng decoder 418 generates four operations of an Op quad in one of four forms All four forms include three LIMM operations The four forms differ only m the immediate values of the LIMM operations and in whether the third operation is an LEA operation or a NOOP operation. A first vectonng decode Op quad has the form LIMM t2, <ιmm32 > LIMM tl, <dιsp32 > LEA t6,@( <gam > ),_ a LIMM t7,LogSeqDecPC[31 0] //logical seq next //instr PC A second vectonng decode Op quad has the foπn LIMM t2, < ιmm32 > LIMM tl , <dιsp32 > NOOP LIMM t7,LogSeqDecPC[31..0] A third vectonng decode Op quad has the foπn- LIMM t2, < +/- 1/2/4 > //equiv to "LDK(D)S t2, + l/+2" LIMM tl, < +/- 2/4/8 > //equiv to "LDK(D)S tl , +2/+4" NOOP LIMM t7,LogSeqDecPC[31..0] A fourth vectonng decode Op quad has the foπn: LIMM t2 , < + 2/4 > //equiv to " LDKD t2. + 2 " LIMM tl , <dιsp32 > LD t6,@(SP).SS.s LIMM t7,LogSeqDecPC[31..0] //predicted RET target adr //from Retum Address Stack The first two forms of vectoring Op quads apply for most opcodes. The first form is used for memory- referencing modr/m instmctions for which the LEA operation is used to compute and load a general address mode effective operand address into a treg. The second form is used for non-modr/m and register-referencing modr/m instmctions. For mstmctions having the second form no address is necessarily computed, although the < ιmm32 > and <dιsp32 > values remain useful insofar as they contain mstmction bytes following the opcode byte The third form of vectonng Op quad is used for all string instmctions plus some neighboring non-modr/m instmctions. A fourth form of vectonng Op quad supports special vectonng and emulation requirements for near RET instmctions. The macroinstmction decoder 230 has four program counters, including three decode program counters 420, 422 and 424, and one fetch program counter 426. A first decode program counter, called an instmction PC 420, is the logical address of the first byte, including any prefix bytes, of either the cuπent instmction bemg decoded or, if no instmction is cuπently decoding, the next mstmction to be decoded If the decode operation is a multiple instmction decode, instmction PC 420 points to the first mstmction of the multiple instmctions to be decoded. The instmction PC 420 corresponds to the architectural address of an instmction and is used to generate instmction fault program counters for handling of exceptions The instmction PC 420 is passed down the scheduler 260 with coπesponding Op quads and is used by an operation commit unit (OCU) (noi show n ) of the scheduler 260 to produce instmction fault program counters to be saved during exception processing When an Op quad is generated by the macroinstmction decoder 230, the cuπent instmction PC 420 value is tagged to the Op quad and loaded into the Scheduler 260 Op quad entry along with the Op quad A second decode program counter, called a logical decode PC 422, is the logical address of the next mstmction byte to be decoded and addresses either an opcode byte or a prefix byte. A third decode program counter, called a linear decode PC 424, is the linear address of the next mstmction byte to be decoded and addresses either an opcode byte or a prefix byte. The logical decode PC 422 and the linear decode PC 424 point to the same instmction byte. The lmear decode PC 424 designates the address of the instmction byte cuπently at the first byte rotator 430. The various decoders in the macroinstmction decoder 230 function on the basis of decoding or consuming either prefix bytes or whole instmctions minus any prefix bytes so that prefixes are generally handled as one-byte instmctions. Therefore, the address boundaries between instruction and prefix byte decodes are more important than mstmction boundaries alone. Consequently, at the beginning of each decode cycle, the next mstmction byte to be decoded is not necessaπly the tme beginning of an mstmction. At the beginning of a decode cycle the logical decode PC 422 and the linear decode PC 424 contain the logical and linear addresses of the next instmction to be decoded, either an instmction or a prefix byte. The lmear decode PC 424 is a primary program counter value that is used during the decoding process to access the instmction buffer 408. The linear decode PC 424 represents the starting point for the decode of a cycle and specifically controls the byte rotator feeding bytes from the instmction buffer 408 to the first short decoder 410 and to the long and vectoring decoders 416 and 418. The linear decode PC 424 also is the reference point for deteπnining the instmction addresses of any further short decode instmctions or prefix bytes, thus generating control signals for the byte rotators feeding the second and third shoπ decoders 412 and 414. The linear decode PC 424 also acts secondarily to check for breakpoint matches during the first decode cycles of new instmctions, before prefix bytes are decoded, and to check for code segment overruns by the macroinstmction decoder 230 during successful instmction decode cycles. The logical decode PC 422 is used for program counter-related transfer control instmctions, including CALL instmctions. The logical decode PC 422 is supplied to the branch unit 234 to be summed with the displacement value of a PC-relative transfer control instmction to calculate a branch target address. The logical decode PC 422 also suppoπs emulation code emulation of instmctions. The next sequential logical decode program counter (PC) 422 is available in emulation code from storage m a temporary register by the vectoring Op quad for general usage. For example, the next sequential logical decode PC 422 is used to supply a retum address that a CALL instmction pushes on a stack. A next logical decode PC 428 is set to the next sequential logical decode program counter value and has functional utility beyond that of the logical decode PC 422. The next logical decode PC 428 directly furnishes the retum address for CALL instmctions decoded by the macroinstmction decoder 230. The next logical decode PC 428 also is passed to emulation code logic during vectoring decode cycles via one of the operations w ithin the vectonng Op quad. During a decode cycle, the linear decode PC 424 points to the next instmction bytes to be decoded The four least significant bits of linear decode PC 424 point to the first mstmction byte within the instmction buffer 408 and thereby directly indicate the amount of byte rotation necessary to align the first and subsequent instmction bytes in the mstmction cache 214. The first byte rotator 430 is an mstmction multiplexer, specifically a 16 1 byte multiplexer, for accessing bytes in the mstmction buffer 408 that are offset by the linear decode PC 424 amount The first byte rotator 430 is seven bytes wide for the first shoπ decoder SDecO 410 and eleven bytes wide for the long decoder 416 and the vectonng decoder 418 in combination. Shared logic in the first shoπ decoder SDecO 410, the long decoder 416 and the vectoring decoder 418 generate a first instmction length value ILenO for the first instmction. The second and third byte rotators 432 and 434 are seven byte-wide mstmction multiplexers, specifically 16: 1 byte multiplexers. The second byte rotator 432 accesses bytes in the instmction buffer 408 that are offset by the sum of the linear decode PC 424 amount and the first instmction length ILenO. Logic in the second short decoder SDecO 412 generate a second instmction length value ILenl for the second instmction. The third byte rotator 434 accesses bytes in the instmction buffer 408 that are offset by the sum of the linear decode PC 424 amount and the first and second instmction lengths ILenO and ILenl . The byte rotators 430, 432 and 434 multiplex instmction bytes but not predecode bits. The byte rotators 430, 432 and 434 are controlled using predecode information in which the predecode bits associated with the first opcode byte or the first byte of the first instmction directly controls the second rotator 432. The first byte of the second instmction directly controls the third rotator 434. Each predecode code implies an instmction length but what is applied to the next rotator is a pointer. The pointer is derived by taking the four least significant bits of the program counter at the present instmction plus the length to attain the program counter to the next instmction. All program counters 420, 422, 424 and 428 in the macroinstmction decoder 230 are initialized during instmction and exception processing. A plurality of signal sources activate this initialization. First, the branch unit 234 supplies a target branch address when a PC-relative transfer control instmction is decoded and predicted taken. Second, a return address stack (not shown) supplies a predicted retum target address when a near RET instmction is decoded. Third, the scheduler 260 generates a conect and alternate branch address when the macroinstmction decoder 230, along with the remaining circuits in the processor 120, is restarted by the scheduler 260 due to a mispredicted branch condition (BRCOND) operation. Fourth, register unit 244, the primary RegOp execution unit, supplies a new decode address when a WRIP RegOp is executed. The WRIP RegOp execution allows emulation code to explicitly redirect instmction decoding. In all four cases, a logical address is supplied and utilized to simultaneously reinitialize the three decode program counters 420, 422 and 424. For the linear decode PC 424, a linear address value is supplied by adding the supplied logical address to the cuπent code segment base address to produce the coπesponding linear address for loading into linear decode PC 424. The logical address is loaded into the cuπent instmction PC 420 and the logical decode PC 422. For each decode cycle until a next reinitialization, the macroinstmction decoder 230 sequentially and synchronously updates the current instmction PC 420, the logical decode PC 422 and the linear decode PC 424 as instmction bytes are successfully decoded and consumed by the individual decoders of macroinstmction decoder 230. Generation of the instmction lengths IlenO and Ilenl occurs serially. To hasten this serial process by emulating a parallel operation, instmction length lookahead logic 436 quickly determines the instmction lengths ILenO and ILenl using four predecode bits specifying the length of each instmction byte in the instmction buffer 408. The predecode bits associated with the opcode byte of the first instmction byte in the instmction buffer 408, the first instmction byte being multiplexed to the first shoπ decoder SDecO 410. directly specifics a byte index of the opcode byte of the second instmction byte in the instmction buffer 408. The predecode bits associated with the opcode byte of the second instmction byte in the instmction buffer 408, the second instmction byte being multiplexed to the second shoπ decoder SDecl 412. directly specifies a byte index of the opcode byte of the third instmction byte in the instmction buffer 408. The instmction length lookahead logic 436 includes two four-bit-wide 16: 1 multiplexers for generating the byte indices of the opcode bytes of the second and third instmction bytes in the instmction buffer 408. The instmction lookahead logic 436 also includes logic for determining validity of the sets of predecode bits. Predecode bits are valid when the associated instmction byte is the start of a valid short decode instmction. Specifically, the instmction lookahead logic 436 determines whether predecode bits for a given byte in the instmction buffer 408 point to the same byte, implying a zero length for an instmction starting at that byte. If so, that byte is not the start of a short decode instmction and no further short decoding is possible. Otherwise, a short decode operation is possible and predecode bits point to the beginning of the next instmction. The predecoder 270 connected between the main memory 130 and the instmction cache 214 has eight logic units, each of which examines its associated instmction byte plus, in some cases, the following one or two instmction bytes. The first instmction byte is decoded as an opcode byte and the second and third instruction bytes, if the opcode byte is a modr/m opcode, are decoded as modr/m and sib bytes. Based on these three bytes, the length of an instmction and whether the instruction is classified as a "short" mstmction are determined. The length of the instmction is added to a four-bit fixed value coπesponding to the position of the logic umt with respect to the sixteen logic units to determine the byte index used by the instmction length lookahead logic 436. This byte index is set as the value of the predecode bits if the instmction falls within the cntena of a short instmction For instmction bytes not meeting the shoπ instmction cntena, the predecode bits are set to the four-bit fixed value coπesponding to the position of the logic unit with respect to the sixteen logic units without increment to designate an mstmction length of zero An implied instmction length of zero is indicative that the mstmction is not a shoπ instmction. The predecode bits are truncated from four bits to three since shoπ decode instmctions are never longer than seven bytes and the most significant bit is easily reconstructed from the three predecode bits and the associated fixed byte address The expansion from three to four predecode bits is performed by predecode expansion logic 440 having sixteen logic units coπesponding to the sixteen instmction bytes of the instmction cache 214 The sixteen logic units of predecode expansion logic 440 operate independently and simultaneously on predecode bits as the mstmction bytes are fetched from die stmction cache 214 to the instmction buffer 408 The final two of the thirty-two instmction bytes that are predecoded and loaded to the mstmction cache 214 have only one or two bytes for examination by the predecoder 270 For modr/m opcodes the full instmction length cannot be determined Thus logic units for bytes 14 and 15 in the predecoder 270 are modified from logic umts for bytes 0 through 13 For instmction byte 15, logic unit 15 of the predecoder 270 forces an mstmction length of zero for all modr/m opcodes and for non-shon decode instmctions For instmction byte 14, an effective instmction length of zero is forced for modr/m opcodes with an address mode requiring examination of a sib byte to reliably determine instruction length, as well as for non-short instmctions Dunng each decode cycle, the macroinstmction decoder 230 checks for several exception conditions, including an instmction breakpoint, a pending nonmaskable interrupt (NMI). a pending interrupt (INTR), a code segment overmn, an instmction fetch page fault, an instmction length greater than sixteen bytes, a nonlockable instmction with a LOCK prefix, a floating point not available condition, and a pendmg floating point error condition Some conditions are evaluated only dunng a successful decode cycle, other conditions are evaluated lπespective of any decoding actions dunng the cycle When an active exception condition is detected, all instmction decode cycles including shoπ, long and vectoring decode cycles, are inhibited and an "exception" vectonng decode is forced in the decode cycle following exception detection The recognition of an exception condition is only overndden or inhibited by inactivity of the macroinstmction decoder 230, for example, when emulation code Op quads are accepted by the scheduler 260, rather than shoπ and long or vector decoder Op quads. In effect, recognition and handlmg of any exception conditions are delayed until an ERET Op seq retums control to the macro mstmction decoder 230. Dunng the decode cycle that forces exception vectonng, a special emulation code vector address is generated in place of a normal instmction vector address. The vectonng Op quad that is generated by the long and vectonng decoders 416 and 418 is undefined. The exception vector address is a fixed value except for low-order bits for identifying the panicuiar exception condition that is recognized and handled When multiple exception conditions are detected simultaneously, the exceptions are ordered in a pπoπty order and the highest pnoπty exception is recognized. The mstmction breakpoint exception, the highest pπoπty exception condition, is recognized when the lmear decode PC 424 pomts to the first byte of an instmction including prefixes, the lmear decode PC 424 matches a breakpoint address that is enabled as an mstmction breakpoint, and none of the mstmction breakpoint mask flags are clear One mask flag (RF) specifically masks recognition of mstmction breakpoints Another mask flag (BNTF) temporanly masks NMI requests and instmction breakpoints The pending NMI exception, the penultimate pnonty exception, is recognized when an NMI request is pendmg and none of the NMI mask flags are clear One mask (NF) specifically masks nonmaskable interrupts Another mask flag (BNTF) temporanly masks NMI requests and mstmction breakpoints The pending INTR exception, the next exception in pnonty followmg the pendmg NMI exception, is recognized when an INTR request is pending and the interrupt flag (IF) and temporary interrupt flag (ITF) are clear The code segment overmn exception, the next exception in pnority followmg the pendmg INTR exception, is recognized when the macroinstmction decoder 230 attempts to successfully decode a set of instmctions beyond a cunent code segment limit The mstmction fetch page fault exception, having a priority immediately lower than the code segment overmn exception, is recognized when the macroinstmction decoder 230 requires additional valid instmction bytes from the instmction buffer 408 before decoding of another instmction or prefix byte is possible and the instmction translation lookaside buffer (ITB) signals that a page fault has occuπed on the cuπent mstmction fetch A faulting condition of the mstmction fetch control circuit 218 is repeatedly retned so that the ITB continually repons a page fault until the page fault is recognized by the macroinstmction decoder 230 and subsequent exception handlmg processmg stops and redirects instmction fetching to a new address The fault indication from the ITB has the same timing as instmctions loaded from the instmction cache 214 and. therefore, is registered in the subsequent decode cycle The ITB does not necessarily signal a fault on consecutive instmction fetch attempts so that the macroinstmction decoder 230 holds the fault indication until fetcbmg is redirected to a new mstmction address Upon recognition of a page fault, additional fault information is loaded into a special register field The mstmction length greater than sixteen bvtes exception, which has a pnonty just below the mstmction fetch page fault exception, is recognized when the macroinstmction decoder 230 attempts to successfully decode an mstmction havmg a total length including prefix bytes of greater than fifteen bytes The instmction length greater than sixteen bytes exception is detected by countmg the number of prefix bytes before an actual instmction is decoded and computing the length of the rest of the instmction when it is decoded. If the sum of the prefix bytes and the remaining instmction length is greater than sixteen bytes, an eπor is recognized. The nonlockable instmction with a LOCK prefix exception, havmg a pnonty below the mstmction length exception, is recogmzed when the macroinstmction decoder 230 attempts to successfully decode an mstmction having a LOCK prefix, in which the mstmction is not included in the lockable mstmction subset The nonlockable LOCK mstmction exception is detected baseύ on decode of the opcode byte and existence of a OF prefix The nonlockable LOCK instruction exception only occurs dunng vectonng decode cycles smce the LOCK prefix inhibits short and long decodes. The floatmg point not available exception, havmg a next to lowest pnonty, is recogmzed when the macroinstmction decoder 230 attempts to successfully decode a WAIT mstmction or an ESC mstmction that is ont a processor control ESC. and the reporting of a floating point eπor is pendmg Macroinstmction decoder 230 detects the floating point not available exception based on decoding of an opcode and modr/m byte, in addition to the existence of a OF prefix Dunng each decode cycle, the macroinstmction decoder 230 attempts to perform some form of instmction decode of one or more instmctions Typically, the macroinstmction decoder 230 succeeds in performing either one or multiple short decodes, one long decode or an instmction vectonng decode Occasionally no decode is successful for three types of conditions including detection of an active exception condition, lack of a sufficient number of valid bytes m the instmction buffer 408, or the macroinstmction decoder 230 does not advance due to an extemal reason When an active exception condition is detected all forms of instmction decode are inhibited and, dunng the second decode cycle after detection of the exception condition, an exception vectonng decode cycle is forced, producing an invalid Op quad When an insufficient number of valid bytes are available in the instmction buffer 408 either no valid bytes are held in the instmction buffer 408 or at least the first opcode is valid and one of the decoders decodes the instmction but the decoded instmction length requires further valid bytes in the mstmction buffer 408, not all of which are cuπently available When an extemal reason prevents macroinstmction decoder 230 advancement either the scheduler 260 is full and unable to accept an additional Op quad dunng a decode cycle or the scheduler 260 is cuπently acceptmg emulation code Op quads so that the macroinstmction decoder 230 is inactive awaiting a return to decodmg In the latter two cases, the decode state of the macroinstmction decoder 230 is inhibited from advancing and the macroinstmction decoder 230 simply retnes the same decodes in the next decode cycle Control of macroinstmction decoder 230 inhibition is based on me generation of a set of decode valid signals with a signal coπesponding to each of the decoders For each decoder there are multiple reasons which are combined into decoder valid signals to determine whether that decoder is able to successfully perform a decode The decoder valid signals for all of the decoders are then monitored, in combination, to determine the type of decode cycle to perform The type of decode cycle is mdicative of the particular decoder to perform the decode The extemal considerations are also appraised to determine whether the selected decode cycle type is to succeed Signals indicative of the selected type of decode cycle select between vanous signals internal to the macroinstruction decoder 230 generated by the different decoders, such as alternative next decode PC values, and also are applied to control an Op quad multiplexer 444 which selects the input Op quad applied to the scheduler 260 from the Op quads generated by the short decoders, the long decoder 416 and the vectonng decoder 418 In the case of vectonng decode cycles, the macroinstmction decoder 230 also generates signals that initiate vectonng to an entry point in either intemal emulation code ROM 232 or extemal emulation code RAM 236. The macroinstmction decoder 230 then monitors the active duration of emulation code fetchmg and loading into the scheduler 260 The mstmction decoder 220 includes the branch unit (not shown) for performing branch prediction so that operations are speculatively executed Performance of an out-of-order processor is enhanced when branches are handled quickly and accurately so that pipeline-draining mispredictions are avoided The processor 120 employs a two-level branch prediction algorithm that is disclosed in detail in U.S. Patent No. 5,454, 117, entitled CONFIGURABLE BRANCH PREDICTION FOR A PROCESSOR PERFORMING SPECULATIVE EXECUTION (Puziol et al., issued September 26, 1995), U.S. Patent No. 5,327,547, entitled TWO-LEVEL BRANCH PREDICTION CACHE (Stiles et al., issued July 5, 1994). U.S. Patent No. 5, 163,140, entitled TWO-LEVEL BRANCH PREDICTION CACHE (Stiles et al.. issued November 10, 1992), and U.S. Patent No. 5, 093,778, entitled INTEGRATED SINGLE STRUCTURE BRANCH PREDICTION CACHE (Favor et al., issued March 3, 1993). The processor 120 further utilizes an 8, 192-entry branch history table (BHT) (not shown) which is indexed by combining four program counter bits with nine bits of global branch history. Each BHT entry contains two history bits. The BHT is a dual-port RAM allowing both a read/lookup access and a write/update access. BHT lookups and updates do not conflict since they take place in opposite half phases of a clock cycle. The large number of entries of the BHT is supplied in a reasonable integrated circuit area because the BHT is only predictmg conditional branch directions so that entnes are not tagged and predicted branch target addresses are not stored, except for a 16-entry retum address stack (not shown). Accordingly, an access to the BHT is similar to a direct mapping into a cache-like stmcture in which the the BHT is indexed to access an entry in the BHT and the accessed entry is presumed to be a branch mstmction. For branches other than retums. the target address is calculated dunng the decode cycle. The target address is calculated with sufficient speed using a plurality of parallel adders (not shown) that calculate all possible target addresses before the location of a branch mstmction is known. By the end of the decode cycle, the branch unit 234 determines which, if any, target address result is valid. If a branch is predicted taken, the target address is immediately known and the target instmctions are fetched on the following cycle, causing a one-cycle taken-branch penalty. The taken-branch penalty is avoided usmg a branch target buffer (BTB) 456. The BTB 456 includes sixteen entnes, each entry having sixteen mstmction bytes with associated predecode bits. The BTB 456 is indexed by the branch address and is accessed dunng the decode cycle. Instmctions from the BTB 456 are sent to the instmction decoder 220. eliminating the taken-branch penalty, for a cache hit of the BTB 456 when the BHT predicts a taken branch Dunng each decode cycle, the linear decode PC 424 is used in a direct-mapped manner to address the BTB 456. If a hit, which is realized before the end of the decode cycle, occurs with a BTB entry, a PC-relative conditional transfer control instmction is decoded by a shoπ decoder and the control transfer is predicted taken, then two actions occur. First, the initial target linear fetch address directed to the instmction cache 214 is changed from the actual target address to a value which pomts to an mstmction byte immediately followmg the valid target bytes contamed in the BTB entry. This modified fetch address is contamed in the BTB entry and directly accessed from the BTB entry. Second, the instmction byte and predecode information from the entry is loaded into the mstmction buffer 408 at the end of the decode cycle. If a PC-relative conditional transfer control instmction is decoded by a short decoder and the control transfer is predicted taken, but a miss occurs, then a new BTB entry is created with the results of the target instmction fetch. Specifically, simultaneously with the first successful load of target mstmction bytes into the instmction buffer 408 from the instmction cache 214, the same information is loaded into a chosen BTB entry, replacing the previous contents. The target fetch and instmction buffer 408 load otherwise proceed normally. Each entry includes a tag part and a data part. The data part holds sixteen extended instmction bytes including a memory byte and three associated predecode bits. The conespondence of the memory byte is memory- aligned with the coπesponding mstmction buffer 408 location. The tag part of a BTB entry holds a 30-bit tag including the 32-bit linear decode PC 424 associated with the transfer control instmction having a cached target, less bits [4 1], an entry valid bit and the 30-bit modified initial target linear instmction fetch address No explicit instmction word valid bits are used since the distance between the tme target address and the modified target address directly implies the number and designation of valid instmction words within the BTB 456. The purpose of the BTB 456 is to capture branch targets within small to medium sized loops for the time penod a loop and nested loops are actively executed In accordance with this purpose, at detection of a slightest possibility of an inconsistency, the entire BTB is invalidated and flushed. The BTB 456 is invalidated and flushed upon a miss of the mstmction cache 214, any form of invalidation of stmction cache 214, an ITB miss, or any form of ITB invalidation. Branch targets outside temporal or spatial locality are not effectively cached. Typically, me BTB 456 contains only a small number of entnes so that complexity is reduced while the majonty of performance benefit of ideal branch target caching is achieved PC-relative branch target address calculation logic performs the target address calculation Branch target address calculation logic is utilized only for PC-relative transfer control instmctions that are decoded by a short decoder SDecO 410. SDecl 414 or SDec2 416 Specifically, the branch target address calculation logic is utilized for the short decode branch instmctions including Jcc dιsp8. LOOP dιsp8, JMP dιsp8, JMP dιspl6/32, and CALL dιspl6/32 Each short decoder SDecO 410, SDecl 412 and SDec2 414 includes logical and linear branch target address calculation logic 452. All three sets of logical and linear branch target address calculation logic (not shown) function in parallel while the shoπ decoders 410. 412 and 414 determine whether any of the operations is a PC- relative shoπ decode branch instmction The logical and linear branch target address calculation logic sum the logical program counter of the branch, the length of the branch instmction and the sign-extended displacement of the branch instmction and conditionally mask the high-order 16 bits of the sum, depending on calculation sizing, to produce a logical target address. The logical and linear branch target address calculation logic sum the logical target address with the cuπent code segment base address to produce a linear target address If the branch is taken, either unconditionally or predicted taken, then calculated addresses coπesponding to the decoded shoπ decode branch stmction are used to reinitialize the logical decode PC 422 and linear decode PC 424 If the branch is predicted not taken, the logical address is saved with the associated shoπ decode branch instmction (BRCOND Op) in a scheduler 260 Op quad entry The logical target address is compared to the cuπent code segment limit value to momtor for a limit violation. If the logical and linear branch target address calculation logic detects a limit violation, whether the branch is predicted taken or predicted not taken, then a special tag bit indicative of the limit violation is set in the scheduler 260 Op quad entry holding the operations generated from the branch stmction. Subsequently, when the operation commit umt (OCU) of the scheduler 260 attempts to commit this Op quad, the Op quad is handled as contammg a fault and aborted. The macroinstmction decoder 230 generates signals that initiate vectonng to a fault handler in emulation code ROM 232. The fault handler temporanly inhibits decoding by the shoπ and long decoders and jumps to the fault PC address of the violating mstmction associated with the faulted Op quad. Ultimately, the branch instmction is redecoded and vectored to instmction emulation code. The emulation code recognizes the limit violation if the branch is actually taken and appropnately handles the violation. The processor 120 generally responds to a fault condition by vectonng to a specific fault handler in the emulation code ROM 232. The fault handler includes operations defined within the RISC instmction set which perform a routine that detennines the source of the fault, an appropnate response to the fault and steps to initiate the appropnate response. As an alternative in appropriate cases, the processor 120 also includes a special "load alternate fault handler" operation which initiates a special fault response. Exceptions that are detected dunng decode time direct execution to a fixed set of entry points, one entrv point for each possible exception condition through operation of the vectonng decoder 418 which activates the alternate fault handler and designates a fault handler address. The alternate fault handler is advantageous for allowing modified full handling of special conditions. The load alternate fault handler instmction passes through the instmction decoder 220 pipeline in the manner of all instmctions, but causes any subsequent exception condition to invoke a different vector mstmction ROM entry pomt. The alternate fault handler terminates upon completion of execution of the cuπent macroinstmction One example of the advantage of the alternate fault handler arises with respect to a repeated move string instmction (REP MOVs). To perform multiple interactions very quickly, a capability to reorder the sequence of operations is impoπant. The sequence of operations typicallv includes a load to a first pointer-designated address, a store to a second pointer-designated address and. if both the load and store are successful, an increment of the first and second pointers and a decrement of a counter. For additional efficiency, the pointers are incremented and the counter decremented before completing the store operation. However, if a fault or exception occurs dunng the sequence of operations, the sequence is aboned with the counters and pomters in the wrong state. For example, the architectural x86 SI, DI and CX registers do not have the coπect value. The alternate fault handler is used by specifying, prior to the sequence, an alternate fault handler that performs a cleanup after a repeated move fault. The sequence proceeds without the overhead of intermediate instmctions for tracking the pointers and counters If no enors occur, the alternate fault handler terminates without effect However, if an eπor occurs, the alternate fault handler is invoked This alternate fault handler is specific to the panicuiar sequence of operations and performs clean-up accordingly and jumps to the default fault handler Advantageously, highly efficient code improves speed performance without hindrance from the alternate fault handler until an cnor arises, at which time the error is addressed. The branch history table (BHT) stores recent history information, panicularly branch direction information, about conditional transfer control instmctions that have been encountered in the past When a branch is repeated, stored mformation relating to the branch is analyzed to predict the cuπent direction of the branch. Subsequently, the stored mformation is updated based on the actual direction taken by the branch. The stored information is denved from the direction of a particular newly encountered branch, the recent direction history of the particular branch and the recent direction history of other branches. The stored information is based on a plurality of sets of two-bit state machines and also on a direction history of the last nine branch executions, whether the last nine branch executions pertained to the particular branch or other branches. The mstmction address of the particular newly encountered branch is used to select one of the plurality of sets of two-bit state machines. The direction history of the last nine branch executions is used to select a particular two-bit state machine in the selected set of state machines. Each state machine is a two-bit saturating counter for counting the directions taken by the most recent few branches that accessed this panicuiar state machine. Typically a panicuiar state machine is accessed by the same static branch, although other branches may access the same state machine. A larger state machme value is mdicative of more taken instances of a branch. A smaller state machine value is mdicative of more not taken instances of a branch. Upon selection of a state machme, the state machine is accessed. If the present overall count is "greater" then a branch is predicted taken. If the present overall count is "lesser" then a branch is predicted not taken. The direction history of the most recent nine branch executions is held a nine-bit shift register which is clocked or shifted each time a branch instmction is successfully decoded The immediate branch direction just predicted is the new direction history value that is shifted into the shift register A history bit value of one indicates a branch taken. A history bit value of zero indicates a branch not taken. Dunng a decode cycle, the linear decode PC 424 is used to perform a BHT table lookup. If a PC-relative branch instmction is decoded, then the accessed state machme immediately predicts the branch direction, although the actual mstmction subsequently fetched and decoded is determined at the end of the decode cycle by the macroinstmction decoder 230 Subsequently, the branch condition (BRCOND) operation generated by decoding of the conditional branch mstmction is resolved by logic in the scheduler 260. at which time the state machme is updated If the branch is actually taken, the state machine is decremented unless already at the maximum value (3) If the branch is actually not taken, the state machine is incremented unless already at a minimum value (0) Accordingly, a state machine value of 0 and 1 respectively indicate a strong and a mild prediction of a branch not taken. A state machine value of 2 and 3 respectively indicate a mild and a strong prediction of a branch taken. To suppoπ updating of BHT entπes, a copy of the branch address and direction history bits for accessing the BHT and a copy of the state machine value are passed to the scheduler 260 along with the branch condition (BRCOND) operation Since a maximum of one BRCOND is included in an Op quad, the BHT suppoπ information is tagged to the Op quad applied to the scheduler 260 It is advantageous for reducmg circuit size and complexity that the BHT does not contain entry tags (addresses of lmear decode PC 424 associated with decoded conditional branches) that are typical in cache structures It is further advantageous that the BHT has a large number of entnes so that the contention rate is low The information saved in a scheduler 260 Op quad along with an associated BRCOND operation has a width of fifteen bits including four branch address bits, nine cuπent history bits, and the immediately accessed two state machine bits, the upper bit of which is also the predicted direction for the immediate branch The first thineen bits are used, when necessary, to reaccess the BHT and to update a state machine value The final two bits are modified to create the new state machine value When a branch is mispredicted, the set of history values in the nine-bit branch history shift register are coπected to reflect the actual direction taken by the branch. Furthermore, the shift register is "shifted back" to correspond to the mispredicted branch, then updated based on the actual branch direction and which branch direction was predicted. A return address stack (RAS) (not shown) is a target address cache for retum (RET) transfer control instructions. RAS is an eight entry, 32-bit wide, single-poned RAM that is managed as a circular buffer usmg a smgle three-bit pomter. Dunng each cycle at most one access, either a read access for a RET decode or a wnte access for a CALL decode, is performed RAS caches RET retum addresses and predicts retum addresses which inherently specify a target address indirectly, in contrast to other transfer control instmctions that contain a direct specification of target address RAS is advantageously utilized since a panicuiar RET instmction often changes target address between different executions of the mstmction RAS discovers and anticipates the target address value for each RET instmction execution through monitonng of the retum addresses that are saved - pushed on a stack - by CALL instmctions. Coπesponding CALL and RET instmctions typically occur dynamically in pairs and in last-in-first-out LIFO order with respect to other CALL and RET instmction pairs. Each time a CALL instmction is successfully decoded, the logical retum address of the CALL instmction is saved (pushed) to a circular buffer managed as a LIFO stack. Each time a RET instmction is successfully decoded, the retum address value cuπently on the top of the RAS is employed as the predicted target address for the RET and the value is popped from the RAS. RAS achieves a high prediction rate although mispredictions do occur because CALLs and RETs do not always occur in nested pairs, only near CALLs and RETs and not far CALLs and RETs are supponed, and mispredictions occur because of the finite depth of the RAS. When a conditional branch misprediction occurs, RAS attempts to restore the state pnor to misprediction by setting the top of stack pointer to the previous condition because CALL and RET instmctions may have been speculatively decoded and the top-of-stack pointer thereby modified. The original pointer, before the misprediction, is to be restored. Restoration following a misprediction is supponed by the scheduler 260. Each scheduler 260 Op quad is tagged with a cunent initial top-of-stack pointer value in effect during the decode cycle in which the Op quad was generated. When the BRCOND Op generated for a conditional branch instmction is resolved and found to be mispredicted, the top-of-stack pointer tagged to the scheduler Op quad is supplied to the RAS during a restan cycle that is generated by the scheduler 260. RAS replaces the cuπent top-of-stack value with the scheduler Op quad top- of-stack pointer tag. Referring to Figure 5. a schematic block diagram depicts an stmction decoder emulation circuit 231 including an instmction register 512, an entry point circuit 514. an emulation code sequencer 510. an emulation code memory 520 and an Op substitution circuit 522. The mstmction decoder emulation circuit 500 is a circuit within the instmction decoder 220. The instmction decoder emulation circuit 231 receives instmction bytes and associated predecode information from the instmction buffer 408 connected to the instmction fetch control circuit 218, the BTB 456 or the instmction cache 214 The mstmction buffer 408 is connected to and supplies the mstmction register 512 with x86 instmctions. The instmction register 512 is connected to the entry point circuit 514 to supply emulation code ROM entry points. The entry point circuit 514 receives the x86 instmction and, from the x86 instmction operation code (opcode), generates an entry point address, a beginning address pointing mto me emulation code memory 520. In this manner an address of an mstmction in emulation code memory 520 is synthesized from the opcode of an x86 mstmction. The address is denved based on the x86 instmction byte, particularly the first and second bytes of the x86 instmction as well as information such as the modem byte, prefixes REP and REPE, the protected mode bit and effective data size bit DSz. Generally, closely related x86 instmctions have similarly coded bit fields, for example a bit field indicative of instmction type is the same among related x86 instmctions, so that a single entry in the emulation code memory 520 conesponds to several x86 instmctions. Entry points are generally synthesized by reading the x86 instmctions and assigning bits of the entry point address according to the values of particular x86 instmction bit fields. The instmction register 512 is connected to the emulation code sequencer 510 which, in tum. is connected to the emulation code memory 520. The emulation code sequencer 510 applies the entry point to the emulation code memory 520 and receives sequencing information from the emulation code memory 520. The emulation code sequencer 510 either controls the sequencing of instmctions or, when a new sequence is to be started, applies an entry point to the emulation code memory 520. Operations (Ops) encoded in the emulation code memory 520 are output by the emulation code memory 520 to the Op substitution circuit as Op quads or Op units. The Ops correspond to a template for RISC-type x86 operation. This template includes a plurality of fields into which codes are selectively substituted. The emulation code memory 520 is connected to the Op substimtion circuit 522 to supply Ops into which the various Op fields are selectively substituted. Functionally, the entry point circuit 514 calculates an entry point into the emulation code ROM 232 or emulation code RAM 236. The sequence in emulation code ROM 232 determines the functionality of an instmction. The emulation code memory 520 includes an on-chip emulation code ROM 232 and an extemal emulation code RAM 236. The emulation code memory 520 includes encoded operations that direct how the processor 120 functions and defines how x86 instmctions are executed. Both the emulation code ROM 232 and RAM 236 include a plurality of operation (Op) instmction encodings having a Op coding format that is the same in ROM 232 and RAM 236. For example, in one embodiment the emulation code ROM 232 has a capacity of 4K 64-bit words. The Op coding format is typically a format defined in 30 to 40-bits for example. In one embodiment, a 38-bit format, shown in Figures 6A through 6E, is defmed. The emulation code ROM 232 base address location within the emulation space is fixed. The extemal emulation code RAM 236 is resident in standard memory address space within cacheable memory. The emulation code RAM 236 base address location within the emulation space is fixed. The 32-bit emulation code RAM 236 address is formed by the fixed base address of the emulation code RAM 236 which supplies bits the most significant fifteen bits < 31 : 17 > , and the Op address which furnishes fourteen bits < 16:3 > concatenated to the base address bits. The two least significant bits < 1 :0 > of the emulation code RAM address are set to zero. The fourteen bit Op address in emulation code RAM 236 is the same as the Op address in emulation code ROM 232. Operations (Ops) are stored in Op coding format, for example 38-bιts. in the extemal emulation code RAM 236 in 64-bit words. Bits in excess of the Op coding format bits of the 64-bit words are used to store control transfer (OpSeq) infoπnation. The extemal emulation code RAM 236 is typically used for test and debug purposes, allowing for patching of any instmction encoded in the emulation code ROM 232. and for implementing special functions such as system management mode (SMM ). For example, if an instmction in emulation code ROM 232 is found to function improperly, the extemal emulation code RAM 236 is accessed to temporarily or permanently substitute for the improperly-functioning fixed code in the emulation code ROM 232. Access to the extemal emulation code RAM 236 is typically gained using one of two techniques. In a first technique, a one-bit field in an OpSeq field of an element of emulation code memory 520 designates that the next address for fetching instmctions is located in extemal emulation code RAM 236. In this first technique, the on-chip emulation code ROM 232 initiates execution of the external emulation code RAM 236. In a second technique, a vector address is simply supplied for vectoring to an entry point in the emulation code RAM 236. The instmction cache 214, instmction fetch control circuit 218 and instmction decoder 220 function in three instmction fetch and decode modes. In a first mode, the instmction decoder 220 fetches emulation code Op quads from the on-chip emulation code ROM 232. Each Op quad includes four operations (Ops) plus control transfer information (OpSeq) for determining the next cycle of fetch and decode function. In a second mode, the instmction fetch control circuit 218 controls fetching of x86 macroinstmction bytes from the instmction cache 214, which is part of the on-chip Ll instmction cache 214. The x86 macroinstmctions are decoded by the macroinstmction decoder 230, which generates four operations (Ops). Four Ops plus the OpSeq field form a full Op quad. The mstmction decoder 220 performs any coded control transfers using the branch unit 234 and vectoring functionality of the macroinstmction decoder 230. In a third mode, the instmction fetch control circuit 218 controls fetching of 64-bit words containing emulation code in Op coding format from the instmction cache 214, one 64-bit word per cycle. Each 64-bit word coπesponds to a smgle operation (Op). In other embodiments, a plurality of 64-bit words may be accessed per cycle. An embodiment in which four 64-bit words are accessed, the emulation code RAM 236 supplies a full Op quad in the manner of the on-chip emulation code ROM 232 so that a fully-reprogrammable processor with full efficiency is achieved. A fully-reprogrammable processor advantageously permits soft implementation of greatly diffenng processors, for example an x86 processor and a PowerPC™ in a single hardware. In the first and third operating three modes, control transfer information is formatted into an operation sequencing (Opseq) field of the Op quad. Unconditional control transfers, such as branch (BR) and return from emulation (ERET) operations, are controlled completely using the Opseq control transfer information Conditional transfers, such as branch on condition (BRcc). are controlled using a combination of the Opseq field and a branch condition (BRCOND) operation. An OpSeq field format graphic is shown in Figure 7. The 16-bit OpSeq field 700 includes a two-bit sequencmg action (ACT) field 710. a single-bit extemal emcode field 712 and a 13-bit operation (Op) address field 714. Four sequencing actions in the ACT field 710 are encoded, as follows: ACT Operation Descnption 0 0 BR/BRcc uncond/cond branch to encode address 0 1 BSR/BSRcc uncond/cond "call" to encode address 1 0 ERET/ERETcc return from emulation to instr decodmg 1 1 SRET/SRETcc retum from emulation call Whether a sequencing action of an OpSeq is unconditional or conditional depends on the presence or absence, respectively, of a branch condition (BRCOND) Op elsewhere within the Op quad. The BRCOND Op within the Op quad specifies the condition to be tested and the alternate emulation code target address. No explicit static branch direction prediction bit exists. Instead the predicted action and next address are always specified by the OpSeq field 700 and the "not predicted" next address is always specified by the BRCOND Op. A BRCOND Op is always paired with a BSR sequencing action including unconditional calls For unconditional and conditional "predicted-taken" calls, the BRCOND Op specifies the retum address to be saved The extemal encode field 712 is set to one if emulation code to be executed is located in extemal emulation code RAM 236. The extemal encode field 712 is set to zero if emulation code to be executed is located in intemal emulation code ROM 232. The Op address field 714 designates an address of a target Op within a non-entry point Op quad. The Opseq control transfer information controls unconditional control transfers when an Op quad or 64-bit memory word is fetched and aπanged or "instantaneously decoded". Designation of the next instmction to be decoded is controlled by the Opseq field alone. The Opseq field specifies one of three alternative actions. First, the Opseq field directs fetching of emulation code from emulation code ROM 232 at a specified 14-bit smgle operation word address so that an emulation code ROM 232 Op quad is fetched. Second, the Opseq field directs fetching of emulation code from emulation code RAM 236 at a specified 14-bit single operation word address so that an emulation code RAM 232 64-bit memory word is fetched. Third, the Opseq field includes a retum from emulation (ERET) directive, which directs the instmction decoder 230 to retum to x86 microinstruction decoding. Emulation code fetched from the emulation code ROM 232 is fetched in the form of aligned Op quads. A branch to an intermediate location within an Op quad causes the preceding operations within the Op quad to be treated as invalid by fetching NOOPs in place of the preceding operations. The byte memory addresses for fetching 64-bit memory words from emulation code RAM 236 are created by concatenating a specified 14-bit operation address with three least significant bits set to zero, thereby creating an aligned 8-bit address. The byte memory addresses for fetching 64-bit memory words are 8-bit aligned, thus rendering memory Op decoding and fetch/decode advancement consistent and simple. The Opseq control transfer information also controls designation of the immediate next instmction to be decoded for conditional control transfers. The branch condition (BRCOND) operation specifies the condition code to be tested and evaluated and specifies an altemative 14-bit emulation code fetch and decode address. Thus, Opseq control transfer information for conditional control transfers effectively specifies the predicted path ofthe conditional branch. The BRCOND address typically is either the 14-bit target Op word address or the 14-bit Op word address of the next "sequential" operation (Op). More generally, the BRCOND address may specify a fully general two- way conditional branch. Note that the word sequential is placed in quotation marks to indicate that, although the "sequential" address generally points to an instmction which immediately precedes the present instmction, the "sequential" address may be set to any addressed location. A conditional ERET operation is implemented by setting the Opseq field to specify an ERET operation so that the conditional ERET is predicted taken. If the ERET operation is subsequently found to be mispredicted, then the x86 macroinstmction stream directed by the ERET is aborted and the sequential macroinstmction stream specified by the BRCOND operation is restarted. BRCOND operations are loaded into the scheduler 260 in an unissued state. BRCOND operations are evaluated in-order by the branch resolution unit of the scheduler 260. If the branch is properly predicted, the branch is marked Completed. Otherwise, the BRCOND state is left unissued and triggers a branch aboπ signal when detected by the Op commit unit. The emulation code memory 520 suppoπs a single-level (no nesting) subroutine functionality, in which an Opseq field is set to specify alternatives for fetching emulation code. The alternatives are stmctured as a typical two-way conditional branch, except that a 14-bit Op word address from the immediate field of a BRCOND Op within the Op quad or memory Op is loaded into a subroutine return address register. The subroutine retum address register stores the 14-bit Op word address plus a single bit which designates whether the retum address is located in emulation code ROM 232 or RAM 236. The condition code specified by the BRCOND Op may be any altemative, including TRUE, so that both unconditional and conditional (predicted-taken) subroutines may be specified. However, the BRCOND Op must be specified to avoid loading an undefined value into the subroutine retum address register. All emulation code subroutine suppoπ and retum address register management is performed by the emulation code sequencer 510 at the front of the pipeline. Thus retum address register loading and usage is fully synchronous with standard decoder timing so that no delays are introduced. Two-Wav Emulation Code Branching The emulation code ROM 232 is storage for a plurality of sequences of operations (Ops). An operation sequence begins at a defined entry point that is hard-coded into the emulation code ROM 232 and extends to a return from emulation (ERET) Opseq directive that ends the operation sequence. The number of operations in a sequence is typically variable as is appropriate for performing various different functions. Some simple x86 instmctions have only a single Op entry in the emulation code ROM 232. although these instmctions are fetched with Op quad granularity. Other more complex x86 instmctions use many component operations. The emulation code ROM 232 storage is stmctured as a plurality of Op quads, programmed into a fixed ROM address space. Each Op quad includes four RISC Op fields and one Opseq field. The operation sequences are typically not aligned within the Op quads so that, absent some technique for branching to interspersed locations in emulation code ROM 232, many ROM units in the emulation code ROM 232 are unusable, wasting valuable integrated circuit space. Furthermore, because the entry point address of an instmction in emulation code ROM 732 is synthesized from the opcode of an x86 instmction, the entry point addresses often are forced into fixed positions spread throughout the ROM address space with intervening gaps that lead to unused portions of ROM . ROM positions that are left without access via an entry point are free for other usage but are not conveniently sequential to allow access. The OpSeq field provides a technique for branching to these interspersed locations, thereby substantially eliminating wasted space. Each of the four RISC Op fields of an Op quad stores a simple, RISC-like operation. The OpSeq field stores a control code that is communicated to the emulation code sequencer 510 and directs the emulation code sequencer 510 to branch to a next location in the emulation code ROM 232. Each of the four RISC Op fields in the emulation code ROM 232 may store a branch operation, either conditional or unconditional, and thereby specify a target address so that a plurality of branches may be encoded in a single Op quad. In some embodiments of the instmction decoder emulation circuit 231, the Op quad is limited to having at most a single branch operation to direct Op order in combination with the OpSeq field. The combination of a conditional branch Op in one of the four RISC Op fields and the OpSeq field in an Op quad yields an Op quad with two possible target or next addresses. For an Op quad having a plurality of target addresses, the emulation code sequencer 510 directs the sequence of operations by selecting a hard-coded, predicted target address. Thus, for an Op quad including an conditional branch, the emulation code sequencer 510 selects a hardcoded OpSeq target address in preference over the conditional branch. The unconditional branch is subsequently handled in accordance with the branch prediction functionality of the processor 120 so that no additional branch handling overhead is incuπed by implementing two- way emulation code branching. The OpSeq field is advantageously used to efficiently fit Op sequences into nonused locations in the emulation code ROM 232. This usage of the OpSeq field to branch to a target address advantageously achieves unconditional branching without incurring a time or cycle penalty. A memory map shown in Figure 8 illustrates processor 120 memory assignments, including assignment of a separate system management RAM (SMRAM) area. The system management mode also uses memory in DRAM main memory that underlies the SMRAM at SMRAM area addresses. In the illustrative embodiment, SMRAM is positioned at memory addresses A0000H-BFFFFH. These addresses are normally accessible only while operating in SMM. The SMRAM area is cacheable both in the instmction cache and the data cache. Cache consistency is maintained without flushing. SMM software 810, including SMM instmctions and SMM data, resides at a predefined location withm the AOOOOH to BFFFFH area of address space and physically resides m mam memory mapped to this region Dunng normal system operation, a main memory controller is configured to respond only to SMM accesses within the portion of the AOOOOH to BFFFFH memory locations that specifically holds SMM software These locations are called an SMRAM memory locations 812 Non-SMM accesses of SMRAM 812 fall through to underlying hardware, for example, to a video memory For other non-SMRAM poπions of the AOOOOH to BFFFFH region, the main memory controller is configured as standard memory with no underlying memory or hardware at the SMRAM addresses BIOS code furnishes support for allowing non-SMM software access to SMRAM, typically by a BIOS code which functions at boot time to initialize SMRAM BIOS code also enables access by SMM software to the hardware or memory overlaid by the SMRAM portion of address space BIOS includes programmed support for SMRAM initialization at boot time Refernng to Figure 9, a flowchart which illustrates SMM functionality is shown SMM 900 is a processor operating mode that is distinct and substantially different from other modes including real, V86 and protected modes Entry 910 into system management mode (SMM) is attained by one three methods including assertion of a signal on a system management interrupt (SMI) intenupt pm a call by a special SMM software instmction and the occunence of an I/O access trap I/O access trapping is activated on the basis of special I/O bitmap or I/O trap address ranges so that no hardware support, such as connection to the SMI pin, is necessary While SMM 900 is active, all x86 architectural features and instmctions are available for use in addition to a set of SMM support instructions A typical SMM embodiment is defined withm a 16-bit environment which is similar to a real mode environment However, the SMM environment definition is a soft definition which is completely adaptable and designated by the information set up or initialized by a RISC SMM entry sequence which begins m step 912. SMM software has three mam functional routines including an SMM initialization routine 920. a routine for redirecting SMM operations to extemal memory 930 and an SMM termination routine 940 The SMM initialization routine 920 is activated upon an SMI signal, a SMM software instmction call or an I/O access trap Upon recognition of an activating signal, the processor 120 vectors to a RISC instmction in the BIOS area of address space in step 922 In an SMM initialization step 924 the processor 120 may save the cuπent x86 state and/or a suitable extended instmction pointer (EIP) if desired, set up or initialize a new x86 operating state including specifying the SMM operating mode, setting a SMM micro-architecture control register bit (see SMM control register 1038 shown in Figure 10), and jump to an x86 SMM handler code which is located at a specified location in the AOOOOH to BFFFFH address area Essentially any type of SMM entry functionality is allowed and implemented SMM operation redirecting routine 930 begins with permission check step 932 which determines whether an I/O access is allowed usmg an x86 I/O instmction When the processor 120 successfully completes the permission steps so that an I/O access is allowed to be performed, the processor then checks an internal SMMVectorlO flag m step 934 If this flag is set, in step 936 the processor 120 vectors to an extemal RISC entry pomt, which is located in the BIOS area of address space AOOOOH to BFFFFH but is at a location different from the "SMM entry" entrypoint. If the flag is not set, the processor 120 executes the remainder of the x86 I/O mstmction in step 938 Vectonng step 936 allows all I/O accesses to be monitored and selectively trapped to SMM handler software In one embodiment, I/O access monitoring is based, for example, on an I/O address bitmap or on a compaπson with a set of I/O address ranges. The SMM operation redirecting routme 930 furnishes a generally-applicable redirection functionality which is applicable to specific operations, such as implementation of a peπpheral activity counter emulation and shadowing of write-only I/O ports, that would conventionally require logic in a system chipset The SMM termination routine 940 is activated when the processor 120 decodes an x86 "SMM exit" instmction, in one embodiment for example an x86 opcode "OF AA" in step 942 In step 944, the processor 120 vectors to an SMM exit entry point in exte al RISC memory In some embodiments, the RISC code at the SMM exit entry point implements a conventional SMM exit procedure Alternatively, the SMM exit RISC code implements multiple SMM functions controlled by a parameter passed m a general register or as an immediate value following the opcode byte In embodiments having a control parameter passed as an immediate value, one argument or function number defines the SMM exit operation, while other function numbers specify x86 instmctions for saving and restoπng an x86 state vanable such as a segment register including a cached descπptor Virtually any set of SMM x86 instmctions may be defined and implemented and usage of these individual instmctions may be restncted. as desired For example, special SMM x86 instmctions may be defined so that most instmctions are executable only while operating in SMM. but ceπain instmctions. such as a software SMI instmction. is also executable by normal software, software operating at the cunent privilege level (CPL=0) of a cuπently active program, outside of SMM In step 946, the processor 120 restores the x86 state that was saved at entry to SMM. re-establishing the operating mode of the restored x86 state, clears the SMM control register bit and jumps back to execution at a suitable instmction pointer (EIP) location, such as an EIP saved by the SMM entry code The SMM 900 is terminated by an exit step 950 Refcmng to Figure 10. a schematic block diagram illustrates vanous details of SMM functionality implemented in processor 120 circuits A system management interrupt (SMI) is indicated by a signal on an SMI# pm 960 The SMI# pin 960 is level-sensitive, active low. 5V tolerant and asynchronous SMI# pin 960 is synchronized and deglitched on the processor 120 chip Logically. SMW 960 is a high pnority intenupt that is recognized at x86 mstmction boundaries The SMI intenupt has a higher pnonrv than INTR, NMI and ResetCPU tenupts The SMI intenupt is recognized between iterations of REP string instructions The SMI intermpt is recognized even in a Halt state. The SMI intermpt is not recognized dunng a shutdown state A SMM mask 970 furnishes intermpt masking while the processor 120 is in SMM, as indicated by an asserted SMM control register bit 988 Specifically, SMM mask 970 masks recogmtion of pending NMI, ResetCPU and SMI interrupts. Recognition of a pending INTR intenupt is controlled by the EFlags IF bit, which typically is cleared durmg SMM entry. Masked interrupts become recognizable immediately after "SMM exit" The original IF bit is restored dunng "SMM exit". The memory controller 134 controls SMM bus transactions While the processor 120 is operating tn SMM, all extemal bus transactions withm the AOOOOH to BFFFFH area of address space are marked as SMM accesses. In particular, a system management mode (SMM) address (SMMAD) bit 986 is communicated on the 64-bit multiplexed address/data (IAD) bus (not shown) dunng the address phase of all bus transactions identified as SMM accesses. Normally, for all transactions, the SMMAD bit 986 is deassened with a value of one. However, when a memory transaction to an address in the range AOOOOH to BFFFFH is initiated, the SMMAD bit 986 is asserted with a value of zero. Whether or not the processor 120 is SMM, all bus transactions to addresses outside of the AOOOOH through BFFFFH range have a deasserted SMMAD bit 986 The memory controller 134 is configured to respond to SMM and/or non-SMM accesses to the area of mam memory that is used for SMRAM 812 During initialization of SMRAM 812, the memory controller 134 is configured to respond to non-SMM accesses to SMRAM 812 After the memory controller 134 is configured, the memory controller 134 is reconfigured to respond to SMM accesses and no longer to non-SMM accesses. In some embodiments, off-chip circuitry provides a configuration lock mechanism (not shown) that prevents subsequent modification of these bits by non-SMM software An SMM caching controller 980 controls caching of SMM instmctions and data while automatically maintaining cache consistency Various embodiments of the SMM caching controller 980 employ vaπous schemes in which on-chip cacheabi ty control registers (CCRs) 982 are used to control cacheability of the SMRAM 812 region of address space In another embodiment, the SMRAM 812 is simply marked as noncacheable. In one embodiment of the SMM caching controller 980, the SMRAM address region is flushed from the processor 120 caches during the SMM entry instmction sequence and the SMM exit instmction sequence In a second embodiment of the SMM cachtng controller 980, caching of the SMRAM 812 address region is enabled by setting appropnate bus in the CCRs 982 dunng the SMM entry mstmction sequence and disabled by alternatively setting appropnate bits in the CCRs 982 dunng the SMM exit instmction sequence Advantageously, the overhead of cache flushing is avoided and SMRAM 812 is cacheable dunng SMM Outside of SMM the processor caches are bypassed and ignored, causing all non-SMM accesses to go to the hardware underlymg SMRAM 812. while leaving cached SMRAM lines resident in the cache One complication of the second embodiment is die possibility of "dirty" SMRAM lines (modified data in the cache that does not match data in mam memory) being replaced and wπtten back to main memory outside of SMM . therefore with a deasseπed SMMAD bit 986 To avoid is complication, caching of all SMRAM 812 memory is forced into a wnte-through mode More specifically, while the SMM control register is set, the state of all new cache lines is forced to be shared instead of exclusive or modified A micro-architecture control register (SMRAMD) bit 984 is furnished to oveπide or inhibit the assertion of the SMMAD bit 986 for data access-related SMM bus transactions Accordmgly, access to hardware underlymg SMRAM is achieved All bus transactions to memory dunng SMM and within the address ranges AOOOOH and BFFFFH, by default, take place with the SMMAD bit 986 asserted. The SMRAMD bit 984 enables access by SMM code to the hardware underlymg SMRAM 812. Assertion of SMMAD 986 for code access-related bus transactions withm the AOOOOH through BFFFFH address range is dependent only upon the sett g of the SMM control register bit 988. Assertion of SMMAD 986 for data access-related bus transactions withm the address range AOOOOH through BFFFFH is dependent on both the SMM and SMRAMD bits Typically, both the SMM and SMRAMD bits are set dunng SMM entry and both bits are cleared dunng SMM exit. Dunng SMM, when SMM software is to perform one or more data accesses to the hardware underlying SMRAM 812, the SMM software clears the SMRAMD bit 982, performs accesses to the hardware underlying SMRAM 812, and then set the SMRAMD bit 982. To avoid accidentally accessing cache entnes with the same addresses as the accesses to hardware underlying SMRAM, cacheability of the coπesponding area of SMRAM 812 is temporanly disabled. Accesses to memory outside of the address range AOOOOH through BFFFFH are allowable during the accessing of hardware underlying SMRAM and are processed in a conventional manner. Svstem Embodiments Superscalar processor 120 may be incoφorated into a wide variety of system configurations, illustratively into standalone and networked personal computer systems, workstation systems, multimedia systems, network server systems, multiprocessor systems, embedded systems, integrated telephony systems, video conferencing systems, etc. Figure 11 depicts an illustrative set of suitable system configurations for a processor, such as superscalar processor 120, that has an instmction decoder which implements an adaptable system management mode (SMM). In particular. Figure 11 depicts suitable combinations of a superscalar processor having an mstmction decoder that implements an adaptable system management mode (SMM) with suitable bus configurations, memory hierarchies and cache configurations, I/O interfaces, controllers, devices, and peripheral components. While the invention has been described with reference to vanous embodiments, it will be understood that these embodiments are illustrative and that the scope of the invention is not limited to them. Many variations, modifications, additions, and improvements of the embodiments described are possible. Additionally, structures and functionality presented as hardware in the exemplary embodiment may be implemented as software, firmware, or microcode in alternative embodiments. For example, the description depicts a macroinstmction decoder having short decode pathways including three rotators 430, 432 and 434, three instmction registers 450. 452 and 454 and three shoπ decoders SDecO 410, SDecl 412 and SDec2 414. In other embodiments, different numbers of shoπ decoder pathways are employed. A decoder that employs two decoding pathways is highly suitable. These and other variations, modifications, additions, and improvements may fall within the scope of the invention as defined in the claims which follow.

Claims: WE CLAIM: 1. A computer system for operating in a system management mode (SMM) comprising: a processor including an mstmction decoder: means coupled to the processor for activating a system management activation signal; an instmction memory coupled to the processor for supplying instmctions to the processor, the mstmction memory storing a software program including: an SMM initialization routine: a routine for redirecting SMM operations to an extemal memory; and an SMM termination routine. 2. A computer system according to Claim 1 wherein the means for activating a system management activation signal is selected from a group including: a system management intermpt (SMI) pm; a system management CALL instmction; and an I/O access trap generator including trap handling circuits coupled to a designated I/O trap address range. 3. A computer system according to Claim 1 wherein the SMM initialization routine further compnses: a routine for saving a specification of the cuπent processor state; a routine for saving an instmction pointer; a routine for activating the SMM operating mode; and a routine for setting a SMM micro-architecture control register bit. 4. A computer system according to Claim 1 wherein the routine for redirecting SMM operations to an extemal memory further includes a routine for jumping to an x86 SMM handler code which is located at a specified location in the AOOOOH to BFFFFH address area. 5. A computer system according to Claim 1 wherem the routine for redirecting SMM operations to an external memory further includes: a permission check routme for determmmg whether an I/O access is allowed usmg an x86 I/O instruction; a flag checkmg routme activated when the permission check routine is successful so that I/O access is allowed for checkmg an internal SMMVectorlO flag, and an I/O monitonng routine for monitoring I/O accesses and trapping selected I/O accesses to an SMM handler routine 6 A computer system according to Claim 5 wherein the I/O monitoπng routine further includes a routine operable when a SMM Vector IO flag is set for vectonng to an extemal RISC entry point located in the BIOS area of address space AOOOOH to BFFFFH but at a different location than an "SMM entry" entry point, and a routine operable when the SMM Vector IO flag is not set for executing the remainder of the processor I/O access 7 A computer system according to Claim 1 wherein the SMM termination routine further compnses a routine for monitonng instmction decodes and recognizing decoding of a processor "SMM exit" instmction, a routine responsive to a recognized "SMM exit" instmction for vectonng to an SMM exit entry point in exte al memory, a routine for restonng the processor state that was saved at initialization of SMM, a routine for re-establishing the operating mode of the restored processor state, a routine for clearing the SMM control register bit, and a routme for jumpmg to execution at the saved instmction pointer location, and a routine for exitmg SMM operation 8. A method of operating a computer system m a system management mode (SMM), the computer system includmg a processor and a memory coupled to the processor, the memory including a BIOS area of memory address space, the method compnsing the steps of: receiving an SMM activating signal, recognizing the received SMM activating signal. initializing a SMM entry sequence by vectoring to a RISC instmction in a BIOS area of the memory address space; initializing the SMM; redirecting SMM operations to an extemal memory; and terminating the SMM. 9. A method according to Claim 8 wherein the step of initializing the SMM further includes the steps of: saving a specification of the cuπent processor state: saving an instmction pointer; activating the SMM operating mode; and setting a SMM micro-architecture control register bit. 10. A method according to Claim 8 wherein the redirecting step further comprises the step of jumping to a processor SMM handler code which is located at a specified location in the AOOOOH to BFFFFH address area. 1 1. A method according to Claim 8 wherein the step of redirecting SMM operations to an extemal memory further includes the steps of: determining whether an I/O access is allowed using a processor I/O instmction when the I/O access is allowed, checking an intemal SMM Vector 10 flag; and monitoring all I/O accesses and trapping selected I/O accesses to an SMM handler routine. 12. A method according to Claim 11 wherein the step of redirecting SMM operations to an extemal memory further includes the steps of: if the SMM Vector IO flag is set, vectoring to an extemal memory entry point located in the BIOS area of address space AOOOOH to BFFFFH but at a different location than the "SMM entry" entry point; and if the SMM Vector IO flag is not set, executing the remainder of the accessed I/O instmction. 13. A method according to Claim 8 wherem the step of terminating the SMM further compnses the steps of recognizing decoding of a processor "SMM exit" instmction, in response to a recognized "SMM exit" instmction. vectoring to an SMM exit entry point in extemal memory, restoring the processor state that was saved at initialization of SMM, re-establishing the operating mode of the restored processor state, cleanng the SMM control register bit, jumping to execution at the saved instmction pomter location: and exiting SMM operation 14 An instmction decoder emulation circuit in a processor comprising an mstmction register, an entry point circuit coupled to the instmction register to receive an instmction code, the entry point circuit for deπving an entry pomt from the mstmction code, an emulation code sequencer coupled to the entry point circuit to receive the denved entry point, the emulation code sequencer for directing a sequence of operations (Ops) and generating direction signals in accordance with the directed sequence. an emulation code memory coupled to the emulation code sequencer to receive the direction signals, the emulation code memory stonng a plurality of Op sequences and sequence control codes, the emulation code memory having a first output terminal for outputtmg Op sequences and a second output terminal for outputtmg sequence control codes, the sequence control code output terminal being coupled to the emulation code sequencer, the emulation code memory further includmg: a hardcoded emulation ROM; and an extemal emulation RAM, the extemal emulation RAM including a software program for implementing a system management mode (SMM) 15. An instruction decoder emulation circuit accordmg to Claim 14 wherein the software program for implementing a SMM mcludes: an SMM initialization routme; a routine for redirecting SMM operations to an extemal memory; and an SMM termination routine. 16 An instmction decoder emulation circuit according to Claim 15 wherein the SMM initialization routine further compnses: a routine for saving a specification of the cunent processor state, a routine for saving an stmction pointer; a routine for activating the SMM operating mode; and a routme for settmg a SMM micro-architecture control register bit. 17. An instruction decoder emulation circuit according to Claim 15 wherein the routme for redirectmg SMM operations to an extemal memory further mcludes a routine for jumping to an x86 SMM handler code which is located at a specified location m the AOOOOH to BFFFFH address area 18. An instmction decoder emulation circuit according to Claim 15 wherein the routine for redirectmg SMM operations to an extemal memory further includes a permission check routine for determining whether an I/O access is allowed using an x86 I/O instmction; a flag checking routine activated when die permission check routine is successful so that I/O access is allowed for checkmg an internal SMMVectorlO flag, and an I/O monitonng routine for monitonng I/O accesses and trappmg selected I/O accesses to an SMM handler routme. 19. An mstmction decoder emulation circuit according to Claim 18 wherein the I/O monitonng routme further mcludes: a routine operable when a SMM Vector IO flag is set for vectonng to an extemal RISC entry point located in the BIOS area of address space AOOOOH to BFFFFH but at a different location than an "SMM entry" entry point; and a routine operable when the SMM Vector IO flag is not set for executing the remainder of the processor I/O access. 20. An instmction decoder emulation circuit according to Claim 15 wherein the SMM termination routine further comprises: a routine for monitoring instmction decodes and recognizing decoding of a processor "SMM exit" instmction; a routine responsive to a recognized "SMM exit" instmction for vectoring to an SMM exit entry point in extemal memory; a routine for restoring the processor state that was saved at initialization of SMM; a routine for re-establishing the operating mode of the restored processor state; a routine for clearing the SMM control register bit; and a routine for jumping to execution at the saved instmction pointer location; and a routine for exiting SMM operation. 21 , A computer system comprising: a memory subsystem which stores data and instmctions; and a processor operably coupled to access the data and instmctions stored in the memory subsystem, the processor including: an instmction decoder; means coupled to the processor for activating a system management activation signal; an instmction memory coupled to the processor for supplying instmctions to the processor, the instmction memory storing a software program including: an SMM initialization routine; a routine for redirecting SMM operations to an extemal memory; and an SMM termination routine. 22. In a computer system having a memory subsystem for storing data and instmctions and a processor operably coupled to access the data and instmctions stored in the memory subsystem, the processor being further characterized as comprising: means coupled to the processor for activating a system management activation signal; an instmction memory coupled to me processor for supplying instmctions to the processor, the instmction memory storing a software program including: an SMM initialization routine; a routine for redirecting SMM operations to an extemal memory; and an SMM termination routine.

Inventors: FAVOR JOHN G, WEBER FREDERICK D, FAVOR, JOHN, G., WEBER, FREDERICK, D.
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1996
Main classification: G06F9
IPC codes: G06F7, G06F9