Semiconductor device

Abstract: In a semiconductor apparatus comprises a signal input portion having an amplifying circuit including one, two or more insulating gate type transistors (MIS Tr), one MIS Tr or at least one (M1) of the two or more MIS Trs of the signal input portion is an MIS Tr of one conductivity channel type. The MIS Tr (M1) of the one conductivity channel type is formed in a semiconductor region which is electrically isolated from the other MIS Tr (M3) of one conductivity channel type provided for a circuit portion other than the signal input portion, so that an input threshold level of the signal amplifying circuit is made coincide with a DC level of the input signal, thereby preventing an erroneous operation.

Description: The present invention relates to an inverter including one or two or more insulated gate type transistors such as MOS transistors and which can process, especially, a micro signal. It also concerns a method of operating such an inverter. Such an inverter or inverters have application, for example, to two-stage inverter circuits and multi-stage analogue-to-digital converters as considered hereinbelow. An inverter using MOS transistors of complementary type (hereinbelow, referred to as CMOS) constructed as shown in a schematic circuit diagram of Fig. 1 is considered. That is, in Fig. 1, a source of a P-channel MOS transistor (hereinbelow, referred to as a PMOS Tr) M1 is connected to a V DD power source terminal 100, a drain of the PMOS Tr M1 is commonly connected to a drain of an N-channel MOS transistor (hereinbelow, referred to as an NMOS Tr) M2, a source of the NMOS Tr M2 is connected to a ground terminal 101, gates of the PMOS Tr M1 and NMOS Tr M2 are commonly connected to an input terminal 1, a back gate of the PMOS Tr M1 is connected to the V DD power source terminal 100, and a back gate of the NMOS Tr M2 is connected to the ground terminal 101, thereby constructing a CMOS inverter. An output of the CMOS inverter constructed by the PMOS Tr M1 and NMOS Tr M2 is connected to an input of an internal circuit (a CMOS inverter constructed by a PMOS Tr M3 and an NMOS Tr M4 in a manner similar to the CMOS inverter constructed by the PMOS Tr M1 and NMOS Tr M2 in Fig. 1). In this case, the PMOS Tr M1 of the input inverter and the PMOS Tr M3 of the internal circuit are formed on a same N well 12 as shown in Fig. 2 and the NMOS Tr M2 of the input inverter and the NMOS Tr M4 of the internal circuit are formed on a P-type substrate 15. In Fig. 2, reference numeral 2001 denotes an n - region formed in the P-type substrate 15. The PMOS Trs M1 and M3 are formed in this n - region. Reference numerals 2002, 2003, 2004, and 2005 indicate p + regions formed in the n - region 2001, respectively. In Fig. 2, the p + region 2003 becomes a source region of the PMOS Tr M1, -the p + region 2005 becomes a source region of the PMOS Tr M3, the p + region 2002 becomes a drain region of the PMOS Tr M1, and the p + region 2004 becomes a drain region of the PMOS Tr M3. Reference numerals 2007, 2008, 2009, and 2010 denote gate electrodes of the MOS Trs, respectively; 2006 and 2015 indicate back gates; and 2011, 2012, 2013, and 2014 show n + regions. In Fig. 2, the n + region 2011 becomes a source region of the NMOS Tr M2, the n + region 2013 becomes a source region of the NMOS Tr M4, the n + region 2012 becomes a drain region of the NMOS Tr M2, and the n + region 2014 becomes a drain region of the NMOS Tr M4. The back gate 2006 is set to an n + region in order to obtain a potential of the n- region 2001. The back gate 2015 is set to a p + region in order to obtain a potential of the P-type substrate 15. In the foregoing CMOS inverter, however, when a signal of a micro amplitude is handled, it is important that a threshold level of the CMOS inverter and a DC level of an input signal coincide. In the case where the threshold level of the CMOS inverter is slightly deviated, there is a case where an erroneous operation of the circuit or the like occurs. The invention is made in consideration of the above problem and it is an object of the invention to provide an inverter in which is prevented erroneous operation due to a difference between threshold level of the inverter and the DC level of a micro input signal. The inverter considered herein is of the type, such as disclosed in United States Patent US-A-4791321, comprising: a P-channel insulated gate transistor defined in an n-type semiconductor; an N-channel insulated gate transistor defined in a p-type semiconductor, and which is configured with the P-channel insulated gate transistor to form an inverter wherein the respective gates of the transistors are connected to an input and the respective drains of the transistors are connected together; a pair of supply lines connected respectively to the respective sources of the transistors for applying respective supply potentials thereto; a supply potential source connected to the pair of supply lines for applying the respective supply potentials thereto; wherein the source of at least a respective one of the transistors is connected to the respective supply line without also being connected to the respective semiconductor in which the respective one of the transistors is defined, the respective semiconductor being isolated so as to be able to assume a different potential to that of the respective source. In accordance with the present invention such inverter is characterised by: a source of adjustable potential, which is connected to at least one respective semiconductor to apply thereto a potential or respective potentials adjusted for equalising the respective one or both threshold levels of the transistors of the inverter and the dc level of a signal applied to the input of the inverter. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic circuit diagram for explaining an example of a CMOS inverter circuit; Fig. 2 is a schematic vertical sectional view showing a constructional example of the inverter circuit of Fig. 1; Figs. 3, 5, and 7 are schematic circuit diagrams each for explaining an example of the CMOS inverter circuit of the invention; Figs. 4, 6, and 8 are schematic vertical sectional views for explaining constructional examples of the CMOS inverter circuit shown in Figs. 3, 5, and 7, respectively; Fig. 9 is a schematic circuit diagram for explaining a constructional example of a circuit in the case where the invention is applied to a ν-MOS circuit; Fig. 10 is a schematic circuit diagram for explaining an example of an 8-bit A/D converter using the invention; Fig. 11 is a schematic circuit diagram for explaining an example of the operation of upper two bits of the circuit in Fig. 10; Fig. 12 is a timing chart for explaining an example of the operation of two bits shown in the schematic circuit diagram of Fig. 11; and Fig. 13 is a schematic circuit diagram in the case where a source of adjustable potential is applied to a differential amplifying circuit. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS According to the invention, when schematically speaking, a semiconductor region of a signal input portion in which an insulating gate type transistor is formed is independently provided so as to be electrically isolated from an insulating gate type transistor of a same conductivity channel type provided in a circuit portion other than the signal input portion. With such a construction, a potential of the semiconductor region is independently controlled and V th (threshold voltage) of the insulating gate type transistor of the signal input portion can be controlled, thereby enabling a threshold level of an input of a signal amplifying circuit to coincide with a DC level of an input micro signal. An embodiment of the invention will now be described in detail hereinbelow with reference to the drawings. Figs. 3 and 4 are a schematic circuit diagram and a schematic vertical sectional view each showing the first embodiment of the invention and show a case where the invention is applied to the circuit construction shown in Fig. 1. The same component elements as those in Fig. 1 are designated by the same reference numerals. In Figs. 3 and 4, reference numeral 100 denotes the power source terminal; 101 the ground terminal; 1 the signal input terminal; 200 an output terminal: M1 and M3 the PMOS transistors; and M2 and M4 the NMOS transistors. An input CMOS inverter circuit is constructed by the PMOS Tr M1 and NMOS Tr M2 and an internal CMOS inverter circuit is constructed by the PMOS Tr M3 and NMOS Tr M4, respectively. The PMOS Tr M1 is formed in an N well 10, the PMOS Tr M3 is formed in an N well 12, and the NMOS Trs M2 and M4 are formed on the P-type substrate 15. The N well 10 is connected to a well potential control terminal 20 through a back gate 2006-1 as an n + region. The N well 12 is connected to the power source terminal 100 through the back gate 2006. The P-type substrate 15 is connected to the ground terminal 101 through the back gate 2015 as a p + region. In the above construction, in the case where a signal of a micro amplitude is supplied to the input terminal 1, each time the signal crosses a threshold voltage of the input CMOS inverter, the signal is transmitted to an internal circuit (internal inverter circuit) at the next stage. In the case where a value of the input voltage to the input CMOS inverter is close to a threshold value, both of the PMOS Tr and the NMOS Tr operate in a saturation region. Those drain currents are obtained by the following equations, respectively. I Dp = K p (V DD - V in + V T p ) 2 I Dn = K n (V in - V Tn ) 2 where, V DD denotes a power source voltage; V in a threshold voltage of the CMOS inverter; I Dp a drain current of the PMOS Tr; I Dn a drain current of the NMOS Tr; K a constant; and V T a threshold voltage of the MOS Tr. They are given by the following equations, respectively. K p = µ p C Ox 2 W p L p K n = µ n C Ox 2 W n L n where, µ denotes a mobility of a carrier; C ox an oxide film capacitance; (W p /L p ) or (W n /L n ) a size of the PMOS Tr or the NMOS Tr; W p and W n widths of the transistors; and L p and L n lengths of the transistors. V Tp = T TOp + γ ( 2 f + V SBp - 2 f ) V Tn = T TOn + γ ( 2 f + V SBn - 2 f ) where, T TO : a threshold value when V SB = 0 (V TOp and V TOn denote threshold values of the PMOS Tr and NMOS Tr, respectively)  f : a fermi level potential V SB : a potential between the source and the substrate (V SBn denotes a source-substrate potential of the NMOS Tr and V SBp denotes a source-substrate potential of the PMOS Tr) γ : a parameter A threshold voltage of the CMOS inverter is obtained as follows by assuming that I Dp = I Dn in the equations (1) and (2). V in = V DD + V Tp + K n K p V Tn 1 + K n K p The well potential control terminal 20 in the first embodiment is means for controlling V SBp in the equation (5) and controls the threshold voltage of the CMOS inverter so as to coincide with a DC level of a micro input signal, so that the accurate operation can be realized. It is considered that the threshold voltage of the CMOS inverter which is expressed by the equation (7) changes due to variations in size of MOS Tr, process parameter, and the like. The well potential control terminal 20, however, can correct such variations. Figs. 5 and 6 show a case where the second embodiment of the invention is applied to the circuit construction shown in Fig. 1. In Figs. 5 and 6, the same component elements as those in Fig. 1 are designated by the same reference numerals (the same shall also similarly apply to embodiments which will be described hereinlater). In the second embodiment, a P well 11 in which the NMOS Tr M2 constructing the input CMOS inverter is formed and a P well 13 in which the NMOS Tr M4 in the internal circuit is formed are formed by using n + buried layers 2060-1 to 2060-4 so as to be electrically isolated. The P well 11 is connected to a well potential control terminal 21 through a p + region 2015-1. The P well 13 is connected to the ground terminal 101 through the p + region 2015. Therefore, as compared with the first embodiment in which only the well potential of the PMOS Tr M1 constructing the input CMOS inverter is controlled, the second embodiment is constructed in a manner such that the well potential of the NMOS Tr M2 can be also simultaneously controlled. With such a construction, the threshold voltage of the input CMOS inverter can be controlled in a wider range. In Fig. 6, reference numerals 2061-1 and 2061-2 denote p + regions, respectively. Figs. 7 and 8 show a case where the third embodiment of the invention is applied to the circuit construction shown in Fig. 1. In the third embodiment, the N wells 10 and 12 and the P wells 11 and 13 which are respectively electrically isolated are formed on an SOI substrate having an isolating layer 16 formed on a substrate 8001 such as a semiconductor substrate or the like, the PMOS Tr M1 constructing the input CMOS inverter is formed on the N well 10, the PMOS Tr M3 constructing the internal circuit is formed on the N well 12, the NMOS Tr M2 constructing the input CMOS inverter is formed on the P well 11, and the NMOS Tr M4 constructing the internal circuit is formed on the P well 13. The N wells 10 and 12 are connected to the well potential control terminal 20 and power source terminal 100, respectively. The P wells 11 and 13 are connected to the well potential control terminal 21 and ground terminal 101, respectively. With such a construction, the threshold voltage of the input CMOS inverter can be independently controlled in a wide range in a manner similar to the second embodiment. Fig. 9 shows a circuit according to the forth embodiment of the invention. The embodiment shows a case where the invention is applied to a ν-MOS circuit. In Fig. 9, reference numerals 9001, 9002, 9003, ..., 900n denote signal input terminals and C 1 , C 2 , C 3 , ..., C n indicate capacitors. Terminals on the side opposite to the signal input terminals of the capacitances are commonly connected to an input of the CMOS inverter constructed by the PMOS Tr M1 and NMOS Tr M2, respectively. When signals are supplied to the signal input terminals 9001 to 900n, charges corresponding to the signal inputs are accumulated in the capacitors C 1 to C n by the signal inputs, respectively. A signal is supplied to the CMOS inverter in correspondence to the sum of the accumulated charge amount. Reference numeral 500 denotes an internal circuit connected to an output of the CMOS inverter; 200 the output terminal; and 20 and 21 the potential control terminals of the wells in which the PMOS Tr M1 and NMOS Tr M2 are formed, respectively. In the above construction, an input voltage amplitude of the CMOS inverter constructed by the PMOS Tr M1 and NMOS Tr M2 becomes as follows by assuming that voltages which are supplied to input terminals 1, 2, 3, ..., n are set to V 1 , V 2 , V 3 , ..., V n . V 1 C 1 + V 2 C 2 + V 3 C 3 + ···+V n C n C 1 + C 2 + C 3 +···+ C n For example, when C 1 = C 2 = C 3 = ... = C n = C, 1 n (V 1 + V 2 + V 3 +···+V n ) when C 1 = 1 2 C 2 = 1 4 C 3 =···= 1 2 n-1 C n , 1 2 n - 1 (V 1 + 2 V 2 + 4 V 3 +···+ 2 n-1 V n ) In the case where V 1 = V and V 2 = V 3 = ... = V n = 0, the input amplitudes of the inverters extremely decrease as follows. 1 n V , 1 2 n - 1 V According to the invention, even in the above case, by properly controlling the voltages at the well potential control terminals 20 and 21, the threshold voltage of the CMOS inverter is made coincide with the input DC level, thereby enabling the operation to be accurately performed. Fig. 10 is a circuit diagram showing the fifth embodiment of the invention and shows an example of an 8-bit A/D (analog - digital) converter of a multi-step type constructed by using the foregoing ν-MOS. In Fig. 10, reference numerals 50 to 54 denote CMOS inverters of the invention; 55 to 63 CMOS inverters; C 1 to C 17 the capacitors; 200 to 204 digital output terminals; and 1 the analog input terminal. The analog input terminal 1 is connected to an input of the inverter 50 and is also connected to inputs of the inverters 51, 52, 53, and 54 through the capacitors C 2 , C 5 , C 9 , and C 17 . An output of the inverter 50 is connected to the digital output terminal (MSB) 200 through the inverter 55 and is also connected to inputs of the inverters 51, 52, 53, and 54 through the capacitors C 1 , C 4 , C 8 , and C 16 . An output of the inverter 51 is connected to the digital output terminal 201 through the inverter 57 and is also connected to the inverter 52, 53, and 54 through the capacitors C 3 , C 7 , and C 15 . Hereinafter, outputs of upper bits are sequentially connected to inputs of all of lower inverters through the inverters and capacitors. Thus, an analog signal inputted from the digital output terminal 200 is converted to a digital signal and is outputted. The operation in the above-mentioned construction will now be described with respect to upper two bits shown in Fig. 11 for simplification. When the voltage V 1 which is sufficiently lower than the threshold value of the inverter 50 is supplied to the input terminal 1, the digital output terminal 200 is specified to the low level through the inverters 50 and 55. The resultant signal is inverted by the inverter 56. A voltage of one end of the capacitor C 1 is equal to the power source voltage. Therefore, a voltage at an input point (a) of the inverter 51 is set to a value obtained by dividing a difference between the power source voltage and the voltage V 1 by a capacitance ratio of the capacitors C 1 and C 2 as follows by setting V 1 to a reference. V a = V 1 + C 1 C 1 + C 2 (V DD - V 1 ) At this time, since the voltage V 1 is sufficiently low, a voltage V a is smaller than the threshold value of the inverter 51, so that the output terminal 201 is specified to the low level. As V 1 increases, V a also increases. However, since V 1 < V a , V a first exceeds the threshold value of the inverter 51. Therefore, an output 201 is first inverted and is set to the high level. Further, when V 1 increases and exceeds the threshold value of the inverter 50, the output 200 is inverted and is set to the high level. Thus, a voltage at one end of C 1 is equal to a ground potential. At this time, a potential at the (a) point is set to the following value V a obtained by dividing V 1 by the capacitance ratio of C 1 and C 2 . V a = C 2 C 1 + C 2 V 1 Since the value V a is smaller than the threshold value of the inverter 51, the signal of the inverter 51 is inverted, so that the output 201 is set to the low level. When V 1 further increases, V a increases in proportion to the value V 1 . When V a exceeds the threshold value of the inverter 51, the output 201 is inverted and is set to the high level (refer to Fig. 12). As will be obviously understood from the fourth embodiment, as for the input voltages of the inverters 50 to 54 in the above construction, as the bit is lower, the capacitance dividing ratio decreases and the amplitude decreases. Since a parasitic gate capacitance exists in each of the MOS Trs M1 to M10 constructing the inverters 50 to 54, the voltage which is supplied to each of the inverters is deviated to the DC level by an offset voltage V OS as shown by V a ' in Fig. 12. In this case, a deviation occurs in the timing of the digital output as shown by a broken line V201 in Fig. 12, so that an erroneous operation is causes. Since the CMOS inverters in which the threshold values can be controlled according to the invention are used as inverters 50 to 54, the threshold value of each inverter is controlled so as to coincide with the DC level at each stage, thereby enabling the erroneous operation to be prevented. Fig. 13 is a circuit diagram showing an example where a source of adjustable potential is applied to a differential amplifying circuit. Reference symbols M11 and M12 denote NMOS Trs. A gate of the NMOS Tr M11 is connected to the signal input terminal 1, a drain is connected to the power source 100 through a resistor R1, and a source is connected to the ground terminal 101 together with a source of the NMOS Tr M12 through a current source 501. A gate of the NMOS Tr M12 is connected to a signal input terminal 2 and a drain is connected to the power source 100 through a resistor R2. The drains of the NMOS Trs M11 and M12 are connected to an internal circuit 500, respectively. The NMOS Trs M11 and M12 are formed in wells which are electrically isolated from the NMOS Trs included in the internal circuit. The wells are connected to the well potential control terminal 20 and 21, respectively. In the differential amplifying circuit with the foregoing construction, characteristics of the input MOS Trs M11 and M12 are designed so as to be equalized. In the case where the characteristics are deviated by variations at the time of manufacturing, however, the threshold values are adjusted by the control terminals 20 and 21, thereby enabling the erroneous operation to be prevented. As a source of potential which is connected to the well potential control terminal of the inverter, an arbitrary construction can be used so long as the well can be controlled to a desired potential. In order to give a desired potential, however, it is preferable that the amplitude of the voltage is not large. Therefore, generally, a constant voltage source is preferably used. Even when the constant voltage source is used, it will be obviously understood that the setting itself of the voltage value can be varied to give the necessary potential. In addition, the present invention is not limited to the foregoing embodiments but many modifications and variations are possible within the scope of the appended claims. As described above, according to the invention, a semiconductor integrated circuit device in which by controlling the threshold value of the insulating gate type transistor constructing the amplifier of the signal input means, it can be made to coincide with the DC level of the input signal. Thus, erroneous operation of the inverter can be prevented and accurate operation can be performed even for micro signals.

Claims: An inverter comprising: a P-channel insulated gate transistor (M1) defined in an n-type semiconductor (10); an N-channel insulated gate transistor (M2) defined in a p-type semiconductor (15;11), and which is configured with said P-channel insulated gate transistor (M1) to form an inverter (M1,M2) wherein the respective gates (2007,2009) of the transistors are connected to an input (1) and the respective drains (2002,2012) of the transistors (M1,M2) are connected together; a pair of supply lines (100,101) connected respectively to the respective sources (2003,2011) of said transistors (M1,M2) for applying respective supply potentials (V DD , G ND ) thereto; a supply potential source connected to said pair of supply lines (100,101) for applying said respective supply potentials thereto; wherein the source (2003) of at least a respective one (M1) of the transistors (M1,M2) is connected to the respective supply line (100) without also being connected to the respective semiconductor (10) in which said respective one (M1) of the transistors (M1,M2) is defined, said respective semiconductor (10) being isolated so as to be able to assume a different potential to that of the respective source; characterised by : a source of adjustable potential, which is connected to at least one said respective semiconductor (10) to apply thereto a potential or respective potentials adjusted for equalising the respective one or both threshold levels of the transistors (M1;M1,M2; M1,M2; M1,M2,M3,M4,...) of the inverter (50,51,...54) and the dc level of a signal applied to said input (1) of the inverter. An inverter according to claim 1 wherein: the respective sources (2003,2011) of both transistors (M1,M2) are connected to the respective supply lines (100,101) without also being connected to the respective semiconductor (10,15;10,11) in which the respective transistor having said respective source is defined; and both semiconductors (10,15;10,11) are isolated and connected to said source of adjustable potential. An inverter according to either of claims 1 or 2 wherein one (15) of said semiconductors is a substrate semiconductor and the other one (10) of said semiconductors is a well region semiconductor provided in said substrate semiconductor. An inverter according to either of claims 1 or 2 wherein said semiconductors (10,11) are respective discrete island semiconductors provided on an insulator (16). A two-stage inverter circuit comprising: a first stage inverter (M1,M2), being an inverter according to any preceding claim; and a second stage inverter (M3,M4) comprising P-channel (M3) and N-channel (M4) insulated gate transistors, the gates (2008 & 2010) of which are connected to the connected drains (2002,2012) of said first stage inverter. A circuit according to claim 5 wherein: said first stage inverter is an inverter according to claim 3 depending from claim 1; said first stage inverter (M1,M2) and said second stage inverter (M3,M4) are integrated in a common substrate (15) wherein the insulated gate transistors (M1,M3;M2,M4) of one channel type P or N are defined in a common substrate semiconductor (15), and the insulated gate transistors (M2,M4;M1,M3) of the other channel type N or P are defined in respective discrete wells (10,12) provided in said common substrate (15); and the well semiconductor (10) is connected to said source of adjustable potential. A circuit according to claim 5 wherein: said first stage inverter (M1,M2) is an inverter according to claim 2; and each insulated gate transistor (M1 to M4) is defined in a respective well region (10 to 13) of a common semiconductor substrate (15). A circuit according to claim 5 wherein: each insulated gate transistor (M1 to M4) is defined in a respective discrete island semiconductor (10 to 13) on a common insulator (16). A multistage analogue-to-digital converter wherein each stage (50 to 54) is an inverter as claimed in any of claims 1 to 4. A multistage analogue-to-digital converter according to claim 9 wherein the gate input of each second and subsequent stage inverters (51 to 54) is connected to the input (1) of the first stage inverter (50) via a respective capacitor (C2,C5,C9,...,C17) and to the connected drains of all preceding stage inverters (50 to 53) via respective capacitors (C1,C3 & C4, C6 to C8,...). A multistage analogue-to-digital converter according to claim 10 wherein the connected drains of the respective stage inverters (50 to 54) are connected to a respective output (200 to 204) via a respective inverting amplifier (55,57,59,61,63) and each output is connected to the respective capacitor at the input of each subsequent stage inverter via another inverting amplifier (56,58,60,62). A method of operating the inverter (M1,M2) of claim 1 wherein supply potentials (V DD , V GND ) are applied to the supply lines (100,101) thereof; a signal is applied to said input (1) thereof; and a potential or respective potential are applied to said one or both of said respective semiconductors (10;10,11) of such value as to result in equalisation of the or both respective transistor threshold values and the dc level of the signal applied to said input.

Inventors: OHZU HAYAO, OUCHI AKIHIRO, SAKASHITA YUKIHIKO, OHZU, HAYAO, OUCHI, AKIHIRO, SAKASHITA, YUKIHIKO, OHZU, HAYAO, C/O CANON K.K., Ouchi, Akihiro, c/o Canon K.K., Sakashita, Yukihiko, c/o Canon K.K.
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1996
Main classification: H01L27
IPC codes: H01L27, H01L21