Timer apparatus

Abstract: In a timer apparatus, the clock controlling circuit thereof outputs a clock signal during a period in which an input signal is significant. The counter thereof counts the number of pulses of the clock signal to generate a count-up signal when the value of count gets to a prescribed value. The initialization circuit thereof outputs an initialization signal when the input signal comes not to be significant. The clock controlling circuit stops the output of the clock signal when the count-up signal is generated. Thereby, it is prevented to misjudge the detection of an effective pulse width to get to the effective pulse width though the pulse width of the pulse does not get to the effective pulse width actually.

Description: BACKGROUND OF THE INVENTION Field of the invention: This invention relates to a timer apparatus for detecting a pulse having an effective pulse width. Description of the Prior Art: Fig. 17 is a block diagram showing the structure of a conventional timer apparatus. This timer apparatus is built in an apparatus such as a microcomputer. In the figure, reference numeral 1 denotes a counter counting the number of pulses of a clock signal C. Reference numeral 2 denotes a clock controlling circuit passing a clock signal B while an input signal A is taking the low level of logic levels as shown in Fig. 18. The counter 1 is a down-counter that decreases the value of count thereof by one by every input of a pulse. Next, the operation thereof will be described. The clock signal B is always supplied to the clock controlling circuit 2. As shown in Fig. 18, while the input signal A is taking the low level, the clock signal B passes through the clock controlling circuit 2 to be supplied to the counter 1 as the clock signal C. The counter 1 counts the pulses in the clock signal C; and when the value of count underflows, the counter 1 generates a count-up signal D. Consequently, when a pulse having a pulse width corresponding to a value n set in the counter 1 as an initial value appears in the input signal A as shown in Fig. 18, the count-up signal D is generated. In Fig. 18, diagram (Q) shows the value of count of the counter 1, and the reference characters of the other diagrams correspond to the characters of respective signals in the block diagram. Such a timer apparatus is used for the detection of an effective pulse width. The effective pulse width is defined as a pulse width used as a reference for dealing with an inputted pulse having a pulse width equal to the effective pulse width or more as an effective signal. Such a timer apparatus is used for, for example, the detection of an input by a switch. In that case, the state of on or off of a contact of the switch is inputted as the input signal A. Consequently, when an on-state continues for a prescribed time or more, the count-up signal D is generated. The prescribed time is defined as a time necessary for the counter 1 to count the value n previously set as an initial value in the counter 1. The count-up signal D is used as, for example, an interrupt signal or a flag setting signal of a central processing unit (CPU). The CPU recognizes a depression of the switch by the occurrence of the interrupt signal or the turn on of a flag. If the on-state of the switch does not continue for a time necessary for the counter 1 to count the value n or more, the CPU regards the state as the occurrence of an on-state for a short time owing to a noise or the like, and concludes that the switch was not depressed. If a simple counter is employed as the counter 1, a certain problem occurs. As shown in Fig. 19, if a pulse having a short pulse width F occurred before the occurrence of a pulse having a prescribed pulse width E, namely the effective pulse width, the value of count of the counter 1 advances during the period of the pulse width F. And then, when the pulse having the pulse width E is inputted into the counter 1, the counter 1 resumes counting from the value of count thereof at that point of time. As a result, the counter 1 underflows before the end of the period of the pulse width E. That is to say, the count-up signal D is outputted before the end of the period of the pulse width E. In Figs. 18 and 19, a pulse width corresponding to three clocks of the clock signal C is shown as the prescribed pulse width. Since the conventional timer apparatus is constructed as above, there is a problem that the count-up signal D is outputted though there is no input of a pulse having the effective pulse width. In document EP 0 243 235 A2, there is disclosed a noise pulse suppressing circuit, which comprises a counter circuit, a latch circuit and a logic circuit. SUMMARY OF THE INVENTION In view of the problem described above, the object of the present invention is to provide an improved timer apparatus. This object is achieved by a timer apparatus according to claim 1. An advantageous further development of the present invention is as set out in the dependent claim. BRIEF DESCRIPTION OF THE DRAWINGS Further objects and advantages of the present invention can be more fully understood from the following detailed description taken in conjunction with the accompanying drawings in which: Fig. 1 is a block diagram showing the structure of a timer apparatus according to a first example useful for understanding the invention; Fig. 2 is a timing chart showing an example of the wave forms of signals at respective parts of the timer apparatus shown in Fig. 1; Fig. 3 is a block diagram showing the structure of a timer apparatus according to a second example useful for understanding the invention; Fig. 4 is a timing chart showing an example of the wave forms of signals at respective parts of the timer apparatus shown in Fig. 3; Fig. 5 is a block diagram showing the structure of a timer apparatus according to a third example useful for understanding the invention; Fig. 6 is a timing chart showing an example of the wave forms of signals at respective parts of the timer apparatus shown in Fig. 5; Fig. 7 is a block diagram showing the structure of a timer apparatus according to a fourth example useful for understanding the invention; Fig. 8 is a timing chart showing an example of the wave forms of signals at respective parts of the timer apparatus shown in Fig. 7; Fig. 9 is a block diagram showing the structure of a timer apparatus according to a fifth example useful for understanding the invention; Fig. 10 is a timing chart showing an example of the wave forms of signals at respective parts of the timer apparatus shown in Fig. 9; Fig. 11 is a block diagram showing the structure of a timer apparatus according to a first embodiment of the present invention; Fig. 12 is a timing chart showing an example of the wave forms of signals at respective parts of the timer apparatus shown in Fig. 11; Fig. 13 is a block diagram showing the structure of a timer apparatus according to a second embodiment of the present invention; Fig. 14 is a timing chart showing an example of the wave forms of signals at respective parts of the timer apparatus shown in Fig. 13; Fig. 15 is a block diagram showing the structure of a timer apparatus according to a sixth example useful for understanding the invention; Fig. 16 is a timing chart showing an example of the wave forms of signals at respective parts of the timer apparatus shown in Fig. 15; Fig. 17 is a block diagram showing the structure of a conventional timer apparatus; Fig. 18 is a timing chart showing an example of the wave forms of signals at respective parts of the timer apparatus shown in Fig. 17; and Fig. 19 is a timing chart showing another example of the wave forms of signals at respective parts of the timer apparatus shown in Fig. 17. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments of the present invention will now be described in detail in conjunction with the accompanying drawings. Fig. 1 is a block diagram showing the structure of a timer apparatus according to a first example useful for understanding the invention. In the figure, reference numeral 1 denotes a counter counting the number of pulses in a clock signal C. Reference numeral 21 denotes a clock controlling circuit passing a clock signal B while an input signal A is taking the low level (significant) of logic levels. Reference numeral 3 denotes an initialization circuit generating an initialization signal G for initializing the value of count of the counter 1 when a rise occurs in the input signal A. A down-counter decreasing the value of count thereof by one by every input of a pulse is used as the counter 1. The counter 1 freely runs in accordance with the input of a clock. That is to say, the counter 1 takes an initial value n to continue counting at the time of the underflow of the value of count. In the present example, an effective pulse width information controlling means is realized by the clock controlling circuit 21 and the initialization circuit 3. A signal controlling means is realized by the clock controlling circuit 21. Next, the operation thereof will be described. The clock signal B is always supplied to the clock controlling circuit 21. The clock controlling circuit 21 passes the clock signal B to supply it to the counter 1 as the clock signal C while the input signal A is taking the low level. The counter 1 counts the number of pulses in the clock signal C. The initializing circuit 3 receives the input signal A, and observes the occurrence of a rise of the input signal A. It is supposed that a pulse having a pulse width a1 shorter than a prescribed pulse width, or the effective pulse width, occurred in the input pulse A and the value of count of the counter 1 decreased by two during the pulse width, as shown in Fig. 2. But, the initialization circuit 3 generates an initialization signal G at the time of detecting the rise of the pulse having the pulse width a1. In Fig. 2, the initialization signal G is denoted by a reference character g1. The counter 1 resets the value of count thereof to the initial value n in response to the initialization signal G. Consequently, there is no case where the counter 1 resumes the count thereof from the value of count that was counted at the last time when the next pulse appears in the input signal A, and the counter 1 always resumes the count thereof from the initial value n. In Fig. 2, the diagram (Q) shows values of count of the counter 1, and the other diagrams illustrate respective signals in the block diagram denoted by the characters corresponding to the characters written on the left side of each diagram. The pulse width corresponding to three clocks of the clock signal C is shown as the prescribed pulse width. When a pulse having a pulse width a2 longer than the prescribed pulse width is inputted into the present example, the counter 1 outputs a count-up signal D at the time of passing a period corresponding to the prescribed pulse width. In Fig. 2, the count-up signal D is denoted by a reference character d1. The count-up signal D is inputted into the clock controlling circuit 21, too. When the clock controlling circuit 21 receives the count-up signal D, the circuit 21 prohibits the clock signal B from passing it even if the input signal A takes the low level then. Consequently, the count-up signal D is not outputted after that during the period of the pulse width a2. The clock controlling circuit 21 removes the prohibition of the passing of the clock signal B when the next fall appears in the input signal A. Thus, it is prevented that the count-up signal D is outputted before the period corresponding to the prescribed pulse width has passed. Besides, the count-up signal D is not outputted after the period corresponding to the prescribed pulse width has passed, even if a pulse having a pulse width equal to the prescribed pulse width or more is inputted. Thereby, there is obtained the advantage that the amount of processes of a CPU is decreased. For example, supposing that the pulse width a2 is double the prescribed pulse width or more, the count-up signal D is outputted twice or more if the passing of the clock signal B is not prohibited. If the count-up signal D is inputted into a CPU as an interrupt signal or a flag setting signal, the CPU must execute a process to distinguish a first time count-up signal D from a second time count-up signal D. As an example, a description will be given to the case where the input signal A indicates the state of on or off of a contact of a switch. If the switch is depressed for a long time, a pulse having a long pulse width appears in the input signal A. But, since the switch is depressed only once, it is desirable that the count-up signal D appears only once. If the embodiment 1 is not applied, there is a probability that the count-up signal is generated twice or more. If the count-up signal is generated twice or more, the CPU must execute a process for distinguishing whether the switch is depressed only once, or twice or more. According to the embodiment 1, such a load of the CPU is decreased. Fig. 3 is a block diagram showing the structure of a timer apparatus according to a second example useful for understanding the invention. In the figure, reference numeral 9 denotes a count-up detecting circuit generating an output signal K on the basis of an input signal A and a count-up signal D. The other composing elements are the same as those of the embodiment 1 or those shown in Fig. 17. In this case, an effective pulse width information controlling means is realized by the initialization circuit 3 and the count-up detecting circuit 9. A signal controlling means is realized by the count-up detecting circuit 9. Next, the operation thereof will be described. It is identical to the first example that, even if a pulse having a pulse width shorter than a prescribed pulse width is inputted, the counter 1 is initialized at the time of the rise of the pulse. But, since the counter 1 is one that freely runs according to the input of clocks, and since the count-up signal D is not inputted into the clock controlling circuit 2, then if a pulse having a pulse width double the prescribed pulse width or more appears in the input signal A, the counter 1 outputs the count-up signal D twice or more. In Fig. 4, the count-up signal D is denoted by reference characters d1 and d2. The count-up detecting circuit 9 outputs an output signal K when a first time count-up signal D (d1) is generated after the fall of the input signal A. That is to say, the occurrence of the output signal K signifies the occurrence of the first time count-up signal D. In Fig. 4, the output signal K is denoted by a reference character k. The counter 1 later outputs a second time count-up signal D (d2) as shown in Fig. 4. But, the count-up detecting circuit 9 refuses the second time count-up signal D and ones after that while the input signal A are taking the low level. Consequently, if a pulse appears in the input signal A, the output signal K is outputted once at the most. The count-up detecting circuit 9 is reset to the initial state thereof when a rise occurs in the input signal A. According to the second example, also, it is prevented that the count-up signal D is outputted before the end of a period corresponding to a prescribed pulse width. Furthermore, even if a pulse having a pulse width equal to the prescribed pulse width or more is inputted, the output signal K is not outputted after the period corresponding to the prescribed pulse width has passed. Thereby, if the output signal K is supplied to a CPU as an interrupt signal or a flag setting signal, there is obtained the advantage that the processes of the CPU is decreased. It may be applicable to compose the structure of the invention so that the count-up signal D, as well as the output signal K, is outputted to the CPU side as an interrupt signal or a flag setting signal. In that case, to the CPU is provided the count-up signal D that is generated at every point of time when the input signal A has been taking the low level for the prescribed time, together with the output signal K that signifies the point of time of the first time occurrence of the count-up signal D, namely signifies the point of time when the input signal A has been taking the low level for the prescribed time. Accordingly, the CPU can execute processes such as detecting the time of the depression of a switch on the basis of the frequency of the occurrence of the count-up signal D as well as detecting the depression of the switch surely. The CPU can also execute such a process as detects the depression of the switch more surely on the basis of the frequency of the occurrence of the count-up signal D. Fig. 5 is a block diagram showing the structure of a timer apparatus according to a third example useful for understanding the invention. In the figure, reference numeral 10 denotes a count-up frequency measuring circuit counting the frequency of the occurrence of the count-up signal D from the counter 1. The other composing elements are the same as those of the embodiment 1 or those shown in Fig. 17. In this case, an effective pulse width information controlling means is realized by the initialization circuit 3 and the count-up frequency measuring circuit 10. Next, the operation thereof will be described. It is identical to the first and second examples that the counter 1 is initialized at the time of the rise of an inputted pulse having a pulse width a1 shorter than a prescribed pulse width. The counter 1 generates a count-up signal D at every occurrence of underflow while the input signal A is taking the low level. In Fig. 6, the count-up signal D is denoted by reference characters d1, d2 and d3. A prescribed frequency is previously set in the count-up frequency measuring circuit 10. The count-up frequency measuring circuit 10 counts the frequency of the occurrence of the count-up signal D to output an output signal K when the frequency of the occurrence gets to the prescribed frequency while the input signal A is taking the low level. Fig. 6 illustrates the case where the prescribed frequency is three. And, Fig. 6 also illustrates the case where a pulse having a pulse width a2 longer than the pulse width corresponding to the maximum value of count of the counter 1 is inputted. This third example is effective especially for the case where the number of bits of the counter 1 is short for the pulse width which an operator wants to detect. That is to say, the third example is effective for the case where an operator wants to detect a pulse width longer than the pulse width corresponding to the maximum value of count of the counter 1 as the prescribed pulse width. In this case, the prescribed pulse width, or the effective pulse width, is one corresponding to the value of count of (the maximum value of count of the counter 1) _ ~ 3. But, an arbitrary prescribed frequency can be set in the count-up frequency measuring circuit 10. That is to say, an arbitrary pulse width can be detected as a prescribed pulse width by taking the maximum value of count of the counter 1 as a unit. The output signal K is used as, for example, an interrupt signal or a flag setting signal of a CPU. By the output signal K, the CPU can immediately recognize that a pulse signal having a pulse width equal to the prescribed pulse width or more was inputted. If there is no count-up frequency measuring circuit 10, the process of count must be executed by software. The structure of the present invention may be composed so that the count-up signal D, as well as the output signal K, is outputted to the CPU side as an interrupt signal or a flag setting signal. In this case, the description was given to the case where the initial value of the counter 1 was set as the maximum value of count, but a value smaller than the maximum vale may be set as the initial value. Moreover, if the initial value of the counter 1 and the prescribed frequency in the count-up frequency measuring circuit 10 are suitably set, a prescribed pulse width having an arbitrary width can be detected. Fig. 7 is a block diagram showing the structure of a timer apparatus according to a fourth example useful for understanding the invention. In the figure, reference numeral 11 denotes a count-up frequency measuring circuit counting the frequency of the occurrence of the count-up signal D from the counter 1. The other composing elements are the same as those of the first example or those shown in Fig. 17. In this case, an effective pulse width information controlling means is realized by the initialization circuit 3 and the count-up frequency measuring circuit 11. A signal controlling means is realized by the count-up frequency measuring circuit 11. Next, the operation thereof will be described. It is identical to the first to third examples that the counter 1 is initialized at the time of the rise of an inputted pulse having a pulse width a1 shorter than a prescribed pulse width. The counter 1 generates a count-up signal D at the time of every occurrence of underflow. In Fig. 8, the count-up signal D is denoted by reference characters d1, d2 and d3. The count-up frequency measuring circuit 11 counts the frequency of the occurrence of the count-up signal D. Then, the count-up frequency measuring circuit 11 outputs the value of count at the time of the rise of the input signal A as the output signal K. According to the fourth example, the pulse width of an inputted pulse can easily be measured even if the number of bits of the counter 1 is short for the pulse width of the inputted pulse. That is to say, if the output signal K is supplied to a CPU as an interrupt signal or a flag setting signal, the CPU can immediately recognize the pulse width on the basis of the output signal K. Fig. 9 is a block diagram showing the structure of a timer apparatus according to a fifth example useful for understanding the invention. In the figure, reference numeral 12 denotes a count-up frequency measuring circuit counting the frequency of the occurrence of the count-up signal D from the counter 1. In this case, the input signal A is not supplied to the count-up frequency measuring circuit 12, which is different from in the third example. The other composing elements are the same as those of the first example. Next, the operation thereof will be described. It is identical to the first to fourth example that the counter 1 is initialized at the time of the rise of an inputted pulse having a pulse width a1 shorter than a prescribed pulse width. The counter 1 generates the count-up signal D at the time of every occurrence of underflow. Similarly in the case of the first example, the clock controlling circuit 2 stops the output of the clock signal C when the count-up signal D is generated. Fig. 10 illustrates the input of respective pulses having pulse widths a21, a22 and a23 longer than the prescribed pulse width respectively. The count-up signal D corresponding to each pulse is denoted by reference characters d1, d2 and d3 respectively. A prescribed frequency is previously set in the count-up frequency measuring circuit 12. The count-up frequency measuring circuit 12 counts the frequency of the occurrence of the count-up signal D to output an output signal K when the frequency of occurrence gets to the prescribed frequency. Fig. 10 shows the case where the prescribed frequency is three. The count-up frequency measuring circuit 12 continues counting the frequency of occurrence whether the input signal A continues taking the low level or not. The fifth example is especially effective for the case of the detection of whether pulses having pulse widths equal to a prescribed pulse width or more are inputted by a prescribed frequency or not. The output signal K is used as, for example, an interrupt signal or a flag setting signal of a CPU. By the output signal K, the CPU can immediately recognize that pulses having pulse widths equal to a prescribed pulse width or more were inputted by a prescribed frequency. If the input signal A indicates the state of on or off of a contact of a switch, the CPU can immediately recognize that the effective depressions of the switch were made by the prescribed frequency. If there is no count-up frequency measuring circuit 10, the process of count must be executed by software. The structure of the present invention may be composed so that the count-up signal D, as well as the output signal K, is outputted to the CPU side as an interrupt signal or a flag setting signal. EMBODIMENT 1. Fig. 11 is a block diagram showing the structure of a timer apparatus according to a first embodiment (embodiment 1) of the present invention. In the figure, reference numeral 14 denotes a one-shot pulse controlling circuit generating a one-shot pulse J that rises in accordance with a fall of the input signal A and falls in accordance with a rise of the input signal A or the occurrence of a count-up signal D. Reference numeral 16 denotes an effective pulse width detecting circuit judging whether a fall of the one-shot pulse J was caused by a count-up of the counter 1 or not. Reference numeral 31 denotes an initialization circuit outputting an initialization signal G in accordance with a fall of the input signal A. The other composing elements are the same as those in the first example or those shown in Fig. 17. In this case, an effective pulse width information controlling means is realized by the initialization circuit 31, the one-shot pulse controlling circuit 14 and the effective pulse width detecting circuit 16. A signal controlling means is realized by the one-shot pulse controlling circuit 14 and the effective pulse width detecting circuit 16. Next, the operation thereof will be described. The clock controlling circuit 2 passes the clock signal B to supply it to the counter 1 as the clock signal C while the input signal A is taking the low level. The counter 1 counts the number of pulses in the clock signal C. The initialization circuit 31 receives the input signal A and observes the occurrence of a fall of the input signal A. As shown in Fig. 12, it is supposed that a pulse having a pulse width a1 shorter than a prescribed pulse width appears in the input signal A and the value of count of the counter 1 decreased by one. But, the initialization circuit 31 generates an initialization signal G when the circuit 31 detects a fall of the next pulse. In Fig. 12, the initialization signal in this case is denoted a reference character g2. The counter 1 resets the value of count thereof to an initial value n in response to the initialization signal G. Consequently, according to the embodiment 1, too, the counter 1 always resumes the count thereof from the initial value n in stead of resuming the count thereof from the value of count that was counted at the last time, when the next pulse appears in the input signal A. The one-shot pulse controlling circuit 14 is realized by, for example, a flip-flop. If the one-shot pulse controlling circuit 14 is realized by the flip-flop, the circuit 14 is set by a fall that occurred in the input signal A and is reset by a rise that occurred in the input signal A or by the occurrence of a count-up signal D. Consequently, if a pulse having a pulse width a1 shorter than the prescribed pulse width is generated, as shown in Fig. 12, the circuit 14 is set by the fall of the pulse and is reset by the rise of the pulse. Then, a one-shot pulse J having a pulse width corresponding to the pulse width a1 shorter than the prescribed pulse width is outputted. The effective pulse width detecting circuit 16 judges whether the fall of a one-shot pulse J is caused by a count-up of the counter 1 or not. If the input signal A continues taking the low level, it can be identified that the one-shot pulse J fell owing to a count-up of the counter 1. In this case where a pulse having a pulse width a1 shorter than the prescribed pulse width was generated, since the input signal A returned to the high level of logic levels, it is judged that the one-shot pulse J did not fall owing to a count-up of the counter 1. If the effective pulse width detecting circuit 16 judged so, the circuit 16 does not output the output signal K. When a pulse having the pulse width a2 longer than the prescribed pulse width is generated, the one-shot pulse controlling circuit 14 resumes the output of the one-shot pulse J in accordance with a fall of the generated pulse. When the counter 1 underflows, the counter 1 outputs a count-up signal D. The one-shot pulse controlling circuit 14 makes the one-shot pulse J fall in accordance with the occurrence of the count-up signal D. Since the input signal A continues taking the low level, the effective pulse width detecting circuit 16 judges that the one-shot pulse J fell owing to a count-up of the counter 1. Accordingly, the effective pulse width detecting circuit 16 outputs an output signal K as shown in Fig. 12. If the pulse width a2 is double the prescribed pulse width or more, the counter 1 again underflows to generate a count-up signal D (d2). But, since the one-shot pulse J is not outputted at that time, the output signal K does not outputted. As described above, according to the embodiment 1, too, it is prevented that the count-up signal D is outputted before a period corresponding to the prescribed pulse width has passed. Moreover, the output signal K is not outputted after the period corresponding to the prescribed pulse width has passed, even if a pulse having a pulse width equal to the prescribed pulse width or more is inputted. Consequently, there is obtained the advantage that a CPU can decrease the load thereof for processing. For instance, if the output signal K is inputted to the CPU as an interrupt signal or a flag setting signal, by the output signal K can the CPU immediately recognize that a pulse having a pulse width equal to the prescribed pulse width or more was inputted. The structure of the present invention may be constructed so that the count-up signal D, as well as the output signal K, is outputted to the CPU side as an interrupt signal or a flag setting signal. The description, here, was given to the case where the one-shot pulse J having the high level was used, but the one-shot pulse J may be one having the low level. EMBODIMENT 2. Fig. 13 is a block diagram showing the structure of a timer apparatus according to a second embodiment (embodiment 2) of the present invention. In the figure, reference numeral 17 denotes an effective pulse width detecting circuit judging whether a fall of the one-shot pulse J was caused by a count-up of the counter 1 or not, and generating a clear signal N if the one-shot pulse J did not fall owing to the count-up of the one-shot pulse J. Reference numeral 18 denotes a continuous pulse counting circuit counting the frequency of the output of the output signal K. The other composing elements are the same as those of the embodiment 1. In this case, an effective pulse width information controlling means is realized by the initialization circuit 31, the one-shot pulse controlling circuit 14 and the effective pulse width detecting circuit 17. A signal controlling means is realized by the one-shot pulse controlling circuit 14 and the effective pulse width detecting circuit 17. Next, the operation thereof will be described. The clock controlling circuit 2 passes the clock signal B to supply to the counter 1 as the clock signal C while the input signal A is taking the low level. The counter 1 counts the number of pulses in the clock signal C. The initialization circuit 31 receives the input signal A and observes the occurrence of a fall in the input signal A. It is identical to the embodiment 1 that, even if a pulse having a pulse width a1 shorter than a prescribed pulse width is inputted, the counter 1 is initialized at the time of a fall of the next pulse. When the counter 1 underflows, the counter 1 outputs a count-up signal D. The one-shot pulse controlling circuit 14 makes the one-shot pulse J fall in response to the occurrence of the count-up signal D. The effective pulse width detecting circuit 17 operates similarly to the effective pulse width detecting circuit 16 in the embodiment 1. Namely, the effective pulse width detecting circuit 17 outputs an output signal K when the circuit 17 judges that the one-shot pulse J fell owing to a count-up of the counter 1. For example, the circuit 17 outputs the output signal K (k0) when a pulse having a pulse width a20 longer than a prescribed pulse width is inputted, as shown in Fig. 14. The effective pulse width detecting circuit 17 generates a clear signal N when the circuit 17 judges that the one-shot pulse J did not fall owing to a count up of the counter 1. The clear signal N is supplied to the continuous pulse counting circuit 18. A prescribed frequency is set in the circuit 18. The circuit 18 counts the frequency of the occurrence of the output signal K to output an output signal M when the frequency of occurrence gets to the prescribed frequency. But, the value of count of the circuit 18 is cleared by the clear signal N. Consequently, the value of count of the continuous pulse counting circuit 18 is initialized when a pulse having a pulse width a1 shorter than the prescribed pulse width is inputted, even if the value of count of the circuit 18 advanced during the period in which the pulse having the pulse width a20 was inputted. The reason is that the effective pulse width detecting circuit 17 generates the clear signal N. If pulses respectively having pulse widths a21, a22 and a23 longer than the prescribed pulse width are continuously inputted, the effective pulse width detecting circuit 17 continuously outputs the output signals K (k1, k2, k3) without generating the clear signal N. Thereby, the value of count of the continuous pulse counting circuit 18 advances. When the value of count gets to the value set as the prescribed frequency, the circuit 18 generates an output signal M. Fig. 14 illustrates the case where the prescribed frequency is three. The output signal M is one indicating that pulses having pulse widths longer than the prescribed pulse width, or the effective pulse width, are continuously inputted by the prescribed frequency. The output signal M is used as, for instance, an interrupt signal or a flag setting signal of a CPU. By the output signal M can the CPU immediately recognize that pulses having pulse widths longer than the prescribed pulse width were continuously inputted by the prescribed frequency. If the input signal A indicates the state of on or off of a switch, the CPU can immediately recognize that the switch is surely depressed by the prescribed times. Fig. 15 is a block diagram showing the structure of a timer apparatus according to a sixth example useful for understanding invention. In the figure, reference numeral 1 denotes a counter counting the number of pulses in a clock signal C. Reference numeral 22 denotes a clock controlling circuit beginning the passing of a clock signal B in response to an initialization signal G and stopping the passing of the clock signal B in response to a stop signal L. Reference numeral 32 denotes an initialization / clock control signal generating circuit generating the initialization signal G when a fall occurs in an input signal A. Next, the operation thereof will be described. The clock signal B is always supplied to the clock controlling circuit 22. The initialization /clock control signal generating circuit 32 receives the input signal A and observes the occurrence of a rise and a fall in the input signal A. When a fall occurs in the input signal A, the initialization / clock control signal generating circuit 32 generates the initialization signal G. In Fig. 16, the initialization signal G is denoted by reference characters g1 and g2. The initialization signal G is supplied to the clock controlling circuit 22. When the clock controlling circuit 22 receives the initialization signal G, the circuit 22 outputs the clock signal B as the clock signal C. The initialization signal G is supplied to the counter 1, too. The counter 1 is initialized by the input of the initialization signal G. The counter 1 counts the number of pulses in the clock signal C. Then, the counter 1 generates the count-up signal D when the value of count underflows. In Fig. 16, the count-up signal D is denoted by a reference character d1. When a rise occurs in the input signal A, the initialization / clock control signal generating circuit 32 generates the stop signal L. In Fig. 16, the stop signal L is denoted by reference characters L1 and L2. The stop signal L is supplied to the clock controlling circuit 22. The clock controlling circuit 22 stops the output of the clock signal C when the circuit 22 receives the stop signal L. Consequently, the value of count of the counter 1 comes not to change. Since the counter 1 is initialized in response to a fall in the input signal A, the counter 1 holds the value of count thereof from the point of time of the end of the pulse having a pulse width a1 to the point of time of the beginning of the pulse having a pulse width a2. Fig. 16 illustrates the state in which a value of count (n - 2) is held. When the next fall appears in the input signal A, the initialization signal G is outputted from the initialization / clock control signal generating circuit 32. Consequently, the value of count of the counter 1 is reset to the initial value n. The value of counts of the counter 1 are supplied to a CPU, for instance. As described above, if a pulse having a pulse width shorter than the prescribed pulse width is inputted, the value of count at the time of the end of the pulse is held in the counter 1. Then, the CPU can recognize the held value of count. That is to say, the CPU can easily recognize the pulse width of an inputted pulse. The examples using a down-counter as the counter 1 were shown in the respective embodiments described above, but an up-counter may be used as the counter 1. Also, all of the embodiments dealt the input signal A in which the low level of logic levels was significant, but an input signal A in which the high level of the logic levels is significant may be applicable. Furthermore, in each embodiment and/or unclaimed example using the initialization circuit 3 generating the initialization signal G at the time of a rise of the input signal A, an initialization circuit 31 generating the initialization signal G at the time of a fall of the input signal A may be used in stead of the initialization circuit 3. Moreover, in each embodiment and/or unclaimed example using the initialization circuit 31 generating the initialization signal G at the time of a fall of the input signal A, an initialization circuit 3 generating the initialization signal G at the time of a rise of the input signal A may be used in stead of the initialization circuit 31. Although the descriptions were given to the advantages in the case where the outputs of the timer apparatus according to the respective embodiments and/or unclaimed examples described above were supplied to the CPU, the outputs of the respective timer apparatus can be supplied to various kinds of control apparatus. Moreover, the descriptions were given to the case where the information concerning the state of on or off of a switch was used as the input signal A. But the input signal A is not limited to the information concerning the state of on or off of a switch. Various kinds of detected information and the like can be employed as the input signal A. As described above, according to a first aspect, the timer apparatus is constructed to process a count-up signal of a counter by the effective pulse width controlling means as the information indicating an effective pulse width of an input signal, and consequently, there is obtained the advantage that it is prevented that a pulse having the effective pulse width is not misjudged to have been inputted though the pulse was not inputted actually, and the advantage that the count-up signal is not outputted after a period corresponding to the effective pulse width has passed, even if a pulse having a pulse width equal to the effective pulse width or more is inputted. Furthermore, according to a second aspect, the timer apparatus is constructed to process the first count-up signal during a period in which an input signal is significant as the information indicating the effective pulse width, and consequently, there is obtained the advantage that it is prevented that a pulse having the effective pulse width is misjudged to have been inputted though the pulse was not inputted actually, and the advantage that an outer control apparatus can immediately judge the input of a pulse having the effective pulse width. Furthermore, according to a third aspect, the timer apparatus is constructed so that a clock controlling circuit stops the output of clock signals when a value of count of the counter takes one indicating a prescribed value, and consequently, there is obtained the advantage that it is prevented that a pulse having the effective pulse width is misjudged to have been inputted though the pulse was not inputted actually without adding any circuit element, and the advantage that a count-up signal is not outputted after a period corresponding to the effective pulse width has passed even if a pulse having a pulse width equal to the effective pulse width or more is inputted. Furthermore, according to a fourth aspect, the timer apparatus is constructed to count the frequency of the occurrence of a signal indicating the effective pulse width by a count-up frequency measuring circuit, there is obtained the advantage that it can immediately be detected whether or not pulses having pulse widths equal to the effective pulse width or more are inputted by a prescribed frequency. Furthermore, according to a fifth aspect, the timer apparatus is constructed to extract a count-up signal at a prescribed frequency of occurrence during a period in which an input signal is significant, and consequently, there is obtained the advantage that it is possible to detect an effective pulse width having an arbitrary width. Furthermore, according to one aspect of the present invention, the timer apparatus is constructed to include a one-shot pulse controlling circuit generating a one-shot pulse beginning at the time of the beginning of a significant period of an input signal and ending at the time of the end of the period or at the time of the generation of an output signal by the counter, and an effective pulse width detecting circuit extracting a count-up signal if the pulse width of the one-shot pulse is a prescribed value or more, and consequently, there is obtained the advantage that it is prevented that a pulse having the effective pulse width is misjudged to have been inputted though the pulse was not inputted actually without altering the clock controlling circuit from a conventional one, and the advantage that a count-up signal is not outputted after a period corresponding to the effective pulse width has passed even if a pulse having a pulse width equal to the effective pulse width or more is inputted. Furthermore, according to another aspect of the present invention, the timer apparatus is constructed to include a continuous pulse counting circuit counting the frequency of the output of a signal by the effective pulse width detecting circuit, and consequently, there is obtained the advantage that an outer control apparatus can immediately recognize that pulses having pulse widths equal to the effective pulse width or more continuously inputted by a prescribed frequency. Furthermore, according to a further aspect, the timer is constructed to include an initialization / clock control signal generating circuit initializing the counter thereof at the time of the beginning of a significant period of an input signal, and prohibiting the output of a clock signal by the clock controlling circuit thereof at the time of the occurrence of a count-up signal, and consequently, there is obtained the advantage that it is prevented that a pulse having the effective pulse width is misjudged to have been inputted though the pulse was not inputted actually, and the advantage that the pulse width of an inputted pulse can be easily recognized.

Claims: A timer apparatus including a clock controlling circuit (2, 21) for outputting a clock signal during a period in which an input signal is significant and a counter (1) counting a number of pulses of the clock signal to generate a count-up signal when a value of count thereof takes a prescribed value, the timer apparatus comprises an effective pulse width information controlling means (3, 9, 10, 11, 12, 14, 16, 17, 31) for processing said count-up signal as information indicating an effective pulse width of said input signal, wherein said effective pulse width information controlling means includes a signal controlling means (3, 9, 10, 11, 12, 14, 16, 17) for processing a first count-up signal during a period in which said input signal is significant as information indicating said effective pulse width, characterized in that said signal controlling means includes a one-shot pulse controlling circuit (14) generating a one-shot pulse beginning at a time of a beginning of a significant period of said input signal and ending at a time of an end of the period or at a time of generation of a count-up signal by said counter, and an effective pulse width detecting circuit (16, 17) extracting an output signal if a pulse width of the one-shot pulse is a prescribed value or more. The timer apparatus according to claim 1, which further comprises a continuous pulse counting circuit (18) counting a frequency of output of a signal by said effective pulse width detecting circuit.

Inventors: WAKIMOTO AKIHIKO, WAKIMOTO, AKIHIKO
Applicants: MITSUBISHI ELEC SEMICONDUCTOR, MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA, MITSUBISHI ELECTRIC SEMICONDUCTOR SOFTWARE CO., LTD.
Application year: 1996
Main classification: H03K5
IPC codes: G04F10, H03K5, H04L7