High electron mobility transistor comprising an InAs/InGaAs superlattice

Abstract: In an InAlAs/InGaAs heterojunction field type semiconductor device including an InP substrate (1), a superlattice layer (11∼18) formed by periods of InAs/AlAs or InAs/AlGaAs is formed over an InGaAs channel layer (3) which is formed over the InP substrate.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a semiconductor device, and more particularly, to an InAlAs/InGaAs heterojunction field effect type semiconductor device formed on an InP substrate. Description of the Related Art A prior art heterojunction field effect type semiconductor device is constructed by an InP substrate, an InAlAs/InGaAs heterostructure formed on the InP substrate, an InAlAs Schottky layer formed on the heterojunction, and electrodes formed on the InAlAs Schottky layer. These layers are sequentially epitaxially grown. This will be explained later in detail. The fabrication of the device, however, generally requires some thermal treatments after growth, so that the electrical quality are degraded. That is, during the thermal treatments, impurity atoms adhered to the surface of epitaxial layers are thermally diffused thereinto, to thereby deteriorate the crystalline quality of the epitaxial layers (see: N. Hayafuji et al., "Thermal Stability of AlInAs/GaInAs/InP Heterostructures", Appl Phys. Lett. 66 (7), pp. 863-865, February 1995). From US-A-5,206,528 a field effect transistor according to the preamble of claim 1 is known comprising a current channel layer formed on an InP substrate through a buffer layer and formed of InGaAs having a lattice constant in match with that of InP. An insulator layer is formed on the current channel layer between the source electrode and a drain electrode, being composed of a superlattice formed of alternately stacked undoped InAs thin films and undoped AlAs thin films, wherein a ratio t1/t2 of the thickness t1 of each one InAs thin film and the thickness t2 of one AlAs thin film adjacent to each one InAs thin film is gradually reduced toward to an upper surface of the superlattice layer. From JP-A-7-142,513 a heterojunction field effect device is known having a superlattice layer including InGaAs material. SUMMARY OF THE INVENTION It is an object of the present invention to provide an InAlAs/InGaAs heterojunction field effect type semiconductor device which can suppress the degradation of the crystalline quality due to the thermal treatments. According to the present invention, in an InAlAs/InGaAs heterojunction field effect type semiconductor device including an InP substrate, a superlattice layer formed by periods of InAs/AlAs or InAs/AlGaAs is formed over an InGaAs channel layer which is formed over the InP substrate. The superlattice layer suppresses the diffusion of impurity atoms adhered to the surface of the device into the interior thereof. A device according to the present invention is defined in claim 1. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be more clearly understood from the description as set forth below, with reference to the accompanying drawings, wherein: Figs. 1 is a cross-sectional view illustrating a prior art InAlAs/InGaAs heterojunction field effect type semiconductor device; and Figs. 2, 3, 4, 5, 6, 7, 8 and 9 are cross-sectional views illustrating first, second, third, fourth, fifth, sixth, seventh and eighth embodiments, respectively, of the InAlAs/InGaAs heterojunction field effect type semiconductor device according to the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS Before the description of the preferred embodiments, a prior art InAlAs/InGaAs heterojunction field effect type semiconductor device (transistor) will be explained with reference to Fig. 1. In Fig. 1, reference numeral 1 designates an InP substrate. Also, an undoped InAlAs buffer layer 2, an undoped InGaAs channel layer 3, an undoped InAlAs spacer layer 4, an N-type InAlAs electron supply layer 5 and an undoped InAlAs Schottky layer 6 are sequentially epitaxially grown on the InP substrate 1. Then, a source electrode 7S, a drain electrode 7D and a gate electrode 7G are formed on the InAlAs Schottky layer 6. The fabrication of the device of Fig. 1, however, generally requires some thermal treatments after growth, so that the electrical quality are degraded. That is, during the thermal treatments, impurity atoms adhered to the surface of epitaxial layers are thermally diffused thereinto, thereby deteriorating the crystalline quality of the epitaxial layers (see: N. Hayafuji et al., "Thermal Stability of AlInAs/GaInAs/InP Heterostructures" Appl Phys, Lett. 66 (7), pp. 863-865, February 1995). The deterioration of the epitaxial layers can be suppressed by introducing an InAlGaAs layer into the InAlAs Schottky layer, i.e., by forming an InAlGaAs layer on the InAlAs electron supply layer 5, to thereby reduce the Al composition ratio of the epitaxial layers on the InAlAs electron supply layer 5 (see: A. Fujihara et al., "Thermal Stability of InAlAs/InGaAs HJFETs with an In (Al 1-x Ga x ) As layer; Technical Report of IEICE, pp. 13-20, October 1995). In this case, however, since the improvement of thermal stability is in a trade-off relationship with the increase of a leakage current and the reduction of a gate breakdown voltage, it is substantially difficult to simultaneously achieve thermal stability while preventing increased gate current and reduced breakdown voltage. Also, the deterioration of the epitaxial layers can be suppressed by forming an InGaAs layer on the InAlAs electron supply layer 5. In this case, however, although the InGaAs layer lattice-matches the InP substrate 1, since the InGaAs layer has a smaller bandgap than the InAlAs layers lattice-matching the InP substrate 1, the leakage current is increased and the gate breakdown voltage is reduced. Further, the deterioration of the epitaxial layers can be suppressed by forming a GaAs layer or an AlAs layer on the InAlAs electron supply layer 5. In this case, however, since the GaAs layer or the AlAs layer lattice-mismatches the InP substrate 1 more than 3 percent thus increasing the strain energy, the crystalline quality of the epitaxial layers are also deteriorated if the thickness of the GaAs layer or the AlAs layer is increased. In Fig. 2, which illustrates a first embodiment of the present invention, a superlattice layer 11 is provided instead of the InAlAs Schottky layer 6 of Fig. 1. In this case, the buffer layer 2 is made of about 200 nm thick In 0.52 Al 0.48 As, the channel layer 3 is made of about 13 nm thick In 0.53 Ga 0.47 As, the spacer layer 4 is made of about 3 nm thick In 0.52 Al 0.48 As, and the electron supply layer 5 is made of about 10 nm thick In 0.52 Al 0.48 As doped by about 5 × 10 18 silicon atoms/cm 3 . The superlattice layer 11 consists of 15 periods of one two-molecules-thick InAs layer 11a and one three-molecules-thick AlAs layer 11b. In Fig. 2, since the superlattice layer 11 suppresses the diffusion of impurity atoms adhered to the surface of the device into the interior thereof, the deterioration of crystalline quality can be suppressed. That is, the electron transfer characteristics are hardly deteriorated. Also, since the composition ratio of InAs in the superlattice layer 11 is 0.4 (=2/5), the leakage current is never increased as compared with In 0.52 Al 0.48 As. Further, the gate breakdown voltage is hardly reduced. Also, in Fig. 2, the thickness of the InAs layer 11a and the thickness of the AlAs layer 11b can be arbitrarily changed; however, each thickness should be less than 4 nm, preferably, 2 nm, in view of the strain energy. If such thickness is too large, the strain energy of each layer becomes too large, which deteriorates the crystalline quality. Further, in Fig. 2, the number of periods of the superlattice layer 11 can be changed. In this case, however, if the thickness ratio of the InAs layer 11a to the AlAs layer 11b is less than 0.5 or more than 2, the average lattice constant of the superlattice layer 11 is greatly deviated from the lattice constant of the InP substrate 1, thus increasing the strain energy. Also, if the thickness ratio of the InAs layer 11a to the AlAs layer 11b is far away from 1, the strain energy increases with the increase of the thickness of the superlattice layer 11. Therefore, the thickness ratio of the InAs layer 11a to the AlAs layer 11b is preferably within approximately 0.5 to 2, and the thickness of the superlattice layer 11 is preferably smaller than approximately 25 nm. In Fig. 3, which illustrates a second embodiment of the present invention, a superlattice layer 12 is provided instead of the superlattice layer 11 of Fig. 2. The superlattice layer 12 consists of 20 periods of one two-molecules-thick InAs layer 12a and one two-molecules-thick AlAs layer 12b. In Fig. 3, since the superlattice layer 12 suppresses the diffusion of impurity atoms adhered to the surface of the device into the interior thereof, the deterioration of crystalline quality can be suppressed. That is, the electron transfer characteristics are hardly deteriorated. Also, since the composition ratio of InAs in the superlattice layer 12 is 0.5 (=2/4), the leakage current is never increased as compared with In 0.52 Al 0.48 As. Further, the gate breakdown voltage is hardly reduced. Also, in Fig. 3, the thickness of the InAs layer 12a and the thickness of the AlAs layer 12b can be arbitrarily changed; however, each thickness should be less than 4 nm, preferably, 2 nm, in view of the strain energy. As a result, the average lattice constant of the superlattice layer 12 is within ±0.5 percent from the lattice constant of the InP substrate 1, so that the strain energy of each layer becomes small, which suppresses the deterioration of the crystalline quality. Further, in Fig. 3, the number of periods of the superlattice layer 12 can be changed. In Fig. 4, which illustrates a third embodiment of the present invention, a superlattice layer 13 is provided instead of the superlattice layer 11 of Fig. 2. The superlattice layer 13 consists of 15 periods of one two-molecules-thick InAs layer 13a and one three-molecules-thick AlGaAs layer 13b. In Fig. 4, since the superlattice layer 13 suppresses the diffusion of impurity atoms adhered to the surface of the device into the interior thereof, the deterioration of crystalline quality can be suppressed. That is, the electron transfer characteristics are hardly deteriorated. Also, since the composition ratio of InAs in the superlattice layer 13 is 0.4 (=2/5), the leakage current is never increased as compared with In 0.52 Al 0.48 As. Further, the gate breakdown voltage is hardly reduced. Also, in Fig. 4, the thickness of the InAs layer 13a and the thickness of the AlGaAs layer 13b can be arbitrarily changed; however, each thickness should be less than 4 nm, preferably, 2 nm, in view of the strain energy. If such thickness is too large, the strain energy of each layer becomes too large, which deteriorates the crystalline quality. Further, in Fig. 4, the number of periods of the superlattice layer 13 can be changed. In this case, however, if the thickness ratio of the InAs layer 13a to the AlGaAs layer 13b is less than 0.5 or more than 2, the average lattice constant of the superlattice 13 is greatly deviated from the lattice constant of the InP substrate 1, thus increasing the strain energy. Also, if the thickness ratio of the InAs layer 13a to the AlGaAs layer 13b is far away from 1, the strain energy increases with the increase of the thickness of the superlattice layer 13. Therefore, the thickness ratio of the InAs layer 13a to the AlGaAs layer 13b is preferably within approximately 0.5 to 2, and the thickness of the superlattice layer 13 is preferably smaller than approximately 25 nm. In Fig. 5, which illustrates a fourth embodiment of the present invention, a superlattice layer 14 is provided instead of the superlattice layer 13 of Fig. 4. The superlattice layer 14 consists of 20 periods of one two-molecules-thick InAs layer 14a and one two-molecules-thick AlGaAs layer 14b. In Fig. 5, since the superlattice layer 14 suppresses the diffusion of impurity atoms adhered to the surface of the device into the interior thereof, the deterioration of crystalline quality can be suppressed. That is, the electron transfer characteristics are hardly deteriorated. Also, since the composition ratio of InAs in the superlattice layer 14 is 0.5 (=2/4), the leakage current is never increased as compared with In 0.52 Al 0.48 As. Further, the gate breakdown voltage is hardly reduced. Also, in Fig. 5, the thickness of the InAs layer 14a and the thickness of the AlGaAs layer 14b can be arbitrarily changed; however, each thickness should be less than 4 nm, preferably, 2 nm, in view of the strain energy. As a result, the average lattice constant of the superlattice layer 14 is within ±0.5 percent from the lattice constant of the InP substrate 1, so that the strain energy of each layer becomes small, which suppresses the deterioration of the crystalline quality. Further, in Fig. 5, the number of periods of the superlattice layer 14 can be changed. In Fig. 6, which illustrates a fifth embodiment of the present invention, a superlattice layer 15 is interposed into the InAlAs Schottky layer 6 of Fig. 1. In this case, the InAlAs Schottky layer 6 is divided into an about 6 nm thick In 0.52 Al 0.48 As layer 6a and an about 5 nm thick In 0.52 Al 0.48 As layer 6b. The superlattice layer 15 consists of 5 periods of one two-molecules-thick InAs layer 15a and one four-molecules-thick AlAs layer 15b. In Fig. 6, since the superlattice layer 15 suppresses the diffusion of impurity atoms adhered to the surface of the device into the interior thereof, the deterioration of crystalline quality can be suppressed. That is, the electron transfer characteristics are hardly deteriorated. Also, since the composition ratio of InAs in the superlattice layer 15 is 0.33 (=2/6), the leakage current is never increased as compared with In 0.52 Al 0.48 As. Further, the gate breakdown voltage is hardly reduced. Also, in Fig. 6, the thickness of the InAs layer 15a and the thickness of the AlAs layer 15b can be arbitrarily changed; however, each thickness should be less than 4 nm, preferably, 2 nm, in view of the strain energy. If such thickness is too large the strain energy of each layer becomes too large, which deteriorates the crystalline quality. Further, in Fig. 6, the number of periods of the superlattice layer 15 can be changed. In this case, however, if the thickness ratio of the InAs layer 15a to the AlAs layer 15b is less than 0.5 or more than 2, the average lattice constant of the superlattice 15 is greatly deviated from the lattice constant of the InP substrate 1, thus increasing the strain energy. Also, if the thickness ratio of the InAs layer 15a to the AlAs layer 15b is far away from 1, the strain energy increases with the increases of the thickness of the superlattice layer 15. Therefore, the thickness ratio of the InAs layer 15a to the AlAs layer 15b is preferably within approximately 0.5 to 2, and the thickness of the superlattice layer 15 is preferably smaller than approximately 25 nm. In Fig. 7, which illustrates a sixth embodiment of the present invention, a superlattice layer 16 is provided instead of the superlattice layer 15 of Fig. 6. The superlattice layer 16 consists of 6 periods of one two-molecules-thick InAs layer 16a and one two-molecules-thick AlAs layer 16b. In Fig. 7, since the superlattice layer 16 suppresses the diffusion of impurity atoms adhered to the surface of the device into the interior thereof, the deterioration of crystalline quality can be suppressed. That is, the electron transfer characteristics are hardly deteriorated. Also, since the composition ratio of InAs in the superlattice layer 12 is 0.5 (=2/4), the leakage current is never increased as compared with In 0.52 Al 0.48 As. Further, the gate breakdown voltage is hardly reduced. Also, in Fig. 7, the thickness of the InAs layer 16a and the thickness of the AlAs layer 16b can be arbitrarily changed; however, each thickness should be less than 4 nm, preferably, 2 nm, in view of the strain energy. As a result, the average lattice constant of the superlattice layer 16 is within ±0.5 percent from the lattice constant of the InP substrate 1, so that the strain energy of each layer becomes small, which suppresses the deterioration of the crystalline quality. Further, in Fig. 7, the number of periods of the superlattice layer 16 can be changed. In Fig. 8, which illustrates a seventh embodiment of the present invention, a superlattice layer 17 is provided instead of the superlattice layer 15 of Fig. 6. The superlattice layer 17 consists of 5 periods of one two-molecules-thick InAs layer 17a and one four-molecules-thick AlGaAs layer 17b. In Fig. 8, since the superlattice layer 17 suppresses the diffusion of impurity atoms adhered to the surface of the device into the interior thereof, the deterioration of crystalline quality can be suppressed. That is, the electron transfer characteristics are hardly deteriorated. Also, since the composition ratio of InAs in the superlattice layer 17 is 0.33 (=2/6), the leakage current is never increased as compared with In 0.52 Al 0.48 As. Further, the gate breakdown voltage is hardly reduced. Also, in Fig. 8, the thickness of the InAs layer 17a and the thickness of the AlGaAs layer 17b can be arbitrarily changed; however, each thickness should be less than 4 nm, preferably, 2 nm, in view of the strain energy. If such thickness is too large, the strain energy of each layer becomes too large, which deteriorates the crystalline quality. Further, in Fig. 8, the number of periods of the superlattice layer 17 can be changed. In this case, however, if the thickness ratio of the InAs layer 17a to the AlGaAs layer 17b is less than 0.5 or more than 2, the average lattice constant of the superlattice 17 is greatly deviated from the lattice constant of the InP substrate 1, thus increasing the strain energy. Also, if the thickness ratio of the InAs layer 17a to the AlGaAs layer 17b is far away from 1, the strain energy increases with the increases of the superlattice layer 17. Therefore, the thickness ratio of the InAs layer 17a to the AlGaAs layer 17b is preferably within approximate 0.5 to 2, and the thickness of the superlattice layer 17 is preferably smaller than approximately 25 nm. In Fig. 9, which illustrates an eighth embodiment of the present invention, a superlattice layer 18 is provided instead of the superlattice layer 17 of Fig. 8. The superlattice layer 18 consists of 6 periods of one two-molecules-thick InAs layer 18a and one two-molecules-thick AlGaAs layer 18b. In Fig. 9, since the superlattice layer 18 suppresses the diffusion of impurity atoms adhered to the surface of the device into the interior thereof, the deterioration of crystalline quality can be suppressed. That is, the electron transfer characteristics are hardly deteriorated. Also, since the composition ratio of InAs in the superlattice layer 18 is 0.5 (=2/4), the leakage current is never increased as compared with In 0.52 Al 0.48 As. Further, the gate breakdown voltage is hardly reduced. Also, in Fig. 9, the thickness of the InAs layer 18a and the thickness of the AlGaAs layer 18b can be arbitrarily changed; however, each thickness should be less than 4 nm, preferably, 2 nm, in view of the strain energy. As a result, the average lattice constant of the superlattice layer 18 is within ±0.5 percent from the lattice constant of the InP substrate 1, so that the strain energy of each layer becomes small, which suppresses the deterioration of the crystalline quality. Further, in Fig. 9, the number of periods of the superlattice layer 18 can be changed. In Figs. 2 to 9, although the channel layer 3 is made of In 0.53 Ga 0.47 As, the channel layer 3 can be made of In x Ga 1-x As (0.53 < x < 1.0). Also, the channel layer 3 can be thicker than 10 nm. In this case, if x > 0.8, the In x Ga 1-x As channel layer 3 increases the strain energy. Therefore, if the thickness of the channel layer 3 is t nm, a multi-layer formed by a 10 nm thick In x Ga 1-x As (0< x <0.8) and a (10-t) nm thick In y G 1-y As (y ≧ 0.8). Also, in Figs. 2 to 9, the thickness of the buffer layer 2 and the thickness of the spacer layer 4 can be changed. In addition, the buffer layer 2 and the spacer layer 4 can be made of other materials such as GaAs, AlAs, InP, AlSb, GaSb, GaP, AlP or InAS. Further, in Figs. 2 to 9, the impurity concentration of Si in the electron supply layer 5 can be changed. In addition, other N-type dopants such as S or Se can be used instead of Si. Further, P-type dopants such as Be or C can be introduced into the layer 5; in this case, the layer 5 constitutes a hole supply layer. Still further, in Figs. 2 to 9, the InAlAs Schottky layers 6a and 6b can be of a conduction type opposite to the charge supply layer 5. For example, if the charge supply layer 5 is of an N-type, the Schottky layers 6a and 6b can be of a P-type. As explained hereinabove, according to the present invention, since the superlattice layer formed by periods of InAs/AlAs or InAs/AlGaAs suppresses the diffusion of impurity atoms into epitaxial layers of the device, the deterioration of crystalline quality can be suppressed to suppress the deterioration of electron transfer characteristics.

Claims: A heterojunction field effect type semiconductor device comprising: an InP substrate (1); an InGaAs channel layer (3) formed over said InP substrate; and a superlattice layer (11-18) formed by periods of InAs/AlAs or InAs/AlGaAs over said InGaAs channel layer, characterised in that the ratio of the average lattice constant of said superlattice layer to the lattice constant of said InP substrate is approximately 0,995 to 1,005 and each of said InAs and said AlAs or said InAs and said AlGaAs of said superlattice layer is thinner than approximately 4nm and in that the thickness of each of said InAs and said AlAs or said InAs and said AlGaAs of said superlattice is homogeneous throughout said superlattice. The device as set forth in claim 1, further comprising an InAlAs charge supply layer (5) formed between said InGaAs channel layer and said superlattice layer. The device as set forth in claim 1, further comprising: a first InAlAs layer (6a) formed beneath said superlattice layer; and a second InAlAs layer (6b) formed on said superlattice layer. The device as set forth in claim 1, wherein a thickness ratio of said InAs and said AlAs or said InAs and said AlGaAs of said superlattice layer is approximately 0,5 to 2. The device as set forth in claim 1, wherein said superlattice layer is thinner than approximately 25nm. The device of claim 1, comprising: an undoped InAlAs buffer layer (2) formed on said InP substrate; an undoped InGaAs channel layer (3) formed on said InAlAs buffer layer; an undoped InAlAs spacer layer (4) formed on said InGaAs channel layer; a doped InAlAs carrier supply layer (5) formed on said InAlAs spacer layer; a superlattice layer (11) formed by periods of one two-molecules-thick InAs layer (11a) and one three-molecules-thick AlAs layer (11b) on said InAlAs carrier supply layer; and electrodes (7S, 7D, 7G) formed on said superlattice layer. The device of claim 1, comprising: an undoped InAlAs buffer layer (2) formed on said InP substrate; an undoped InGaAs channel layer (3) formed on said InAlAs buffer layer; an undoped InAlAs spacer layer (4) formed on said InGaAs channel layer; a doped InAlAs carrier supply layer (5) formed on said InAlAs spacer layer; a superlattice layer (12) formed by periods of one two-molecules-thick InAs layer (12a) and one two-molecules-thick AlAs layer (12b) on said InAlAs carrier supply layer; and electrodes (7S, 7D, 7G) formed on said superlattice layer. The device of claim 1, comprising: an undoped InAlAs buffer layer (2) formed on said InP substrate; an undoped InGaAs channel layer (3) formed on said InAlAs buffer layer; an undoped InAlAs spacer layer (4) formed on said InGaAs channel layer; a doped InAlAs carrier supply layer (5) formed on said InAlAs spacer layer; a superlattice layer (13) formed by periods of one two-molecules-thick InAs layer (13a) and one three-molecules-thick AlGaAs layer (13b) on said InAlAs carrier supply layer; and electrodes (7S, 7D, 7G) formed on said superlattice layer. The device of claim 1, comprising: an undoped InAlAs buffer layer (2) formed on said InP substrate; an undoped InGaAs channel layer (3) formed on said InAlAs buffer layer; an undoped InAlAs spacer layer (4) formed on said InGaAs channel layer; a doped InAlAs carrier supply layer (5) formed on said InAlAs spacer layer; a superlattice layer (14) formed by periods of one two-molecules-thick InAs layer (14a) and one two-molecules-thick AlGaAs layer (14b) on said InAlAs carrier supply layer; and electrodes (7S, 7D, 7G) formed on said superlattice layer. The device of claim 1, comprising: an undoped InAlAs buffer layer (2) formed on said InP substrate; an undoped InGaAs channel layer (3) formed on said InAlAs buffer layer; an undoped InAlAs spacer layer (4) formed on said InGaAs channel layer; a doped InAlAs carrier supply layer (5) formed on said InAlAs spacer layer; a first InAlAs Schottky layer (6a) formed on said InAlAs carrier supply layer; a superlattice layer (15) formed by periods of one two-molecules-thick InAs layer (15a) and one four-molecules-thick AlAs layer (15b) on said first InAlAs Schottky layer; a second InAlAs Schottky layer (6b) formed on said supperlattice layer; and electrodes (7S, 7D, 7G) formed on said second InAlAs Schottky layer. The device of claim 1, comprising: an undoped InAlAs buffer layer (2) formed on said InP substrate; an undoped InGaAs channel layer (3) formed on said InAlAs buffer layer; an undoped InAlAs spacer layer (4) formed on said InGaAs channel layer; a doped InAlAs carrier supply layer (5) formed on said InAlAs spacer layer; a first InAlAs Schottky layer (6a) formed on said InAlAs carrier supply layer; a superlattice layer (16) formed by periods of one two-molecules-thick InAs layer (16a) and one two-molecules-thick AlAs layer (16b) on said first InAlAs Schottky layer; a second InAlAs Schottky layer (6b) formed on said supperlattice layer; and electrodes (7S, 7D, 7G) formed on said second InAlAs Schottky layer. The device of claim 1, comprising: an undoped InAlAs buffer layer (2) formed on said InP substrate; an undoped InGaAs channel layer (3) formed on said InAlAs buffer layer; an undoped InAlAs spacer layer (4) formed on said InGaAs channel layer; a doped InAlAs carrier supply layer (5) formed on said InAlAs spacer layer; a first InAlAs Schottky layer (6a) formed on said InAlAs carrier supply layer; a superlattice layer (17) formed by periods of one two-molecules-thick InAs layer (17a) and one four-molecules-thick AlGaAs layer (17b) on said first InAlAs Schottky layer; a second InAlAs Schottky layer (6b) formed on said supperlattice layer; and electrodes (7S, 7D, 7G) formed on said second InAlAs Schottky layer. The device of claim 1, comprising: an undoped InAlAs buffer layer (2) formed on said InP substrate; an undoped InGaAs channel layer (3) formed on said InAlAs buffer layer; an undoped InAlAs spacer layer (4) formed on said InGaAs channel layer; a doped InAlAs carrier supply layer (5) formed on said InAlAs spacer layer; a first InAlAs Schottky layer (6a) formed on said InAlAs carrier supply layer; a superlattice layer (18) formed by periods of one two-molecules-thick InAs layer (18a) and one two-molecules-thick AlGaAs layer (18b) on said first InAlAs Schottky layer; a second InAlAs Schottky layer (6b) formed on said supperlattice layer; and electrodes (7S, 7D, 7G) formed on said second InAlAs Schottky layer.

Inventors: NAKAYAMA TATSUO, NAKAYAMA, TATSUO
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1996
Main classification: H01L29
IPC codes: H01L29, H01L21