DEMODULATOR AND A METHOD OF DEMODULATION IN A TDM RECEIVER

Abstract: A demodulator for a receiver of digital data in packets sent in predetermined time slots within fixed length time frames is provided. The demodulator comprises at least one data processor and is operative to receive data packets each including synchronisation data. The demodulator includes a buffer for storing data of a received data packet, processing means for reading at least part of the synchronisation data both in the order the synchronisation data was received and in the reverse order, and training means for training the or each data processor dependent upon the synchronisation data.

Description: DEMODULATORANDAMETHODOFDEMODULATION INA TDMRECEIVER The present invention relates to a demodulator for a receiver of digital data in packets sent in predetermined time slots within fixed length time frames. Data packets in conventional TDM/TDMA communications networks include a sequence of predetermined (synch) symbols which is designed to be used by the receiver for timing and carrier (phase, frequency) synchronisation. For TDM/TDMA networks subject to significant multipath interference, the synch sequence may also be used for what is known in the art as equaliser training, see for example Cellular Radio Systems, DM Balston and RCV Macario Editors, Artech House Inc 1993, page 167-168. Training is the process of iteratively adapting parameters of a data processor dependent upon a predetermined data sequence such that initial parameter values converge towards more accurate values. The parameters are used in processing data. In the specific case of a equaliser training, the purpose is to adaptively adjust the equaliser filter coefficients so that they converge to values which generate a frequency or time domain response which compensates for the effect of multipath interference. However, training can also be applied to other data processors such as those for carrier phase recovery, TDM/TDMA time slot timing recovery and/or automatic gain control. In conventional receivers, demodulation starts with data in the received synch sequence and then proceeds sequentially (symbol-by-symbol) through the message data portion of the packet. This ensures that the data processors which form the demodulator can be trained prior to the recovery of the message content thereby minimising the likelihood of message symbol decision errors. The length of the synch sequence has a bearing on the performance of the demodulator and the complexity of equalisation methods applied. Short sequences imply rapid training which normally means highly-complex adaption methods (such as recursive least squares, RLS) must be used, rather than simple adaption methods such as Least Means Squared (LMS). A detailed coverage of LMS, RLS and adaptive techniques generally is given in the book "Adaptive Filter Theory" by Simon Haykin, Prentice Hall Publishers, 1991, 2nd Edition. Long sequences provide more time for training allowing more options for equaliser implementation but reduce the proportion of the packet that can be allocated to message data. The present invention is defined in the claims to which reference should now be made. Preferred features are laid out in the dependent claims. The present invention preferably provides a demodulator for use in a TDM/TDMA communications network, the demodulator comprising at least one data processor and being operative to receive data packets each including synchronisation data, the demodulator including buffer means for storing data of a received data packet, processing means for reading at least part of the synchronisation data both in the order the synchronisation data was received and in the reverse order, and training means for training the or each data processor dependent upon the synchronisation data. Synchronisation data, which is expected by the demodulator, is processed by the training means so that the demodulator can accurately process message data. Data processors can be for adaptive filtering, carrier phase recovery, TDM/TDMA time slot timing recovery, or automatic gain control. The present invention allows a greater number of training iterations than is available from a single pass of the synchronisation sequence leading to more accurate values for parameters to be used in processing the message data and, therefore, improved demodulator performance. In consequence simple adaption methods, such as least means squares (LMS) can be used without the need for a long training sequence. Synchronisation data can be processed such that later received part of the data is read first and in the order received, then substantially all the synchronisation data is read in reverse order. Alternatively, the first received part can be read in reverse order followed by substantially all the synchronisation data in the order received. Further forward/reverse processing of the synchronisation data can be undertaken to provide more training iterations and, thus, longer for convergence. This approach is particularly advantageous where the received signal is affected by additive noise which is uncorrelated with the synchronisation sequence. The present invention also relates to a method of demodulation of data packets including synchronisation data for use in a TDM/TDMA communications network, the method including storing data of a received data packet and processing at least part of the synchronisation data both in the order the synchronisation data was received and in the reverse order. The synchronisation data is preferably used for training at least one data processor. A preferred embodiment of the present invention will now be described by way of example and with reference to the accompanying drawings in which: Figure 1 is a schematic diagram illustrating the system including a base station (BTE- Base Terminating Equipment) and subscriber unit (NTE - Network Terminating Equipment); Figure 2 is a diagram illustrating frame structure and timing for a duplex link; Figure 3 is a schematic diagram showing different types of data packet transmitted from a base station to a subscriber unit (i.e. downlink); Figure 4 is a functional block diagram illustrating the symbol processor of the demodulator at the subscriber unit; Figure 5 illustrates the multipass training method used. Figure 6 illustrates equaliser output quantisation according to a π/4 - Differential Quadrative Phase shift keying modulation scheme. The Basic System As shown in Figure 1, the preferred system is part of a telephone system in which the local wired loop from exchange to subscriber has been replaced by a full duplex radio link between a fixed base station (BTE) and fixed subscriber unit (NTE). The preferred system includes the duplex radio link (Air Interface), and transmitters and receivers for implementing the necessary protocol. There are similarities between the preferred system and digital cellular mobile telephone systems such as GSM which are known in the art. This system uses a protocol based on a layered model, in particular the following layers: PHY (Physical), MAC (Medium Access Control), DLC (DataLink Control), NWK (Network). One difference compared with GSM is that, in the preferred system, subscriber units are at fixed locations and there is no need for hand-off arrangements or other features relating to mobility. This means, for example, in the preferred system directional antennae and mains electricity can be used. Each base station in the preferred system provides six duplex radio links at twelve frequencies chosen from the overall frequency allocation, so as to minimize interference between base stations nearby. The frame structure and timing for a duplex link is illustrated in Figure 2. Each duplex radio link comprises an up-link from a subscriber unit to a base station and, at a frequency offset, a down-link from the base station to the subscriber unit. The down-links are TDM, and the up-links are TDMA. Modulation for all links is π/4 - DQPSK, and the basic frame structure for all links is ten slots per frame of 2560 bits, i.e. 256 bits per slot. The bit rate is 512kbps. Down-links are continuously transmitted and incorporate a broadcast channel for essential system information. When there is no user information to be transmitted, the down-link transmissions continue to use the basic frame and slot structure and contain a suitable fill pattern. For both up-link and down-link transmissions, there are two types of slot: normal slots which are used after call set-up, and pilot slots used during call set-up. Each down-link normal slot comprises 24 bits of synchronisation information followed by 24 bits designated S-field which includes an 8 bit header followed by 160 bits designated D-field. This is followed by 24 bits of Forward Error Correction and an 8 bit tail, followed by 12 bits of the broadcast channel. The broadcast channel consists of segments in each of the slots of a frame which together form the down-link common signalling channel which is transmitted by the base station, and contains control messages containing link information such as slot lists, multi-frame and super-frame information, connectionless messages, and other information basic to the operation of the system. During the call set-up, each down-link pilot slot contains frequency correction data and a training sequence for receiver initialisation, with only a short S- field and no D- field information. Up-link slots basically contain two different types of data packet. The first type of packet, called a pilot packet, is used before a connection is set up, for example, for an ALOHA call request and to allow adaptive time alignment. The other type of data packet, called a normal packet, is used when a call has been established and is a larger data packet, due to the use of adaptive time alignment. Each up-link normal packet contains a data packet of 244 bits which is preceded and followed by a ramp of 4 bits duration. The ramps and the remaining bits left of the 256 bit slot provide a guard gap against interference from neighbouring slots due to timing errors. Each subscriber unit adjusts the timing of its slot transmissions to compensate for the time it takes signals to reach the base station. Each up-link normal data packet comprises 24 bits of synchronisation data followed by an S-field and D-field of the same number of bits as in each down-link normal slot. Each up-link pilot slot contains a pilot data packet which is 192 bits long preceded and followed by 4 bit ramps defining an extended guard gap of 60 bits. This larger guard gap is necessary because there is no timing information available and without it the propagation delays would cause neighbouring slots to interfere. The pilot packet comprises 64 bits of sync followed by 104 bits of S-field which starts with an 8 bit header and finishes with a 16 bit Cyclic Redundancy Check, 2 reserved bits, 14 FEC bits, and 8 tail bits. There is no D-field. The S-fields in the above mentioned data packets can be used for two types of signalling. The first type is MAC signalling (MS) and is used for signalling between the MAC layers of the base station and the MAC layer of a subscriber unit whereby timing is important. The second type is called associated signalling, which can be slow or fast and is used for signalling between the base station and subscriber units in the DLC or NWK layers. The D-field is the largest data field, and in the case of normal telephony contains digitised speech samples, but can also contain non-speech data samples. Provision is made in the preferred system for subscriber unit authentication using a challenge response protocol. General encryption is provided by combining the speech or data with a non-predicable sequence of cipher bits produced by a key stream generator which is synchronised to the transmitted super-frame number. In addition, the transmitted signal is scrambled to remove dc components. Subscriber Unit Demodulator The subscriber unit demodulator is concerned with the physical reception of data transmitted in the downlink direction base-to-subscriber. Dispersion due to multipath propagation does not vary significantly frame-to-frame. This allows filter coefficients determined in the equalisation of one packet to be applied in equalising the corresponding packet in the next TDMA frame, as discussed below. Two of the three types of downlink packet are shown in Figure 3. From the demodulation perspective, the third packet type (Idle Packet) is the same as the Pilot Packet shown except that the DOWN-P-DATA field is replaced with a fixed fill pattern. Pilot packets occupy non-traffic bearing slots and are specifically intended for subscriber unit timing synchronisation and equaliser training as part of downlink connection establishment. Voice and data traffic is carried by the Normal Packet which provides a higher effective bandwidth by allocating less of the packet to synchronisation data; on the basis that slot-by-slot equaliser training is not required. Symbol Processor The following functions are undertaken by a sub-section of the subscriber unit demodulator known as the symbol processor: Synch Correlation (slot timing recovery, digital gain control and initial phase recovery); Channel equalisation; Carrier phase tracking; Slicing (symbol decisions). Symbol timing recovery, channel filtering and analogue gain control are handled by other components of the subscriber unit. In general terms, the symbol processor operates as one of a basic (non-equalising) coherent receiver; a linear equaliser; or a decision feedback equaliser (DFE). Which of these is best for any particular subscriber unit depends on the characteristics of the RF propagation path. The coherent receiver is likely to perform best where multipath effects are not significant, the linear equaliser will offer a performance benefit where multipath propagation is present but not severe and the DFE has the potential to operate through severely dispersive channels. Symbol Processing The functions performed by the symbol processor are shown in Figure 4 which is a signal flow diagram in which double-edged arrows denote paths for complex data. The output from the radio frequency (RF) section (not shown) of the subscriber unit receiver is digitised and presented to the symbol processor as a sequence of complex samples. These samples are buffered to enable non-real-time processing. The demodulated bit sequence (the symbol processor output) which can be a normal or pilot packet or a broadcast data fragment depending upon operating mode, is passed to a separate circuit block for deformatting and bit-level protocol processing. With the exception of the correlator 2, which operates at the input sample rate, all processing is performed iteratively symbol-by-symbol. Timing is organised such that the received slot synch sequence of the captured packet falls within a predetermined region of the input buffer used by the correlator 2. Complex correlation with a stored representation of the expected synch sequence then produces estimates of instantaneous carrier phase and signal level which are subsequently used to scale and phase-align (ie. rotate) the entire input sample set. Scaling is undertaken by operation of the Automatic Gain Control (AGC) block 1 and rotation by the rotator block 3. This phase recovery technique establishes the carrier phase mid-way through the synch sequence and, accordingly, symbol-by-symbol processing starts at this point. The phase and gain-corrected samples (starting with the one closest to the middle of synch) are applied to the main demodulation loop which carries out: symbol slicing (absolute phase decoding); carrier tracking (phase locked loop PLL); equalisation. The equaliser is implemented in four principal sections: a feedforward filter 2 a feedback filter 4 a quantiser 8 and a filter adaption mechanism The two filter sections each consist of a complex tapped delay line (ie. a Finite Impulse Response filter) with variable tap weights (ie. coefficients). The feedforward filter 4, which has at least one delay element/coefficient per symbol period, takes input data from the AGC block 1, convolves the samples held in its tapped delay line with the current coefficient set and presents its output to the rotator 10 of the phase locked loop (PLL) 2. Likewise, the feedback filter 4, which has only one delay element/coefficient per symbol period, convolves constellation decisions from the quantiser 8 with a further coefficient set. The combined output from feedforward and feedback filters 4, 6 constitutes the equaliser output and this particular configuration of filter sections is generally referred to as a decision feedback equaliser (DFE). In operation, the equaliser generates one (equalised) output sample per symbol period which is fed to the quantiser 8. The function of the quantiser 8 is then to compare the output with the set of 'ideal' constellation points characterising the modulation scheme and to select the constellation point which is closest in the Euclidean sense. This process is depicted for the π/4-DQPSK modulation scheme in Figure 6, which shows an equaliser output sample X being selected as having a closest constellation point Y' of possible constellation points Y. The selected constellation point Y' forms the quantiser 8 decision for the current receive symbol and, as such, the next input sample for the feedback filter 4. Successive quantiser 8 decisions are also fed to a symbol decoding circuit where they are processed to recover the transmitted bit sequences. The difference between the equaliser output X and the selected constellation point Y represents the decision error Z for the current symbol and this error Z is used by the coefficient adaption mechanism to drive the error Z towards zero over time. The equaliser is said to have converged when the coefficients in the feedforward and feedback filters 4, 6 have reached values which adequately mitigate the effects of intersymbol interference. Equaliser coefficients are initialised with constants (zeroes except for the main 'tap' which is set to unity) prior to pilot packet processing (the extended training sequence ETS is used to train the equaliser initially). Thereafter, the final coefficient values in one slot are used as the starting values in the corresponding slot of the next frame. The intra-slot coefficient training method is described in more detail below. The two equaliser filter 4, 6 outputs are combined on the quantiser side of a phase rotator 10 which is driven by a decision-directed phase locked loop (PLL) 12. The quantiser produces a phase error term and, from the vector difference between the phase rotator output and closest (in the Euclidean sense) candidate constellation point, a symbol error vector Z is produced suitable for equaliser coefficient updating. The phase error term is passed to the carrier tracking algorithm which modifies the current reference phase estimate (a state variable within the carrier tracking algorithm) in preparation for the next symbol iteration. A sine lookup table 13 is used to convert the current phase estimate to an equivalent cartesian (complex) representation compatible with the phase rotator 10. At the start of each packet, or more specifically for the first sample of synch data (the middle sample in the synch sequence), the phase reference is set to zero (degrees) since initial phase recovery is performed by the correlator 2 as described above. Two representations of the symbol error are required: the unprocessed error for feedback updates, and a 'derotated' error vector - which reintroduces the phase offset removed by the phase locked loop - for feedforward updates. Derotation by derotator 14 is necessary to re-establish the correlative relationship between decision error and input samples in the feedforward filter. Coefficients are adjusted using the so-called Stochastic Gradient LMS algorithm although any direct form adaption algorithm could be employed. The adaption properties of the carrier tracking phase locked loop 12 and equaliser are chosen to ensure that carrier phase variations during the packet (including frequency offset) are removed by the actions of the phase-locked loop 12 leaving the equaliser to compensate exclusively for multipath channel variations. On completing slot demodulation, the equaliser coefficients are stored away for use in the corresponding TDMA slot of the following frame. Training Normally, the equaliser coefficients are initialised without prior knowledge of the channel impulse response. Typically, this involves setting the main tap to unity and all other coefficients to zero so as to provide an all-pass response to input signals. In the early stages of packet demodulation, when the equaliser is attempting to earn' the "inverse channel", ie. the filter coefficients necessary to remove the effects of multipath propagation, constellation decision errors slow down, and in severe cases prevent, convergence. To ensure that this does not happen, the equaliser is 'trained' from the known packet sequences (Slot Synch, Frame Synch and ETS depending upon the packet type) before the switch to (unknown) data demodulation. During training, the phase quantiser 8 is bypassed and, after synchronisation, equaliser coefficients and phase locked loop (PLL) 12 adaption is based upon the error Z measured between corresponding equaliser output samples and the corresponding samples from the known 'training sequence'. Symbol-by-symbol demodulation starts in the middle of the synch sequence. Multiple backward-forward passes are made through the synch sequence which has the effect of effectively extending the known symbol sequence, firstly, by providing access to the otherwise unused half of synch and, secondly, by simply allowing more iterations to take place. The effect is similar to increasing the coefficient adaption constants for the equaliser and phase locked loop but without the associated increase in residual error after convergence. Note that the ultimate performance is governed by the synch length not the total number of training iterations performed. Figure 5 illustrates the multiple-pass technique as applied to equaliser training in Normal and Pilot packets. The same process is applicable in Broadcast mode although the direction of movement through the data is reversed. In Figure 5, the arrows represent power in the equaliser filter coefficients which are being adapted. No particular significance should be attached to the magnitudes shown except that the biggest arrow is the main tap and as such the demodulator/equaliser time reference. The leftmost arrow represents the relative position of the feedback tap in a 1-tap DFE. As shown, demodulation starts in the middle of the synch sequence (at sample S7) and proceeds chronologically through the second (later) half until the main tap is aligned with the last sample of synch symbol (S12). The demodulator then reverses the processing order such that the equaliser time reference moves backwards through the (same) input data until the main tap is aligned with the earliest synch sample (SO). Here the processing order is again reversed and the equaliser can train through the entire training sequence in chronological order before running into the (unknown) data part (DO) of the packet. The forward/reverse processing of received and synch samples is achieved by means of linear storage buffers (not shown) and programmable sequential address generators (not shown). In the preferred embodiment, each address generator counts up to access samples in an order corresponding to that in which they were received and counts down to affect time reversal. A slight complication arises from the processing of samples in reverse chronological order since it implies frequency inversion of any prevailing carrier offset. Accordingly, each time the direction of movement is reversed (at the first and last samples of synch) the carrier tracking loop inverts the polarity of an internal state variable which represents instantaneous frequency offset. In the preferred demodulator, training stops in the middle of the synch data at which point the quantiser is re-enabled and the demodulator advances in a decision-directed mode, in which constellation decisions are based entirely on the quantiser input, no use being made of predetermined data sequences. The first 12 bits to be demodulated in a packet are therefore the last 12 bits of synch for normal and pilot packets and the first 12 bits of synch (in reverse time order) in broadcast mode. A downstream protocol processing circuit compares the demodulated segment of synch with a stored reference in order to detect synch errors. This information is preferably used to protect the equaliser coefficients from corrupted data packets or to control voice path muting functions. How the training is applied in practice to the various types of data packets received is explained in more detail below. Training to a Pilot Physical Packet Demodulation starts when the control processor module (CPM) of the subscriber unit selects demodulator Call Processing mode configured for pilot packet reception. Equalisation coefficients are initialised using data consistent with the selected demodulator architecture. The procedure is then as follows: 1) Digitise and capture the required pilot packet into the slot buffer (in the preferred demodulator synch processing and packet capture are overlapped to minimise group delay). 2) Correlate for Slot Synch (Frame Synch in slot 0) over the synch window. Use the peak correlator output to scale and rotate the Synch region of the slot buffer. Reset the PLL phase reference to 0°. 3) Train the equaliser and PLL by running forward/backward passes through Synch, starting and finishing in the middle of the sequence. The PLL controls unwanted carrier modulation effects such as noise and frequency offset. Equaliser and PLL updates are made with relatively large adaption constants to achieve rapid acquisition. 4) Demodulate the last half of the Synch. 5) Correlate for Extended Training Sequence (ETS) data over a delayed synch window. Use the peak correlator output to scale and rotate the ETS and DOWN-P-DATA regions of the slot buffer. Reset the PLL phase reference to 0°. 6) Train the equaliser and PLL 12 by running forward/backward passes through the ETS starting in the middle of the sequence and finishing just before DOWN-P-DATA. 7) Demodulate the DOWN-P-DATA FIELD, updating the equaliser and PLL 12 from constellation decisions. For these updates, small adaption constants minimise residual errors and, hence, Symbol Error Rate (SER). Note that data between the Synch and DOWN-P-DATA field is not demodulated. 8) Store away the equaliser coefficients for the next Pilot or Normal Packet on the corresponding TDMA slot of the following frame. Training to a Normal Packet A switch to Normal Packet demodulation would normally occur once the equaliser has successfully trained from pilots packets. The switch may be triggered when the integrated squared vector error (out of the phase quantiser) drops below a threshold or, alternatively, when decoded packets are received error-free by the protocol processing module (PPM) of the subscriber unit. In either case, packet processing involves the following: 1) Digitise and capture the required normal packet into the slot buffer (in the preferred demodulator synch processing and packet capture are overlapped to minimise group delay). 2) Correlate for Slot synch (Frame Synch in slot 0) over the synch window. Use the peak correlator output to scale and rotate the slot buffers contents. Reset the PLL phase reference to 0°. 3) Train the equaliser and PLL by running forward/backward passes through Synch starting and finishing in the middle of the sequence. 4) Demodulate the last half of Synch followed by the data field. 5) Store away the equaliser coefficients ready for the next packet on the corresponding TDMA slot of the following frame. Training to a Broadcast Packet The general strategy applied for Broadcast packet processing is identical to that used for Normal Packets except that the Broadcast equaliser coefficients are initialised by the CPM before reception is attempted and the time-order in which received symbols are accessed is reversed. The procedure is otherwise as follows: 1) Capture the Broadcast fragment from slot N-l and immediately-adjacent Synch from slot N. 2) Correlate for Slot Synch (Frame Synch is slot 0) over the synch window. Use the peak correlator output to scale and rotate the captured Broadcast and Synch samples. Reset the PLL phase reference to 0°. 3) Train the equaliser and PLL by running backward/forward passes through Synch starting and finishing in the middle of the sequence. 4) Demodulate (in reverse time order) the first half of slot N's Synch followed by the Broadcast data field of slot N-l. 5) Store away the equaliser coefficients ready for the next fragment.

Claims: CLAIMS 1. A demodulator for a receiver of digital data in packets sent in predetermined time slots within fixed length time frames, the demodulator comprising at least one data processor and being operative to receive data packets each including synchronisation data, the demodulator including buffer means for storing data of a received data packet, processing means for reading synchronisation data of a received data packet stored in the buffer means, the processing means reading at least part of the synchronisation data both in the order the synchronisation data was received and in the reverse order, and training means for training the or each data processor dependent upon the synchronisation data read. 2. A demodulator according to claim 1, in which each of said at least one data processor is for adaptive filtering, carrier phase recovery, time slot timing recovery, or automatic gain control. 3. A demodulator according to claim 2, in which one data processor is an adaptive digital filter. 4. A demodulator according to any preceding claim, in which a greater number of training iterations are undertaken by said reading at least part of the synchronisation data both in the order the synchronisation data was received and in the reverse order than are available from a single reading through the synchronisation data, so as to provide more accurate values for parameters to be used by said at least one data processor in processing further data. 5. A demodulator according to claim 4, in which a simple iterative adaption method is used to provide said more accurate values for said parameters. 6. A demodulator according to claim 5, in which the simple iterative adaption method is a least means squares (LMS) method. 7. A demodulator according to any preceding claim, in which synchronisation data is read by the processing means such that the later received part of the data is read first and in the order received, then at least substantially all the synchronisation data is read in reverse order. 8. A demodulator according to any of claims 1 to 7, in which the synchronisation data is read by the processing means such that the first received part of the synchronisation data is read in reverse order followed by at least substantially all the synchronisation data in the order received. 9. A demodulator according to claim 7 or claim 8, in which further forward and/or reverse reading of the synchronisation data is undertaken to provide more training iterations. 10. A demodulator according to any preceding claim, further comprising correlation means operative to perform a complex correlation between received and expected synchronisation data to determine carrier phase at a predetermined symbol in each data packet for use in subsequent processing. 11. A receiver of digital data sent in predetermined time slots within fixed length time frames comprising a demodulator according to any preceding claim. 12. A receiver according to claim 11, which is a subscriber unit operative to receive time division multiplex (TDM) data signals. 13. A receiver according to claim 1 1 or claim 12, which is a subscriber unit having a fixed location. 14. A receiver according to claim 11, 12 or 13, which comprises a transmitter operative to transmit time division multiple access (TDMA) data signals to a base station. 15. A receiver according to any of claims 11 to 14, operative to receive digital data sent by radio. 16. Communications means comprising a plurality of subscriber units each operative to receive digital data messages comprising data packets in predetermined time slots within fixed length time frames from a base station, and the base station operative to receive digital data messages comprising data packets in predetermined time slots within fixed length time frames from the subscriber units, the subscriber units each comprising a receiver including a demodulator, the demodulators each comprising at least one data processor and being operative to receive data packets each including synchronisation data, each demodulator including buffer means for storing data of a received data packet, processing means for reading the synchronisation data stored in the buffer means, the processing means reading at least part of the synchronisation data both in the order the synchronisation data was received and in the reverse order, and training means for training the or each data processor dependent upon the synchronisation data read. 17. A method of demodulation of data packets sent in predetermined time slots within fixed length time frames including synchronisation data, the method including storing data of a received data packet and reading at least part of the synchronisation data both in the order the synchronisation data was received and in the reverse order, the synchronisation data being used for training at least one data processor.

Inventors: RUDKIN PAUL WILLIAM, RUDKIN, PAUL, WILLIAM
Applicants: IONICA INT LTD, RUDKIN PAUL WILLIAM, IONICA INTERNATIONAL LIMITED, RUDKIN, PAUL, WILLIAM
Application year: 1996
Main classification: H04L25
IPC codes: H04J3, H04L25, H04L27