Timesharing internal bus, particularly for non-volatile memories

Abstract: A non-volatile memory device, having the particularity that it comprises an internal bus (3) for the transmission of data and other information of the memory to output pads (4); timer means (8); and means (5, 5') for enabling/disabling access to the internal bus; the timer means (8) time the internal bus to transmit information signals of the memory device that originate from local auxiliary lines (7) over the internal bus (3) when the bus is in an inactive period during a normal memory data reading cycle; the timer means (8) drive the enabling/disabling means (5, 5') to allow/deny access to the internal bus (3) on the part of the information signals or of the data from or to the memory.

Description: The present invention relates to a timesharing internal bus that acts as site for streams that relate to data originating from the memory, codes related to the wiring of paths, configuration data, information of internal points, etcetera, particularly for non-volatile memories, and more particularly relates to a particular architecture of the memory, which allows better management of the information streams of the memory device. In non-volatile memories, such as for example EPROMs, EEPROMs, and FLASH memories, an architecture is generally known which includes a memory matrix with paths directed toward the I/O pads arranged on one side of the device for data reading/writing, while the input (address) pads are placed in a different position, for example on the opposite side, in order to optimize the area of the device. These input (address) pads stimulate the various processes of the memory, whereas the output pads collect the data in output or provide the data to be written to the memory. Often it is necessary to transmit outside the memory device, internal situations of the memory (for example for testing or troubleshooting), related to circuit parts that are possibly even quite distant from the I/O terminals. It is also necessary to reconfigure the read/write paths and to provide particular operating modes. Due to the considerable distance between the parts, which are typically arranged opposite each other, every form of "dedicated" transmission entails increases in space occupation and management of the memory device. Accordingly, in order to obtain the desired signals in output available long connecting lines between one side and the other of the memory device are necessary. Each connecting line, despite performing functions that are indispensable for the functionality of the circuit, still entails an expenditure of area together with reliability problems. Indeed, the larger the memory device, the longer said connecting lines must be, with problems of area occupation, management complexity, and possibility of malfunction. The aim of the present invention is therefore to reduce the connecting lines present between the pads between one front and the other of the memory device, in order to reduce the area occupation of the device. Within the scope of this aim, an object of the present invention is to optimally utilize the internal transmission resources that intrinsically exist and are indispensable. Another object of the present invention is to provide a data transmission system that is compact and flexible. Another object of the present invention is to standardize the functional modes of the memory device and to increase its potential. Another object of the present invention is to provide an architecture of the memory device that is highly reliable and relatively easy to provide at competitive costs. This aim, these objects, and others which will become apparent hereinafter are achieved by a non-volatile memory device, comprising an internal bus for the transmission of data and other information of said memory to output pads; timer means; and means for enabling/disabling access to said bus; said timer means timing said internal bus to reroute information signals of the memory device that originate from local auxiliary lines onto said internal bus when said bus is in an inactive period during a normal cycle for reading data of the memory, said timer means driving said enabling/disabling means to allow/deny access to said internal bus on the part of said information signals or of the data from or to the memory. The characteristics and advantages of the invention will become apparent from the description of a preferred but not exclusive embodiment of the device according to the invention, illustrated only by way of non-limitative example in the accompanying drawings, wherein: figure 1 is a schematic view of the architecture of the memory device according to the invention; figure 2 shows a circuital embodiment of a tristate buffer used in the architecture shown in figure 1; figure 3 shows a circuital embodiment of a latch circuit with a tristate buffer used in the architecture shown in figure 1; figure 4a shows an embodiment of a multiplexer that has the same function as the circuit shown in figure 2; figure 4b shows another embodiment of the tristate buffer, equivalent to the one shown in figure 2; figure 5 is a chart of the timings of the signals of a memory device having a conventional architecture; and figure 6 is a chart of the timings of the signals of a memory device according to the invention. With reference to the above figures, the architecture of the data bus according to the invention is as follows. Figure 1 illustrates the architecture of a memory according to the invention, in which the reference numerals 1 and 2 designate the half-matrices that compose the non-volatile memory and 3 is an internal bus for the transmission of data from the memory half-matrices to the output buffers 4 connected to the internal bus 3. Hereinafter, the internal bus will be referenced as data bus to point out its fundamental and irreplaceable function. The number of the output buffers 4 is equal to the number of bits of the memory half-matrices 1 and 2 and in this case is eight for each half-matrix. The reference numerals 5 designate enabling/disabling structures that are advantageously provided by tristate-type circuits and are connected between the sense amplifiers that are present in the memory half-matrices (not shown in the figures) and the data bus 3. The number of said tristate structures 5 is equal to the number of lines present in the data bus 3. The reference numeral 5' instead designates similar tristate structures that are however dedicated to enabling/disabling the communication of the external sources with the data bus 3. Data lines originating from different sources carrying system information are designated by the reference numeral 7 in figure 1. These data lines are local, i.e., they are arranged at the input (address) pads of the memory matrix or local circuits and do not run along the memory half-matrices 1 and 2. Said data lines are not necessarily buses. Data storage means, conveniently provided for example by latch-type circuits 6, are connected in output to the data bus 3 and act as interface between the data bus 3 and data lines 7', similar to the lines 7, to obtain in output the information data that originate from the lines 7. These 5 lines are local in this case, too, i.e., they are confined to the output side of the memory matrix. The memory means 6 can be executed for example also by virtue of flip-flops. The number of latches 6 is equal to the number of lines of the data bus 3, but the number can be smaller for the sake of optimizing space occupation. Synchronization means 8, advantageously constituted by binary structures, are provided for the management of the tristate structures 5, of the charging of the latches 6, and of the enabling of the output buffers 4. The timer means 8 generate the signals PC (precharge) and EQ (equalization). Figure 1 also shows data lines 9, 10 and 11, dedicated respectively for transmitting signals that are normally present in the memory. The line 9 is dedicated to the signal RM (Read Mode), the line 10 is dedicated to the signal PC (Precharge), and the line 11 is dedicated to the signal EQ (Equalization). The signal EQ captures the data to be sent over the data bus 3. The signal RM indicates the beginning of a step for the download of the data arriving from the memory matrix onto the data bus 3; the signal PC, besides precharging the read circuits, samples the data to be stored in the latches 6 involved in the reading operation. The signal RM constitutes an input to the tristate structures 5. Again with reference to the timer means 8, additional signals are shown which are meant for controlling the read cycle of the memory: the signal ATD (Address Transition Detection, which is normally present in a memory), the signal READ, and the signal SEND. The signal SEND is a timing signal that is correlated to the burst signal ATD. The timer means 8 receive in input the signals READ (request to read the memory) and ATDn, and the signals RM and SEND are generated with the signals PC and EQ. In greater detail, the signal READ and the signal ATDn, together with the signal EQ, inverted by means of the inverter 37, are sent in input to a NAND gate 35 whose output passes through an inverter 36 to produce the signal RM. The signal READ and the signal PC, inverted by means of the inverter 38, pass through a NAND gate 39 from which the signal SEND is produced in output. In particular, while the signals RM, EQ, and PC have their own dedicated lines, for propagation to the output side of the memory, the signal SEND is sent, together with the data present on the data lines 7, to tristate structures 5' (in this case, one for each half-matrix) for propagation over the data bus 3. With reference to figure 2, a possible implementation of a tristate structure 5 is shown which receives in input the data related to system information, referenced here as DATA-IN, and the signal SEND, and produces in output the data on the data bus 3. Said conventional structure comprises P-type transistors 12 and 13, two pass transistors 15 and 16 formed respectively by a P-type transistor and by an N-type transistor, N-type transistors 14 and 18, and an inverter 17, which are connected as shown in the figure. Figures 4a and 4b illustrate further possible implementations of the tristate circuits 5 and 5'. The illustrated latch circuit 6 receives in input the signal DATA that relates to the system data sent by the data bus 3. In input to the latch circuit 6 there is a tristate circuit 6' that receives in input the signals DATA, which arrive from the data bus 3, and the precharge signal PC, to emit the signals DATA to the latch circuit 6 when appropriate. The tristate circuit 6' comprises a P-type transistor: its drain terminal is connected to the supply voltage V DD of +5V, its gate terminal receives the signal PC, appropriately inverted through the inverter 20, and its source terminal is connected to the drain terminal of a P-type transistor 21 whose source terminal is connected to the drain terminal of an N-type transistor 22. The gate terminals of the transistors 21 and 22 are supplied with the signal DATA. The source terminal of the transistor 22 is connected to the drain terminal of a transistor 23, whose gate terminal is supplied with the signal PC and whose source terminal is connected to the ground. The signal (DATA) that leaves the tristate structure 6' described above is sent to the latch circuit 6, which is composed, as known, of two P-type transistors 24 and 25 and of two N-type transistors 26 and 27. The signal in output from the circuit 6 is sent to the lines 7'. Figure 5 is a chart of the timings of the various signals in a normal reading cycle for a non-volatile memory having a conventional architecture, whereas figure 6 is a chart of the timings of the various signals in a reading cycle for a non-volatile memory having the architecture according to the invention, with timesharing management of the data bus 2. These two figures will be explained in detail while describing the operation of the non-volatile memory according to the invention. With reference to the above figures, the operation of the non-volatile memory device having a timesharing data bus, according to the invention, is as follows. In order to better understand the operation of the memory device according to the invention, it is necessary to explain a normal reading cycle of a conventional memory device. The figures that provide the best explanation in this regard are figures 5 and 6. In a normal reading cycle of a memory there are three fundamental intervals: a first interval for activating reading by recognition of a transition of the addresses, performed by means of a control pulse ATD (the inverted signal ATD, i.e., ATDn, is shown in figure 5); a second interval for the propagation and presetting of the nodes affected by the reading operation at their working point, provided by virtue of the setting of two signals that are fundamental for correct reading of the data, namely PC and EQ; a third interval for evaluating, capturing, and sending the updated data to the output pads. Of these three intervals, the only one that requires the data bus 3 for actual data transmission is the third one. The three signals ATD, PC, and EQ are fundamental for the execution of a memory reading cycle. Figure 5 is a chart of the timings of the signals of a conventional memory device, which illustrates the timings of said three signals as a consequence of a change in the address ADD. Therefore, the variation of ADD, indicated by the pulsed signal ATDn, sets the signals PC and EQ. As shown by the figure, the data bus 3 that transmits the signals DATA is used exclusively during some time slices, designated by the reference numeral 30, whereas in others, designated by 31, it remains unused. The transmission of signals on data lines that are external to the bus 3 occurs in parallel to the operation of the data bus. These lines transmit signals that provide information as to the state of the system from one end of the memory to the other. The signals that are transmitted are, for example: redundancy messages (RED) rescrambling codes for the output that is made redundant (ROC, Redundancy Out Code) byte identifier manufacturer codes (MC, Manufacturer Code) special operating modes (verify) testing procedures, such as for example DMA (Direct Memory Access). The references ISTR and CONF of figure 5 generically relate to instruction and configurations signals, respectively, for the memory device. Hereinafter, reference will be made to the signals ROC, CONF, and ISTR as to the signals transmitted by the above auxiliary lines, which carry said signals from one front to the other of the memory device. Said auxiliary lines (i.e., additional to the data bus 3) can be defined as global in the conventional memory device, in contrast with the term "local" used to define the auxiliary lines 7, on one side of the memory device, and 7', on the other side, shown in figure 1. Figure 6 is a chart of the timings of the signals shown in figure 5 in the case of the memory device according to the invention. In the memory device according to the invention, the data bus 3 is timed appropriately during the normal reading cycle so as to use it, in the periods 31 during which it would normally be inactive, for the transmission of the signals ROC, CONF, and ISTR, thus avoiding the need to have auxiliary lines that connect the input side to the output side of the memory device. The data bus 3 is used to transmit the signals ROC, CONF, and ISTR by utilizing the timing signals ATD, PC, and EQ that are normally present in the memory device, by virtue of the timer means 8. The signal ATD, at the beginning of the memory read cycle, has the following effects: it presets the signals PC and EQ (this step corresponds to the second of the above-mentioned intervals); it sets to the tristate mode the structures 5 that connect the memory matrix (in particular the sense amplifiers, not shown) to the data bus 3, deactivating bus control, in order to be able to utilize the data bus during its inactive period, i.e., before the data of the memory matrix can be read reliably and can be transmitted by said bus; it keeps in the tristate mode the enabling structures 5' that receive in input the signals CONF, ISTR, and ROC that originate from the lines 7; said structures 5' are close to assuming control of the data bus 3 for transmission of said signals to the corresponding lines 7' arranged at the other side of the memory device. The time interval 31 is therefore used to transmit the signals ROC, CONF, and ISTR on the data bus 3. The signal PC, in addition to its normal function of precharging the nodes affected by the reading operation, samples the data present on the data bus 3, determining their charging time in the latches 6. The signal PC also presets to a high impedance the tristate structures 5', freeing the data bus 3 for the transmission of the data that originate from the memory matrices 1 and 2 in the interval referenced by 30. In detail, the operation of the synchronization means 8 is as follows. When a burst variation of the signal ATDn occurs, so that said signal goes from high to low, the signal PC switches from low to high and so does the signal EQ. Likewise, with a delay with respect to the switching of said signals, the signal SEND switches from low to high and the signal READ also switches from low to high with an additional delay. The switching of the signal SEND enables the connection between the local line, which carries the signals ROC+CONF+ISTR, and the data bus 3 for transmission of said signals on the data bus 3 within a first step of the reading cycle of the memory. The enabling structures of the tristate type 5' thus receive in input the information signals, exemplified in this case, by way of example, by ROC, ISTR, and CONF, and the timing signal SEND, which is related to the signal ATD (in our case, ATDn). When the signal SEND is low, and therefore when ATDn is high and PC and EQ are low, the transistor 12 is on, the transistor 18 is on, the pass transistors 15 and 16 are off, and the transistors 13 and 14 are off: accordingly, the structure 5' is at high impedance and the connection between the local bus 7 and the internal bus 3 is interrupted. In figure 2, the data that enter the tristate structure are referenced by DATA-IN, since said structure is similar for the tristate structures 5' and for the tristate structures 5, and therefore in the first case DATA-IN references the information signals ROC, ISTR, and CONF, whereas in the second case it references the data that originate from the memory matrix and are designated by DATA in figures 5 and 6. For the tristate structures 5, instead of the signal SEND in input there is the signal RM (Read Mode) that designates the step for downloading the data of the matrix onto the data bus 3. Therefore, if SEND is low, access to the data bus 3 is denied to the information signals ROC, CONF, and ISTR, and is obviously allowed to the data DATA of the memory matrices 1 and 2, which are transmitted in the interval 30. In this case, therefore, the signal RM is high, so that the data that originate from the memory matrix propagate on the data bus 3 (interval 30 of figure 6). Instead, when the signal SEND switches from low to high, therefore every time ATDn has a burst variation from high to low, the signals PC and EQ go high and the following operation occurs for the tristate structures 5': the transistors 12 and 18 are off, the transistors 15 and 16 are on, and so is one of the two transistors 13 or 14 according to the data item, respectively "1" or "0". Accordingly, the structures 5' enable the transit of the data in input, i.e., the signals ROC, CONF, and ISTR, to the data bus 3, at the time when said data bus would be inactive (interval 31 of figure 6). The similar tristate structures 5 that interface with the memory matrices 1 and 2 at the data bus 3 are in fact at high impedance, since the signal RM in input is low (i.e., the matrix data read mode has not been defined yet). An inversion of the input signal occurs in the above described tristate structures 5 and 5'; i.e., if a high DATA-IN (which, as described, corresponds to DATA in one case and to ROC+CONF+ISTR in the other) occurs in input, a low DATA is present at the output on the data bus 3, and vice versa. The inversion is of course not indispensable for the execution of the memory device according to the invention, but is used herein for convenience in implementation. If inversion is not necessary, one must use tristate structures 5 and 5' that are modified with respect to the one shown in figure 2. The signal PC samples the data present on the data bus 3, determining their charging time in the latches 6. Therefore, if PC is high, the signal DATA in input to the latch configures said latch; otherwise, if PC is low, the signal DATA is "transparent" for the latch. In the first case, the data are charged in the latches 6 for sending to the lines 7', whereas in the second case they are ignored. In practice it has been observed that the memory device having a timesharing bus according to the invention fully achieves the intended aim, since it allows to use the same data bus 3, by virtue of an appropriate timing during the read cycle, for multiple internal functions. In this manner it is in fact possible to transmit over the same bus both the data that originate from the memory matrix and the information data. The timing allows to utilize the time intervals during which the data bus 3 is inactive to transmit said data, subsequently freeing the bus for the transmission of memory data. In this manner, it is avoided to provide long connecting lines between one side and the other of the matrix for transferring information data, with consequent advantages in reliability, area occupation, and inspection activity. The signals used for the timing of the data bus are the signals ATD, PC, and EQ, which are fundamental for a normal reading cycle of a memory and are therefore always present in the device. The result is a transmission system that is very compact and flexible and allows to optimize the utilization of the data bus 3. The device thus conceived is susceptible of numerous modifications and variations, all of which are within the scope of the inventive concept. Thus, for example, the data lines 7 and 7' can be configured as auxiliary data buses without modifying any detail of the above-described configuration. The information signals, in addition to being stored in the latches 6, can be sent to the output buffers 4, since the latches 6 are connected to the data bus 3. The lines that compose the data bus 3 can also be used so as to group the lines in two or more groups, thus assigning multiple meaning levels to the data bus. In other words, by combining as a product the two or more groups, it is possible to use part of the lines of the bus to modify the meaning of a same combination; in this manner, with a decoding approach it is possible to assign to each particular configuration of the second group a different selection or activation, guided by the first group. The disadvantage of subtracting some lines from the data bus is widely compensated by the possibility of considerably extending the meaning levels that can be assigned to the other lines. Finally, all the details may furthermore be replaced with other technically equivalent elements. In practice, the materials employed, so long as they are compatible with the specific use, as well as the dimensions, may be any according to the requirements and the state of the art. Where technical features mentioned in any claim are followed by reference signs, those reference signs have been included for the sole purpose of increasing the intelligibility of the claims and accordingly such reference signs do not have any limiting effect on the interpretation of each element identified by way of example by such reference signs.

Claims: Non-volatile memory device, comprising an internal bus (3) for the transmission of data and other information of said memory to output pads; timer means (8); and means (5,5') for enabling/disabling access to said bus; characterized in that said timer means (8) times said internal bus to reroute information signals (ROC, CONF, ISTR) of the memory device that originate from local auxiliary lines (7) onto said internal bus (3) when said bus is in an inactive period during a normal cycle for reading data of the memory, said timer means (8) driving said enabling/disabling means (5,5') to allow/deny access to said internal bus on the part of said information signals or of the data from or to the memory. Non-volatile memory device according to claim 1, characterized in that it also comprises storage means adapted to store said information signals synchronously with the driving of said means for enabling/disabling the access of said information signals to the bus. Non-volatile memory device according to claim 1, characterized in that said timer means receive in input an address transition detection signal of said memory and a signal for requesting the reading of said memory. Non-volatile memory device according to claim 1, characterized in that said enabling/disabling means comprise enabling/disabling means for allowing/denying the access of said information signals to said internal bus, and enabling/disabling means for allowing/denying the access of the data of the memory to said internal bus. Non-volatile memory device according to claim 3, characterized in that said timer means are adapted to generate the signals for correctly reading and capturing the data of said memory, a timing signal for driving said enabling/disabling means for the access of said information signals to the bus, and a read mode signal for driving said enabling/disabling means for the access of the memory data to said internal bus. Memory device according to claim 5, characterized in that said means for enabling/disabling the access of the information signals to said internal bus receive in input the information signals and the timing signal generated by said timer means. Memory device according to claim 5, characterized in that said means for enabling/disabling the access of the memory data to said internal bus receive in input said memory data and the read mode signal generated by said timer means. Memory device according to claim 1, characterized in that said storage means are connected, in output to the memory device, between said internal bus for receiving said information data and local output auxiliary lines. Memory device according to claim 1, characterized in that said means for enabling/disabling the access of said information signals and of the memory data to the internal bus are tristate circuits. Memory device according to claim 2, characterized in that it comprises means for enabling/disabling said storage means, adapted to enable/disable the storage of said information signals. Memory device according to claim 2, characterized in that said means for storing information signals are latch circuits. Memory device according to claim 2, characterized in that said information signal storage means are flip-flop circuits. Memory device according to claim 2, characterized in that said information signal storage means are equal in number to the lines of said internal bus. Memory device according to claim 9, characterized in that said means for enabling/disabling the access of the data of said memory to the internal bus are equal in number to the lines of said internal bus. Memory device according to claim 8, characterized in that said local auxiliary lines and said local auxiliary output lines are arranged at opposite sides of said memory device, the transmission of data between said local lines occurring exclusively by means of said internal bus. Memory device according to claim 1, characterized in that said local auxiliary lines form a local auxiliary bus. Memory device according to claim 1, characterized in that said internal bus is adapted to transmit said information signals to said output terminals. Memory device according to one or more of the preceding claims, characterized in that it comprises one or more of the described and/or illustrated characteristics. Data transmission method for a non-volatile memory device comprising timer means, a timesharing internal bus, and means for enabling/disabling the access of information signals of said device and of memory data to the bus, comprising the steps of: detecting an address transition signal in input to said timer means; presetting, by virtue of said timer means, signals for correctly reading and capturing the data of the memory; keeping at high impedance said means for enabling/disabling the access of said memory data to the internal bus, in order to prevent the access of the memory data in a first step of the reading cycle of said memory; transmitting, on the internal bus, said information signals that originate from auxiliary lines in a first step of a normal memory reading cycle, in which the memory data of the memory are not yet ready for correct reading; presetting at a high impedance said means for enabling/disabling the access of said information signals to the internal bus and allowing the transmission of the memory data of the memory to said internal bus, during said normal memory cycle. Method according to claim 19, characterized in that it furthermore comprises the step that consists in storing in storage means said information signals transmitted over said internal bus. Method according to claim 19, characterized in that both the transmission of information signals and the transmission of memory data over said internal bus occur in a mutually exclusive manner, in different times, during the same normal reading cycle of the memory device.

Inventors: BARCELLA ANTONIO, FONTANA MARCO, PASCUCCI LUIGI, ROLANDI PAOLO, BARCELLA, ANTONIO, FONTANA, MARCO, PASCUCCI, LUIGI, ROLANDI, PAOLO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1996
Main classification: G11C7
IPC codes: G11C16, G11C7