High voltage withstanding circuit and voltage level shifter

Abstract: A switch circuit having a high withstanding voltage and low driving ability and another switch circuit having a low withstanding voltage and high driving ability are connected to a specified node in parallel. When discharging the charges of the specified node, the switch circuit having the high withstanding voltage is turned ON and the switch circuit having the great driving ability is then turned ON. Accordingly, it is sufficient that only the transition of the logical voltage of a switch circuit having the high withstanding voltage is taken into consideration to set the ON timing of a switch circuit having the high driving ability. Consequently, timing setting can be performed easily. After the switch circuit having the high driving ability is turned ON, a discharge path for the charges of the specified node takes two paths which passes through both switch circuits in parallel. Consequently, an operating speed can be increased.

Description: BACKGROUND OF THE INVENTION The present invention relates to a high voltage withstanding circuit having a high voltage source and to a voltage level shifter using the high voltage withstanding circuit. From DE 43 36 887 A an integrated semiconductor circuit is known having a contact pad for receiving a predetermined potential. A line is connected to the contact pad for transmitting the potential to an output device which receives the potential over the line and generates an output signal at the predetermined potential level at a first output node in response to a first data signal. Similarly, a second output device generates an output signal at the predetermined potential level at a second node in response to a second data signal. The distance between the second output device and the contact pad is larger than the distance between the first output device and the contact pad. The second output device has an adjustment component for raising the drive rate of the second output node to be the same as for the first output node. EP-A-0 348 051 discloses an output circuit having a voltage-level shifting circuit and supplying a high voltage output signal responsive to a low voltage input signal. The output circuit includes a pull-up circuit and a pull-down circuit. Each pull-up and pull-down circuit includes two transistors. One of the transistors in each respective circuit starts the pull-down or pull-up with a predetermined time delay with respect to the pull-up or pull-down of the remaining transistor. At the static state, the capacitance at the output terminal is charged or discharged by the two transistors in the respective pull-up and pull-down circuits. In general, it is required that a high voltage withstanding circuit having a high voltage source can operate well without breakdown caused by a high voltage. A N channel MOS transistor has the characteristics shown in Fig. 23. In the figure, when a gate voltage Vgn is 0 V, an OFF-state withstanding voltage (which is obtained during OFF operation) is 15 V or more. When the gate voltage Vgn exceeds 0 V, an ON-state withstanding voltage (which is obtained during ON operation) is reduced to about 9 V. A P channel MOS transistor has the characteristics shown in Fig. 24. In the figure, when a gate voltage Vgp is 15 V, the OFF-state withstanding voltage is 15 V or more. When the gate voltage Vgp is less than 15 V, the ON-state withstanding voltage is 15 V or more. Referring to the high voltage withstanding circuit having N and P channel MOS transistors, a hot carrier is generated if a high voltage (for example, 12 V) is continuously applied to the source and drain of the N channel MOS transistor for a long time when turning ON the N channel MOS transistor. Consequently, the N channel MOS transistor is sometimes broken down. Japanese Laid-Open Patent No. 5-259891 and the like have disclosed a high voltage withstanding circuit which prevents the breakdown of the N channel MOS transistor. Such a high voltage withstanding circuit generally controls a current which flows to transistors which compose an inverter to be a clocked inverter, thereby a hot carrier can be prevented to obtain a high withstanding voltage, which will be described below. Fig. 21 shows a high voltage withstanding circuit composing the clocked inverter according to the prior art. In Fig. 21, VPP designates a high voltage source and VSS designates a ground voltage source. P channel MOS transistors Qp211 and Qp212 and N channel MOS transistors Qn211 and Qn212 are provided in series between the voltage sources VPP and VSS. N211 designates an output node for connecting the P channel MOS transistor Qp212 and the N channel MOS transistor Qn212. N212 designates a node for connecting the P channel MOS transistors Qp211 and Qp212. N213 designates a node for connecting the N channel MOS transistors Qn211 and Qn212. A control signal C211 is input to the gates of the P and N channel MOS transistors Qp211 and Qn211. A control signal C212 is input to the gate of the P channel MOS transistor Qp212. A control signal C213 is input to the gate of the N channel MOS transistor Qn212. The operation of the high voltage withstanding circuit according to the prior art will be described below with reference to a timing chart shown in Fig. 22. At first, the control signals C211, C212 and C213 have logical voltages "L", "L" and "H". The nodes N211 to N213 have the logical voltage "H" (a high voltage Vh of the high voltage source VPP). At a time t20, the control signals C212 and C213 are set to have the logical voltages "H" and "L". The P and N channel MOS transistors Qp212 and Qn212 are turned OFF so that the output node N211 is floated. Subsequently, when the control signal C211 is set to have the logical voltage "H" at a time t21, the N channel MOS transistor Qn211 is turned ON so that the node N213 starts the transition of the logical voltage from "H" to "L". Then, at the stage where a drop in voltage of the node N213 is advanced to some extent, for example, at a time t22 when the voltage of the node N213 is dropped to the voltage which is half of the high voltage Vh, the control signals C212 and C213 are set to have the logical voltages "L" and "H". Consequently, the N channel MOS transistor Qn212 is turned ON so that the output node N211 is connected to the ground voltage source VSS. As a result, the voltage of the output node N211 starts the transition from "H" to "L". At this time, the difference between the voltage of the output node N211 and that of the node N213, that is, half of the high voltage Vh is applied to the N channel MOS transistor Qn212, and the difference between the voltage of the node N213 and the ground voltage of the ground voltage source VSS, that is, half of the high voltage Vh is applied to the N channel MOS transistor Qn211. Consequently, a current which flows to the N channel MOS transistors Qn211 and Qn212 is limited so that the transistors Qn211 and Qn212 become hard to break down. In the high voltage withstanding circuit according to the prior art described above, however, the N channel MOS transistors Qn211 and Qn212 are connected in series. Accordingly, it is necessary to consider the transition of the logical voltage of the N channel MOS transistor Qn 211 from "H" to "L" and that of the logical voltage of the N channel MOS transistor Qn212 from "H" to "L" so as to set the time t22. For this reason, it is hard to set the clock timing of the time t22. As a result, if the time t22 is not set properly, the N channel MOS transistors Qn211 and Qn212 are broken down. Since the N channel MOS transistors Qn211 and Qn212 are connected in series, the driving ability is small and an operating speed is low. In particular, if the capacity of the output node N211 is great, it is much harder to set the timing of the time t22 and the operating speed is decreased still more. SUMMARY OF THE INVENTION It is an object of the present invention to provide a high voltage withstanding circuit in which a clock timing can be set easily and an operating speed can be increased. This object is attained by the features of claim 1. It is also attained by the circuit disclosed in DE 43 36 887 A but there a larger increase of the lagout area than in the present invention is needed. Preferred embodiments are subject matter of the claims dependent thereof. Furthermore, the present invention provides a voltage level shifter which inputs an external signal that is changed to have a predetermined voltage and a ground voltage, and outputs a signal having the ground voltage when the input signal has the predetermined voltage and outputs a signal having a higher voltage than the predetermined voltage when the input signal has the ground voltage, comprising the features of claim 12. Preferred embodiments thereof are subject matter of the respective sub-claims. According to the above structure of the present invention, the third switch circuit having the high withstanding voltage is first turned ON when changing the logical voltage of the specified node from "H" to "L". Consequently, the specified node is connected to the ground voltage source so that the voltage of the specified node is dropped. Then, the second switch circuit is turned ON when a preset time passes. Accordingly, it is sufficient that only the transition of the logical voltage of the third switch circuit from "H" to "L" is taken into consideration to set the ON timing of the second switch circuit. Thus, timing setting can be performed easily. After the second switch circuit is turned ON, a discharge path for the charges of the specified node takes two paths which passes through the second and third switch circuits in parallel. Consequently, the operating speed can be increased. This is also attained in the circuit disclosed in EP-A-O 348 051 but there a larger increase of the lagout area is needed. The above object and novel characteristics of the present invention will be more completely apparent from the following detailed description and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings show the preferred embodiments of the present invention in which: Figure 1 is a block diagram showing the structure of a high voltage withstanding circuit according to a first embodiment of the present invention; Figure 2 is a timing chart showing the operation of the high voltage withstanding circuit according to the first embodiment of the present invention; Figure 3 is a diagram showing a first specific circuit according to the first embodiment of the present invention; Figure 4 is a timing chart showing the operation of the first specific circuit according to the first embodiment of the present invention; Figure 5 is a diagram showing a second specific circuit according to the first embodiment of the present invention; Figure 6 is a diagram showing the relationship between the gate length and width of a transistor and the ON-state withstanding voltage thereof; Figure 7 is a timing chart showing the operation of a third specific circuit according to the first embodiment of the present invention; Figure 8 is a diagram showing a fourth specific circuit according to the first embodiment of the present invention; Figure 9 is a timing chart showing the operation of the fourth specific circuit according to the first embodiment of the present invention; Figure 10 is a block diagram showing the structure of a high voltage withstanding circuit according to a second embodiment of the present invention; Figure 11 is a timing chart showing the operation of the high voltage withstanding circuit according to the second embodiment of the present invention; Figure 12 is a diagram showing a specific high voltage withstanding circuit according to the second embodiment of the present invention; Figure 13 is a timing chart showing the operation of the specific high voltage withstanding circuit according to the second embodiment of the present invention; Figure 14 is a diagram showing a high voltage withstanding circuit according to a third embodiment of the present invention; Figure 15 is a timing chart showing the operation of the high voltage withstanding circuit according to the third embodiment of the present invention; Figure 16 is a diagram showing a voltage level shifter according to a fourth embodiment of the present invention; Figure 17 is a timing chart showing the operation of the voltage level shifter according to the fourth embodiment of the present invention; Figure 18 is a diagram showing a voltage level shifter according to a fifth embodiment of the present invention; Figure 19 is a diagram showing a voltage level shifter according to a sixth embodiment of the present invention; Figure 20 is a diagram showing a voltage level shifter according to a seventh embodiment of the present invention; Figure 21 is a diagram showing a specific high voltage withstanding circuit according to the prior art; Figure 22 is a timing chart showing the operation of the specific high voltage withstanding circuit according to the prior art; Figure 23 is a diagram showing the ON-state withstanding voltage characteristics of an N channel MOS transistor used for the high voltage withstanding circuit; and Figure 24 is a diagram showing the ON-state withstanding voltage characteristics of a P channel MOS transistor used for the high voltage withstanding circuit. DETAILED DESCRIPTION OF THE INVENTION Preferred embodiments of the present invention will be described below with reference to the drawings. (First Embodiment of the Present Invention) Fig. 1 is a block diagram showing a high voltage withstanding circuit according to a first embodiment of the present invention. In Fig. 1, VPP designates a high voltage source for generating a predetermined high voltage (for example, 12 V), VSS designates a ground voltage source, S11 to S13 designate first to third switch circuits, and N11 designates an output node (a specified node). The first switch circuit S11 is provided between the high voltage source VPP and the output node N11, and is turned ON on receipt of a control signal C11. The second switch circuit S12 is provided between the output node N11 and the ground voltage source VSS. The third switch circuit S13 is provided in parallel with the second switch circuit S12. The second switch circuit S12 has a low withstanding voltage and great driving ability, and is turned ON on receipt of a control signal C12. The third switch circuit S13 has a high withstanding voltage and small driving ability, and is turned ON on receipt of a control signal C13. The operation of the high voltage withstanding circuit shown in Fig. 1 will be described below with reference to the timing chart of Fig. 2. At first, the control signals C11, C12 and C13 are not output at all. Accordingly, all the switch circuits S11 to S13 are turned OFF and the output node N11 has a logical voltage "L". When the control signal C11 is output at a time tll, the first switch circuit S11 is turned ON so that the high voltage source VPP is connected to the output node N11. Accordingly, the output node N11 is set to have a logical voltage "H". Then, the output of the control signal C11 is stopped at a time t12. Consequently, the first switch circuit S11 is turned OFF so that the output node N11 is floated with the logical voltage "H" kept. When the control signal C13 is output at a time t13, the third switch circuit S13 having a high withstanding voltage is turned ON. Consequently, the output node N11 is connected to the ground voltage source VSS so that it starts the transition of the logical voltage from "H" to "L". At a time t14 when the voltage of the output node N11 is dropped to a value which is less than the intermediate potential between the logical voltages "H" and "L", the control signal C12 is output. As a result, the second switch circuit S12 having the great driving ability is turned ON so that the output node N11 is connected to the ground voltage source VSS through the second switch circuit S12. In this state, the voltage of the output node N11 reaches the logical voltage "L". It is sufficient that only the transition of the third switch circuit S13 from ON to OFF (the transition of the logical voltage from "H" to "L") is taken into consideration to set the timing of the ON operation of the second switch circuit S12, that is, the time t14 when the control signal C12 is output. Consequently, the timing can be set easily. In addition, after the second switch circuit S12 is turned ON, the output node N11 is connected to the ground voltage source VSS through the third switch circuit S13 having the small driving ability and the second switch circuit S12 having the great driving ability. Consequently, a speed at which charges are discharged is increased so that the voltage of the output node N11 is changed from the intermediate voltage to the logical voltage "L" at a high speed. (First Specific Example of First Embodiment) Fig. 3 shows a first specific circuit according to the first embodiment of the present invention. In Fig. 3, a first switch circuit S11 is formed by a P channel MOS transistor (first MOS transistor) Qp31. The P channel MOS transistor Qp31 has a source connected to a high voltage source VPP, a drain connected to an output node N11, and a gate to which a control signal C11 is input. A second switch circuit S12 is formed by an N channel MOS transistor (second MOS transistor) Qn31. The N channel MOS transistor Qn31 has a source connected to a ground voltage source VSS, a drain connected to the output node N11, and a gate to which a control signal C12 is input. A third switch circuit S13 is formed by an N channel MOS transistor (third MOS transistor) Qn32. The N channel MOS transistor Qn32 has a source connected to the ground voltage source VSS, a drain connected to the output node N11, and a gate to which a control signal C13 is input. The N channel MOS transistor (second MOS transistor) Qn31 has a low withstanding voltage and great driving ability. The N channel MOS transistor (third MOS transistor) Qn32 has a high withstanding voltage and small driving ability. Accordingly, the specific circuit according to the present example operates as shown in the timing chart of Fig. 4. More specifically, when the control signal C11 is output at a time t11 (that is, "H" (the voltage of the high voltage source VPP) is changed to "L" (the voltage of the ground voltage source VSS)), the P channel MOS transistor Qp31 is turned ON so that the output node N11 is set to have a logical voltage "H". Then, the output of the control signal C11 is stopped at a time t12 to turn OFF the P channel MOS transistor Qp31 so that the output node N11 is floated. Thereafter, when the control signal C13 is output (that is, the transition from "L" to "H") at a time t13, the N channel MOS transistor Qn32 having the high withstanding voltage is turned ON so that the output node N11 starts the transition of the logical voltage from "H" to "L". When the control signal C12 is output (that is, the transition from "L" to "H") at a time t14, the N channel MOS transistor Qn32 having the great driving ability is also turned ON so that the output node N11 is set to have the logical voltage "L" at a high speed. The specific circuit according to the present example has a high withstanding voltage (15 V) surely. Furthermore, a speed at which the logical voltage of the output node N11 is changed from "H" to "L" is increased by about 50 % or more as compared with the prior art. (Second Specific Example of First Embodiment) Fig. 5 shows a second specific circuit according to the first embodiment of the present invention. In Fig. 5, a third switch circuit S13 comprises N channel MOS transistors Qn32A and Qn32B which are connected in parallel with each other. The N channel MOS transistors Qn32A and Qn32B are turned ON on receipt of a control signal C13. In addition, the N channel MOS transistors Qn32A and Qn32B have great gate lengths I. and small gate widths W. Since other structures are the same as the structure of the first specific circuit described above, the same reference numbers designate the same portions whose description will be omitted. Since the operation of the specific circuit according to the present example is the same as that of the first specific circuit shown in Fig. 4, its description will also be omitted. Fig. 6 shows the ON-state withstanding voltage characteristic curve of the N channel MOS transistor. As seen from Fig. 6, as the gate length L is increased or the gate width W is decreased, the ON-state withstanding voltage of the N channel MOS transistor becomes higher. If a plurality of N channel MOS transistors having a great gate length L and a small gate width W are connected in parallel as in the specific circuit of the present example, the ON-state withstanding voltages thereof can be increased. Thus, the ON-state withstanding voltage is increased because a hot carrier can be prevented from occurring in a transistor portion. If an N channel MOS transistor having a gate length L of 1 µ m and a gate width W of 100 µ m is used, the ON-state withstanding voltage is 4 V. If 20 N channel MOS transistors having a gate length L of 5 µ m and a gate width W of 25 µ m are connected in parallel, the ON-state withstanding voltages of the N channel MOS transistors are increased to 10 V without deteriorating the driving ability thereof. It is the most preferable that the N channel MOS transistors Qn32A and Qn32B have great gate lengths L and small gate widths W. However, even if the N channel MOS transistors having either the great gate lengths L or the small gate widths W are used, the same effects can be obtained. Furthermore, also in the case where a plurality of N channel MOS transistors having the small gate length L are connected in series, the same effects can be obtained. According to the present example, a high voltage withstanding circuit having more reliability than that of the first specific circuit described above can be formed without increasing the layout area. (Third Specific Example of First Embodiment) A third specific circuit according to the first embodiment of the present invention will be described below. The structure of the specific circuit according to the present example adopts that of the first or second specific circuit described above except for the voltage value of a control signal. Fig. 7 is a timing chart showing the specific circuit according to the present example. In Fig. 7, control signals C11 and C12 are controlled so as to have the voltages of a high voltage source VPP and a ground voltage source VSS. A control signal C13 is controlled so as to have a predetermined voltage V0 which is lower than the voltage of the high voltage source VPP, and the voltage of the ground voltage source VSS. According to the specific circuit of the present example, the control signal C13 is changed from the voltage of the ground voltage source VSS to the predetermined voltage V0 which is lower than the voltage of the high voltage source VPP at a time t13 as shown in Fig. 7. At this time, the gate voltage of an N channel MOS transistor Qn32 (or Qn32A and Qn32B) is low, that is, equal to the predetermined voltage V0 so that a hot carrier can be prevented from occurring. Accordingly, the N channel MOS transistor Qn32 (or Qn32A and Qn32B) is hard to break down. Thus, a high voltage withstanding circuit having much better reliability can be formed. (Fourth Specific Example of First Embodiment) Fig. 8 shows a fourth specific circuit according to the first embodiment of the present invention. The specific circuit shown in Fig. 8 differs from the first specific circuit shown in Fig. 3 in that a third switch circuit S13 has a different structure. In other words, the third switch circuit S13 is formed by the N channel MOS transistor Qn32 in Fig. 3, while the third switch circuit S13 of the present example is formed by a P channel MOS transistor Qp82. According to the specific circuit of the present example, a control signal C13 which is input to the gate of the P channel MOS transistor Qp82 is output (changed from "H" to "L") at a time t13 as shown in the timing chart of Fig. 9. As seen from the characteristic charts of a transistor shown in Figs. 23 and 24, generally, the ON-state withstanding voltage of the P channel MOS transistor is higher than that of the N channel MOS transistor. According to the specific circuit of the present example, when discharging the charges of an output node N11, the charges are discharged by the P channel MOS transistor Qp82 having a high withstanding voltage and then by the N channel MOS transistor Qn31 having great driving ability at a high speed. According to the specific circuit of the present example, if the gate voltage of the P channel MOS transistor Qp82 is 0 V, the charges cannot be discharged completely. Consequently, the charges are completely discharged by the N channel MOS transistor Qn31 which is connected to the P channel MOS transistor Qp82 in parallel. (Second Embodiment of the Present Invention) Fig. 10 is a block circuit diagram showing a second embodiment of the present invention. A high voltage withstanding circuit shown in Fig. 10 is formed by adding a resistor R101 to the high voltage withstanding circuit according to the first embodiment shown in Fig. 1. The resistor R101 is provided between an output node N11 and the output node N 11 side (that is, a node N102 shown in Fig. 10) of a third switch circuit S13. The operation of the high voltage withstanding circuit according to the present embodiment is the same as that of the high voltage withstanding circuit according to the first embodiment. As seen from the timing chart of Fig. 11, the time for which a high voltage is applied to the third switch circuit S13 is reduced because the resistor R101 is provided. The time for which the high voltage is applied is determined by the capacity of the output node N11 and the value of the resistor R101. Accordingly, as the time for which the high voltage is applied to the third switch circuit S13 is reduced, a hot carrier can be prevented from occurring more effectively. Consequently, higher voltage withstanding properties can be obtained as compared with the high voltage withstanding circuit according to the first embodiment described above. (Specific Example of Second Embodiment of the Present Invention) Fig. 12 shows a specific circuit according to the second embodiment of the present invention. The specific circuit of the present example is formed by adding a resistor 101 to the structure of the first specific circuit according to the first embodiment shown in Fig. 3. Fig. 13 shows the operating timing of the specific circuit of the present example. The high voltage withstanding circuit according to the second embodiment is not restricted to the specific circuit of the present example but can be formed by the structure of the second specific circuit according to the first embodiment shown in Fig. 5, the timing of the control signal of the third specific circuit shown in Fig. 7, and the structure of the fourth specific circuit shown in Fig. 8. (Third Embodiment of the Present Invention) Fig. 14 is a circuit diagram according to a third embodiment of the present invention. According to the present embodiment, the structure of a third switch circuit S13 is changed. More specifically, the third switch circuit S13 comprises N channel MOS transistors Qn142, Qn143 and Qn144. The first and second N channel MOS transistors Qn144 and Qn142 are connected on a node N142 in series. The drain of the first N channel MOS transistor Qn144 which is provided on the upper side in Fig. 14 is connected to an output node N11. The second N channel MOS transistor Qn142 provided on the lower side in Fig. 14 has a source connected to a ground voltage source VSS and a gate to which a control signal C13 is input. The third N channel MOS transistor Qn143 has a source to which the control signal C13 is input, a drain connected to the gate of the first N channel MOS transistor Qn144, and a gate connected to a high voltage source VPP. According to the present embodiment, when the control signal C13 is output, (that is, a logical voltage (the voltage of a high voltage source VPP) is changed from "L" to "H") at a time t13 as shown in the timing chart of Fig. 15, the control signal C13 is input to the gate of the first N channel MOS transistor Qn144 and a voltage which is lower than that of the control signal C13 by the threshold voltage of the third N channel MOS transistor Qn143 is input to the gate of the second N channel MOS transistor Qn142. As a result, the first and second transistors Qn144 and Qn142 are turned ON so that the charges of the output node N11 are discharged to the ground voltage source VSS. Consequently, the voltage of the output node N11 is changed from "H" to "L". During this transition, it is hard for a current to flow to the first N channel MOS transistor Qn144. Accordingly, the first and second transistors Qn144 and Qn142 are hard to break down. (Fourth Embodiment of the Present Invention) Fig. 16 is a circuit diagram showing a fourth embodiment of the present invention. The present embodiment provides a voltage level shifter using a high voltage withstanding circuit according to the present invention. In Fig. 16, first, second and third switch circuits S11, S12 and S13 have the same structures as that of the first specific circuit according to the first embodiment shown in Fig. 3. Other structures will be described below. A control signal (external signal) C13 is changed to have logical voltages "H" and "L". The logical voltage "H" is a predetermined voltage having a normal value within a range, for example, between 3.3 V and 5 V. The control signal C13 is input to the gate of an N channel MOS transistor (third switch circuit) Qn32, and passes through an N channel MOS transistor Qn163 and is changed to a control signal C11 whose voltage is dropped by the threshold voltage of the N channel MOS transistor Qn163. The control signal C11 is input to the gate of a P channel MOS transistor (first switch circuit) Qp31. A voltage source VDD having the same voltage as the logical voltage "H" of the control signal C13 is connected to the gate of the N channel MOS transistor (another N channel MOS transistor) Qn163. The reference numeral 16 designates a signal delay circuit. The signal delay circuit 16 delays the control signal C13 by a set time. The delayed signal is input as a control signal C12 to the gate of an N channel MOS transistor (second switch circuit) Qn31. Qp162 designates a P channel MOS transistor having a gate connected to an output node N11, a source connected to a high voltage source VPP, and a drain connected to the gate of the P channel MOS transistor (first switch circuit) Qp31. Accordingly, the P channel MOS transistor Qp162 is turned ON when the voltage of the output node N11 is changed from "H" to "L". Consequently, the high voltage (for example, 12 V) of the high voltage source VPP is applied to the gate of the P channel MOS transistor (first switch circuit) Qp31 to be completely turned OFF. Accordingly, the voltage level shifter of the present embodiment operates as follows. At first, the control signals C11, C12 and C13 have the logical voltage "L" and the output node N11 has the logical voltage "H" as shown in the timing chart of Fig. 17. Then, when the control signal C13 is set to have the logical voltage "H" at a time t13, an N channel MOS transistor (third switch circuit) Qn32 having a high withstanding voltage is turned ON so that the output node N11 is connected to a ground voltage source VSS. Consequently, the voltage of the output node N11 starts the transition from "H" to "L". In this case, the control signal C11 is also set to have the logical voltage "H" (for example, 3.3 V) so that the P channel MOS transistor (first switch circuit) Qp31 is turned ON. Consequently, the disconnection between the high voltage source VPP and the output node N11 is started. At a time t14 when a set time has passed, the control signal C12 is output from the signal delay circuit 16 (the logical voltage is changed from "L" to "H") so that the N channel MOS transistor Qn31 (second switch circuit S12) having great driving ability is turned ON. Consequently, the output node N11 is completely set to have the logical voltage "L". At a time t15 when the control signal C13 is set to have the logical voltage "L", the control signal C12 is also set to have the logical voltage "L" at almost the same time. Consequently, the N channel MOS transistors Qn31 and Qn32 (second and third switch circuits S12 and S13) are turned OFF. At this time, since the control signal C11 is also set to have the logical voltage "L", the P channel MOS transistor Qp31 (first switch circuit S11) is turned ON so that the voltage of the output node N11 is set to the logical voltage "H". Consequently, the P channel MOS transistor Qp162 is turned OFF. According to the voltage level shifter of the present embodiment, the control signal C13 which is changed to have the ground voltage and the predetermined voltage (for example, 3.3 V) is converted to a signal which is changed to have the ground voltage and the voltage of the high voltage source VPP (for example, 12 V). The converted signal can be output from the output node N11. (Fifth Embodiment of the Present Invention) Fig. 18 shows a voltage level shifter according to a fifth embodiment of the present invention. In Fig. 18, the voltage level shifter is formed by using the structure of the second specific high voltage withstanding circuit according to the first embodiment shown in Fig. 5. More specifically, the structure of the third switch circuit S13 of the voltage level shifter according to the fourth embodiment shown in Fig. 16 is changed so that the third switch circuit S13 is formed by N channel MOS transistors Qn32A and Qn32B which are connected in parallel, the gate lengths L of the N channel MOS transistors Qn32A and Qn32B are increased and the gate widths W thereof are decreased to raise the ON-state withstanding voltage of the third switch circuit S13. (Sixth Embodiment of the Present Invention) Fig. 19 shows a voltage level shifter according to a sixth embodiment of the present invention. Fig. 19 differs from Fig. 16 showing the fourth embodiment in that an N channel MOS transistor Qn33 is provided as a third switch circuit S13 in series in addition to the N channel MOS transistor Qn32 and a control signal C11, that is, a voltage which is lower than that of a control signal 13 by the threshold voltage of an N channel MOS transistor Qn163 is input to the gate of the N channel MOS transistor Qn33. According to the present embodiment, the voltage of the control signal C11 is lower than that of the control signal 13 by the threshold voltage of the N channel MOS transistor Qn163. Consequently, it is hard for a current to flow to the N channel MOS transistor Qn33. As a result, the third switch circuit S13 is hard to break down. (Seventh Embodiment of the Present Invention) Fig. 20 shows a voltage level shifter according to a seventh embodiment of the present invention. Fig. 20 differs from Fig. 19 showing the sixth embodiment in that the N channel MOS transistor Qn32 is not provided but only an N channel MOS transistor Qn33 which is controlled by a control signal C11 is provided on a third switch circuit S13. According to the present embodiment, the N channel MOS transistor Qn32 is omitted so that a circuit structure can be simplified. In addition, the third switch circuit S13 is hard to break down.

Claims: A high voltage withstanding circuit which operates by using a high voltage source (VPP), comprising: a first switch circuit (S11) connected between said high voltage source (VPP) and a specified node (N11); and second and third switch circuits (S12, S13) connected in parallel between said specified node (N11) and a ground voltage source (VSS), wherein said third switch circuit (S13) alone is turned on to connect said output node (N11) to said ground voltage source (VSS) when said specified wode (N11) has a high voltage of said high voltage source (VPP) and said second switch circuit (S12) is turned on to additionally connect said output node (N11) to said ground voltage source (VSS) when a preset period has passed after said third switch is turned on so that the charges stored in said specified hode are discharged only through said third switch circuit at the beginning of the discharge of the charges characterized in that said second switch circuit (S12) has a lower withstanding voltage in the ON state than the third switch circuit (S13). The high voltage withstanding circuit of Claim 1, wherein a resistor (R101) is provided between said specified node (N11) and said third switch circuit (S13). The high voltage withstanding circuit of Claim 1, wherein when said specified node (N11) has the high voltage of said high voltage source (VPP), said third switch circuit (S13) is turned ON so that the charges stored in said specified node (N11), are discharged through said third switch circuit (S13) at the beginning of the discharge of the charges: and wherein said second switch circuit (S12) is turned ON when a preset period passes after said third switch circuit (S13) is turned ON, and the charges of said specified node (N11) are discharged through said second and third switch circuits (S12,S13). The high voltage withstanding circuit of Claim 3, wherein said second switch circuit (S12) has greater driving ability than that of said third switch circuit (S13). The high voltage withstanding circuit of Claim 1, wherein said third switch circuit (S13) is formed by an N channel MOS transistor (Qn32). The high voltage withstanding circuit of Claim 1, wherein said third switch circuit (S13) is formed by a P channel MOS transistor (Qp 82). The high voltage withstanding circuit of Claim 5 or 6, wherein said third switch circuit (S13) is formed by a MOS transistor (Qn 32). The high voltage withstanding circuit of Claim 5 or 6, wherein said third switch circuit (S13) is formed by a plurality of MOS transistors (Qn32A, Qn32B) having a great gate length (L) which are connected in parallel. The high voltage withstanding circuit of Claim 5 or 6, wherein said third switch circuit is formed by a plurality of MOS transistors (Qn32A, Qn32B) having a small gate width (W) which are connected in parallel. The high voltage withstanding circuit of Claim 1, wherein said third switch circuit (S13) is formed by an N channel MOS transistor (Qn32) which is turned ON when a voltage which is lower than the voltage of said high voltage source (VPP) is applied to the gate thereof; and wherein it is hard for a current to flow through said N channel MOS transistor (Qn32) during ON operation. The high voltage withstanding circuit of Claim 1, wherein said third switch circuit (S13) comprises: first and second N channel MOS transistors (Qn144, Qn142) provided between a specified node (N11) and a ground voltage source (VSS) and connected in series; and a third N channel MOS transistor (Qn143) having a gate connected to the high voltage source (VPP), wherein said second N channel MOS transistor (Qn 142) is turned ON on receipt of a control signal, and said first N channel MOS transistor (Qn144) is turned ON on receipt of said control signal through said third N channel MOS transistor (Qn 143). A voltage level shifter which receives as an input signal, an external signal that is changed to have a predetermined voltage (V0) and a ground voltage (VSS), and outputs a signal having the ground voltage (VSS) when said input signal has said predetermined voltage (VO) and outputs a signal having a high voltage other than said predetermined voltage (VO) when said input signal has the ground voltage (VSS), comprising: a high voltage source (VPP) for generating said high voltage; a first switch circuit (S11) connected between said high voltage source (VPP) and an output node (N11); and second and third switch circuits (S12, S13) connected in parallel between said output node (N11) and a ground voltage source (VSS), wherein said first switch circuit (S11) is turned ON to connect said high voltage source (VPP) to said output node (N11) when said input signal has said ground voltage (VSS), and said third switch circuit (S13) is turned on to connect said output node (N11) to said ground voltage source (VSS) when said input signal has the transition from said ground voltage (VSS) to said predetermined voltage and said second switch circuit (S12) is turned on to additionally connect said output node (N11) to said ground voltage source (VSS) when a preset period has passed after said third switch is turned on characterized in that said third switch circuit (S13) has a higher withstanding voltage in the ON state than said second switch circuit (S12) and Said high voltage is higher than said predetermined voltage. The voltage level shifter of Claim 12, further comprising a signal delay circuit (16) for delaying the input signal by a set time; wherein a signal which is delayed by said signal delay circuit (16) is input to a second switch circuit (S12) to turn ON said second switch circuit (S12) when said input signal is changed to have a predetermined voltage (V0). The voltage level shifter of Claim 12, wherein said second switch circuit (S12) has greater driving ability than that of said third switch circuit (S13). The voltage level shifter of Claim 12, wherein said third switch circuit (S13) is formed by an N channel MOS transistor (Qn32). The voltage level shifter of Claim 15, wherein said external signal is input to the gate of the N channel MOS transistor (Qn32) forming said third switch circuit (S13). The voltage level shifter of Claim 12, wherein said third switch circuit (S13) is formed by a plurality of MOS transistors (Qn32A, Qn32B) having a great gate length (L) which are connected in parallel. The voltage level shifter of Claim 12, wherein said third switch circuit is formed by a plurality of MOS transistors (Qn32A, Qn32B) having a small gate width (W) which are connected in parallel. The voltage level shifter of Claim 15, further comprising another N channel MOS transistor (Qn163) having a gate connected to a voltage source (VDD) for generating said predetermined voltage (V0); wherein said third switch circuit (S13) is formed by two N channel MOS transistors (Qn33, Qn32) which are connected in series; and wherein said external signal (C13) is directly input to the gate of one (Qn32) of the N channel MOS transistors forming said third switch circuit (S13), and said external signal is input to the gate of the other N channel MOS transistor (Qn33) through said another N channel MOS transistor (Qn163). The voltage level shifter of Claim 15, further comprising another N channel MOS transistor (Qn163) having a gate connected to a voltage source (VDD) for generating said predetermined voltage; wherein said third switch circuit (S13) is formed by an N channel MOS transistor (Qn33); and wherein said external signal (C13) is input to the gate of the N channel MOS transistor (Qn33) forming said third switch circuit (S13) through said another N channel MOS transistor (Qn163).

Inventors: CHAYA SHIGEO, HIRANO HIROSHIGE, HONDA TOSHIYUKI, CHAYA, SHIGEO, HIRANO, HIROSHIGE, HONDA, TOSHIYUKI
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1996
Main classification: H03K17
IPC codes: H03K17, H03K3