MEMORY BUS TERMINATION MODULE

Abstract: A memory bus termination module is described for reducing overshoot and undershoot in a communication bus. The module includes circuitry which reduces or eliminates unwanted signal fluctuations. The module can be placed in a personal computer memory bus to allow the computer purchaser to expand memory capabilities, and in particular install high data rate memories. These memories include burst access memories which operate at or above 66 MHz. Two clamping diodes are provided in the termination circuitry and connected to communication lines of the bus.

Description: MEMORY BUS TERMINATION MODULE Technical Field ofthe Invention The present invention relates generally to personal computers and in particular to memory buses in personal computers. Background ofthe Invention Personal computers, as shown in Figures 1 and 2, include a monitor 100, keyboard input 102 and a central processing unit 104. The processor unit typically includes a microprocessor 106, a memory bus circuit 108, and other peripheral circuitry 1 10. The memory bus is provided with a number of expansion sockets to allow the purchaser ofthe personal computer to install additional memory circuits as the user's needs change. A number of expansion sockets for memory upgrades typically exist along a memory bus. The expansion sockets remain empty unless the user decides to upgrade the system's memory by installing additional memory circuits. In general, the characteristic impedance ofthe computer's memory bus interface is designed to match the impedance of a fully loaded memory bus. When the memory bus is fully loaded, therefore, the interface and the bus will be matched. The mismatch in impedance creates a ringing effect on the memory bus which results in overshoot and undershoot in a signal communicated over the bus. Such ringing has not created difficulty in communicating with typical memory circuits. This is due to the limited communication speeds of memory circuits used to-date. Memory circuits, however, are being designed which can operate at increasingly faster communication speeds. Computers which have a memory bus and memory bus interface where the impedance therebetween is mismatched can experience errors in communication when fast data rate memory circuits are installed in a partially empty data bus. For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a computer which can have the memory capacity expanded by an end user and is capable of high speed communication without incurring data errors due to impedance mismatch. Summary of the Invention The above mentioned problems with communicating with high speed memories and other problems are addressed by the present invention and which will be understood by reading and studying the following specification. In particular, the present invention describes a memory bus termination module comprising a module housing adapted to fit into a memory socket of a memory bus, the module housing including communication line input and output connections, and termination circuitry connected to the communication line input and output connections. The module housing can be provided to fit into a socket designed to receive a JEDEC standard circuit package. In another embodiment, a memory bus is described which comprises a plurality of memory circuit expansion sockets, and at least one high data rate memory located in one ofthe memory circuit expansion sockets, the memory bus also comprises a termination module housing located in one ofthe memory circuit expansion sockets and including communication line input and output connections, and termination circuitry having a plurality of clamping diodes connected to the communication line input and output connections. The memory bus can include a high data rate memory which has a minimum data rate of 66 MHz, and can be designed as a synchronous memory circuit. Brief Description ofthe Drawings Figure 1 illustrates a personal computer; Figure 2 is a block diagram ofthe CPU of Figure 1 ; Figure 3 is a memory bus of Figure 2; Figure 4 is an ideal step function signal; Figure 5 is a step function signal with ringing; Figure 6 is a 33 MHz signal pulse on a computer memory bus; Figure 7 is a 66 MHz signal pulse on a computer memory bus; Figure 8 is one embodiment of a termination module ofthe present invention; Figure 9 is a schematic diagram ofthe module of Figure 8; Figure 10 is a schematic diagram of an alternate module of Figure 8; Figure 11 is a schematic diagram of an alternate module of Figure 8; Figure 12 is a schematic diagram of an alternate module of Figure 8; Figure 13 is a schematic diagram of an alternate module of Figure 8; and Figure 14 is a schematic diagram of an alternate module of Figure 8. Detailed Description of the Preferred Embodiment In the following detailed description ofthe preferred embodiments, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the inventions may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that other embodiments may be utilized and that logical, mechanical and electrical changes may be made without departing from the spirit and scope ofthe present inventions. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope ofthe present inventions is defined only by the appended claims. There are a number of integrated circuit memories commercially available. For example, dynamic memory circuits having memory cells arranged to be accessed in a random fashion are referred to as dynamic random access memories, DRAMs. These memories can be produced in a variety of designs which provide different methods of reading from and writing to the dynamic memory cells of the memory. One such method is page mode operation. Page mode operations in a DRAM are defined by the method of accessing a row of a memory cell array and randomly accessing different columns ofthe array. Data stored at the row and column intersection can be read and output while that column is accessed. Page mode DRAMs require access steps which limit the communication speed ofthe memory circuit. A typical communication speed using page mode DRAMs is approximately 33 MHz. An alternate type of memory circuit is the extended data output (EDO) memory which allows data stored at a memory array address to be available as output after the addressed column has been closed. This memory circuit can increase some communication speeds by allowing shorter access signals without reducing the time in which memory output data is available on the memory bus. A more detailed description of a DRAM having EDO features is provided in the "1995 DRAM Data Book" pages 1-1 to 1-30 available from Micron Technology, Inc. Boise, Idaho, the assignee ofthe present application. Yet another type of memory circuit is a burst access memory which receives one address of a memory array on external address lines and automatically addresses a sequence of columns manner without providing additional column addresses on the external address lines. Burst EDO memory circuits are capable of outputting data at significantly faster communication rate than previous memory circuits. Burst EDO memories can operate at speeds in excess of 66 MHz, with potential frequencies of 200 MHz. Another type of high speed memory device is a synchronous memory. These memory devices operate in synchronization with an externally provided clock signal. One type of synchronous memory is a synchronous dynamic random access memory (SDRAM). As described above, a personal computer includes a microprocessor and a memory bus. The computer is usually sold by the manufacture with a partially full memory bus. This allows the purchaser ofthe computer to customize the computer to meet their personal needs. The memory bus interface is designed to have an impedance which matches a fully loaded memory bus. If the memory bus is only partially full, the memory bus and its interface will have a mismatched impedance. Mismatched impedances along a communication line, as known to one skilled in the art, result in signal ringing when a signal is transmitted on the communication line. The ringing is a result of signal "ghosts" which reflect or bounce along the communication line. Figure 3 illustrates a memory bus 108 where the memory socket 112(n) farthest from the interface with the microprocessor 106 does not contain an integrated memory circuit. When a signal is communicated by the microprocessor to the memory bus, signal reflection can occur. As known to one skilled in the art, the reflection created by an open, or unterminated, bus is maximized. Further, because the interface between the microprocessor and the bus is mismatched, a signal reflected by the end ofthe bus will be partially reflected back down the bus by the interface. An ideal step function signal, low to high signal transition, communicated by the microprocessor to a memory bus line is shown in Figure 4. The signal transitions to a high state with little or no fluctuation in the signal. Figure 5 shows a step signal which results from ringing in a communication line. The signal experiences both overshoot and undershoot ofthe desired final signal level. In a worst case situation where the communication line is open and has a high impedance mismatch the overshoot 120 and undershoot 122 can be 50% to 100% ofthe final signal level. The signal ringing is a damped function, such that the ringing decreases in amplitude over time. To appreciate the problems which ringing can create in a memory bus consider the length of a typical signal in a system using 33 MHz memories. The period or signal length would be 30 ns and the ringing incurred would be approximately 3-5 ns for a 2 cm bus. Figure 6 illustrates one positive pulse signal in such a system. The 10 ns of stable signal (15 ns - 5 ns) is adequate time for the signal to be correctly communicated to a memory connected to the bus. If the communication frequency is increased to 66 MHz, the period is decreased to 15 ns, Figure 7. Assuming 5 ns of ringing, the stable signal length is reduced to 2.5 ns. It can be appreciated that errors in communication can occur as the amount of stable signal is reduced. A memory bus termination module is illustrated in Figure 8. The termination module is intended to be placed in the memory expansion socket adapted to receive a single in-line memory module (SIMM). The termination module housing is designed as a SIMM board and placed in the socket 112(n) located the farthest from the microprocessor mother board interface. As such, a preferred embodiment ofthe present invention is a housing or package designed to fit into a standard memory socket, including JEDEC standard memory module pinouts and mechanical dimensions. It will be appreciated by those skilled in the art that this package can be any configuration used in memory circuit and computer bus designs and is not limited to SIMMs. The module contains circuitry which reduces or eliminates the ringing experienced on a partially full memory bus. The memory bus termination module can be installed by the computer manufacture when the computer is assembled. Alternatively, the termination module can be installed by a purchaser ofthe computer when upgrading the system to include high data speed memories, such as burst access memories. Figure 9 illustrates one embodiment ofthe circuitry included in a memory module ofthe present invention. The termination module 125 has two clamping diodes 126 arranged in the module such that they are connected to each communication line ofthe bus. These communication lines include data input / output, address lines, row address signal (RAS*), and column address signal (CAS*). The diodes clamp overshoot and undershoot voltages on the communication lines. Figure 10 illustrates an alternate embodiment ofthe circuitry included in a memory module ofthe present invention. The termination module 125 has clamping capacitors 130 arranged in the module such that they are connected to each communication line of the bus. These communication lines include data input / output, address lines, row address signal (RAS*), and column address signal (CAS*). Figure 11 illustrates an alternate embodiment of the circuitry included in a memory module ofthe present invention. The termination module 125 has clamping capacitors 132 and a line resistor 134 arranged in the module such that they are connected to each communication line ofthe bus. Figure 12 illustrates an alternate embodiment ofthe circuitry included in a memory module ofthe present invention. The termination module 125 has clamping capacitors 138 and an inductor 136 arranged in the module such that they are connected to each communication line ofthe bus. Figure 13 provides a resistor 140 arranged in the module such that they are connected to each commvmication line ofthe bus. The termination circuit 125 of Figure 14 uses one diode 142 to terminate each communication line ofthe bus. It will be appreciated by those skilled in the art that the circuitry of Figures 9-14 can be connected to any bias voltage and not limited to a ground potential as illustrated. Further, although the termination module is preferably installed in the memory socket 1 12(n) farthest from the interface with the microprocessor 106, multiple termination modules could be used in any number memory sockets 1 12. In addition, memory socket 1 12(n) could remain empty and a termination module placed in a different socket. Conclusion A memory bus termination module has been described which can be placed in the last socket of a computer memory expansion bus. The memory bus can be filled with additional memory circuits, including burst memories. When all sockets are full, the termination module can be removed and replaced with an additional memory circuit. The memory termination module, thereby, reduces overshoot and undershoot which can create errors in communicated data over a mismatched memory bus.

Claims: What is claimed is: 1. A memory bus termination module comprising: a module housing adapted to fit into a memory socket of a memory bus, the module housing including communication line input and output connections; and termination circuitry connected to the communication line input and output connections. 2. The memory bus termination module of claim 1 wherein: the module housing fits into a socket designed to receive a JEDEC standard circuit package. 3. The memory bus termination module of claim 1 wherein the termination circuitry comprises a clamping diode connected to the communication line input and output connections. 4. The memory bus termination module of claim 1 wherein the termination circuitry comprises a plurality of clamping diodes connected to the communication line input and output connections. 5. The memory bus termination module of claim 1 wherein the termination circuitry comprises a capacitor connected to the communication line input and output connections. 6. The memory bus termination module of claim 1 wherein the termination circuitry comprises a capacitor and a resistor connected in series with the communication line input and output connections. 7. The memory bus termination module of claim 1 wherein the termination circuitry comprises a capacitor and an inductor connected in series with the communication line input and output connections. 8. The memory bus termination module of claim 1 wherein the termination circuitry comprises a resistor connected to the communication line input and output connections. 9. The memory bus termination module of claim 1 wherein the module housing is designed as a single in-line memory module (SIMM). 10. A memory bus comprising: a plurality of memory circuit expansion sockets; at least one high data rate memory located in one ofthe memory circuit expansion sockets; and a termination module housing located in one ofthe memory circuit expansion sockets and including communication line input and output connections, and termination circuitry having a plurality of clamping diodes connected to the communication line input and output connections. 1 1. The memory bus of claim 6 wherein the high data rate memory has a minimum data rate of 66 MHz. 12. The memory bus of claim 6 wherein the high data rate memory is a synchronous memory circuit. 13. The memory bus of claim 6 wherein the termination module housing is designed as a single in-line memory module (SIMM).

Inventors: WALTHER TERRY R, WALTHER, TERRY, R.
Applicants: MICRON TECHNOLOGY INC, MICRON TECHNOLOGY, INC.
Application year: 1996
Main classification: G06F13
IPC codes: G06F3, G06F12, G06F13