METHOD AND APPARATUS FOR ELECTRONIC POWER CONTROL

Abstract: The method and apparatus of the invention involve electronic power control by varying the amplitude of an electrical power supply voltage or current. A power controller is disclosed for controlling an AC input voltage to a load, the input voltage having one or more phases. The controller circuit has four independently controllable switches (Q1, Q2, Q3, Q4) and at least one inductor (L1), one such circuit for each input line to be regulated, the switches and inductor(s) of the circuit arranged in a conventional power regulator topology, whereby a selected regulator topology may be implemented, depending upon the position of the inductor(s) with respect to the input voltage. The controller has logic control with a two output polarity detector (160) in parallel with the input voltage, and a duty cycle modulator with two outputs; each of the outputs of the polarity detector and of duty modulator being inverted with respect to one another. Each switch is separately controlled and modulated by the logic control so that some combination of one or more of the switches is always electrically conducting.

Description: Title: METHOD AND APPARATUS FOR ELECTRONIC POWER CONTROL TECHNICAL FIELD The invention relates to the field of electrical power conversion and control, across a wide range of current and voltages; more particularly, it relates to method and apparatus for electronically implemented power control, more particularly, those implemented with switch mode power conversion techniques. BACKGROUND OF THE INVENTION An electrical power conversion circuit is a circuit in which electrical power is changed so that a power source with a voltage or current can serve a load requiring a different voltage or current. In switch mode conversion circuits and power conversion techniques, power is typically changed from a supply that is higher in current or voltage to serve a load requiring lower current or voltage, or from a supply that is lower in voltage or current to a load requiiing higher voltage or current. Where high conversion efficiency is made possible by design of the circuit, power output is substantially equal to power input. Where voltage - ampere products (VA) are close to the same at both output and input, and assuming a fixed VA at the input, a reduction in voltage at a resistive load is necessarily accompanied by an increase in load current, and vice-versa. There are three basic topologies of switch mode power converters. They include step-down (buck - see Figure 1), step-up (boost), inverting (including flyback) converters, and "duals" of these three. A "dual" version of any of the three basic class devices can sometimes be effected by a simple transform as follows: series inductors become parallel capacitors; and parallel capacitors becomes series inductors. Other transforms can be more involved, and the above transforms are provided as illustrative only, as will be appreciated by those skilled in the art. Dual topologies are known to have the following characteristics: a) discontinuous currents to and from the voltage sources become continuous currents to and from voltage sources; b) the DC transfer function (output voltage vs. input voltage vs. duty cycle) remains the same; and c) the dual input and output inductors can be combined together in one magnetic structure. In all such topologies, at least with respect to DC functionality, each converter typically consists of two switches, an inductor, and input and output filters. Nearly all conventional converters are some derivation or combination of these topologies and their duals. Output voltage regulation in these known converter topologies then is achieved by varying the duty cycle ofthe switches. Figure 1 shows a simple buck converter with ideal switches. In DC conversion circuits of the type generally known as buck or boost regulators, the two solid state switches typically employed are reciprocally and cyclically operated so that one switch is "on" or conducting, while the other is "off or non¬ conducting, and vice-versa. Thus as the duty cycle ofthe modulation of the two switches is varied, so is the voltage (or current) conversion ratio varied between source and load. For example, in a buck topology, if Si is modulated at a given duty cycle D and S2 is modulated exactly opposite Si (S2 closed when Si is open and vice versa) then output voltage is given by the formula: V " out = V v w * D 1J - Other known formulae similarly apply to other respective known regulator classes, as will be appreciated by those skilled in the art. This relationship holds for either polarity of V m . Theoretically then, alternating voltage on the input would manifest itself on the output according to the same relationship, assuming the use of "ideal" switches. However, as a matter of practice, in the absence of such ideal switches, conventional single stage converter implementations do not function in AC to AC conversions. In conversion circuits used to drive reactive loads such as induction motors, bi¬ directional energy flows and other four quadrant operation must also be accommodated. Simple power transformers are in common usage, though necessarily restricted to AC power conversion; however, they grow heavy and bulky as power levels increase, and they are by nature not readily variable in their conversion ratios without some kind of tap changing modification. There has been substantial work done in the area of AC converters, but known methods suffer for one or more reasons. For instance, some employ simplistic control schemes that lead to a variety of failure modes in the switches. In all real world switches, there exist timing delays and finite rise/fall times, both of which vary from device to device and over varying operating conditions. If care is not taken in a conventional two switch converter as outlined above, both switches could conduct simultaneously, with attendant high currents and excessive power dissipation which can destroy the switches. Power transistors of some of the types commonly employed as switches in converter topologies (and other semiconductors similarly employed) are known to store significant amounts of charge, and if a control voltage is applied to turn one transistor off as the control voltage is being applied to turn the other transistor on, the flow of current in the first transistor would continue for sometime after the turn off control, and simultaneous conduction in both transistors would occur to cause a short across the power source, with potentially damaging current flow through the switches. A simultaneous "off condition for both transistors is also a problem, for if the first transistor is turned off before the second transistor is turned on- the series inductor in such regulating circuits (in series with the opening switch) would discharge, or force current, through the opening switch and subject the switch to potentially damaging voltage. One known technique for dealing with the first phenomenon is the addition of a switohing delay, or dead time, into the turn-on of each switch, after turn-off of the other switch. Generally, a value for the length ofthe switching delay is chosen to insure that one switch is completely off before the other is enabled. But in the AC circuit supposed above, that then results in both switches being disabled at the same time. And as discussed above, if any current is flowing in the output inductor Ll, then the result of both switches simultaneously disabled is a voltage spike across the switches which will likely destroy them. This spike typically has to be clamped via some snubber or clamping network, but that then results in excessive clamp power dissipation and excessive switching losses in the switches. For an example of a manifestation of this problem, and an example of this limi ing solution, see US Patent 4,947,311 to Peterson, the disclosure of which is hereby incorporated by this reference into this disclosure as background as if fully set forth. Another approach to the problems described above has been through the use of resonant switching circuits that employ zero voltage or current switching techniques. These are sometimes referred to as "soft switching", or zero voltage switched, techniques. Converters employing these techniques do tend to be more efficient in theory than the "hard" switching circuits using snubbers mentioned above, but some topologies have proven difficult to control, where the resonant circuit becomes increasingly unstable at lower power ranges. In addition, such resonant circuits also have more narrowly defined operating conditions (i.e., minimum and maximum current limitations), and are therefore less robust for industrial appUcations, and these circuits typically trade switch losses for increased conduction losses, and require bulky resonant componentry. Switching losses into an inductive load, as encountered in conventional circuits, are generally proportional to the product of turnoff time, peak current, peak voltage, and switching frequency, and can be calculated from the well known formula: P iW = 0.5 t ofr * V p ..]- * I p .^ * Frequency where P iW is the switching loss expressed in units of power. In a snubbed or clamped circuit, there is always a voltage rise across the snubber during dead time as long as either current or voltage is non-zero. As a result, there is always a significant switch or snubber dissipation. In addition, during high current surge conditions, the snubber may not be able to adequately limit the voltage rise, leading to potentially catastrophic device failure. These known circuits therefore have significant limits in capability of conversion, at least in terms of output power, efficiency, reliability and cost. This is especially the case with present high power semiconductor technology where higher power and lower cost devices are also generally the slowest, and therefore have inherent and unacceptably high switching losses. Recently, a variety of other topologies have been suggested for direct AC/AC converters (also sometimes simply referred to as electronic transformers). These suggested topologies have generally fallen into two types: "zero voltage switched" (ZVS) a.k.a. "soft switched"; and traditional switchmode topologies, a.k.a. "hard switched". In those topologies suggested for use in hard switched converters, it appears that the power switches are implemented either as two bidirectional switches or as four unidirectional switches. A control scheme for a two switch converter referred to above is typically some form of simple modulation (such as pulse width modulation or PWM), which schemes make use of dead times, or delays, as discussed above. Where these suggested topologies are implemented with four switches, it appears the corresponding suggested control schemes diverge from one another. Venturini describes a scheme for switch control as a "staggered commutation", while Lipo discusses a siinilar method. In both of these descriptions, all four switches are required to be controlled at high speed, with both critical timing (including dead times) and level shifting required from a common controller. Cho briefly describes a different scheme which modulates two switches at high speed, but does not define any required dead times or transitions (if any are needed). Villaca employs two bidirectional, zero voltage switching (ZVS) switches operating from a simple pulse width modulator. These suggested control schemes have a number of points in common: 1) they all have multiple switches operating simultaneously at high frequencies; 2) the timing between these switches is highly critical, in order to avoid cross conduction or voltage spikes from the output inductor; 3) maximum duty cycle may have to be limited to accommodate what may be required as fixed timing delays, and circuit response time to output overload can be consequently dangerously delayed; 4) they all apply high frequencies voltage waveforms to the output inductor, which frequencies are essentially the same from no load to full load, which results in a fixed core loss in the inductor with attendant significant power loss even at light load or no load operation, thus reducing conversion efficiency at light load with attendant increased electricity costs; 5) by employing an unchanging high frequency waveform, the switching frequency AC current component in the output inductor is also similar from no load to full load condition, so that at light load significant current is left circulating through power components like transistors, diodes, and filter capacitors, all with attendant significant power loss and reduced light load conversion efficiency and increased electricity costs; 6) they all modulate multiple switches at high frequencies, which leads to high average current requirements for control circuitry, especially with large semiconductor power devices like IGBTs MOSFETs, BJTs and MCTs. In another vein, three phase power has been the mainstay of electrical power distribution for nearly a century, with three wire (also known as "delta") distribution being common for most situations. Various methods are currently employed to regulate three phase power, including tap selection, magnetic synthesizers, ferroresonant transformers, inverters and the like. A circuit has been described by Mozdzer and Bose that is different from those listed above. Other known uses for power controllers are so called static VAR compensators, which effectively add or subtract inductance or capacitance from a system, and also adaptive VAR compensators and "dynamic voltage restorers". These known devices have shortcomings in delivering a variable capacitance or variable inductance to a system, as has been reported in the literature. AC power quality is best and electrical operating efficiency is greatest when the line current is sinusoidal in wave form and in phase with the line voltage. It is well known however that electrical elements such as reactive loads shift the fine current in the mains out of phase with the Une voltage. This phase shift is commonly defined in terms of "power factor", or more specifically, "displacement power factor", where displacement power factor (referred to hereafter for sake of simpUcity as PF or as power factor) is given by the well known relationship: PF = cos θ where θ ' is the degree of phase shift "lead" (or "lag", as the case might be), also known as the phase angle, between the fundamental voltage and current. A perfect, or in- phase, relationship is equated to 1.0, while increasing degrees of phase shift are represented by power factors decreasing below unity. Power factor is also sometimes defined as the ratio of "true" power (in watts) to apparent power (in volt-amperes, or VA). Power factor is therefore a measure of relative efficiency of power transfer and energy usage, and becomes more critical with the use of heavy draw machinery and the like, such as motors. Typical induction motor power factors can range from very low at no load to around 0.85 to 0.90 ("perfect" is 1.00) at full load. Electric utility services typically add surcharges to customers with power factors below .90. In addition, power factor can be highly variable, depending as it does on the instantaneous total load on the power supply. Power factor correction ("PFC") then is therefore routinely appUed to compensate for bad power factor situations and, through better utilization of the existing power distribution system, to reduce the need for capital intensive additions to the power grid. Power factor correction is conventionally accomplished generaUy by having a series of capacitors across the line, and incrementally switching the various capacitors in and out with thyristors or relays. Other conventional PFC techniques consist of a bridge of transistors that operate with a storage bank of capacitors or batteries (for example, see Wilkerson US Patent 5,283,726). A major disadvantage of this conventional PFC technique is that the output switches always switch to and from the DC storage bank voltage, which is above the peak power Une voltage. As a result, switching losses are quite high. Known automatic power factor correctors are bulky, slow and complex, and therefore only practical for large motors and groups of smaUer motors. Even then, it is only the "system average" PF that is corrected, and studies show that it is preferable to correct PF at the load, rather than at the system level. For the above reasons, and other as will be appreciated by those skilled in the art, it is not practical to connect conventional PFC equipment at each load (motor). This is significant in that 60% of the electrical energy produced at this time is consumed by electric motors of 5 HP or greater in size (fully 80% of industrial consumption of electricity is for motors). And this at a time when annual electricity production is valued in excess of $52 billion! Any significant reduction in electrical consumption by these motors and/or increase in their efficiency of consumption would result in huge dollar savings. In addition, other elements such as rectifying power suppUes and SCR'β, and other non-linear sources such as computers, switchmode power suppUes, welders, inverters, controlled bridge rectifiers, fluorescent Ughts and other Ughts requiring a ballast, actually alter the sinusoidal waveform of the AC Une current. These non- linear devices typically only draw current when the voltage is at its peak, thus causing the harmonic distortion. This is not how the power grid was designed to work. The resulting non-sinusoidal current produced by these nonlinear loads can be mathematically resolved into a "fundamental" sine wave current at line frequency, with a number of harmonic waves at multiples of Une frequency, with the fundamental producing the power in the load, while the so called "harmonics" only increase heat losses and decrease the system's power factor (that is, they generally lower the efficiency of the distribution system) with no net contribution to power in the load. EPRI (Electrical Power Research Institute) estimates predict that by the year 2010, 60% of aU electrical loads will be such nonlinear, solid state electronic loads, so that the majority of aU future electrical loads will consist of unwanted harmonic generators. This is already even true for conventional PFC techniques that, in addition to other noted disadvantages, also react themselves to exacerbate harmonic problems, amplify circuit resonances, and even cause "ringing" on the mains when capacitors are switched. This ringing can cause malfunctioning and shutdowns in adjustable speed motor drives and other electronic equipment. As discussed above, each non-linear device produces its own distorted waveform composed of varying harmonic components. Each device aUows current to pass during a portion of the voltage sine wave and blocks the flow of current during another portion ofthe sine wave. To make matters worse, phase controlled devices such as adjustable speed drives (SCR) generate harmonic currents with ampUtudes varying as a function of load change. In addition, the continued trend in government regulation appears to be towards increasing energy efficiency, and is eventually expected to mandate harmonic cleanup at the source. AU of this suggests that power quality (PQ) issues are a major concern, and that there is a clear need for PFC and PQ techniques that more efficiently use power without also generating harmonic distortion themselves. It has been suggested that the variety of power quaUty problems, now extant and steadily growing in magnitude and variety, are all actuaUy summed within a power distribution system, producing effects such as: deterioration of electronic equipment performance, and continuous or sporadic computer and other microprocessor malfunctions; tripping protection circuitry of adjustable speed drives; overheating of neutral in three phase systems, leading to neutral burnout; overheating and premature failure of transformers, even when the transformer rating appears otherwise adequate; overheating of motors; nuisance tripping of circuit breakers; telephone interference; and PFC capacitor fuse blowing. In addition, the need for improved power regulation and/or power conversion is felt in other industries as weU. For instance, in the motion picture and entertainment industries, conventional light source dimming technologies produce an audible 60 Hz hum in large studio lamps. The conventional technology generally appUed is dunming by means of phase angle fired triacs, which limit the energy to the lamps by basically opening the circuit to the lamps for a given percentage of every half cycle (see example of resultant broken waveform in Figure 2). This scheme is relatively simple to implement, but is electrically very noisy, which leads to additional design problems and additional implementation costs. A means of smoothly and quietly dimming such lamps would be of great use. DISCLOSURE OF THE INVENTION Accordingly, it is an object of the invention to provide a power controUer that is low in electrical and audible noise, applicable to both low and high power appUcations, having high tolerance for inductive loads, Ught in weight, digitally controUable, and fast in response time. It is a further object ofthe invention to provide a power converter having output power, efficiency, reUability and cost superior to known topologies. It is another object of the invention to provide a power converter with reduced total switching losses. It is another object ofthe invention to provide a power converter that during high current surge conditions and reactive currents is not subject to switch device failure due to voltage rise. It is a further object of the invention to provide a power converter adapted for four quadrant operation and bi-directional power flow, with respect to input and output voltage and current. It is another object of the invention to provide a converter/controUer topology that addresses the disadvantages of conventional active PFC techniques. It is another object of the invention to provide a controller topology that can be used as a continuously variable capacitive load. It is another object ofthe invention to provide a controUer topology that can be used as a continuously variable inductive load. It is another object ofthe invention to provide a controUer topology that can be used as a continuously variable resistive load. It is another object of the invention to provide a relatively inexpensive, fast response, self-dampening power factor corrector of size and bulk sufficiently smaU to be practical for the majority of motors in current and future use, and which does not contribute to line harmonic problems or problems of system resonance and ringing caused by capacitor switching. It is another object of the invention to provide a power controUer for assuring best power quaUty and greatest electrical operating efficiency by controlling an AC source to provide current and/or voltage outputs that are sinusoidal in waveform and in phase with each other. It is another object ofthe invention to provide a power controller for neutralizing Une harmonics. It is another object ofthe invention to provide a power controUer for successfuUy addressing any one or more of the foUowing power quaUty concerns: deterioration of electronic equipment performance, and continuous or sporadic computer and other microprocessor malfunctions; overheating and premature failure of transformers, even when the transformer rating appears otherwise adequate; overheating of motors; nuisance tripping of circuit breakers; telephone interference; and PFC capacitor fuse blowing. It is another object ofthe invention to provide voltage regulation or a power line conditioner to mitigate voltage swells and sags, and overvoltage and under voltage conditions. It is another object of the invention to provide a means of power regulation (voltage and/or current) that has the characteristic of being low impedance source with respect to a load. It is another object ofthe invention to provide a means of controlling power on single or multiphase distribution systems, including the majority of known power system frequencies, such as 50, 60 and 400 Hz. It is another object of the invention to provide a means of controUing a power converter which aUows for nearly instantaneous regulation, among the benefits of which is that the device is non self destructive in overcurrent situations. It is a further object of the invention to provide a means of dimming lamps in such a way as to produce no audible hum. It is yet another object of the invention to provide a system meeting any one or a combination of aU ofthe needs summarized above. These and such other objects of the invention as will become evident from the disclosure below are met by the invention disclosed herein. The invention addresses and provides such a system. The invention represents means to quickly, precisely, and remotely convert AC power with losses that are lower than conventionally available technology can provide. It also represents a compact, efficient, and low cost device for processing AC power, and that is simple and reUable and low in harmonic distortion; applicable to both low and high power appUcations, having high tolerance for reactive and bi-directional loads, Ught in weight, digitaUy controllable, and fast in response time. Application of the invention to solutions to power quality problems, especiaUy solutions requiring variable ampUfication, is especially beneficial in that the invention is the only system that effectively provides fuU four quadrant operation in a single stage AC to AC power conversion device, particularly with respect to reactive loads, and which utilizes four independently controllable switches. The invention provides an electrical power controUer (also sometimes referred to herein as a regulator or converter) apparatus or device for controlling or regulating an AC voltage or current to a load. The voltage may be in single or multiple phase (such as conventional three phase) configurations. The controller device has four independently controUable switches and at least one inductor for each input Une (or phase) to be regulated, aU in one of several otherwise conventional power regulator topologies, such as buck, boost, inverted or isolated converter/regulators or duals of these topologies. A corresponding regulation or conversion scheme may thus be implemented depending upon the position of the inductor with respect to the switches and the input voltage, as will be appreciated by those skUled in the art. The controUer also has a logic control block. The logic control block is comprised in part of a polarity detector preferably in paraUel with the input voltage. The polarity detector preferably has two outputs, each of which is the reciprocal of the other (inverted with respect to each other), although this may be accompUshed in a number of functionaUy equivalent ways, such as through use of one or more inverters, as wiU be appreciated by those skilled in the art. The logic control unit also has a duty cycle modulator with two reciprocal outputs. Each switch is then separately modulated by these detector and modulator outputs under logical control so that some combination of one or more switches is always electrically conducting, or "closed". In other words, so there is never a combination of aU four switches that is open, except of course when the device is not in operation (turned off or out ofthe circuit). Each switch thus turns off only into the instantaneous Une voltage (ILV), rather than switchmg to a storage bank voltage or DC rail. Since the ILV can be as low as zero, losses are thereby reduced to the extent the ILV is lower than a storage bank voltage or that of a DC rail TypicaUy, this can save 36% or more in switching losses alone, even for resistive loads (with greater savings possible for reactive loads). A variation of this device has 4 OR gates fed by outputs from the polarity detector and the duty cycle modulator through turn off and turn on delays, respectively, such that first and third OR gates each receive as a first input a first output from the polarity detector, and second and fourth OR gates each receive as a first input a second output from the polarity detector; and such that first and second OR gates receive as a 2nd input a first output from the duty cycle modulator, and third and fourth OR gates receive as a 2nd input a second output from the duty cycle modulator. The output from each OR gate controls or modulates or drives one switch or gate each. Preferably, the switch sources of each pair of switches are tied together, but do not have to be in some alternate embodiments. In preferred embodiments ofthe controUer device, at least one of, and preferably aU of, the switches are electronicaUy controllable, though alternate, non-electrical, implementations may occur to those skiUed in the art, including partially or fully manual control schemes, and control schemes involving conducted Ught optics, such as fiber optical control means. Preferably each switch is a solid state switching device, with a diode poled to have a sense opposite to the switch, in parallel across the source and drain of the switch, and the diodes of a pair of such switches are opposite in sense to each other. The switches are preferably transistors, such as B T (bipolar junction transistors), IGBT, or MOSFET transistors, or even thyristors such as MCT or GTO. One embodiment of the controUer device has two switches in series with each other, though preferably poled in the opposite sense from each other, and connected with the inductor to one input, and two switches in series with each other, also preferably poled in the opposite sense from each other, and connected with the inductor to the return. In other words, wherein a first pair of switches is connected between the input and the inductor, and a second pair of switches is connected between the inductor and return. As employed in this disclosure, the term "poled in the opposite sense" when referring to electronic devices that resist or obstruct the flow of current in one direction (usuaUy under a set of defined conditions), but not in the other, means they are placed so that current flow is not blocked in the same direction in both devices; in other words, their "poles" are oppositely arranged, as will be appreciated by those skilled in the art. In another aspect ofthe invention, there is separately provided a logic controUer for controlling the duty cycle of a power controUer. The logic controUer is particularly adapted for controlling a power controUer device that has four independently controUed separate switches. The logic controUer has a polarity detector in paraUel with the input voltage that has two outputs, and it has a duty cycle modulator that also has two outputs. Each ofthe outputs ofthe polarity detector and ofthe duty cycle modulator are inverted with respect to one another (reciprocal). The controUer is employed in such a way that each ofthe four switches to be controUed is separately modulated so that some combination of one or more switches is always closed. Turn off or turn on delays may optionaUy be employed. Preferred embodiments of the controller device employ four OR gates fed by outputs from the polarity detector and the duty cycle modulator through optional turn off and turn on delays, respectively, such that first and third OR gates each receive as a first input a first output from the polarity detector, and second and fourth OR gates each receive as a first input a second output from the polarity detector; and such that first and second OR gates receive as a second input a first output from the duty cycle modulator, and third and fourth OR gates receive as a second input a second output from the duty cycle modulator. Output from each OR gate modulates or drives one switch or gate each. In another aspect ofthe invention, a controUer chooses its quadrant modes based upon input voltage and error circuit output. A positive input voltage determines that either Quadrant I or Quadrant II wiU be employed, while a negative input voltage determines that either Quadrant III or Quadrant IV will be employed. The selection of Quadrant I vs. Quadrant II or Quadrant III vs. Quadrant IV is dependent upon the error circuitry. The error circuitry compares output voltage to the reference and determines both the required direction of current flow and the required amount of modulation by way of the error ampUtude output to maintain controUer output regulation Current can be in either direction for any particular Quadrant or transition without damaging the controUer. This AC electronic power controller is implemented in three parts: 1) a voltage polarity detector senses the polarity of the input voltage and feeds the signal into the Control Logic section; 2) a control input signal is fed into a modulator section (such as a PWM) which converts the input signal into a modulated digital pulse train, which is in turn fed into the Control Logic section (this control input may be fixed, varied and/or sourced by either an external, source or error amplifier or corrector of a such types as will be known to those skilled in the art); 3) the Control Logic then takes the polarity and control input signals and implements the control scheme tabularly summarized in Table 2. In preferred embodiments, step 2) above is further particularized in that a control input is fed to a programmable reference which in turn produces a variable sine wave reference output (in phase with the input voltage) that is fed into an error correction circuit which compares the reference output to the converter output and provides a resulting signal to the modulator. The logic scheme may be implemented by any of a number of methods as will be appreciated by those skilled in the art, including microcontroller, PAL, or discrete logic. Output from the Control Logic section is then fed into the level shift circuits, which in turn interface the power switches. This preferred control scheme has a number of advantages over known and suggested control schemes when appUed to the power controUer ofthe invention. 1. Since no more than one switch is in operation at high frequency in any given mode, critical tuning between or among the various switches in controUers using other schemes is eliminated. 2. There is no need for any kind of delay or dead time to be implemented during high frequency switching operation, resulting in greater maximum duty cycle and/or smoother operation from 0% to 100% duty cycle. In addition, overload shutdown response is immediate (or at least substantially reduced), with no delays to step through before shutting down. 3. The power controUer may be operated discontinuously during no load and Ught load conditions, resulting in reduced duty cycle for these conditions, with beneficiaUy reduced core loss in the output filter inductor. Light load efficiency is significantly improved, with decreased electricity costs. 4. This same discontinuous operation capabiUty also reduces the high frequency current component in the output filter inductor, in turn reducing the amount of recirculating current switched and conducted by the switches and diodes ofthe converter during Ught load operation, thus further reducing power loss and further enhancing Ught load efficiency. 5. Since no more than one switch is modulated at any given time, average total switch drive power is greatly reduced. The invention also provides a variable inductor, a variable resistor and a variable capacitor. The variable capacitor of the invention can be made non-resonating, and implementation of these devices appear as linear loads and therefore do not degrade the power factor of the system in which they are employed (i.e., they are "transparent"). The variable capacitor is appUcable to an automatic PFC system. These devices are novel with respect to known static VAR compensators, adaptive VAR compensators and dynamic voltage restorers, and implemented as a combination ofthe power controUer of invention and a capacitor connected across an output and a return ofthe controUer whereby the combination functions as a variable capacitor. The power controUer of the invention may also be combined with an inductor connected across an output and a return ofthe controUer whereby the combination of controUer and inductor functions as a variable inductor. The invention also provides several method aspects. In one embodiment, a low impedance method of power regulation or conversion is provided whereby an amplitude of an input voltage waveform is varied linearly, without respect to its frequency, with or without changing its characteristic waveform, to produce a proportional output voltage to a load, employing only a single stage conversion (i.e., no intermediate DC voltage or current link). In a variation of this method, the above referred to voltage ampUtude variation is accomplished by variable duty cycle modulation switching of an input voltage through an inductor in a manner otherwise consistent with conventional power regulation topology. A preferred method for accomplishing the variable duty cycle modulation follows these steps: 1) sensing in real time a polarity of the input voltage to derive a pair of polarity signals that are inverted with respect to each other; 2) varying the duty cycle of a modulator, in accordance with and in proportion to the desired modification ofthe ampUtude, the modulator having two outputs inverted with respect to each other; 3) feeding a polarity signal and a modulator output signal to an OR gate, where each signal has a duration, and the beginning of the duration of the duty cycle modulating output signal is delayed, and the end of the duration of the polarity signal is also delayed; 4) using the OR gate logical output to control a switching device for the variable duty cycle modulation of the input voltage. These method steps 1 - 4 are then preferably iterated separately for each of four OR gates, and the step of variable duty cycle modulation switching ofthe input voltage includes the step of modulating the switching during operation so that aU ofthe switches in the controUer of the invention are not ever electricaUy non-conducting (or "open") at the same time (except when there is no power applied to the circuit). Another aspect of the invention is a variable po e factor corrector that has a capacitor in paraUel with the load to be corrected on an AC Une, and a Une driven variable voltage output in series with the capacitor for varying the voltage to the capacitor, so as to vary the amount of capacitance reflected through the power controUer onto the AC Une. In corresponding manner, a line driven variable voltage output is employed in conjunction with other appropriate components to create variable resistors, tuned LC circuits, and variable inductors. Preferred embodiments ofthe power factor corrector have the variable voltage output implemented in an electrical power controUer, regulator, or converter, for regulating an AC input voltage. Preferred embodiments of such a controUer have two pairs of switches, for a total of four switches, and an inductor, and the pairs of switches and the inductor are preferably in one of several conventional power regulator topologies such as buck, boost, or inverted (or some dual). The controUer also has a logic controUer as described above, so that each switch is separately modulated in such a way that some combination of one or more switches is always closed, or in other words so there is never a combination of aU four switches that is open. A preferred power factor corrector also has a current sensor in series with a load on the AC Une. Both line voltage and current sense signals are fed into a phase delay detector that determines the phase delay between the AC Une voltage and the load current. A power factor error amplifier is employed that is fed by an output of the phase delay detector, and the amplifier feeds a signal to the power controUer logic controUer, to automatically maintain a selected power factor correction on the line. The power factor corrector may also advantageously employ a current sensor in series between the power controUer and the load, and a harmonic error ampUfier fed by an output of the current sensor, so that the amplifier feeds a signal to the power controUer logic controller for auto resonance suppression, harmonic dampening and/or load current shaping. In a variation of the power factor corrector, a pluraUty of capacitors and a pluraUty of power controUers are employed for variable and automatic power factor correction in a multiphase AC system. In a three phase variation, a first power controUer is preferably in paraUel between a first AC Une and a third AC line, and a second power controUer in paraUel between a second AC line and a third AC Une. At the same time, a first capacitor is preferably connected between the output of the first power controUer and the third AC Une, a second capacitor is connected between the output of the second power controUer and the third AC line, and a third capacitor is connected between the output ofthe first power controUer and the output ofthe second power controUer. Another variation of the power factor corrector employs a first power controUer in paraUel between a second AC line and a third AC line, with the power controUer fed by a signal derived from a first AC line. A second power controUer is in paraUel between the first AC Une and the second AC line, with the power controUer fed by a signal derived from the third AC Une. A third power controller is in paraUel between the first AC Une and the third AC line, with the power controUer fed by a signal derived from the second AC Une. Another method aspect of the invention provides for power factor correction by reflecting or introducing a continuously variable capacitance onto a power Une to correct displacement power factor, where the capacitance is variable by means of a voltage from the power line varied by a power control methodology. This method preferably employs a power control methodology based on variable duty cycle modulation with the foUowing steps: 1) sensing in real time a polarity of the input voltage to derive a pair of polarity signals that are inverted with respect to each other; 2) varying the duty cycle of a modulator, in accordance with and in proportion to the desired modification of the ampUtude, the modulator having two outputs inverted with respect to each other; 3) feeding a polarity signal and a modulator output signal to an OR gate, where each signal has a duration, and the begi-αning of the duration of the duty cycle modulating output signal is delayed, and the end of the duration of the polarity signal is also delayed; 4) using the OR gate logical output for the variable duty cycle modulation ofthe input voltage. A variation of this method employs, before reflecting or introducing a variable capacitance onto a power Une, these additional steps: 1) sensing in real time an ampUtude of current on the power line; 2) detecting phase delay (such as by calculating phase delay of current relative to voltage) on the power line in conjunction with the current sense; 3) amplifying an output of the phase delay detection step; then 4) controlling a power factor correction power controller with the amplified output from step 3. Another variation of this method employs, before reflecting or introducing a variable capacitance onto a power line, these additional steps: 1) sensing in real time an amplitude of current on a line between the power controUer and the power factor correction capacitor; 2) amplifying an output of the current sense step; 3) controlling a power factor correction power controUer with the amplified output. The method of the invention in one aspect involves electronic power control by varying the ampUtude of an electrical power supply voltage, independent of frequency, whereby the output frequency will always be the same as the input frequency. An electrical circuit apparatus for accomplishing this function in a preferred embodiment is also disclosed herein. The preferred circuitry of this aspect of the invention uses four solid state switches, such as IGBTs, four diodes, an inductor, input and output filters and novel controlling circuitry. The controUer apparatus and methods ofthe invention may be used to implement aU otherwise conventional converter types, buck, boost, and inverting (and duals of these) versions to obtain different regulating characteristics, including galvanic isolation of the output from the input. The inventive methods and devices may be used in power factor correction, voltage and/or current harmonic filtering and neutralization, line and load conditioning, improving or changing impedance characteristics of electrical generators, control of power transfer between two power grids, and programmable control of surges, sags, dropouts and most other voltage or power regulation problems. In another aspect of the invention, a method of power factor correction is disclosed employing essentially the same control circuitry in a different appUcation. In essence, a method as disclosed above, preferably employing the control circuitry referred to above, is used to dynamicaUy control the voltage to (and therefore the reflected capacitance of) a single large capacitor (or several if one large enough is not avaUable) that is continuously adjustable with vastly fewer parts than previously thought possible, and all at correction speeds of under 1 second. The circuit can interface between the power Une and a PFC capacitor, and/or reactor. As the duty cycle D is varied, the reflected capacitance onto the power line is: Thus, the capacitor can be continuously controUed between 0 and its given value, and the corrective load presented to the power line can be continuously controlled between 0 and unity times the corrective load in direct connection to the Une. If the power factor, or the phase delay, is measured, and fed into an appropriate error amplifier, such as will occur to those skilled in the art, then the control circuitry wfll automatically correct power factor, even approaching unity, with response time on the order of 0.1 seconds. No other method uses reflected capacitance via a variably controlled voltage source to achieve PFC. The apparatus and method of the invention has no DC storage bank, unlike known converter and PFC correction devices, and only one device is actually conducting output current at any given moment. Furthermore, the turn off voltage varies with the instantaneous line voltage, and (for reactive loads) is at a maximum when output current is at a minimum. Thus, switching losses are dramatically lower than existing methods, and the power factor corrector disclosed has greater output capability and efficiency, and smaUer size than known PFC methods. The disclosed PFC method and apparatus can also be configured for three phase PFC for balanced loads by employing two units and three PFC capacitors. In another appUcation, since the invention can vary reactive loads and impedances, it may also be used as a whole or part of a tunable circuit for mitigation of power Une harmonic currents, with either manual or automatic tuning of the filter. Yet another extension ofthe invention includes a relatively last (several kUohertz or more) loop which is closed around either system (motor and PFC) current or device (invention) output (capacitor) current. The control circuitry can be made to reject and to some degree correct existing harmonic currents that arise from resonances in such systems. Power line harmonic currents are a widely recognized problem in electrical distribution systems. This has great advantage over the common PFC technique where several different capacitors are switched in and out with thyristors or relays. The apparatus of the invention is simpler, smaUer, cheaper, and more accurate, and more reliable. It also eliminates the system resonances associated with PFC capacitors. This circuit has the advantage that each switch turns off only into the instantaneous input voltage. The voltage is clamped to that value by an appropriate freewheeling diode, as will be appreciated by those skilled in the art. In a nominal 240 VAC system, average turn off voltage in the circuit of the invention is about 220V, compared to existing systems, such as those employing a DC rail, where a clamp value might be as much as 500V, causing more than double the switching loss over the device of the invention. Thus the invention reduces switching losses to less than half of that common in known circuits, and with no clamp dissipation at all. A circuit with a snubber would require a capacitor so large that the snubber dissipation alone would be several times the total switching loss of the inventive device. The device of the invention reduces total switching losses dramatically over known devices, and this is particularly true while driving reactive loads, where peak Une voltage and current are not in phase with each other. This phase separation normally leads to even higher losses in conventional devices. But since, as discussed above, switching loss is proportional to the product of frequency and voltage, this phase difference results in decreased switching losses in devices embodying the invention. Further advantages are that reduced peak voltage results in lower EMI RFI conducted to input and output; while reduced switching losses allow higher switching frequencies, saving size and weight in input and output filters. Another advantage is that any of several power device types may be successfully employed in the circuit, including bipolar, MOSFET, IGBT, GTO, and MCT devices. Topologies like those disclosed by others (Peterson, for example) are not so versatile. Because all four switches in devices embodying the invention are on briefly at zero crossing ofthe voltage waveform, the current can flow in either direction during that transition without initiating a high voltage spike on the switches during that period. The resulting circuit is quieter, smaller, more efficient, and more reUable than existing treatments. It can handle voltage and current in either direction for true four quadrant operation and true bi-directional energy flow, with the small premium in extra control circuitry more than offset by savings in switch cost, heat sink size and weight, and mechanical size. BRIEF DESCRIPTION OF THE DRAWINGS Figure / is a schematic of a known simple buck regulator. Figure 2. is a graphic representation of a voltage waveform output from a phase angle fired triac. Figure 3 is a graphic representation of an amplitude modulated sinusoidal voltage waveform output from devices embodying the invention. Figure is a schematic of one embodiment of the power controller of the invention. Figure 5 " is a block diagram and partial schematic of one embodiment of the power controller of the invention. Figure 6 is a set a - d of schematic and partial block diagrams of alternate embodiments ofthe power controUer of the invention. Figure 7 is a set a - d of block diagrams and partial schematics of alternate dual topologies. Figure β is a switch timing diagram for operation of the circuit of Figure 4. Figure ? is a block diagram and partial schematic of an alternate embodiment of the power controller of the invention. Figure 10 is a block diagram of an autovariable power factor corrector. Figure / / is a schematic and partial block diagram of a three phase power factor controller of the invention. Figure 12. is a schematic and partial block diagram of an alternate method of power factor correction with soft start current Umits. Figure /J is a schematic and partial block diagram of an adjustable capacitor of the invention. Figure IH is a schematic and partial block diagram of an adjustable inductor of the invention. Figure }ζ is a schematic and partial block diagram of an adjustable harmonic rejecter of the invention. Figure ]b is a schematic and partial block diagram of an adjustable resistor ofthe invention. Figure /7 is a schematic and partial block diagram of an AC power conditioner of the invention. Figure J8 is a schematic and partial block diagram of an isolated output AC power conditioner of the invention. Figure 1° is a schematic and partial block diagram of a high voltage input AC power conditioner of he invention. Figure 2σ is a schematic and partial block diagram of an AC hybrid power conditioner of the invention. Figure Z> is a schematic and partial block diagram of a hybrid isolated AC power conditioner of the invention. Figure 32. is a schematic and partial block diagram of an AC voltage regulator of the invention. Figure 3? is a schematic and partial block diagram of an isolated AC voltage regulator of the invention. Figure 2V is a schematic and partial block diagram of an adjustable parallel harmonic filter of the invention. Figure 2S~ is a schematic and partial block diagram of an adjustable series harmonic rejector of the invention. Figure 2έ is a set a - e of printouts of oscilloscope readings during a test on a prototype PF corrector ofthe invention. Figure 27 is a spreadsheet of comparative data on SCR performance vs. an invention prototype power controller. Figure 1β is a graph of relative efficiencies of conventional power control devices compared to the power controller of the invention. Figure 23 is a graph of relative harmonics and power factor (for resistive loads) of conventional power control devices compared to the power controller of the invention. Figure 30 is a block diagram of a preferred embodiment of a power controller of the invention. Figure 31 is a partial schematic and block diagram of a preferred three phase delta power conditioner of the invention. Figure 32 is an alternate block diagram of a preferred embodiment of a power controUer of the invention. Figure 33 is a partial schematic and block diagram of a preferred embodiment of a high voltage power controUer of the invention. Figure 34 is an alternate partial schematic and block diagram of a preferred embodiment of a high voltage power controUer ofthe invention. Figure 35 is a partial schematic and block diagram of a preferred three phase delta high voltage power conditioner of the invention. BEST MODE OF CARRYING OUT THE INVENTION Turning now to the drawings, the invention will be described in a preferred embodiment by reference to the numerals of the drawing figures wherein Uke numbers indicate like parts. Figure 1 is a conventional configuration of known buck regulator topology, included here as a point of reference. Convention buck regulator 10 has a first switch 11, a second switch 12, input filter capacitor 13, output filter capacitor 14, inductor 15, input 16, output 17, and return 18. Switches 11 and 12 alternately close and open (are modulated), so that in conjunction with inductor 15, in well known fashion, voltage at output 17 may be stepped down from the voltage at input 16 in proportion to the duty cycle modulation of the switches. Figure 2 is a graphic representation ofthe broken waveform output from a phase angle fired triac, to be compared with Figure 3 which is a graphic representation of an output voltage waveform having its ampUtude varied over time by the power controller of the invention, without interruption of the waveform or change to the frequency. Figure 2 is typical of phase controlled variable output voltage, in that step down of an instantaneous average voltage at output is achieved by cutting off a part of the waveform. This process results in many ofthe power regulation ills described elsewhere herein. Figure 4 shows an electrical circuit for use in a preferred embodiment of the controller (sometimes also referred to herein as a converter or power converter) apparatus ofthe invention. The preferred circuitry of this aspect of the invention uses four IGBT solid state switches, four diodes, an inductor, input and output filters and novel controUing circuitry. The control circuitry is generaUy laid out in functional blocks in accordance with Figure 5. The controller apparatus and methods of the invention may be used to implement all otherwise conventional converter types, including buck, boost, inverting, and flyback versions, as illustrated in Figure 6a-d, and duals of these topologies, as shown in Figure 7. A preferred circuit for controlling power to reactive, resistive, or non-linear loads in accordance with Figs. 5 or 4 would be comprised of at least four separately controlled unidirectional switches that are aU modulated differently according to the polarity of the Une voltage according to a logic "box" so that some combination of the four switches is always on, no matter what the polarity is, including the "zero cross" point of polarity change on the input voltage waveform. A preferred means of control in the "box" consists of a polarity detector, a modulator (preferably a pulse width modulator), and control logic. Those skilled in the art wiU appreciate that the modulator may use any of several known methods, including fixed and variable frequency, and voltage and current mode, and can be implemented in one or more in a variety of ways, including use of one or more microcontrollers. Any of a number of algorithms can be employed to provide constant, varying, or programmable output (in terms of RMS, average and peak voltage and/or current) to control the modulator. The modulator preferably provides a high frequency (>10 KHz) logic output of between 0% and 100% duty cycle. An additional output of opposite or reciprocal polarity is also preferably provided. During the "zero crossing" of the line voltage (i.e., when input voltage is in transition from one polarity to another), all switches are turned on simultaneously for a short period of time (it is contemplated that this will be on the order of a few microseconds in preferred embodiments) to allow continuous current to flow in the output, as may be necessary- Thus, current can flow in either direction during the zero crossing transition without initiating a high voltage spike on the switches at that time. During this time, the input and output ofthe circuit are effectively short circuited by the simultaneous conduction ofthe four switches. However, the transition is chosen to occur at a point where the instantaneous input voltage is low enough (near the "zero" crossing - i.e., in the range of +/- 4V, or less, depending on the power switches used) that Uttle or no current is drawn from the input source. Then each time the polarity has cycled, operation returns to that previously described. Thus there are four operational stages per line cycle: Positive polarity, polarity transition (zero cross), negative polarity, and polarity transition (zero cross). As the switches in preferred circuits are likely to operate at high and varying voltages, the control logic also includes level shifting as needed to interface with the switches. The power controUer. 100 of the invention can best be appreciated in detail through a description of its basic schematic building blocks, as illustrated in a preferred circuit embodiment in Figure 4. Input block 110 includes jumper JPl through which power is appUed to controUer 100. JP1-2 is connected to a power return bus (as is Une 2 of output connector JP2-2) and this bus is separate from chassis ground (JPl-3 and JP2-3). The common power return bus enables controUer 100 to be portrayed (at least for purposes of block diagram form, such as for example Figure 10) as a three terminal component. Input current limiting for catastrophic failure is provided by fuse F2. Input filter 120 includes capacitors C14 - C18, inductors L3 and L4, and resistor R10. This is a multistage filter which keeps high frequency switching noise out of the input Une, reducing conducted EMI/RFI, as will be appreciated by those skiUed in the art. R10 provides damping for the filter to reduce ringing. R26 is a bleeder resistor to remove stored charge from the input filter after power disconnection. Power stage 130a-b consists of switches Ql - Q4 and diodes Dl - D4. The switches are preferably implemented as IGBT type transistors, though they may also be any of several other types, as detaUed elsewhere herein. Each of the four IGBT switches Q 1 - Q4 is separately controUed, though they form in combination a unique arrangement that, in conjunction with control circuitry disclosed herein, provides four quadrant operation (see discussion infra) and low switching losses. In preferred embodiments, the four switches Ql - Q4 are paired, and each pair Q1-Q2 and Q3-Q4 have their sources tied together, and each of the switches in a pair are poled in the opposite sense to each other. Output overcurrent protection is accomplished on a cycle by cycle basis via current transformers Tl and T2. Current sense information is rectified by diodes D9 and D10, and fed into sense resistors R27 - R29 (block 130b), and then compared in the current Umit pin Ul-9 of modulator IC Ul (see infra). Switch Q6 and resistors R30 and R31 (block 130b) provide slope compensation to the current sense circuit in order to provide more stable operation under a variety of duty cycles. Diodes D5 • D8 are used to limit transformer Tl, T2 leakage reactance voltage spikes on switches Ql, Q2 during turn off. Output filter 140 provides output averaging and filtering through inductors LI, L2 and capacitors C12, C13. LI and C12 average the modulated power stage output into an instantaneous DC value (which varies over time, proportionate to input voltage and to duty cycle). L2 and C13 further filter out the high frequency switching waveform components from the output. Resistor Rll bleeds off charge from capacitors C12, C13 upon removal of input voltage. Output block 150 includes output connector (jumper) JP-2, having output high side JP2-1 and power return JP2-2 (which as disclosed above is common with JPl-2). Long term output overcurrent protection is provided by fuse Fl, while instantaneous limiting is provided for internaUy as previously discussed. Polarity detector 160 serves to detect line polarity via comparator U8A and its associated circuitry. Input voltage is sensed through resistor R25 and clamped via diode D15 and switch Q5 to keep the signal within the common mode input range of comparator U8A. U8A detects voltage and provides a smaU amount of hysteresis (about IV) to prevent spurious operation in a noisy environment. Some filtering is also provided via capacitors C27, C28 for the same purpose. Modulator 170 includes IC UI which provides for modulation in this embodiment of controUer 100, using pulse width modulation as its particular method. However, those skilled in the art will appreciate that a number of other conventional controllers and other modulation types may also be employed as desired. Modulator UI is an off-the-shelf part used as a modulator/regulator for conventional switching power suppUes, and its operation here is Ukewise conventional. Timing components R 1, R33, and C30 are used to set operating frequency in the 20KHz to 40KHz range. Duty cycle is varied via resistor R32, which is connected to the soft start pin Ul-8. There is no regulation loop shown in this particular circuit embodiment, although output voltage and current may be regulated in a variety of ways, including average, instantaneous, RMS, harmonic reduction and/or neutralization, power factor correction, and the like, all as discussed elsewhere herein. Modulator output is taken from Ul-11 (normal) and Ul-14 (inverted). Level shifting may be accompUshed by means of a variety of conventional methods involving transformers, optocouplers, and the Uke. In the preferred circuit shown in Figure 4, the task is accomplished with a readily available integrated circuit (IC). This IC provides an optocoupler and high current driver for interfacing with the gate of a MOSFET or IGBT device. Electrical power at the gate is provided via an isolated transformer winding with rectifier and filter, although a number of equivalent methods may be alternately employed by those skilled in the art. Level shifting block 180 receives output signals from the logic circuitry (q.v., infra), which are then shifted in voltage level to drive switches Ql - Q4 via ICs U2 - U5, respectively. U2 - U5 are stock components that include an optocoupler input and high current MOSFET driver output. They operate from smaU power suppUes VH and VL which are 15VDC floating power sources, the conventional derivation of which wiU readily occur to those skiUed in the art. In this case, smaU linear power suppUes are used but are not shown in the schematic for sake of clarity. Each transistor gate has a series resistor (Rl - R4) to limit ringing and to control rise and faU times during switching transitions. Each transistor also has a bleeder resistor from gate to source to insure that aU devices are in the non-conducting or "off' state in the event that VH or VL are bst. Current into each optocoupler input is limited by a 1.2 IK resistor (R12 - R15) to about 7mA per the TC4804 specification, with a smaU capacitor (C19 - C22) in paraUel to speed up the response time. Control logic block 190 includes IC devices U7A, U7B and U6A-D. Operation of control logic block 190 may best be understood from discussion of its three basic modes of operation. In aU modes, control logic 190 takes three input signal types (normal modulated output • from Ul-11, inverted modulated output • from Ul-14, and polarity detect - from U8A-1) and translates them into four individual transistor drive outputs, which in turn control Ql • Q4. It is thus useful to discuss the invention in terms of three modes, corresponding as they do to the three types of input signals received by the control logic unit. This does not negate however the earUer discussion based on four operational stages, corresponding to the four parts of a voltage waveform as it moves in time. For each of the three basic operating modes there are two conditions (discussion of which also sets forth the essence of the full four quadrant operation of the apparatus and method ofthe invention). First mode is positive polarity of input voltage. During positive input polarity, U8A wiU be low, holding inverters U7B (output) high and U7A (output) low. With U7B high, both OR gates U6B and U6D will be high, turning on Q2 via U3 and Q4 via U5. With U7A low, U6A is controUed by the modulator output from Ul-11. A turn on delay (rising edge) is provided by R18 and C23. Turn off is not delayed because diode D14 bypasses R18 on the falling edge. U6A in turn controls Ql via U2. At the same time, U7A low aUows U6C to be controUed by the inverted modulator output Ul-14. It contains a simUar turn on delay circuit comprised of R19, C24 and D13. Both delay times are the same and are sufficient to prevent Ql and Q3 from conducting simultaneously during operation. U6C controls Q3 via U4. The two conditions of operation for positive polarity are 1) positive output current, and 2) negative output current. During positive output current, Ll current is sourced through Ql and D2 during the Ql "on" (conducting) state. When Ql is turned off, Ll current freewheels through Q4 and D3. Q3 is turned on (after delay) during the time that Ql is off, but no current flows through it due to its polarity; the current passes through D3 instead. During negative output current, Ll current is controUed by Q3, passing through Q3 and D4. When Q3 is turned off, Ll current freewheels through Q2 and Dl back to the input. Ql is turned on during that time, but no current flows through it due to its polarity; current passes through Dl instead. The second mode is negative polarity of input voltage. During negative input polarity, U8A wiU be high, holding inverters U7B (output) low and U7A (output) high. With U7A high, both OR gates U6A and U6C will be high, turning on Ql via U2 and Q3 via U4. With U7B low, U6B is controUed by the modulator output from Ul-11. A turn on delay (rising edge) is provided by R18 and C23. Turn off is not delayed because diode D 14 bypasses R18 on the falling edge. U6B in turn controls Q2 via U3. At the same time, U7B low aUows U6D to be controUed by the inverted modulator output Ul-14. It contains a simUar turn on delay circuit 192 comprised of R19, C24 and D13. Both delay times are the same and are sufficient to prevent Q2 and Q4 from conducting simultaneously during operation. U6D controls Q4 via U5. The two conditions of operation for negative polarity are 1) negative output current, and 2) positive output current. During negative output current, Ll current is controlled through Q2 and Dl during the Q2 "on" state. When Q2 is turned off, Ll current freewheels through Q3 and D4. Q4 is turned on (after delay) during the time that Q2 is off, but no current flows through it due to its polarity; the current passes through D4 instead. During positive output current, Ll current is controUed by Q4, passing through Q4 and D3. When Q4 is turned off, Ll current freewheels through Ql and D2 back from the input. Q2 is turned on during that time, but no current flows through it due to its polarity; current passes through D2 instead. The third mode is polarity transition, with the two conditions being positive transition and negative transition. During positive transition (from negative polarity to positive polarity), Q2 and Q4 are turned on at transition according to the previously described comparator and logic states. Ql and Q3 had been turned on during negative polarity, as explained above, and do not now turn off immediately at this transition because of a delay circuit formed by resistor R16 and capacitor C25. Diode D 11 prevents any turn on delay during this transition. During negative transition (from positive polarity to negative polarity), Q 1 and Q3 are turned on at transition according to the previously described comparator and logic states. Q2 and Q4 had been turned on during positive polarity, as explained above, and do not now turn off immediately at this transition because of a delay circuit formed by resistor R17 and capacitor C26. Diode D12 prevents any turn on delay during this transition. In some preferred embodiments the turn on delay is comprised of a circuit wherein a high input transition creates a high output transition after some predetermined delay, and a bw input transition results in an immediate (i.e., minimum delay) bw output transition. This is aU preferably accomplished with a diode, resistor and capacitor combination, such that on a low-to-high transition, the capacitor is charged high through the resistor, taking an amount of time to reach the logic threshold voltage of the OR gate being driven, thus providing a delay, the amount of which may be selected through selection of the values ofthe diode, resistor and capacitor referred to above, as will be appreciated by those skilled in the art. Then, on a high-to-low transition, the resistor is bypassed by the diode creating a bw impedance discharge path to greatly increase the discharge rate of the capacitor. The capacitor voltage is thus lowered in minimum time, and the logic transition thus occurs with minimum delay. In preferred embodiments the turn off delay is comprised of a circuit wherein a low input transition creates a low output transition after some predetermined delay, and a high input transition results in an immediate (i.e., minimum delay) high output transition This is also aU preferably accomplished with a diode, resistor and capacitor combination, such that on a high-to-low transition, the capacitor is discharged low through the resistor, taking an amount of time to reach the logic threshold voltage of the OR gate being driven, thus providing a delay, the amount of which also may be selected through selection of the values of the diode, resistor and capacitor referred to above. Then, on a low-to-high transition, the resistor is bypassed by the diode creating a low impedance charge path to greatly increase the charge rate of the capacitor. The capacitor voltage is thus raised in minimum time, and the logic transition thus occurs with minimum delay. For either or both of the turn off and turn on delay methods disclosed, a number of alternate methodologies may be used to create the respective delays, such as use of monostable multivibrators, counters, microcontroUers, and the Uke, aU as will be appreciated by those skUled in the art. As a result of this logic, for either positive or negative transition, the input voltage and output voltage are momentarily clamped and are likewise momentarily effectively short circuited to the inputoutput return and to each other. However, though this runs contrary to conventional thinking, the transition logic events described above aU occur at a point in the input voltage waveform where the absolute value of the instantaneous input voltage is actuaUy less than the total semiconductor voltage drops between the input voltage and the input output voltage return (i.e., less than about four volts in the circuit iUustrated). For this reason, no excessive current inputs are drawn during transition. Output voltage is held at a minimum voltage, proportionate to the input voltage, as it should be. Ll current freewheels appropriately, and no excessive voltage spikes occur on either the input, the output, or across any ofthe transistors or diodes in power stage 130. After turn off delay, transition is complete, and operation returns to either positive or negative polarity mode, as appropriate, and as discussed above. OveraU control logic and operation of controUer 100 is therefore fuUy defined, logicaUy controlled at aU times, and smooth in transition for aU modes and conditions. In the circuit illustrated in Figure 4, preferred component values and/or part types are given in the table below. This list, in conjunction with the schematic and other disclosure herein, will enable the technician or other skilled artisan to construct the circuit disclosed. This list, with such differences as will be appreciated by those skilled in the art also illustrates componentry of other topologies and embodiments disclosed herein. Drawing Numerals Part Type C1 - C8 .1UF R30 LOOK R12 - R15 1.21K D11 - D15 1N4448 Q5 2N3906 06 2N7000 C13 - C15 2UF 400V R5 - R9 4.99K RIO 5.1 10W C12, C16 - C18 5UF 400V R31 6.21K Rl - R4, R27 - R29 10.0 R16 - R21 10.0K R32 10K R33 20K Fl, F2 25A LA 30UH C27 47PF L2, L3 50UH RU, R25, R26 82K 2W R22 90.9K R24 100K C19 - C26 100PF C9 - Cll 100UF C28, C29 220PF Ll 240UH R23 453K C30 4700PF U7 CD4049UB U6 CD4071B D9, D10 HER105 D5 - D8 HER305 D1 - D4 HFA25BP60 JPl INPUT 81 - Q4 IRGPC50U 8 LM393A JP2 OUTPUT Tl, T2 PE51687 U2 - U5 TC4804 UI UC3824 The functional blocks discussed above with reference to Figure 4 can be further understood now by reference to Figure 5. Power controUer 100 (also sometimes referred to herein as a converter) has four OR gates 181 • 184 in logic control unit 190 fed by outputs from polarity detector 160 and duty cycle modulator 170 through turn off delays 194, 195 and turn on delays 192, 193 such that OR gates 181, 183 each receive as a first input an output from the polarity detector 160 (inverted) through delay 194, and OR gates 182, 184 each receive as a first input an output from the polarity detector 160 through delay 195. OR gates 181, 182 each receive as a second input an output from the duty cycle modulator 170 through delay 192, and OR gates 183, 184 each receive as a second input an output from the duty cycle modulator 170 through delay 193. The output from each OR gate, through appropriate level shifting in level shift block 180, controls or drives one of four switches Ql - Q4 in power stage 130 (through its respective gate) each. Preferably, the switch sources of each pair of switches are tied together, as illustrated in this drawing figure, but do not have to be in some alternate embodiments, such as that shown in Figure 9. Preferably, each switch is a soUd state switching device, with a diode, poled to have a sense opposite to the switch, in parallel across the source and drain of the switch, and with the diodes of a pair of such switches opposite in sense to each other, as illustrated. The switches are preferably transistors, such as the IGBT transistors iUustrated for Ql - Q4. This embodiment of controUer 100 has a buck regulator type of topology, but has two switches in series with each other, preferably poled in the opposite sense from each other, and connected with inductor Ll to input 110, and two switches in series with each other, also preferably poled in the opposite sense from each other, and connected with inductor Ll to return 101. The buck regulator general form of controUer 100 in Figure 5, can better be seen in Figure 6a, along with other conventional regulator type configurations for controUer 100. Figure 6b shows controUer 100 in step-up or boost configuration. Figure 6c shows controller 100 in inverting regulator configuration. Figure 6d shows controller 100 in isolated or flyback configuration. As a further iUustration ofthe versatility of the invention, and its potential for replacing conventional topologies without their disadvantages, Figure 7 shows the corresponding "dual" transforms for each of the four topologies shown in Figure 6. Figure 7a shows controUer 100 in step-down or buck dual configuration Figure 7b shows controUer 100 in step-up or boost dual configuration. Figure 7c shows controUer 100 in inverting regulator dual configuration Figure 7d shows controUer 100 in isolated inverting dual configuration. The resulting output controller 100 voltage under any input voltage mode or output current condition is equal to the product of the input voltage and the modulator duty cycle, as more fully discussed elsewhere herein. SUght deviations do exist, due to turn on delay times and semiconductor and resistive voltage drops, as will be appreciated by those skilled in the art, but the overaU waveform purity is excellent in the disclosed circuit, especially at higher voltages (such as 230VAC and up). The controUer or converter apparatus and method ofthe invention is envisioned for use in a wide range of appUcations via a range of alternate topologies disclosed herein. For instance, it is envisioned that control modules comprising the apparatus or methodology ofthe invention can be made for manual usage, power factor correction and automatic power factor correction, as a universal Une conditioner, a motor economizer, and as a harmonic neutralizer. Other uses such as industrial process controls can be accessed via standard industrial interfaces such as the 4-20mA current loop, and any one of a number of other standard control interfaces, such as RS232, RS485, IEEE488.2, VXI, 0-lOV, 0-5V, +/-10V, +/-5V, and manual. Power converters envisioned can be made for use in a wide range of operating voltages and currents, from for instance 120VAC, 1.5KVA to 600VAC, 200KVA; and even beyond this range, higher amperages can be accommodated by paraUeling two or more of the converter modules of the invention, and higher voltages and currents may be controUed via a controUer/transformer hybrid. In a preferred method of the invention, with aU four preferably transistor switches separately controlled, and modulated differently according to the polarity of the input voltage, a sequence can be implemented whereby each switch turns off only into the instantaneous Une input voltage, as graphically represented in the timing diagram of Figure 8. In Figure 8, an idealized Une voltage is shown schematically as a sine wave with representative cross over points 901, 902, 903 (the points where the waveform line crosses the "zero crossing" Une, emphasized by vertical dashed Unes, and corresponding to the point in time where the waveform shifts from one polarity to the other). A pulse width modulation (PWM) signal 920, capable of ranging between 0% and 100% (and here illustrated at about 50%), and its "anti-modulated" reciprocal 921, are fed into a logic network, such as has been described herein, along with the output from a Une polarity detector. When Une voltage (polarity) is positive (time duration 910), switch Ql is pulse width modulated (on and off), each "on" time 911 sUghtly delayed relative to the corresponding rising edge 912 of the PWM, and in Uke manner, Q3 is anti-modulated (ie. the opposite state of Ql, or in other words, when Ql is on, Q3 is off, and υice-versa). A small delay or dead time 913 is added for each turn-on of each switch (emphasized with dotted lines) to avoid simultaneous conduction, where the amount of time will depend on the characteristics of the particular switch employed, aU as will be appreciated by those skilled in the art. Q2 and Q4 remain on 915, 916 at aU tunes during this positive polarity operational phase. When Une voltage polarity is negative (time duration 930), Q2 is pulse width modulated and Q4 is anti-modulated (le. the opposite state of Q2). Again, a small delay 913 (present, but not emphasized with dotted Unes) or dead time is added for the turn- on of each switch to avoid simultaneous conduction, and Ql and Q3 remain on 935, 936 at aU times during this negative polarity operational phase. At crossover 902, 903, Q3 turn off delay 941 and Q4 turn off delay 942 (emphasized with dotted lines) assure that at least one switch (preferably aU switches, as here iUustrated) remains on, or conducting. Preferably, aU switches are turned on simultaneously at this zero cross for a short period of time (on the order of a few microseconds) to aUow continuous current to flow in either direction during zero crossing transition without initiating voltage spikes on any ofthe switches at that time, as more fully disclosed elsewhere herein. This may be aU be summarized in Table 1. Table 1 INPUT SWITCH STATES POLARITY Ql Q2 Q3 Q4 POSITIVE MODULATE ON MODULATE ON NEGATIVE ON MODULATE ON MODULATE TRANSITION ON ON ON ON Note: "MODULATE" it oppoait* of "MODULATE" In Figure 30, an alternate control logic for logic section 190, with additional control input 210 to modulator 170, is implemented as summarized in Table 2. Table 2 Mode Voltage Current Ql Q2 Q3 Q4 Quadrant I + + mod on off on Quadrant II + - off on mod on Quadrant III - - on mod on off Quadrant IV - + on off on mod Voltage Transition (-Ho-, -to+) 0 X on on on on Mode Transition (Quadrants I to II, II to I) + X off on off on Mode Transition (Quadrants III to IV, IV to III) - X on off on off Shutdown + X off on off on Shutdown " X on off on off j where "mod" means modulate (i.e., by means of PWM, pulse frequency modulation, or the like as will be known to those skilled in the art); where "x" means that it doesn't matter what the polarity ofthe current is; where "Mode" refers to the various operating states that can occur during operation of the power controUer; where "Voltage" refers to the input voltage polarity of controUer 100 (from the polarity detector 160) and where "0" refers to the voltage transition point; where "Current" refers to the output current polarity from power controUer 100; and where Ql, Q2, Q3, and Q4 are the outputs that define the operation of those respective power switches. These switches interface with the control logic section 190 via conventional level shift circuitry 180. It should be kept in mind that, while a mode transition might look inconsistent with an "x" as a current state, in the various Quadrant modes, current is a desired output resulting from the logic scheme rather than an input to it. In preferred embodiments, converter 100 chooses its quadrant modes based upon input voltage and error circuit output (in modulator 170). Thus, a positive input voltage will determine that either Quadrant I or Quadrant II wiU be employed, wbile a negative input voltage will determine that either Quadrant III or Quadrant IV wiU be employed. The selection of Quadrant I vs. Quadrant II or Quadrant III vs. Quadrant IV is dependent upon the error circuitry on the other hand. The error circuitry compares output voltage to the reference and determines both the required direction of current flow and the required amount of modulation by way of the error amplitude output to maintain converter output regulation Thus, in the practice of the invention in this aspect, current can be in either direction for any particular Quadrant or transition without damaging the converter 100. In operation, the logic scheme summarized above for controlling the power switches drives the output current in the right current direction; the transitions serve only to provide a controUed and nondestructive logic transition between operating modes. It should also be noted that both Mode and Voltage transitions are short term events that last in the range of a few hundred nanoseconds to several microseconds, with typical times on the order of a microsecond. Quadrant selection in these embodiments can be roughly analogized to changing motor directions in a motor driven watercraft. The motor has both direction (forward and reverse) and magnitude (throttle) control, which correspond to quadrant modes and modulation ampUtude, respectively. It is clear then that it is not necessary for either the boat, or the converter, to be stopped (zero output current) in order for the boat to change motor directions, or for the converter to transition between modes. The advantages of he control logic scheme summarized in Table 2 are several: 1. It provides for a truly instantaneous regulator because only one switch is modulated at a time, whereas other schemes use a sequence or a series of switches and the whole sequence or series has to run before a return to a changed switch state. 2. There are no deadtimes. This differs from some disclosed embodiments where deadtimes are appUed to prevent simultaneous conduction across power switches. In this scheme there is no opportunity for cross conduction; the switching is virtuaUy instantaneous. 3. Lower switching losses and discontinuous conduction at lower power ranges aUows for higher efficiency. 4. No snubbers are required, so there are no snubber losses. 5. It can make use of an "aU on" zero crossing. 6. It provides for devices with true four quadrant operation and bi-directional power flow. In Figure 32 a preferred embodiment of the power controUer 100 is shown in block diagram form, with particular reference to variation of details of input to the modulator section 170. Sine wave reference 162 feeds polarity switch 163, is in phase with the voltage at input 110, and may be derived from any of a number of known sources. For instance, a sine wave generator, phase locked to the input line, or a microprocessor look up table, could be used. The input voltage itself, attenuated and optionaUy filtered to eliminate harmonics, could also be employed in some appUcations. Voltage polarity detector 161 senses polarity (+ or -) of the input voltage at the input of power stage 130. When input voltage is positive, detector 161 outputs a high logic state to aU polarity switches 163 - 165 and to control logic 190. When input voltage is negative, detector 161 outputs a low logic state. If polarity switches 163 - 165 receive high logic input, they pass their input directly to their output; if they receive low logic input, they first invert their input signal, then pass it to output. This configuration is preferred over a simple full wave rectification block. In order for the error corrector 172 to properly signal modulators 173 and 174, all references and error signal inputs must be referenced to the polarity ofthe voltage across the iiφut to power stage 130. Output voltage and current transients and rings could temporarily change polarity, but the error signals must not change polarity state or else error corrector 172 wiU amplify errors rather than correct them. Gain control 171 receives input from polarity switch 163 and sine wave reference 162. It is an adjustable attenuator varying the ampUtude of the reference signal to error corrector 172. Gain control 171 also receives input from control input 210 which is preferably an external input to determine overaU output level, as will be appreciated by those skUled in the art. In a preferred embodiment, it is a digitally controlled attenuator, but in some appUcations, a simple potentiometer would suffice. Error corrector 172 then compares the attenuated reference signal with the output voltage from output 150 and, optionaUy, the output current, from optional current sense 220, one or both of which are run through optional attenuator 230 and then through polarity switches 164 and 165, respectively, as described above. Error corrector 172 then outputs a signal to modulators 173 and 174 that wiU keep power controUer 100 output 150 accurately foUowing the reference. In a preferred embodiment, this is accomplished with a single error amplifier, although a microcontroller may also be used advantageously, as wUl be appreciated by those skilled in the art. Each of the modulators 173 and 174 receive an input from error corrector 172 and convert it to a digitally modulated output. This is generally in the form of PWM ranging from 0% to 100% at frequencies preferably between 10 KHz andδO KHz, depending upon the appUcation Other frequencies and other modulation methods such as pulse frequency modulation (PFM) may be employed as weU. In a preferred embodiment, each modulator comprises a triangle waveform generator and a comparator. The triangle waveform itself is fed into the negative input of the comparator and the error corrector output is fed in the positive input of the comparator. The comparator output of each modulator is then fed to control logic 190. Preferably, each modulator has its triangle wave input offset from the other in order to allow a sequential response from the modulators according to the output of error corrector 172. For instance, in a preferred embodiment, triangle waves of 2.5V peak to peak are offset in relative steps of 2.5V as they feed into the modulator comparators. Modulator 173 (for Ql, Q2) then responds to error corrector outputs of 3.5VDC to 6.0VDC, while modulator 174 (for Q3, Q4) responds to error corrector outputs of 1.0VDC to 3.5VDC. In addition, the output of modulator 174 is preferably inverted. The overaU output response o the modulators is therefore in accordance with Table 3 (where "1" is "on", and "<r is Off). Table 3 Error Corrector Output 3, 4 Modulator Output Ql, Q2 Modulator Output 0.0V to 1.0V 1 0 l.O to SΛV MODULATE 0 3.δVto β.0V 0 MODULATE 0 >6.0V 0 1 Outputs from polarity detector 161 and the modulators are fed into control logic 190, which outputs power transistor drive signals according to Table 2 or 4. Optional current sense 220 senses for overcurrent protection or for output current 5 regulation into a load. It is preferably a current transformer, but may also be via an isolation amplifier, haU effect sensor or other means known to those skilled in the art. Attenuator 230 is preferably a simple resistive divider. Where the power converter of the invention drives only nonreactive loads (i.e., in Quadrants I and III only), a simplified logic scheme may optimally be employed, as 0 summarized in Table 4. Table 4 Mode Voltage Current Ql Q2 Q3 Q4 Quadrant I + + mod on off on Quadrant m - • on mod on oσ Voltage Transition (-Ho-, -to+) 0 X on on on on Figure 33 iUustrates a high voltage regulator 1000 embodiment ofthe invention comprised of two power converters 1001 and 1002 of the invention and a transformer 1060. An input voltage from an AC source is connected to VIN (high) 1090 0 and VIN (low) 1020. VIN (high) 1090 and VIN (low) 1020 connect to primary winding 1051 of transformer 1050, and VIN (high) 1090 also connects to output 1061 of controUer 1001. Output 1062 of controUer 1002 is connected to VOUT (high) 1030, while VIN (low) 1020 is connected directly to VOUT (bw) 1040. Both controllers have as their voltage source secondary winding 1052 and each δ controUer is controUed independently so that the difference in output voltages of the two controUers is algebraically added to input voltage at VIN (high) 1090. For example, if the input voltage is 10, 000 VAC and the secondary winding is δOOVAC, which is within the operating range ofthe invention controUer, both controUers are controUed to remain at zero output voltage when no regulation is needed, since the difference between the two controUer outputs is thus zero, and the input voltage passes to the output at VOUT (high) 1030 unmodified. It will be appreciated that the difference is also zero if both controUers are modulated to some identical, but non-zero, voltage, except that that would not be as efficient a usage of power in the controUers themselves. If controUer 1002 is modulated to increase its output voltage with respect to its return, and if controUer 1001 is controUed to produce zero output voltage, then an AC voltage equal to the difference in output voltages of the two controUers is added to VIN (high) 1090 and sent to VOUT (high) 1030. This output addition is typicaUy adjustable from 0VAC to 500VAC. Then to achieve a like continuously adjustable subtraction of voltage from VIN (high) 1090, controUers 1001 and 1002 are modulated inversely from that outlined above, so that 1001 has increased output while 1002 remains at zero. In this manner, for the given example, voltage may be continuously varied from about 9500VAC to 10.500VAC (10KVAC - 500VAC to 10KVAC + 500VAC), for a total high voltage regulation range of +/-5%. In Figure 34 an extended range high voltage AC regulator 1080 is Ulustrated. Extended range (for instance over that associated with the embodiment in Figure 33) is achieved by adding another secondary winding 1053 and another pair of power controUers 1003 and 1004. The two pairs of controUers illustrated are connected as shown in series with each other (output 1062 connected to output 1063), and the outputs of each pair are thus simply added to each other and to VIN (high) 1090. The number of controUer pairs employed in this fashion may also be increased to achieve any particular desired regulation range (in the example above, thus adding 500VAC of range per pair). Optional conventional fail sense circuitry may be employed in such multiple pair embodiments to insure that operable pairs continue to provide maximum range leaving off only the failed pair(s). Figure 35 Ulustrates a three phase delta high voltage conditioner 1110 embodiment corresponding to the single phase embodiment of Figure 34. Three transformers 961, 962, 963 have their respective primaries connected to the reespective phase input voltages 971, 972, 973. These are shown as three separate transformers, although a single conventional three phase transformer may also be employed. Each transformer primary has two associated secondary windings for the purpose of adding or subtracting voltage from the input voltage as previous described for Figures 33 and 34. As it is typicaUy desirable to keep the output of such a system in phase with the input, especiaUy when employing the circuit in utility appUcations, each phase is 5 modified by two power controUer pairs. For example, to regulate phase A, it is fed through controUers 1001 and 1002 (delta phase C-A) and controUers 1007 and 1008 (delta phase A-B) to phase A output 981. In like manner, phase B is fed through controUers 1005 and 1006 (delta phase A-B) and controUers 1011 and 1012 (delta phase B-C) to phase B output 982, and phase C is fed through controUers 1009 and 1010 (delta 10 phase B-C) and controUers 1003 and 1004 (delta phase C-A) to phase C output 983. Compare this embodiment to the other three phase delta power controUer of Figure 31. Figure 9 Ulustrates an alternate embodiment of the power converter of the invention It is particularly weU adapted for higher power (100A and up) appUcations. It is in most respects the same as that shown in Figure δ, except for the arrangement lδ of switches Ql - Q4, and a different switch diode arrangement. Ql • Q4 are independently controUed as before (logical control direct to the gate of each switch, no two gates tied together or receiving control from the same logical controUer element), but the switch sources of respective switch pairs (i.e. Q1-Q2) are not directly tied together, as they are in the embodiment in Figure δ. Diodes Dl - D4 are also differently 0 placed, rather than simply connected across source and drain of their respective switches. Additional diodes Dδ • D8 are relatively smaU and inexpensive, and added to the design to help bypass the switches as they (diodes Dl - D4 )tum off, but are not necessary when MOSFET switches are used (instead ofthe preferred IGBT's). In a power factor correction appUcation the converter circuit ofthe invention can δ interface between the power line and a PFC capacitor, and/or reactor. If the power factor, or the phase delay, on the Une is measured, and then fed into an appropriate error amplifier, of such design as will be readily avaUable to those skiUed in the art, then the power controller with its control circuitry wUl automatically correct power factor on the Une, even approaching unity PF, and with response time on the order of 0 0.1 seconds. Figure 10 shows such an automatic variable power factor corrector 600, having a power controUer 100 and power factor correction capacitor(s) 630 and control circuitry. This topology is weU adapted for correcting lagging power factor due to use of motors and transformers on the line. 5 Operation of automatic power factor corrector 600 is based upon the addition of a variable leading load in parallel with the lagging load to be corrected. The two loads wiU cancel each other out, achieving a unity power factor. This is accompUshed by varying controUer 100 output into PFC capacιtor(s) 630, so that the varying output voltage in turn varies output current into capacitor 630, so that a variable capacitive load is reflected back into the power line. Automatic correction is achieved by adding a current sensor 641 in series with the load. A current sense signal 671 firom current sensor 641 is compared with a voltage signal 672 to detect phase delay (and thus power factor) in phase delay detector 620. A phase error amplifier 650 receives this phase delay information 673 and adjusts power controUer 100 through its modulator 170 to vary reflected capacitance, and thus minimize phase delay (bringing PF toward unity). This loop preferably has a bandwidth of 20 Hz or less. (Power controUer 100 is shown as a dotted block w th its modulator 170 drawn as though separate to emphasize its function in this illustration.) PFC capacitors can resonate with other elements m the power system. To limit or eliminate this possibility, an optional additional current sensor 642 is placed between controUer 100 output and PFC capacitor 630, m series Within current sensor 642, the fundamental Une frequency is filtered out, as will be appreciated by those skilled in the art, to leave only harmonic currents information. Current sense signal 674 containing this harmonic information is then sent to a fast error amplifier 660 (several KHz bandwidth) which in turn adjusts modulator 170 of power controUer 100 to keep the capacitor current sinusoidal (non-harmonic). Thus power controUer 100 responds to slow signals from power factor error amplifier 650, and fast signals from harmonic error amplifier 660. The result is an automatic power factor corrector 600 with continuous variability and which does not tend to resonate with other elements m a power distribution system. The disclosed PFC method and apparatus can also be configured for three phase PFC for effecting balanced loads by employing two power controUer units 100a and 100b, and three PFC capacitors 630ab, 630ac and 630bc as shown in Figure 11. In this embodiment, power controUer 100a is preferably in paraUel between a first AC Une (A) and a third AC line (C), and power controUer 100b is in paraUel between a second AC line (B) and the third AC line Capacitor 630ac is preferably connected between the output of controller 100a and AC line (C), capacitor 630bc is connected between the output of controUer 100b and AC line (C), and capacitor 630ab is connected between the output of controUer 100a and the output of controUer 100b. Figure 12 shows a configuration for controlling three phase induction motor 612, as an alternate PFC correction method accomplished by lowermg the motor terminal voltage via controUers 100a, 100b when motor 612 m not operating at full load. Power controUer 100a is in series in Une 1, and power controUer 100b is in series in Une 3. Both controUers return to line 2. Independent modulation and control of controUers 100a, 100b results in optimal power conversion and control for induction motor 612, while also optimizing power quaUty on the three phase line system, δ The power controUer 100 of the invention is also weU adapted to be used in combination with simple componentry to fashion fuUy (and optionaUy automaticaUy) adjustable components, such as capacitors, inductors, resistors, and the like, for example as shown in Figures 13, 14, and 15. In Figure 31, a three phase delta power conditioner is shown in block diagram 0 form. It is a combination of three power controUers of the invention and three transformers, which together implement a circuit for controlling the output voltage of a delta wired three phase input. Each power controUer is connected between two different phases and each controUer divers a transformer which modifies the voltage on two different phases. Put differently, each phase is acted upon by two different 5 converter/transformer combinations. As an illustrative example, regard phase A IN 971 in Figure 31. Power controUer 992 is connected between phase B and Phase A and drives transformer 962. Power controUer 991 is connected between phase A and Phase C and drives transformer 961. The primary return of transformer 962 is connected to phase A IN 971, and the autotransformed tap of transformer 962 is in turn fed to the floating winding of transformer 961. The output ofthe floating winding of transformer 961 is then fed to the output as phase A OUT 981. Now under normal operating conditions, aU controUer outputs start at zero output voltage. In this mode, phase A passes through transformer 962 and transformer 961 unmodified. However, as power controUer 991 and power controUer 992 increase their output, phase A begins to be modified. Increasing output voltage from power controUer 992 through transformer 962 moves the output tap of transformer 962 closer to phase B. Similarly, an equal increase in the output voltage from power controUer 991 through transformer 961 moves phase A OUT 981 an equal distance toward phase C. The result of these two vectors is that phase A OUT 981 is reduced in ampUtude but remains in phase with phase A IN 921. A Uke effect upon phase B and phase C will be appreciated, so that the overaU effect is an adjustable delta voltage source, concentric with the input voltage, and in phase with it. If the controUers are independently adjusted, then input phase angle irregularities may also be compensated for, which reduces voltage imbalance losses in three phase motors and transformers. For operation from no output voltage to fuU output voltage, the turns ratio of each transformer primary to its autotransformed tap and floating winding is 3:1:1. Numbers higher than this (such as 6:1:1) will result in a smaUer range of voltage adjustability while reducing the required output current from each power controUer. In an alternate embodiment, each of the three power controUers is connected to a different iiφut phase and provides an output that is between 0% and 100% of the input voltage (i.e., between IN and RETURN). Each output drives the primary of its own transformer, where each such transformer has an autotransformed tap that is fed into the auxiliary winding of the transformer that is connected to the adjacent phase. The output of that auxiliary winding is then the conditioned output of the phase for that transformer. For the full range output from OV to the fuU input voltage, the turns ratio ofthe transformer is: N(primary) = 3 N(tap) = 3 N(auxiliary) where N(primary) is the number of total turns from the output of the power controUer to its return, and it includes the turns in the tapped winding. Operation over different ranges is possible by varying the transformer turns ratio, as long as the tap and auxiliary windings aU have the same number of turns. It will be appreciated therefore that output voltage is at a maximum (approaching the iiφut voltage) when aU power controUers are at minimum output voltage. Conversely, output voltage is at a minimum when aU power controUers are at maximum output voltage. GeneraUy speaking, it will be preferred to operate aU three power controllers at equal output voltages; however, since they may all three be individuaUy controUed, the conditioner can be used to compensate for voltage imbalance on the input. Figure 13 shows adjustable capacitor 510. Power controUer 100 variably reflects the capacitance of capacitor Cl back onto the input and return connections. The reflected capacitance value ranges between 0 and the fuU rated value of Cl. Typical applications would be adjustable power Une filters with variable frequency and ampUtude characteristics, and adjustable components of harmonic current traps and rejecters. See discussion infra of Figures 24 and 25. Figure 14 shows adjustable inductor 520 whose reflected inductance can be varied, via controUer 100, between the fuU rated value of Ll and (theoreticaUy) infinity. Its appUcations are as complementary components to the variable capacitor in its appUcations as disclosed above. It should be noted that for a duty cycle D and a full rated inductance L, reflected inductance is given by the formula: I^ fl = L/ D 2 Figure 16 shows variable resistor 530 with a resistance value adjustable, via controUer 100, between Rl and (theoreticaUy) infinity. This topology would have applications including motor controls, a variable damping element in power line filters, δ and variable AC/DC power loads for testing electrical equipment (transformers, generators, AC power suppUes, inverters, power distribution systems, and the like). Figure lδ shows adjustable harmonic rejector (shunt filter) 6δ0 with controUer 100. Inductor Ll is connected between the output of controUer 100 and the return, wbib capacitor Cl is connected between output and iiφut of controUer 100. As 10 controUer 100 duty cycle is increased, both reflected capacitance and inductance decrease. The result is a paraUel LC filter with resonance (or "notch") that is tunable over a wide frequency range. This would have appUcation in power Une harmonic voltage and current reduction. For instance, the unit could be instaUed in series with the power line and its resonance adjusted to reject a desired harmonic. In response to lδ changes of load on the system, it may be suitably readjusted, either manually or automaticaUy, for optimum performance. Figure 17 shows AC power conditioner 700 for regulating output voltage over a Umited range. This configuration aUowβ use of a lower voltage power controUer than one otherwise required for operation over a larger voltage range. 0 Input voltage is fed to autotransformer 702 having two output taps 704, 706. Lower tap 706 is configured to be the lowest desired voltage step down, whUe higher tap 704 is set for the highest desired voltage step up. Power controller 100 is connected between these two taps and thus varies the output voltage from one tap to the other in continuously variable increments. Conditioner/converter 700 may thus be used either 5 as a constant output voltage regulator for iiφut voltages that vary, or as a device for providing varying output voltages from a constant input voltage. Using this configuration, if an output variation range of +/- 20% is desired, then power controUer 100 itself need only withstand 40% ofthe input voltage. This aUows available semiconductors to regulate much higher output voltages than if the controUer 0 100 were operating without autotransformer 702. In lower voltage circuits (such as 120VAC), it aUows inexpensive low voltage semiconductors (<100VDC) to be used, giving significant cost advantages over other Une conditioning methods. Figure 18 shows isolated output AC power conditioner 710 having power controUer 100 and three part coupled magnetic structure 720. This topology provides 5 isolated variable output voltage over a Umited output range while also providing galvanic isolation from input to output. Magnetic structure 720 comprises three core sections which are coupled at each end. Each section has associated winding 722A 722B, and 722C respectively, each winding having a number of turns N*, N and N c respectively. For operation within the saturation limits ofthe core, voltages V may be appUed to the windings according to the foUowing formula: V A / N A + V B / N B + V c / N c = 0 whfle the corresponding formula for current is: In this isolated output AC power conditioner, input voltage is appUed directly across winding 722A. Power controUer 100 receives the same input voltage and appUes a variable voltage across winding 722B with the number of turns N B corresponding to the maximum amount of output voltage regulation range desired. The voltage deUvered from the output winding 722C can be described therefore by the foUowing formula: V out / N c = -V m / N A - V ∞ntroUer / N B With this topology, N B can be much greater than N A as the output regulation range is reduced. Thus power controUer 100 output current is reduced for a given total conditioner 710 output current (and power), and Une regulation over the desired range is accomplished with a relatively smaUer power regulator 100. Costs are thus reduced, efficiency is increased, and larger amounts of power may be regulated than by merely cascading a power controller with a standard isolation transformer. AppUcations for this topology are anticipated in line voltage regulation, data processing, telecommunications, and medical equipment. Figure 19 shows high voltage input AC power conditioner 730. The circuitry is substantiaUy the same as for Figure 18 above, except that power controUer 100 is operated from a voltage that is lower than the input voltage. Winding 722A has tap 724 in it, creating in effect a step down autotransformer for use by controUer 100. The tap voltage is selected according to the voltage input limitations of power controUer 100. AU other specification and operation is the same as above. This topology can regulate voltages far beyond what could be done with conventional power semiconductors employed in direct regulation. As an example, the input voltage can be as much as 13,200V, and yet regulation can be accomplished using nothing more than standard semiconductors (liaving ratings such as 1200V or 1700V). AppUcations are envisioned in regulated distribution transformers such as those dropping distribution voltages down to 120/240VAC for residential and commercial customers. Figure 20 shows AC hybrid power conditioner 740, similar to AC power conditioner 700 disclosed above, except that it is capable of connecting different taps 746a-d in autotransformer 742 to the input voltage. Output regulation is generaUy accomplished in two steps. The first step comprises selecting and connecting an appropriate tap 746a, b, c, or d on autotransformer 742 to the input voltage. The tap is selected so that the iiφut 748 of power controUer 100 is higher than the desired output voltage and the return of power controUer 100 is lower than the desired output voltage. Connection is preferably accomplished using thyristor switches 746a-d, and in a manner similar to connection in conventional tap switching Une conditioners. The second step consists of modulating controUer 100 to provide an adjustable output voltage that can be varied continuously between its input and return voltages. By combining these steps, precise regulation of output voltages is possible over a wide range of input voltages. This circuit topology aUows controller 100 to operate over a smaller voltage range so that lower voltage power controUer components may be employed for a given output voltage. At the same time, continuous output adjustability is maintained, providing superior regulating capability over conventional power conditioners. Figure 21 shows hybrid isolated AC power conditioner 750, simUar to high voltage input AC power conditioner 730 disclosed above, particularly in that it uses a three part magnetic structure 720 and power controUer 100, but it adds tap selecting capability to the winding 722A. Tap connection is preferably accomplished using thyristor switches 744a-c to connect the proper tap 746a-c of winding 722A to the iiφut voltage. This tap selection allows a coarse adjustment ofthe output voltage in one or more discreet steps. Fine adjustment is achieved by varying the voltage on winding 722B by varying the output of power controUer 100. With tap selecting capability in this embodiment of the invention, power controller 100 is only required to regulate over a much smaUer range than otherwise practical or useful, and the amount of power deUvered by controUer 100 to the transformer is decreased. This aUows either a decrease in the size of the power controUer, or an increase in the output capability ofthe conditioner system for a given size power controUer. Figure 22 βchematicaUy Ulustrates preferred AC voltage regulator 300 of the invention This circuit employs two power controUers 100a and 100b that drive opposite ends of a primary winding 311 of transformer 310. Secondary winding 312 is in series with Input line (high). Regulator 300 functions by using the secondary 312 output to either add to or subtract from the input voltage. Adding and subtracting are controUed by separately modulating the outputs of controUers 100a and 100b. There are three modes of operation. In mode 1, both controUers are at zero output voltage. The transformer primary 311 is thus clamped to no voltage, while the current is aUowed to pass through secondary 312 (and through the primary as reflected through the transformer). Zero primary voltage translates to zero secondary voltage, and the input voltage is thereby maintained firom input to output with voltage neither added nor subtracted. In mode 2, controUer 100a output is increased over the output of controUer 100b (preferably held at a minimum). In this mode, a variable amount of voltage from controUer 100a on primary 311 adds a proportional voltage (according to turns ratio of primary to secondary windings) to the input voltage, and output voltage is thereby effectively increased. In mode 3, controUer 100b output is increased over the output of controUer 100a (now preferably at a minimum). In this mode, a variable amount of voltage from controUer 100b on primary 311 subtracts a proportional voltage (according to turns ratio of primary to secondary windings) from the input voltage, and output voltage is thereby effectively decreased. For industrial level (460VAC) voltage regulators, a +/- 10% variability is required. This would mean a transformer turns ratio (primary to secondary) in the preferred circuit of approximately 10: 1. With this circuit and conventional power semiconductor technology, it should be possible to provide regulation at power levels in excess of 1MW per phase. Figure 23 schematicaUy Ulustrates preferred isolated AC voltage regulator 320 of the invention. Regulator 320 is anticipated to be used to take utility distribution voltages and provide isolated and regulated low voltage outputs for residential, commercial, and industrial appUcations. In operation, input voltage is appUed to input winding 331 and provides thereby most of the voltage that is transformed to output winding 333. Two power controllers 100a and 100b operate in accordance with the disclosure herein from a lower voltage tap 335 on winding 331. ControUers 100a and 100b are used to drive intermediate winding 332, which preferably has several time the number of turns of winding 331. Output winding 333 has conventional neutral tap 338 The two power controUers operate in essentially the same three modes as described in conjunction with the apparatus shown in Figure 22. In total, the controllers provide a smaU part ofthe total voltage transformed to winding 333 to effectively adjust output voltage up or down from nominal voltage value, or to clamp to the nominal value. Advantages of this circuit include continuous ampUtude adjustability over the entire regulating range, and no mechanical contacts to wear out. δ Figure 24 schematicaUy Ulustrates adjustable paraUel harmonic filter 400 embodiment ofthe invention. FUter 400 is a system that employs the power controUer 100 ofthe invention as a kind of adjustable capacitor, as more fully disclosed elsewhere herein. PFC capacitor 430 Ues between the output of controUer 100 and low side of load 410. Inductor 420 Ues between input high and controUer 100 input. ControUer 100 is 10 in paraUel with load 410. It is envisioned that filter system 400 will find use as a harmonic current trap, with the advantage of continuous adjustability of its resonant frequency. With continuous adjustabiUty, filter 400 may be fine tuned for better performance and less ringing with other power line components. It may also be readjusted at any time in lδ accordance with the changing line and load conditions in the electrical system. Figure 25 schematicaUy Ulustrates adjustable series harmonic rejector 450 embodiment of the invention. Rejector 450 is a system appUcation of the adjustable harmonic rejector 550 discuss in conjunction with Figure 15, and which functions as a kind of adjustable paraUel LC network. Inductor 420 Ues between controUer 100 input 0 and output, whUe PFC capacitor 430 Ues between controUer 100 output and high side of load 410. ControUer 100 is in series with load 410. Optional filter 460 is in paraUel with load 410. Rejector 450 is envisioned for use to selectively reject any harmonic current in a system so as to keep it from conducting back to source. Rejector 450 may be optionally 5 aided by addition of paraUel filter 460 to absorb (or shunt) any rejected harmonic current. As with the adjustable paraUel harmonic filter 400, rejector 450 may be fine tuned for optimum performance and to accommodate changing power distribution conditions. Preliminary testing of prototypes of power controUer embodiments of the 0 invention are very encouraging. In a test of a power factor corrector embodiment of the invention, a one horsepower pump (running dry, at minimum load, at maximum load), a window fan (at low, medium, high), and a radial arm saw (running idle) were tested, and iiφut current was first measured without any attempt at power factor correction, and PF was noted. Then the corrector ofthe invention was appUed to correct PF, and 5 input current was again measured, and PF noted. The results are summarized in Table 5. AU measurements were taken at 120VAC, 60Hz. 4δ Table 5 Input Input Current Power Current Power Test Unit with/o PFC Factor with/ PFC Factor Comments 1 HP pump 10.74A .365 5.31A .950 Dry operation 14.16A .782 11.68A .986 pumping, min. load 15.10A .853 13.72A .990 pumping, max. load Window fan .649 .988 Low, 93W .690 .986 Medium. 141W « .694 .985 High, 180W Radial M 7.41A .281 3. ISA .845 Running, idle These tests, whUe providing good numbers, highhghted the importance of proper treatment of resonances between the PFC capacitors and parasitic system inductances. The occurrence of this problem is weU known. Most manufacturers of conventional PFC systems use an elaborate and expensive array of optional harmonic "traps" that have to be customized to a specific instaUation. Passive damping, as will be appreciated by those skilled in the art, can to some extent be built into a system to reduce harmonic currents. But active damping, which is preferred, yields better PFC results, increased efficiency, and reduced cost. In active damping, smaU signal control circuitry is used to vary the duty cycle of the PWM in opposition to the harmonics, causing the power controUer to reject the harmonics, and leading to yet higher PF. It is anticipated that it will also lead to reduced resonances in the utility service as well. A second round of testing on the 1 HP motor, running at no load, was conducted to test and demonstrate PFC effectiveness ofthe power factor corrector of the invention with added capability for active damping. Figure 26a is an oscilloscope printout showing the line current waveform of the 1 HP motor running at no load. Input voltage is 120VAC. In this test, PF was noted at below 0.4, with input current at 10.7ARMS. The waveform shows sUght distortion. Common oscilloscope settings for the tests in the Figure 26 series were: auto edge trigger; edge; source=l; level=875.000 mV; and holdoff time= 14.000 mS. Figure 26b is an oscilloscope printout showing the effect of the prototype invention PFC, but without any damping. Input current was substantiaUy reduced to 4.8ARMS. Significant resonance and current draw at the ninth harmonic (540Hz) can be seen Figure 26c is an oscilloscope printout showing the results of adding a passive (and power consuming) damper into the circuit. Input current drops to 4.6ARMS, and the ringing is somewhat diminished. Figure 26d is an oscilloscope printout showing the results of removing the passive damping and e pbying the prototype PFC's own active damping circuit. It can be seen that the ringing has been eliminated (though there remain in this screen traces of crossover gUtcheβ caused by polarity switching in the error amplifier). Some distortion remains on the waveform, this is beUeved to be the uncorrected distortion existing on the original motor current waveform. Iiφut current is reduced to 4.3 ARMS, even lower than with passive damping appUed. Figure 26e is an oscilloscope printout showing, for comparison purposes, the effect of both active and passive damping appUed. In most respects the waveform is identical to the previous printout, but the passive damper clearly contributes to greater power consumption as the iiφut current increases to 4.5ARMS, without significant improvement in the waveform over active damping alone. Better results than these however are anticipated at the higher voltages more common in industrial use. These tests were conducted at 120VAC where IGBT and diode voltage drops are more significant in terms of percentage loss, than would be the case at the higher voltages. Also at 240VAC and 480VAC, there will be less converter loss per KVAR. Secondly, the tests were not conducted in a worst case resonance scenario; in an industrial plant with for less "clean" power, multiple motor and PFC resonant combinations typicaUy create fuse blowing and PFC capacitor failures, and have much greater need for the kind of PFC demonstrated here. Another test was performed as a comparison of a conventional SCR power control device with the invention power controUer (sometimes also referred to in the table and graphs as an "MPC"). Figure 27 is a spreadsheet of comparative data on SCR performance vs. an invention prototype power controUer. A prototype power controUer in accordance with this disclosure was run, in "buck" mode, at 120VACRMS from 100% to 0% of range. Both KW efficiency and KVA efficiency were noted, as weU as both input and output KW, KVA, PF and %THD-rmsa. The SCR device was run over the same range. The results are summarized in the spreadsheet, and the trend ofthe data, at least in certain respects, is evident from reading the spreadsheet. WhUe the SCR remains highly efficient throughout the range from 100% voltage to 0%, and the MPC declines at 50% then falls off badly below 20%, the MPC sustains high input PF to a much lower voltage (stiU .89 at 40%; the SCR falls below .9 around 85%), and maintains near unity output PF down to below 10%. Similarly, the MPC sustains lower input and output current draw throughout the range, and is sharply lower in %THD on both input and output sides. Figure 28 is a graph of relative efficiencies of conventional power control devices compared to the power controUer ofthe invention and Figure 29 is a graph of relative harmonics and power factor (for resistive loads) of conventional power control devices compared to the power controUer of the invention. A study of both graphs together δ suggests that, whUe SCR's with their noted efficiency stay at the top of the graph in Figure 28, they are clearly the worst in PF and %THD performance in Figure 29. In Figure 28, it is apparent that the MPC's KW efficiency is quite close (above 90%) to that of the SCR down to 60% of range, and exceeds the efficiency of both inverters and Unear suppUes down to about 20% of range. In summary, the MPC compared to conventional 10 devices has good efficiency, good power factor, and exceUent harmonics (THD < 1%). With regard to componentry and assembly methodology above referred to, but not otherwise specified or described in detail herein, the workings and specifications of such components and the manner in which they may be made or assembled or used, both cooperatively with each other and with the other elements of the invention described lδ herein, to effect the purposes herein disclosed, are aU beUeved to be weU within the knowledge of those skilled in the art. No concerted attempt to repeat here what is generaUy known to the artisan has therefore been made. INDUSTRIAL APPLICABILITY An electrical converter implemented with a high frequency (>10KHz) and using 0 switchmode power conversion techniques achieves great advantage over existing circuits, including higher output, smaUer size, Ught weight, lower cost, greater efficiency, electricaUy quieter operation and better reUabUity. In broad terms, the largest markets for the invention are related to electrical power quaUty products and electrical energy conservation products. At least half of the 5 appUcations currently identified for the invention relate to improving the efficiency of, or cleaning up power problems caused by, electrical motors and/or motor drives. The Edison Electric Institute reports that there are one billion electric motors in the US alone, and that they consume coUectively nearly half of the total electricity consumed in the US. 30 In compliance with the statute, the invention has been described in language more or less specific as to structural features. It is to be understood, however, that the invention is not limited to the specific features shown, since the means and construction shown comprise preferred forms of putting the invention into effect. The invention is, 5 therefore, claimed in any of its forms or modifications within the legitimate and vaUd scope ofthe appended claims, appropriately interpreted in accordance with the doctrine of equivalents.

Claims: CLAIMS I claim: 1. A power controUer for controlling an AC input voltage to a bad, the iiφut voltage having one or more phases, the controUer comprising: a circuit comprised of four independently controUable switches and at least one inductor, one such circuit for each input Une to be regulated, the switches and inductor(s) ofthe circuit arranged in a conventional power regulator topology, whereby a selected regulator topology may be implemented, depending upon the position of the inductor(s) with respect to the switches and to the input voltage; the controller further comprising logic control having a polarity detector in parallel with the input voltage, the polarity detector having two outputs; and a duty cycle modulator having two outputs; each of the outputs of the polarity detector and of the duty cycle modulator being inverted with respect to one another; whereby each switch is separately controUed and modulated by the logic control so that some combination of one or more of the switches is always electrically conducting. 2. The controUer of Claim 1 further comprising within the logic control circuitry four OR gates, each OR gate fed by an output from the polarity detector through a turn off delay and by an output from the duty cycle modulator through a turn on delay, such that first and third OR gates each receive as a first input a first output from the polarity detector, and second and fourth OR gates each receive as a first input a second output from the polarity detector; and such that first and second OR gates receive as a second input a first output from the duty cycle modulator, and third and fourth OR gates receive as a second input a second output from the duty cycle modulator; whereby output from each OR gate controls one switch. 3. A logic controUer for controlling the duty cycle of a power controUer having four independently controlled separate switches, the logic controller having a polarity detector in paraUel with the input voltage, the polarity detector having two outputs; the logic controUer further having a duty cycle modulator having two outputs; each ofthe outputs of the polarity detector and of the duty cycle modulator being inverted with respect to one another; whereby each of the four switches to be controUed is separately modulated so that some combination of one or more switches is always closed. 4. The logic controUer of Claim 3 further comprising four OR gates, each OR gate δ fed by an output from the polarity detector through a turn off delay and by an output from the duty cyde modulator through a turn on delay, such that first and third OR gates each receive as a first input a first output from the polarity detector, and second and fourth OR gates each receive as a first input a second output from the polarity detector; and such that first and second OR gates receive as a second input a first output 10 from the duty cyde modulator, and third and fourth OR gates receive as a second input a second output from the duty cyde modulator; whereby output from each OR gate controls one switch. δ. A method of switching an input voltage by variable duty cycle modulation lδ comprising the steps of: a. Sensing in real time a polarity and an ampUtude ofthe iiφut voltage; b. Varying the duty cycle of a modulator in accordance with the desired modification of the ampUtude, the modulator having inverted outputs; c. Feeding a polarity signal and a duty cyde signal to an OR gate each by 0 way of a controllable delay; d. Using the OR gate output to control a switching device for the variable duty cyde modulation. 6. The method of Claim δ wherein steps a - d are iterated separately for each of four δ OR gates. 7. The method of Claim δ wherem said step of variable duty cycle modulation switching of the input voltage includes modulating the switching during operation so that aU of the switches in the controUer ofthe invention are not ever electrically non- 0 conducting at the same time. 8. A variable power factor corrector comprising: a. a power factor capadtor in paraUel with a load on an AC Une; and b. a line driven variable voltage output in series with the capadtor for 5 varying the amount of capadtance reflected back onto the AC line; δl wherein the variable voltage output is implemented in a power controUer for regulating an AC input voltage, the controUer comprising a circuit comprised of a four switches and an inductor; the controUer further comprising logic control having a polarity detector in δ paraUel with the input voltage, the polarity detector having two outputs; and a duty cyde modulator having two outputs; each of the outputs of the polarity detector and ofthe duty cycle modulator being inverted with respect to one another; whereby each switch is separately modulated so that some combination of one or more switches is always dosed. 10 9. The power factor corrector of Claim 8 further comprising: a current sensor in series with a load on the AC Une; a phase deby detector that receives voltage input from the AC Une and current sense input from the current sensor; lδ a power factor error amplifier fed by an output of the phase delay detector, the amplifier feeding a signal to the power controUer logic control; whereby a selected power factor correction may be automaticaUy maintained. 10. The power factor corrector of Claim 9 further comprising: 20 a second current sensor in series between the power controller and the power fador capadtor; a harmonic error ampUfier fed by an output of the current sensor, the amplifier feeding a signal to the power controUer logic control for auto resonance suppression and harmonic dampening. 25 11. The power factor corredor of Claim 8 further comprising: a pluraUty of capacitors and a pluraUty of power controUers for variable power factor correction in a three phase AC system, a first power controUer in paraUel between a first AC Une and a third AC Une, and a second power controller in paraUel between a 30 second AC Une and a third AC Une; and a first capacitor connected between an output of the first power controller and the third AC line, a second capacitor connected between an output of the second power controUer and the third AC Une, and a third capacitor connerted between an output of the first power controUer and an output ofthe second power controUer. 35 12. A method of power fador corredion comprising the steps of: reflecting a continuously variable capadtance onto a power Une to correct power factor, said capadtance variable by means of a voltage from the power line varied by a variable duty cyde modulation comprising the steps of: 5 a. Sensing in real time a polarity and an ampUtude of the iiφut voltage; b. Varying the duty cyde of a modulator in accordance with the desired modification ofthe ampUtude, the modulator having inverted outputs; c. Feeding a polarity signal and a duty cycle signal to an OR gate each by way of a controllable delay; 10 d. Using the OR gate output to control a switching device for the variable duty cyde modulation. 13. The method of Claim 12 further comprising, ahead of the step of refleding a variable capadtance, the steps of: lδ a. Sensing in real time an ampUtude of current on the power line; b. Deteding phase delay of current relative to voltage on the power line in conjunction with the current sense; c. Amplifying an output of the phase delay detedion step; d. Controlling a power factor corredion power controUer with the amplified 0 output from step three above. 14. The method of Claim 12 further comprising, ahead of the step of refleding a variable capadtance, the steps of: a. Sensing in real time an ampUtude and harmonic content of current on a δ line between the power controUer and the power fador corredion capadtor; b. Amplifying an output ofthe current sense step; c. Controlling a power factor corredion power controUer with the amplified output for resonance suppression and harmonic dampening. 0 lδ. A power controller having quadrant modes based upon an input voltage and an error circuit output, whereby a positive input voltage will determine that either Quadrant I or Quadrant II wiU be employed, and whereby a negative input voltage wUl determine that either Quadrant III or Quadrant IV wUl be employed; wherein seledion of Quadrant I vs. Quadrant II or Quadrant III vs. Quadrant IV is dependent upon the 5 error circuitry. 16. The power controUer of daim ? wherein the error circuitry compares output voltage to a reference and determines both the required diredion of current flow and the required amount of modubtion by way of an error ampUtude output to maintain controUer output regulation. 17. The power controUer of claim ? further comprising a capadtor connected across an output and a return of the controUer whereby the combination of controUer and capacitor functions as a variable capadtor. 18. The power controUer of aim ? further comprising an indudor conneded across an output and a return of the controUer whereby the combination of controller and indudor fundions as a variable indudor.

Inventors: BARETICH DAVID F, WIEGAND GREGORY P, BARETICH, DAVID, F., WIEGAND, GREGORY, P.
Applicants: BARETICH DAVID F, MICROPLANET LTD, WIEGAND GREGORY P, BARETICH, DAVID, F., MICROPLANET LTD., WIEGAND, GREGORY, P.
Application year: 1996
Main classification: G05F1
IPC codes: G05F1, H02M1, H02M5