High-speed encoder

Abstract: An encoder capable of taking four bits of uncompressed data and encoding the received bits. The encoder in parallel generates one or a plurality of codes if the bits can be represented by a code or by a plurality of codes and keeps the bits that can not be represented by a code unaltered. On the following clock cycle, the unaltered bits from the previous clock cycle will be combined with a new set of four bits of data and the cumulative bits will be converted to a code if they can be represented by a code and if they can not be represented by a code, they will be stored until the next clock cycle. The process of storing the cumulative number of bits is continued until the cumulative number of bits can be represented by a code.

Description: The present invention relates to data processing, and more particularly relates to techniques for high speed encoding of data. With a growing need for faster facsimiles and faster printers, the need for faster encoders (compressors) is also growing. Typically, to transmit data electronically from one point to another, an encoder is used to compress the data prior to transmission in order to transmit less amount of data. One of the factors in transmitting the data faster is to speed up the encoder. Based on the CCITT (ITU), IBMMR and TIFF compression algorithms, the encoder, which receives the data serially, has to identify the change of color on the current line and with respect to the change of color of the previous line encode (compress) the current line data. Usually, the codes, which represent the frequent color changes on the document, slow down the decoder. In any of the above compression algorithms, a change of color encodes one code. Potentially, the change of color can occur in two consecutive bits. A sequence of these frequent changes of color will result in worst case performance, which will slow down the encoding process. This effect slows down the flow of data to the transmission system. To overcome the above problem, there is a great need for an encoder capable of encoding several bits of data in parallel. Encoding more than one bit data at each clock cycle where there is a frequent change of color complicates the encoding process. EP-A-0211611 describes an image signal coding apparatus including reference and coding line change point detection circuits, reference line shift registers, a coding line shift register, a symbol detection circuit, coding and reference line ROM tables and a code determination circuit. The coding line change point detection circuit receives a serial reference line image signal in synchronism with a serial coding line image signal. The reference line shift registers receive serial change point data in the reference line image signal and output parallel reference line change point data. The coding line shift register receives serial change point data in the coding line image signal and outputs parallel coding line change point data. The symbol detection circuit monitors output states of the reference and coding line shift registers. A run length counter counts the number of pixels between the change points in the coding line image signal. The ROM tables cooperate with the code determination circuit to code the coding line image signal in response to outputs from the symbol detection circuit and the run length counter. In accordance with a first aspect of the present invention, a method of encoding compressed image data is provided in accordance with claim 1. In accordance with a second aspect of the present invention, we provide apparatus for encoding compressed image data according to claim 4. This invention enables at least four bits of data to be encoded at each clock cycle. In one embodiment of the present invention, there is disclosed an encoder which is capable of taking four bits of uncompressed data and encoding the received data by generating an intermediate code for each color change either one code if the four bits can be represented by one intermediate code or in parallel generating a plurality of intermediate codes if the four bits can be represented by a plurality of intermediate codes and keeping the bits that can not be represented by an intermediate code unaltered. In the same clock cycle, a first code generator receives the one intermediate code if the received bits of uncompressed data can be represented by one intermediate code and converts it into one code or receives the plurality of intermediate codes if the received bits can be represented by a plurality of codes and converts them each into a code. It should be noted that hereinafter "code" shall mean either "a CCITT code, an IBMMR code or a TIFF code". In the same clock cycle, a second code generator receives the unaltered bits of uncompressed data if they can not be represented by an intermediate code and stores them. At each clock cycle the second code generator adds the stored number of bits from previous clock cycles to the four bits of uncompressed data of the current clock cycle and stores the cumulative number of bits if no intermediate codes have been generated for the given number of bits of the current clock cycle, and repeating the storing process within each clock cycle until at least a leftmost one intermediate code has been generated from the four bits of the current clock cycle and then generating one of said codes from the stored number of bits from previous clock cycles along with the leading bits corresponding to the first intermediate code of the current clock cycle. Within a clock cycle in which an intermediate code has been generated from the stored number of bits from previous clock cycles along with the leading bits of uncompressed data of the current clock cycle , the second code generator converts the cumulative number of bits into a horizontal code, If the cumulative number of bits cannot be represented by a pass code or a vertical code, and the first code generator generates a pass code or a vertical code if the cumulative number of bits can be represented by a pass code or a vertical code. Embodiments of the invention will now be described, by way of example, with reference to the accompanying drawings, in which: Figure 1 shows a block diagram of the encoder of this invention; Figure 2 shows an example of a portion of previous line data and a corresponding portion of current line data; Figure 3 shows a detailed block diagram of the encoding window of Figure 1 along with the normalizer block of Figure 1; Figure 4 shows how the registers in the encoding window receive their data from the current line and the previous line at each clock cycle; Figure 5 shows bits of data in an encoding window with respect to the starting position of that encoding window; Figure 6 shows an encoding window in which the starting position is black and also shows the same window after it has been normalized; Figure 7 shows the encoding window for the encoder A and its starting position; Figure 8 shows the encoding window for the encoder B and its starting position; Figure 9 shows the encoding window for the encoder C and its starting position; Figure 10 shows the encoding window for the encoder D and its starting position; Figure 11 shows the data in an encoding window which will be used by encoders A, B, C and D to be encoded in parallel; Figure 12 shows the color changes of the encoding window for encoder A; Figure 13 shows the color changes of the encoding window for encoder B; Figure 14 shows the color changes of the encoding window for encoder C; Figure 15 shows the color changes of the encoding window for encoder D; Figure 16 shows 16 different conditions that can occur between the encoders; Figure 17 shows a detailed block diagram of the LH code generator block of Figure 1; Figure 18 shows five different conditions on the following bits of a long code along with deltaH for each condition; Figure 19 shows a block diagram of the PVSH code generator of Figure 1; Figure 20 shows a block diagram of a code merge block; and Figure 21 shows different states of the state machine of Figure 1. In this invention, the speed of encoding is increased by designing the encoder to process four bits of data at each clock cycle. To achieve this performance, at each clock cycle, four bits of data are taken by the encoder and they are converted into a code or multiple codes depending on the color changes of the four bits. In the case that each bit has a color change, the encoder of this invention is capable of converting each bit into one code and as a result send out four codes for the received four bits. The process of receiving four bits and converting them into one to four codes and sending them out is performed in one clock cycle. The encoder of this invention utilizes four parallel encoders to produce one to four codes in one clock cycle. Referring to Figure 1, there is shown a block diagram of an encoder 10 of this invention. Intermediate block 12 of the encoder 10 receives a current line data through bus 14 and previous line data through bus 16. The intermediate block 12 contains an encoding window 18, a normalizer block 20, four encoders A, B, C and D, a miss and match block 22 and a state machine 24. The encoding window 18 ensures that all the data needed for encoding 4 bits of data is available to the encoder 10. Encoding window 18 sends the current line data and the previous line data to the normalizer block via line 19. Normalizer block 20 is utilized to invert the data both on the current line and on the previous line if the starting position is at a black data. By inverting the data, the normalizer block 20 ensures that the encoders A, B, C and D always references to a white data. This approach simplifies the encoding process since the encoders A, B, C and D need to identify only the change of color based on one reference color (white). Normalizer block 20 normalizes the data for each encoder separately based on the color of the starting position of each encoder and sends the normalized data to each of four parallel encoders A, B, C individually via lines 15, 17, 21 and 23 respectively. The parallel encoders A, B, C and D each independently encodes the received data assuming a different starting position. Each one of the encoders A, B, C and D generate an intermediate code. Intermediate codes are generated to simplify the process of parallel encoding. Each intermediate code has a fixed length of 5 bits. Each block of Figure 1 will be described in a greater detail hereinafter. The outputs of each one of encoders A, B, C and D will be sent to miss and match block 22 via lines (28 & 29), (30 & 31), (32 & 33) and (34 & 35) respectively. Depending on the number of bits encoded by the encoder A, B, C and D the miss and match block 22 will select one to four intermediate codes to be sent out in order to ensure four bits of data are being encoded at each clock cycle. The output of the miss and match block 22 could be one intermediate code icode1, two intermediate codes icode1 and icode2, three intermediate codes icode1, icode2 and icode3 or four intermediate codes icode1, icode2, icode3 and icode4. The miss and match block 22 selects only the intermediate code A or the intermediate code A along with a combination from the intermediate codes B, C and D. The miss and match block 22 sends the selected intermediate code or codes and the information about the color of each code to code generator 36 via lines 38 and 39 respectively. In parallel, code generator 36 converts icode1, icode2, icode3 and icode4 each into a code. It should be noted that for the purpose of simplicity, in Figure 1, there is shown only one line 38 which delivers the intermediate codes to the PVSH code generator 36 and only one line 39 which delivers the color of different intermediate codes to PVSH code generator 36. However, in the actual implementation of disclosed embodiment of this invention each intermediate code and its color is sent to the PVSH code generator 36 individually. At each clock cycle, if any one of the encoders A, B, C and D does not find a color change, it means that the end of that code is in one of the following clock cycles. In the same clock cycle, the unencoded bits (INTH) will be sent to the LH code generator 40 via line 42 to be stored till the next clock cycle. The end of a code might be found after many clock cycles. In the mean time, the LH code generator 40 adds the number of bits in each clock cycle to the stored number of bits from the previous clock cycle and stores the cumulative number of bits until the end of a code is found. Once the end of a code is found, depending on if the cumulative number of bits can be represented by a code, the LH code generator 40 will convert the cumulative number of bits into a long horizontal code and if they can be represented by a pass code, vertical code or a short horizontal code, the PVSH will generate a code. It should be noted that a long horizontal code is defined as a code which represents more than four bits-of uncompressed data and a short horizontal code is a code which represents a four or less bits of uncompressed data. State machine 24 ensures the encoding states on each clock cycle is transferred into the following cycle and it controls the miss and match block 22 via line 23 and the LH code generator 40 via line 86. The result from the PVSH code generator 36 will be sent to the code merge 46 via line 48 and the result from the LH code generator 40 will be sent to code merge 46 via line 50. The code merge 46 will concatenate the result from the PVSH code generator 36 and send them out. Concatenating the result from the PVSH code generator ensures that four bits of data has been encoded at each clock cycle. In order to comprehend the encoder of this invention, it is necessary to study the conventions used in CCITT algorithm. Referring to Figure 2, there is shown a portion of previous line data 53 and a corresponding portion of current line data 55. On the current line 55, a0 represents the starting position. At the start of a line, a0 is set on an imaginary white position situated just before the first element on the line. During coding of the current line 55, the position of a0 is defined by the previous coding mode. On the current line 55, a1 represents the next change of color to the right of a0. Also, on the current line 55, a2 represents the next change of color to the right of a1. On the previous line 53, b1 represents the first change of color to the right of a0 and of opposite color to a0. Also, on the previous line, b2 represents the next change of color to the right of b1. Referring to Figure 3, there is shown a detailed block diagram of the encoding window 18 of Figure 1 along with the normalizer block 20 of Figure 1. Encoding window 18 is the interface between the encoder 10 (Figure 1) and the elements outside of the encoder 10. In the Encoding window 18, there are four registers 52, 54, 56 and 58. At each clock cycle, register 52 receives four consecutive bits C1, C2, C3 and C4 of current line data. The four bits received at each clock cycle is the following four bits of the bits from the previous clock cycle. Register 54 holds one bit which indicates the a0 bit and it is denoted as C0. At the start of the scan line, register 54 is reset to zero to depict a white data. Register 56 receives seven consecutive bits P1, P2, P3, P4, P5, P6 and P7 of previous line data at each clock cycle. The seven bits received at each clock cycle is the following seven bits of the bits from the previous clock cycle. Register 58 holds one bit which indicates P0. P0 is the bit which has the same position as a0 (right above a0) on the previous line. The C0 and P0 are reset to zero at the beginning of a scan line because at the start of the current line, a0 is an imaginary position which is one position before the first bit under encoding (C1) and is regarded as a white bit. Referring to Figure 4, there is shown how the registers 52, 54, 56 and 58 receive their data from the current line and the previous line at each clock cycle. As it can be observed, after the first clock cycle the window moves forward by four bits. At the second clock cycle, the content of C4 will be loaded into register 54 and the content of P4 will be load into register 58. In the mean time, register 52 receives the next 4 bits and register 56 receives the next 7 bits. This process repeats on each clock cycle. For example, on the nth clock cycle, again the content of C24 will be loaded into register 54 and the content of P24 will be load into register 58. In the mean time, register 52 receives the next 4 bits and register 56 receives the next 7 bits. In the same manner the rest of the data from both previous line and current line will be loaded into the registers 52, 54, 56 and 58. When the encoding reaches the end of the scan line, a change of color is placed after the last bit C28 of the scan line, in order to terminate the last code of the scan line. It should be noted that for the purpose of simplicity, in Figure 4, there are 28 (C1-C28) bits on a scan line. However, an actual scan line has a greater number of bits. Referring back to Figure 3, the encoding window 18 sends out the 4 bits of current line data via line 60 and one bit representing a0 via line 62 to the normalizer block 20. Also, the encoding window 18 sends out the 7 bits of previous line data via line 64 and one bit P0 representing a bit on the previous line data above the a0 via line 66 to the normalizer block 20. The reason for having 5 bits of current line data and 8 bits of previous line data is that 4 bits on the current line is needed to be encoded. Encoder A assumes the position of a0 to be one position before the first bit (C1) under encoding. The four bits under encoding are C1, C2, C3 and C4 and C0 is the reference bit for encoding the bits C1, C2, C3 and C4. The change of color on C1, C2, C3 and C4 with respect to C0 is the enabling factor in the encoding process. Therefore, register 54 holds the C0 (a0) and register 52 holds the four bits C1, C2, C3 and C4 under encoding. On the previous line all the bits above C0, C1, C2, C3 and C4 are needed. In addition, three more bits are needed to determine if the last bit of the four bits on the current line is a vertical code. Therefore, register 58 holds P0 and register 56 holds P1, P2, p3, P4, P5, P6 and P7. The normalizer block 20 has to normalize the data based on the color of a0. Referring to Figure 5, if the content of a0 is 0 (white) the data will be kept the same. However, referring to Figure 6, if the content of a0 is 1 (black) the data for both the current line and the previous line will be inverted. The reason for inventing the data is to have one look up table for the codes. Typically, white color data has one look up table and black color data has a different look up table. The look up table for the white data contains a data which is the inverse of the data in the look up table for the black data. Therefore, if the black data is converted to the white data or the white data is converted into black data, then only one look up table will be required. Therefore, normalizing reduces the need for two tables into one table. In this invention, only one table containing the white data is used. It should be noted that the normalizing has to be done individually for each encoder. Referring to Figures 7-10, the starting position for encoder A is at C0 which is the starting position for encoder A (Figure 7). The data for encoder A should be normalized with respect to C0. The starting position for encoder B is at C1 (Figure 8) and the data should be normalized with respect to C1. The starting position for encoder C is at C2 (Figure 9) and the data should be normalized with respect to C2. The starting position for encoder D is at C3 (Figure 10) and the data should be normalized with respect to C3. It should be noted that throughout this specification of this embodiment, every time notations C0, C1, C2, C3, C4, P0, P1, P2, P3, P4, P5, P6 and P7 are used, Figure 7 can be used to identify the position of each notation. Referring back to Figure 1, after the data is normalized for each encoder, the normalized previous line data and the normalized current line data will be sent to each of four encoders A, B, C, D via lines 28, 30, 32 and 34 respectively. Each one of the encoders A, B, C and D is a look up table. The encoders A, B, C and D assign a global intermediate format of 10000 to the pass codes and a 00XXX intermediate format to the vertical codes in which the three least significant bits (XXX) represent the position of a1 with respect to b1. For example, XXX=111 represent VL3 which means that a1 is located 3 bits to the left of b1. Each one of the encoders also assigns a 010XX intermediate format to the leading code of a short horizontal code and 011XX intermediate format to the trailing code of a short horizontal code. The two least significant bits of a leading code (XX) of a short horizontal code represent the relative distance between a0 and a1 and the two least significant bits of a trailing code (XX) of a short horizontal code represent the relative distance between a1 and a2. The encoders assign a dummy intermediate format of 11111 to a code that its end has not been found in order to notify the miss and match block 22 that a code has not been generated. It should be noted that in a horizontal code, a leading code is a0a1 (the distance between a0 and a1) and a trailing code is a1a2 (the distance between a1 and a2). It should also be noted that each one of the leading code or the trailing code can have either have one portion called terminating code or two portions called terminating code and makeup code. Having just a terminating code or a terminating code along with a makeup code depends on the number of the bits being represented by the leading code or the trailing code. If the number of bits being represented by either a leading code or a trailing code is less than or equal to 63 bits, then only a terminating code will be sent out. However, if the number of bits being represented by either a leading code or a trailing code is more than 63 bits, then a terminating code and a makeup code will be sent out. Referring to Figures 7, 8, 9 and 10 there are shown encoding window and position of a0 on each encoder. Referring to Figure 7, the encoder A has a0 at C0 position and needs all 13 bits to encode. Referring to Figure 8, encoder B has a0 at C1 position and needs 11 bits to encode. Encoder B is to make up for the condition when encoder A encodes only one bit. Referring to Figure 9, encoder C has its a0 at C2 position and needs 9 bits. Encoder C is to make up for the condition when either encoder A encodes only two bits or both encoder A and encoder B encode only one bit. Referring to Figure 10, encoder D has its a0 at C3 position and needs only 7 bits. Encoder D is to make up for the condition when encoder A, encoder A and B or encoder A, B and C encode three bits. It should be noted that the encoder A uses 8 bits of previous line data and five bits of current line data (Figure 7). However, encoder B uses 7 bits of previous line data and 4 bits of current line data (Figure 8), encoder C uses 6 bits of previous line data (Figure 9) and 3 bits of current line data and encoder D uses 5 bits of previous line data and 2 bits of current line data (Figure 10). It should be noted each encoder, along with the intermediate code, will send out the color of its starting position. The color of the starting position determines the color of that intermediate code. Therefore, referring back to Figure 1, colorA, colorB, colorC and colorD are sent to the miss and match block via lines 29, 31, 33 and 35. Figures 11,12, 13, 14 and 15 show an example of parallel encoding. It should be noted that for the purpose of simplicity, the positions C0-C4 and P0-P7 are only shown in Figure 11. However, it should also be noted that the positions C0-C4 and P0-P7 in Figure 12-15 are the same as the positions C0-C4 and P0-P7 of Figure 11. As it can be observed, since the encoding window (Figure 11) is at the start of the scan line, a0 is reset to 0 which depicts a white data. With the encoding window of Figure 11, encoder A finds a color change (as shown in Figure 12) on the current line data on bit C3 and a color change on the previous line on P5. Since b1 on the previous line is on P5, the code is a vertical code (VL2). Since the color change is on C3, the encoder A has encoded three bits. While encoder A is encoding the data from encoding window of Figure 11, encoders B, C and D are also encoding the data from the encoder window of Figure 11. Referring to Figure 13, encoder B encodes the data from the encoding window of Figure 11 by placing a0 on C1. Encoder B, finds a color change on the current line data on bit C3 and a color change on the previous line on P5. Since b1 on the previous line is on P5, the code is a vertical code (VL2). Referring to Figure 14, encoder C encodes the data from the encoding window of Figure 11 by placing a0 on C2. Encoder C, finds a color change on the current line data on bit C3 and a color change on the previous line on P5. Since b1 on the previous line is on P5, the code is a vertical code (VL2). Referring to Figure 15, encoder D encodes the data from the encoding window of Figure 11 by placing a0 on C3. However, since the data in C3 is black (1) the current line and the previous line have to be normalized. Encoder D finds a a color change on the current line data on C4 and a color change on the previous line on P7 and since b1 is on P7, the code is a vertical code (VL3). Since encoder A has encoded 3 bits, the result from encoders B and C will be ignored. However, the result from encoder D is needed. In this example, the result from encoder A along with the result from encoder D will be sent out. The result from encoder A could be a vertical code, a pass code or a part of the horizontal code. The result from encoder B could be a vertical code, a pass code or a horizontal code which has three or less bits. The result from encoder C could be a vertical code, a pass code or a short horizontal code which has two or less bits. The result from encoder D could be a vertical code or a short horizontal code which has only one bit. The result from encoder D can not be a pass code since a pass code needs a minimum of two bits. Referring to Figure 16, there is shown 16 different conditions that can occur between the encoders. For example, the first condition shows that the Encoder A finds no color change in any of the four bits. Zero on the table represents the condition that there is no code found. As another example, condition 2 shows that Encoder A encodes all four bits. This means that the first color change is on the last bit C4. Condition 3 shows that Encoder A encodes 3 bits, but encoder D finds no code. In which case, the unencoded bit from encoder D will be sent to LH code generator 40 (Figure 1) to be stored and the result from encoder A will be sent to PVSH code generator 36 (figure 1). As yet another example, condition 8 shows a condition in which encoder A encodes 2 bits. As a result, the result from encoder C will be needed. However, encoder C has encoded only one bit. Therefore, the result from encoder D is also needed. In this condition 8, the result form encoder A, C and D will be sent out. It should be noted that when it is mentioned that there is no code found (shown as 0 on the table of Figure 15), it means that there is no change of color in the data stream. When there is no change of color, it means that the data is a part of a code which will terminate at the following clock cycle. Therefore, the following bits after C4, which will be available in the next clock cycle, are needed in order to encode the bits from the current clock cycle. It should be noted that a code, which its data is partially in the encoding window of one clock cycle and partially in the encoding window of the following clock cycle, can be a pass code, a vertical code, a short horizontal code or a long horizontal code. It should also be noted that the miss and match block 22 is the implementation of the table shown in Figure 16. Referring back to Figure 1, the Miss and match block 22, observes the number of bits encoded in each encoder and selects only the output of encoder A or the output of encoder A in combination with the output of one or two or three of the encoders B, C or D. If encoder A encodes 4 bits, the result from encoder B, C and D will be ignored. If encoder A encodes 3 bits, the next a0 position will be three bits away from the current a0. Therefore, the result from encoder D will be combined with result from the encoder A since a0 of encoder D which is at C3 (Figure 10) is three bits away from the a0 of encoder A which is at C0 (Figure 7). The encoder D provides the one bit necessary to be added to the three bits from the encoder A to ensure four bits of data being encoded in one clock cycle. For the extreme case when each encoder encodes only one bit, the result from all four encoders are integrated together. It should be noted that the miss and match block 22 selects the intermediate code along with their colors. Referring to Figure 1, the miss and match block sends the outputs of encoders A, B, C and D via line 38 along with their colors color1, color2, color3 and color4 via line 39 to the short code decoder 36. However, it should be noted that the miss and match block can send the output of encoder B, C and D on icode2 and color2, the output of encoders C and D on iocde3 and color3 and only the output of the encoder D on icode4 and color4. For example, if encoder A has used 2 bits of data, then the result from encoder A should be combined with the result from encoder C or encoders C and D. In this case, the result from encoder A will be sent on icode1 and its color on color1 and the result from encoder C will be sent on icode2 and its color on color2 and depending on if the result from encoder D is needed, it will be sent on icode3 and its color on color3. As and alternative example, if encoder A uses 3 bits of data, then the result from encoder A should be combined with the result from encoder D. In this case, the result from encoder A will be sent on icode1 and the result form encoder D will be sent on icode2. It should be noted that if encoder A or one of the encoders B, C and D does not find a color change, the number of unencoded bits have to be stored in a register in LH code generator 40 in order to be combined with the following bits. The number of unencoded bits will be sent from the miss and match block 22 to the LH code generator 40 via INTH 42. At each clock cycle, if any one of the encoders A, B, C and D does not find a color change, it means that the end of that code is in one of the following clock cycles. In the case that one of the encoders B, C and D does not find a color change, the intermediate code or the intermediate codes from the encoder or encoders prior to the encoder that could not find a color change will be sent to PVSH code generator 36 and in the same clock cycle, PVSH code generator 36 converts the intermediate codes each into a code while the unencoded bits will be stored in LH code generator 40. If encoder A does not find a color change, then all the unencoded bits (C1-C4) will be stored in LH code generator 40 and the PVSH code generator 36 will be inactivated. on the following clock cycle, the code generator 40 combines the stored number of unencoded bits from a previous clock cycle with the number of bits from of the current clock cycle and if in the four bits of the current clock cycle a color change is not detected, it means that the end of the code is in one of the following clock cycles. In this case, the LH code generator 40 has to store the cumulative number of unencoded bits from the previous clock cycle to the number of unencoded bits from the current clock cycle. The process of storing the cumulative number of unencoded bits and combining them with the following bits and storing the new combination has to be continued until the end of the code is detected. Once the end of a code is detected, if the code happens to be a pass code or a vertical code, the number of count in the count register 80 will be discarded since a pass code and a vertical code can be defined by a code and the data on the previous line without having the actual count for the number of bits. However, if the code is a long Horizontal code, the count from the LH generator 40 has to be used for the count of the long horizontal code. It should be noted that once the end of a code is detected and it happens to be a pass code or a vertical code, then the miss and match block 22 will send an intermediate pass code or an intermediate vertical code respectively as icodel to PVSH code generator 36 and PVSH code generator 36 generates a pass code. Referring to Figure 17, there is shown the LH generator block 40. Every time there is an undetected code in the encoding window, the number of the unencoded bits INTH 42 will be stored in the H count register 80. The output of H count register 80 is sent to Adder 82 via line 84. The adder 82 also receives a deltaH (the number of encoded bits) via line 86 which comes from the state machine 24. On the next cycle, if a code is found, the adder 82 will add deltaH (the number of encoded bits of the current clock cycle) to the number from the H counter register 80 in order to generate an H value (length of the long horizontal code) which will be sent to Hvalue register 86 via line 88 to be stored in the Hvalue register 86. It should be noted that the Hvalue is defined as the length of the long horizontal code since it will be used only if the code is a long horizontal code. Once the end of a code is found, at the start of the following clock cycle, the H count register 80 will be reset and if there are unencoded bits on that clock cycle, the H count register 80 will store the INTH 42 (unencoded bits) from the miss and match block 22 However, if on the following clock cycle there is no code detected, the adder 82 will add a delatH equal to 4 to the number from the H count register 80. In this case, the H value will not be available to Hvalue register 86. Therefore, the output of the adder 82 will not be stored in the Hvalue register. Instead, the output of the adder 82 will be sent to H count register 80 via addedH 90 to be stored in the H count register 80. The Hvalue from the Hvalue register 86 will not be used until the end of the code is detected. In summary, if no code is generated on a particular clock cycle, on the next clock cycle, the H count register 80 will store a new value delivered by addedH 90. However, if a code is generated on a particular clock cycle, on the next clock cycle, the INTH will be stored in the Hcount register 80 and if there are no unencoded bits, then INTH will be 0 which will set the Hcount register 80 to zero. If in one clock cycle, unencoded bits are stored, then on the following clock cycle, the following bits can have one of the conditions shown on Figure 18. Referring to Figure 18, there are shown five different conditions on the bits following the unencoded bits from the previous clock cycle along with deltaH for each condition. In Figure 18, C represents a color change and N represents no color change and X is don't care (ignore). As it can be observed, in condition 1, since the color change is on bit C1, only one bit is encoded and therefore deltaH is 1. In condition 2, since the color change is on bit C2, two bits are encoded and therefore deltaH is 2. In condition 3, since the color change is on bit C3, three bits are encoded and therefore deltaH is 3. In condition 4, since the color change is on bit C4, four bits are encoded and therefore deltaH is 4. However, in condition 4 there is no color change, but since all four bits are considered in the encoding process, deltaH is 4. Referring back to Figure 17, it should be noted that for the first cycle, -1 will be loaded to the H counter register 80 since the position of P0 is an imaginary position which is one position before the first position to compensate for the extra bit generated by the imaginary position of a0. Once the end of a code is detected, if it happens to be a long horizontal code, then the H value form the Hvalue register 86 will be used to generate a long horizontal code. The Hvalue register 86 sends the Hvalue to Hvalue definer 92 via line 94. Hvalue definer 92 will determine if the Hvalue is less than or equal to 63 in which case it sends out an enabling signal HVL63 to both path a and path b via line 96. If H value definer 92 determines that H value is more than 63, then it will send an enabling signal HVG63 to both path a and path b via line 98. It should be noted that once the end of a code is detected, if the code happens to be a pass code or a vertical code, the Hvalue will not be available to the Hvalue register 86. For a long horizontal code, the Hvalue will be divided into two parts. The 6 least significant bits (bits 0 to 5) will be sent to path a and the remaining bits (bit 6 and above) will be sent to path b. Path a which contains two look up tables 102 and 106 for terminating codes will be used for the first 63 bits and path b which contains two look up tables 104 and 108 for makeup codes will be used for the remaining value of Hvalue above 63. Each path has a white look up table 102 (path a) and 104 (path b) and a black look up table 106 (path a) and 108 (path b) . Therefore, in each path two codes; one for the black and one for the white will be generated. However, depending on the color of each code, the appropriate code will be selected. Each table sends out a code and its count. In path a MUX (multiplexer) 110 selects the white code 112 and white code count 114 or the black code 116 and black code count 118. Color 119 which comes from the miss and match block 22 controls the selection of the MUX 110. In path b MUX 210 selects the white code 212 and white code count 214 or the black code 216 and black code count 218. Color 119 also controls the selection of the MUX 210. Therefore, the MUXs 110 and 210 each provide a code and count for that code. MUX 110 sends out a Tcode as a terminating code via line 220 and Tcount (terminating code count) via line 222 to code merge block 46 and MUX 210 sends out a Mcode as a makeup code via line 224 and Mcount (makeup code count) via line 226 to code merge block 46. If the Hvalue is equal or less than 63, only path a will be activated by HVL63 96. However, if the Hvalue is more than 63, then both path a and path b will be activated by HVG63 98. It should be noted that if the Hvalue is more than 2560, a 2560 code will be sent out and 2560 will be subtracted from the Hvalue and if the Hvalue is still greater than 2560, another 2560 code will be sent out. However, if after the subtraction, the the Hvalue is less than 2560 a proper code will be sent out. Referring back to Figure 1, the intermediate codes from encoders A, B, C and D will be sent to PVSH code generator 36. Block 36 is called PVSH code generator since it converts the intermediate codes for the pass codes, vertical codes and short horizontal codes. Referring to Figure 19, there is shown a block diagram of the PVSH code generator 36. In the PVSH code generator 36, there is one look up table for each individual encoder. Look up table 230 receives the icode1 via line 232, look up table 234 receives the icode2 via line 236, look up table 238 receives the icode3 via line 240 and look up table 242 receives the icode4 via line 244. The icode1, icode2, icode3 and icode4 are sent to the PVSH code generator 36 from the miss and match block 22. Each look up table contains the actual codes for pass code, vertical codes and short horizontal codes. Each look up table sends out the actual code with count for the number of bits of that code. Look up table 230 sends out code1 via line 246 and its count via line 248, look up table 234 sends out code2 via line 250 and its count via line 252, look up table 238 sends out code3 via line 254 and its count via line 256 and look up table 242 sends out code4 via line 258 and its count via line 260. The codes and the counts from the PVSH code generator 36 will be sent to the code merge block 46 (Figure 1). Referring back to Figure 1, the results from the PVSH code generator 36 and the LH code generator 40 will be sent to the code merge block 46. Referring to Figure 20, there is shown a block diagram of a code merge block 46. The code merge block 46, receives four codes with their counts from the PVSH code generator 36 and two codes with their counts from the LH code generator 40. MUX 270 will select either code1 246 and count1 248 with its count from the PVSH code generator 36, Tcode 220 and Tcount 222 or Mcode 224 and Mcount 226 from the LH code generator 40. Select 100 which is sent from the state machine 24 controls the selection of the MUX 270. If select 100 is 0, then codel 246 and its count 248 will be selected. However, if select 100 is 1 then depending on if a terminating code is needed, Tcode 220 and Tcount 222 will be selected and if a makeup code is needed, Mcode 224 and Mcount 226 will be selected. Furthermore, if the Tcode 220 or Mcode 224 with their counts 222 and 226 are selected, a heading of 001 which is the indicator of a horizontal code has to be added to the beginning of the codes and therefore, a number 3 representing the number of bits in the header (001) should be added to the count of the horizontal code. This is accomplished by the adder block 272 and the Add header block 274. The selected code from MUX 270 will be sent to both the Add header block 272 and MUX 276 via lines 278 and 280 respectively. Add header block 272 adds the header to the selected code. The result from the Add header block 272 will also be sent to MUX 276 via line 282. In the same manner, the selected count from MUX 270 will be sent to both MUX 284 and Adder block 274 via lines 286 and 288. Adder block 274 will add 3 to the count and the result will be sent to MUX 284 via line 290. Select 100 will control the selections of MUX 276 and MUX 284. If select is 0, then MUX 276 will select the code from MUX 270 and MUX 284 will select the count from MUX 270. However, if select = 1, then MUX 276 will select the output 282 of the Add Header 272 and MUX 284 will select the output 290 of Adder 274. The output 292 of the MUX 272 is either code1 or long horizontal code and the output 294 of the MUX 284 is the either count for code1 or count for long horizontal code respectively. The code merge block 46, shifts code2, code3 and code4 in order to place them one after the other. Code3 will be shifted by Shifter 300. Shifter 300 shifts code3 by the number of the bits in code2. In other words, Shifter 300 receives count2 via line 252 and code3 via line 254 and shifts code3 by the number on count2. Shifting code3 by count2 ensures that when the codes are placed serially, they don't overwrite each other. Then code4 will be shifted by Shifter 302. Shifter 302 shifts code4 by a number equal to the count of code2 and code3. Adder 304 receives both count2 and count3 via lines 252 and 256 respectively and adds them together and delivers the result count23 to Shifter 302 via line 306. Shifter 302 uses count23 which is the addition of Count2 and count3 to shift code4. Again, this is done to ensure that when the codes are placed serially they precisely follow each other. Merge block 308, receives code2, shifted code3 and shifted code4 via lines 250, 310 and 312 respectively and places them serially. Control block 314 receives count2 252 and the result 316 of Adder 304 and generates a signal 318 to control the Merge block 308. Control block 314 generates a mask to select code2, code3 or code4 or a combination of them depending on the number of bits of code1. Finally, Shifter 320 shifts the result 322 of the Merge block 308 by the number of the bits on code1 (count1 248). The result 324 of the Shifter 320 will be sent to the Merge block 326. Merge block 326, which also receives code1 246, places code1 and result 324 of shifter 320 serially. If all of code2, code3 and code4 are used, the result 324 of shifter 320 will be code2, code3 and code4 one after the other. In this case the result 328 of Merge block 326, will be code1, code2, code3 and code4. Therefore, the result of Merge 326 will always be code1 with any combination of code2, code3 and code4 Control block 330 receives count1 248 to generate a control signal 232 for Merge block 326. Control block 330 generates a mask to select code1 alone or code1 with a combination of code2, code3 and code4. Adder 334, receives count23 316 and count4 260 and adds them together to generate count234 336. Adder 338 receives count234 336 and count1 248 and adds them together to provide the count 340 for all the codes. When the end of a code is detected, along with that code, a combination of code2, code3 and code4 can also be sent out depending on if that code ends on the C1, C2 or C3 of the encoding window. Referring to Figure 21, there is shown the state machine 24 which serves to pass the encoding status from current clock cycle to the next clock cycle. State machine 24 is designed for three states: normal state 400, trailing state 402 in which the trailing horizontal code of the two dimensional coding is expected and b1 states 404 and 406 in which the change of color on the previous line is detected, but no change of color is detected on the current line. The state machine 24 is reset to normal state 400 at the beginning of a scan line. When condition 410 occurs, it means that there is no code found, as in case 5 of Figure 15. In this condition 410 the state machine stays at the normal state 400 and a deltaH equal to 4 will be added to the adder 82 of the LH code generator 40 (Figure 16). Condition 410 is shown as no a1 no b1. When condition 412 occurs, it means that there is a pass code, a vertical code or a pair of codes representing the leading code and trailing codes of a horizontal code. In this condition 412 the state machine 24 stays at the normal state 400 and the horizontal count register 80 (Figure 16) receives INTH 42. At the same time, the output 88 of the adder 82 will be loaded into the Hvalue register 86. Condition 412 is shown as found a1, b1 or b2 ( vertical code or pass code). When condition 414 occurs, it means only the leading code of a horizontal code is detected, the state of the state machine is changed to trailing state 402. Condition 414 is shown by found a1 and b1 therefore there is a H (horizontal) code. Once the state machine enters into this state 402, it will stay in this state until the end of the horizontal code is detected and then it will return to normal state 400. The condition shown by 416 shows that a1 is found meaning that the end of horizontal code is found and the state machine returns to normal state 400. In this state 402, if condition 418 happens, it means that no code is found (no a1). Therefore, a deltaH equal to 4 will be added to the adder 82 of the LH code generator 40 (Figure 16). State b1, which is shown as two states b1(4) 406 and b1(123) 404, is a state in which the change of color (b1) on previous line is detected, but the change of color on the current line (a1) is not found. The position of b1 is important since it can determine whether the code at the next cycle is a VR1, VR2, VR3, a pass code or a horizontal code. State b1 (1) is defined as b1 at position P4 in which the code at the next cycle could a VR2, VR3, a pass code or a horizontal code. State b1 (2) is defined as b1 at position P3 in which the code at the next cycle could be VR3, a pass code or a horizontal code. State b1 (3) is defined as b1 at position P2 in which the code at the next cycle could be a pass code, a vertical code or a horizontal code. State b1 (4), which is defined as b1 at position P1, has ruled out all VR codes and it can only be either a pass code, or a horizontal code. In normal state 400, if condition 420 occurs, it means that b1 has been found and b1 is on either P2, P3 or P4, but a1 is not found. This condition 420, takes the state machine 24 into b1(123) state 404. Once the state machine enter into state 404, if condition 420 occurs, it means b2 is found and therefore there is a pass code. This condition 420 returns the state machine to normal state 400. At the same time, the horizontal count register 80 (Figure 16) receives INTH 42. In b1 (123) state 404, if condition 424 occurs, it means that a1 has been found and a1 is not more than 3 bits away from b1 and therefore there is a vertical code. This condition 424 returns the state machine to normal state 400. At the same time the horizontal count register 80 (Figure 16) receives INTH 42. In b1 (123) state 404, if condition 426 occurs, it means that a1 has been found and a1 is more than 3 bits away from b1 and therefore there is a horizontal code. This condition 426 takes the state machine to trailing state 402. At the same time, the horizontal count register 80 (Figure 16) receives INTH 42. In b1 (123) state 404, if condition 428 occurs, it means that no a1 and no b2 has been found and therefore the state machine moves to b1(4) state 406. At the same time, a deltaH equal to 4 will be added to the adder 82 (Figure 16). In normal state 400, if condition 430 occurs, it means that b1 has been found and b1 is on either P1, but a1 is not found. This condition 430, takes the state machine 24 into b1(4) state 402. Once the state machine enter into b1 (4) state 402, if condition 432 occurs, it means a1 is found and since a1 is more than 3 bits away from b1, there exists a horizontal code. This condition 432 takes the state machine 24 to trailing state 402. At the same time the horizontal count register 80 (Figure 16) receives INTH 42. In b1 (4) state 406, if condition 434 occurs, it means that no a1 and no b2 has been found and therefore the state machine stays in b1(4) state 406. At the same time, a deltaH equal to 4 will be added to adder 82 of the LH code generator 40 (Figure 16). In b1 (4) state 406 , if condition 436 occurs, it means that b2 has been found and therefore the state machine returns to normal state normal. At the same time, the horizontal count register 80 (Figure 16) receives INTH 42. The disclosed encoder of this invention is capable of encoding with both one dimensional and two dimensional CCITT algorithms and also with IBMMR and TIFF algorithms.

Claims: A method for encoding uncompressed image data based on one of the CCITT, IBMMR and TIFF compression algorithms and the corresponding codes, the method comprising: a. within a clock cycle, receiving a given number of at least two bits of uncompressed data and generating one or more intermediate codes for as many of the leading bits of said given number of bits which can be represented by a corresponding number of one or more of said codes and keeping unaltered the remainder of said given number of bits from which an intermediate code was not generated, the intermediate codes having a common, fixed length and each corresponding to a respective one of said codes; b. within the same clock cycle, converting the or each intermediate code into a respective one of said codes; c. within the same clock cycle, storing any unaltered bits of uncompressed data if they can not be represented by one of said codes; d. within a clock cycle, adding the stored number of bits from previous clock cycles to the given number of bits of uncompressed data of the current clock cycle and storing the cumulative number of bits if no intermediate codes have been generated for the given number of bits of the current clock cycle, and repeating the storing process within each clock cycle until at least a leftmost one intermediate code has been generated from the given number of bits of the current clock cycle and then generating one of said codes from the stored number of bits from previous clock cycles along with the leading bits corresponding to the first intermediate code of the current clock cycle; e. within a clock cycle in which an intermediate code has been generated from the stored number of bits from previous clock cycles along with the leading bits of uncompressed data of the current clock cycle, converting the cumulative number of bits into a horizontal code, if the cumulative number of bits cannot be represented by a pass code or a vertical code; and f. generating a pass code or a vertical code if the cumulative number of bits can be represented by a pass code or a vertical code. The method as recited in claim 1, further comprising the step of concatenating said code or codes generated by step b. The method as recited in any of the preceding claims, wherein the given number bits of uncompressed data is four, and/or said plurality of intermediate codes comprises two, three or four intermediate codes. An apparatus for encoding uncompressed image data based on one of the CCITT, IBMMR and TIFF compression algorithms and the corresponding codes, the apparatus comprising: converging means (18,20,A-D) for, within a clock cycle, receiving a given number of at least two bits of uncompressed data and generating one or more intermediate codes for as many of the leading bits of said given number of bits which can be represented by a corresponding number of one or more of said codes and keeping unaltered the remainder of said given number of bits from which an intermediate code was not generated, the intermediate codes having a common, fixed length and each corresponding to a respective one of said codes; a first code generator (36) operably connected to said converting means; within the same clock cycle, said first code generator (36) converting the or each intermediate code into a respective one of said codes; a second code generator (40) operably connected to said converting means; within the same clock cycle, said second code generator receiving any unaltered bits of uncompressed data if they can not be represented by one of said codes and storing them; within a clock cycle, said second code generator (40) adding the stored number of bits from previous clock cycles to the given number of bits of uncompressed data of the current clock cycle and storing the cumulative number of bits if no intermediate codes have been generated for the given number of bits of the current clock cycle, and repeating the storing process within each clock cycle until at least a leftmost one intermediate code has been generated from the given number of bits of the current clock cycle and then generating one of said codes from the stored number of bits from previous clock cycles along with the leading bits corresponding to the first intermediate code of the current clock cycle; within a clock cycle in which an intermediate code has been generated from the stored number of bits from previous clock cycles along with the leading bits of uncompressed data of the current clock cycle, said second code generator converting the cumulative number of bits into a horizontal code, if the cumulative number of bits cannot be represented by a pass code or a vertical code; and said first code generator (36) generating a pass code or a vertical code if the cumulative number of bits can be represented by a pass code or a vertical code. The apparatus as recited in claim 4, further comprising means for concatenating said code or codes generated by said first code generator (36). The apparatus as recited in claim 4 or claim 5, wherein the given number bits of uncompressed data is four bits, and/or said plurality of intermediate codes comprises two, three or four intermediate codes.

Inventors: KAO JEAN-SWEY, ONG DANNY T, SU SAM S, KAO, JEAN-SWEY, ONG, DANNY T., SU, SAM S.
Applicants: XEROX CORP, XEROX CORPORATION
Application year: 1996
Main classification: G06T9
IPC codes: H03M7, G06T9, H04N1