IMPROVED TEST AND ASSEMBLY APPARATUS

Abstract: An integrated test and placement device for testing partial memory circuits and loading the said partial memory circuits onto a memory module such that the partial memory circuits are matched according to some predetermined criterion. The device preferably using a single axis to locate the partial memory circuits.

Description: Improved Test and Assembly Apparatus This invention relates to the testing and assembly of electronic components such as semiconductor memory devices. It finds particular application in the production of Single In-line Memory Modules (SIMMs) composed of partial DRAM (Dynamic Random Access Memory) circuits. A worldwide demand for SIMMs combined with the inability of memory manufacturers to supply sufficient quantities of perfect DRAM circuits has ensured that using partial DRAM circuits in SIMMs is an attractive proposition. Partial DRAM circuits are circuits containing some defective memory locations. Usually, however, only a small proportion of the memory cells are defective: this makes memory cell replacement schemes using partial DRAM circuits viable. Incorporating partial memory circuits into SIMMs requires a few additional production steps to those used in producing SIMMs with perfect circuits. Previously, these additional steps were performed manually. The present invention seeks to provide a more automated route for producing a SIMM composed of partial memory circuits. Thus the present invention provides an integrated test and placement device for testing partial memory circuits and loading the partial memory circuits on to a memory module so that the partial memory circuits are matched according to some predetermined criterion. The current procedure for producing a SIMM with partial memory circuits is generally as follows: The partial memory circuits arrive as packaged parts which need to be tested to ensure that they are within the required specification. This testing stage is to ensure that there are no memory circuits with catastrophic failures, for example one half of the cells on a partial circuit being defective. Any partial circuits with more than the maximum number of failures that a particular memory replacement scheme can cope with is rejected. The rest of the partial memory circuits are accepted for the next stage and transferred to tubes for transportation. The next stage is called the "active burn-in" stage. The memory circuits are baked in an oven for a certain time (typically from one to three days) during which time the memory circuits are exercised. The conditions of the baking (for example oven temperature, the use of temperature cycling) and the manner in which the memory circuits are exercised may vary from process to process. This stage is needed to ensure that all defects are brought to light, even those that are only observable under conditions of stress (for example due to high temperature or temperature cycling). Once the "active burn-in" stage is complete the memory circuits are again loaded into tubes and transferred to the next stage of the process. Full characterisation of the memory circuits occurs after the "active burn-in" stage. Full characterisation is the stage which locates and records all of the faults on each memory circuit. Usually, at this stage the partial memory circuits are arranged into groups or sets, each set representing the partial memory devices needed for a complete SIMM. It is important that the contents of these sets is not varied because memory replacement schemes cannot cope with certain fault coincidences. This is taken into account in the algorithm used in creating these sets. Therefore these sets of memory circuits are either loaded into individual tubes or some other type of container to keep them separate or are individually marked to enable them to be recognised. The next stage in the process is to mount the partial memory circuits from these sets onto SIMMs. All of the partial memory circuits in a set are mounted onto a SIMM. Hitherto this was done by a separate, standard automated pick-and-place machine. Once the partials from a set are mounted onto a SIMM then the faulty locations on the partials are programmed into a memory replacement controller. The final stage is to test the SIMM to ensure that it works perfectly. According to the present invention there is provided apparatus for the automatic testing and placement of electronic components comprising delivery means to supply a succession of components to a testing station, testing means for successively testing said components and for storing the results of testing each successive component, second delivery means to supply a succession of mounting means to a mounting station and transport means sequentially to transport components from said testing station to said mounting station wherein said testing means includes inhibiting means to prevent the mounting of two components having common predetermined characteristics on the same mounting means. The invention will be particularly described, by way of example, with reference to the accompanying drawings in which: Figure 1 shows a view of a test assembly station. Figure 2 shows a diagram of the moveable stage portion of the test assembly station. Referring to the drawings, Figure 1 shows a test assembly station 10 with a single axis 12 in the form of a screw thread. Mounted to this axis 12 and designed to be moved along the length of the axis is a lifter device 14 which is used to pick up and deposit memory circuits. The lifter device 14 is moved along the axis 12 by a motor 16. At the first stage of the process partial memory circuits 18 are placed in the "IN" tray 20 of the device. These partial memory devices 18 are fed through the tray 20 so that one device is presented to the lifter 14 at a time. This feeding of the partial memory devices could be done using a wedge-shaped chute or there could be an electric motor with a conveyor belt. The first stage of the process involves the lifter 14 picking up a partial memory circuit 18 from the output of the "IN" tray 20 and depositing it on a test fixture plate 22. The test fixture plate 22 may be designed so that the partial memory circuits can be tested without needing to remove the test fixture plate 22 from the test assembly station 10. The test fixture plate 22 is also moveable along a single axis; however, the single axis along which the test fixture plate 22 is moveable is perpendicular to the single axis 12 on which the lifter device 14 is mounted. The test fixture plate 22 moves in a channel 24 which is designed to allow a plate to be moved in one plane. There would usually be more than one channel 24 in an embodiment of the present invention. A control unit 26 is used to move the test fixture plate 22 back and forward to present a space for a new partial memory device on the test fixture plate 22 each time that the lifter device 14 deposits a partial memory device onto a space in the test fixture plate 22. Once the test fixture plate 22 has been filled with partial memory circuits (or according to some other predetermined criterion) then the filling process stops and either the test fixture plate 22 is removed to test the circuits 18 or the circuits are tested while they are on the test fixture plate 22. In the preferred embodiment of the present invention the circuits are tested while they are on the test fixture plate 22. This initial test is used to determine whether or not the circuits meet the required specification. If a circuit does not meet the required specification then the lifter device 14 picks up that circuit and deposits it in the waste chute 28. The next stage in the process is to send the partials 18 for the "active burn-in" stage. This is done by removing the entire test fixture plate 22 from the test assembly station 10 and placing the test fixture plate 22 with the circuits still attached into an oven to perform the necessary temperature cycling and exercising of the partials 18. Typically, all of the locations in a partial are written to logic one then they are all written to logic two. and then to logic one again, and so on. When the "active burn-in" stage has been completed then the test fixture plate 22 is returned to the test assembly station 10 for the next stage in the process, the circuit characterisation stage. At this stage each circuit is tested fully to determine all of the faulty cell locations on each circuit. Usually, when a predetermined number of partials can be combined (i.e. the circuits contain no coincident errors) to form a set then the partials which comprise that set are put into tubes. In this invention the test assembly station 10 has a second moveable plate called an assembly fixture plate 30. The assembly fixture plate 30 moves along a single axis in a similar way to the test fixture plate 22. A test unit 31 performs predetermined tests on each circuit on the test fixture plate 22 and stores information relating to the locations of faulty cells within each circuit. The assembly fixture plate 30 contains a number of printed circuit boards 32 which have been prepared so that partial memory circuits can be mounted onto them directly. The test assembly station 10 places the first partial onto the first available PCB. It then determines whether the next partial can be used on the same SIMM as the first; that is, whether there are any faulty locations in the first partial that also appear on the second partial. If there are coincident errors, or if some other predetermined criterion is not met then the second partial is placed on the next available board (the next board with no faults at the same location on the partial being placed as on the partials already mounted on that board). This process continues with each successive partial: if possible it is placed on the first board, if that is not possible then the second, if that is not possible then the third, and so on. When a board has been populated fully then a flag is set (for example a lamp) to indicate that the board should be removed and replaced with an unpopulated board. The locations of the faulty cells on each populated SIMM are recorded so that the locations can be programmed into whatever memory replacement controller is being used for the particular SIMM. In some embodiments of the present invention it is envisaged that the memory replacement controller will be programmed with the addresses of the faulty memory locations on each partial on the particular SIMM being programmed. Figure 2 shows one possible mechanism which could be used for moving the assembly fixture plate 30 and the test fixture plate 22. It is based on a rack and pinion approach. A fixture plate (either test or assembly) is attached to a toothed strip 34 via a carrier strip 36. The carrier strip 36 may contain electrical contacts to enable electrical tests to be performed on the fixture plate. The toothed strip 34 is moved by a toothed wheel 38. In other embodiments of the invention a belt drive may be used instead of a rack and pinion. An optical reader could be used to provide a reference to locate the position of the toothed strip 34 and hence the position of the fixture plates located on the toothed strip 34. It is essential to have some means of knowing the position of each fixture plate as partials have to be placed at the correct location. It will be appreciated that various modifications may be made to the above described embodiments within the scope of the present invention. For example, the test assembly station may have an arm to pick up and place the partials rather than a single axis in the form of a screw thread.

Claims: Claims 1 An integrated test and placement device for testing partial memory circuits and placing the said partial memory circuits onto a memory module such that the partial memory circuits are matched according to some predetermined criterion. 2 An integrated test and placement device according to claim 1 and arranged for producing populated Single In-line Memory Modules from partial memory circuits, said device including means for recording the locations of faulty cells in the said partial memory circuits used in each Single In-Line Memory Module. 3. Apparatus for the automatic testing and placement of electronic components comprising delivery means to supply a succession of components to a testing station, testing means for successively testing said components and for storing the results of testing each successive component, second delivery means to supply a succession of mounting means to a mounting station and transport means sequentially to transport components from said testing station to said mounting station characterised in that said testing means (31 ) includes inhibiting means to prevent the mounting of two components ( 18) having common predetermined characteristics on the same mounting means (30).

Inventors: DEAS ALEXANDER ROGER, DEAS, ALEXANDER, ROGER
Applicants: DEAS ALEXANDER ROGER, MEMORY CORP PLC, DEAS, ALEXANDER, ROGER, MEMORY CORPORATION PLC.
Application year: 1996
Main classification: H01L21
IPC codes: G11C29