FM demodulator

Abstract: In a quadrature FM detector, demodulation is performed by a product detector (18) which multiplies an amplitude limited FM modulated information signal by a version of the amplitude limited FM modulated information signal which has been phase shifted by a phase shifting network (26) including a single tuned LC circuit (32, 34). In order to assure that the LC circuit is tuned to the carrier frequency of the FM signal, the LC circuit is tuned by a variable impedance device (40) in response to a control signal generated by a bus controlled DAC (44). The control signal is coupled to the variable impedance device (40) at the same pin (42) of an integrated circuit (10) where the LC circuit is coupled to the demodulator.

Description: Frequency Modulation (FM) detection, using a so called quadrature detector, is well known. This kind of FM detector typically is a four quadrant multiplier with one input terminal driven by an amplitude limited FM modulated information signal (reference signal), and another input terminal driven with a version of the reference signal which is quadrature (90°) phase shifted relative to the reference signal using a tuned circuit including an RLC network. With a single tuned circuit, the resultant transfer characteristic of the detector, while closely approximating a straight line near the center (carrier) frequency of the modulated signal, departs from a straight line when the frequency of the FM signal deviates appreciably. Because of the wide deviation of a conventional FM broadcast signal (±75KHz), the departure from a straight line introduces harmonic distortion, particularly for louder audio signals. The slope of the phase versus frequency curve of the tuned circuit is determined by its "Q". Distortion can be reduced by lowering the "Q" but this reduces the output signal level so that a reduced signal-to-noise (S/N) ratio results. This means that the quadrature FM detector requires a linearity versus sensitivity trade-off between total harmonic distortion (THD) and S/N. Tolerances in the values of the inductance and capacitance of the tuned circuit can result in a phase versus frequency curve that is not centered at the FM carrier frequency. Although the demodulator will still function under such non-ideal conditions, less of the linear portion of the phase curve will be available and the THD will be degraded. This degradation of THD can be compensated for by lowering the "Q" of the tuned circuit. However, as stated above, the result would be to degrade S/N performance. In order to optimize THD while still maintaining a reasonably high "Q" for good S/N, an alignment of the tuned circuit is desirable so that it is accurately tuned to the FM carrier frequency. Current manufacturing processes and apparatus control systems make it desirable that such an alignment be performed electronically since the operation of currently produced apparatus, e.g., television receivers and the like, is typically bus controlled under the control of a programmed microprocessor and a PROM memory. An example of an FM demodulator of the multiplying type is described Madsen in US-A 5,453,714 entitled BINARY FM DEMODULATOR WITH SELF-ADJUSTING RESONANT OPERATING FREQUENCY ACCORDING TO DEMODULATED BINARY OUTPUT SIGNAL DUTY CYCLE which issued 26 September 1995. In this arrangement the tuned circuit for providing phase shift has a signal input line 162, a signal output line 164, a frequency control line 30g and a Vcc reference voltage line Vcc via L2. Thus, in this arrangement a total of four connections are required to be made to the tuned circuit when implementing the FM demodulator. Another example of an FM demodulator of the multiplying type is described by Ishigaki et al. in DE-A 28 31 091. In this arrangement the tuned circuit for the phase comparator has a ground reference terminal, an input terminal 10, an output terminal 16 and a control terminal 13. Altogether four terminals are required (counting ground) for coupling of the tuned circuit to the remainder of the demodulator. A further example of an FM demodulator of the multiplying type is described by Watanabe in JP-A-031208 entitled QUADRATURE WAVE DETECTION CIRCUIT which was laid open 30 March 1981. In this arrangement the tuned circuit for delaying the input signal to the multiplier includes a signal input via L1, a signal output to multiplier 2, a frequency control input via R1 and a pair of supply inputs Er and Eb. Thus total of five connections to the tuned circuit are required. In the foregoing examples, relatively large numbers of connections to the tuned circuits are required. This complicates coupling to an integrated circuit. It is an object of the present invention to reduce the number of pins required in an integrated circuit for connection of input, output and control signals to an external frequency determining circuit. A demodulator according to the present invention is defined in appended claim 1, with advantageous embodiments given by the dependend claims 2 - 5. Fig. 1 shows, partially in block diagram form and partially in schematic form, a quadrature FM detector according to aspects of the present invention. Fig. 2 is a schematic of the product detector of Fig. 1. Fig. 3 is an alternate embodiment of the product detector of Fig. 2. Referring to Fig. 1, an FM modulated information signal, which in the exemplary embodiment is the 4.5 MHz (U.S.) intercarrier sound signal of a television receiver, is coupled to input terminal pin 14 of integrated circuit (IC) 12. This FM modulated information signal is amplitude limited by limiter 16 and is coupled, via series capacitor 20 (30 picofards) and shunt resistor 22 (10 Kohms), to an input terminal 52 of a four quadrant product detector 13, which in the exemplary embodiment, is a Gilbert cell. A quadrature signal, which is 90 degree phase shifted with respect to the signal coupled to input terminal 52 (reference signal), is coupled to a second input terminal 50 of detector 13 via a phase shift network of series capacitor 24 (7 picofards), RLC tank circuit 26 coupled between IC terminal pin 42 and ground, series capacitor 28 (50 picofards), and shunt resistor 30 (10 Kohms). A bias voltage is also provided to input terminals 52, 50 via respective resistors 22 and 30. Tank circuit 26 includes an adjustable inductance (L) 32 in parallel with a fixed capacitance (C) 34. LC circuit 32,34 is a purchased unit manufactured by the Sony Company, part No. 1T363, and is provided in a shielded container 36, which is grounded. In the exemplary embodiment, capacitor 34 is 75 picofards and inductance 32 is 12 microhenries. This unit is tuned to within 1 percent of 5.3 MHz. Resistor 38 is coupled across LC circuit 32,34, and with an exemplary value of 5 Kohms, provides a circuit "Q" of about 8.5. Varactor diode 40 is coupled in parallel with LC circuit 32,34 in order to accurately adjust the tuned frequency of tank circuit 26 to 4.5 MHz. Diode 40 is adjustable between 13 and 33 picofarads by a control voltage, generated by DAC 44 ,which is applied to the anode of diode 40 via isolation resistor 47. In the exemplary embodiment, the adjustment range of diode 40 is limited by the range of control voltages available from DAC 44. When LC circuit 32,34 is used with a varactor diode, the value of capacitor 34 is added to the capacitance of varactor diode 40 and the sum of the two capacitances tunes tank 26 to 4.5 MHz. The control voltage generated by DAC 44 is coupled to varactor 40 via the same pin 42 used to couple tank 26 to the other members of demodulator 10 disposed on IC 12. The control voltage generated by DAC 44 is responsive to control signals received via bus 46, under the control of a microprocessor or microcomputer (not shown). Each DAC discussed herein is associated with a bus decoder for determining which data is addressed to the particular DAC, and for decoding the bus data into plural data lines for applicaton to the DAC ladder. For simplicity of illustration, the bus decoder for the respective DACs discussed herein is not shown. The bus of the exemplary embodiment is I2C but any applicable bus, such as an IM bus, can be used. In order to prevent the control voltage across varactor diode 40 from being shunted to ground by inductance 32, a DC blocking capacitor 48 is connected in series with the LC circuit 32,34 at node 39. For the same reason, resistor 38 is also returned to node 39. However, since the resistance of resistor 38 is much larger than the DC resistance of inductance 32, returning resistor 38 to node 39 is optional, and it may be returned to ground. Additionally, DC blocking capacitor 48 also permits the use of an inductive component which is not intended to pass DC current since the additional magnetic flux due to such a current would have to be taken into account in the design of inductance 32. Thus, the designer has greater flexibility in the choice of components. When tank circuit 26 is tuned to the carrier frequency of the FM signal, it is resistive at the tuned frequency. In this manner, the signal coupled to terminal 50 via capacitor 24, tank circuit 26, capacitor 28 and resistor 30 is 90 degrees shifted from the reference signal coupled to terminal 52 via capacitor 20 and resistor 22, which add some phase shift to the reference signal path. The detected output information signal at terminal 58 of product detector 18 is a square wave (train of pulses) at the frequency of the FM carrier but with the duty cycle of the square wave being a function of the frequency deviation of the carrier. The demodulated information signal is recovered from the duty cycle variation by an integrator 60 (low pass network) which can be any suitable active or passive network, and is coupled via amplifier 62 to IC sound output terminal 64. Referring now to Fig. 2, there is shown a detailed schematic of the Gilbert cell product detector 18 based upon the Gilbert cell product detector described on page 177 of "Solid State Radio Engineering" by Herbert K. Krause et al., published by the Wiley Company, Copyright 1980. For the purposes of Fig. 2, resistors 22a,22b and 30a,30b can be considered equivalents of respective resistors 22, 30 of Fig. 1. Detector 18 is driven in an unbalanced configuration by unbalanced signals at terminals 50,52. Resistor 72 is coupled between Vcc and the collector electrodes of the transistors 66, 68 which are connected together at node 73. The demodulated output signal at terminal 58 is derived across load resistor 72 and corresponds to the currents flowing through resistor 72. Output level DAC 54, under computer control via bus 46, generates an output level control signal, current Ig, which is coupled to node 73 via terminal 56. In the absence of any signal from DAC 54, current Ic of transistor 66, flowing through resistor 72, determines the amplitude of the demodulated pulse output signal. Transistor 66 is a current sink. As current Ig is provided by DAC 54 to node 73, less signal current is drawn through resistor 72 for the same Ic though transistor 66. Consequently, the voltage drop across resistor 72 is decreased, and the lower level of the output signal square wave at terminal 58 will rise towards Vcc. Similarly, the lower level of the output signal square wave will decrease (move further away from Vcc) as Ig decreases and a larger percentage of Ic flows through resistor 72. This relationship is described by the following equation, where RL is resistor 72 and Vo is the voltage at terminal 58: Vo = Vcc + iRL where i=Ig-Ic and |Ic| > |Ig| Thus, the peak level of the output signal square wave at terminal 58 is Vcc and the lower level of the output signal square wave is Vcc minus Vo. In this manner, the peak-to-peak amplitude of the output signal square wave is adjusted in response to the output current Ig of DAC 54, as determined by the digital data on bus 46. In an alternate embodiment shown in Fig. 3, the collector-emitter path of a bipolar transistor or the drain-source path of a field effect transistor (FET) is coupled in parallel with load resistor 72. These devices are shown in Fig. 3 as a block member with the numerical designation 76. The control electrode of transistor 76 is coupled to input terminal 56 to receive the control signals from DAC 54. The impedance of parallel circuit 72,76 is adjustable in response to the control signal applied to the control electrode. When the total impedance of the parallel circuit 72,76 is reduced, collector current Ic of transistor 66 will generate a lower voltage across the lower impedance value. Alternately, when the impedance of parallel circuit 72,76 is maximum, i.e., the conduction path of transistor 76 has maximum impedance, the peak-to-peak square wave output voltage generated by the same Ic will be maximum. Demodulator 10 has a variety of uses, e.g., in FM radios and television receivers including VCRs for demodulating the FM IF sound signal to produce an audio signal, or in VCRs for demodulating the video luminance signal which, in VHS format, is FM recorded onto the tape.

Claims: A demodulator (10,12,26,44, 46), comprising: a first portion (10) of said demodulator internal to an integrated circuit, IC (12), for processing AC signals; a second portion (44,46) of said demodulator internal to said IC and including signal generating means (44) for generating a DC control signal in response to digital information provided by a control bus (46); a third portion (26) of said demodulator external to said IC for influencing a phase characteristic of said first portion (10) of said demodulator, said third portion (26) including a tunable element (40) which is responsive to said DC control signal; and a common signal pin (42) of said IC through which said third portion (26) is coupled to said first portion (10) and said DC control signal is coupled to said tunable element (40). A demodulator as recited in Claim 1 wherein said third portion of said demodulator external to said IC comprises: an LC parallel tuned circuit (36) coupled between said pin (42) of said IC and a source of reference potential (ground); and a variable capacitance diode (40) coupled in parallel with said LC tuned circuit (36) between said pin (42) of said IC and said source of reference potential (ground). A demodulator as recited in Claim 2 wherein said first portion of said demodulator comprises: a source (16) of FM signal to be demodulated; a capacitor (24) coupling said FM signal to said common signal pin (42) of said IC; a multiplier (18) having a first input (52) coupled to an output of said source of FM signal and having a second input (50) coupled to said common signal pin (42) of said integrated circuit (12); and a further signal generating means (54) internal to said IC for generating a further DC control signal in response to further digital information provided by said control bus (46), said further signal generating means having an output coupled to said multiplier (18) for controlling the level of a demodulated output signal produced by said multiplier. A demodulator as recited in Claim 3 wherein: said output (56) of said further signal generating means is coupled to an output (58) of said multiplier for supplying an amplitude control current (lg) thereto for controlling said level of said demodulated output signal of said multiplier. A demodulator as recited in Claim 3 wherein: said multiplier (18) includes an output load resistor (72) coupled between the output (58) of said multiplier and a source of supply voltage (Vcc); and said output (56) of said further signal generating means is coupled to a control terminal of a variable impedance device (76) coupled in parallel with said output load resistor (72) of said multiplier.

Inventors: HUTCHINSON DANIEL MARK, MILLER RICK WAYNE, HUTCHINSON, DANIEL MARK, MILLER, RICK WAYNE
Applicants: THOMSON CONSUMER ELECTRONICS, THOMSON CONSUMER ELECTRONICS, INC.
Application year: 1996
Main classification: H03D3
IPC codes: H03D3