Fetching apparatus for fetching data from a main memory

Abstract: A fetching apparatus (20) is for use in a data processing equipment comprising a processor (11) and a main memory (12). The main memory has a page structure comprising a plurality of pages each of which has a plurality of page data. The fetching apparatus is located between the processor and the main memory. The fetching apparatus fetches the page data of a specific one of the pages as fetched page data from the main memory and supplies the fetched page data to said processor. The fetching apparatus comprises a plurality of resistors (23-1 to 23-K) each of which is for memorizing the fetched page data. A table section (24) is for memorizing addresses corresponding the page data in each of the page. The table section further memorizes, as data transfer locations, the memory areas corresponding to the addresses. In response to the specific page, a reading section (25) reads the page data of the specific page out of the main memory as read page data with reference to the table section to fetch the read page data as the fetched page data to a specific one of the registers in accordance with a specific one of the data transfer locations.

Description: This invention relates a fetching apparatus for fetching data from a main memory to supply the data to a central processing unit and, more particularly, to a fetching apparatus for use in processing data at a high speed. In general, an information or data processing equipment comprises a central processing unit or a processor and a main memory. The main memory may comprise a plurality of memory areas each of which has a predetermined memory size. Each of the memory areas is for memorizing a plurality of data as memorized data. Each of the memory areas may be called a page. In such a data processing equipment, a cache or buffer memory may be located between the processor and the main memory in order to carry out a memory access at a high speed. In case where the processor needs a particular data memorized in the main memory, the cache memory fetches, as a fetched page data block, a content of a page including the particular data. In order to obtain the particular data, the processor accesses the cache memory instead of the main memory. In a data processing, the processor may need an additional data which does not include the fetched page data block. The cache memory again fetches, as an additional fetched page data block, a content of an additional page including the additional data. In order to obtain the additional data, the processor accesses the cache memory. As described above, it is necessary for the cache memory to frequently carry out a fetching operation when the fetched page data block does not include the data which the processor needs. In case where the cache memory frequently carries out the fetching operation, it is difficult to carry out the data access at the high speed. Furthermore, the cache memory has a memory capacity for the fetched page data block. The fetched page data block may have unused data. Taking the unused data into consideration, it is necessary to determine the memory capacity. It is difficult to effectively use the cache memory. WO-A-88/03292 discloses a data alignment system for transferring only system words of a subarray between the system memory and a buffer memory. It is therefore an object of this invention to provide a fetching apparatus capable of carrying out a data access at a high speed. It is another object of this invention to provide a fetching apparatus capable of effectively using a memory area. These objects are achieved with the features of the claims, and in particular of claim 1. Other objects of this invention will become clear as the description proceeds. On describing the gist of this invention, it is possible to understand that a fetching apparatus is for use in a data processing equipment comprising a main memory and a processor. The main memory has a page structure comprising a plurality of pages each of which memorizes a plurality of page data. The fetching apparatus is located between the main memory and the processor to fetch the data of a specific one of the pages as fetched page data from the main memory and to supply the fetched page data to the processor. According to this invention, the fetching apparatus comprises memory means having a plurality of memory areas each of which is for memorizing the fetched page data, table means for memorizing addresses corresponding to the page data in each of the pages and for memorizing, as data transfer locations, the memory areas corresponding to the addresses, and reading means responsive to the specific page for reading the page data of the specific page out of the main memory as read page data with reference to the table means to fetch the read page data as the fetched page data to a specific one of the memory areas in accordance with the transfer locations. Fig. 1 shows a view for describing a fetch operation of a conventional fetching apparatus; and Fig. 2 is a block diagram for describing a fetching apparatus according to a preferred embodiment of this invention. Referring to Fig. 1, a conventional fetching apparatus will be described at first in order to facilitate an understanding of this invention. The fetching apparatus may be for use in a data processing system comprising a processor 11 and a main memory 12. The fetching apparatus comprises a cache memory 13 located between the processor 11 and the main memory 12. The main memory 12 has a page structure comprising a plurality of pages each of which memorizes a plurality of page data. More particularly, the main memory 12 has first through N-th pages #1 to #N, where N represents a positive integer which is greater than one. Each of the first through the N-th pages has page data in the number of M, where M represents a positive integer which is greater than one. The cache memory 13 has a capacity corresponding to one page. It will be assumed that the processor 11 needs a particular page data including a specific one of the first through the N-th pages. The specific page may be, for example, the first page. In this event, the content of the first page is fetched in the cache memory 13. The processor 11 accesses the cache memory 13 to obtain the particular page data. In a job, the processor 11 intends to access the page data including the specific page. Therefore, the processor 11 can carry out a data access at a high speed when the specific page is memorized in the cache memory 13. In a job, the processor 11 may access the page data of another page, for example, the second page, after accessing the page data of the first page. In this case, the cache memory 13 must fetch the content of the second page after the processor 11 obtains the page data of the first page. As readily understood from the above description, the processor 11 can not carry out the data access at the high speed when the processor 11 uses a plurality of pages in the job. Furthermore, the processor 11 may successively process the first through the N-th pages at a predetermined period. In this event, it is necessary to periodically memorize the first through the N-th pages in the cache memory 13. In case where the first through the N-th pages are periodically memorized in the cache memory 13, the processor 11 can not carry out data access at the high speed. Referring to Fig. 2, description will proceed to a fetching apparatus according to a preferred embodiment of this invention. The illustrated fetching apparatus is designated by a reference numeral 20. The fetching apparatus 20 may be for use in the data processing system comprising the processor 11 and the main memory 12. The fetching apparatus 20 is located between the processor 11 and the main memory 12. The fetching apparatus 20 comprises a page address register (PAR) 21, a page counter (PCTR) 22, first through K-th fetching registers (PFR) 23-1 to 23-K, where K represents a positive integer which is not greater than the positive integer M, a time-source-destination table (TSDT) 24, and a synchronous data transfer controller (SDTC) 25. The main memory 12 has the page structure comprising first through N-th pages #1 to #N each of which has page data in the number of M. More particularly, each of the first through the N-th pages has first through M-th page data. The TSDT 24 stores table information which is representative of a relationship between offset addresses in each of the first through the N-th pages and the first through the K-th fetching registers 23-1 to 23-K. Each of the offset addresses may be called a transfer source. The TSDT 24 comprises a source area for memorizing the offset addresses in the number of K and a destination area for memorizing outlet port numbers corresponding to the offset addresses, respectively. More specifically, each of the first through the N-th pages has first through M-th offset addresses. Specific ones of the first through the M-th offset addresses are memorized in the source area. The number of the specific offset addresses is equal to the positive integer K. The page address register 21 stores a specific page number as a stored page number which is indicative of one of the first through the N-th pages #1 to #N. The specific page number is supplied from the processor 11 to the page address register 21. The stored page number is renewed into a renewed page number by the processor 11 as will be described later. The synchronous data transfer controller 25 comprises an address producing circuit 26, a switch control circuit 27, and a switching circuit 28. The stored page number is supplied from the page address register 21 to the address producing circuit 26. The page counter 22 is supplied with a start signal and a reset signal from an external device (not shown). Each of the start and reset signals are supplied to the page counter 22 at a predetermined period which may be equal to a processing time duration assigned to each page. The page counter 22 starts a count in response to the start signal and stops the count in response to the reset signal. Supplied with the start signal, the page counter 22 starts a count to supply the TSDT 24 with a count signal representative of the count. Responsive to the count signal, the offset addresses and the outlet port numbers are successively read out of the TSDT 24. It will be assumed that the page counter 22 produces first through K-th count signals during the predetermined period. The first through the K-th count signals are representative of first through K-th counts, respectively. It will be assumed that an m-th offset address and a k-th outlet port number are read out of the TSDT 24 in responce to a k-th count signal, where m represents a variable between one and M and k represents a variable between one and K, both inclusive. The m-th offset address corresponds to the k-th outlet port number. The m-th offset address is supplied to the address producing circuit 26. The k-th outlet port number is supplied to the switch control circuit 27. As described above, the address producing circuit 26 is supplied with the stored page number from the page address register 21. Responsive to the stored page number, the address producing circuit 26 knows a page which should be fetched. More particularly, the address producing circuit 26 produces a main memory address in accordance with the stored page number and the m-th offset address in order to read m-th page data in the specific page out of the main memory 12. Now, it will be assumed that the stored page number is the first page number #1. In this event, the m-th page data of the first page are read as m-th #1 page data out of the main memory 12 in accordance with the m-th offset addresses. The m-th #1 page data are supplied to the switching circuit 28. As described above, the switch control circuit 27 is supplied with the k-th outlet port number. The switch control circuit 27 controls the switching circuit 28 in response to the k-th outlet port number. More specifically, the switch control circuit 27 controls the switching circuit 28 in response to the k-th outlet port number in order to make the switching circuit 28 supply the k-th #1 page data to a k-th fetching register 23-k. As a result, the k-th fetching resister 23-k fetches the m-th #1 page data. In the manner described above, the first through the k-th fetching resisters 23-1 to 23-k fetch specific ones of the first through the M-th #1 page data or first through k-th page data, respectively. The processor 11 carries out a data processing in accordance with the first through the K-th page data which are fetched in the first through the K-th fetching registers 23-1 to 23-K. respectively. After the end of the data processing, the processor 11 supplies the page address register 21 with a page number needed in a next data processing. Namely, the processor 11 renews the stored page number into the renewed page number. After the predetermined period lapses, the page counter 22 is reset by the reset signal supplied from the external device. The page counter 22 is reset after the count reaches to the K-th count. The page counter 22 again starts the count in response to the start signal. As described above, the synchronous data transfer controller 25 carries out a data transfer from the main memory 12 to the first through the K-th fetching registers 23-1 to 23-K. After the predetermined period lapses, the processor 11 renews the stored page number into the renewed page number. The fetching apparatus 20 fetches the page data in accordance with the renewed page number.

Claims: A fetching apparatus (20) for use in a data processing equipment comprising a main memory (12) and a processor (11), said main memory having a page structure comprising a plurality of pages each of which memorizes a plurality of page data, said fetching apparatus being located between said main memory and said processor to fetch part of page data in a specific one of said pages as fetched page data from said main memory and to supply said fetched page data to said processor, characterized by : memory means (23-1 to 23-K) having a plurality of memory areas which is for memorizing said fetched page data; table means (24) for memorizing addresses corresponding to at least part of page data in said specific page and for memorizing, as data transfer locations, said memory areas corresponding to said addresses; and reading means (25) for reading at least part of page data of said specific page out of said main memory as read page data in accordance with the addresses of said table means on specifying said specific page, to store said read page data as said fetched page data to a specific one of said memory areas in accordance with a specific one of said data transfer locations. A fetching apparatus as claimed in claim 1, wherein said memory means comprises a plurality of registers (23-1 to 23-K) which are said memory areas. A fetching apparatus as claimed in claim 1 or 2, wherein: said fetching apparatus further comprises: a page address register (21) for indicating said specific page; and a page counter (22) for counting a count during a predetermined period to produce a count signal representative of said count; said table means being responsive to said count signal for synchronously producing a pair of said address and said data transfer location as a read address and a read data transfer location. A fetching apparatus as claimed in claim 1, 2, or 3, wherein said reading means comprises: accessing means (26) for accessing said main memory in accordance with the read address of said specific page to read said read page data out of said main memory; and transferring means (27, 28) for transferring said read page data to a specific one of said memory areas in accordance with said read data transfer location to store said read page data as said fetched page data in said specific memory area. A fetching apparatus as claimed in any one of claims 1 to 4, wherein: said reading means (25) carries out a read-out operation at which said read page data are read out of said main memory, on the basis of a specific one of said addresses; and said reading means carrying out a transfer operation at which said read page data is transferred to said specific memory area to be stored in said specific memory area, on the basis of a specific one of said data transfer locations.

Inventors: HARASAWA AKIO, HARASAWA, AKIO, Harasawa, Akio, c/o NEC Corporation
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1996
Main classification: G06F5
IPC codes: G06F7, G06F12