INSTRUCTION DECODER INCLUDING EMULATION USING INDIRECT SPECIFIERS

Abstract: A ROM-based decoder exploits the high degree of redundancy between instructions to share various operation structures and substantially reduce memory size. The decoder includes a circuit which merges and shares common ROM sequences to reduce ROM size. A superscalar microprocessor includes an instruction decoder having an emulation code control circuit and an emulation ROM which emulates the function of a logic instruction decoder. An instruction register is loaded with a current instruction and has various bit-fields that are updated according to the state of the processor. An entry point circuit derives an emulation ROM entry point from the instruction stored in the instruction register. The emulation ROM entry point is used to address the emulation ROM, from which an operation (Op) is read. Various fields of the Op are selectively substituted from the instruction register and emulation environment registers.

Description: INSTRUCTION DECODER INCLUDING EMULATION USING INDIRECT SPECIFIERS TECHNICAL FIELD This invention relates to processors. More specifically, this invention relates to processors having an instruction decoder including an emulation ROM for emulating decoder logic. BACKGROUND ART Advanced microprocessors, such as P6-class x86 processors, are defined by a common set of features. These features include a superscalar architecture and performance, decoding of multiple x86 instructions per cycle and conversion of the multiple x86 instructions into RJSC-li e operations. The RISC-like operations are executed out-of-order in a RISC-type core that is decoupled from decoding. These advanced microprocessors support large instruction windows for reordering instructions and for reordering memory references. Performance of an advanced superscalar microprocessor is highly dependent upon decoding performance including decoding speed, the number of x86 instructions decoded in a single cycle, and branch prediction performance and handling. Instruction decoders in advanced superscalar microprocessors often include one or more decoding pathways in which x86 instructions are decoded by hardware logic translation and a separate decoding pathway which uses a ROM memory for fetching a RISC operation sequence that corresponds to an x86 instruction. Generally, x86 instructions that are translated by hardware logic are simple x86 instructions. The lookup ROM is used to decode more complex x86 instructions. A substantial problem in a processor which uses a microcode ROM to direction instruction execution is the size ofthe ROM memory. Another problem with usage ofa lookup ROM for decoding instructions is the overhead incurred in determining a vector ROM address and retrieving operations (Ops) from ROM. This overhead typically causes a penalty in decoder throughput for instructions that are decoded using the ROM. This throughput penalty lowers decoding performance. A further problem with the usage of lookup ROM for decoding x86 instructions is the existence of large number of different CISC-type instructions that are standard for an x86 processor. Since a substantial number of instructions are implemented, a large ROM circuit on the processor chip is necessary for converting the mstructions to RISC-like operations. The large number of implemented instructions corresponds to an increased circuit complexity for deriving pointers to the ROM and applying the derived pointers to the ROM. This increased circuit complexity directly relates to an increased overhead that reduces instruction decoding throughput. A large lookup ROM increases the size ofthe processor integrated circuit and thereby reduces manufacturing yields of the circuits and increases production costs. One characteristic ofa lookup ROM is that many instruction sequences are mutually similar and have only minor differences. Accordingly, a lookup ROM memory typically has a high degree of redundancy between various instructions. What is needed is a reduced-size and reduced-complexity ROM-based decoder in a superscalar instruction decoder. DISCLOSURE OF THE INVENTION In accordance with the present invention. a ROM-based decoder exploits the high degree of redundancy between instructions to share various operation structures and substantially reduce memory size. The decoder includes a circuit which merges and shares common ROM sequences to reduce ROM size. In accordance with one aspect of the present invention, a superscalar microprocessor includes an instruction decoder having an emulation code control circuit and an emulation ROM which emulates the function of a logic instruction decoder. An instruction register is loaded with a current instruction and has various bit-fields that are updated according to the state of the processor. An entry point circuit derives an emulation ROM entry point from the instruction stored in the instruction register. The emulation ROM entry point is used to address die emulation ROM, from which an operation (Op) or a group of Ops is read. Various fields in the Op are selectively substituted from the instruction register. In accordance with a first embodiment ofthe present invention, an instruction decoder emulation circuit in a processor includes an instruction register for holding an instruction code and an entry point circuit connected to the instruction register to receive an instruction code. The instruction register has a plurality of encoded bit fields within the instruction code. The entry point circuit derives an entry point from the instruction code. The instruction decoder emulation circuit also includes an emulation code sequencer connected to the entry point circuit to receive the derived entry point and an emulation code memory connected to the emulation code sequencer to receive the direction signals. The emulation code sequencer directs a sequence of operations (Ops) and generates direction signals in accordance with the directed sequence. The emulation code memory stores a plurality of Op sequences and sequence control codes. The emulation code memory has a first output terminal for outputting Op sequences and a second output terminal for outputting sequence control codes. The sequence control code output terminal is connected to the emulation code sequencer. The instruction decoder emulation circuit also includes an operation (Op) substitution circuit connected to the emulation code memory first output terminal to receive an Op sequence and connected to the instruction register to receive selected encoded bit fields ofthe instruction code. The Op substitution circuit substitutes selected fields of the instruction code bit fields into the Op sequence. The instruction register holds instruction bytes that are decoded by a vectoring decoder. During a vectoring instruction decode, the vectoring decoder generates an initial vectoring quad and an entry point address based on the contents ofthe instruction register. At the same time, the vectoring decoder initializes the emulation environment variables, also called the emulation environment register, from various information based on fields of - j - the mstruction register and based on other mformation information from the emulation environment register is supplied to Op substitution logic that performs the substitution operation In accordance with another embodiment ofthe present invention, a method of operating an instruction decoder emulation circuit in a processor includes the steps of receivmg an instruction code mto an mstruction register having a plurality of encoded bit fields withm the mstruction code and selectively updating vaπous ones of the plurality of encoded bit fields in accordance with a processor state The method further mcludes the steps of deπvmg an entry point from the instruction code and addressmg an emulation code memory accordmg to the denved entry point The emulation code memory stonng a plurality of Op sequences. The method also inciudes the steps of outputting an addressed operation from the emulation code memory and substituting selected encoded bit fields of the mstruction code into the addressed operation Many advantages are gamed by the described decoder Usage of emulation mode substitution achieves encoding of CISC functionality while substantially reducing the size of emulation code ROM, advantageously reducmg the size and cost of a processor integrated circuit Emulation mode substitution enables sharing of ROM sequences by instructions which are similar BRIEF DESCRIPTION OF THE DRAWINGS The features ofthe invention believed to be novel are specifically set forth in the appended ciaims. However, the mvention itself, both as to its structure and method of operation, may best be understood by referring to the following description and accompanying drawings. Figure 1 is a block diagram which illustrates a computer system in accordance with one embodiment ofthe present invention Figure 2 is a block diagram illustratmg one embodiment of processor for usage m the computer system shown in Figure 1 Figure 3 is a timing diagram which illustrates pipeline tuning for an embodiment of the processor shown in Figure 2 Figure 4 is a schematic block diagram showmg an embodiment of an instruction decoder used the processor shown m Figure 2 Figure 5 is a schematic block diagram which depicts a structure of an emulation code sequencer and an emulation code memory ofthe instruction decoder shown m Figure 4 Figures 6A through 6E are pictorial illustrations showing a plurality of operation (Op) formats generated by the instruction decoder shown in Figure 4 Figure 7 is a pictorial depiction of an OpSeq field format employed in the emulation code memory shown in Figure 5. Figure 8 is a pictorial depiction of an exemplary instruction substitution. FIGURE 9 is a block diagram of a personal computer incoφorating a processor having an instruction decoder including emulation using indirect specifiers in accordance with an embodiment ofthe present invention. MODE(S) FOR CARRYING OUT THE INVENTION Referring to Figure 1. a computer system 100 is used in a variety of applications, including a personal computer application. The computer system 100 inciudes a computer motherboard 110 containing a processor 120 in accordance with an embodiment of the invention. Processor 120 is a monolithic integrated circuit which executes a complex instruction set so that the processor 120 may be termed a complex instruction set computer (CISC). Examples of complex instruction sets are the x86 instruction sets implemented on the well known 8086 family of microprocessors. The processor 120 is connected to a level 2 (L2) cache 122, a memory controller 124 and local bus controllers 126 and 128. The memory controller 124 is connected to a main memory 130 so that the memory controller 124 forms an interface between the processor 120 and the main memory 130. The local bus controllers 126 and 128 are connected to buses including a PCI bus 132 and an ISA bus 134 so that the local bus controllers 126 and 128 form interfaces between the PCI bus 132 and the ISA bus 134. Referring to Figure 2. a block diagram of an embodiment of processor 120 is shown. The core ofthe processor 120 is a RISC superscalar processing engine. Common x86 instnictions are converted by instruction decode hardware to operations in an intemal RISC86 instruction set. Other x86 instructions, exception processing, and other miscellaneous functionality is implemented as R1SC86 operation sequences stored in on-chip ROM. Processor 120 has interfaces including a system interface 210 and an L2 cache control logic 212. The system interface 210 connects the processor 120 to other blocks ofthe computer system 100. The processor 120 accesses the address space ofthe computer system 100. including the main memory 130 and devices on local buses 132 and 134 by read and write accesses via the system interface 210. The L2 cache control logic 212 forms an interface between an extemal cache, such as the L2 cache 122, and the processor 120. Specifically, the L2 cache control logic 212 interfaces the L2 cache 122 and to an mstruction cache 214 and a data cache 216 in the processor 120. The instruction cache 214 and the data cache 216 are level 1 (L l ) caches which are connected through the L2 cache 122 to the address space ofthe computer system 100. Instructions from main memory 130 are loaded mto mstruction cache 214 via a predecoder 270 for anticipated execution. The predecoder 270 generates predecode bits that are stored in combination with instruction bits in the mstruction cache 214. The predecode bits, for example 3 bits, are fetched along with an associated instruction byte (8 bits) and used to facilitate multiple instruction decoding and reduce decode time, instruction bytes are loaded into instruction cache 214 thirty-two bytes at a time as a burst transfer of four eight-byte quantities. Logic ofthe predecoder 270 is replicated eight times for usage four times in a cache line so that predecode bits for all eight instruction bytes are calculated simultaneously immediately before being written into the instruction cache 214. A predecode operation on a byte typically is based on mformation m one, two or three bytes so that predecode information may extend beyond an eight-byte group. Accordingly, the latter two bytes of an eight-byte group are saved for processing with the next eight-byte group in case of predecode information that overlaps two eight-byte groups. Instructions in instruction cache 214 are CISC instructions, referred to as macroinstructions. An instruction decoder 220 converts CISC instructions from instruction cache 214 into operations ofa reduced instruction set computing (RISC) architecture instruction set for execution on an execution engine 222. A single macroinstruction from instruction cache 214 decodes into one or multiple operations for execution engine 222. Instruction decoder 220 has mterface connections to the instruction cache 214 and an instruction fetch control circuit (shown in Figure 4). Instruction decoder 220 includes a macroinstruction decoder 230 for decoding most macroinstructions. an instruction emulation circuit 231 including an emulation ROM 232 for decoding a subset of instructions such as complex instructions, and a branch unit 234 for branch prediction and handling. Macroinstructions are classified according to the general type of operations into which the macroinstructions are converted. The general types of operations are register operations (RegOps), load-store operations (LdStOps), load immediate value operations (LIMMOps), special operations (SpecOps) and floating point operations (FpOps). Execution engme 222 has a scheduler 260 and six execution units includmg a load unit 240, a store unit 242, a first register unit 244, a second register unit 246, a floating point unit 248 and a multimedia unit 250. The scheduler 260 distributes operations to appropnate execution units and the execution units operate in parallel. Each execution unit executes a particular type of operation. In particular, the load unit 240 and the store unit 242 respectively load (read) data or store (write) data to the data cache 216 (L 1 data cache), the L2 cache 122 and the main memory 130 while executing a load/store operation (LdStOp). A store queue 262 temporarily stores data from store unit 242 so that store unit 242 and load unit 240 operate in parallel without conflicting accesses to data cache 216. Register units 244 and 246 execute register operations (RegOps) for accessing a register file 290. Floatmg pomt unit 248 executes floating point operations (FpOps). Multimedia unit 250 executes arithmetic operations for multimedia applications. Scheduler 260 is partitioned into a plurality of, for example, 24 entries where each entry contains storage and logic. The 24 entnes are grouped into six groups of four entπes. called Op quads. Information in the storage of an entry describes an operation for execution, whether or not the execution is pending or completed. The scheduler monitors the entries and dispatches information from the entries to information-designated execution units. Referring to Figure 3. processor 120 employs five and six stage basic pipeline timing. Instruction decoder 220 decodes two instructions in a single clock cycle. During a first stage 310. the mstruction fetch control circuit 218 fetches CISC instructions into instruction cache 214. Predecoding ofthe CISC instructions dunng stage 310 reduces subsequent decode time. During a second stage 320. instruction decoder 220 decodes instructions from mstruction cache 214 and loads an Op quad mto scheduler 260 Dunng a third stage 330. scheduler 260 scans die entπes and issues operations to corresponding execution units 240 to 252 if an operation for the respective types of execution units is available. Operands for the operations issued during stage 330 are forwarded to the execution units in a fourth stage 340. For a RegOp. the operation generally completes in the next clock cycle which is stage 350, but LdStOps require more time for address calculation 352. data access and transfer ofthe results 362. For branch operations, instruction decoder 220 performs a branch prediction 324 during an initial decoding ofa branch operation. A branch unit 252 evaluates conditions for the branch at a later stage 364 to determine whether the branch prediction 324 was correct. A two level branch prediction algorithm predicts a direction of conditional branching, and fetching CISC instructions in stage 310 and decoding the CISC instructions in stage 320 continues in the predicted branch direction. Scheduler 260 determines when all condition codes required for branch evaluation are valid, and directs the branch unit 252 to evaluate the branch instruction. If a branch was incorrectly predicted, operations in the scheduler 260 which should not be executed are flushed and decoder 220 begins loading new Op quads from the correct address after the branch. A time penalty is incurred as instructions for the correct branching are fetched. Instruction decoder 220 either reads a previously-stored predicted address or calculates an address using a set of parallel adders. If a previously-predicted address is stored, the predicted address is fetched in stage 326 and instructions located at the predicted address are fetched in stage 328 without a delay for adders. Otherwise, parallel adders calculate the predicted address. In branch evaluation stage 364. branch unit 252 determines whether the predicted branch direction is correct. If a predicted branch is correct, the fetching, decoding, and instruction-executing steps continue without interruption. For an incorrect prediction, scheduler 260 is flushed and instruction decoder 220 begins decoding macroinstructions from the correct program counter subsequent to the branch. Referring to Figure 4. a schematic block diagram illustrates an embodiment of an instruction preparation circuit 400 which is connected to the main memory 130. The instruction preparation circuit 400 includes the instruction cache 214 that is connected to the main memory 130 via the predecoder 270. The instruction decoder 220 is connected to receive instruction bytes and predecode bits from three altemative sources, the instruction cache 214, a branch target buffer (BTB) 456 and an instruction buffer 408. The instruction bytes and predecode bits are supplied to the instruction decoder 220 through a plurality of rotators 430. 432 and 434 via instruction registers 450, 452 and 454. The macroinstruction decoder 230 has input connections to the instruction cache 214 and instruction fetch control circuit 218 for receiving instruction bytes and associated predecode information. The macroinstruction decoder 230 buffers fetched instruction bytes in an instruction buffer 408 connected to the instruction fetch control circuit 18. The instruction buffer 408 is a sixteen byte buffer which receives and buffers up to 16 bytes or four aligned words from the insmiction cache 214. loading as much data as allowed by the amount of free space in the instruction buffer 408. The instruction buffer 408 holds the next instruction bytes to be decoded and continuously reloads with new instruction bytes as old ones are processed by the macroinstruction decoder 230. Instructions in both the insmiction cache 214 and the instruction buffer 408 are held in "extended" bytes, containing both memory bits (8) and predecode bits (5), and are held in the same alignment. The predecode bits assist the macroinstruction decoder 230 to perform multiple instruction decodes within a single clock cycle. Instruction bytes addressed usmg a decode program counter (PC) 420. 422, or 424 are transferred from the instruction buffer 408 to the macroinstruction decoder 230 The mstruction buffer 408 is accessed on a byte basts by decoders in the macromstruction decoder 230 However on each decode cycle, the mstruction buffer 408 is managed on a word basis for tracking which of the bytes in the mstruction buffer 408 are valid and which are to be reloaded with new bytes from the instruction cache 214 The designation of whether an mstruction byte is valid is maintained as the instruction byte is decoded For an invalid instruction byte, decoder invalidation logic (not shown), which is connected to the macromstruction decoder 230, sets a "byte invalid" signal. Control of updating ofthe current fetch PC 426 is synchronized closely with the validity of mstruction bytes in the instruction buffer 408 and the consumption ofthe instruction bytes by the mstruction decoder 220 The macromstruction decoder 230 receives up to sixteen bytes or four aligned words of mstruction bytes fetched from the instruction fetch control circuit 218 at the end ofa fetch cycle Instruction bytes from the instruction cache 214 are loaded into a 16-byte instruction buffer 408 The instruction buffer 408 buffers mstruction bytes, plus predecode information associated with each ofthe instruction bytes, as the mstruction bytes are fetched and/or decoded The instruction buffer 408 receives as many instruction bytes as can be accommodated by the mstruction buffer 408 free space, holds the next instruction bytes to be decoded and continually reloads with new instruction bytes as previous mstruction bytes are transferred to individual decoders withm me macroinstruction decoder 230 The instruction predecoder 270 adds predecode information bits to the mstruction bytes as the instruction bytes are transferred to the instruction cache 214 Therefore, the mstruction bytes stored and transferred by the instruction cache 214 are called extended bytes Each extended byte mcludes eight memory bits plus five predecode bits The five predecode bits mclude three bits that encode instruction length, one D-bit that designates whether the mstruction length is D-bit dependent, and a HasModRM bit that indicates whether an mstruction code includes a modrm field The thirteen bits are stored in the instruction buffer 408 and passed on to the macroinstruction decoder 230 decoders The mstruction buffer 408 expands each set of five predecode bits mto six predecode bits Predecode bits enable the decoders to quickly perform multiple instruction decodes withm one dock cycle The mstruction buffer 408 receives mstruction bytes from the instruction cache 214 m the memory-aligned word basis of instruction cache 214 storage so that mstructions are loaded and replaced with word granulanty Thus, the mstruction buffer 408 byte location 0 always holds bytes that are addressed m memory at an address of 0 (mod 16) Instruction bytes are transferred from the instruction buffer 408 to the macroinstruction decoder 230 with byte granularity Dunng each decode cycle, the sixteen extended instruction bytes withm the instruction buffer 408 , including associated implicit word valid bits, are transferred to the plurality of decoders withm the macroιnstructιondecoder230 This method of transferring mstruction bytes from the mstruction cache 214 to the macromstruction decoder 230 via the instruction buffer 408 is repeated with each decode cycle as iong as instructions are sequentially decoded When a control transfer occurs, for example due to a taken branch operation, the mstruction buffer 408 is flushed and the method is restarted The current decode PC has an arbitrary byte alignment that the mstruction buffer 408 has a capacity of sixteen bytes but is managed on a four-byte word basis which all four bytes of a word are consumed before removal and replacement or the word with four new bytes in the mstruction buffer 408 An mstruction has a length of one to eleven bytes and multiple bvtes are decoded so that the alignment of an instruction in the mstruction buffer 408 is arbitrary As instruction bytes are transferred from the instruction buffer 408 to the macromstruction decoder 230, the instruction buffer 408 is reloaded from the instruction cache 214 Instruction bytes are stored in the instruction buffer 408 with memory alignment rather than a sequential byte alignment that is suitable for application of consecutive instruction bytes to the macroinstruction decoder 230. Therefore, a set of byte rotators 430. 432 and 434 are interposed between the instruction buffer 408 and each ofthe decoders of the macroinstruction decoder 230 Four instruction decoders, including three short decoders SDecO 410. SDecl 412 or SDec2414. and one combined long and vectoring decoder 418. share the byte rotators 430, 432 and 434 In particular, the short decoder SDecO 410 and the combined long and vectormg decoder 418 share byte rotator 430 Short decoder SDec 1 412 is associated with byte rotator 432 and short decoder SDec2414 is associated with byte rotator 434 A plurality of pipeline registers, specifically instruction registers 450, 452 and 454, are inteφosed between the byte rotators 430. 432 and 434 and the instruction decoder 220 to temporanly hold the instruction bytes, predecode bits and other information, thereby shortening the decode timing cycle The other information held in the instruction registers 450, 452 and 454 includes vaπous information for assisting mstruction decodmg, including prefix (e.g. OF) status, immediate size (8-bit or 32-bιt), dispiacementand long decodable length designations Although a circuit is shown utilizing three rotators and three short decoders, in other embodiments, different numbers of circuit elements mav be employed For example, one circuit includes two rotators and two short decoders Instructions are stored in emorv alignment, not instruction alignment, in the instruction cache 214, the branch target buffer (BTB) 456 and the instruction buffer 408 so that the location of the first mstruction byte is not known The byte rotators 430. 432 and 434 find the first byte of an instruction The macroinstruction decoder 230 also performs vaπous instruction decode and exception decode operations, including validation of decode operations and selection between different types of decode operations Functions performed during decode operations include prefix byte handling, support for vectormg to the emulation code ROM 232 for emulation of instructions, and for branch unit 234 operations, branch unit interfacing and retum address prediction Based on the instruction bytes and associated mformation. the macro struction decoder 230 generates operation mformation in groups of four operations correspondmg to Op quads The macroinstruction decoder 230 also generates instruction vectoring control information and emulation code control mformation The macromstruction decoder 230 also has output connections to the scheduler 260 and to the emulation ROM 232 for outputting the Op quad information, instruction vectoring control information and emulation code control formation. The macroinstmction decoder 230 does not decode mstmctions when the scheduler 260 is unable to accept Op quads or is acceptmg Op quads from emulation code ROM 232 The macroinstruction decoder 230 has five distinct and separate decoders, includmg three "short" decoders SDecO 410. SDecl 412 and SDec2 414 that function in combination to decode up to three "short" decode operations of instructions that are defined within a subset of simple instmctions of the x86 instruction set. Generally, a simple mstmction is an mstruction that translates to fewer than three operations The short decoders SDecO 410, SDecl 412 and SDec2 414 each typically generate one or two operations, although zero operations are generated m certam cases such as prefix decodes Accordmgly for three short decode operations, from two to six operations are generated in one decode cycle The two to six operations from the three short decoders are subsequently packed together by operation packmg logic 438 into an Op quad smce a maximum of four ofthe six operations are valid. Specifically, the three short decoders SDecO 410. SDecl 412 and SDec2 414 each attempt to decode two operations, potentially generating six operations Only four operations may be produced at one time so that if more than four operations are produced, the operations from the short decoder SDec2 414 are invalidated The five decoders also mclude a single "long" decoder 416 and a single "vectonng" decoder 418 The long decoder 416 decodes mstmctions or forms of mstmctions having a more complex address mode form so that more than two operations are generated and short decode handling is not available The vectonng decoder 418 handles instmctions tiiat cannot be handled by operation of the short decoders SDecO 410. SDecl 412 and SDec2 414 or by the long decoder 416. The vectonng decoder 418 does not actually decode an mstmction, but rather vectors to a location of emulation ROM 232 for emulation ofthe instmction Vanous exception conditions that are detected by the macroinstmction decoder 230 are also handled as a special form of vectoring decode operation When activated, the long decoder 416 and the vectonng decoder 418 each generates a full Op quad An Op quad generated by short decoders SDecO 410. SDecl 412 and SDec2 414 has the same format as an Op quad generated by the long and vectonng decoders 416 and 418 The short decoder and long decoder Op quads do not include an OpSeq field The macroinstruction decoder 230 selects either the Op quad generated b> the short decoders 410, 412 and 414 or the Op quad generated by the long decoder 416 or vectoring decoder 418 as an Op quad result ofthe macroinstmction decoder 230 are each decode cycle Short decoder operation, long decoder operation and vectoring decoder operation function in parallel and independently of one another, although the results of only one decoder are used at Each ofthe short decoders 410 412 and 414 decodes up to seven instruction bytes, assuming the first byte to be an operation code (opcode) byte and the instmction to be a short decode instmction Two operations (Ops) are generated with correspondmg valid bits Appropriate values for effective address size, effective data size, the current x86-standard B-bit, and any override operand segment register are supplied for the generation of operations dependent on these parameters The logical address ofthe next ' sequential" instmction to be decoded is supplied for use in generatmg the operations for a CALL mstmction Note that the word sequential is placed in quotation marks to indicate that, although the "sequential" address generally pomts to an instruction which immediately precedes the present mstmction. the "sequential" address mav be set to anv addressed location. The current branch prediction is supplied for use in generating the operations for conditional transfer control instructions. A short decode generates control signals including indications ofa transfer control mstmction (for example, Jcc, LOOP, JMP, CALL), an unconditional transfer control instmction (for example, JMP, CALL), a CALL mstmction, a prefix byte, a cc-dependent RegOp, and a designation of whether the mstmction length is address or data size dependent Typically one or both operations are valid, but prefix byte and JMP decodes do not generate a valid op Invalid operations appear as valid NOOP operations to pad an Op quad The first short decoder 410 generates operations based on more than decodmg ofthe instmction bytes. The first short decoder 410 also determines the presence of any prefix bytes decoded durmg preceding decode cycles. Vaπous prefix bytes include OF address size override, operand size override, six segment overnde bytes, REP/REPE, REPNE and LOCK bytes Each prefix byte affects a subsequent instruction decode in a defmed way. A count of prefix bytes and a count of consecutive prefix bytes are accumulated during decoding and furnished to the first short decoder SDecO 410 and the long decoder 416 The consecutive prefix byte count is used to check whether an mstmction being decoded is too long Prefix byte count information is also used to control subsequent decode cycles, including checking for certain types of instmction-specific exception conditions Prefix counts are reset or initialized at the end of each successful non-prefix decode cycle in preparation for decoding the prefix and opcode bytes ofa next instruction Prefix counts are also reinitialized when the macroinstmction decoder 230 decodes branch condition and write instmction pointer (WRIP) operations Prefix bytes are processed by the first short decoder 410 in the manner of one-byte short decode mstmctions At most, one prefix byte is decoded in a decode cycle, a condition that is enforced through invalidation of all short decodes following the decode of a prefix byte Effective address size, data size, operand segment register values, and the current B-bit, are supplied to the first short decoder 410 but can decode along with preceding opcodes The address size prefix affects a decode of a subsequent mstmction both for decoding of instructions for which the generated operation depends on effective address size and for decodmg ofthe address mode and instruction length of modr/m mstmctions The default address size is specified by a currently-specified D-bit, which is effectively toggled by the occurrence of one or more address size prefixes The operand size prefix also affects the decode of a subsequent mstruction both for decoding of mstmctions for which the generated operation depends on effective data size and for decodmg ofthe mstmction length The default operand size is specified by a currentlv-specified x86-standard D-bit, which is effectively toggled by the occurrence of one or more operand size prefixes The segment override prefixes affect the decode of a subsequent instruction only in a case when the generation ofa load-store operation (LdStOps) is dependent on the effective operand segment ofthe instruction. The default segment is DS or SS, depending on the associated general address mode, and is replaced by the segment specified by the last segment overnde prefix The REP/REPE and REPNE prefixes do not affect the decode of a subsequent mstmction. If the mstmction is decoded by the macroinstmction decoder 230. rather than the emulation code ROM 232, then any preceding REP prefixes are ignored However, if the instruction is vectored, then the generation ofthe vector address is modified in some cases Specifically, if a string mstmction or particular neighboring opcode is vectored, then an indication ofthe occurrence of one or more ofthe REP prefixes and designation ofthe last REP prefix encountered are included in the vector address For all other instructions the vector address is not modified and the REP prefix is ignored A LOCK prefix inhibits all short and long decodmg except the decoding of prefix bytes, forc g the subsequent instruction to be vectored When the vector decode cycle of this subsequent mstmction occurs, so long as the subsequent instruction is not a prefix, the opcode byte is checked to ensure that the mstmction is withm a "lockable" subset ofthe mstmctions If the instmction is not a lockable instmction. an exception condition is recognized and the vector address generated by the vectonng decoder 418 is replaced by an exception entry pomt address Instructions decoded by the second and third short decoders 412 and 414 do not have prefix bytes so that decoders 412 and 414 assume fixed default values for address size, data size, and operand segment register values. Typically, the three short decoders generate four or fewer operations because three consecutive short decodes are not always performed and mstmctions often short decode into only a single operation However, for the rare occurrence when more than four valid operations are generated, operation packing logic 438 inhibits or invalidates the third short decoder 414 so that only two instructions are successfully decoded and at most four operations are generated for packmg into an Op quad When the first short decoder 410 is unsuccessful, the action ofthe second and third short decoders 412 and 414 are invalidated When the second short decoder 412 is unsuccessful, the action ofthe third short decoder 414 is invalidated When even the first short decode is invalid, the decode cycle becomes a long or vectormg decode cycle In general, the macroinstmction decoder 230 attempts one or more short decodes and, if such short decodes are unsuccessful, attempts one long decode If the long decode is unsuccessful, the macromstruction decoder 230 performs a vectonng decode Multiple conditions cause the short decoders 410. 412 and 414 to be m validated Most generally, short decodes are invalidated when the mstmction operation code (opcode) or the designated address mode of a modr/m instruction does not fall withm a defined short decode or "simple" subset of instructions. This condition typically restricts short decode instructions to those operations that generate two or fewer operations Short decodes are also invalidated when not all ofthe bytes m the instmction buffer 408 for a decoded instruction are valid Also, "cc-dependent" operations, operations that are dependent on status flags, are only generated by the first short decoder 410 to ensure that these operations are not preceded by and " cc" RegOps A short decode is invalidated for a second of two consecutive short decodes when the immediately preceding short decode was a decode of a transfer control instruction, regardless of the direction taken A short decode is invalidated for a second of two consecutive short decodes when the first short decode was a decode of a prefix byte. In general, a prefix code or a transfer control code inhibits further decodes m a cycle. Furthermore, no more than sixteen stmction are consumed by the macromstruction decoder 230 since the instruction buffer 408 only holds sixteen bytes at one time. Also, at most four operations can be packed into an Op quad. These constraints only affect the third short decoder 414 since the length of each short decoded mst ction is at most seven bytes and operations n excess of four only arise in the third short decoder 414. In a related constraint, if the current D-bit value specifies a 16-bit address and data size default, then an instruction having a length that is address and or data dependent can only be handled by the first short decoder 410 smce the predecode information is probably incorrect. Also, when multiple instruction decodmg is disabled, only the first short decoder 410 is allowed to successfully decode instructions and prefix bytes. Validation tests are controlled by short decoder validation logic in the macroinstruction decoder 230 and are independent of the operation of short decoders 410, 412 and 414. However, each ofthe short decoders 410, 412 and 414 does set zero, one or two valid bits depending on the number of operations decoded. These valid bits, a total of six for the three short decoders 410, 412 and 414. are used by the operation packing logic 438 to determine which operations to pack into an Op quad and to force invalid operations to appear as NOOP (no operation) operations. The operation packmg logic 438 operates without short decoder validation information since valid short decodes and associated operations are preceded only by other valid short decodes and associated operations. The short decoders 410, 412 and 414 also generate a plurality of signals representing various special opcode or modr/m address mode decodes These signals indicate whether a certam form of mstmction is currently bemg decoded by the instruction decoder 220. These signals are used by short decode validation logic to handle short decode validation situations The mstmction bytes, which are stored unaligned in the mstruction buffer 408, are aligned by byte rotators 430, 432 and 434 as the mstmction bytes are transferred to the decoders 410-418. The first short decoder SDecO 410, the long decoder 416 and the vectoring decoder 418 share a first byte rotator 430. The second and third short decoders SDec l 412 and SDec2 414 use respective second and third byte rotators 432 and 434. Durmg each decode cycle, the three shoπ decoders SDecO 410. SDec l 412 and SDec2 414 attempt to decode what are. most efficiently, three short decode operations using three independently-operating and parallel byte rotators 430. 432 and 434 Although the multiplexing by the byte rotators 430. 432 and 434 of appropriate bytes the instruction buffer 408 to each respective decoder SDecO 410, SDec l 412 and SDec2 414 is conceptually dependent on the preceding instruction decode operation, instruction length lookahead logic 436 uses the predecode bits to enable the decoders to operate substantially m parallel. The long and vectormg decoders 416 and 418. in combination, perform two parallel decodes of eleven instruction bytes, taking the first byte to be an opcode byte and generating either a long mstruction decode Op quad or a vectonng decode Op quad. Information analyzed by the long and vectormg decoders 416 and 418 includes effective address size, effective data size, the current B-bit and DF-bit, any override operand segment register, and logical addresses of the next sequential and target instmctions to be decoded The long and vectormg decoders 416 and 418 generate decode signals cludmg an mstmction length excluding precedmg prefix bits, a designation of whether the mstmction is withm the long decode subset of instmctions. a RET instruction, and an effective operand segment register, based on a default implied by the modr/m address mode plus any segment overnde Dunng a decode cycle in which none ofthe short decoders SDecO 410, SDecl 412 and SDec2414 successfully decodes a short mstruction. the macromstruction decoder 230 attempts to perform a long decode usmg the long decoder 416 If a long decode cannot be performed, a vectoring decode is performed. In some embodiments, the long and vectonng decoders 416 and 418 are conceptually separate and independent decoders, just as the long and vectoring decoders 416 and 418 are separate and mdependent ofthe short decoders 410, 412 and 414 Physically, however, the long and vectoring decoders 416 and 418 share much logic and generate similar Op quad outputs Instmctions decoded by the long decoder 416 are generally included within the short decode subset of instmctions except for an address mode constraint such as that the instruction cannot be decoded by a short decoder because the instmction length is greater than seven bytes or because the address has a large displacement that would require generation ofa third operation to handle to displacement The long decoder 416 also decodes certain additional modr/m instructions that are not in the short decode subset but are sufficiently common to warrant hardware decoding Instruction bytes for usage or decoding by the long decoder 416 are supplied from the instruction buffer 408 by the first byte rotator 430. the same instruction multiplexer that supplies mstmction bytes to the first short decoder SDecO 410 However, while the first short decoder SDecO 410 receives only seven bytes, the long decoder 416 receives up to eleven consecutive instruction bytes, corresponding to the maximum length of a modr/m instruction excluding prefix bytes Thus, the first byte rotator 430 is eleven bytes wide although only the first seven bytes are connected to the first short decoder SDecO 410 The long decoder 416 only decodes one mstmction at a time so that associated predecode information within the mstmction buffer 408 is not used and is typicallv invalid The first byte of the first byte rotator 430 is fully decoded as an opcode byte and, m the case ofa modr/m mstmction. the second mstruction byte and possibly the third are fully decoded as modr/m and sib bytes, respectively The existence ofa OF prefix is considered in decodmg ofthe opcode byte The OF prefix byte inhibits all short decoding smce all short decode mstmctions are non-OF or "one-byte" opcodes Because all prefix bytes are located within the "one-byte" opcode space, decoding ofa OF prefix forces the next decode cycle to be a two-byte opcode mstmction. such as a long or vectormg decode instruction In addition to generating operations based on the decoding of modr/m and sib bytes, the first byte rotator 430 also determines the length ofthe instruction for usage by various program counters, whether the instruction is a modr/m instmction for inhibiting or invalidating the long decoder, and whether the mstmction is an instmction within the long decode subset of operation codes (opcodes) The long decoder 416 always generates four operations and. like the short decoders 410, 412 and 141, presents the operations in the form of an emulation code-like Op quad, excluding an OpSeq field The long decoder 416 handles only relatively simple modr/m instructions A long decode Op quad has two possible forms that differ only in whether the third operation is a load operation (LdOp) or a store operation (StOp) and whether the fourth operation is a RegOp or a NOOP A first long decode Op quad has the form LIMM t2,<ιmm32> LIMM tl,<dιsp32> LD.b/d t8L/t8,@(<gam>)OS a <RegOp> A second long decode Op quad has the form LIMM t2.<ιmm32> LIMM t l ,<dιsp32> ST.b/d @(<gam>).t2L/t2.0S a NOOP The @(<gam>) address mode specification represents an address calculation corresponding to that specified by the modr/m and or sib bvtes ofthe instruction, for example @(AX + BX*4 + LD) The <ιmm32> and <dιsp32> values are four byte vaiues containing the immediate and displacement instruction bytes when the decoded mstmction contains such values The long decoder 416. like the first short decoder 410, generates operations taking mto account the presence of any prefix bytes decoded by the short decoders during preceding decode cycles. Effective address size, data size, operand segment register values, and the current B-bit are supplied to the long decoder 416 and are used to generate operations No indirect size or segment register specifiers are included within the final operations generated by the long decoder 416 Only a few conditions inhibit or invalidate an otherwise successful long decode. One such condition is an instmction operation code (opcode) that is not included in the long decode subset of mstructions A second condition is that not all of the mstmction buffer 408 bytes for the decoded instmction are valid The vectoring decoder 418 handles instmctions that are not decoded by either the short decoders or the long decoder 416 Vectonng decodes are a default case when no short or long decoding is possible and sufficient valid bytes are available Typicallv the instructions handled by the vectoring decoder 418 are not included in the short decode or long decode subsets but also result from other conditions such as decodmg being disabled or the detection of an exception condition During normal operation, only non-short and non-long instructions are vectored However, all mstmctions mav be vectored Undefined opcodes are always vectored Only prefix bytes are always decoded Prefix bytes are always decoded by the short decoders 410. 412 and 414 When an exception condition is detected during a decode cycle, a vectoring decode is forced, generally ovemding any other form of decode without regard for instruction byte validity of the decoded instruction When a detected exception condition forces a vectonng decode cycle, the generated Op quad is undefined and the Op quad valid bit for presentation to the scheduler 260 is forced to zero The Op quad valid bit informs the scheduler 260 that no operations are to be loaded to the scheduler 260 As a result, no Op quad is loaded mto the scheduler 260 dunng an exception vectormg decode cycle Few conditions inhibit or invalidate a vectoring decode One such condition is that not all ofthe bytes in the instruction buffer 408 are valid When an instmction is vectored, control is transferred to an emulation code entry point. An emulation code entry pomt is either in internal emulation code ROM 232 or in extemal emulation code RAM 236 The emulation code starting from the entry point address either emulates an instruction or initiates appropnate exception processing A vectoring decode cycle is properly considered a macroinstruction decoder 230 decode cycle In the case ofa vectoring decode, the macroinstmction decoder 230 generate the vectoring quad and generate the emulation code address into the emulation code ROM 232 Following the initial vectoring decode cycle, the macroinstruction decoder 230 remains mactive while instructions are generated by the emulation code ROM 232 or emulation code RAM 236 until a return from emulation (ERET) OpSeq is encountered The retum from emulation (ERET) sequencing action transitions back to macromstruction decoder 230 decoding Durmg the decode cycles followmg the initial vectonng decode cycle, the macroinstmction decoder 230 remains inactive, continually attempting to decode the next "sequential" instruction but havmg decode cycles repeatedly invalidated until after the ERET is encountered, thus wait g by default to decode the next "sequential" mstruction Instmction bytes for usage or decoding by the vectonng decoder 418 are supplied from the instmction buffer 408 by the first byte rotator 430. the same instruction multiplexer that supplies instruction bytes to the first short decoder SDecO 410 and to the long decoder 416 The vectonng decoder 418 receives up to eleven consecutive instruction bytes, corresponding to the maximum length ofa modr/m instruction excluding prefix bytes. Thus, the full eleven byte width ofthe first byte rotator 430 is distπbuted to both e long decoder 416 and the vectoring decoder 418 The predecode information withm the mstmction buffer 408 is not used by the vectonng decoder 418 As in the case ofthe long decoder 416, the first byte ofthe first byte rotator 430 is fully decoded as an opcode byte and. m the case of a modr/m instruction, the second mstmction bvte and possibly the third are fully decoded as modr/m and sib bytes, respectively The vectormg decoder 418 generates operations taking mto account the presence of any prefix bytes decoded by the short decoders during preceding decode cycles The existence ofa OF prefix is considered in decoding of the opcode byte In addition to generating operations based on the decodmg of modr/m and sib bytes, the first byte rotator 430 also determines the length ofthe mstmction for usage by vaπous program counters, whether the instmction is a modr/m mstmction for inhibiting or invalidating the long decoder, and whether the mstmction is an mstmction within the long decode subset of operation codes (opcodes) If not, a vectormg decode is initiated Effective address size, data size and operand segment register values are supplied to the vectoring decoder 418 and are used to generate operations No indirect size or segment register specifiers are included withm the final operations generated by the vectormg decoder 418 Duπng a vectonng decode cycle, the vectonng decoder 418 generates a vectonng Op quad, generates an emulation code entry pomt or vector address, and initializes an emulation environment The vectonng Op quad is specified to pass vanous information to initialize emulation environment scratch registers The value ofthe emulation code entry point or vector address is based on a decode ofthe first and second instruction bytes, for example the opcode and modr/m bytes, plus other information such as the presence of an OF prefix, a REP prefix or the like In the case of vectoring caused by an exception condition, the entry pomt or vector address is based on a simple encoded exception identifier The emulation environment is stored for resolving environment dependencies All ofthe short decoders 410, 412 and 414 and long decoder 416 directly resolve environmental dependencies, such as dependencies upon effective address and data sizes, as operations are generated so that these operations never contain indirect size or register specifiers However, emulation code operations do refer to such effective address and data size values for a particular instance of the mstmction being emulated The emulation environment is used to store this additional information relatmg to the particular instmction that is vectored This information mcludes general register numbers, effective address and data sizes, an effective operand segment register number, the prefix byte count, and a record ofthe existence ofa LOCK prefix The emulation environment also loads a modr/m reg field and a modr/m regm field are loaded into Reg and Regm registers The emulation environment is initialized at the end ofa successful vectoring decode cycle and remains at the initial state for substantially the duration ofthe emulation of an mstruction by emulation code, until an ERET code is encountered The vectormg decoder 418 generates four operations of an Op quad in one of four forms All four forms include three LIMM operations The four forms differ only in the immediate values ofthe LIMM operations and in whether the third operation is an LEA operation or a NOOP operation A first vectoring decode Op quad has the form LIMM t2.<ιmm32> LIMM tl ,<dιsp32> LEA t6,@(<gam>)._ a LIMM t7.LogSeqDecPC[31 0] //logical seq next //instr PC A second vectormg decode Op quad has the form LIMM t2,<ιmm32> LIMM t l .<dιsp32> NOOP LIMM t7.LogSeqDecPC[31 0] A third vectoring decode Op quad has the form LIMM t2,<+/- l /2/4> //equiv to "LDK(D)S t2,+l/+2" LIMM tl ,<+/- 2/4/8> //equiv to "LDK(D)S t l ,+2/+4" NOOP LIMM t7.LogSeqDecPC[31 0] A fourth vectoring decode Op quad has the form: LIMM t2,<+2/4> //equiv to "LDKD t2,+2" LIMM tl,<disp32> LD t6,@(SP).SS.s LIMM t7,LogSeqDecPC[31..0] //predicted RET target adr //from Retum Address Stack The first two forms of vectoring Op quads apply for most opcodes. The first form is used for memory- referencing modr/m instmctions for which the LEA operation is used to compute and load a general address mode effective operand address into a treg. The second form is used for non-modr/m and register-referencing modr/m instmctions. For instmctions having the second form no address is necessarily computed, although the <imm32> and <disp32> values remain useful insofar as they contain instmction bytes following the opcode byte. The third form of vectoring Op quad is used for all string instmctions plus some neighboring non-modr/m instmctions. A fourth form of vectoring Op quad supports special vectoring and emulation requirements for near RET instmctions. The macroinstmction decoder 230 has four program counters, including three decode program counters 420, 422 and 424, and one fetch program counter 426. A first decode program counter, called an instruction PC 420, is the logical address ofthe first byte, including any prefix bytes, of either the current instmction being decoded or, if no instruction is currently decoding, the next instruction to be decoded. If the decode operation is a multiple insmiction decode, instruction PC 420 points to the first instmction ofthe multiple instmctions to be decoded. The instmction PC 420 corresponds to the architectural address of an instmction and is used to generate instmction fault program counters for handling of exceptions. The instmction PC 420 is passed down the scheduler 260 with corresponding Op quads and is used by an operation commit unit (OCU) (not shown) ofthe scheduler 260 to produce instruction fault program counters to be saved during exception processing. When an Op quad is generated by the macroinstmction decoder 230. the current instmction PC 420 value is tagged to the Op quad and loaded into the Scheduler 260 Op quad entry along with the Op quad. A second decode program counter, called a logical decode PC 422, is the logical address ofthe next instmction byte to be decoded and addresses either an opcode byte or a prefix byte. A third decode program counter, called a linear decode PC 424. is the linear address ofthe next instruction byte to be decoded and addresses either an opcode byte or a prefix byte. The logical decode PC 422 and the linear decode PC 424 point to the same insmiction byte. The linear decode PC 424 designates the address of the instruction byte currently at the first byte rotator 430. The various decoders in the macroinstruction decoder 230 function on the basis of decoding or consuming either prefix bytes or whole instructions minus any prefix bytes so that prefixes are generally handled as one-byte instructions. Therefore, the address boundaries between insmiction and prefix byte decodes are more important than instmction boundaries alone. Consequently, at the beginning of each decode cycle, the next instmction byte to be decoded is not necessarily the true beginning of an instmction. At the beginning of a decode cycle the logical decode PC 422 and the linear decode PC 424 contain the logical and linear addresses ofthe next instmction to be decoded, either an insmiction or a prefix byte. The linear decode PC 424 is a primary program counter value mat is used during the decoding process to access the mstmction buffer 408 The linear decode PC 424 represents the starting point for the decode ofa cycle and specifically controls the byte rotator feeding bytes from the instmction buffer 408 to the first short decoder 410 and to the long and vectoring decoders 416 and 418 The linear decode PC 424 also is the reference pomt for determmmg the instruction addresses of any further shoπ decode instructions or prefix bytes, thus generatmg control signals for the byte rotators feeding the second and third short decoders 412 and 414 The lmear decode PC 424 also acts secondarily to check for breakpoint matches durmg the first decode cycles of new instructions, before prefix bytes are decoded, and to check for code segment overruns by the macroinstmction decoder 230 during successful instruction decode cycles The logical decode PC 422 is used for program counter-related transfer control instructions, includmg CALL instmctions The logical decode PC 422 is supplied to the branch unit 234 to be summed with the displacement value of a PC-relative transfer control mstmction to calculate a branch target address The logical decode PC 422 also supports emulation code emulation of instructions The next sequential logical decode program counter (PC) 422 is available in emulation code from storage in a temporary register by the vectonng Op quad for general usage For example, the next sequential logical decode PC 422 is used to supply a retum address that a CALL mstmction pushes on a stack A next logical decode PC 428 is set to the next sequential logical decode program counter value and has functional utility beyond that of the logical decode PC 422. The next logical decode PC 428 directly furnishes the return address for CALL instructions decoded by the macroinstmction decoder 230. The next logical decode PC 428 also is passed to emulation code logic dunng vectonng decode cycles via one of the operations within the vectonng Op quad Dunng a decode cvcle the linear decode PC 424 points to the next instmction bytes to be decoded The four least significant bits of linear decode PC 424 point to the first mstmction byte withm the instruction buffer 408 and thereby directly indicate the amount of byte rotation necessary to align the first and subsequent insmiction bytes in the stmction cache 214 The first byte rotator 430 is an instruction multiplexer, specifically a 16 1 byte multiplexer, for accessing bytes in the mstmction buffer 408 that are offset by the linear decode PC 424 amount. The first byte rotator 430 is seven bvtes wide for the first short decoder SDecO 410 and eleven bytes wide for uie long decoder 416 and the vectoring decoder 418 in combination Shared logic in the first short decoder SDecO 410, the long decoder 416 and the vectoring decoder 418 generate a first mstmction length value ILenO for the first mstmction The second and third byte rotators 432 and 434 are seven byte-wide instruction multiplexers, specifically 16 1 byte multiplexers The second byte rotator 432 accesses bytes in the mstruction buffer 408 that are offset by the sum of the linear decode PC 424 amount and the first instmction length ILenO. Logic in the second short decoder SDecO 412 generate a second mstmction length value ILenl for the second instmction The third byte rotator 434 accesses bytes in the stmction buffer 408 that are offset by the sum of the lmear decode PC 424 amount and the first and second instruction lengths ILenO and ILenl The byte rotators 430, 432 and 434 multiplex mst uction bytes but not predecode bits The byte rotators 430, 432 and 434 are controlled usmg predecode mformation which the predecode bits associated with the first opcode byte or the first byte ofthe first mstmction directly controls the second rotator 432 The first byte of the second instruction directly controls the third rotator 434 Each predecode code implies an instruction length but what is applied to the next rotator is a pomter. The pomter is derived by taking the four least significant bits of the program counter at the present instmction plus the length to attain the program counter to the next mstmction All program counters 420. 422. 424 and 428 in the macroinstmction decoder 230 are initialized durmg mstmction and exception processing A plurality of signal sources activate this initialization First, the branch unit 234 supplies a target branch address when a PC-relative transfer control mstmction is decoded and predicted taken. Second, a retum address stack (not shown) supplies a predicted retum target address when a near RET mstruction is decoded Third, the scheduler 260 generates a correct and alternate branch address when the macroinstmction decoder 230. along with the remaining circuits in the processor 120. is restarted by the scheduler 260 due to a mispredicted branch condition (BRCOND) operation Fourth, register unit 244, the primary RegOp execution unit, supplies a new decode address when a WRIP RegOp is executed The WRIP RegOp execution allows emulation code to explicitly redirect mstmction decoding In all four cases, a logical address is supplied and utilized to simultaneously reinitialize the three decode program counters 420. 422 and 424 For the linear decode PC 424, a lmear address value is supplied by adding the supplied logical address to the current code segment base address to produce the corresponding linear address for loading into linear decode PC 424 The logical address is loaded mto the current instmction PC 420 and the logical decode PC 422 For each decode cycle until a next reinitialization, the macromstruction decoder 230 sequentially and synchronously updates the current instruction PC 420, the logical decode PC 422 and the lmear decode PC 424 as msmiction bytes are successfully decoded and consumed by the individual decoders of macroinstruction decoder 230 Generation ofthe instmction lengths llenO and Ilenl occurs serially To hasten this serial process by emulating a parallel operation, mstruction length lookahead logic 436 quickly determines the instruction lengths IlenO and Ilenl usmg four predecode bits specifying the length of each mstmction byte in the mstmction buffer 408 The predecode bits associated with the opcode byte ofthe first mstmction byte the mstmction buffer 408, the first mstmction byte bemg multiplexed to the first short decoder SDecO 410. directly specifies a byte mdex ofthe opcode byte of the second mstruction byte m the instruction buffer 408 The predecode bits associated with the opcode byte of the second instruction byte in the instruction buffer 408 the second mstruction byte bemg multiplexed to the second short decoder SDecl 412, directly specifies a byte mdex ofthe opcode byte ofthe third mstruction byte in the mstmction buffer 408 The mstmction length lookahead logic 436 includes two four-bit-wide 16 1 multiplexers for generatmg the byte indices ofthe opcode bytes ofthe second and third instruction bytes in the mstruction buffer 408 The instruction lookahead logic 436 also mcludes logic for determmmg validity ofthe sets of predecode bits Predecode bits are valid when the associated instmction byte is the start of a valid short decode mstmction Specifically, the mstmction lookahead logic 436 determines whether predecode bits for a given byte in the mstmction buffer 408 pomt to the same byte, implying a zero length for an mstmction starting at that byte. If so, that byte is not the start of a short decode mstmction and no further short decodmg is possible. Otherwise, a short decode operation is possible and predecode bits point to the beginning ofthe next instruction The predecoder 270 connected between the mam memory 130 and the mstmction cache 214 has eight logic units, each of which examines its associated mstmction bvte plus, in some cases, the following one or two instruction bytes The first mstmction byte is decoded as an opcode byte and the second and third mstmction bytes, if the opcode byte is a modr/m opcode, are decoded as modr/m and sib bytes Based on these three bytes, the length of an mstmction and whether the mstmction is classified as a "short" instruction are determined. The length ofthe stmction is added to a four-bit fixed value correspondmg to the position of the logic unit with respect to the sixteen logic units to determine the byte index used by the mstmction length lookahead logic 436 This byte mdex is set as the value of the predecode bits if the instmction falls withm the criteria ofa short instmction For instmction bytes not meeting the short stmction criteria the predecode bits are set to the four-bit fixed value corresponding to the position ofthe logic unit with respect to the sixteen logic units without increment to designate an mstruction length of zero An implied instmction length of zero is indicative that the mstmction is not a short instruction The predecode bits are tmncated from four bits to three since short decode instmctions are never longer than seven bytes and the most significant bit is easily reconstructed from the three predecode bits and the associated fixed byte address The expansion from three to four predecode bits is performed by predecode expansion logic 440 having sixteen logic units corresponding to the sixteen instruction bytes ofthe instmction cache 214 The sixteen logic units of predecode expansion logic 440 operate independently and simultaneously on predecode bits as the instruction bytes are fetched from the instruction cache 214 to the instmction buffer 408 The final two ofthe thirty-two instmction bytes that are predecoded and loaded to the instruction cache 214 have only one or two bytes for examination by the predecoder 270 For modr/m opcodes the full instmction length cannot be determined Thus logic units for bytes 14 and 15 in the predecoder 270 are modified from logic units for bvtes 0 through 13 For instruction byte 15, logic unit 15 ofthe predecoder 270 forces an instruction length of zero for all modr/m opcodes and for non-short decode mstmctions For mstmction byte 14, an effective mstruction length of zero is forced for modr/m opcodes with an address mode requiring examination of a sib byte to reliably determme instruction length, as well as for non-short instmctions Durmg each decode cycle, the macroinstmction decoder 230 checks for several exception conditions, including an instruction breakpoint, a pending nonmaskable intermpt (NMI), a pending intermpt (INTR), a code segment overmn, an instruction fetch page fault, an instmction length greater than sixteen bytes, a nonlockable mstruction with a LOCK prefix, a floating point not available condition, and a pending floating point error condition Some conditions are evaluated only durmg a successful decode cycle, other conditions are evaluated irrespective of any decoding actions during the cvcle When an active exception condition is detected, all instruction decode cycles including short, long and vectormg decode cycles, are inhibited and an "exception" vectoring decode is forced in the decode cycle following exception detection The recognition of an exception condition is only overridden or inhibited by inactivity ofthe macromstruction decoder 230, for example, when emulation code Op quads are accepted by the scheduler 260. rather than short and long or vector decoder Op quads. In effect, recognition and handling of any exception conditions are delayed until an ERET Op seq retums control to the macromstruction decoder 230 During the decode cycle that forces exception vectoring, a special emulation code vector address is generated place ofa normal instmction vector address The vectoring Op quad that is generated by the long and vectonng decoders 416 and 418 is undefined. The exception vector address is a fixed value except for low-order bits for identifying the particular exception condition that is recognized and handled When multiple exception conditions are detected simultaneously, the exceptions are ordered in a priority order and the highest pπoπty exception is recognized. The mstmction breakpoint exception, the highest priority exception condition, is recognized when the linear decode PC 424 pomts to the first byte of an mstmction including prefixes, the lmear decode PC 424 matches a breakpoint address that is enabled as an mstmction breakpoint, and none ofthe instruction breakpoint mask flags are clear. One mask flag (RF) specifically masks recognition of instmction breakpoints Another mask flag (BNTF) temporarily masks NMI requests and instmction breakpoints The pendmg NMI exception, the penultimate priority exception, is recognized when an NMI request is pendmg and none ofthe NMI mask flags are clear One mask (NF) specifically masks nonmaskable interrupts. Another mask flag (BNTF) temporarily masks NMI requests and instmction breakpoints. The pending INTR exception, the next exception in pπoπty following the pendmg NMI exception, is recognized when an INTR request is pending and the intermpt flag (IF) and temporary intermpt flag (ITF) are clear. The code segment overmn exception, the next exception in priority following the pending INTR exception, is recognized when the macro struction decoder 230 attempts to successfully decode a set of mstmctions beyond a current code segment limit The mstruction fetch page fault exception having a priority immediately lower than the code segment overrun exception, is recognized when the macroinstruction decoder 230 requires additional valid instruction bytes from the instruction buffer 408 before decoding of another instruction or prefix byte is possible and the mstmction translation lookaside buffer (1TB) signals that a page fault has occurred on the current instruction fetch A faulting condition ofthe instruction fetch control circuit 218 is repeatedly retried so that the ITB continually reports a page fault until the page fault is recognized by the macroinstmction decoder 230 and subsequent exception handlmg processmg stops and redirects mstmction fetching to a new address The fault indication from the ITB has the same timing as mstructions loaded from the instmction cache 214 and, therefore, is registered in the subsequent decode cycle. The ITB does not necessarily signal a fault on consecutive stmction fetch attempts so that the macroinstruction decoder 230 holds the fault indication until fetching is redirected to a new instmction address. Upon recognition of a page fault, additional fault information is loaded into a special register field The mstmction length greater than sixteen bytes exception, which has a pπoπty just below the mstmction fetch page fault exception, is recognized when the macroinstruction decoder 230 attempts to successfully decode an instruction having a total length including prefix bytes of greater than fifteen bytes. The mstmction length greater than sixteen bytes exception is detected by countmg the number of prefix bytes before an actual mstruction is decoded and computing the length of the rest of the instmction when it is decoded If the sum ofthe prefix bytes and the remaining mstmction length is greater than sixteen bytes, an error is recognized The nonlockable mstmction with a LOCK prefix exception, having a pnonty below the instruction length exception, is recognized when the macroinstmction decoder 230 attempts to successfully decode an mst ction having a LOCK prefix, in which the instmction is not included in the lockable instmction subset. The nonlockable LOCK instruction exception is detected based on decode of the opcode byte and existence ofa OF prefix. The nonlockable LOCK instruction exception only occurs dunng vectoring decode cycles since the LOCK prefix inhibits short and long decodes The floating point not available exception, havmg a next to lowest priority, is recognized when the macroinstmction decoder 230 attempts to successfully decode a WAIT instruction or an ESC instmction that is ont a processor control ESC, and the reporting of a floating point error is pending Macroinstmction decoder 230 detects the floating point not available exception based on decoding of an opcode and modr/m byte, m addition to the existence ofa OF prefix Durmg each decode cycle, the macroinstruction decoder 230 attempts to perform some form of mstmction decode of one or more instructions Typically, the macroinstmction decoder 230 succeeds in performing either one or multiple short decodes, one long decode or an instruction vectoring decode Occasionally no decode is successful for three types of conditions including detection of an active exception condition, lack of a sufficient number of valid bytes in the instmction buffer 408 or the macroinstmction decoder 230 does not advance due to an external reason When an active exception condition is detected all forms of mstruction decode are inhibited and, dunng the second decode cycle after detection of the exception condition, an exception vectormg decode cycle is forced, producing an invalid Op quad When an insufficient number of valid bytes are available in the mstmction buffer 408 either no valid bytes are held in the instruction buffer 408 or at least the first opcode is valid and one of the decoders decodes the mstruction but the decoded mstmction length requires further valid bytes in the instmction buffer 408, not all of which are currently available When an extemal reason prevents macroinstmction decoder 230 advancement either the scheduler 260 is full and unable to accept an additional Op quad dunng a decode cycle or the scheduler 260 is currently acceptmg emulation code Op quads so that the macroinstmction decoder 230 is inactive awaitmg a retum to decoding. In the latter two cases, the decode state ofthe macromstruction decoder 230 is inhibited from advancing and the macroinstmction decoder 230 simply retnes the same decodes m the next decode cycle Control of macromstruction decoder 230 inhibition is based on the generation ofa set of decode valid signals with a signal correspondmg to each ofthe decoders For each decoder tnere are multiple reasons which are combined mto decoder valid signals to determine whether that decoder is able to successfully perform a decode The decoder valid signals for all ofthe decoders are then monitored, in combmation, to determine the type of decode cycle to perform. The type of decode cycle is mdicative ofthe particular decoder to perform the decode The exte al considerations are also appraised to determine whether the selected decode cycle type is to succeed Signals indicative ofthe selected type of decode cycle select between various signals intemal to the macroinstmction decoder 230 generated by the different decoders, such as alternative next decode PC values, and also are applied to control an Op quad multiplexer 444 which selects the input Op quad applied to the scheduler 260 from the Op quads generated by the short decoders, the long decoder 416 and the vectonng decoder 418 In the case of vectonng decode cycles, the macromstruction decoder 230 also generates signals that in ate vectonng to an entry point either intemal emulation code ROM 232 or external emulation code RAM 236. The macroinstmction decoder 230 then monitors the active duration of emulation code fetchmg and loading mto the scheduler 260 The mstruction decoder 220 includes the branch unit (not shown) for performing branch prediction so that operations are speculatively executed Performance of an out-of-order processor is enhanced when branches are handled quickly and accurately so that pipeline-draining mispredictions are avoided The processor 120 employs a two-level branch prediction algorithm that is disclosed in detail in U S Patent No 5,454,1 17, entitled CONFIGURABLE BRANCH PREDICTION FOR A PROCESSOR PERFORMING SPECULATIVE EXECUTION (Puziol et al issued September 26. 1995), U S Patent No 5.327.547. entitled TWO-LEVEL BRANCH PREDICTION CACHE (Stiles et al . issued Julv 5, 1994) U S Patent No 5.163,140, entitled TWO- LEVEL BRANCH PREDICTION CACHE (Stiles et al , issued November 10. 1992), and U S Patent No 5, 093,778. entitled INTEGRATED SINGLE STRUCTURE BRANCH PREDICTION CACHE (Favor et al , issued March 3. 1993) The processor 120 further utilizes an 8.192-entry branch history table (BHT) (not shown) which is mdexed by combining four program counter bits with nine bits of global branch history Each BHT entry contams two history bits The BHT is a dual-port RAM allowing both a read/lookup access and a write/update access BHT lookups and updates do not conflict since they take place in opposite half phases of a clock cycle The large number of entries of the BHT is supplied in a reasonable integrated circuit area because the BHT is only predicting conditional branch directions so that entnes are not tagged and predicted branch target addresses are not stored, except for a 16-entry retum address stack (not shown) Accordingly, an access to the BHT is similar to a direct mapping into a cache-like structure in which the the BHT is mdexed to access an entry in the BHT and the accessed entry is presumed to be a branch instmction For branches other than retums, the target address is calculated dunng the decode cycle The target address is calculated with sufficient speed usmg a plurality of parallel adders (not shown) that calculate all possible target addresses before the location ofa branch instruction is known. By the end of die decode cycle, the branch unit 234 determines which, if any, target address result is valid. If a branch is predicted taken, the target address is immediately known and the target instmctions are fetched on the following cycie. causing a one-cycle taken-branch penalty. The taken-branch penalty is avoided using a branch target buffer (BTB) 456. The BTB 456 inciudes sixteen entries, each entry having sixteen instmction bytes with associated predecode bits. The BTB 456 is indexed by the branch address and is accessed during the decode cycle. Instructions from the BTB 456 are sent to the instmction decoder 220. eliminating the taken-branch penalty, for a cache hit ofthe BTB 456 when the BHT (not shown) predicts a taken branch. During each decode cycle, the linear decode PC 424 is used in a direct-mapped manner to address the BTB 456. If a hit, which is realized before the end ofthe decode cycle, occurs with a BTB entry, a PC-relative conditional transfer control instmction is decoded by a short decoder and the control transfer is predicted taken, then two actions occur. First, the initial target linear fetch address directed to the instmction cache 214 is changed from the actual target address to a value which points to an instmction byte immediately following the valid target bytes contained in the BTB entry. This modified fetch address is contained in the BTB entry and directly accessed from the BTB entry. Second, the instruction byte and predecode information from the entry is loaded into the instmction buffer 408 at the end of the decode cycle. If a PC-relative conditional transfer control instmction is decoded by a short decoder and the control transfer is predicted taken, but a miss occurs, then a new BTB entry is created with the results ofthe target instmction fetch. Specifically, simultaneously with the first successful load of target instmction bytes into the instmction buffer 408 from the instmction cache 214, the same information is loaded into a chosen BTB entry, replacing the previous contents. The target fetch and instruction buffer 408 load otherwise proceed normally. Each entry includes a tag part and a data part. The data part holds sixteen extended instmction bytes including a memory byte and three associated predecode bits. The correspondence of the memory byte is memory- aligned with the corresponding insmiction buffer 408 location. The tag part ofa BTB entry holds a 30-bit tag including the 32-bit linear decode PC 424 associated with the transfer control instmction having a cached target, less bits [4: 1 ], an entry valid bit and the 30-bit modified initial target linear instmction fetch address. No explicit instruction word valid bits are used since the distance between the true target address and the modified target address directly implies the number and designation of valid instruction words within the BTB 456. The puφose of the BTB 456 is to capture branch targets within small to medium sized loops for the time period a loop and nested loops are actively executed. In accordance with this puφose, at detection ofa slightest possibility of an inconsistency, the entire BTB is invalidated and flushed. The BTB 456 is invalidated and flushed upon a miss of the instruction cache 214. any form of invalidation of insmiction cache 214, an ITB miss, or any form of ITB invalidation. Branch targets outside temporal or spatial locality are not effectively cached. Typically, the BTB 456 contains only a small number of entries so that complexity is reduced while the majority of performance benefit of ideal branch target caching is achieved. PC-relative branch target address calculation logic (not shown) performs the target address calculation. Branch target address calculation logic is utilized only for PC-relative transfer control mstmctions mat are decoded by a short decoder SDecO 410. SDecl 414 or SDec2 416 Specifically, the branch target address calculation logic is utilized for the short decode branch instmctions including Jcc dιsp8. LOOP dispδ, JMP dispδ, JMP dιspl6/32, and CALL dιspl6/32 Each short decoder SDecO 410 SDecl 412 and SDec2 414 includes logical and lmear branch target address calculation logic (not shown) All three sets of logical and linear branch target address calculation logic function in parallel while the short decoders 410. 412 and 414 determine whether any ofthe operations is a PC-relative short decode branch instruction The logical and linear branch target address calculation logic sum the logical program counter of he branch, the length ofthe branch instruction and the sign-extended displacement of the branch instmction and conditionally mask the high-order 16 bits ofthe sum. depending on calculation sizing, to produce a logical target address The logical and linear branch target address calculation logic sum the logical target address with the current code segment base address to produce a linear target address If the branch is taken, either unconditionally or predicted taken, then calculated addresses corresponding to the decoded short decode branch instruction are used to reinitialize the logical decode PC 422 and linear decode PC 424 If the branch is predicted not taken, the logical address is saved with the associated short decode branch mstruction (BRCOND Op) in a scheduler 260 Op quad entry The logical target address is compared to the current code segment limit value to monitor for a limit violation If the logical and linear branch target address calculation logic detects a limit violation, whether the branch is predicted taken or predicted not taken, then a special tag bit indicative ofthe limit violation is set the scheduler 260 Op quad entry holdmg the operations generated from the branch instruction Subsequently, when the operation commit unit (OCU) ofthe scheduler 260 attempts to commit this Op quad, the Op quad is handled as contammg a fault and aborted The macromstruction decoder 230 generates signals that initiate vectoring to a fault handler m emulation code ROM 232 The fault handier temporariK inhibits decoding by the short and long decoders and jumps to the fault PC address of the violating mstmction associated with the faulted Op quad Ultimately, the branch mstmction is redecoded and vectored to mstmction emulation code The emulation code recognizes the limit violation if the branch is actually taken and appropπatelv handles the violation The processor 120 generally responds to a fault condition by vectoring to a specific fault handler m the emulation code ROM 232 The fault handler includes operations defined withm the RJSC instmction set which perform a routme that determines the source of the fault an appropriate response to the fault and steps to inmate the appropriate response As an alternative in appropriate cases, the processor 120 also includes a special "load alternate fault handler" operation which initiates a special fault response Exceptions that are detected durmg decode time direct execution to a fixed set of entry points one entry point for each possible exception condition through operation ofthe vectonng decoder 418 which activates the alternate fault handler and designates a fault handier address The alternate fault handier is advantageous for allowing modified full handling of special conditions The load alternate fault handler instruction passes through the instmction decoder 220 pipeline m the manner of all mstmctions, but causes anv subsequent exception condition to mvoke a different vector instruction ROM entry point. The alternate fault handler terminates upon completion of execution ofthe current macroinstmction. One example ofthe advantage of the alternate fault handler arises with respect to a repeated move string instmction (REP MOVs). To perform multiple interations very quickly, a capability to reorder the sequence of operations is important. The sequence of operations typically includes a load to a first pointer-designated address, a store to a second pointer-designated address and, if both the load and store are successful, an increment ofthe first and second pointers and a decrement of a counter. For additional efficiency, the pointers are incremented and the counter decremented before completing the store operation. However, if a fault or exception occurs during the sequence of operations, the sequence is aborted with the counters and pointers in the wrong state. For example, the architectural x86 SI, DI and CX registers do not have the correct value. The alternate fault handier is used by specifying, prior to the sequence, an alternate fault handler that performs a cleanup after a repeated move fault. The sequence proceeds without the overhead of intermediate instmctions for tracking the pointers and counters. If no errors occur, the alternate fault handler terminates without effect. However, if an error occurs, the alternate fault handler is invoked. This alternate fault handier is specific to the particular sequence of operations and performs clean-up accordingly and jumps to the default fault handler. Advantageously, highly efficient code improves speed performance without hindrance from the alternate fault handler until an error arises, at which time the error is addressed. The branch history table (BHT) stores recent history information, particularly branch direction information, about conditional transfer control instmctions that have been encountered in the past. When a branch is repeated, stored information relating to the branch is analyzed to predict the current direction ofthe branch. Subsequently, the stored information is updated based on the actual direction taken by the branch. The stored information is derived from the direction of a particular newly encountered branch, the recent direction history ofthe particular branch and the recent direction history of other branches. The stored infoπnation is based on a plurality of sets of two-bit state machines and also on a direction history ofthe last nine branch executions, whether the last nine branch executions pertained to the particular branch or other branches. The instmction address of the particular newly encountered branch is used to select one of the plurality of sets of two-bit state machines. The direction history of the last nine branch executions is used to select a particular two-bit state machine in the selected set of state machines. Each state machine is a two-bit saturating counter for counting the directions taken by the most recent few branches that accessed this particular state machine. Typically a particular state machine is accessed by the same static branch, although other branches may access the same state machine. A larger state machine value is indicative of more taken instances of a branch. A smaller state machine value is indicative of more not taken instances of a branch. Upon selection of a state machine, the state machine is accessed. If the present overall count is "greater" then a branch is predicted taken. If the present overall count is "lesser" then a branch is predicted not taken. The direction history ofthe most recent nine branch executions is held in a nine-bit shift register which is clocked or shifted each time a branch instmction is successfully decoded. The immediate branch direction just predicted is the new direction history value that is shifted mto the shift register A history bit value of one mdicates a branch taken A history bit value of zero mdicates a branch not taken Durmg a decode cycle, the lmear decode PC 424 is used to perform a BHT table lookup. If a PC-relative branch instmction is decoded, then the accessed state macnine immediately predicts the branch direction, although the actual instmction subsequently fetched and decoded is determined at the end of the decode cycle by the macroinstmction decoder 230 Subsequently, the branch condition (BRCOND) operation generated by decodmg of the conditional branch instruction is resolved by logic the scheduler 260. at which time the state machine is updated If the branch is actually taken, the state machine is decremented unless already at the maximum value (3). If the branch is actually not taken, the state machme is incremented unless already at a mmunum value (0). Accordingly, a state machine value of 0 and 1 respectively mdicate a strong and a mild prediction ofa branch not taken A state machine value of 2 and 3 respectively indicate a mild and a strong prediction ofa branch taken. To support updating of BHT entnes. a copy of the branch address and direction history bits for accessing the BHT and a copy ofthe state machine value are passed to the scheduler 260 along with the branch condition (BRCOND) operation Since a maximum of one BRCOND is included m an Op quad, the BHT support information is tagged to the Op quad applied to the scheduler 260 It is advantageous for reducing circuit size and complexity that the BHT does not contam entry tags (addresses of linear decode PC 424 associated with decoded conditional branches) that are typical in cache structures It is further advantageous that the BHT has a large number of entπes so that the contention rate is low The mformation saved in a scheduler 260 Op quad along with an associated BRCOND operation has a width of fifteen bits mcludmg four branch address bits, nme current history bits, and the immediately accessed two state machine bits, the upper bit of which is also the predicted direction for the immediate branch The first thirteen bits are used, when necessary, to reaccess the BHT and to update a state machine value The final two bits are modified to create the new state machine value When a branch is mispredicted, the set of history values m the nine-bit branch history shift register are corrected to reflect the actual direction taken by the branch Furthermore, the shift register is "shifted back" to correspond to the mispredicted branch, then updated based on the actual branch direction and which branch direction was predicted A retum address stack (RAS) (not shown) is a target address cache for retum (RET) transfer control mstructions RAS is an eight entry, 32-bιt wide, single-ported RAM that is managed as a circular buffer usmg a smgle three-bit pomter During each cycle at most one access, either a read access for a RET decode or a write access for a CALL decode, is performed RAS caches RET retum addresses and predicts retum addresses which inherently specify a target address indirectly, in contrast to other transfer control instructions that contam a direct specification of target address RAS is advantageously utilized since a particular RET instruction often changes target address between different executions ofthe mstmction RAS discovers and anticipates the target address value for each RET instmction execution through monitoπng ofthe return addresses that are saved - pushed on a stack - by CALL instructions. Corresponding CALL and RET instructions typically occur dynamically in pairs and in last-in-first-out LIFO order with respect to other CALL and RET instruction pairs. Each time a CALL instruction is successfully decoded, the logical return address ofthe CALL instmction is saved (pushed) to a circular buffer managed as a LIFO stack. Each time a RET instmction is successfully decoded, the retum address value currently on the top of the RAS is employed as the predicted target address for the RET and the value is popped from the RAS. RAS achieves a high prediction rate although mispredictions do occur because CALLs and RETs do not always occur in nested pairs, only near CALLs and RETs and not far CALLs and RETs are supported, and mispredictions occur because ofthe finite depth ofthe RAS. When a conditional branch misprediction occurs, RAS attempts to restore the state prior to misprediction by setting the top of stack pointer to the previous condition because CALL and RET instmctions may have been speculatively decoded and the top-of- stack pointer thereby modified. The original pointer, before the misprediction, is to be restored. Restoration following a misprediction is supported by the scheduler 260. Each scheduler 260 Op quad is tagged with a current initial top-of-stack pointer value in effect during the decode cycle in which the Op quad was generated. When the BRCOND Op generated for a conditional branch instmction is resolved and found to be mispredicted, the top-of- stack pointer tagged to the scheduler Op quad is supplied to the RAS during a restart cycle that is generated by the scheduler 260. RAS replaces the current top-of-stack value with the scheduler Op quad top-of-stack pointer tag. Refeπing to Figure 5. a schematic block diagram depicts an instruction decoder emulation circuit 231 including an instmction register 512. an entry point circuit 514, an emulation environment register 516, an emulation code sequencer 510, an emulation code memory 520 and an Op substitution circuit 522. The instruction decoder emulation circuit 500 is a circuit within the instmction decoder 220. The instmction decoder emulation circuit 231 receives instruction bytes and associated predecode information from the instruction buffer 408 connected to the insmiction fetch control circuit 218. the BTB 456 or the instruction cache 214. The instruction buffer 408 is connected to and supplies the instmction register 512 with x86 instmctions. The instruction register 512 is connected to the entry point circuit 514 to supply emulation code ROM entry points. The entry point circuit 514 receives the x86 instruction and. from the x86 instruction operation code (opcode), generates an entry point address, a beginning address pointing into the emulation code memory 520. In this manner an address of an instruction in emulation code memory 520 is synthesized from the opcode of an x86 insmiction. The address is derived based on the x86 insmiction byte, particulariy the first and second bytes ofthe x86 insmiction as well as infoimation such as the modem byte, prefixes REP and REPE, the protected mode bit and effective data size bit DSz. Generally, closely related x86 instmctions have similarly coded bit fields, for example a bit field indicative of instmction type is the same among related x86 instructions, so that a single entry in the emulation code memory 520 corresponds to several x86 instmctions. Entry points are generally synthesized by reading the x86 instructions and assigning bits ofthe entry point address according to the values of particular x86 instruction bit fields. The instruction register 512 is connected to the emulation code sequencer 510 which, in tum, is connected to the emulation code memory 520. The emulation code sequencer 510 applies the entry point to the emulation code memory 520 and receives sequencing information from the emulation code memory 520. The emulation code sequencer 510 either controls the sequencing of instructions or, when a new sequence is to be started, applies an entry pomt to the emulation code memory 520 Operations (Ops) encoded in the emulation code memory 520 are ouφut by the emulation code memory 520 to the Op substitution circuit as Op quads or Op units The Ops correspond to a template for RISC-type x86 operation This template includes a plurality of fields mto which codes are selectively substituted The emulation code memory 520 is connected to the Op substitution circuit 522 to supply Ops into which the various Op fields are selectively substituted Functionally, the entry pomt circuit 514 calculates an entry point into the emulation code ROM 232 or emulation code RAM 236 The sequence in emulation code ROM 232 determines the functionality of an instmction The emulation code memory 520 includes an on-chip emulation code ROM 232 and an external emulation code RAM 236 The emulation code memory 520 includes encoded operations that direct how the processor 120 functions and defines how x86 mstmctions are executed Both the emulation code ROM 232 and RAM 236 mclude a plurality of operation (Op) mstmction encodings having a Op coding format that is the same in ROM 232 and RAM 236 For example, in one embodiment the emulation code ROM 232 has a capacity of 4K 64-bιt words. The Op coding format is typically a format defined in 30 to 40-bιts for example In one embodiment, a 38-bιt format, shown in Figures 6A through 6E, is defined The emulation code ROM 232 base address location withm the emulation space is fixed The extemal emulation code RAM 236 is resident in standard memory address space withm cacheable memory The emulation code RAM 236 base address location withm the emulation space is fixed. The 32-bιt emulation code RAM 236 address is formed by the fixed base address ofthe emulation code RAM 236 which supplies bits the most significant fifteen bits <31 17>, and the Op address which furnishes fourteen bits <16 3> concatenated to the base address bits The two least significant bits <1 0> ofthe emulation code RAM address are set to zero The fourteen bit Op address in emulation code RAM 236 is the same as the Op address emulation code ROM 232 Operations (Ops) are stored in Op coding format, for example 38-bιts. in the extemal emulation code RAM 236 in 64-bit words Bits in excess of the Op coding format bits of the 64-bιt words are used to store control transfer (OpSeq) information The extemal emulation code RAM 236 is typically used for test and debug puφoses, allowing for patching of any mstmction encoded in the emulation code ROM 232. and for implementing special functions such as system management mode (SMM) For example, if an instmction emulation code ROM 232 is found to function improperly, the extemal emulation code RAM 236 is accessed to temporarily or permanently substitute for the improperly-functioning fixed code in the emulation code ROM 232. Access to the exte al emulation code RAM 236 is typically gained using one of two techniques In a first technique, a one-bit field m an OpSeq field of an element of emulation code memory 520 designates that the next address for fetchmg mstructions is located in extemal emulation code RAM 236 In this first technique, the on-chip emulation code ROM 232 inmates execution ofthe extemal emulation code RAM 236 In a second technique, a vector address is simply supplied for vectoring to an entry point tn the emulation code RAM 236 The mstruction cache 214, instmction fetch control circuit 218 and instmction decoder 220 function m three mstmction fetch and decode modes In a first mode, the instmction decoder 220 fetches emulation code Op quads from the on-chip emulation code ROM 232 Each Op quad includes four operations (Ops) plus control transfer information (OpSeq) for deteπnining the next cycle of fetch and decode function. In a second mode, the instmction fetch control circuit 218 controls fetching of x86 macroinstruction bytes from the instmction cache 214, which is part ofthe on-chip L 1 mstmction cache 214. The x86 macroinstmctions are decoded by the macroinstmction decoder 230. which generates four operations (Ops). Four Ops plus the OpSeq field form a full Op quad. The instruction decoder 220 performs any coded control transfers using the branch unit 234 and vectoring functionality ofthe macroinstmction decoder 230. In a third mode, the instruction fetch control circuit 218 controls fetching of 64-bit words containing emulation code in Op coding format from the instmction cache 214, one 64-bit word per cycle. Each 64-bit word corresponds to a single operation (Op). In other embodiments, a plurality of 64- bit words may be accessed per cycle. An embodiment in which four 64-bit words are accessed, the emulation code RAM 236 supplies a full Op quad in the manner ofthe on-chip emulation code ROM 232 so that a fully- reprogrammable processor with full efficiency is achieved. A fully-reprogrammable processor advantageously permits soft implementation of greatly differing processors, for example an x86 processor and a PowerPCO in a single hardware. In the first and third operating three modes, control transfer infoπnation is formatted into an operation sequencing (Opseq) field of the Op quad. Unconditional control transfers, such as branch (BR) and retum from emulation (ERET) operations, are controlled completely using the Opseq control transfer information. Conditional transfers, such as branch on condition (BRcc), are controlled using a combination ofthe Opseq field and a branch condition (BRCOND) operation. An OpSeq field format graphic is shown in Figure 7. The 16-bit OpSeq field 700 includes a two-bit sequencing action (ACT) field 710, a smgle-bit extemal emcode field 712 and a 13-bit operation (Op) address field 714. Four sequencing actions in the ACT field 710 are encoded, as follows: ACT Operation Description 0 0 BR/BRcc uncond/cond branch to emcode address 0 1 BSR BSRcc uncond/cond "call" to emcode address 1 0 ERET/ERETcc retum from emulation to instr decoding 1 1 SRET/SRETcc retum from emulation call Whether a sequencing action of an OpSeq is unconditional or conditional depends on the presence or absence, respectively, of a branch condition (BRCOND) Op elsewhere within the Op quad. The BRCOND Op within the Op quad specifies the condition to be tested and the alternate emulation code target address. No explicit static branch direction prediction bit exists, instead the predicted action and next address are always specified by the OpSeq field 700 and the "not predicted" next address is always specified by the BRCOND Op. A BRCOND Op is always paired with a BSR sequencing action including unconditional calls. For unconditional and conditional "predicted-taken" calls, the BRCOND Op specifies the return address to be saved. The external emcode field 712 is set to one if emulation code to be executed is located in extemal emulation code RAM 236. The extemal emcode field 712 is set to zero if emulation code to be executed is located in intemal emulation code ROM 232. The Op address field 714 designates an address of target Op within a non- entry point Op quad. - 31 - The Opseq control transfer information controls unconditional control transfers when an Op quad or 64-bit memory word is fetched and arranged or "instantaneously decoded" Designation ofthe next mstruction to be decoded is controlled by the Opseq field alone The Opseq field specifies one of three alternative actions First, the Opseq field directs fetching of emulation code from emulation code ROM 232 at a specified 14-bιt single operation word address so that an emulation code ROM 232 Op quaα is fetched Second, the Opseq field directs fetchmg of emulation code from emulation code RAM 236 at a specified 14-bit smgle operation word address so that an emulation code RAM 232 64-bit memory word is fetched Third, the Opseq field includes a retum from emulation (ERET) directive, which directs the mstmction decoder 230 to return to x86 microinstruction decoding Emulation code fetched from the emulation code ROM 232 is fetched in the form of aligned Op quads. A branch to an intermediate location within an Op quad causes the preceding operations within the Op quad to be treated as invalid by fetchmg NOOPs in place of the preceding operations The byte memory addresses for fetching 64-bιt memory words from emulation code RAM 236 are created by concatenating a specified 14-bit operation address with three least significant bits set to zero, thereby creating an aligned 8-bιt address The byte memory addresses for fetching 64-bιt memory words are 8-bit aligned, thus rendering memory Op decoding and fetch/decode advancement consistent and simple The Opseq control transfer information also controls designation ofthe immediate next mstmction to be decoded for conditional control transfers The branch condition (BRCOND) operation specifies the condition code to be tested and evaluated and specifies an alternative 14-bit emulation code fetch and decode address Thus, Opseq control transfer information for conditional control transfers effectively specifies the predicted path ofthe conditional branch The BRCOND address typically is either the 14-bit target Op word address or the 14-bit Op word address ofthe next "sequential" operation (Op) More generally, the BRCOND address mav specify a fully general two-wav conditional branch Note that the word sequential is placed in quotation marks to indicate that, although the "sequential" address generally points to an instruction which immediately precedes the present mstmction, the "sequential" address may be set to any addressed location A conditional ERET operation is implemented by setting the Opseq field to specify an ERET operation so that the conditional ERET is predicted taken If the ERET operation is subsequently found to be mispredicted, then the x86 macromstruction stream directed by the ERET is aboπed and the sequential macroinstruction stream specified by the BRCOND operation is restarted BRCOND operations are loaded into the scheduler 260 in an unissued state BRCOND operations are evaluated in-order by the branch resolution unit ofthe scheduler 260 If the branch is properly predicted, the branch is marked Completed Otherwise, the BRCOND state is left unissued and triggers a branch abort signal when detected by the Op commit unit The emulation code memory 520 supports a single-level (no nesting) subroutine functionality, in which an Opseq field is set to specify alternatives for fetchmg emulation code The alternatives are structured as a typical two-way conditional branch, except that a 14-bit Op word address from the immediate field ofa BRCOND Op withm the Op quad or memory Op is loaded into a subroutme return address register. The subroutine retum address register stores the 14-bιt Op word address plus a single bit which designates whether the retum address is located in emulation code ROM 232 or RAM 236 The condition code specified by the BRCOND Op may be any alternative, mcludmg TRUE, so that both unconditional and conditional (predicted-taken) subroutines may be specified However, the BRCOND Op must be specified to avoid loading an undefined value mto the subroutme retum address register All emulation code subroutine support and retum address register management is performed by the emulation code sequencer 510 at the front of the pipeline Thus return address register loading and usage is fully synchronous with standard decoder timmg so that no delavs are introduced Two-Wav Emulation Code Branching The emulation code ROM 232 is storage for a plurality of sequences of operations (Ops) An operation sequence begms at a defined entry point that is hard-coded into the emulation code ROM 232 and extends to a retum from emulation (ERET) Opseq directive that ends the operation sequence The number of operations a sequence is typically variable as is appropriate for performing vaπous different functions Some simple x86 instmctions have only a single Op entry in the emulation code ROM 232, although these instructions are fetched with Op quad granularity Other more complex x86 instructions use many component operations The emulation code ROM 232 storage is stmctured as a plurality of Op quads, programmed into a fixed ROM address space. Each Op quad includes four RISC Op fields and one Opseq field The operation sequences are typically not aligned within the Op quads so that, absent some technique for branchmg to mterspersed locations in emulation code ROM 232. many ROM units in the emulation code ROM 232 are unusable, wasting valuable integrated circuit space Furthermore, because the entry point address of an instruction in emulation code ROM 732 is synthesized from the opcode of an x86 mstmction. the entrv point addresses often are forced into fixed positions spread throughout the ROM address space with intervening gaps that lead to unused portions of ROM ROM positions that are left without access via an entry pomt are free for other usage but are not conveniently sequential to allow access. The OpSeq field provides a technique for branching to these interspersed locations, thereby substantially elimmatmg wasted space Each ofthe four RISC Op fields of an Op quad stores a simple, RISC-like operation The OpSeq field stores a control code that is communicated to the emulation code sequencer 510 and directs the emulation code sequencer 510 to branch to a next location tn the emulation code ROM 232 Each ofthe four RISC Op fields m the emulation code ROM 232 may store a branch operation, either conditional or unconditional, and thereby specify a target address so that a plurality of branches may be encoded in a single Op quad. In some embodiments ofthe instruction decoder emulation circuit 231. the Op quad is limited to having at most a smgle branch operation to direct Op order in combination with the OpSeq field The combination of a conditional branch Op in one ofthe four RISC Op fields and the OpSeq field in an Op quad yields an Op quad with two possible target or next addresses. For an Op quad having a plurality of target addresses, the emulation code sequencer 510 directs the sequence of operations by selecting a hard-coded, predicted target address. Thus, for an Op quad including an conditional branch, the emulation code sequencer 510 selects a hardcoded OpSeq target address in preference over the conditional branch. The unconditional branch is subsequently handled in accordance with the branch prediction functionality of the processor 120 so that no additional branch handling overhead is incurred by implementing two- way emulation code branching. Emulation microcode may be written so that a BRCOND Op is positioned in one ofthe first three positions ofthe Op quad. Thus, the Ops following the BRCOND Op within the Op quad are executed based on the predicted direction rather than whether the branch is ultimately taken. If the branch is ultimately found to be correctly predicted, all ofthe Ops ofthe Op quad and the Ops of subsequent Op quads are committed to the scheduler 260. If the branch is ultimately found to be mispredicted, all of the Ops following the BRCOND Op plus all subsequent Op quads are aborted. The emulation code is supplied to include the branch conditions, a target address, a "sequential" address, and also the prediction for the branch condition. For most instmctions, the OpSeq field alone supplies the next fetch address, either a vector address or an ERET retum. This is advantageous for simplifying the control hardware, supplying a fast and simple control logic that controls operation fetching without analysis of conditional branching or branch prediction. For conditional branch instmctions, the OpSeq field supplies a predicted branch address and a BRCOND operation in the quad specifies a condition code to be evaluated and specifies the alternate fetch address in case of misprediction. The emulation code handling advantageously achieves the flexibility of nonsequential Op quad fetching in which the instruction control sequence is selected by the program with few constraints. Accordingly, the OpSeq field is advantageously used to efficiently fit Op sequences into nonused locations in the emulation code ROM 232. The emulation code handling also includes the flexibility of optional two-way branching in the case of conditional branches and also in the case ofa subroutine call which may be directed to return to substantially any location rather than being constrained to retum to the insmiction following the calling mstmction. This usage of the OpSeq field to branch to a target address advantageously achieves unconditional branching without incurring a time or cycle penalty. Emulation Environment Substitution The emulation code sequencer 510 controls various emulation environment substitutions to substantially expand the number of encoded operations beyond the number of operation entπes in the emulation code ROM 232. The emulation code sequencer 510 includes logic circuits that analyzes specific typically dedicated encodings of an Op field to determine when a substitution is to be made and which substitution is performed. Most encodings directly specify a field value. Other encodings indirectly specify a field value through emulation environment substitution. Usage of emulation mode substitution achieves encoding of CISC functionality while substantially reducing the size of emulation code ROM 232. advantageously reducmg the size and cost ofa processor integrated circuit. The Op fields, includmg the register field and some ofthe size fields, directly specify a register or specify an indirect register specifier such as AX or Tl . Similarly, a field may select RegM which is the direct register specifier The Op substitution logic analyzes the coding for the indirect register specifier to subsequently define the register coding and substitute the register encoding with the current register. The size fields select one byte, two bytes or four bytes, or select a D-size so that the current effective data size replaces the ongmal encoding. The symbols such as HReg represent panicuiar encodings such as HReg_T2 which is a symbolic representation ofthe encoding for T2. Illustrative symbols include Hreg, HDSz. HASz. HSegDescr. HSpecOpType and others. Pseudo-RTL code, as follows, particularly descnbes the emulation environment substitution operation: // Emulation Environment Substitution: // Decode: switch (OpQuad.Ops (I) Tyρe) ( case HOpType RegOp: if ((HReg_Reg & Ox l c) ==(OpQuad.Ops(i).RegOp.Src lReg & Oxlc)) OpQuad.Ops (i) RegOp Src 1 Reg = HReg (uint (DEC_EmReg)); ) if ((HReg_RegM & Ox l c) == (OpQuad.Ops(i) .RegOp.SrclReg & Oxlc)) ( OpQuad.Ops(ι) RegOp.SrclReg = HReg(uιnt(DEC_EmRegm)); ) if(!OpQuad.Ops(i).RegOp I) ( // not immediate if((HReg_Reg & Oxlc) == (OpQuad.Ops(i) .RegOp.Immδ & Oxlc)) OpQuad.Ops(ι).RegOp.Imm8 = DEC_EmReg; if((HReg_RegM & Ox lc) == (OpQuad.Ops(i).RegOp.Imm8 & Oxlc)) OpQuad.Ops(ι) RegOp.Immβ = DEC_EmRegm; ) // not immediate if((HReg_Reg & Ox l c) == (oρQuad.Ops(i).RefOp.DestReg & Ox lc)) ( OpQuad.Ops(ι).RegOp DestReg = HReg(uιnt(DEC_EmReg)); ) ιf((HReg_RegM & Ox l c) == (OpQuad.Ops(i).RegOp.DestReg & Oxlc)) ( OpQuad.Ops(ι) RegOp.DestReg = HReg(uint (DEC EmRegm)); ) if(HDSz_D = OpQuad Ops(ι) RegOp.DSz) ( OpQuad.Ops(ι).RegOp.DSz = DEC_EmDSz ? HDSz_4B : HDSz_2B ) ιf(HDSz_A == OpQuad Ops(ι) RegOp DSz) ( OpQuad.Ops(ι) RegOp.DSz = DEC_EmASz ? HDSz_4B : HDSz_2B ) if(HDSz_S == OpQuad Ops(ι) RegOp.DSz) ( OpQuad.Ops(ι).RegOp.DSz = RUX_B ? HDSz_4B : HDSz_2B; ) break; case HOpType_LdStOp- if((HLdStOpType_LDST == OpQuad.Ops(ι).LdStOp.Type) &.&. DEC_EmLock) ( OpQuad.Ops(ι).LdStOp.Type = HLdStOpType_LDSTL; ) ιf((HReg_Reg & Oxlc) == (OpQuad.Ops(ι).LsStOp.DataReg & Oxlc)) ( OpQuad.Ops(i).LdStOp.DataReg = HReg (uint (DEC_EmReg)); ) if(HReg_RegM & Oxlc) = (OpQuad.Ops(i).LdStOp.DataReg & Oxlc)) ( OpQuad.Ops(i).LdStOp.DataReg = HReg(uint(DEC_EmRegm)); ) if(HDSz_D = OpQuad.Ops(i).LdStOp.DSz) ( OpQuad.Ops(i).LdStOp.DSz=DEC_EmDSz ? HDSz_4BB : HDSz_2B; ) if(HASz_A = OpQuad.Ops(i).LdStOp.ASz) ( OpQuand.Ops(i).LdStOp.ASz = DEC_EmASz ? HASz_4B : HASz_2B ) if(HASz_S = OpQuad.Ops(i).LdStOp.ASz) ( OpQuad.Ops(i).LdStOp.ASz = RUX_B ? HASz_4B : HASz_2B ) if(HASz_D = OpQuad.Ops(i).LdStOp.ASz) ( OpQuad.Ops(i).LdStOp.ASz = DEC_EmDSz ? HASz_4B : HASz_2B ) if(HSegDescr_OS = OpQuad.Ops(i).LdStOp.Seg) ( OpQuad.Ops(i).LdStOp.Seg = HSegDescr (uint(DEC_EmOprSeg)); ) break; case HOpType SpecOp: if(HReg_Reg & Oxlc) = (OpQuad.Ops(i).SpecOp.DestReg & Oxlc)) ( OpQuad.Ops(i).SpecOp.DestReg = HReg(uint(DEC_EmReg)); ) if((HReg_RegM & Oxlc) == (OpQuad.Ops(i).SpecOp.DestReg & Oxlc)) ( OpQuad.Ops(i).SpecOp.DestReg + HReε(uint(DEC_EmRegm)); ) iftΗDSz_D = OpQuad.Ops(i).SpecOp.DSz) ( OpQuad.Ops(i).SpecOp.DSz - DEC EmDSz ? HDSz 4B : HDSz 2B; ) - - - // LDKD Op; if (OpQuad.Ops(i).SpecOp.Type = HSpecOpType_LDKD) ( HVector Imm 17 = OρQuad.Oρs(i).SpecOp.Imm 17 if(DEC_EmDSz) ( Imml7 (5,0) = (Imm 17(4,0) << 1 ) 1 Imm l7 (0); ) OpQuad.Ops(i).SpecOp.Imm 1 17 = Imm 17 (0); ) break; ) ) EDR_OpQuad = OpQuad: EDR_ERET = DEC_EXT Emc ? IC_ERET (OpQuad.Action = HOpSeq_ERET); ) The emulation code sequencer 510 sequences to a next entry point in the emulation code ROM 232, producing an Op quad, including four operations (Ops) and an Opseq field. For each ofthe four operations in an Op quad, various substitutions are made, the type of substitution depending on the particular operation type ofthe five general operation types. The five operation types include register operations (RegOps), load-store operations (LdStOps), load immediate operations (LIMMOps), special operations (SpecOps) and floating point operations (FpOps). Op formats for the five operation types are depicted in Figures 6A through 6E. The Ops that are produced by the emulation code ROM 232 are genenc in nature, in particular, the Ops do not correspond exactly to an x86 mstruction Instead, the Ops from the emulation code ROM 232 form a stmcture for an x86 mstmction Various bit fields within the Op template are substituted usmg a substitution funαion performed by the emulation code sequencer 510 Simply αescπbed. the substitution function substitutes some bits ofthe Op with other selected bits X86 mstmctions typically include an opcode followed by a modr/m byte The modr/m byte designates an mdexmg type or register number to be used in the instruction The modr/m byte has three fields mcludmg a 2-bit (MSB) mode field, a 3-bit (intermediate) reg field and a 3-bit (LSB) r/m field The mode field combines with the r/m field to form 32 possible values indicative of eight registers and 24 indexing modes. The reg field specifies either a register number or three more bits of opcode information The r/m field either specifies a register as the location of an operand or is used combination with the mode field to define registers and indexing modes Figure 6A is a register operation (RegOp) field encoding graphic that illustrates vanous fields m the RegOp format In the RegOp field 610. most-significant bits 36 and 37 are cleared to designate the operation as a RegOp The RegOp field 610 also includes a 6-bit operation type (TYPE) field 612 at bit locations [35.30], a 4-bιt extension (EXT) field 614 at bit locations [2926], a RUl-only (Rl) bit 616 at bit location [25], a 3-bit operation/data size (DSz) field 618 at bit locations [2422], a 5-bit destmation (DEST) general register field 620 at bit locations [2117] and a 5-bit source I (SRC 1 ) general register field 622 at bit locations [1612] The RegOp field 610 also mcludes a single-bit set status (SS) field 624 at bit location [9], a smgle-bit immediate source 2 (I) field 626 at bit location [8] and an 8-bit immediate data or general register for source 2 operands (IMM8/SRC2) field 628 at bit locations [70] The TYPE field 612 of RegOp encodings include, as follows TYPE code Class TYPE DescπDtion 00000 ALU ADD/INC add/increment 00001 ALU MOV/OR move/or (only or if DSz= 1 ) 00010 ALU ADC add with carry 00011 ALU SBB subtract with borrow 00100 ALU AND/EAND.BAND logical and 00101 ALU SUB/ESUB/DEC subtract/decrement 00110 ALU EXOR/XOR exclusive or 00111 ALU CMP compare 01000 SHIFT SLL/BLL logical shift left 01001 SHIFT SRL logical shift πght 01010 SHIFT SLC/RLC shiftrotate left, carry 01011 SHIFT SRCRRC shift/rotate right, borrow 01100 SHIFT SLA aπthmetic shift left 01101 SHIFT SRA arithmetic shift πght 01110 SHIFT SLD/RLD shift/rotate left, double 01111 SHIFT SRDRRD shift/rotate right, double 1 oooo MOVE RDFLG read flag 10001 MOVE SEXT/ZEXT 10010 MOVE RDFLGS 10011 MOVE MOVcc move conditional 10100 MOVE MUL1S/MUL1L [ multiply signed/unsigned 10101 MOVE MULEH/MULEL multiply high/low data 10110 MOVE DIV1/DIV2 divide 1 0 1 1 1 MOVE DIVER/DIVEQ divide 1 1 0 0 0 SPEC RDxxx read special register 1 1 0 0 1 SPEC 1 1 0 1 0 SPEC 1 1 0 1 1 SPEC 1 1 1 0 0 SPEC WROR/WROL write 1 1 1 0 1 SPEC WRxxx write special register 1 1 1 1 0 SPEC CHKS,WRDH check selector, 1 1 1 1 1 SPEC WRIP write instruction pointer Several RegOp encodings, specifically xxOlx encodings, specify condition code dependence. The rotate and shift shift Ops are functionally equivalent except that different statmod bits are asserted. The extension field (EXT) 614 is used, in combination with bit<0> ofthe TYPE field 612, for MOVcc operations to specify a 5-bit condition code. The extension field (EXT) 614 is also used for RDxxx WRxxx operations to specify a 4-bit special register number. The set status (SS) field 624, in combination with the EXT field 614. is used to designate the status flags that are affected by an operation. For Ops in which the set status (SS) field 624 is set to 1. indicating that this Op does modify flags, the extension field (EXT) 614 specifies four status modification bits designating the groups of flags that are modified by the Op. For RDSEG Ops, the EXT field 614 specifies a 4-bit segment (selector) register. For a WRFLG conditional Op, the special register encoding matches die desired StatMod value for when the SS field is set. The set status (SS) field 624 and the EXT field 614 are RegOp fields. Condition codes are encoded in five bits, bit<0> ofthe 5-bit condition code field specifies whether die condition or its complement is to be tested for tmth or assertion, for example if cc<0> is equal to one then invert the condition. Bits <4: 1> ofthe five-bit condition code (CC) field specify the condition to be evaluated, as follows: CC mnemonic condition 0000 Tme 1 000 I ECF ECF 0010 EZF EZF 0011 SZnZF (EZF)# . ZF 0100 MSTRZ EZF.IP . DTF+SSTF 0101 STRZ EZF.IP . DTF+SSTF 0110 MSTRC ECF.IP . DTF+SSTF 0111 STRZnZF EZF.IP . DTF+SSTF . ZF 1000 OF OF 1001 CF CF 1011 CvZF CF+ZF 1100 SF SF 1101 PF PF 1110 SxOF SF?OF 1111 SxOvZF SF?OF?ZF The EXT field 614 is used to update condition flags including six flags corresponding to x86 flags and two emulation flags. The eight flags are divided into four groups, using one status modification bit per group of flags. The EXT field 614 defines updating ofthe various condition code flags substantially independent of the TYPE 612 specification.so that functionally related flags are controlled and updated as a group. Updating of related flags as a group advantageously conserves control logic. The EXT field 614 defines a set of bits which determine the flags to be updated for a particular instruction. Decoupling of condition code handling from operation type, using the independent TYPE 612 and set status (SS) field 624. allows some operationsto be defined which do not update the flags. Accordingly, for those circumstances in which updating of condition flags is not necessary, it is highly advantageousto disable flag updating to avoid unnecessary dependency on previous flag values. The RU 1 -on ly field 616 is indicative of Ops that are issued to the first register unit 244 and not to the second register unit 246 so that the Rl field 616 is a bit for hard-encodingan execution unit specification. Thus, die RUl-only field 616 indicates that a particular operation is only executable on a specific execution unit, generally because only the specific execution unit incoφoratesa function implemented on that unit. The set status (SS) field 624 modifies status flags according to EXT field 614 settings. The I field 626 specifies whether the source 2 operand is immediate or a general register. The IMM8/SRC2 field 628 specifies a 5-bit general register if the I field 626 is zero. The IMM8/SRC2 field 628 specifies a signed immediate value which is extended to the size of operation specified by the DSz field size if the I field 626 is one. In the case of register operation ( RegOp) substitution, the operation (Op) from the Op quad is a register operation (RegOp). The instruction register 512 holds instmction bytes that are decoded by the vectoring decoder 418. During a vectoring instmction decode, the vectoring decoder 418 generates an initial vectoring quad and an entry point address based on the contents ofthe insmiction register 512. At the same time, the vectoring decoder 418 initializes the emulation environment variables, also called the emulation environment register 516, from various infoπnation based on fields of the instmction register 512 and based on other information. Information from the emulation environment register 516 is supplied to Op substitution logic that performs the substitution operation. For RegOp substitution, various substitutions are made into fields ofthe RegOp format 610 shown in Figure 6A. For the destination (DEST) 620 and source 1 (SRC1) 622 fields of a RegOp operation, a five-bit register encoding specifies a register using direct register specifiers (0-15) or indirect register specifiers (Reg and RegM). The direct register specifiers directly designate one of sixteen registers. The indirect specifiers, Reg and RegM, are substituted at Op decode time by the current register numbers (0-15) from the emulation environment registers 516. Substitution takes places as the instmction decoder 230 decode an instmction, vectors to an emulation code sequence in emulation code ROM 232. initialize the emulation environment register 516 with various fields from the instmction and other information. During operation of an emulation code sequence, the Ops in the sequence include various fields, such as indirect register specifier fields and size data fields, which are substituted based on current values ofthe emulation environment register 516. Op substitution logic determines whether the encodings for a field are indicative ofa substituted field. An encoding for a field may indicate that other fields are substituted. For example, the coding of indirect specifiers Reg and RegM in the dest 620 and srcl 622 fields is indicative that the DSz field 618 is also substituted. With respect to the DSz field 618, the x86 instruction set mstructions operate on 8 bit, 16 bit or 32 bit data, depending on the current default condition ofthe processor 120 The DSz field 618 mcludes three bits which indicate a data size of one byte, two bytes or three bytes For mstmctions specifying substitution of data size, mdirect size specifiers designate an A size, D size or S size A data size substitution is determined by a B-bit and a D-bit The B- bit is specified by the current stack-segment register (SS) The D-bit is specified by the code-segment register (CS). For mdirect size specifiers, S size is determined by the B-bit The effective address (A) size and the effective data (D) size are determined by the D-bit. possibly ovemdden ov address or data size overwπte prefixes, and held in the emulation environment register 516 In general, the indirect specifiers of A size. D size, and S size are substituted or replaced by the absolute encoding for the bytes or four bytes For example, if a D size is selected, the data size is resolved into two bytes or four bytes based on the effective data size as specified by a bit in the emulation environment register 516 Similarly, if an indirect size specifier encodes the A size, the effective address size is specified by a bit in the emulation environment register 516 to be either two bytes or four bytes If the mdirect specifier selects the S size, a B-bit determines whether two byte or four bytes are substituted Substitution ofthe Imm8/Src2 field 628 is performed only if source 2 (src2) operand is an mdirect register specifier, rather than an immediate value Op substitution logic determmes whether the encoding for the immediate (I) field 626 is indicative ofa substitution in the Imm8/Src2 field 628 by accessmg the I field bit 626 and, if an mdirect register specifier is selected, substituting a five-bit general register designation into the ιmm8/src2 field 628 of the RegOp format 610 For a register-stored src2 operand usmg the memory-indexed addressing form, no substitution takes place and the ιmm8/src2 field 628 ofthe RegOp format 610 is loaded with an mdex value. The RegOp format 610 is a RISC-type three (two source and one destination) operand format including the srcl field 622. the ιmm8/src2 field 628 and the dest field 620 A standard x86 format is a two operand format The I field 626 advantageouslyallows the source 2 operand to flexibly take the form of either an immediate value or a general register The RegOp field 610 defines a group of specific Ops, includmg signed multiply (MUL 1 S), unsigned multiply (MUL 1 U). multiply high data (MULEH) and multiply low αata (MULEL) Ops. that execute parts of multiplicationand unloadmg operations so that a multiply mstmction is made up ofa plurality of these specific multiplication Ops. A division operation is similarly executed by combmationof a plurality of specific simple division Ops, mcludmg one and two bit divide (DIV 1 ), step divide (DIV2). divide unload remainder (DIVER) and divide unload quotient (DIVEQ) Ops, for example performing a two-bit iteration on a divide The WRIP Op writes the x86 program counter (PC) to change the execution address when the WRIP Op is retired, restarting instruction fetching at a desired address The WRIP Op is particularly advantageous in the case of vaπous instmctions for which decoding of the mstruction length is difficult or impossible so that, to avoid logic complexity, the implemented logic does not correctly decode the length The mstmction is also advantageous for seπalizmg instruction fetch operations and for emulating branches Efficiency is achieved by allowing the logic to incorrectly decode the mstmction length and to set the program counter usmg the WRIP Op so that the incorrectly decode instmction length is ignored The check selector (CHKS) Op is used for handlmg x86 instruction set segment descπptors and selectors. The CHKS Op inmates a process of loadmg a segment register, mcludmg the operations of checking for a null selectorand generating an address offset into a descπptortable Figure 6B is a load-store operation (LdStOp) field encoding graphic that illustrates vaπous fields in the LdStOp format. In the LdStOp field 630 most-significantbits 36 and 37 are respectively set to one and zero to designate the operation as a LdStOp The LdStOp field 630 also mcludes a 4-bιt operation type (TYPE) field 632 at bit locations [35 32], and a two-bit index scale factor (ISF) field 634 at bit locations [31 30] designating factors lx, 2x, 4x and 8 The LdStOp field 630 includes a 4-bit segment register (SEG) field 636 at bit locations [29.26] and a two-bit address calculation size (ASz) field 638 at bit locations [25 24] designating a selection between A size, S size, D size and four bytes. The effective data and address sizes are substituted for LdStOps m the same manner as RegOp substitution The LdStOp field 630 includes a 2-bit data size (DSz) field 640 at bit locations [23.22] specify g sizes (1, 2, 4 and DSize bytes) for integers and sizes (2, 4 and 8 bytes) for floating point, a 5-bιt data source/destmatιon(DATA) general register field 642 at bit locations [21 17] and a single-bit large displacement (LD) bit 644 at bit location [16] specifying a large displacementusmg the Dιsp8 displacement from a precedmg Op The LD bit 644 is useful smce Ops are only 38 bits wide, an mstmction format msufficientto specify a full 32-bit displacement into an operation Only displacements encoded in eight bits are possible for a smgle LdStOp field 630 The LD bit 644, when asserted, mdicates that the immediately preceding Op supplies a full 32-bit displacement The LdStOp field 630 includes a 4-bit base (BASE) general register field 646 at bit locations [15.12] The LdStOp field 630 also includes an 8-bit signed dιspiacement(DISP8) field 648 at bit locations [11 4] and a 4-bιt mdex (INDEX) general register 49 at bit locations [3 0]. The TYPE field 632 of LdStOp encodings mclude, as follows TYPE code TYPE Descnption 0 0 0 0 LD load integer 0 0 0 1 LDF load floating point 0 0 1 0 — 0 0 1 1 — 0 1 0 0 LDL load integer, locked 0 1 0 1 — 0 1 1 0 LDSTL load t w/store check, locked 0 1 1 1 LDST load mt w/store check 1 00 0 ST store teger 1 0 0 1 STF store floatmg point 1 0 1 0 STUPD store int w/ base register update 1 0 1 1 ~ 1 1 0 0 CDA check data effective address 1 1 0 1 CIA check lnstr effective address 1 1 1 0 TIA TLB invalidate address 1 1 1 1 LEA load effective address In the case of load-store operation (LdStOp) substitution, the emulation code sequencer 510 first determmes whether a LOCK prefix has been acknowledged durmg setup ofthe emulation environment If the designated LdStOp operation is a load mteger with store check (LDST) and the LOCK prefix is acknowledged, the emulation code sequencer 510 substitutesa load mteger with store check, locked (LDSTL) opcode for the LDST opcode For LdStOp substitution, various substitutions are made mto fields ofthe LdStOp format 630 shown in Figure 6B For the data register (DataReg) field 642 ofa LdStOp operation, a five-bit register encodmg specifies a register usmg direct register specifiers (0-15) or mdirect register specifiers (Reg and RegM) The direct register specifiers directly designate one of sixteen registers The mdirect specifiers. Reg and RegM, are substituted at Op decode time by the current register numbers (0- 15) from the emulation environment registers 516 Substitution takes places as the mstmction decoder 230 decode an mstruction. vectors to an emulation code sequence in emulation code ROM 232. initialize the emulation environment register 516 with various fields from the mstmction and other mformation Dunng operation of an emulation code sequence, the Ops in the sequence mclude various fields, such as mdirect register specifier fields and size data fields, which are substituted based on current values ofthe emulation environment register 516 Op substitution logic determines whether the encodings for a field are mdicative ofa substituted field An encoding for a field may indicate that other fields are substituted The particular substitution depends on whether the data register (DataReg) 642 is addressed using register addressmg or memory-indexedaddressing If the register addressmg form is designated. DataReg field 642 ofthe LdStOp format 630 is determined by indirect specifier Reg If memory-mdexedaddressing is designated. DataReg field 642 ofthe LdStOp format 630 is determinedby indirect specifier RegM With respect to the ASz field 638 and the DSz field 640, the x86 mstmction set mstructions operate on 8 bit, 16 bit or 32 bit data, depend g on the current default condition of the processor 120 The ASz field 638 and DSz field 640 each mclude two bits which indicate a data size of one byte, two bytes or three bytes For instructions specify mg substitution of data size, mdirect size specifiers designate an A size, D size or S size. A data size substitution is determined by a B-bit and a D-bit The B-bit is specified by the current stack-segment register (SS) The D-bit is specified by the code-segment register (CS) For indirect size specifiers, S size is determined by the B-bit The effective address (A) size and the effective data (D) size are determined by the D-bit, possibly overπdden by address or data size overwrite prefixes, and held in the emulation environment register 516 In general, the mdirect specifiers of A size. D size, and S size are substituted or replaced by the absolute encoding for the bytes or four bytes For example, if a D size is selected, the data size is resolved into two bytes or four bytes based on the effective data size as specified by a bit in the emulation environment register 516 Similarly, if an indirect size specifier encodes the A size, the effective address size is specified by a bit in the emulation environment register 516 to be either two bytes or four bytes If the indirect specifier selects the S size, a B-bit determines whether a two byte or four bytes are substituted The LdStOp operation is checked to determme whether a four-bit segment register field 636 is to be substituted When the emulation environment is set up, segment overnde prefixes are monitored Segment overnde prefixes affect the decode ofa subsequent instruction when the generation ofa LdStOp is dependent on the effective operand segment ofthe mstmction The default segment is DS or SS, depending on the associated general address mode, and is replaced by the segment specified by the last segment override prefix The segment register address space is expanded from conventional x86 specification to four bits to allow additional special segment registers to be support The segment register is encoded as follows SegReg# Seg Descnption 0 0 0 0 ES architectural segment register 0 0 0 1 CS architectural segment register 0 0 1 0 SS architectural segment register 0 0 1 1 DS architectural segment register 0 1 0 0 FS architectural segment register 0 1 0 1 GS architectural segment register 0 1 1 0 HS temporary segment register 0 1 1 1 -- (reserved) 1 0 0 x TS descriptor table SegReg (GDT or LDT) 1 0 1 0 LS linear SegReg (ie, null segmentation) 1 0 1 1 MS emulation memory segment register 1 1 x x OS effective (arch ) data segment register At Op decode time, the emulation code sequencer 510 replaces the "OS" segment register with the current three bit segment register number from the emulation environment Thus, a segment register is alternatively hardcoded in a specific segment register, or set to segment OS which designates the current effective data segment register but which can be overridden with a segment override The emulation memory segment regιster(MS) designates access ofa special emulation memory for usage the emulation environment The descriptor table SegReg TS designates access of either the global descπptortable (GDT) or the local descriptor table (LDT) Figure 6C is a load ιmmedιate operatιon(LIMMOp) field encodιnggraphιcthat ιllustratesvanous fields m the LIMMOp format In the LIMMOp field 650, most-significantbits 36 and 37 are both set to one to designate the operation as a LIMMOp The LIMMOp field 650 also includes a 16-bit immediate high part (I mm Hi) 652 at bit locations [35 20], a 5-bιt destination ( DEST) general register field 654 at bit locations [19 16] and a 16-bit immediate low part (ImmLo) 656 at bit locations [ 15 0] ImmHi 652 and ImmLo 656 combine to specify a 32-bit value that is loaded into the register specified by the DEST field 654 Figure 6D is a special operation ( SpecOp) field encoding graphic that illustrates various fields m the SpecOp format In the SpecOp field 660 most-significantbits 35 to 37 are respectivelyset to 101 to designate the operation as a SpecOp The SpecOp field 660 also includes a 4-bιt operation type (TYPE) field 662 at bit locations [34 31 ], a 5-bit condition code (CC) field 664 at bit locations [30 26] and a two-bit data size (DSz) field 666 at bit locations [23.22] designatingsizes of 1. 4 and DSize bvtes The SpecOp field 660 includes a 5-bit destination general regιster(DEST) field 668 at bit locations [21 17] and a 1 7-bit immediate constant (Imm 17) field 670 at bit locations [ 16 0] The Imm 17 field 670 holds either a 17-bιt signed immediate value or a 14-bit Op address The CC field 664 is only used by BRCOND Ops The DSz field 666 and DEST field 668 are used only by LDKxx Ops A standard NOP Op is defmed to be "LIMM +0,<undefmed> The TYPE field 662 of SpecOp encodings mclude. as follows TYPE code TYPE Description O O x x BRCOND branch condition 0 1 O x LDDHA set default fault handler address 0 1 1 x LDAHA set alternate fault handler address l O O x LDK load constant 1 0 1 x LDKD load constant, data 1 1 x x FAULT unconditional fault In the case of special operation (SpecOp) substitution, the SpecOp is checked to determine wheϋter a destination general register (DestReg) is addressed using register addressing or memory-indexedaddressing. If the register addressing form is designated, the emulation code sequencer 510. up-substitutesa previously stored modr/m reg field from Reg register into the DestReg field 668 ofthe SpecOp format 660 shown in Figure 6D. If the memory- indexed addressing form is designated, the emulation code sequencer 510. up-substitutesa previously stored modr/m regm field from Regm register into the DestReg field 668 ofthe SpecOp format. The SpecOp is also checked to determine whether the data size (DSz) field 666 is to be substituted. A substitution value for the DSz field is determined previous to Op handling by the emulation code sequencer 510 when the emulation environment is defined in accordance with current segment default information as overridden by any operand size overrides. The DSz field 666 is set to a size of 1 byte, 4 bytes or an altemative defined D size. The emulation code sequencer 510 substirutesa designated substitution value into the DSz field 666 ofthe SpecOp format 660. If a SpecOp is a load constant, data (LDKD) operation, the emulation code sequencer 510 adjusts or scales data in the 17-bit immediate (1mm 17) field 670 based on the current effective data size, which is specified by the data size (DSz) field 666. Register Address Space and Emulation interface The processor 120 implements a register address space that is expanded in comparison to a conventional x86 register address space. The processor 120 register address space is addressed by five bits so that 2 3 , or 32, registers may be defined. Eight registers correspond to x86 architectural registers. Sixteen additional temporary registers are added. The data size (DSz) field either directly or indirectly specifies the data size of the operation. For a single-byte operation, a register designated by the register encoding field is different from a two or four byte register designated by the same register encoding field. The data size of an operation may be either one-byte (1 B ) or two/four bytes (2 B /4 β ) for RegOps, SpecOps and the data field 642 of LdStOps. The data size is always two/four bytes (2 B /4 B ) for the base 646 and index 649 fields ofthe LdStOps. The processor 120 register field encoding is. as follows: DSz DSz Setup & Usage REG number 2 fi 4_ S i- Description 0 0 0 0 0 AX/EAX AL 0 0 0 0 1 CX/ECX CL 0 0 0 1 0 DX/EDX DL 0 0 0 1 1 BX/EBX BL 0 0 1 0 0 SP/EPS AH 0 0 1 0 I BP/EBP CH 0 0 1 I 0 SI ESI DH 00 1 1 1 DI/EDI BH 0 1 0 0 0 tl tlL disp32 0 1 0 0 1 12 t2L imm32 0 1 0 1 0 t3 OL address temp 0 1 0 1 1 t4 t4L address temp 0 1 1 0 0 t5 tlH address temp 0 1 1 0 1 t6 t2H modr/m effective address 0 1 1 1 0 t7 t3H next decode PC (seq or ret) 0 1 1 1 1 tO/- t4H 1 0 0 0 t8 t8L intermediate data temp 1 0 0 0 1 t9 t9L lmtermediate dau temp 1 0 0 1 0 tlO tlOL intermediate data temp 1 0 0 1 1 ti l tl lL intermediate data temp 1 0 1 0 0 tl2 t8H intermediate data temp 1 0 1 0 1 tl3 t9H intermediate data temp 1 0 1 1 0 tl4 tlOH intermediate data temp 1 0 1 1 1 tl5 tl IH data save temp 1 I 0 x x reg reg 1 1 1 x x regm regm The intermediate data temporary registers are used, beginning with t8 in order of value derivation or ttle- endian significance The "reg" and 'regm" register numbers are replaced at Op decode time by the current three bit register number from the emulation environment, specifically by substituting Reg/RegM with "OOxxx" The three- bits designate a register from among the first eight registers (AX through DI) The organization of the Op formats and the expanded register address space define a flexible internal microarchitectural state ofthe processor 120 The x86 architectural state is merely a subset of the processor 120 microarchitectural state The expanded register address space mcludes an expanded number of temporary registers, as compared to the x86 register address space Twenty-four registers are supplied by the expanded register address space ofthe processor 120, only eight of these registers correspond to the x86 architectural registers and sixteen additional temporary registers are supplied Similarly, the processor 120 mcludes an expanded number of flag registers, only some of which correspond to the x86 status flags For example, in one processor 120 embodiment, an emulation carry flag is defined in addition to the conventional carry flag and associated with the emulation environment Thus, a conventional add instmction is defined that sets the carry flag and changes the permanent architectural state ofthe processor 120 An emulation add operation is defined that sets the emulation carry flag and not the conventional carry flag Vaπous mstmctions are defined to branch on the basis ofthe emulation carry flag while other mstmctions branch on the basis ofthe conventional carry flag Thus, the processor 120 is concurrently operational in both a conventional microarchitectural state and in an emulation microarchitectural state This operation in an emulation environment allows the processor 120 to execute an emulation microsequence and to not change the visible microarchitectural state Referπng to Figure 8, the substitution technique is illustrated by a specific example An ADD register mstmction in the x86 mstmction set is encoded as an opcode followed by a modr/m byte The 8-bit opcode field of the ADD instmction. in combination with specification in the modr/m byte that the mstmction is a register instruction, are used to derive a particular ROM entry point that causes the emulation code ROM 232 to produce an Op for an ADD RegM to Reg operation The reg and regm fields m the mstmction register 512 specify that reg becomes AX and regm becomes BX. respectively The reg and regm fields are applied from the mstmction register 512 to the Op substitution circuit 522 so that substitution is achieved The emulation code ROM 232 includes Op templates for only a limited number of Ops and the Op substitution circuit 522 fills the templates variously to generate a large number of different Ops Referπng to the listed processor 120 register field encodings, register AX is hard-specified by a reg code, 0 0 0 0 0 Alternatively, four possible reg encodings, 1 1 0 x x, specify substitution ofa register. The substitution is made based on the particular mstruction emulated and the current state ofthe processor 120 mcludmg the current emulation environment. Generally, a substitution and execution of an operation is performed by substituting: (1) an encoding for a Reg mto the dest field 620, (2) an encodmg for a register Reg into the srcl field 622, (3) an encoding for a RegM into the Imm8/Src2 field 628. (4) a zero into the immediate (I) field 626, and (5) either the one, two or four bytes designated by the data size mto the DSz field 618 SYSTEM DISCLOSURE TEXT A wide variety of computer system configurations are envisioned, each embodying an mstruction decoder including emulation using mdirect specifiers in accordance with the present invention. For example, such a computer system (e.g., computer system 1000) mcludes a processor 100 providmg an mstmction decoder including emulation using mdirect specifiers in accordance with the present invention, a memory subsystem (e g., RAM 1020), a display adapter 1010, disk controller/adapter 1030, various input output interfaces and adapters (e.g., parallel interface 1009, serial mterface 1008, LAN adapter 1007, etc.), and correspondmg extemal devices (e.g., display device 1001, printer 1002, modem 1003, keyboard 1006, and data storage). Data storage mcludes such devices as hard disk 1032, floppy disk 1031, a tape unit, a CD-ROM, a jukebox, a redundant array of mexpensive disks (RAID), a flash memory, etc While the invention has been described with reference to various embodiments, it will be understood that these embodiments are illustrative and that the scope of the invention is not limited to them Many variations, modifications, additions, and improvements ofthe embodiments described are possible Additionally, structures and functionality presented as hardware m the exemplary embodunent may be implemented as software, firmware, or microcode m altemative embodmients For example, the description depicts a macromstruction decoder havmg short decode pathways mcludmg three rotators 430, 432 and 434, three mstruction registers 450. 452 and 454 and three short decoders SDecO 410, SDecl 412 and SDec2 414 In other embodiments, different numbers of short decoder pathways are employed. A decoder that employs two decoding pathways is highly suitable These and other vaπations, modifications, additions, and improvements may fall within the scope of the invention as defined m the claims which follow

Claims: WE CLAIM: 1 An instmction decoder emulation circuit in a processor compnsmg an mstmction register for holdmg an insmiction code, the mstmction register havmg a plurality of encoded bit fields within the instmction code. an entry pomt circuit coupled to the instmction register to receive an mstmction code, the entry pomt circuit for deriving an entry point from the instmction code, an emulation code sequencer coupled to the entry point circuit to receive die denved entry pomt, the emulation code sequencer for directing a sequence of operations (Ops) and generating direction signals in accordance with the directed sequence. an emulation code memory coupled to the emulation code sequencer to receive the direction signals, me emulation code memory storing a plurality of Op sequences and sequence control codes, the emulation code memory having a first output terminal for ouφuttmg Op sequences and a second ouφut terminal for outputting sequence control codes, the sequence control code ouφut term mal being coupled to the emulation code sequencer, and an operation (Op) substitution circuit coupled to the emulation code memory first ouφut term mal to receive an Op sequence and coupled to the instruction register to receive selected encoded bit fields ofthe instmction code, the Op substitution circuit for substituting selected fields ofthe instmction code bit fields into the Op sequence 2 The instmction decoder emulation circuit in accordance with Claim 1, wherein the instruction register includes a plurality of fields with a field being set from a combination ofa current instruction and a current state of the processor including an emulation environment 3 The mstruction decoder emulation circuit in accordance with Claim 1 wherein the emulation environment loads a modr/m reg field into a Reg register and a modr/m regm field mto a Regm register and the Op substitution circuit substitutes the Reg and RegM registers mto selected fields ofthe mstruction code bit fields of the Op sequence so that the emulation code memory mcludes a single ROM entry point for generatmg Ops operating upon a plurality of different register specifications 4 The mstruction decoder emulation circuit m accordance with Claim 1 wherem the emulation environment loads a data size specification and the Op substitution circuit substitutes the data size specification mto a data size field of the mstruction code bit fields of the Op sequence so that the emulation code memory mcludes a smgle ROM entry point for generating Ops operating upon a plurality of different data sizes 5 The mstmction decoder emulation circuit in accordance with Claim 1 wherem the emulation environment loads a memory segment descπptor and the Op substitution circuit substitutes the memory segment descπptor into a segment descπptor field ofthe mstruction code bit fields of the Op sequence so that die emulation code memory mcludes a smgle ROM entry pomt for generatmg Ops operatmg m a plurality of different memory segments 6 The mstmction decoder emulation circuit m accordance with Claun 1 wherem the emulation environment loads an address size specification and the Op substitution circuit substitutes the address size specification into an ASz field 7 The mstmction decoder emulation circuit in accordance with Claim 1 wherem the emulation environment loads a data size specification and the Op substitution circuit substitutes the data size specification into an DSz field 8 A method of operating an mstmction decoder emulation circuit in a processor compnsmg the steps of. receiving an instruction code into an instruction register, the insmiction register having a plurality of encoded bit fields within the instruction code, selectively updating various ones ofthe plurality of encoded bit fields in accordance wim a processor state; deπvmg an entry point from the instruction code. addressing an emulation code memory according to the denved entry point, the emulation code memory storing a plurality of Op sequences, ouφutting an addressed operation from the emulation code memory, and substituting selected encoded bit fields ofthe mstruction code mto the addressed operation 9 An instruction decoder in a superscalar processor, compnsmg a plurality of first type macroinstmction decoders for simultaneously decodmg a plurality of instructions m a predetermined group of first type mstmctions. and an emulation ROM decoder coupled to the plurality of macroinstmction decoders mcludmg an mstmction register for holdmg an mst ction code, the mstmction register having a plurality of encoded bit fields withm the mstmction code, an entry pomt circuit coupled to the mstmction register to receive an mstmction code, the entry pomt circuit for deriving an entry pomt from the mstruction code, an emulation code sequencer coupled to the entry point circuit to receive the denved entry pomt, the emulation code sequencer for directing a sequence of operations (Ops) and generating direction signals in accordance with the directed sequence, an emulation code memory coupled to the emulation code sequencer to receive the direction signals, the emulation code memory stonng a plurality of Op sequences and sequence control codes, me emulation code memory havmg a first ouφut terminal for ouφutting Op sequences and a second ouφut terminal for outputtmg sequence control codes, the sequence control code ouφut term mal bemg coupled to the emulation code sequencer; and an operation (Op) substitution circuit coupled to the emulation code memory first ouφut teπninal to receive an Op sequence and coupled to die instmction register to receive selected encoded bit fields ofthe instmction code, the Op substitution circuit for substituting selected fields of the instruction code bit fields into the Op sequence. 10. An instmction decoder emulation circuit in a processor comprising: an instmction register for holding an instmction code, die instruction register having a plurality of encoded bit fields within the instmction code; means coupled to the instruction register for receiving an instmction code and deriving an entry point from the instruction code; means coupled to the entry point deriving means for receiving the derived entry point and directing a . sequence of operations (Ops); means coupled to the receiving and directing means for generating direction signals in accordance with the directed sequence: an emulation code memory coupled to the direction signal generating means for storing a plurality of Op sequences and sequence control codes, the emulation code memory for ouφutting Op sequences and for ouφutting sequence control codes, the sequence control code ouφut terminal being coupled to the emulation code sequencer, and an operation (Op) substitution circuit coupled to the emulation code memory to receive an Op sequence and coupled to the instmction register to receive selected encoded bit fields ofthe instmction code, the Op substitution circuit for substituting selected fields ofthe insmiction code bit fields into the Op sequence. 1 1. The instmction decoder emulation circuit in accordance with Claim 10, wherein the instmction register includes a plurality of fields with a field being set from a combination ofa current instmction and a current state of the processor including an emulation environment. 12. The instruction decoder emulation circuit in accordance with Claim 10 wherein the emulation environment loads a modr/m reg field into a Reg register and a modr/m regm field into a Regm register and the Op substitution circuit substitutes the Reg and Regm registers into selected fields ofthe instmction code bit fields of the Op sequence so that die emulation code memory includes a single ROM entry point for generating Ops operating upon a plurality of different register specifications. 13. The instmction decoder emulation circuit in accordance with Claim 10 wherein the emulation environment loads a data size specification and the Op substitution circuit substitutes the data size specification into a data size field ofthe instmction code bit fields of the Op sequence so that me emulation code memory inciudes a single ROM entry point for generating Ops operating upon a plurality of different data sizes. 14. The instmction decoder emulation circuit in accordance with Claim 10 wherein the emulation environment loads a memory segment descriptor and die Op substitution circuit substitutes the memory segment descriptor into a segment descriptor field ofthe instmction code bit fields of the Op sequence so that the emulation code memory includes a single ROM entry point for generating Ops operating in a plurality of different memory segments. 15. The instmction decoder emulation circuit in accordance with Claim 10 wherein the emulation environment loads an address size specification and the Op substitution circuit substitutes the address size specification into an ASz field. 16. The instmction decoder emulation circuit in accordance with Claim 10 wherein the emulation environment loads a data size specification and the Op substitution circuit substitutes the data size specification into an DSz field. 17. An instmction decoder in a superscalar processor for converting CISC-type instmctions to RISC-type operations, comprising: a plurality of first type macroinstmction decoders for simultaneously decoding a plurality of CISC-type instmctions in a predetermined group of first CISC-type instmctions; and an emulation ROM decoder coupled to the plurality of macroinstmction decoders for decoding a second CISC-type insmiction to RISC type operations, die emulation ROM decoder including: an instmction register for holding a second CISC-type instmction code, die instmction register having a plurality of encoded bit fields within the instmction code; an entry point circuit coupled to the instmction register to receive a second CISC-type instmction code, the entry point circuit for deriving an entry point from the second CISC-type instmction code; an emulation code sequencer coupled to the entry point circuit to receive the derived entry point, the emulation code sequencer for directing a sequence of operations (Ops) and generating direction signals in accordance with the directed sequence; an emulation code memory coupled to the emulation code sequencer to receive the direction signals, the emulation code memory storing a plurality of Op sequences and sequence control codes, d e emulation code memory having a first ouφut terminal for ouφutting Op sequences and a second ouφut terminal for outputting sequence control codes, the sequence control code ouφut terminal being coupled to the emulation code sequencer; and an operation (Op) substitution circuit coupled to the emulation code memory first ouφut terminal to receive an Op sequence and coupled to the instmction register to receive selected encoded bit fields ofthe mstmction code, the Op substitution circuit for substituting selected fields of the mstmction code bit fields mto the Op sequence. 18. A computer system compnsing a memory subsystem which stores data and mstmctions. and a processor operably coupled to access the data and instmctions stored m the memory subsystem, wherem the processor mcludes an mstruction decoder further mcludmg a plurality of first type macromstruction decoders for simultaneously decodmg a plurality of instmctions in a predetermined group of first type instmctions; and an emulation ROM decoder coupled to the plurality of macromstruction decoders includmg: an mstruction register for holdmg an mstmction code, die mstmction register having a plurality of encoded bit fields within the msmiction code, an entry point circuit coupled to the mstruction register to receive an mstmction code, the entry pomt circuit for deriving an entry pomt from the mstmction code, an emulation code sequencer coupled to the entry pomt circuit to receive the denved entry point, the emulation code sequencer for directing a sequence of operations (Ops) and generating direction signals m accordance with the directed sequence; an emulation code memory coupled to the emulation code sequencer to receive the direction signals, the emulation code memory stonng a plurality of Op sequences and sequence control codes, die emulation code memory havmg a first ouφut terminal for outputting Op sequences and a second ouφut terminal for outputting sequence control codes, the sequence control code ouφut terminal being coupled to the emulation code sequencer; and an operation (Op) substitution circuit coupled to the emulation code memory first ouφut terminal to receive an Op sequence and coupled to the mstmction register to receive selected encoded bit fields ofthe mstmction code, the Op substitution circuit for substituting selected fields ofthe mstmction code bit fields mto die Op sequence 19 In a processor having a decoder, the decoder bemg characteπzed that die decoder mcludes an mst ction decoder emulation circuit compnsmg an mstmction register for holdmg an mstmction code, the mstmction register having a plurality of encoded bit fields withm the instmction code, an entry pomt circuit coupled to the instruction register to receive an mstmction code, the entry pomt circuit for deriving an entry pomt from the mstruction code, an emulation code sequencer coupled to die entry pomt circuit to receive the denved entry pomt, me emulation code sequencer for directing a sequence of operations (Ops) and generatmg direction signals xn accordance with the directed sequence, an emulation code memory coupled to the emulation code sequencer to receive the direction signals, me emulation code memory storing a plurality of Op sequences and sequence control codes, the emulation code memory having a first ouφut ter inal for outputting Op sequences and a second ouφut terminal for ouφutting sequence control codes, the sequence control code ouφut terminal being coupled to the emulation code sequencer; and an operation (Op) substitution circuit coupled to the emulation code memory first output terminal to receive an Op sequence and coupled to the instruction register to receive selected encoded bit fields ofthe instruction code, the Op substitution circuit for substituting selected fields ofthe instmction code bit fields into die Op sequence.

Inventors: FAVOR JOHN G, FAVOR, JOHN, G.
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1996
Main classification: G06F9
IPC codes: G06F9