APPARATUS AND METHOD FOR EFFICIENTLY DETERMINING ADDRESSES FOR MISALIGNED DATA STORED IN MEMORY

Abstract: An apparatus and method for efficiently generating the consecutive addresses needed to access misaligned or doubleword length data stored in the memory of a general purpose microprocessor. The apparatus shares the address generation operations between a small 3 bit adder, typically contained in the bus unit, and the execution unit. Control logic is used to determine whether a data misalignment situation exists based on the length of the data which is to be retrieved and the starting address of the data. When misalignment is indicated, the control unit acts to assign the address calculations to either the 3 bit adder or the execution unit depending upon how much the present address must be incremented to obtain the new addresses.

Description: APPARATUS AND METHOD FOR EFFICIENTLY DETERMINING ADDRESSES FOR MISALIGNED DATA STORED IN MEMORY TECHNICAL FIELD The present invention relates to the accessing of data stored in the memory of a computer, and more specifically, to an apparatus and method for efficiently determining the sequential addresses used to access misaligned data stored in the memory of a microprocessor. BACKGROUND OF THE INVENTION A general purpose computer typically has its memory space divided into multiple data storage locations, each of which is accessed by means of an address which corresponds to that location. The memory locations can be used for storing an application program, data to be used in executing a program, or a stack which stores return addresses, parameters passed by a calling routine, and temporary variables assigned by a routine. In many computers the memory locations are aligned at the boundaries of 16 bit words, with the location consisting of two 8 bit (1 byte) half-words. In a computer having memory locations aligned at the boundaries of 32 bit words, the memory location is composed of two 16 bit half-words. This means that each unique address specifies a memory location which consists of a 16 bit or 32 bit wide memory space for the storage of data. A bus is used to send addresses to the memory and transfer the data contained at the memory locations corresponding to those addresses to the microprocessor. In some situations the computer architecture may be designed such that the data width of the bus is less than that of the memory locations. For example, a bus may have a width of 16 bits and be used in an architecture which uses 32 bit wide memory spaces. In such a case, if it was desired to read a piece of data 32 bits long, then at least two memory accesses would be required. A first memory access would transfer the first 16 bits of the data and a second memory access would transfer the last 16 bits of the data. As will be discussed, depending on how the data is aligned in memory, this may require generating more than one address in order to retrieve the data from memory. When accessing the memory, a single address typically corresponds to both half-words at the location associated with that address. In the case of a 32 bit wide bus with the data stored in memory so that all 32 bits are stored at the two half-words corresponding to the same memory location, than a single memory address can be used to access the data. In this case, a single memory access at address K would retrieve both half-word 0 and half-word 1 at that location. If the data width of the bus is 16 bits instead of 32 bits, then multiple memory accesses would be needed to retrieve the entire 32 bits of data. In such a case, a first memory access would have an address of K and would access half-word 0 at that location, while a second access would have an address of K and would access half-word I at that location. Note that in the case of a 16 bit wide memory location, where both half-words (bytes) are stored at the two half-words corresponding to the same memory location, than a single memory address can be used to access the data in the case of a 16 or 32 bit wide bus. However, in some situations multiple addresses must be generated in order to perform multiple accesses of memory. One situation in which this occurs is when data is misaligned in memory. This refers to the situation in which the data is not aligned so that it starts with the beginning byte or half- word of an address location. As an example, with a 16 bit wide memory location and a 2 byte sized piece of data to be accessed, if the data is aligned in memory such that the first byte is located at byte 1 of address location K while the second byte is located at byte 0 of address location K+2, then two memory addresses will be required to read the data and transfer it out of memory. The first memory access would be at address location K, byte I , followed by a second memory access at location K+2, byte 0. In this situation, the computer must access two consecutive regions of memory (and hence compute two different addresses) in order to retrieve the data. Note that if the data had been properly aligned with the partitioned memory regions, then only one access at location K, bytes 0 and 1 would be required. A similar problem to that encountered with misaligned data occurs when doubleword length data (32 bits long in the case of 16 bit wide memory locations and 64 bits long in the case of 32 bit wide memory locations) is placed in memory and aligned at either the zero-th or first byte of a memory location. In such a case, the length of the data is such that at least two memory locations are needed to store the data. This requires the generation of multiple memory addresses in order to complete the task of retrieving the data. The generation of multiple memory addresses for use in accessing misaligned data degrades the performance of a computer because it requires additional clock cycles to access the data. It also requires special control circuitry and additional hardware to implement. This can significantly increase the processing overhead (exception logic, address translation logic, etc.) when data processing instructions attempt to access misaligned data. For these reasons, many modern computers do not permit access to misaligned data. Instead, these systems utilize a complex alignment network to prevent misalignment of data. Although accessing doubleword length data is not the same situation as misaligned data, it does present the same challenge, i.e., the need to efficiently generate multiple memory addresses. In those computer systems which allow access to misaligned data, the consecutive memory addresses needed to access the data are typically generated by using a full adder or incrementor in the bus unit. Another approach used is to generate the addresses using the execution unit's arithmetic logic units. Using a full adder or incrementor in the bus unit to solve the misalignment problem has the result of increasing the complexity, size, and cost of the product. If instead the execution unit is used to generate the addresses, then the efficiency of the overall system is sacrificed because the address generation keeps the execution unit busy during times when it could be put to other uses. What is desired is a means of generating the consecutive addresses needed to access misaligned or doubleword length data stored in the memory of a general purpose microprocessor which is more efficient and results in a less complex system than the approaches currently used. SUMMARY OF THE INVENTION The present invention is directed to an apparatus and method for efficiently generating the consecutive addresses needed to access misaligned or doubleword length data stored in the memory of a general purpose microprocessor. The apparatus shares the address generation operations between a small 3 bit adder, typically contained in the bus unit, and the execution unit. Control logic is used to determine whether a data misalignment situation exists based on the length of the data which is to be retrieved and the starting address of the data. When data misalignment is indicated, the control unit acts to assign the address calculations to either the 3 bit adder or the execution unit depending upon how much the present address must be incremented to obtain the new addresses. If the misaligned address is within an eight byte boundary, then the 3 bit adder is used. When the misaligned address is larger, the execution unit is used to perform the address calculation. As most address calculations can be performed with the 3 bit adder, this approach frees up the execution unit to perform other tasks. Further objects and advantages of the present invention will become apparent from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of the architecture of a microprocessor which includes apparatus for efficiently generating addresses for accessing misaligned data according to the method of the present invention. Fig. 2 is a detailed diagram showing the portions of the architecture of the microprocessor of Fig. 1 which are used to generate addresses for accessing misaligned data according to the method of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Fig. 1 is a block diagram of the architecture of a microprocessor 1 which includes apparatus for efficiently generating addresses for accessing misaligned data according to the method of the present invention. Although the figure shows the basic elements of a particular microprocessor architecture, it is intended only for purposes of example. The apparatus and method of the present invention may be implemented in other forms and are applicable to general purpose microprocessors having different architectures. The microprocessor architecture of figure 1 employs a three stage pipeline using microprogrammed control. The three primary stages of the pipeline are the decode, execute and writeback stages. The decode stage contains the decode unit 10, the prefetch buffer 12, the instruction cache 14, and the icrosequencer 16. Prefetch buffer 12 is 16 bytes wide and is designed as a two tier unit. Prefetch unit 12 acts to keep instruction decoder 10 fully supplied with all the bytes of the instruction it is currently decoding. Prefetch unit 12 interfaces with instruction cache 14 and is designed to fetch ahead of the decode stage. This look-ahead mechanism improves the efficiency with which the microprocessor operates. Instruction cache 14 contains 1 K bytes organized as a direct map with a line size of 8 bytes. Cache 14 checks on the bus to avoid stale data due to self modifying code. Decoder 10 is capable of decoding simple instructions in a single cycle. Prefixes and complex instructions can take more than one cycle to decode. Microsequencer 16 steps through the decoded microcode for the instructions. The execute stage fetches operands and executes the instructions, and also computes the memory addresses. Most microprocessor architectures make use of a segmented memory space, with many addressing modes being used to access this space. The use of a segmented memory space means that to obtain the physical address that actually goes on the bus, at least one addition must be performed, that of the segment base and the offset within that segment. This can be further complicated by the computation of the segment offset, which can have up to three parts; a base, an index, and a displacement. As noted, execution unit 18 performs the address computation. Segment limit checking is also done at this point to prevent segment overruns. The computed linear address is sent to bus unit 20 for dispatch to the external world. The execute stage also utilizes the architectural register file 22 and protection logic unit 24. Register file 22 resolves the source and destination information for all the operations performed in the execute stage. It also allows bypassing of results from either the output of the arithmetic and logic unit (ALU) contained in execution unit 18 or from a load operation from memory. This helps to reduce pipeline backups due to data dependencies. The writeback stage includes bus interface unit 20, debug logic unit 26 and register writeback logic. In this stage the memory access is initiated and completed. An update of register file 22 is also performed. A second writeback substage permits the completion of an independent register operation, out of order, while a memory write access is pending. In this architecture the memory access is pipelined, which allows a new read/write operation to be initiated every cycle. As indicated in figure 1, the microprocessor core is divided into 1 1 blocks. These blocks are the prefetch unit 12, decoder unit 10, microsequencer 16, register file unit 22, execution unit 18, protection logic unit 24, exception logic unit 28, debug logic unit 26, bus unit 20, global control unit 30, and instruction cache 14. Prefetch unit 12 consists of two eight byte registers that are filled in from either instruction cache 14 or directly from memory. Decode unit 10 gets an instruction from prefetch unit 12 and generates the entry microcode address for the instruction, register addresses, immediate values, displacement values and segment information. Decoder 10 also generates information for some of the exceptions. Microsequencer 16 controls the process of stepping through the instruction microcode. It generates the next microcode address and performs the look-ups in the micro(code) ROM. The micro-ROM address can come from decoder 10 if a new instruction is started, from the microcode if the present instruction is not finished, or from exception logic unit 28 in the case of exceptions. Register file unit 22 reads the operands, resolves the bypasses, generates constants, and aligns operands for an instruction. The architecture registers and the selectors (i.e., the segment look-up registers) are implemented in this block. Registers contained in register file unit 22 can be accessed either as a single byte, a word (2 bytes), or a doubleword (4 bytes). Execution unit 18 has two major functions. One is to perform all the arithmetic and logic operations. For this function, execution unit 18 has an arithmetic and logic unit (ALU) and a barrel shifter. The second function(s) of execution unit 18 are address computation (linear address generation) and limit checking. Bus unit 20 is the interface between the microprocessor core and the external world. An important feature of this unit is the ability to support pipelined memory access where a memory access is initiated before the previous one has finished. In this mode, the external DRAMs which constitute the memory are divided into pages, typically 4 K bytes long. As long as an access is within one page in the DRAM, single cycle reads and writes to memory can be sustained. If a page miss occurs, then it takes 3 cycles to complete that access. DRAM, SRAM and ROM accesses can also be supported with wait states and non- pipelined memory accesses. Global control unit 30 is the supervisor of the entire architecture. This unit controls the stepping of the instruction pipeline. Interlocks, control of the exception handling, and process shutdown are also handled by this unit. Exception logic unit 28 prioritizes and resolves all the exceptions and external interrupts. This includes the software interrupts, arithmetic exceptions, protected mode exceptions, and other faults and traps. Protection logic unit 24 is responsible for any protection mechanisms implemented in the architecture. Debug logic unit 26 includes all the debug registers and implements the instruction and data breakpoints. Fig. 2 is a detailed diagram showing the portions of the architecture of microprocessor 1 of figure I which are used to generate addresses for accessing misaligned or doubleword length data according to the method of the present invention. The dotted box labelled 18 contains elements of the microprocessor architecture which are typically contained in the execution unit, while the box labelled 20 contains elements typically found in the bus unit. Data paths 100 and 102 provide data from the decoder 10 or register file 22 (shown in figure 1) which is input to elements 106 and 104, respectively. Elements 104 and 106 are shown as two-input- single-output logic elements or switches. They typically take the form of a data multiplexer, with control logic selecting which of the two inputs is routed out of the element as the output. The outputs of elements 104 and 106 provide the inputs to arithmetic logic unit (ALU) 110. In the preferred embodiment of the present invention, ALU 110 is principally used to implement adding operations. The outputs of elements 104 and 106 (which in most instances is the data provided along data paths 100 and 102) are used by ALU 110 to calculate the address in memory which is accessed for the purpose of writing data to memory or reading data from memory. Depending upon the addressing mode being used, the data may consist of an offset value, displacement value, or other term used in computing a memory address. ALU 110 is used to compute the sum of the data input to that unit. This value represents the total offset amount from a base address for the memory location which is to be accessed. The output of ALU 110 is provided as an input to arithmetic logic unit (ALU) 112. The output of ALU 110 is also provided as an input to register 134. The output of register 134 serves as the second input to element 104. As with ALU 110, in the preferred embodiment of the present invention, ALU 112 is principally used to implement adding operations. The second input to ALU 112 is the base address of the first memory location in the segment of memory to be accessed. This base address value is obtained from register 114. ALU 112 performs ar add operation on its two inputs to produce an output which represents the complete 32 bit address of the memory location to be accessed. The output of ALU 112 is provided to a 29 bit misalignment register 116 and to a 29 bit general register 118. The 3 least significant bits of the 32 bit address output by ALU 112 are provided to element 120. Division of the 32 bit output of ALU 112 into 29 bit and 3 bit components is accomplished by routing the bus lines carrying the output of ALU 112 to the appropriate locations. Element 120 is shown as a two-input-single-output logic element or switch. As discussed previously, it typically takes the form of a data multiplexer, with control logic selecting which of the two inputs is routed out of the element as the output. The other input to element 120 is provided along data path 122. The output of element 120 serves as the input to register 124. T e output of register 124 is provided along two data paths. The first data path from element 124 serves as an input to location 128, while the second data path serves as an input to element 126, which in the preferred embodiment of the present invention is a 3 bit incrementor. The output of 3 bit incrementor 126 is provided along data path 122 and serves as the second input to element 120. The outputs of misalignment register 116 and general register 118 are provided as inputs to element 130, which again takes the form of a two-input-single-output logic element or switch. The output of element 130 serves as the second data path feeding into location 128. The two data paths feeding into location 128 are combined into a single data path at that point. The single data path leaving location 128 is provided as the input to memory 132. As noted, the output of ALU 112 is a 32 bit address, the 29 most significant bits of which are provided to registers 116 and 118. Control unit 140 performs two primary functions: (1) it determines if consecutive memory addresses need to be generated, i.e., if a misalignment problem or doubleword length data access exists; and (2) it controls the operation of elements 130 and 120 in response to that determination. A data misalignment or doubleword length data situation is determined based on the starting address of the memory location to be accessed and the length of the data which is to be retrieved from memory 132. Note that some or all of the functions performed by control unit 140 may be performed by other stages of microprocessor 1 of figure 1. If there is no need to generate consecutive addresses, control unit 140 causes element 130 to pass the output of register 118 to location 128 as the output of element 130. Control unit 140 similarly causes element 120 to pass the 3 least significant bits of the address generated by ALU 112 to register 124. The output of register 124 is provided as the second input to location 128. At location 128, both input data paths are combined into a single address 32 bit which is then passed to memory 132. The function occurring at location 128 may be implemented in the form of two sets of bus lines (a 29 bit set and a 3 bit set) which are fed to a common destination. The 32 bit address produced is used to access the location in memory 132 which holds the desired data. However, in accordance with the present invention, when control unit 140 determines that a data misalignment problem or doubleword length data access exists, it controls elements 130 and 120 in such a manner as to produce the consecutive addresses needed to access the data in memory. The present invention divides the misalignment or doubleword length data problems into two cases: (1) situations where the address to be generated is within an 8 byte block in memory; and (2) situations where the address to be generated is outside of an 8 byte block in memory. In the situation in which control unit 140 determines that the address to be generated is within an 8 byte block, 3 bit incrementor 126 is used to increment the 3 least significant bits of the address provided by ALU 112 to element 120. A 3 bit incrementor is capable of incrementing the address by a value up to 2 , or 8 bits (values of 0 to 7). The incremented address is provided by incrementor 126 along data path 122 to element 120. Control unit 140 then causes element 120 to pass the incremented 3 bit value, rather than the 3 bit value provided by ALU 112. Control unit 140 also causes element 130 to select the value passed to it from misalignment register 116 as the output of element 130. Location 128 thus receives as a data path containing the 29 most significant bits of the address passed to it by misalignment register I lό and a data path containing the incremented value of the 3 least significant bits which is passed by the actions of element 120 and register 124. The address data passed to location 128 by element 130 and register 124 is combined to form the 32 bit address of the next memory location which is to be accessed. Thus, when control unit 140 detects a misalignment problem, during a first clock cycle the initial address is calculated and control unit 140 causes the contents of register 118 and the 3 least significant bits of the address output by ALU 112 to be passed to memory 132. In the next clock cycle, the 3 least significant bits of the address are incremented and combined with the contents of misalignment register 116 to form the incremented address. This new address is then passed to memory 132. In the situation in which control unit 140 and/or global control unit 30 determine that the address to be generated is outside of an 8 byte block, ALU 110 of execution unit 18 is used to generate the incremented address(es). In this case, during a first clock cycle the initial address is calculated and control unit 140 again causes the contents of register 118 and the 3 least significant bits of the address output by ALU 112 to be passed to memory 132. During the next clock cycle, the contents of register 134 is passed back to ALU 110 by means of controlling the action of element 104. This value, which is the initially calculated offset value for the first memory address, is then incremented to obtain the offset for the next address location. This process of incrementing the offset is accomplished by combining the offset of the initial address with a value of 8 which is supplied by register 150. This value is passed through element 108 to element 106. Element 108 may have other inputs which are selected by controlling the operation of element 108. Element 106 is controlled to select the incrementing value from register 150 instead of the data supplied along path 100 to send to ALU 110 as the second input. ALU 110 combines the offset value from register 134 and the incrementing value from register 150 to obtain the offset value for the new address. This value is provided as an input to ALU 112. The second input to ALU 112 is again the base address of the first memory location in the segment of memory to be accessed. This base address value is obtained from register 114. ALU 112 performs an add operation on its two inputs to produce an output which represents the complete 32 bit address of the memory location to be accessed. The output of ALU 112 is provided to 29 bit misalignment register 116 and to 29 bit general register 118. The 3 least significant bits of the 32 bit address output by ALU 112 are provided to element 120. Control unit 140 now causes element 130 to pass the output of register 118 to location 128 as the output of element 130. Control unit 140 similarly causes element 120 to pass the incremented value of the 3 least significant bits of the address generated by ALU 112, as generated by incrementor 126, to register 124. The output of register 124 is provided as the second data path to location 128. At location 128, the two data paths are combined into a single address which is then passed to memory 132. This address is used to access that location in memory 132 which holds the desired data. It is noted that because this address is based on the incremented offset value provided by ALU 110, it can be used to access a memory location which differs from that accessed during the first clock cycle. One of the primary benefits of using misalignment register 116 is for implementing read-write- modify operations that involve a misalignment situation. An example of a read-write-modify instruction is ADD WordPtr [ 1007], AX. This instruction performs the operation(s) of taking the data located at WordPtr [1007] and replacing it with the sum of that data and the contents of register AX. In order to implement this instruction, three operations must be carried out: (1 ) a data read at the memory location WordPtr [1007] must be carried out; (2) the addition operation must be carried out; and (3) the result must be stored at the memory location WordPtr [1007]. The first step involves a misalignment situation, and the execution unit ALU's would be used to perform the misalignment calculation. The result of this calculation would then be stored in register 116. This means that when step (3) is performed, the misaligned address does not have to be recalculated. Generation of thf memory addresses for doubleword length data is accomplished in a similar manner. Control unit 140 determines if multiple addresses will need to be generated based on the initial memory address and the length of the data to be accessed. Control unit 140 then controls the routing of the address data during the clock cycles so that an initial address is calculated by ALU 110 and ALU 112, followed by the generation of the next address by use of either the 3 bit incrementor 126 or ALU 110. Thus, in accordance with the present invention, an apparatus and method for generating multiple addresses to access memory is based on apportioning the address generation operations between either a 3 bit incrementor or a full adder which is typically contained in an arithmetic logic unit. The division of the address generation between the two adders is controlled by a control unit which determines if a data misalignment or doubleword data access is indicated, based on the initial address location and the length of the data to be accessed. The first address in the group of addresses is calculated by adding the address components which comprise the offset value together to obtain the complete offset. This value is then added to the base address value to obtain a complete 32 bit address. This address is then incremented to obtain the next address to access. The incrementing is carried out by one of two procedures, depending upon whether the new address is within an 8 byte block or outside of an 8 byte block. If the new address is within an 8 byte block, a control unit utilizes the 29 most significant bits of the previous address and an incremented value of the 3 least significant bits (provided by means of a 3 bit incrementor) to generate the new address. If the new address lies outside an 8 byte block, the control unit causes an incremented offset value to be produced during the first add operation. This value is then combined with the base value to form a new 32 bit address. The 29 most significant bits of this address and an incremented value of the 3 least significant bits provided by a 3 bit incrementor are then used to generate the new address. The present invention has the capability of generating the multiple addresses needed to access misaligned or doubleword length data in a manner which is more efficient than currently used methods. This improvement in efficiency results from using a 3 bit incrementor to perform as much of the address generation as possible, instead of relying on a full adder or using the arithmetic logic units in the execution unit. This saves development time, device size and cost, and frees up the execution unit to perform more essential tasks. The invention embodiments described herein have been implemented in an integrated circuit which includes a number of additional functions and features which are described in the following co-pending, commonly assigned patent applications, the disclosure of each of which is incorporated herein by reference: U.S. patent application Serial No. 08/ , entitled "DISPLAY CONTROLLER CAPABLE OF ACCESSING AN EXTERNAL MEMORY FOR GRAY SCALE MODULATION DATA" (arty, docket no. NSC 1-62700); U.S. patent application Serial No. 08/ , entitled "SERIAL INTERFACE CAPABLE OF OPERATING IN TWO DIFFERENT SERIAL DATA TRANSFER MODES" (arty, docket no. NSC 1-62800); U.S. patent application Serial No. 08/ , entitled "HIGH PERFORMANCE MULTIFUNCTION DIRECT MEMORY ACCESS (DMA) CONTROLLER" (atty. docket no. NSC 1-62900); U.S. patent application Serial No. 08/ , entitled "OPEN DRAIN MULTI-SOURCE CLOCK GENERATOR HAVING MINIMUM PULSE WIDTH" (atty. docket no. NSC 1-63000); U.S. patent application Serial No. 08/ , entitled "INTEGRATED CIRCUIT WITH MULTIPLE FUNCTIONS SHARING MULTIPLE INTERNAL SIGNAL BUSES ACCORDING TO DISTRIBUTED BUS ACCESS AND CONTROL ARBITRATION" (atty. docket no. NSCI-63100); U.S. patent application Serial No. 08/ , entitled "EXECUTION UNIT ARCHITECTURE TO SUPPORT x86 INSTRUCTION SET AND x86 SEGMENTED ADDRESSING" (atty. docket no. NSC 1-63300); U.S. patent application Serial No. 08/ , entitled "BARREL SHIFTER" (atty. docket no. NSC 1-63400); U.S. patent application Serial No. 08/ , entitled "BIT SEARCHING THROUGH 8, 16, OR 32-BIT PERANDS USING A 32-BIT DATA PATH" (atty. docket no. NSC 1-63500); U.S. patent application Serial No. 08/ , entitled "DOUBLE PRECISION (64-BIT) SHIFT OPERATIONS USING A 32-BIT DATA PATH" (atty. docket no. NSC 1-63600); U.S. patent application Serial No. 08/ , entitled "METHOD FOR PERFORMING SIGNED DIVISION" (atty. docket no. NSC 1-63700); U.S. patent application Serial No. 08/ , entitled "METHOD FOR PERFORMING ROTATE THROUGH CARRY USING A 32-BIT BARREL SHIFTER AND COUNTER" (atty. docket no. NSC 1-63800) U.S. patent application Serial No. 08/ , entitled "AREA AND TIME EFFICIENT FIELD EXTRACTION CIRCUIT" (atty. docket no. NSC 1-63900); U.S. patent application Serial No. 08/ , entitled "NON-ARITHMETICAL CIRCULAR BUFFER CELL AVAILABILITY STATUS INDICATOR CIRCUIT" (atty. docket no. NSC 1-64000); U.S. patent application Serial No. 08/ , entitled "TAGGED PREFETCH AND INSTRUCTION DECODER FOR VARIABLE LENGTH INSTRUCTION SET AND METHOD OF OPERATION" (atty. docket no. NSC 1-64100); U.S. patent application Serial No. 08/ , entitled "PARTITIONED DECODER CIRCUIT FOR LOW POWER OPERATION" (atty. docket no. NSC 1-64200); U.S. patent application Serial No. 08/ , entitled "CIRCUIT FOR DESIGNATING INSTRUCTION POINTERS FOR USE BY A PROCESSOR DECODER" (atty. docket no. NSC 1-64300); U.S. patent application Serial No. 08/ , entitled "CIRCUIT FOR GENERATING A DEMAND-BASED GATED CLOCK" (atty. docket no. NSC 1-64500); U.S. patent application Serial No. 08/ , entitled "INCREMENTOR/DECREMENTOR" (atty. docket no. NSC 1-64700); U.S. patent application Serial No. 08/ , entitled "A PIPELINED MICROPROCESSOR THAT PIPELINES MEMORY REQUESTS TO AN EXTERNAL MEMORY" (atty. docket no. NSC 1-64800); U.S. patent application Serial No. 08/ , entitled "CODE BREAKPOINT DECODER" (atty. docket no. NSC 1-64900); U.S. patent application Serial No. 08/ , entitled "TWO TIER PREFETCH BUFFER STRUCTURE AND METHOD WITH BYPASS" (atty. docket no. NSC 1-65000); U.S. patent application Serial No. 08/ , entitled "INSTRUCTION LIMIT CHECK FOR MICROPROCESSOR" (atty. docket no. NSC 1-65100); U.S. patent application Serial No. 08/ , entitled "A PIPELINED MICROPROCESSOR THAT MAKES MEMORY REQUESTS TO A CACHE MEMORY AND AN EXTERNAL MEMORY CONTROLLER DURING THE SAME CLOCK CYCLE" (atty. docket no. NSC 1-65200); U.S. patent application Serial No. 08/ , entitled "APPARATUS AND METHOD FOR EFFICIENT COMPUTATION OF A 486™ MICROPROCESSOR COMPATIBLE POP INSTRUCTION" (atty. docket no. NSC1-65700); U.S. patent application Serial No. 08/ , entitled "APPARATUS AND METHOD FOR EFFICIENTLY DETERMINING ADDRESSES FOR MISALIGNED DATA STORED IN MEMORY" (atty. docket no. NSC 1-65800); U.S. patent application Serial No. 08/ , entitled "METHOD OF IMPLEMENTING FAST 486™ MICROPROCESSOR COMPATIBLE STRING OPERATION" (atty. docket no. NSC 1-65900); U.S. patent application Serial No. 08/ , entitled "A PIPELINED MICROPROCESSOR THAT PREVENTS THE CACHE FROM BEING READ WHEN THE CONTENTS OF THE CACHE ARE INVALID" (atty. docket no. NSC 1-66000); U.S. patent application Serial No. 08/ , entitled "DRAM CONTROLLER THAT REDUCES THE TIME REQUIRED TO PROCESS MEMORY REQUESTS" (atty. docket no. NSC 1-66300); U.S. patent application Serial No. 08/ , entitled "INTEGRATED PRIMARY BUS AND SECONDARY BUS CONTROLLER WITH REDUCED PIN COUNT" (atty. docket no. NSC 1-66400); U.S. patent application Serial No. 08/ , entitled "SUPPLY AND INTERFACE CONFIGURABLE INPUT/OUTPUT BUFFER" (atty. docket no. NSC 1-66500); U.S. patent application Serial No. 08/ , entitled "CLOCK GENERATION CIRCUIT FOR A DISPLAY CONTROLLER HAVING A FINE TUNEABLE FRAME RATE" (atty. docket no. NSC 1-66600); U.S. patent application Serial No. 08/ , entitled "CONFIGURABLE POWER MANAGEMENT SCHEME" (atty. docket no. NSC 1-66700); U.S. patent application Serial No. 08/ , entitled "BIDIRECTIONAL PARALLEL SIGNAL INTERFACE" (atty. docket no. NSC 1-67000); U.S. patent application Serial No. 08/ , entitled "LIQUID CRYSTAL DISPLAY (LCD) PROTECTION CIRCUIT" (atty. docket no. NSC 1-67100); U.S. patent application Serial No. 08/ , entitled "IN-CIRCUIT EMULATOR STATUS INDICATOR CIRCUIT" (atty. docket no. NSC 1-67400); U.S. patent application Serial No. 08/ , entitled "DISPLAY CONTROLLER CAPABLE OF ACCESSING GRAPHICS DATA FROM A SHARED SYSTEM MEMORY" (atty. docket no. NSC 1-67500); U.S. patent application Serial No. 08/ , entitled "INTEGRATED CIRCUIT WITH TEST SIGNAL BUSES AND TEST CONTROL CIRCUITS" (atty. docket no. NSC 1-67600); U.S. patent application Serial no. 08/ , entitled "DECODE BLOCK TEST METHOD AND APPARATUS" (atty. docket no. NSC 1-68000). The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention in the use of such terms and expressions of excluding equivalents of the features shown and described, or portions thereof, it being recognized that various modifications are possible within the scope of the invention claimed.

Claims: We claim: 1. An apparatus for generating memory addresses for accessing misaligned data stored in a memory, comprising: means for venerating an offset value for an address, wherein the offset value corresponds to an amount by which a memory location is offset from a base address; means for generating the base address; means for adding the offset value and the base address to produce a complete memory address; control means for determining whether a piece of data stored at the complete memory address is misaligned; means for dividing the complete memory address into a set of most significant bits and a set of least significant bits; means for incrementing a value of the set of least significant bits when the control means determines that the data is misaligned; and means for combining the set of most significant bits and the incremented set of least significant bits to form a new address for memory, when the control means determines that the data is misaligned. 2. The apparatus for generating memory addresses of claim 1 , wherein the means for adding the offset value and the base address to produce a complete memory address is an arithmetic logic unit. 3. The apparatus for generating memory addresses of claim 1, wherein the control means determines whether a piece of data is misaligned based on a length of the data and the complete memory address. 4. The apparatus for generating memory addresses of claim 1 , wherein the means for incrementing a value of the set of least significant bits is a 3 bit adder. 5. The apparatus for generating memory addresses of claim 4, wherein the 3 bit adder is contained in a bus unit. 6. The apparatus for generating memory addresses of claim 1 , wherein the means for generating an offset value for an address generates the offset by incrementing the offset value from a previous address. 7. A method of generating memory addresses for accessing misaligned data stored in a memory, comprising: generating an offset value for an address, wherein the offset value corresponds to an amount by which a memory location is offset from a base address; generating the base address; adding the offset value and the base address to produce a complete memory address; determining whether a piece of data stored at the complete memory address is misaligned; dividing the complete memory address into a set of most significant bits and a set of least significant bits; incrementing a value of the set of least significant bits when it is determined that the data is misaligned; and combining the set of most significant bits and the incremented set of least significant bits to form a new address for memory, when it is determined that the data is misaligned. 8. The method of generating memory addresses of claim 7, wherein the offset value is generated by incrementing the offset value of a previous address. 9. The method of generating memory addresses of claim 7, wherein the determination of whether a piece of data stored at the complete memory address is misaligned is based on a length of the data and the complete memory address. - I I

Inventors: DIVIVIER ROBERT JAMES, NEMIROVSKY MARIO, SANKAR NARENDRA, DIVIVIER, ROBERT, JAMES, NEMIROVSKY, MARIO, SANKAR, NARENDRA
Applicants: NAT SEMICONDUCTOR CORP, NATIONAL SEMICONDUCTOR CORPORATION
Application year: 1996
Main classification: G06F9
IPC codes: G06F9