IBM PC COMPATIBLE MULTI-CHIP MODULE

Abstract: A multi-chip module (10) and a chip set that comprises a plurality of the multi-chip modules. The multi-chip module (10) includes a plurality of functional circuits (40, 42, 36, 32, 34, 44, 28, 50, 48, 20, 26, 46, 30) provided on a substrate, the circuits (40, 42, 36, 32, 34, 44, 28, 50, 48, 20, 26, 46, 30) defining a plurality of signal inputs and outputs. The functional circuits (40, 42, 36, 32, 34, 44, 28, 50, 48, 20, 26, 46, 30) of one embodiment of the module include a CPU (20), serial interfaces (32, 34), a parallel interface (36), a hard drive interface (42), a floppy disk interface (40), a keyboard interface (28), and flash memory (44).

Description: ΗTLE OF THE INVENTION IBM PC COMPATIBLE MULTI-CHIP MODULE FIELD OF THE INVENTION This invention relates to a multi-chip module. BACKGROUND OF THE INVENTION The most successful applications of computer technology have been those that people do not see. Microcontrollers and microprocessors govern automotive anti lock braking systems, automatic teller machines, elevators, subway ticket systems, and medical equipment. These hidden computers, otherwise known as embedded systems, permeate our lives. The embedded control market is, in fact, growing significantly faster than the desk top computing market. A major trend is the move from 4- and 8-bit processors to more powerful devices that provide more computing power and enable more "friendly" man-machine interfaces. A study by Desk Top Strategies showed that in 1994 over 320 million 16- and 32-bit embedded control processors were shipped to original equipment manufacturers (OEMs) for use in embedded control applications. In contrast, only 50 million were shipped to desk top computer manufacturers. The compound annual growth rate for 32-bit processors in the embedded market from 1992 to 1997 is projected to be 53 percent, compared with an estimated 32 percent in the desk top market. The area of greatest growth in the embedded control market is the segment of ultra- miniature controllers for portable and transportable instruments. OEMs have indicated a strong interest in developing products with the PC architecture, but have found that size, integration, power, reliability, or cost constraints make existing broad-level products unsuitable for their applications. The Cardio 386 developed by S-Mos Systems comprises a full function, small footprint, X86 computer that includes a CPU, all standard PC-type I/O controllers, PGA graphics, floppy and hard disk drive interfaces, DRAM, flash memory, and transparent power management. It adopts a PC AT architecture which complies with the ISA (industry standard architecture) bus pin configuration. However, it makes use of a unique edge connector comprising a plurality of tracks formed into rows on a card. This is - " I - received in a complementary slot for connection to peripheral devices. The use of a connector for connecting the module to a board makes its implementation inherently unreliable since vibrations can compromise the electrical connections between the various tracks forming the pins, and the corresponding contacts of the slot connector. Furthermore, no provision is made for integrating the module with proprietary hardware of OEMs (original equipment manufacturers). Another prior art device is the Northstar HI by Micro Module Systems that comprises a multi-chip module, including a Pentium processor, a cache controller, and RAM incoφorated in a 349 pin PGA package. Once again, no facility is provided for interfacing with OEM proprietary hardware, Furthermore, the North Star module is packaged in a 349 pin PGA which makes simple direct connection to peripheral devices impossible without complicated track layout design. Therefore it does not allow the module to be simply dropped into an OEM system. OBJECTS AND SUMMARY OF THE INVENTION It is an object of the invention to incorporate a multi-chip module in an ultra- miniature form factor. In particular it is an object of the invention to provide a module the size of a large integrated circuit. It is a further object of the invention to provide an Intel X86 compatible computer module and peripheral controller modules wherein the computer module includes a CPU, I/O (a parallel port and two serial ports), a keyboard interface, a DRAM interface, floppy disk controller, hard disk controller, and flash disk functions based on Intel X86 architecture. Specifically, it is an object of the invention to provide a multi-chip module that provides an OEM (Original Equipment Manufacturer) with the facility for incorporating a feature set that is compatible with IBM PC/AT hardware, software, and bus pin configuration. It is a further object of the invention to provide a module having low power consumption, broad thermal adaptability, low cost, and high reliability by eliminating cables and mounting hardware. It is yet a further object of the invention to provide a module family having identical ISA bus pin configurations to facilitate easy interconnection. It is yet a further object of the invention to provide a development board to form a platform for receiving a multi-chip module of the invention, thereby to provide for the quick development of pilot projects. According to the invention there is provided a multi-chip module comprising a plurality of functional circuits provided on a substrate, the circuits defining a plurality of signal inputs and outputs, and a plurality of module pins secured in a single row along the periphery of the substrate and connected to the inputs and outputs, the module pins including a set of 91 pins, two ground pins, and a power pin, defining an ISA bus means, the signal pins having a configuration complying in number and signal type with the signal pins laid down under the IEEE-P996 specification, and as applied in the ISA (Industry Standard Architecture) requirements. For this reason it will hereinafter be referred as to as j the ISA bus. The module can be rectangular in shape, having a first side, a second side opposite the first side, a third side, and a fourth side, and is defined by an upper surface, a lower surface, and a peripheral wall, and wherein the plurality of pins extend from the peripheral wall. The pins of the ISA bus means of the present invention preferably comprise: pin 38 corresponding to signal IOCHCK; pin 39 corresponding to signal SD07; pin 40 corresponding to signal RESETDRV; pin 41 corresponding signal SD06; pin 42 corresponding to signal SD05; pin 43 corresponding to signal IRQ9; pin 44 corresponding to signal SD04; pin 45 corresponding to signal SD03; pin 46 corresponding to signal DRQ2; pin 47 corresponding to signal DRQ2OUT-; pin 48 corresponding to signal SD02; pin 49 corresponding to signal SD01-; pin 50 corresponding to signal OWS; pin 51 corresponding to signal SDOO; pin 52 corresponding to signal IOCHRDY; pin 53 corresponding to signal SBHE-; pin 54 corresponding to signal MEMSC16-; pin 55 corresponding to signal AEN; pin 56 corresponding to signal SMEMW-; pin 57 corresponding to signal LA23; pin 58 corresponding to signal IOCS16-; pin 59 corresponding to signal SA19; pin 60 corresponding to signal SMEMR- ; pin 61 corresponding to signal LA22; pin 62 corresponding to signal IRQ 10; pin 63 corresponding to signal SA18; pin 64 corresponding to signal IOW-; pin 65 corresponding to signal LA21; pin 66 corresponding to signal IRQ11; pin 67 corresponding to GND; pin 68 corresponding to signal SA17; pin 69 corresponding to signal IOR-; pin 70 corresponding to signal LA20; pin 71 corresponding to signal IRQ12; pin 72 corresponding to signal SA16; pin 73 corresponding to signal DACK3-; pin 74 corresponding to signal LAI 9; pin 75 corresponding to signal IRQ 15; pin 76 corresponding to signal SA 15; pin 77 corresponding to signal DRQ3; pin 78 corresponding to signal LAI 8; pin 79 corresponding to signal IRQ 14; pin 80 corresponding to signal SA14; pin 81 corresponding to signal DACK1-; pin 82 corresponding to signal LA 17; pin 83 corresponding to signal DACK0-; pin 84 corresponding to signal SA13; pin 85 corresponding to VCC; pin 86 corresponding to signal DRQ1-; pin 87 corresponding to signal MEMR-; pin 88 corresponding to signal DRQO; pin 89 corresponding to signal SA12; pin 90 corresponding to signal REFRESH-; pin 91 corresponding to signal MEMW-; pin 92 corresponding to signal DACK5-; pin 93 corresponding to signal SA1 1; pin 94 corresponding to signal SYSCLK; pin 95 corresponding to signal SD08; pin 96 corresponding to signal DRQ5; pin 97 corresponding to signal S A 10; pin 98 corresponding to signal IRQ7; pin 99 corresponding to signal IRQ7OUT; pin 100 corresponding to signal SD09; pin 101 corresponding to signal DACK6-; pin 102 corresponding to GND; pin 103 corresponding to signal SA09; pin 104 corresponding to signal IRQ6; pin 105 corresponding to signal IRQ6OUT; pin 106 corresponding to signal SD10; pin 107 corresponding to signal DRQ6; pin 108 corresponding to signal SA08; pin 109 corresponding to signal IRQ5; pin 110 corresponding to signal SDl 1 ; pin 11 1 corresponding to signal DACK7-; pin 1 12 corresponding to signal SA07; pin 113 corresponding to signal IRQ4; pin 1 14 corresponding to signal SD12; pin 115 corresponding to signal DRQ7; pin 116 corresponding to signal SA06; pin 117 corresponding to signal IRQ3; pin 118 corresponding to signal SD13; pin 119 corresponding to signal SA05; pin 120 corresponding to signal DACK2-; pin 121 corresponding to signal SD14; pin 122 corresponding to signal MASTER-; pin 123 corresponding to signal SA04; pin 124 corresponding to signal TC; pin 125 corresponding to signal SD15; pin 126 corresponding to signal SA03; pin 127 corresponding to signal BALE; pin 128 corresponding to signal SA02; pin 129 corresponding to signal SA01 ; pin 130 corresponding to signal OSC; and pin 131 corresponding to signal SAOO. The pin of the ISA bus means of the present invention can alternatively comprise: pin 38 corresponding to signal SA00; pin 39 corresponding to signal OSC; pin 40 to signal SAOl; pin 41 corresponding signal SA02; pin 42 corresponding to signal BALE; pin 43 corresponding to signal SA03; pin 44 corresponding to signal SD15; pin 45 corresponding to signal TC; pin 46 corresponding to signal SA04; pin 47 corresponding to signal MASTER-; pin 48 corresponding to signal SD14; pin 49 corresponding to signal DACK2-; pin 50 corresponding to signal SA05; pin 51 corresponding to signal SDl 3; pin 52 corresponding to signal IRQ3; pin 53 corresponding to signal SA06; pin 54 corresponding to signal DRQ7; pin 55 corresponding to signal SDl 2; pin 56 corresponding to signal IRQ4; pin 57 corresponding to signal SA07; pin 58 corresponding to signal DACK7-; pin 59 corresponding to signal SDl 1; pin 60 corresponding to signal IRQ5; pin 61 corresponding to signal SA08; pin 62 corresponding to signal DRQ6; pin 63 corresponding to signal SD10; pin 64 corresponding to signal IRQ6OUT; pin 65 corresponding to signal IRQ6; pin 66 corresponding to signal SA09; pin 67 corresponding to GND; pin 68 corresponding to signal DACK6-; pin 69 corresponding to signal SD09; pin 70 corresponding to signal IRQ7OUT; pin 71 corresponding to signal IRQ7; pin 72 corresponding to signal SA10; pin 73 corresponding to signal DRQ5; pin 74 corresponding to signal SD08; pin 75 corresponding to signal SYSCLK; pin 76 corresponding to signal SA11; pin 77 corresponding to signal DACK5-; pin 78 corresponding to signal MEMW-; pin 79 corresponding to signal REFRESH-; pin 80 corresponding to signal SA12; pin 81 corresponding to signal DRQ0; pin 82 corresponding to signal MEMR-; pin 83 corresponding to signal DRQ1; pin 84 corresponding to signal SA13; pin 85 corresponding to VCC; pin 86 corresponding to signal DACK0-; pin 87 corresponding to signal LA 17; pin 88 corresponding to signal DACK1-; pin 89 corresponding to signal SA14; pin 90 corresponding to signal LRQ14; pin 91 corresponding to signal LA18; pin 92 corresponding to signal DRQ3; pin 93 corresponding to signal SA15; pin 94 corresponding to signal IRQ 15; pin 95 corresponding to signal LA19; pin 96 corresponding to signal DACK3-; pin 97 corresponding to signal SA16; pin 98 corresponding to signal IRQ12; pin 99 corresponding to signal LA20; pin 100 corresponding to signal IOR-; pin 101 corresponding to signal SA17; pin 102 corresponding to GND; pin 103 corresponding to signal LRQ11 ; pin 104 corresponding to signal LA21 ; pin 105 corresponding to signal IOW-; pin 106 corresponding to signal SA18; pin 107 corresponding to signal IRQ10; pin 108 corresponding to signal LA22; pin 109 corresponding to signal SMEMR-; pin 110 corresponding to signal SA19; pin 111 corresponding to signal IOCS16-; pin 112 corresponding to signal LA23; pin 113 corresponding to signal SMEMW-; pin 1 14 corresponding to signal AEN; pin 115 corresponding to signal MEMCS16-; pin 116 corresponding to signal SBHE-; pin 117 corresponding to signal IOCHRDY; pin 118 corresponding to signal SDOO; pin 119 corresponding to signal 0WS-; pin 120 corresponding to signal SD01; pin 121 corresponding to signal SD02; pin 122 corresponding to signal DRQ2OUT; pin 123 corresponding to signal DRQ2; pin 124 corresponding to signal SD03; pin 125 corresponding to signal SD04; pin 126 corresponding to signal IRQ9; pin 127 corresponding to signal SD05; pin 128 corresponding to signal SD06; pin 129 corresponding to signal RESETDRV; pin 130 corresponding to signal SD07; and pin 131 corresponding to signal IOCHCK-.The ISA bus pins preferably extend along the first side and at least partially along the third and fourth sides. The multi-chip module can include 240 module pins. The functional circuits in a module can include a central processing unit. The functional circuits can further include two serial interfaces, a parallel interface, a hard drive interface, a floppy disk interface, a keyboard interface, and flash memory. Other modules can include functional circuits that include a PCMCIA interface, an Ethernet interface, or a display controller. The substrate can comprise a printed circuit board and the functional circuits comprise semiconductor devices which can be packaged or can be in bare die form secured to the printed circuit board. Further, according to the invention, there is provided a multi-chip module comprising a plurality of functional circuits encapsulated in a rectangular housing, the housing having an upper surface and a lower surface, and a peripheral wall extending along a first side, a second side opposite the first side, a third side, and a fourth side; and a plurality of pins extending laterally from the peripheral wall, wherein the pins include a set of 91 signal pins, two ground pins and a power pin defining an ISA bus means, the signal pins of which comply in number and signal type, with the signal pins laid down under the LEEE-P996, and as applied in the ISA (Industry Standard Architecture) requirements. Still further, according to the invention, there is provided a module family comprising a plurality of functionally different modules, wherein each module has a plurality of pins and the pins of each module include a set of 91 signal pins, two ground pins, and a power pin, defining an ISA bus means, the signal pins of which comply in number and signal type with the signal pins laid down under the IEEE-P996, and as applied in the ISA (Industry Standard Architecture) requirements. Each module can comprise at least one functional circuit encapsulated in a rectangular housing, the housing having an upper surface and a lower surface, and a peripheral wall extending along a first side, a second side opposite the first side, a third side, and a fourth side, and wherein the pins of the module extend laterally from the peripheral wall. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view of a multi-chip module of the invention; Fig. 2 is a side view of the module of Fig. 1; Fig. 3 is a block diagram of a multi-chip module of the invention; Fig. 4 is a schematic representation of the first embodiment of a multi-chip module of the invention indicating the configuration of the pins; Fig. 5 is a schematic representation of the alternative embodiment of a multi-chip module of the invention indicating the configuration ofthe pins; Fig. 6 shows a PC board layout for a development board showing the mounting site for the module of Fig. 1, and Fig. 7 is a schematic representation of a number of different modules in accordance with the invention connected to each other by means of their ISA buses to form a module family of the invention. DESCRIPTION OF PREFERRED EMBODIMENTS A need exists in the field of embedded applications for small, highly reliable computer systems that draw little power, are easy to integrate, have broad thermal adaptability and are relatively inexpensive. Applications for such devices include medical instruments, data logging devices, security systems, test equipment, point-of-sale terminals, communications devices, such as Internet and facsimile machines, and navigational instruments. OEMs (original equipment manufacturers) typically use the Intel X86 architecture since it offers the world's largest body of hardware and software. The present invention has accordingly been developed to address the problems in the prior art by providing a multi-chip module packaged to resemble a large integrated circuit chip comprising a 240 pin QFP having an overall footprint of 59.54 x 79.88 mm. The module includes a set of pins constituting a bus for connection to the OEM designer's proprietary internal hardware. The invention specifically contemplates providing this bus with a configuration complying with the ISA (Industry Standard Architecture) requirements. This will allow the OEM designer quickly to incorporate IBM PC/AT hardware and software and to implement the module in ISA compatible proprietary product designs. The module is now described in greater detail with reference to Figs. 1 and 2 which show a plan view and a side view, respectively, of the module. The module 10 is a 240 pin QFP with gull wing pins having a 0.762 mm. pitch. The body is rectangular, the one side of which measures 76.2 mm and the overall footprint in this embodiment being 59.54 x 79.88 mm. The pins themselves are typically .5 mm wide, and the dimensions of distances 12 and 14 in Fig. 1 are 3.5 mm for this embodiment. By using a chip-like package in which the pins are formed around the periphery of the module 10 in a single row as illustrated in Figs. 1 and 2, the module 10 can easily be soldered into place to form a very sturdy, reliable set of connections. Furthermore, tracks can be designed to lead directly from the pins to another device by making use of PC board tracks on one or both surfaces of the PC board without the need for several layers to route the various tracks. Since the pins are soldered directly to the interconnecting tracks, the system has inherent reliability in that it eliminates cables and mounting hardware that could otherwise vibrate loose. As many as half a dozen interconnecting cables, assorted connectors and mounting hardware required with many existing prior art single board computers, are thereby eliminated. The module thus provides an Intel X86 compatible computer in an ultra-miniature form factor that can be integrated as easily as a semiconductor device and provides the full functionality of a desk top computer. As is described in greater detail below, the same concepts of using a chip-like module using a QFP package with gull wing pins and having an ISA compatible bus is extended also to peripheral controller modules. By integrating a full X86 AT-compatible computer onto a proprietary OEM design, the need for multiple boards is eliminated, thereby eliminating cables and mounting hardware. The full compatibility with PC-AT ISA allows for easy integration with low-cost hardware peripherals. The ISA, compliant bus makes it easy to interface with proprietary hardware design. One embodiment of the module 10, having a CPU as one of its functional circuits, is illustrated in Fig. 3 and includes the standard I/O interfaces, serial ports, a parallel port, and floppy and hard disk interfaces allowing standard hardware, cables, and software libraries to be incoφorated in the design. The module 10 includes an 80386 SX CPU 20 which is connected to a DRAM bus 22 and an ISA bus 24 by means of core logic 26. The core logic controls AT-compatible DMA controllers, interrupt controllers, and timers/counters. It also controls the AT keyboard controller 28 and the real time clock 30. Two serial ports 32, 34 and a parallel port 36 are provided, as are a floppy disk controller 40 and an IDE hard drive interface 42. In order to facilitate total solid state operation, internal flash memory 44 is provided that is controlled by a solid state flash disk controller 46. Power is controlled by means of a power monitor 48 that provides a power saving function by controlling CPU sleep modes, and by a watch dog timer 50. The watch dog timer 50 monitors CPU cycles to detect interrupts in the cycle thereby allowing the system to be automatically reset after a predetermined time delay. The microprocessor and various controllers and interfaces comprise chips, optionally in die form, mounted on a multi-layer PC board, e.g. ten-layers. The CPU 20 can be a standard 33 MHz 80386 SX CPU having a DRAM controller for supporting up to 16 M bytes of DRAM. Alternatively, CPU20 can be another standard microprocessor chip such as another type of 80386 chip or die, a 80486 chip or die, a Pentium chip or die, or any other desired microprocessor which is capable of providing the function of the 80386 device. The standard DRAM interface provides all the signals for connecting standard page-mode DRAMs of various configurations, including standard 8- and 9-bit 30-pin SIMM modules and discrete components, such as standard IM x 4 and 4M x 4 DRAM chips. The interface is designed to support 70 ns or faster DRAMs. The DRAM interface consists of: • Multiplexed addresses MA00-MA10 • Bi-directional data D0-D15 • Column Address Strobes CASL0- to CASL3- (low byte) • CASH0- to CASH3- (high byte) • Row Address Strobes RAS0- to RAS3- • Memory Write Strobe DRWE- The serial ports 32, 34 are PC-compatible asynchronous serial ports, typically treated as COM 1 and COM 2 devices by DOS. Serial Typical I/O Standard Port Usage Address Interrupt Serial 1 COM1 3F8-3FF IRQ4 Serial 2 COM2 2F8-2FF LRQ3 Serial Port Resources Either or both serial ports can be disabled using SETUP. When disabled, the port*s I/O address and interrupt are made available for other expansion devices on the PC bus. A full complement of input and output handshaking lines are supported by the serial ports, and all serial port signals are at standard LSTTL levels. In another embodiment, RS232C signal compatibility can be achieved by including a TTL-RS232C level converter to provide the necessary bipolar signal levels. The parallel port is a fully-compatible PC/AT parallel port providing bi-directional operation. It is typically used to support a line printer. As appears from the table below: Parallel Typical I/O Standard Port Usage Address Interrupt Parallel 1 LPT1 378H-37FH IRQ7 Parallel Port Resources 4.7K-ohm pull-ups (+5V) are typically provided to the following parallel port signals: • STROBE- • SLLN- • LNΓΓ- • AUTOFD- Generally, if the parallel port will be connected to a cable for high speed data communication (as opposed to static digital output levels or static TTL level sensing), certain signals require a 2.2 nF capacitor connected to ground. These include: • PD0-PD7 • STRB- Parallel port registers are provided for the parallel port as appears from the table set out below: Signal Active D Register Bit Name In/Out High/Low B2 5F Pi n DATA 0 PDO I/O HIGH 2 (A+0) 1 PDI I/O HIGH 3 2 PD2 o HIGH 4 3 PD3 I/O HIGH 5 4 PD4 I/O HIGH 6 5 PD5 I/O HIGH 7 6 PD6 I O HIGH 8 7 PD7 I O HIGH 9 STATUS 0 1 - - - (A+D) 1 1 - - - 2 1 - - - 3 ERROR- IN LOW 15 4 SLCT- IN HIGH 13 5 PE IN HIGH 12 6 ACK- IN HIGH 10 7 BUSY IN LOW 11 CONTROL 0 STRB- OUT LOW 1 (A+2) 1 AUTOFD OUT LOW 14 2 INTT- OUT HIGH 16 3 SLCTIN- OUT LOW 17 4 IRQ ENABLE - HIGH - 5 I - - - 6 1 - - 7 1 ~ ~ - Parallel Port Registers The DOS-compatible floppy drive interface 40 allows cable connections for up to four floppy drives. In PC-compatible systems, the BIOS and DOS support two drives. These are configured using the BIOS SETUP function. Hardware controls for two additional drives are provided. The floppy drive interface supports the following standard floppy formats: Capacity Drive Size Tracks Data Rate 360K 5-1/4 inch 40 250 KHz 1.2M 5-1/4 inch 80 500 KHz 720K 3-1/2 inch 80 250 KHz 1 44M 3-1/2 inch 80 500 KHz The various floppy interface resources are given in the table below Resource Function I O Address 3F2 FDC Digital Output Register (LDOR) 3F0h-3F7h 3F4 FDC Main Status Register 3F5 FDC Data Register 3F7 FDC Control Register (LDCR) IRQ6 Interrupt DRQ2BDACK2 DMA Controller Channel ^loppy Interface Resources Outputs to the floppy drive and from the floppy drive are Aopen collector≡. Pull¬ up resistors are therefore required for proper termination, both on the SMX 386 board and on one of the attached floppy drives (not both). 330-Ohm pull-ups are required for the following floppy interface signals: DSKCHG- RDATA- WRPRT- TRK0- INDEX- The pin numbers and functions associated with the floppy drive are given in the table below: 24 22 WDATA- Write Data OUT 25 24 WGATE- Wπte Gate OUT 26 26 TRK0- Track 0 INPUT 27 28 WRPRT- Wπte Protect INPUT 28 30 RDATA- Read Data INPUT 29 32 HDSEL- Head Select OUT 30 34 DSKCHG- Disk Change INPUT 1 B33 Ground Ground Floppy Drive Interface The IDE hard drive interface 42 is a standard interface used in PC-compatible systems for hard disk drives. Up to two drives can be connected in a master-slave arrangement. The resources are depicted in the table below: Resource Function I/O Address Hard Disk Interface lF0h- lF7h IRQ 14 Interrupt IDE Hard Disk Resources The IDE interface pins are arranged to easily attach to a male PC-mounted ribbon- cable connector, the IDE drives typically being attached to the drive interface using a 40- pin ribbon cable. The pin configuration for the IDE interface is given in the table below: Pin IDE Signal Name Function In/Out Pin 223 1 HDRESET- Reset signal from host OUT 2 GND Ground OUT 224 3 IDED7 Data bit 7 I O 225 4 HDD08 Data bit 8 I/O 226 5 HDD06 Data bit 6 I/O 227 6 HDD09 Data bit 9 I/O 228 7 HDD05 Data bit 5 I/O 229 8 HDD10 Data bit 10 I/O 230 9 HDD04 Data bit 4 I/O 231 10 HDD1 1 Data bit 1 1 vo 232 1 1 HDD03 Data bit 3 I/O 233 12 HDD 12 Data bit 12 I/O 234 13 HDD02 Data bit 2 I/O 235 14 HDD13 Data bit 13 I/O 236 15 HDD0I Data bit 1 I/O 237 16 HDD14 Data bit 14 I/O 238 17 HDD00 Data bit 0 I/O 239 18 HDD 15 Data bit 15 I/O 19 GND Ground OUT 20 KEY Keyed pm N/C 21 N/A Reserved N/C 22 GND Ground OUT 240 23 HDIOW- Wπte strobe OUT 24 GND Ground OUT 1 25 HDIOR- Read strobe OUT 26 GND Ground OUT 27 RSVD Reserved N/C 2 28 HDALE Address latch enable OUT 29 RSVD Reserved N/C 30 GND Ground OUT 237 31 HED14 Dπve interrupt request IN LDE Drive Interface One embodiment of the pin configuration for the module 10 as a whole is illustrated in Fig. 4 and is given in the pm description table below: Pm Pin Name Descπption Typ3 1 HDIOR- IDE I/O Read, active low Buffered version of 024 IOR 2 HDALE IDE Address Latch Enable, active high 024 Buffered version of BALE 3 IRQ14 IDE Interrupt Request 14 For use with IDE I interface Same signal appears on pm 90 4 IOCS 16 IDE I/O Chip Select 16 A low requests a 16-bit I transfer on the S A bus Same signal appears on pin 238 This one is used for the IDE interface 5 HDA1 IDE Address 1 Buffered version of SA1 024 6 HDAO IDE Address 0 Buffered version of SAO 024 7 HDA2 IDE Address 2 Buffered version of SA2 024 8 HDCS- IDE Chip Select A low indicates that data is 024 being transferred to or from the IDE dπve 9 FDCS- Floppy disk Chip Select A low indicates that 024 data is being transferred to or from the floppy disk 10 LEDIN LED signal from IDE dπve 1 1 1 DENSEL 12 INDEX- Floppy disk index pulse, input from dnvc I 13 MTRO- Floppy disk active lower open drain output selects motor dnver 0 The motor enable bits are software controlled via the floppy's Digital Output Register (DOR) 14 MTR2- Floppy disk active low open dram output selects motor dnver 2 The motor enable bits are software controlled via the floppy's Digital Output Register (DOR) 15 DRV 1- Floppy disk active lower open drain output that selects floppy dπve 1 16 DRV3- Floppy disk active low open drain output that selects floppy dπve 3 17 GND 18 DRV0- Floppy disk active low open dram output that selects floppy dπve 0 19 DRV2- Floppy disk active low open drain output that selects floppy dπve 2 20 MTR1- Floppy disk active low open drain output selects As mentioned above, the core logic 26 supports a DRAM bus 22 and an ISA compatible expansion bus 24 complying in number and signal type with the IEEE-P996 requirements (and corresponding to the ISA (Industry Standard Architecture) requirements). The pin configuration for the expansion bus 24 is given in the table below with corresponding pin numbers for expansion bus connectors A, B, C, D. The bus 24 comprises 94 pins that includes VCC and two GND pins. Pin Signal Name Function In/Out Current Load* 38 A31 SAOO Address bit 0 I/O 12 mA PU 39 B30 osc 14318 MHz clock Out 6 mA 33 SER 40 A30 SAOl Address bit 1 I/O 12 mA PU 41 A29 SA02 Address bit 2 I/O 12 mA PU 42 B28 BALE Address latch enable Out 12 mA 43 A28 SA03 Address bit 3 I/O 12 mA PU 44 C18 SD15 System Data bit 15 I/O 12 mA PU 45 B27 C DMA Terminal Out 4 mA Count An alternative embodiment of the pin configuration for the module 10 as a whole is illustrated in Fig. 5 and is given in the pin description table below: Pin Pin Name Descπption Type 1 HDIOR- IDE I/O Read, active low Buffered version of 024 1 IOR 2 HDALE IDE Address Latch Enable, active high 024 Buffered version of BALE 3 IRQ14 IDE Interrupt Request 14 For use with IDE interface Same signal appears on pin 90 1 4 IOCS 16- IDE I/O Chip Select 16 A low requests a 16- I bit transfer on the SA bus Same signal appears on pin 238 This one is used for the IDE interface 5 HDA1 IDE Address 1 Buffered version of SA1 024 6 HDA0 IDE Address 0 Buffered version of SAO 024 7 HDA2 IDE Address 2 Buffered version of SA2 024 8 HDCS- IDE Chip Select A low indicates that data is 024 being transferred to or from the IDE dnve A second embodiment of the pin configuration for the expansion bus 24 is given in the table below with corresponding pin numbers for expansion bus connectors A, B, C, D. As mentioned before, bus 24 comprises 94 pins that includes VCC and two GND pins. 126 B4 SA03 interrupt request 9 In N/A PU 127 A4 BALE System Data bit 5 o 24 mA PU 128 A4 SA02 System Data bit 6 VO 24 mA PU 129 B2 SAOl System reset signal Out 24 mA 130 A2 OSC System Data bit 7 vo 24 mA PU 131 Al SA00 Sub NMI input In N/A 4.7K PU The exact pin configuration as illustrated for the expansion bus on Fig. 5 is a critical feature of the invention. Since it forms a single row of pins on the module 10, the pins can be easily connected directly to the expansion bus connectors without having to resort to multiple layer boards to route the PC board tracks from the module 10 to the expansion bus connectors A, B, C, D. Furthermore, as mentioned above, the present invention includes both microprocessor modules as illustrated in Fig. 3, as well as peripheral controller modules such as display controller modules, Ethernet control modules, and PCMCIA compatible modules for extended memory (RAM, ROM, EEPROM, flash memory, etc.), as well as for modem, fax, and network interfaces, and also for wireless communication devices. By providing an identical pin configuration for the ISA buses, the various modules can easily be connected to one another. A further feature of the invention is illustrated in Fig. 6. Fig. 6 illustrates a card 54 having a mounting site 56 for a module having a pin configuration as described above with reference to Fig. 4. The card 54 provides an integrated way for system development in standard ISA passive backplane systems. The card includes an AT-bus and a PC/104 bus, and occupies a single slot in an AT-class (16-bit) passive backplane. This allows development to be performed using a terminal on a serial port as a console. A standard VGA or SVGA display controller can be plugged into another slot on the backplane if desired. Instead, a PC/104 display controller can be installed directly on the PC/104 header 58 on the card 54. Since the module 10 is fully compatible with PC/AT ISA, a wide selection of hardware peripherals may be integrated. The ISA-compatible bus allows an OEM to easily interface his proprietary hardware design with the module 10. Furthermore, the standard BIOS and embedded DOS allows application software to be developed using standard desk top PCs and standard development tools for implementation on the system using one or more modules of the present invention. It will be appreciated that, depending on the nature of the module, the size of the module and the number of pins may vary, however it is an important feature of this invention that the pins for the ISA bus retain their configuration in each module to allow the modules to be readily connected to one another as illustrated in Fig. 7 in which different modules 60, 62, 64 of the invention are connected to each other by means of bus lines 66, 68 extending between the ISA compatible bus pins indicated by reference numerals 70, 72, 74, respectively.

Claims: WE CLAIM: 1. A multi-chip module comprising a plurality of functional circuits provided on a substrate, the circuits defining a plurality of signal inputs and outputs, and a plurality of module pins secured in a single row along the periphery of the substrate and connected to the inputs and outputs, the module pins including a set of 91 signal pins, two ground pins and a power pin, defining an ISA bus means, the signal pins having a configuration complying in number and signal type with the IEEE-P996 requirements. 2. A multi-chip module of Claim 1 , wherein the module is rectangular in shape, having a first side, a second side opposite the first side, a third side, and a fourth side, and is defined by an upper surface, a lower surface, and a peripheral wall, and wherein the plurality of pins extend from the peripheral wall. A multi-chip module of Claim 2, wherein the pins of the ISA bus means comprise: pin 38 corresponding to signal IOCHCK; pin 39 corresponding to signal SD07; pin 40 corresponding to signal RESETDRV; pin 41 corresponding signal SD06; pin 42 corresponding to signal SD05; pin 43 corresponding to signal LRQ9; pin 44 corresponding to signal SD04; pin 45 corresponding to signal SD03; pin 46 corresponding to signal DRQ2; pin 47 corresponding to signal DRQ2OUT-; pin 48 corresponding to signal SD02; pin 49 corresponding to signal SD01-; pin 50 corresponding to signal 0WS-; pin 51 corresponding to signal SDOO; pin 52 corresponding to signal IOCHRDY; pin 53 corresponding to signal SBHE-; pin 54 corresponding to signal MEMSC16-; pin 55 corresponding to signal AEN; pin 56 corresponding to signal SMEMW-; pin 57 corresponding to signal LA23; pin 58 corresponding to signal IOCS 16-; pin 59 corresponding to signal SA19; pin 60 corresponding to signal SMEMR-; pin 61 corresponding to signal LA22; pin 62 corresponding to signal IRQ 10; pin 63 corresponding to signal SA18; pin 64 corresponding to signal IOW-; pin 65 corresponding to signal LA21; pin 66 corresponding to signal IRQ11; pin 67 corresponding to GND; pin 68 corresponding to signal SA17; pin 69 corresponding to signal IOR-; pin 70 corresponding to signal LA20; pin 71 corresponding to signal IRQ 12; pin 72 corresponding to signal SA16; pin 73 corresponding to signal DACK3-; pin 74 corresponding to signal LA 19; pin 75 corresponding to signal IRQ 15; pin 76 corresponding to signal SA15; pin 77 corresponding to signal DRQ3; pin 78 corresponding to signal LAI 8; pin 79 corresponding to signal IRQ 14; pin 80 corresponding to signal SA14; pin 81 corresponding to signal DACK1-; pin 82 corresponding to signal LA 17; pin 83 corresponding to signal DACK0-; pin 84 corresponding to signal SA13; pin 85 corresponding to VCC; pin 86 corresponding to signal DRQ1-; pin 87 corresponding to signal MEMR-; pin 88 corresponding to signal DRQO; pin 89 corresponding to signal SA12; pin 90 corresponding to signal REFRESH-; pin 91 corresponding to signal MEM -; pin 92 corresponding to signal DACK5-; pin 93 corresponding to signal SA1 1; pin 94 corresponding to signal SYSCLK; pin 95 corresponding to signal SD08; pin 96 corresponding to signal DRQ5; pin 97 corresponding to signal SA10; pin 98 corresponding to signal IRQ7; pin 99 corresponding to signal IRQ7OUT; pin 00 corresponding to signal SD09; pin 01 corresponding to signal DACK6-; pin 02 corresponding to GND; pin 03 corresponding to signal SA09; pin 04 corresponding to signal IRQ6; pin 05 corresponding to signal IRQ6OUT; pin 06 corresponding to signal SD10; pin 07 corresponding to signal DRQ6; pin 08 corresponding to signal SA08; pin 09 corresponding to signal IRQ5; pin 10 corresponding to signal SDl 1; pin 11 corresponding to signal DACK7-; pin 12 corresponding to signal SA07; pin 13 corresponding to signal IRQ4; pin 14 corresponding to signal SD12; pin 15 corresponding to signal DRQ7; pin 16 corresponding to signal SA06 pin 17 corresponding to signal IRQ3 pin 18 corresponding to signal SDl 3; pin 19 corresponding to signal SA05; pin 20 corresponding to signal DACK2-; pin 21 corresponding to signal SD14; pin 22 corresponding to signal MASTER- pin 23 corresponding to signal SA04; pin 24 corresponding to signal TC; pin 25 corresponding to signal SDl 5; pin 26 corresponding to signal SA03; pin 27 corresponding to signal BALE; pin 28 corresponding to signal SA02; pin 29 corresponding to signal SAOl ; pin 30 corresponding to signal OSC; and pin 31 corresponding to signal SA00 4. A multi-chip module of Claim 3, wherein the pins of the ISA bus means extend along the first side and at least partially along the third and fourth sides. 5. A multi-chip module of Claim 2, wherein the pins of the ISA bus means comprise: pin 38 corresponding to signal SA00; pin 39 corresponding to signal OSC; pin 40 corresponding to signal SAOl; pin 41 corresponding signal SA02; pin 42 corresponding to signal BALE; pin 43 corresponding to signal SA03; pin 44 corresponding to signal SD15; pin 45 corresponding to signal TC; pin 46 corresponding to signal SA04; pin 47 corresponding to signal MASTER-; pin 48 corresponding to signal SD14; pin 49 corresponding to signal DACK2-; pin 50 corresponding to signal SA05; pin 51 corresponding to signal SDl 3; pin 52 corresponding to signal IRQ3; pin 53 corresponding to signal SA06; pin 54 corresponding to signal DRQ7; pin 55 corresponding to signal SD12; pin 56 corresponding to signal IRQ4; pin 57 corresponding to signal SA07; pin 58 corresponding to signal DACK7-; pin 59 corresponding to signal SDl 1; pin 60 corresponding to signal IRQ5; pin 61 corresponding to signal SA08; pin 62 corresponding to signal DRQ6; pin 63 corresponding to signal SD10; pin 64 corresponding to signal IRQ6OUT; pin 65 corresponding to signal IRQ6; pin 66 corresponding to signal SA09; pin 67 corresponding to GND; pin 68 corresponding to signal DACK6-; pin 69 corresponding to signal SD09; pin 70 corresponding to signal IRQ7OUT; pin 71 corresponding to signal IRQ7; pin 72 corresponding to signal SA10; pin 73 corresponding to signal DRQ5; pin 74 corresponding to signal SD08; pin 75 corresponding to signal SYSCLK; pin 76 corresponding to signal SA11; pin 77 corresponding to signal DACK5-; pin 78 corresponding to signal MEMW-; pin 79 corresponding to signal REFRESH-; pin 80 corresponding to signal SA12; pin 81 corresponding to signal DRQO; pin 82 corresponding to signal MEMR-; pin 83 corresponding to signal DRQ1; pin 84 corresponding to signal SA13; pin 85 corresponding to NCC; pin 86 corresponding to signal DACK0-; pin 87 corresponding to signal LA 17; pin 88 corresponding to signal DACK1-; pin 89 corresponding to signal SA14; pin 90 corresponding to signal IRQ 14; pin 91 corresponding to signal LA 18; pin 92 corresponding to signal DRQ3; pin 93 corresponding to signal SA15; pin 94 corresponding to signal IRQ15; pin 95 corresponding to signal LA 19; pin 96 corresponding to signal DACK3-; pin 97 corresponding to signal SA16; pin 98 corresponding to signal IRQ 12; pin 99 corresponding to signal LA20; pin 100 corresponding to signal IOR-; pin 101 corresponding to signal SA17; pin 102 corresponding to GND; pin 103 corresponding to signal IRQ1 1; pin 104 corresponding to signal LA21; pin 105 corresponding to signal IOW-; pin 106 corresponding to signal SA18; pin 107 corresponding to signal IRQ 10; pin 108 corresponding to signal LA22; pin 09 corresponding to signal SMEMR-; pin 0 corresponding to signal SA19; pin 1 corresponding to signal IOCS 16-; pin 2 corresponding to signal LA23; pin 3 corresponding to signal SMEMW-; pin 4 corresponding to signal AEN; pin 5 corresponding to signal MEMCS16-; pin 6 corresponding to signal SBHE-; pin 7 corresponding to signal IOCHRDY; pin 8 corresponding to signal SDOO; pin 9 corresponding to signal 0WS-; pin 20 corresponding to signal SD01; pin 21 corresponding to signal SD02; pin 22 corresponding to signal DRQ2OUT; pin 23 corresponding to signal DRQ2; pin 24 corresponding to signal SD03; pin 25 corresponding to signal SD04; pin 26 corresponding to signal IRQ9; pin 27 corresponding to signal SD05; pin 28 corresponding to signal SD06; pin 29 corresponding to signal RESETDRV; pin 30 corresponding to signal SD07; and pin 31 corresponding to signal IOCHCK-. 6. A multi-chip module of Claim 5, wherein the pins of the ISA bus means extend along the first side and at least partially along the third and fourth sides. 7. A multi-chip module of Claim 1, wherein the module pins comprise 240 gull wing pins. 8. A multi-chip module of Claim 1, wherein the functional circuits include a central processing unit. J 9. A multi-chip module of Claim 8, further comprising a watchdog timer means for resetting the central processing unit. 10. A multi-chip module of Claim 8, wherein the functional circuits further include two serial ports, a parallel port, a hard disk controller, a floppy disk controller, a keyboard interface, a DRAM interface and flash memory. 11. A multi-chip module of Claim 1, wherein the functional circuits include a PCMCIA interface. 12. A multi-chip module of Claim 1, wherein the functional circuits include an Ethernet interface. 13. A multi-chip module of Claim 1, wherein the functional circuits include a display controller. 14. A multi-chip module of Claim 1 , wherein the substrate comprises a printed circuit board and the functional circuits comprise semiconductor devices secured to the printed circuit board. 15. A multi-chip module comprising a plurality of functional circuits encapsulated in a rectangular housing, the housing having an upper surface and a lower surface, and a peripheral wall extending along a first side, a second side opposite the first side, a third side, and a fourth side; and a plurality of module pins extending laterally from the peripheral wall, wherein the module pins include a set of 91 signal pins, two ground pins and a power pin, defining an ISA bus means, the signal pins complying in number and signal type with the IEEE-P996 requirements. 16. A multi-chip module of Claim 15, wherein the bus pins extend along the first side and at least partially along the third and fourth sides. 17. A multi-chip module of Claim 15, wherein the module pins comprise 240 gull wing pins. 18. A multi-chip module of Claim 15, wherein the functional circuits include a central processing unit. 19. A multi-chip module of Claim 18, further comprising a watchdog timer means for resetting the central processing unit. 20. A multi-chip module of Claim 18, wherein the functional circuits further include two serial ports, a parallel port, a hard disk controller, a floppy disk controller, a keyboard interface, a DRAM interface and flash memory. 21. A multi-chip module of Claim 15, wherein the functional circuits include a PCMCIA interface. 22. A multi-chip module of Claim 15, wherein the functional circuits include an Ethernet interface. 23. A multi-chip module of Claim 15, wherein the functional circuits include a display controller. 24. A multi-chip module of Claim 15, wherein the functional circuits comprise semiconductor devices that are mounted on a printed circuit board. 25. A module family comprising a plurality of functionally different modules, wherein each module has a plurality of pins and the pins of each module include a set of 91 signal pins, two ground pins, and a power pin, defining an ISA bus means complying in number and signal type with the LEEE-P996 requirements. 26. A module family of Claim 25, wherein each module comprises at least one functional circuit encapsulated in a rectangular housing, the housing having an upper surface and a lower surface, and a peripheral wall extending along a first side, a second side opposite the first side, a third side, and a fourth side, and wherein the pins of the module extend laterally from the peripheral wall. 27. A module family of Claim 26, wherein the pins of the ISA bus means extend along the first side and at least partially along the third and fourth sides. 28. A module family of Claim 26, wherein the pins of the modules comprise gull wing pins. 29. A module family of Claim 26, wherein the at least one functional circuit of at least one of the modules includes a central processing unit. 30. A module family of Claim 29, further comprising a watchdog timer means for resetting the central processing unit. 31. A module family of Claim 29, wherein said at least one module that includes a central processing unit, further includes two serial ports, a parallel port, a hard disk controller, a floppy disk controller, a keyboard interface, a DRAM interface and flash memory. 32. A module family of Claim 26, wherein the at least one functional circuit of at least one of the modules includes a PCMCIA interface. 33. A module family of Claim 26, wherein the at least one functional circuit of at least one of the modules includes an Ethernet interface. 34. A module family of Claim 26, wherein the at least one functional circuit of at least one of the modules includes a display controller. 35. A module family of Claim 26, wherein, in each module, the functional circuits include semiconductor devices that are mounted on a printed circuit board.

Inventors: FELDMAN DAVID L, FELDMAN, DAVID, L.
Applicants: FELDMAN DAVID L, ZF MICROSYSTEMS INC, FELDMAN, DAVID, L., ZF MICROSYSTEMS, INC.
Application year: 1996
Main classification: G06F15
IPC codes: G06F13, G06F15