High speed switched OP-AMP for low supply voltage applications

Abstract: In a switched operational amplifier including a differential input stage and at least a second output stage the compensation capacitor (CC) commonly required to couple the output node of the second stage with the respective output node of the input differential stage of the amplifier is associated with switching means (M5P, M5N) controlled by the same control phase (Ph1) that enables/disables the amplifier for interrupting the connection between the compensation capacitor (CC) and the output node of the differential input stage during a phase in which the amplifier is disabled for reducing the switch-on time. Notably the differential input stage of the operational amplifier remains always active and only the second output stage is switched on and off.

Description: The present invention relates to switched-capacitors (SC) circuits, particularly for low voltage supply and low power consumption applications using at least a so-called switched op-amp for providing a high conductance input switch, under any signal condition. Switched-capacitor circuits are widely used for signal processing because of their low distortion and simple integration. Filters of any type are realized with switched-capacitor circuits. In battery operated integrated circuits, in general when operating at low voltage supply and low power consumption, there exists the need for the circuits to function at particularly low voltages down to about 1.5V. Under these conditions it is difficult to efficiently drive the switches, which are commonly constituted by field effect (FET) transistors, usually MOSFET. Indeed, when the power supply is lowered down to levels comparable to those of the threshold voltage of the devices, the classical switched-capacitor structures as shown in Fig. 1, may lose their efficiency rapidly. In order to guarantee a correct functioning of the input switch S1, whose overdrive voltage depends upon the input signal, the operating voltage swing of the circuit must be limited. A proposed solution to this problem that would ensure to the switches, and in particular to the input switch S1, a high conductance under any input signal condition, is based on realizing the switches with low voltage threshold devices or on employing dedicated dock voltage multipliers circuits integrated in the device (voltage boosters), with which the switches may then be overdriven. This second approach, while overcoming the problem of having to diversify the manufacturing process in order to realize low threshold devices, requires the integration of dedicated voltage boosters. An alternative solution based on the use of a switching structure called "Switched Op-Amp" that is represented by an operational amplifier, is disclosed in the article: "Switched-Opamp, an approach to Realize Full CMOS Switched-Capacitor Circuits at Very Low Power Supply Voltages" by Jan Crols and Michel Steyaert, Journal of Solid State Circuits, Vol. 25, No. 8, August 1994, pages 936-942. According to this approach, the proposed solution for ensuring to the switches a high conductance under any signal condition, and in particular the input switch S1, rests upon substituting the MOSFET that is conventionally used as input switch with a switched op-amp driven ON and OFF through a dedicated switch. The other switches of the switched-capacitor structure may be also realized with single n-channel or p-channel transistors, without necessarily resorting to CMOS structures. Fig. 7 of the above cited article shows the complete topology of a switched op-amp used as a switch to realize a switched-capacitor circuit. The circuit of Fig. 7 of the above mentioned article is herein reproduced as Fig. 2. The switched op-amp circuit substantially consists of two amplifying stages with a compensation capacitor CM according to a classical Miller compensation scheme. This known amplifier presents a problem concerning the switching time. Being the circuit primarily destined to switched-capacitor circuits, where switched op-amps replace those simple switches that may constitute critical elements in low voltage supply applications, the output node of the op-amp is driven to the supply voltage during a switching phase, so to avoid the use of a critical switch along the signal path. Of course, its switching speed represents a fundamental performance parameter. In the known circuit of Fig. 1, the switching time is strongly limited by the Miller capacitor CM. In fact, during a first switching phase Ph1 when the switched op-amp is OFF, the output node Vop is coupled to a very low reference voltage (or to ground) and therefore also a plate of the compensation capacitor CM. The potential of the other plate of the CM capacitor also shifts because the first stage of the amplifier is OFF. This situation is reflected in an increased switch-on time because of the charge recovering time on the compensation capacitor CM. Vis-a vis this prior art technology, the purpose of the present invention is that of reducing the switch-on time. This is achieved, according to the present invention, by modifying the compensation scheme in a way that only the second stage of the amplifier is disabled during the relative switching phase. According to a first important aspect of the invention, the compensation network includes a capacitor coupled through a switch to the respective output node of the first stage of the amplifier and to a folded-cascode stage coupled to the control terminal of a pull-down transistor, composed of two transistors. The switch linking the compensation capacitor to the folded-cascode, may be driven by the minimum supply voltage necessary to ensure a proper op-amp performance, for example with a voltage equivalent to VTH+ 2Vov (where VTH represents the threshold voltage of the switch.) In this way the compensation capacitor keeps its charge even during the OFF phase of the op-amp eliminating the need for a charge recovering time at the op-amp turn-on instant. According to an other aspect of the invention, the op-amp circuit is not completely disabled during the OFF phase but instead only the output stage is turned off, while the input stage is kept active. This further increases the switching speed which is limited only by the electric characteristics of the CMOS output pair. The different aspects and advantages of the invention will become more evident through the following description of an important embodiment and by referring to the attached drawings, wherein: Figure 1 shows a switched-capacitor circuit, as discussed in the preamble; Figure 2 as above-mentioned, reproduces the complete topology of a switchable op-amp of the prior art; Figure 3 shows the circuit topology of a switchable op-amp realized according to the invention, by way of example, in a fully differential form. Purely for illustrative purposes, Fig. 3 depicts an embodiment relative to a fully differential architecture (that is, having a differential output) of a switchable op-amp. It is evident that the invention may also be practiced in a conventional single-ended architecture instead of in a fully differential one. Having established this, the circuital aspects that implement the invention are clearly identifiable upon comparing anyone of the two branches of the fully differential amplifier of Fig. 3 with a known circuit as reproduced in Fig. 2. In relation to the Vop output branch, the modified scheme of compensation of the invention is realized by employing a switch, M5P, controlled by the control phase Ph1 which also controls the switch M6P that enables/disables the respective output stage composed of the pair of transistors M9P and M8P, while the folded stage remains ON. In this manner, the compensation capacitor CC, differently from the corresponding Miller compensator CM of the known architecture of Fig. 2, retains its charge during the interval the op-amp is disabled by the control phase Ph1. Moreover, the differential input stage of the op-amp, constituted by the M0, M1N, M1P, M2N and M2P devices, is not disabled but remains always active. The scheme of the invention is duplicated for the other Vom output branch of the switchable op-amp according to the fully differential embodiment depicted in Fig. 3. Of course, in the case of a fully differential embodiment as that of Fig. 3, it is necessary to implement a control in a common mode by applying a common mode signal ,Vcm, to the gate terminals of the two transistors M2N and M2P of the differential input stage of the op-amp. The Vcm signal may be generated by employing any known common mode voltage sensing network coupled to the Vop and Vom outputs nodes of the op-amp suitable for operating at the relatively low supply voltage for which the op-amp is designed. According to the results of test simulations of the circuit of the invention, an appreciable reduction of the switch-on time of the op-amp as compared to the case of the known architecture of Fig. 2 has been recorded. In practice the circuit of the invention is 15 times faster than the known circuit.

Claims: A switchable op-amp comprising a differential input stage and at least a second or output stage, means of enabling and disabling the amplifier controlled by a control signal (Ph1) and a compensation capacitor (CC) coupled between an output node of said second stage and a respective output node of said differential input stage of the amplifier, characterized by comprising further at least a switch (M5P, M5N) driven by said control signal (Ph1) interrupting the connection between said compensation capacitor (CC) and said output node of the differential input stage when the op-amp is disabled; a folded-cascode stage (M3P-M4P; M3N-M4N) coupling said output node of the differential input stage of the op-amp to a control node of a pull-down transistor of said output stage of the op-amp. The op-amp according to claim 1, characterized in that it has a differential output and comprises two distinct output stages, each having a compensation capacitor (CC) connected through a switch (M5P, M5N) to the respective output node of the differential input stage and to said folding cascode stage. An op-amp according to an any of the preceding claims, characterized in that said differential input stage has not any disabling means and remains always active.

Inventors: BASCHIROTTO ANDREA, CASTELLO RINALDO, NAGARI ANGELO, BASCHIROTTO, ANDREA, CASTELLO, RINALDO, NAGARI, ANGELO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1996
Main classification: H03H1
IPC codes: H03F3, H03F1