Binary decision diagram (BDD) logic device

Abstract: A binary decision diagram (BDD) logic device is fabricated on a nanometre scale. Packets of electrons (e.g. <10) are used as messenger signals and are passed from a root (R) through branches (B) to one of two leaves (L1, L2), along a path which passes through switching nodes (Nd), controlled by input signals (X i ). For at least some of the nodes, e.g. node 2 packets of electrons enter the node through MTJ1, and are selectively clocked out by tunnelling through MTJ2 or MTJ3, depending on the values of side gate voltages (V 2 , V 3 ) applied to their side gates (6), in dependence on the value of the input signal (X 1 ).

Description: This invention relates to a binary decision diagram (BDD) logic device. Binary decision diagram (BDD) logic is now commonly used to construct large scale integrated (LSI) circuits. Transistor logic circuits based on BDD architecture have several advantages as compared with the usual AND/OR combinational circuits: higher packing density, lower power consumption, and higher speed. See, for example, K Yano, Y Sasaki, K Rikino and K Seki, IEEE 1994 Custom Integrated Circuits Conference, p. 603. A binary decision diagram represents a digital function as a directed acylic graph with each node labelled by a variable. It provides a complete and concise representation for most digital functions encountered in logic-design applications. For details, reference is directed to S. B. Akers, "Binary decision diagrams," IEEE Trans. Comput., vol. C-27, no. 6, p. 509, 1978, and R. E. Bryant, "Graph-based algorithm for Boolean function manipulation," IEEE Trans. Comput., vol. C-35, no. 8, p.677, 1986. As an example, a three-variable digital function represented by the Boolean equation, (X 1 +X 2 ) X 3 will be considered. This function can be represented by the BDD in Figure 1. A BDD is a graph composed of many nodes Nd i and two leaves L i . In the Figure 1 each node is represented by a circle Nd containing the variable X 1 , X 2 , X 3 with two branches B labelled 0 and 1, and leaf L 1 and L 2 is represented by a square containing the value "0" or "1". In determining the value of the function, the diagram is entered at the root R and proceeded through downward to a leaf L. At each node Nd, the branch corresponding to the value of the variable is followed, namely, the branch B labelled 0 is followed if X i = 0 and the branch labelled 1 is followed if X i = 1. For a given set of variables there is only one path from the root to a leaf of "0" or "1." The value of the function is equal to the value of the leaf at the end of the path: the function is 0 if the end is a "0" leaf, and it is 1 if the end is a "1" leaf. Most digital systems contain multiple output functions that are closely related, and these functions can be represented as a single diagram with multiple roots. The ordering of the variables influences the size of a diagram, and several methods for determining the optimum ordering to minimise the diagram's size have been developed. BDD's corresponding to a combinational logic circuit with several thousand gates have already been designed, and still more complex BDD's are being developed. Figure 2 shows an example of a simple BDD logic device which makes use of the decision diagram shown in Figure 1. The three binary input signals X 1 -X 3 are fed on input terminals I 1 = I 3 to BDD switching nodes Nd1 - Nd3 respectively. Each node has an input and first and second outputs that are connected to first and second branches respectively. Thus, considering node Nd1 as an example, it has an input Nd1 in and outputs Nd1 out1 , Nd1 out2 that are connected to first and second branches B1, B2 respectively. The nodes Nd2 and Nd3 have a corresponding architecture with the branches being connected as shown. As previously explained, when an input set of variables X 1 , X 2 , X 3 are applied to the nodes Nd1, Nd2, Nd3, a path through the BDD logic device can be traced from the root R to a leaf L. In the device of Figure 2, a signal travels along the path and reaches a "0" or "1" leaf and the value of the function is determined by detecting which leaf the signals reaches. The signal is referred to hereafter as a messenger signal and is injected into the device by an injector at the root R shown in Figure 2. Each of the nodes Nd1, Nd2, Nd3 includes a BDD switching device BDD1-3, which switches the messenger signal between the branches connected to the node output according to the state of the input signal X i . Detector circuits D1, D2 are disposed at the leaves L1, L2 in order to detect the messenger signal. An amplifier in the form of a comparator A provides a final output. It will be understood that many different BDD trees can be constructed using the BDD devices such as BDD1 in a suitable cascade of nodes Ndi coupled between the root R and the leaves L. In the past, the switching nodes have been implemented with transistors but with large cascades of BDD devices, the transistors can take up a significant amount of space even on an LSI circuit and can consume considerable levels of power. The present invention provides an improved BDD logic device which overcomes these problems. In accordance with the invention there is provided a BDD logic device including means defining a root, leaves to provide data outputs, branches to convey messenger signals from the root to the leaves, and at least one node for switching signals between first and second ones of the branches selectively in dependence upon applied input signals, the node being adapted to receive electrical charge to a level limited by Coulomb blockade, potential barrier means coupled between the node and the first and second branches respectively, clocking means to provide a clocking waveform that causes charge carrier tunnelling between the node and the first or second branches, and means for altering the relative levels of the potential barrier means selectively in dependence upon the applied control signals whereby to cause charge carriers preferentially to tunnel between the first or the second branch and the node selectively. The present invention permits the nodes in the BDD logic device to be constructed on a nanometre scale so that the messenger signals may comprise individual or small numbers of charge carriers e.g. electrons. This arises because the node is adapted to receive charge at a level limited by Coulomb blockade. The principle of Coulomb blockade will now be described. For a nanofabricated island, if one electron is added to the island, the charging energy will increase. Consequently, an electron cannot enter the island when the charging energy is larger than the thermal energy. This is known as Coulomb blockade. Using this effect, Fulton and Dolan [T. A. Fulton and G. J. Dolan, Phys. Rev. Lett. 59 (1987) 109] demonstrated a single electron transistor in which the gate voltage controls the successive flow of single electrons. Geerligs et al. demonstrated the transfer of electrons one by one [ L. J. Geerligs, V. F., Anderegg, P. A. M. Holweg, J. E. Mooij, H. Pothier, D. Esteve, C. Urbina and M. H. Devoret, Phys. Rev. Lett. 64 (1990) 2691], synchronised with an external alternating gate voltage. For the static-confinement of discrete numbers of electrons, a single-electron box with one stable state [P. Lafarge, H. Pothier, E. R. Williams, D. Esteve, C. Urbina and M. H. Devoret, Z. Phys. B85 (1991) 327] and a single electron memory with several stable states [K. Nakazato, R. J. Blaikie, J. R. A. Cleaver and H. Ahmed, Electron. Lett. 29 (1993) ' 384 and PCT/GB93/02581] have also been demonstrated. _ In our EP-A-0 562 751, there is described a device in which a plurality of storage nodes are provided, which exhibit first and second stable storage states, in which electron transport to each node is through series connected tunnel junctions devices and limited by Coulomb blockade. A clocking system is provided to control the switching between electron states between each node. The concept of bistable or internal memory at a node, achieved by a series connected capacitance and a series of tunnel junctions or a multiple tunnel junction (MTJ) device is discussed in Averin D.V., and Likharev K. K., "Possible Applications of Single Charge Tunnelling" in H. Grabert and M. H. Devoret "Single Charge Tunnelling" (Plenum Press, New York, 1992) pp 311-332. Preferably, the potential barrier means between the node and the two branches comprise multiple tunnel barrier configurations. They may be provided with side gates. The input signals may be applied to the side gates. The or each tunnel barrier configuration may include a conductive channel that has been formed from a δ-doped layer in a substrate, the channel including a region of restricted width which exhibits the characteristics of a multiple tunnel junction. The side gate may comprise a conductive track that overlies the conductive channel. In order that the invention may be more fully understood, embodiments there of will now be described by way of example with reference to the accompanying drawings, in which: Figure 1 is a schematic diagram of a conventional BDD logic tree; Figure 2 illustrates the architecture of a conventional BDD logic device; Figure 3 is a schematic circuit diagram of a BDD logic device in accordance with the invention; Figure 4 is a circuit diagram for explaining the characteristics of a MTJ; Figure 5 is a graph illustrating the hysteresis of the circuit of Figure 4; Figure 6 is a graph of the voltage of node 2 versus electron flow, for the logic element shown in Figure 3; Figure 7 is an enlarged schematic perspective view of a MTJ structure formed in a δ-doped layer; Figure 8 is an enlarged view of the energy distribution in the constricted region of Figure 7; Figure 9 is a graph of the currents flowing through MTJs 2 and 3 of Figure 3 as a function of V 2 , with V 3 set to zero; Figure 10 illustrates an embodiment of BDD according to the invention, using MTJs; Figure 11 illustrates the form of the input signals used in Figure 10; Figure 12 illustrates the clocking waveform , used in Figure 10; Figure 13 illustrates the phase relationship of the clocking waveforms  1 ,  2 ,  3 and  4 ; Figure 14 is a circuit diagram of an alternative form of the BDD tree shown in Figure 10; Figure 15 illustrates one form of output configuration for use with a MTJ BDD tree; Figure 16 illustrates an alternative form of output configuration; Figure 17 is a schematic perspective view of another embodiment of MTJ, with an overlying side gate; Figures 18a-e illustrate process steps for fabricating the MTJ shown in figure 17, and Figure 19 is an electron micrograph of an example of the MTJ shown in Figure 17. Referring to Figure 3, this illustrates a configuration that is used according to the invention in a BDD node for use in a BDD logic tree e.g. as shown in Figure 2. The node configuration includes an input 1 for the messenger signal, a node 2 and output connections 3, 4 for connection to first and second of the branches of the BDD logic tree. Multiple tunnel junctions devices MTJ1, 2, 3 are connected between the terminals 1, 3 and 4, to the node 2, as shown. Each of the multiple tunnel junction devices receives a bias voltage V i from a voltage source 5, that is applied to a side gate 6. Thus, for MTJs 2, 3 their gates 6 2 , 6 3 respectively receive side gate voltages V 2 , V 3 . A clocking voltage V c , from a source 7 is applied through a capacitance C g to the node 2. As will be explained in more detail hereinafter, during a first half cycle of the clocking waveform, a messenger signal which comprises one or a small group of electrons e.g. <10, tunnels through the barrier configuration of MTJ1 to the node 2. A precise number of electrons tunnels through the configuration due to the fact that the charge that can be achieved at node 2 is limited by the Coulomb blockade effect. During the next half cycle of the clocking waveform, electrons which form the messenger signal are caused to tunnel out of the node 2 either to terminal 3 or terminal 4 through the barrier configurations of MTJ2 or 3. The route selected depends on the relative values of the side gate voltages V 2 , V 3 . The structure of the multiple tunnel junction devices will now be considered in more detail. As used herein, the term multiple tunnel junction device (MTJ) means a device with more than two series connected tunnelling junctions. The detailed structure of a MTJ will now be considered with reference to Figures 4 and 5 in order to explain its characteristics. Considering the MTJ shown in Figure 4, connected to the node 2, the passage of single electrons through the MTJ is prevent by Coulomb blockade when the modulus of the charge Q on one side of the device is less than a critical charge Q c i.e. when -Q c < Q < Q c where the critical charge Q c is given by Qc = eC ΣC (1+Δ) 2 Here ΣC is the total capacitance C + C g + C s , where C is the capacitance of the MTJ, Cg is the gate capacitance, and C s is the stray capacitance; Δ determines a multi-state condition given by Δ = ( N-1 ) N ( C g + C 5 ) C where N is the number of tunnel junctions in the MTJ. The voltage V at the node 2 is given by v= e ΣC ( C g V g e - n ) where n is the number of excess electrons on the node. Equation (3) is plotted in Figure 5 and consists of a series of parallel lines for different values of n, shown in dotted outline. Within a Coulomb Blockade regime, -Q c /C<V<Q c /C, electrons cannot enter or exit the memory node 2 and the upper and lower limits of the voltage ±V c of the memory node 2 that are set by Coulomb Blockade, corresponding to ±Q c /C, are shown by chain lines in Figure 5. When V reaches the boundary of this Coulomb Blockade regime, one electron enters or leaves to keep the energy of the node 2 inside the Coulomb Blockage regime. By applying a gate-voltage pulse V g with magnitude larger than eΔ/C g , the number of electrons on the node 2 can be changed as will be explained in more detail hereinafter. The resulting characteristic exhibits hysteresis and is represented by the solid line shown in Figure 5. Considering when the gate voltage is increased from the lowest value V g1 of the range shown in Figure 5, the characteristic moves along line (a) for which n=-3 (a shortfall of 3 electrons at the node 2) until the voltage of node 2 reaches the Coulomb Blockade limit V c = Q c /C. The node 2 then gains an electron by virtue of the Coulomb Blockade effect, so the characteristic jumps to the line for n=-2, since the node voltage V is limited by Coulomb Blockade. As the gate voltage is progressively increased to V gu , its upper value, the electron state of the memory node progressively increases stepwise until a surplus of 3 electrons becomes established on the node 2, i.e. n= 3. If the gate voltage V g is then decreased , the voltage at memory node 2 decreases along line (b) for n= 3, until the lower Coulomb Blockade limit -V c = -Q c /Cis reached, whereafter the electron state of the node changes stepwise to n=-3 as the gate voltage is reduced to its lower limit V gl . When the gate voltage V g is at zero, the node 2 can thus assume one of two stable states, for which, as shown in Figure 5, in this example, n= ±2, and this can be used as a memory. In general, one bit of information can be represented by + n and - n electron number states, where n is given by the integer part of (Δ+1)/2. If the capacitances are chosen to satisfy the condition Δ<1, a binary code can be represented by the presence or absence of one electron. For further details, reference is directed to our PCT/GB93/02581. The effect of applying a side gate voltage to the side gate 6 in Figure 4 will now be described. From Figure 5, it will be seen that Coulomb blockade occurs between a memory node voltage of +V c and -V c . The effect of the side gate voltage is to modify the value of the Coulomb blockade voltage V c . Thus, referring to Figure 5, the range 8 of voltage in which Coulomb blockade can be varied by varying the side gate voltage applied to the side gate 6 shown in Figure 4. For further details, reference is directed to PCT/GB93/02581 supra . Referring now to Figure 6, the disposition of the Coulomb blockade voltage regions 8 1 , 8 2 and 8 3 for MTJ1, MTJ2 and MTJ3, is shown in respect of the circuit configuration shown in Figure 3. It will be understood that a clocking voltage V c1 is applied to the node 2, which, as shown in Figure 6, varies between a minimum value of V c1 min and a maximum value of V c1 max . In operation, when the clocking voltage V c1 is reduced from its maximum value towards to its minimum value, the characteristic shown in Figure 6 moves downwardly along line b until the limit of Coulomb blockade for MTJ1 is reached namely -V C1 . As the clocking voltage is reduced further, electrons tunnel through the multiple tunnel junction barrier of MTJ1 so that the electron state at node 2 changes from n= 2 to n=-3 as a result of successive electron tunnelling through the barrier, until the clocking voltage reaches its minimum value V c1 min . When the clocking voltage increases, the characteristic moves along line (a) for the condition in which n=-3. This continues until a Coulomb blockade limit is reached. In this example, the limit is set by the Coulomb blockade limit voltage for MTJ2, namely +V c2 . When the characteristic shown as line (a) reaches +V c2 , an electron tunnels through the barrier presented by MTJ2 and the characteristic jumps to a condition n=-2, and as the clocking voltage V c1 increases, further electron tunnelling is occurs until the condition n=2 is reached. Thus, electrons from node 2 tunnel through MTJ2 and pass to terminal 3 shown in Figure 3. As previously explained, the Coulomb blockade voltage +V c2 and the corresponding voltage +V c3 are set by means of the side gate voltages V 2 and V 3 for the MTJs respectively. It can therefore be seen that by suitably adjusting the side gate voltages, the level +V c3 can be made <V c2 , in which case electrons would tunnel preferentially through the barrier of MTJ3 to the terminal 4, rather than through MTJ2 to terminal 3. Thus, electrons can tunnel either to terminal 2 or 3 depending on the settings of the side gate voltages V 2 and V 3 . Furthermore, it will be understood that the number of electrons that tunnel for each cycle of clocking voltage is determined by the voltage excursion of V c1 . The device thus operates as a turnstile in which a fixed number of electrons transfers to and from the node 2 for each cycle of clocking voltage. In this example, 6 electrons are transferred to and from the node for each cycle. The structure of the MTJ will now be described. In order to utilise the Coulomb Blockade effect, the structures must be made sufficiently small to make the charging energy larger than their thermal energy; the charging energy is proportional roughly inversely to the linear dimension. To realise a suitable very small structure, a side-gate structure in δ-doped GaAs material may be used, as shown in Figure 7. An elongate electron channel 9 is formed in a δ-doped layer 10 which is situated 30 nm below the surface of a GaAs substrate 11 and is a few atomic layers in thickness. The layer 9 is typically doped with Si to a concentration of 5 x 10 12 cm -2 and the various layers are grown by molecular beam epitaxy (MBE) or metalorganic chemical vapour deposition (MOCVD) techniques. In both processes, the thickness of the dopant layer can be introduced into only one atomic layer, and the resulting material is said to be δ-doped. [Nakazato, K., Thornton, T.J., White, J., and Ahmed, H.: "Single-electron effects in a point contact using a side-gating in delta-doped layers", Appl. Phys. Lett., 1992, 61, 3145]. A fine side-gated constriction 12 with a spaced side gate 13 is defined by electron beam lithography and wet etching to a depth of 120 nm to form the MTJ. The resistance of the junction is controllable since the application of a negative voltage to the side gate 13 changes the electron Fermi energy and repels the electrons from the edge of the electron channel. As a specific example of the process parameters, the MTJ was formed by an etched constriction with a mask width of 500 nm and length of 200 nm. The mask width at the narrowest part (i.e. side-gate to channel separation) was 150 nm. The pattern was defined by electron beam (EB) lithography and wetetching. The EB exposure was performed on a 150 nm thick polymethylmetacrylate (PMMA) coated on the δ-doped GaAs wafer. After exposure, a 30 sec development process with a weak developer (methylisobutyl-ketone : isopropyl-alcohol = 1:5) was made in order to develop only the strongly exposed regions. After 20 sec O 2 plasma etch to remove residual resist, the δ-doped GaAs layers were etched using an H 3 PO 4 : H 2 O 2 : H 2 O = 1:2 : 40 solution. The depth of the trench was controlled to 120 nm by adjusting the etch-time. The total capacitance C of the MTJ is estimated to be 5 aF from the observed Coulomb gap voltage e/ 2C ∼ 15 mV. This characteristic can be explained by postulating a series of micro-segments split by potentials of donor atoms and forming a series of single-electron transistors. The formation of several islands is supported by another measurement in the highly pinched-off region of operation in that negative resistance due to resonant tunnelling among microsegments has been observed, and by the calculation of conductance modelled using standard single-particle recursive Green's function techniques [R. J. Blaikie, K. Nakazato, R. B. S. Oakeshott, J. R. A. Cleaver and H. Ahmed, Appl. Phys. Lett. 64 (1994) 118]. The calculated potential landscape within a constriction 60 nm long and 30 nm wide is shown in Fig. 8. There are large ( ∼ 30 meV) potential fluctuations within the channel, and more than 5 potential wells are evident for the random impurity configuration used for this simulation. A test chip has been constructed consisting of a BDD logic element as described with reference to Figure 3, using side gated MTJs in a δ-doped layer. Clear switching characteristics have been obtained as shown in Figure 9, where a 6 MHz rf signal was applied as a clocking waveform V c1 to the node 2 shown in Figure 3. Currents I 2 and I 3 through MTJ2 and MTJ3 respectively were measured with a voltage of 10 mV across the logic element. The gate voltage V 3 was fixed at zero. When the gate voltage V 2 was set at zero, electrons flowed equally through MTJ2 and MTJ3. When V 2 was decreased, the Coulomb blockade region of MTJ2 expanded and electron flow was switched from MTJ2 to MTJ3. Figure 10 shows an implementation of the logic function (X 1 + X 2 ) X 3 according to the BDD shown in Figure 1, by means of BDD logic elements that employ MTJs in a manner described with reference to Figure 3. Each input signal X comprises a complimentary pair of voltages ± V as shown in Figure 11. Thus, for node Nd1, the input signal X 1 is applied to the side gates 6 of MTJ2 and MTJ3. Similarly, for node Nd2, the input signal X 2 is applied to the side gates of MTJ4 and MTJ5 respectively. Clocking waveforms  are applied to various points in the circuit as shown in Figure 12. The clocking waveform is generated as shown schematically in Figure 13. Four clocking waveforms  1 -  4 are applied, which have respective phase differences as shown in Figure 13. Thus, considering the node Nd1, clocking waveform  1 causes discrete packets for electrons to tunnel sequentially through MTJ1 to the node Nd1 and the input signal X1 causes the packets of electrons either to tunnel through MTJ2 or MTJ3 depending on the value (sign) of X 1 , according to the principles described with previously with reference to Figure 6. It will be noted that MTJ1 does not have a side gate in this example as it is not strictly necessary for operation of the device. Similarly, it will be noted that MTJ6 does not include a side gate. MTJ6 is included to maintain the correct phase relationship between the signals passing through the BDD tree, and MTJ6 cooperates with MTJ3 to operate as a turnstile. Similarly, MTJ7 cooperates with MTJ4 to operate as a turnstile and maintain the correct phase relationship for signals passing through the BDD logic tree. Figure 14 illustrates a modification in which a two-phase clocking regime is used, which permits MTJ6 and 7 to be omitted. This has the advantage of . simplifying the device structure but has the disadvantage of a higher power consumption because the capacitance of each node is higher than in Figure 14 as compared with Figure 10. In practice, a combination of the two-phase and four-phase techniques described with reference to Figures 10 and 14 can be combined in a single circuit. It will be appreciated that a number of the BDD logic circuit elements as shown in Figure 3, can be combined in different ways to achieve different BDD trees. This is shown generally in Figure 15, which can be considered as a modification of the circuit of Figure 14 with the BDD logic tree being shown generally as 14. First and second CMOS inverters A1, A2 are responsive to the electron state of the nodes which constitute the leaves L1, L2 so as to provide a binary conventional voltage output at terminals T1, T2. An alternative configuration of the CMOS inverter output stages A1, A2 is shown in Figure 16. Other output stages can be used for example single-electron transistor or a gated MTJ, instead of the CMOS transistor arrangement. Whilst satisfactory BDD logic trees can be constructed using side gated MTJs as described with reference to Figures 7 and 8, a disadvantage arises in that the side gate and electron channels for all of the devices are formed in the same plane, from the same δ-doped layer. This has the disadvantage that the circuit configuration needs to be designed so that they various conductive tracks do not overlie one another. For complicated logic circuits it is simpler to use multi-layer interconnections in order to optimise the circuit layout. Referring now to Figure 17, an alternative MTJ structure is shown which includes a constriction 15 in a δ-doped layer 10 on a substrate 11, in a conductive track 9 formed according to the principles described with reference to Figure 7. In this example, the constriction 15 is formed by bilateral cutout regions 16a, 16b on opposite sides of the conductor 9. A metallic gate layer 17 so that a voltage applied to the gate produces a functionally similar effect to a voltage applied to the side gate 13 shown in Figure 7. An example of a method of manufacturing the MTJ shown in Figure 17 will now be described with reference to Figure 18. Referring to Figure 18a, the δ-doped layer 10 was grown on the GaAs substrate 11 by MOCVD. The δ-doped layer 10 was formed 30 nm below the surface and was doped with Si to a concentration of 5 x 10 12 cm -2 . The carrier concentration is estimated to be 4 x 10 12 cm -2 from Hall resistance measurements made at liquid helium temperatures. After resist patterning by electron beam lithography, aluminium was evaporated onto the substrate to a thickness of 40 nm, and patterned by a lift-off method, to achieve the configuration shown in Figure 18a. Referring to Figure 18b, a mask 19 of 450 nm thickness PMMA was deposited on the structure and patterned by electron beam lithography to form a transverse track 19a. Then the GaAs substrate 11 was wet etched isotropically through the track 19a to a depth of 120 nm, using citric acid:H 2 O 2 (6%) = 2:1 solution so as to form the regions 16a, 16b and the corresponding constriction 15 in the δ-doped layer 10. Gold was evaporated to a thickness of 250 nm and patterned by a lift-off method so as to form the gate electrode 17 as shown in Figure 18c. Then, using the deposited A1 layer 18 and the Au layer 17 as a mask, the GaAs substrate was etched to a depth of 120 nm by a reactive ion etch method in SiCl 4 and Ar gases as shown in Figure 18d, removing GaAs from regions 20a, 20b. Thereafter, the Al layer 18 was removed using MF319 developer and the final structure was formed as shown in Figure 18e. An electron micrograph of a device constructed according to the above described method is shown in Figure 19. Many modifications and variations of the described examples of the invention are possible. Whilst the described examples make use of side gated MTJs, other single electron devices can be used with the requirement their blocking voltage be alterable in order to produce the selective switching in a manner analogous to the side gate switching function described previously. A number of different techniques have been employed hitherto in order to realise ultra-small tunnel junctions, which could be used in the BDD logic device according to the invention, including double-angle evaporation of Al [G. J. Dolan, Appl. Phys. Lett. 31 (1977) 337], and Schottky gate confinement of the two-dimensional electron gas (2DEG) formed at the GaAs/AlGaAs heterointerfaces [U. Meirav, M. A. Kastner and S. J. Wind, Phys. Rev. Lett. 65 (1990) 771, and L. P. Kouwenhoven, N. C. van der Vaart, A. T. Johnson, W. Kool, C. J. P. M. Harmans, J. G. Williamson, and A. A. M. Staring, Z. Phys. B - Condensed Matter 85 (1991) 367]. Recently, single-electron effects have been observed in several new semiconductor structures, in-plane gate 2DEG [H. Pothier, J. Weis, R. J. Haug, K. v. Klitzing and K. Ploog, Appl. Phys. Lett. 62 (1993) 3174], silicon-on-insulator (SOI) [D. Ali and H. Ahmed, Appl. Phys. Lett. 64 (1994) 2119], dual-gated Si MOS [H. Matsuoka, T. Ichiguchi, T. Yoshimura and E. Takeda, Appl. Phys. Lett. 64 (1994) 586], and SiGe structures [D. J. Paul, J. R. A. Cleaver, H. Ahmed and T. E. Whall, Appl. Phys. Lett. 63 (1993) 631]. Metallic single electron transistors can also be used in BDD devices according to the invention. They can be made in a variety of ways. The classical approach was to use the Al-Al 2 O 3 -Al structure with the oxide providing the thin tunnel barrier. The problem of achieving a small size as well as accurate alignment was overcome by using a procedure which gives self-aligned structures. A suspended or free-standing bridge of a material is fabricated by electron beam lithographic techniques. An Aluminium film is evaporated at an angle to the bridge and oxidised to form a very thin insulating layer on its surface. A second film evaporated at an angle overlaps the first film by.a few hundred nanometers if the angle is carefully chosen. This gives a metal-insulator-metal junction with a capacitance of the order of 1 fF and the device exhibits clear Coulomb blockade at low temperatures. The shadow evaporation technique has been used successfully by a number of researchers. A chromium structure was fabricated by Yu. A. Pashkin, L. S. Kuzmin, A. N. Tavkhelidze, F.-J. Ahlers, T. Weimann, D. Quenter, and J. Niemeyer, in International Symposium "Nanostructures: Physics and Technology", St. Petersburg, June 1995. Chromium has a small grain structure which gives a low potential barrier with good chemical and thermal stability. Another method was used by Chen, Ahmed and Nakazato in which a number of ultra-small gold islands were formed by ionised beam evaporation in a small gap between two narrow lines fabricated by high resolution electron beam lithography [W. Chen, H. Ahmed, and K. Nakazato, Appl. Phys. Lett. 66 (1995) 3383]. This reduced the island size and also the junction capacitance very considerably. The structure was made on a SiO 2 covered Si substrate. Clear Coulomb blockade was seen at 77K and even at room temperatures a non-linearity in the current-voltage characteristics was clearly observed. Another novel method of making atomic scale metallic islands was designed by Woodham and Ahmed which should enable the reduction of island sizes to the level of 1 nm or less so that room temperature operation of Coulomb blockade based devices may be possible [R. G. Woodham and H. Ahmed, J. Vac. Sci. Technol. B12 (1994) 3280]. In this method a focused ion beam system is used with a retarding field so that gold ions are deposited at a well controlled energy within the range 1 keV to < 100 eV to form ultra-small islands of gold on the substrate. The method has been used to make islands consisting of a few tens of atoms only and is capable of achieving single atom lithography in principle. Another effective method for making metallic tunnel junctions is to make very thin metallic wires with a discontinuity created by a step coverage break induced by a sharp-edged groove in the substrate. The sharp groove can be created in a SiO 2 layer on Si substrate. Clear Coulomb blockade has been seen in such devices [S. Altmeyer, B. Spangenberg, and H. Kurz, Appl. Phys. Lett. 67 (1995) 569, and W. Langheinrich and H. Ahmed, Proceedings of the 1995 International Microprocess Conference]. Single-electron devices can be realised in semiconductor structures by the split-gate method [T. J. Thornton, M. Pepper, H. Ahmed, D. Andrews, and G. J. Davies, Phys. Rev. Lett. 56 (1986) 1198], employing electrostatic squeezing to vary the shape of a two-dimensional electron gas at a GaAs and AlGaAs heterointerface. Meirav et al. fabricated narrow channels interrupted by two controlled potential barriers and having a tuneable electron density [U. Meirav, M. A. Kastner and S. J. Wind, Phys. Rev. Lett. 65 (1990) 771]. Kouwenhoven et al. fabricated a split-gate quantum dot structure in which gate structure allows independent control of the conductances of the two tunnel barriers separating the quantum dot from the two 2DEG leads, and enables the number of electrons localised in the dot to be varied. Field et al. investigated the behaviour of a laterally confined quantum dot in close proximity to a one dimensional channel in a separate electric circuit used as a voltage probe [M. Field, C. G. Smith, M. Pepper, D. A. Ritchie, J. E. F. Frost, G. A. C. Jones, and D. G. Hasko, Phys. Rev. Lett. 70 (1993) 1311]. Although many different materials systems have been used to demonstrate Coulomb blockade, silicon devices are of particular importance because the material is widely used and fabrication processes have been developed for metal-oxide-semiconductor (MOS) transistors that can be readily adapted for single electronics. A device structure showing clear Coulomb blockade effect in silicon-on-insulator (SOI) was first demonstrated by D. Ali and H. Ahmed in Appl. Phys. Lett. 64 (1994) 2119. The silicon island was separated from source and drain contacts by tunnel junctions formed in ultra-thin silicon. When the capacitance of such a structure was reduced the necessary condition e 2 /2C > > k B T was met at near room temperature and single electron characteristics were observed by Y. Takahashi, M. Nagase, H. Namatsu, K. Kurihara, K. Iwdate, Y. Nakajima, S. Horiguchi, K. Murase, and M. Tabe in Electron. Lett. 31 (1995) 136. SOI not only lends itself readily to a variety of fabrication processes which are compatible with future CMOS technologies but allows multiple tunnel junction (MTJ) devices to be made in silicon. Devices were fabricated on a 50 nm thick silicon layer of a silicon-on-insulator substrate formed by separation by implantation of oxygen (SIMOX). The silicon was uniformly doped to above the metal-insulator transition by implanting 1 x 10 14 cm -2 of phosphorus at 20 keV and was annealed at 950°C for 30 minutes, initially in an oxidising environment to grow at 25 nm thick oxide cap and minimise loss of dopant. The oxide cap was then removed in buffered HF. Electron beam lithography and dry etching were used to define a very narrow wire in the SOI layer, and tunnel junction regions were defined with a second stage of electron beam lithography, and etching perpendicular to the wire length, without etching all the way through the silicon. Another silicon based structure was demonstrated by H. Matsuoka, T. Ichiguchi, T. Yoshimura and E. Takeda, in J. Appl. Phys. 76 (1994) 5561. They used a double gate MOS device. One gate was used to control the inversion layer while a second patterned or grating gate was used to form islands and tunnel junctions. Both gates were fabricated by electron beam lithography between source and drain n+ regions with 5 mm separation. The gates were separated by 50 nm thick SiO 2 . Thus, all of these known devices can be used to isolate small numbers of electrons, typically less than ten, at a node, and to switch the electrons. to different branches in a BDD logic device according to the invention.

Claims: A binery decision diagram -BDD- logic device including means defining a root (R), leaves (L1, L2) to provide data outputs, branches (B) to convey messenger signals from the root to the leaves, and at least one node (Ndi, 2) for switching signals between first and second ones of the branches (B1, B2) selectively in dependence upon applied input signals (Xi), the node being adapted to receive electrical charge to a level limited by Coulomb blockade, potential barrier means (MTJ, 2, 3) coupled between the node and the first and second branches respectively, clocking means (Vcl) to provide a clocking waveform (ϕ1) that causes charge carrier tunnelling between the node (2) and the first or second branches (B1, B2), and means (V2, V3) for altering the relative levels of the potential barrier means selectively in dependence upon the applied control signals whereby to cause charge carriers preferentially to tunnel between the first or the second branch and the node selectively. A device according to claim 1 including a messenger signal input (1) for the node (2) and potential barrier means (MTJ1) between the input and the node. A device according to claim 2 including means (Vcl,Cg) for applying the clocking waveform (ϕ1) to the node (2). A device according to any preceding claim including a plurality of BDD logic elements (BDD1) coupled to one another, each of said elements comprising a respective set of two of said branches, an associated said node and potential barrier means between the two branches and the node. A device according to claim 4 including means for applying a plurality of clocking waveforms (ϕ1, ϕ2, ϕ3, ϕ4) to the BDD logic elements with a phase difference for causing charge carriers to move from node to node of the logic elements. A device according to any preceding claim wherein the potential barrier means comprise multiple tunnel barrier configurations (MTJ1, MTJ2, MTJ3). A device according to claim 6 wherein the multiple tunnel barrier configurations are provided with side gates (6). A device according to claim 7 including means for applying said input signals (X1, X2, X3) to the side gates (61, 62, 63). A device according to any one of claims 6 to 8 wherein the means providing the tunnel barrier configuration includes a conductive channel (10) that has been formed from a δ doped layer in a substrate (11), the channel including a region (12, 15) of constricted width which exhibits the characteristics of a multiple tunnel junction. A device according to claim 9 including side gate means (13, 17) adjacent the constricted region. A device according to claim 10 wherein the side gate means comprises a conductive track (17) that overlies the conductive channel. A device according to any preceding claim including output means (A1, A2) coupled to the leaves to provide an output logical signal. A device according to claim 12 wherein the output means comprises an amplifier.

Inventors: NAKAZATO KAZUO, NAKAZATO, KAZUO
Applicants: HITACHI EUROP LTD, HITACHI EUROPE LIMITED
Application year: 1996
Main classification: H03K19
IPC codes: H01L29, H03K19