Image processing method and apparatus thereof

Abstract: An image processing method and apparatus for processing an image signal using a DSP (digital signal processor), wherein shading correction process, logarithmic transformation process, edge emphasizing process, density adjustment process, binarization process or the like are performed utilizing the DSP and a look-up table outside the DSP. An image signal is inputted in an order of raster scanning, each pixel data of the image signal is set to an input register of the DSP, calculations necessary for shading correction is performed in parallel on the pixel data by a plurality of ALUs in the DSP, and a logarithmic transformation is performed on the calculation results utilizing the look-up table. Further, the logarithmically-transformed signal is inputted to the DSP and set to the input register for an edge emphasizing process which is performed by the plurality of ALUs. The result is inputted again to the look-up table for a density adjustment process and sent to the DSP, then binarized by the DSP and outputted.

Description: Present invention relates to an image processing method and apparatus for inputting an image signal, processing the inputted image signal and outputting the result. In an image processing apparatus, an original image is read by an image sensor such as a CCD and the obtained luminance signal is logarithmically transformed to generate a density signal proportional to a recorded density. Herein, since the luminance signal obtained from the sensor is a raster signal of every line, an LUT (look-up table) conversion is performed utilizing a memory of 256 words having eight address terminals, for a logarithmic transformation of an image signal with one pixel having 8 bit. A non-linear data conversion of this type is not limited to a logarithmic transformation, but other various conversions such as a γ-conversion for density adjustment, a conversion for correcting recording unevenness of solid recording elements or the like are known. Further, an edge emphasizing process or a smoothing process are performed on the image signal. Still further, calculation such as multiplying of the image data by matrix data representative of two-dimensional space filter is performed for a pattern recognition process or the like for recognizing the image. The calculation is complicated and must be executed every time one pixel is read; therefore, it is necessary to two-dimensionally store all the read image signals in a predetermined area and execute multiplication and summing on the stored two-dimensional image signals. Recently, a DSP (digital signal processor), developed for the purpose of an image processing, which comprises a number of arithmetic logic unit (ALU) for a real-time process of high-speed video signals such as an NTSC signal, makes it possible to process pixel data of one raster in parallel at each processor. Generally, the above described image processing is performed utilizing the look-up table (LUT). Such image processing where image data is converted by the LUT has an advantage that the process can be serially executed with a single LUT without considering the numbers of pixels in one raster. However, in order to perform this type of image processing utilizing the above described DSP which enables a parallel processing, memory for the LUT is necessary as many as the numbers of pixels; therefore, the size of the LUT becomes extremely large, thereby it is difficult to realize. Taking a DSP (SVP: scan-line video processor) made by Texas Instrument, Inc. as an example, the bit numbers of each register simultaneously-usable for calculating each pixel data is 256 bit. Therefore, if the foregoing LUT conversion is to be performed, the capacity of a register must be ten times larger than the one currently used. Further in the above-described multiplication and summing calculation, if an image processing area for the image data is extended, the circuit structure becomes large, thereby becomes expensive; therefore, an inexpensive circuit structure cannot be achieved. Even if a circuit utilizing the above described DSP is utilized, the image data area subjected to be processed is limited by the DSP specification. Further, even if an image processing in a wide area is possible, the processing by the DSP cannot be completed within a predetermined time. United States Patent Specification No. US 5,333,263 discloses a digital image processing apparatus which has in serial a multiplying circuit, an ALU, a bit shift circuit and a data conversion table (LUT) so that image data flows in the order. The apparatus of this specification connects three image processing circuits 7 connected in parallel to an image data bus, as shown in Fig. 16, and performs image processing on image data by using the image processing circuits 7, and image memory 2 (Fig. 18) and image input/output control blocks (Figs. 19, 20 and 21). United States Patent Specification No. US 5,184,317 discloses a method and apparatus for generating mathematical functions by using compact look-up tables (LUTs) accessed by look-up techniques. In this specification, in order to prevent the size of the LUT becoming too large, bits of an input signal are divided into two parts and the LUT conversion is reduced to 1/(power of 2) so as to form a compact LUT. European Patent Specification No. EP-A-0,118,053 discloses an ISP which mounts four PE's on one chip (Fig. 5). The PE's operate in parallel, and perform a 4x4 spatial convolution operation. One aspect of the present invention provides image processing apparatus as set out in claim 1. Another aspect of the present invention provides an image processing method as set out in claim 14. Embodiments of the present invention will now be described with reference to the accompanying drawings, in which: Fig. 1 is a block diagram of a DSP 100 (scanner-line video processor (SVP) made by Texas Instrument, Inc.) utilized in present embodiments; Fig. 2 is a block diagram explaining a series of image processing according to the present embodiments; Fig. 3 is a block diagram showing a hardware structure of an image processing circuit according to a first embodiment of the present invention; Fig. 4 is a flowchart showing a flow of a process in the SVP according to the first embodiment of the present invention; Fig. 5 is a block diagram showing a hardware structure of an image processing circuit according to a second embodiment of the present invention; Fig. 6 is a diagram showing data contents of a data input register (DIR) according to the second embodiment; Fig. 7 is a diagram showing contents of data output register (DOR) according to the second embodiment; Fig. 8 is a diagram showing contents of a register RF0 according to the second embodiment; Fig. 9 is a diagram showing contents of a register RF1 according to the second embodiment; Fig. 10 is a diagram illustrating timing of a signal input/output according to the second embodiment; Fig. 11 is a flowchart showing operations executed by a circuit shown in Fig. 5; Fig. 12 is a diagram illustrating timing of signal processing according to a third embodiment of the present invention; Figs. 13A and 13B are diagrams showing contents of an input register (DIR) according to the third embodiment; Fig. 14 is a block diagram showing a hardware structure of an image processing circuit according to the third embodiment; Fig. 15 is a flowchart showing operations executed by a circuit shown in Fig. 14; Fig. 16 is a block diagram showing a structure of an image processing apparatus according to a fourth embodiment of the present invention; Figs. 17A and 17B are explanatory views showing image data and matching data according to the fourth embodiment; Figs. 18A and 18B are explanatory views showing the image data and the matching data of Figs. 17A and 17B divided into columns; Fig. 19 is a table showing a relationship of a pixel, processed by the x-th processor element (PE) of the DSP and the matching data according to the fourth embodiment; Fig. 20 is a flowchart for obtaining an element which represents a coincidence of image data and matching data according to the fourth embodiment; Fig. 21 is a table showing an arrangement of the element data calculated by each processor element of the DSP according to the fourth embodiment; Fig. 22 is a flowchart showing a process for calculating coincident data executed by the DSP according to the fourth embodiment; and Fig. 23 is a flow chart functionally showing a process of the image processing apparatus according to the fourth embodiment. Fig. 1 is a block diagram of a DSP 100 (a scanner-line video processor (SVP) made by Texas Instrument, Inc.) according to the present embodiment. In the DSP 100, a raster image signal with a maximum width of 40 bit is inputted from an input bus 1 and stored in a data-input register (DIR) 2. The data-input register 2 is capable of storing image signals for 960 pixels (40×960 bits) and parallelly outputting the image signals for 960 pixels to a processor 3. The processor 3 is composed of 960 sets of processor elements each of which having two register files with 128 bit: RF0 and RF1, four working registers (WR) and 960 units of arithmetic logic units (ALU). All of the ALUs process the inputted image signal in parallel according to a program prepared in a single program memory unit (PM) 5. Note that in the SVP 100, the n-th PE can access to registers processed by adjoining four PEs (the (n-2)th PE to the (n+2)th PE) of the n-th PE. A result processed in the foregoing manner is transferred to a data output register DOR 4 having a 24-bit width, then performed a parallel-to-serial conversion and outputted via an output data bus 6. <First Embodiment> Fig. 2 is a block diagram explaining a series of image processing according to a first embodiment of the present invention. An image signal 21, read by a reading sensor such as an image scanner, is corrected for color unevenness at a shading correction portion 10 based upon a white signal read as a reference from a white plate. Then, a LOG transformation is performed at a logarithmic transformation portion 11 for converting a luminance signal to a density signal. At an edge emphasizing portion 12, edges are emphasized for clear reproduction of the image. After density is adjusted by a density adjusting lever at a density adjusting portion 13, the image signal is binarized by a method of organizational dither at a binarization circuit 14 and outputted to a recording apparatus to be recorded. In the first embodiment, non-linear data transformation at the logarithmic transformation portion 11 and the density adjusting portion 13 is performed employing a polynomial approximation. Note that an example is given using an ink-jet recording with one raster including 512 pixels (a serial-type inkjet printer apparatus having 512 nozzles of inkjet heads) in the first embodiment. Generally, in the logarithmic transformation process, a luminance signal F (8 bit: 0 to 255) can be transformed into a density signal D (8 bit) by the following equation (1). D=-K×Log (F/255) (K is a constant) The equation (1) can be approximated by the following polynomial. D→ K0+K1×F+K2×F×F+K3×F×F×F +K4×F×F×F×F+K5×F×F×F×F×F+........ =K0+K1×F+K2×F×F+K3×F1×F +K4×F2×F+K5×F3×F+.......... Herein, F1=F×F, F2=F1×F, F3 = F2×F are satisfied; and K0, K1, K2, k3, K4 and K5 are constants. In the equation (2), if a polynomial approximation is to be calculated up to the N-degree, the number of times for multiplication is (1+2+3+4+..... +N) times; accordingly, adding is required for (N+1) times. On the other hand, if a calculation for power of F is consecutively performed only on the input signal F, and multiplication and summing are repeated utilizing necessary values from the obtained values (F n s) of the power of F, the number of times for multiplication is [1 +2×(N-1)], which is much less than the conventional calculation. For instance, if N=15, the number of times for multiplication can be reduced from 120 times (=1+2+ 3.... +15) to 29 times (1+2×14). Further, all the range of the input signal F needs not be approximated with one type of polynomial; instead, for instance, the range can be divided into three subranges where each of the subrange is approximated with a different polynomial, and the equation (used polynomial) can be switched depending on the value of the input signal F. This way, even if a calculation with five-degree terms is executed, a logarithmic transformation can be performed with almost no error. Note that descriptions are given only on the logarithmic transformation in the first embodiment; however, general non-linear data transformations such as shading correction, edge emphasizing, density adjustment, and binarization shown in Fig. 2 can be performed similarly. Fig. 3 is a block diagram showing a hardware structure of a logarithmic transformation circuit according to the first embodiment of the present invention. In Fig. 3, a multi-plexer (MPX) 9 switches from data inputting of an MPU 16 to a raster image signal and inputs data to the SVP 100. All the above-described process is processed in the SVP 100 and a binarized result is outputted from the output data bus 6. The role of the MPU 16 is to switch the MPX 9 for inputting image data from the MPU 16 to the SVP 100 and set constants, and control loading of a program as well as timing for the SVP 100. Fig. 4 is a flowchart for explaining the logarithmic transformation process at the SVP 100 according to the first embodiment. For the purpose of explanation, the flowchart describes a flow of the processes executed in parallel, and not necessarily describes a sequence of actual operations. The MPU 16 manages data to be inputted to the SVP 100. A pixel signal (luminance signal F) for 960 pixels corrected at the shading correction portion 10 is parallelly inputted in step S1. When the pixel signal is inputted, a power value (F1, F2, F3) of the luminance signal for the pixels is calculated in step 2, and the calculation result is stored in the register RF0 or the RF1. In parallel with the above process, constants K0, K1, K2.... is inputted respectively from the MPU 16 via the MPX 9 in step 4, each of the constants is multiplied with the power value of F (F1, F2, F3....) stored in the register RF0 or the RF1 in step S3, and the result is summed according to the equation (2). The density signal D is obtained in the foregoing manner, then the result is set at the output register DOR 4, and outputted via the output data bus 6. As set forth above, according to the first embodiment, non-linear data conversion conventionally performed by the LUT conversion method utilizing a memory, can be performed by a processor capable of parallelly processing one raster of an image, with high speed, high precision and low cost. [Second Embodiment] Next, a second embodiment according to the present invention will be described. Note that the SVP 100 utilized in the second embodiment is identical to the one described with reference to Fig. 1; and the process for image processing is identical to the one described with reference to Fig. 2; accordingly, their explanations will be omitted. However differences should be noted in the second embodiment that processes of the shading correction portion 10, the edge emphasizing portion 12 and the binarization circuit 14 are performed by the SVP 100 shown in Fig. 1; and the processes of the logarithmic transformation portion 11 and the density adjustment portion 13 are performed by the LUT transformation utilizing an external memory as conventionally performed. Descriptions are given based upon an ink-jet recording with one raster including 512 pixels in the second embodiment. Fig. 5 is a block diagram showing a hardware structure of a circuit according to the second embodiment of the present invention. The SVP 100 first performs a shading correction on an input signal 1 (A) inputted via the MPX 9 and outputs to the output data bus 6. An LUT 7 comprises two RAMs each of which having 256 byte, and one of the RAMs performs a logarithmic transformation on the data from the output bus 6 and inputs back to the SVP 100 via the MPX 9. The SVP 100 stores the logarithmic-transformed signal D (0, N) for three lines, performs an edge emphasizing process for the area of 3 X 3 pixels and outputs to the output bus 6. Data conversion is performed on the edge-emphasized signal E for density adjustment utilizing the other RAM in the LUT 7 and inputted back to the SVP 100 as similar to the foregoing process. The SVP 100 performs a binarization process on the density-adjusted signal F and outputs the binarized data to the output bus 6 as a processed result. In the foregoing process, one byte in the input bus 1 (5 byte) of the SVP 100 is allocated for the input signal A, another one byte is allocated for the logarithmic-transformed signal D (0, N) which is obtained by performing logarithmic transformation on a prior raster line of the input signal A, and another one byte is allocated for the density-adjusted signal F which is obtained by performing density adjustment on two-raster prior line of the input signal A. The SVP 100 simultaneously inputs signals of three byte via the input bus 1 in the above manner and performs any of a shading process, an edge emphasizing process, or a binarization process on each signal. Further, one byte in the output bus 6 of the SVP 100 is allocated to a signal S which has been shading-corrected, other one byte to the edge-emphasized signal E, and one bit to a binarized signal O; and these signals are simultaneously outputted to the output bus 6. Data conversion is executed individually on each of the shading-corrected signal S and the edge-emphasized signal E at the LUT 7 for a logarithmic transformation and density adjustment respectively. Meanwhile, the binarized signal O is a binarization result of a signal three-lines prior to the current input signal A. Processes are performed in parallel on all the 512 pixels by an internal processor of the SVP 100. Note that the MPU 16 performs writing and reading of data to the LUT 7, MPX 9, and SVP 100. The process performed by the SVP 100 will be described next with reference to the memory map of the internal registers of the SVP 100: DIR, DOR, RF0 and RF1 shown in Figs. 6-9. Fig. 6 shows that the above described input signal A, logarithmic-transformed signal D (0, N), and density-adjusted signal F are allocated respectively to three byte of the DIR 2. After data for one raster (512 pixels) is inputted, the input signal A is transferred to an RF03 of the RF0, the logarithmic-transformed signal D (0, N) to an RF04, and the density-adjusted signal F to an RF07 as shown in Fig. 8. <Shading Correction> As shown in Fig. 8, white data W in each pixel obtained by reading the white plate as a reference and black data B obtained by turning off the light source for exposing an original image are stored in each of an RF01 and an RF02 of the register RF0. The shading-corrected signal S is obtained by performing the following calculation on the input signal A. S = 255×A / (W-B) The shading-corrected signal S obtained by the above calculation is stored in an RF11 of the register RF1 shown in Fig. 9. <Edge Emphasizing> When a logarithmic-transformed signal D (0, N) is inputted to the RF04, a logarithmic-transformed signal D (1, N) of a prior raster line and a logarithmic-transformed signal D (2, N) of a two-raster prior line have been already stored in an RF05 and an RF06 of the register RF0. An edge emphasizing signal E is obtained with the following calculation utilizing the logarithmic-transformed signals for the above described three lines. LP=4×D(1,N)-D(0, N-1)-D(0, N+1)-D(2, N-1)-D(2, N+ 1) wherein, if -K1<LP<K1 holds, LP=0 E=D(1, N)+K2×LP wherein, if E<0 holds, E=0 if E>255 holds, E=255 Herein, each of D(0, N-1) and D(2, N-1) represents data in the RF04 and RF06 which are processed by the parallelly corresponding ALUs in the processor 3, and the K1 and K2 are constants set previously by the MPU 16. The edge emphasizing signal E obtained in the foregoing manner is stored in an RF12 of the register RF1 as a signal emphasizing D(1, N). Then, data {D(1, N)} in the RF05 is copied to the RF06, similarly the data {D(0, N) } of the RF04 is copied to the RF05 to for a process at a next line. <Binarization> A binarization process according to the second embodiment is performed by a dither method with 4×4 pixels as a basic dither matrix. Descriptions of binarization by an organization dither method is given hereinafter. As shown in Fig. 8, threshold values T1, T2, T3 and T4 each having 4 byte are respectively stored in RF08, RF09, RFOA and RF0B of the register RF0. The density-adjusted signal F is binarized with the threshold value (T) . Herein, a binarization signal O satisfies the followings: if F>T holds, O=1 other 0=0 The threshold value T is selected in the order of T1, T2, T3, T4, T1, T2..., according to a value of a line counter (not shown). Then the binarized signal O is stored in an RF13 of the register RF1 (Fig. 9). When the foregoing series of process is completed and the next raster data is inputted, the shading-corrected signal S, edge-emphasized signal E, binarized signal O stored respectively in the RF11, RF12 and RF13 are transferred to the DOR 4 as shown in Fig. 7. Note that the data in the register DOR 4 is serially outputted in synchronous with the beginning of inputting of the next data as illustrated in Fig. 10. An image processing for one page is completed by repeating the above described process for one page in synchronous with a raster signal. Fig. 11 is a flowchart showing a process according to the second embodiment. The MPU 16 first sets the MPX 9 to select the input signal 8 (A). A shading correction is performed on the input signal A by the SVP 100 and the result thereof is outputted from the DOR 4 to the output bus 6 (S12). In the next step S13, the MPU 16 selects a table for performing a logarithmic transformation from the LUT 7. In step S14, the MPX 9 selects the output from the LUT 7 and the logarithmic-transformed data is inputted back to the SVP 100 via the MPX 9. As set forth above, since the SVP 100 is structured to maintain the logarithmic-transformed data D (0, N) for three lines, if data for three lines is maintained, the process proceeds from step S15 to step S16, where an edge emphasizing process is performed in the 3×3 pixel area, and then the data is outputted to the output bus 6. In step S17, the MPX 9 selects the other table of the LUT 7 and data conversion for density adjustment is performed on the edge-emphasized signal E. Then, the process proceeds to step S18 where an output of the LUT 7 is selected by the MPX 9 and inputted back to the SVP 100, similar to the above described step. Accordingly, in step S19, the SVP 100 performs a binarization process on the density-adjusted signal F and the binarized data is outputted to the output bus 6 as a final process result. <Third Embodiment> In the second embodiment, various processes as well as inputting and outputting at the SVP 100 are performed in synchronous with an input signal for one raster, as shown in Fig. 10. In the following third embodiment, a period of the input signal for one raster will be divided into six periods and a process is performed individually at each period. Fig. 12 is a diagram illustrating timing of the signal processing. An input signal of one raster is first divided into two (A1, A2) parts, velocity of the input signal is converted by a FIFO or the like, and the data is inputted to the SVP 100 within one third the period of the one raster. In this manner, the first half of 960 pixels, A1, is inputted to the DIR 2 within a Period 1 as show in Fig. 12 and transferred to the above described RF0 immediately before a Period 2. The ALU performs only the above described shading correction process on the inputted data A1 during the Period 2 and stores the result in the register RF1. Note that in the Period 2, the latter half of input data A2 is inputted to the DIR 2. Figs. 13A and 13B show the contents of the DIR 2. The shading-corrected data S1 is transferred to the DOR 4 immediately before a Period 3 and outputted from the SVP 100 in the Period 3. A logarithmic transformation is performed on the output signal S1 utilizing an RAM 72 having an LUT 1 shown in Fig. 14, and at the same time, the signal S is inputted to the SVP 100 as a signal D1. An MPX 91 in Fig. 14 switches an input addressed to the SVP 100, from the input signal 8 to an output signal of the RAM 72 in the Period 3. Note that in the Period 3, a shading correction is performed on the latter half of the input signal A2 which has been inputted in the Period 2. Similarly, an edge emphasizing process is performed on the logarithmic-transformed signal D1 in a Period 4. An edge-emphasized signal E1 is outputted in the next Period 5 and data conversion required for density adjustment is performed at a RAM (LUT 2) 71 in Fig. 14. The density-adjusted signal F1 is inputted to the SVP 100 in the Period 5 with the switching of the MPX 91. Further, the signal F1 is binarized in a Period 6 and outputted at a first period (corresponding to Period 1) of the next raster period of an input signal as a binarized signal O1. For the latter half of input signal (A2), an edge emphasizing process is performed in the Period 5, binarization process is performed in the first period of the next raster period, and a binarized signal 02 is outputted in the second period of the next raster period. Fig. 15 is a flowchart showing the process executed in the third embodiment. The first half of an input signal A1 is inputted to the SVP 100 in step S21 (Period 1). At this point, if any previous raster data is found in the SVP 100, the latter half of the data is binarized; and if the first half of the binarized signal is found in the SVP 100, it is outputted. In the next step S22, the latter half of the raster signal (A2) is inputted to the SVP 100 via the MPX 91. In step S23, shading correction is performed on the first half of the signal A1 by the SVP 100 and the result (S1) is stored in the register RF1 (Period 2). In step S24, the shading-corrected signal S1 is outputted to the output bus 6, a logarithmic transformation is performed thereon by an LUT 72, and the result (D1) is inputted to the SVP 100 via the MPX 91. In step S25, the SVP 100 performs shading correction on the signal A2 and stores the result (S2) in the register RF1 (Period 3). In the next step S26, the SVP 100 performs an edge emphasizing process on the signal D1 and stores the result (E1) in the register RF1. In step S27, the signal S2 is outputted to the output bus 6, a logarithmic transformation is performed thereon by the LUT 72 and the result (D2) is inputted to the SVP 100 via the MPX 91 (Period 4). The process proceeds to step S28 where density adjustment is performed on the edge-emphasized signal E1 by an LUT 71 and the result (F1) is inputted to the SVP 100 via the MPX 91. In step S29, the SVP 100 performs an edge emphasizing process on the signal D2 and the result (E2) is stored in the register RF1 (Period 5). In the next step S30, a binarization process is performed on the signal F1 at the SVP 100 and the result (O1) is set at the register RF1. In step S31, a density adjustment process is performed on the signal E2 outputted to the output bus 6 by the LUT 71 and the result (F2) is inputted to the SVP 100 via the MPX 91 (Period 6). Then in step S32, the binarized data (O1) stored in the register RF1 of the SVP 100 at the first period of the next raster is outputted, the signal F2 is binarized in the same period, and the result (02) is outputted from the output bus 6 in the next period. In the third embodiment, since only 8 bit of the input/output registers DIR 2 and DOR 4 is required as described above, a color image, e.g. where each of the input signals R, G and B is 24 bit, can be processed. More than 1920 pixels can be also processed by further dividing the one raster period. As set forth above, according to the second and third embodiments, an image processing conventionally performed serially by an ASIC or the like can be executed with high speed and low cost, by having a plural sets of arithmetic logic units on one chip, performing an LUT conversion on an output signal of the DSP where serially inputted data is stored parallelly and processed in parallel, and inputting the LUT-converted signal to the DSP again for further processing. Moreover, image data having large volume can be processed by dividing the period of one raster. <Fourth Embodiment> Fig. 16 is a block diagram showing a structure of an image processing apparatus according to a fourth embodiment of the present invention. A reference numeral 101 in Fig. 16 denotes a CPU for controlling the entire image processing apparatus, and 102, a program memory for storing control programs executed by the CPU 101 and various data. Note that the control programs stored in the program memory 102 can be a program, for instance, loaded from hard disk or a floppy disk. A reference numeral 103 denotes a RAM for temporarily storing various data at the time of controlling by the CPU 101, and for storing image data 110 inputted from a scanner 104 as well as matching data 111 which is utilized for determining a coincidence of the image data. An original image is photoelectrically read by the scanner 104. Note that the image data 110 stored in the RAM 103 can be image data loaded via hard disk or a communication line. A reference numeral 105 denotes a display portion consisting of an LCD or a CRT or the like for displaying inputted image data or messages to an operator. A reference numeral 100 denotes a DSP shown in Fig. 1, and a SVP made by TI (Texas Instrument, Inc.) can be given as an example. A reference numeral 107 denotes an output portion such as an NCU for outputting to a printer, a communication line or the like. A reference numeral 108 denotes a system bus which connects each of the above described portions. In the following description, explanations are given in a case where the image data 110 stored in the RAM 103 is inputted to the DSP 100 for a process; however, image data can be inputted serially from, e.g. the scanner 104, for a process. Figs. 17A and 17B are explanatory views for providing an outline of pattern matching according to the fourth embodiment. Fig. 17A, for instance, shows image data 110 read by the scanner 104 and stored in the RAM 103, in which predetermined process is performed and binarized. The matching data 111 in Fig. 17B, for instance, is structured with 10 pixels × 10 pixels and provided as a binarized data group of 100 pixels representing a shape to be matched in the image data. A coincidence level between the image data 110 and the matching data 111 can be obtained by comparing each pixel of the matching data 111 with each corresponding pixel of the image data 110 and summing the number of coincident pixels. In other words, a coincidence level SS(x, y) around the pixel of interest (x, y) can be expressed in the following equation: Herein, denotes an exclusive OR. The above process is achieved by sliding a position of a pixel of interest one pixel by one pixel on the image data and executing calculations consecutively. In order to clearly explain the above described process utilizing the parallel-process-type DSP 100, dividing of a calculation process will be described with reference to Figs. 18A and 18B. As shown in Fig. 18B, the two-dimensional matching data 111 is divided into columns M0 to M9 for every ten pixels. Image data corresponding to the divided pixel positions is similarly divided in a column for every ten pixels as shown in Fig. 18A, and each column is defined with B(x) to B(x+9). That is: M0= {M(0, 0), M(0, 1), ..., M(0, 9)} : : M9= {M(9, 0), M(9, 1), ..., M(9, 9)} and, B(x)= {B(x, 0), B(x, 1), ..., B(x, 9)} B(x+1)= {B(x+1, 0), B(x+1, 1), ..., B(x+1, 9)} B(x+9)= {B(x+9, 0), B(x+9, 1), ..., B(x+9, 9)} Therefore, the equation (3) can be expressed as follows: Herein, the following conditions are defined: With the above described condition, a process utilizing the parallel-process-type DSP 100 will be described below. As described before, in the DSP 100, each processor element (PE) comprises two register files (RF0, RF1) each having 128 bit. A predetermined process is performed on 8-bit image data inputted by raster scanning and the data is stored as binary data in one of the register files. In other words, binary data B(x) [= {B(x, 0), B(x, 1) ... B(x, 9)} ] shown in Fig. 19 is image data for ten pixels included in a column which is processed by the x-th PE. Herein, B(x, 0) is pixel data included in most-currently-inputted raster data. B(x, 1) is pixel data from a prior raster line, and similarly, B(x, 9) is from nine-raster prior line. The DSP 100 comprises 960 PEs; therefore in the entire DSP 100, image data for 10X960 pixels is maintained at all times. As raster data is consecutively inputted, the oldest raster data is deleted. Next, the process executed at the x-th PE will be described. Herein, in the DSP 100, these 960 PEs perform simultaneous and parallel processing. <Calculation of Element Data> Fig. 20 is a flowchart showing a calculation process of the equations (3) and (4). A control program for executing the process is stored in the program memory (PM) 5 in Fig. 1. In Fig. 20, variables m and n are first reset to 0 (zero) in step S41 and element data S(x, m), that is S(x, 0), is reset to 0 (zero) in step S42. Then in step S43, an exclusive OR between image data B(x, 0) and matching data M(0, 0) is calculated and the result is stored in S(x, 0). If coincident, the element value S(x, 0) becomes 0 (zero). In the above described manner, from steps S43 to S45, an exclusive OR between each of the image data B(x, 1) to B(x, 9) and each of the matching data M(0, 1) to M(0, 9) is calculated and the result is consecutively added to the element S(x, 0). As a result, element data having the maximum value of 10 and the minimum value of 0 (zero) is obtained as the element S(x, 0). In the next step S44, if n=9 is satisfied, the process proceeds to step S46 where m+1 is executed; then in step S48, element S(x-1, 1) is cleared to 0 (zero). Element S(x-1, 1) is then obtained by repeating steps S43 to S45 described above. Hereinafter, elements S(x-2, 2) to S(x-9, 9) are obtained in the same manner. When it is determined that the calculation of element S(x-9, 9) is completed in step S47, the calculation process ends. Elements S(x, 0) and S(x-1, 1) to S(x-9, 9) corresponding to the image data B(x) processed by the x-th PE can be obtained in the above described manner. Note that element S(x+1, 0) and S(x, 1) to S(x-8, 9) corresponding to image data B(x+1) is obtained by the (x+1)th PE adjoining to the x-th PE. Similarly, elements for image data corresponding to other PEs are obtained in parallel. Fig. 21 shows element data S obtained by each of the PEs and each element data is simultaneously stored in the address 0 to address 9 of the register file (RF0 or RF1 each of which having 128 bit). <Adding to Coincidence Level Data> Next, descriptions are given on the steps of obtaining coincidence level data at a position of a pixel of interest by summing the element data obtained in the foregoing calculations. Fig. 22 is a flowchart illustrating a calculation process in the PE of the DSP 100 according to the fourth embodiment, and a control program for executing the process is stored in the PM 5. In Fig. 22, a variable n is set to 8 in step S51, and in step S52 element data S at the address (n+1), processed by an adjoining processor on the right, is added to element data S at the address n. In the DSP 100, the n-th PE can access to registers allocated for PEs addressed at (n+1), (n+2), (n-1) and (n-2). Accordingly, all the PEs are capable of executing a 5×5 two-dimensional filter calculation. In other words, element data S at address 9, processed by the adjoining PE on the right, is added to the element data S at address 8. Referring to Fig. 21, the x-th PE executes the calculation: S(x-8, 8)←S(x-8, 8)+S(x-8, 9) in step S52. Similarly at the (x+1)th PE, the calculation: S(x-7, 8) ←S(x-7, 8)+S(x-7, 9) is executed. Other PEs execute the same operation. Then, n-1 is executed for the variable n in step S54 and the x-th PE executes the calculation: S(x-7, 7) ←S(x-7, 7)+S(x-7, 8) in the next step S52. Since S(x-7, 9) has been already added to S(x-7, 8) in the previous step S52, the above calculation is equivalent to the following calculation: S(x-7, 7) ←S(x-7, 7)+S(x-7, 8) +S(x-7, 9) If the above calculation is repeated nine times until n=0 is satisfied in step S53, the result is equivalent to execution of the following calculation by the x-th PE: S(x, 0)=S(x, 0)+S(x, 1)+S(x, 2)+S(x, 3)+ S(x, 4)+S(x, 5)+S(x, 6) +S(x, 7)+S(x, 8)+S(x, 9). As apparent from a comparison between the above equation and the equation (4), coincidence level data SS(x, y) can be obtained by the above calculation. Similarly, the (x+1)th PE adjoining to the x-th PE executes the calculation: S(x+1, 0)=S(x+1, 0)+S(x+1, 1)+S(x+1, 2)+S(x+1, 3)+S(x+1, 4)+S(x+1, 5) +S(x+1, 6)+S(x+1, 7)+S(x+1, 8)+S(x+1, 9) and stores the result at the address 0 (zero). This is equivalent to obtaining S(x+1, 0), where a position of a pixel of interest is shifted for one pixel from the x-th PE. Accordingly, by parallel executing these processes by ten PEs, coincidence level data representative of a coincidence level between image data for 10 pixels × 10 pixels and matching data for 10 pixels × 10 pixels, at a position where the matching data is shifted for one pixel (one row) from the inputted image data, can be stored in the address 0 (zero) of a register managed by each PE. In step S55, contents at the address 0 (zero) of a register of each processor element (PE) is examined. If it is 0 (zero), it denotes that the matching data and the corresponding image data for 10 pixels × 10 pixels are coincident, and if it is not 0 (zero), it denotes that there are non-coincident pixels and the numbers of the non-coincident pixels are determined. The characteristic of the fourth embodiment is that all the divided pattern data (coefficient data) for image data processed by each PE is calculated, as described above. In other words, although necessary data for each PE is only one data among the calculation results, calculation results required by other adjoining PEs are obtained, thereby enabling parallel processing. Further, it is possible to execute a two-dimensional multiplication and summing calculation in a wide area by consecutively summing the calculation results obtained at the adjoining PE. Note that according to the calculation examples in the fourth embodiment, the number of times for calculating an exclusive OR for one bit is 100 times, and the number of times for summing calculation for one bit is 150 times; accordingly it is possible to execute calculations in 250 instruction cycles as a whole. Fig. 23 is a functional view of the above described process. Image data is inputted in step 201 and stored in the RAM 103 as the image data 110. In step 202, the image data 110 is divided in columns or rows so that the number of bit (pixel) in a column or a row of the matching data 111, which is a calculation subject of the image data 110, coincides with the number of pixels in a column of the image data 110. In step 203, one row (column) of image data and one row (column) of matching data is calculated in each pixel unit utilizing each PE of the DSP 100. The calculation result is stored as the above-described element SS(x, y). At step 204, a coincidence level of the image data and the matching data is calculated utilizing the result calculated by the adjoining PE. <Other embodiment> Pattern matching among bit data, that is, calculation of a correlation among bit data has been described in the foregoing embodiment. The equation (3): can be applied to two-dimensional multiplication and summing calculation, if B(x+i, y+j) is a density signal having 8 bit, M(i, j), a weight coefficient for a general space filter, and if a multiplication (×) is executed instead of the exclusive OR ( ). In other words, the equation (3) is applicable to a smoothing calculation, an edge emphasizing calculation or the like without any limitations. For the purpose of explanation, a calculation area is set to 10 pixels × 10 pixels in the above description; however, the calculation area is not limited to this area as long as the DSP is able to apply a calculation result from at least one of the adjoining PE. The present invention can be applied to a system constituted by a plurality of devices such as a host computer, an interface, a printer and the like, or to an apparatus comprising a single device such as a copy machine. Furthermore, the invention is applicable also to a case where the object of the invention is attained by supplying a program to a system or an apparatus. In this case, a memory medium storing a program according to the present invention composes the present invention. By reading the program from the memory medium to a system or an apparatus, the system or apparatus performs predetermined operations. As has been described above, according to the fourth embodiment, when two-dimensional multiplication and summing calculation is performed between image data and a two-dimensional operation coefficient such as pattern data, the image data as well as the two-dimensional operation coefficient are divided in rows, and each of a plurality of parallelly-positioned ALUs executes calculations with all the two-dimensional operation coefficients for the image data divided in rows, where each ALU utilizes a calculation result of the adjoining ALU. By virtue of this feature, calculations in a wide area of image data can be executed with high speed and low cost. Further, by having a plurality of calculation units and activating them in parallel, quick calculation of two-dimensional image data and two-dimensional operation coefficient is possible. Furthermore, by performing a calculation utilizing a calculation result obtained by other calculation units, image processing is realized with less calculation time. Note that each of the embodiments has been independently described in the above descriptions, however the present invention can be also attained by appropriately combining the structures of each embodiment. The present invention is not limited to the above embodiments and various changes and modifications can be made without departing from the present invention as defined by the appended claims.

Claims: An apparatus to perform image processing, comprising inputting means (8) for inputting an image signal in raster scan order, and further comprising: first memory means (2) for storing a plurality of pixel signals included in the image signal and outputting a plurality of pixel signals in parallel; calculating means (3) comprising a plurality of sets of arithmetic logic units corresponding to said plurality of pixel signals and wherein said calculating means are adapted to execute calculations, in parallel, on each of said plurality of pixel signals outputted from said first memory means; second memory means (4) for storing in parallel said calculated pixel signals outputted by said calculating means and outputting said calculated pixel signals in raster scan order; converting means (7) for converting the calculated pixel signals outputted from said second memory means, by means of a look-up table in accordance with said raster scan order; and control means (16) for selectively switching either said converted pixel signals converted by said converting means or said image signal inputted by said inputting means, and for supplying said selected signal to said first memory or said calculating means. Apparatus according to claim 1, characterised in that said image processing is a logarithmic transformation process. Apparatus according to claim 1 or claim 2, characterised in that said image processing comprises a shading correction process. Apparatus according to any one of claims 1 to 3, characterised in that said image processing comprises an edge emphasizing process. Apparatus according to any one of claims 1 to 4, characterised in that said image processing comprises a density adjustment process. Apparatus according to any preceding claim, characterised in that said image processing is a binarization process. Apparatus according to claim 1 wherein said calculating means comprise: power calculating means for calculating a power value for each of the pixel signal stored in said first memory; and multiplying means for multiplying each said power value by a constant to compute multiplied values ; summing means for summing each of said multiplied values ; and control means for controlling said power calculating means, said multiplying means and said summing means in such away to perform calculation of a function related to said image processing by approximating said function with a polynomial. Apparatus according to claim 1, characterised in that said calculating means (3) comprises maintaining means for maintaining plural lines of said image signal, and means to perform an edge emphasizing process based on said plural lines of said image signal maintained by said maintaining means. Apparatus according to claim 1 or 2, characterised in that said calculating means (3) further comprising means to store a threshold value, and means to perform a binarization process by comparing said inputted image signal with said threshold value. Apparatus according to any one of claims 1 to 3, characterised in that said converting means (7) further comprising means adapted to perform logarithmic transformation by means of said look-up table. Apparatus according to any one of claims 1 to 3, characterised in that said converting means (7) further comprising means to perform density adjustment of said image signal by means of said look-up table. Apparatus according to any one of the preceding claims, characterised in that said calculating means (3) includes a plurality of processors embodied in one chip of a digital signal processor. Apparatus according to any one of the preceding claims, characterised in that said plurality of sets of arithmetic units includes the same number of sets of arithmetic units as the number of said plurality of pixel signals output in parallel from said first memory means and wherein said plurality of sets of arithmetic units further comprising means to output in parallel the same number of calculated pixel signals as said number of plurality of pixel signals output in parallel from said first memory means. An method to perform image processing, comprising the steps of: inputting (S11) an image signal as a plurality of pixel signals in raster scan order; storing said plurality of pixel signals in a first memory means and outputting said plurality of pixel signals in parallel from said first memory means (2) ; calculating (S12, S16, S19) step to perform parallel calculations on each of said plurality of pixel signals outputted from said first memory means by means of calculation means comprising a plurality of sets of arithmetic and logic units wherein said plurality of sets of arithmetic and logic units correspond to said plurality of pixel signals; inputting calculation results related to said inputted plurality of pixel signals by said calculating step in parallel into a second memory means (4), and outputting said results from said second memory means in the order of the raster scanning; converting (S13, S17) said calculation results of said plurality of pixel signals outputted in raster scan order of said raster scanning from said second memory means by utilizing a look-up table; and selectively switching (S11, S14, S18) said plurality of pixel signals converted in said converting step or said plurality of pixel signals included in said input image signal and supplying said selected signal to either said first memory means or said calculation mean performing said parallel calculations. A method according to claim 14, characterised in that in said calculating step (S16), plural lines of said image signal are maintained and wherein an edge emphasizing process is performed based on said maintained plural lines of image signal. A method according to claim 14 or 15, characterised in that in said calculating step (S19), a threshold value is stored and wherein a binarization process is performed by comparing said inputted image signal with said threshold value. A method according to any one of claims 14 to 16, characterised in that in said converting step (S13), logarithmic transformation is performed utilizing said look-up table. A method according to any one of claims 14 to 17, characterised in that in said converting step (S17), density adjustment is performed on said image signal utilizing said look-up table. A method according to any one of claims 14 to 18, characterised in that in said calculating step (S12, S16, S19), calculations are executed by said calculation means comprising a plurality of processors embodied in one chip of a digital signal processor. A method according to any one of claims 14 to 19, characterised in that in said calculating step (S12, S16, S19), said calculation means using a plurality of sets of arithmetic and logic units being the same number as the number of said plurality of pixel signals outputted in parallel from said first memory means and wherein said calculation means outputs in parallel the same number of calculated pixel signals as the number of said plurality of sets of arithmetic and logic units. Storage means to store a set of instructions that when executed on a processor perform all the method steps of any of claims 14 to 20.

Inventors: TANIOKA HIROSHI, UMEDA YOSHINOBU, TANIOKA, HIROSHI, UMEDA, YOSHINOBU, Tanioka, Hiroshi, c/o Canon K.K., Umeda, Yoshinobu, c/o Canon K.K.
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1996
Main classification: G06T1
IPC codes: G06T5, G06T15