INTERFACE CIRCUIT AND DATA PROCESSING APPARATUS AND METHOD

Abstract: A data to be processed by CPU (11) is sequentially read from an external storage device (21), and transferred to first and second memories (24, 25) alternatively. CPU (11) accesses the one of the first and second memories (24, 25) alternatively, and processes the data previously read.

Description: INTERFACE CIRCUIT AND DATA PROCESSING APPARATUS AND METHOD BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to an interface circuit capable of fast data transfer between an external storage device and a CPU (Central Processing Unit). This invention also relates to a data processing apparatus and method which can access an external storage device at a high speed. Description of the Related Art An ordinary data processing apparatus is equipped with an external storage device, such as a hard disk or a CD-ROM, and executes data transfer between its internal memory and the external storage device to carry out data processing. The access time of the external storage device is however very slow as compared with the operation speed of a CPU, and this slow speed reduces the throughput of data processing. In particular, an application which processes a vast amount of bit map image data or the like takes time to transfer data with an external device, which interferes with the thinking of an operator. SUMMARY OF THE INVENTION Accordingly, the object of the present invention to provide methods and devices for high speed transfer of data between an external memory device and internal memory of a computer. The high speed data transfer device comprises a first memory, a second memory, a first circuit for communicating data with the external memory device, and a second circuit for communicating data with the internal memory. The device also comprises a data switching circuit which alternative couples the first circuit to one of the first and second memories and alternatively couples the second circuit to the remaining one of the first and second memories. When the first circuit is coupled to the first or second memory, data is transferred between the external memory device and the first or second memory. When the second circuit is coupled to the first or second memory, data is transferred between the first or second memory and internal memory. One of the advantages of the above data transfer device is that the first and second circuits can perform different data transfer operation concurrently. For example, the external memory device can transfer data to the first memory while the internal memory can transfer data from the second memory. When the first memory is full, the second memory is empty. The external memory can then be switched to the second memory. Consequently, the external memory can continue to transfer data to the second memory while the internal memory can continue to transfer data from the first memory. As a result, data can be transferred between the external memory device and the internal memory almost continuously. In a preferred embodiment, the first memory, the second memory and the internal memory are semiconductor devices. Because the external memory device is a mechanical device, the time required for data transfer is long. Thus, data transfer from and to the internal memory would be completed while the external memory device is still in operation. Because the external memory device is controlled by the data transfer device of the present invention, the CPU of the computer would normally be sitting idle. One aspect of the present invention is a method for utilizing the idle CPU time. The data transfer device further comprises means for generate status signals related to the data switching. A software driver responsive to the status signal can allow other software programs to run during the time period the CPU is not needed for data transfer. As a result, the CPU would not be sitting idle. Because the inventive data transfer device and the inventive software driver act synergically in speeding up of program execution involving external memory device access, the inventive software should be used to replace conventional drivers (such as IBM personal computer's BIOS hard disk device service routine). These and other features and advantages can be understood from the following detailed description of the invention together with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram illustrating the structure of a data processing apparatus according to the first embodiment of this invention. Fig. 2 is a block diagram showing the structure of a transfer controller shown in Fig. 1. Fig. 3 is a timing chart illustrating the relationship between the timing of reading data from a hard disk and the timing of processing read data. Fig. 4 is a diagram used for explaining a plurality of blocks which construct map data. Fig. 5 is a diagram showing a window opened on a map defined by map data. Fig. 6 is a diagram illustrating the movement of a window on a map. Fig. 7 is a diagram showing the shifting of an image in a window. Figs. 8A and 8B are diagrams showing the shifting of an image in a window. Fig. 9 is a block diagram illustrating a modification of the data processing apparatus. Fig. 10 is a block diagram of a computer system incorporating a data transfer device according to the second embodiment of the present invention. Fig. 11 is a flow chart showing the operation of the data transfer device. Fig. 12 is a flow chart showing another mode of operation of the data transfer device. Fig. 13 shows the relative timing between various cycles during the operation of the data transfer device. Fig. 14 is a block diagram of a computer system containing a data transfer interface and a software driver in accordance with the present invention operating in a Windows based environment. Fig. 15 is a flow chart showing the operation of the system shown in Fig. 14. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First embodiment A data processing apparatus and an interface circuit according to the first embodiment of this invention will be described below. Fig. 1 shows the structure of the data processing apparatus according to the first embodiment. As illustrated, this data processing apparatus comprises a CPU (Central Processing Unit) 11 , a ROM 13, a video RAM (VRAM) 14 and a display device 15 for displaying the contents of VRAM 14. ROM 13 and VRAM 14 are connected to CPU 11 by a first bus 12. CPU 11 performs data processing, and the general control of the system. First bus 12 is designed to conform to the EISA standards, for example, and includes a data bus, an address bus and a control bus. ROM 13 has stored control programs which are to be executed by CPU 11 , fixed data, etc. VRAM 14 stores bit map data which defines a display image. Display device 15 is comprised of a CRT, a liquid crystal display device or the like. This data processing apparatus further includes an external storage device (auxiliary storage device) 21 such as a hard disk or CD-ROM. In this embodiment, external storage device 21 is a hard disk. Hard disk 21 , which conforms to the SCSI (Small Computer System Interface) standards, is connected to an SCSI interface 22 via a parallel line. According to this embodiment, raster type (bit map type) image data is serially stored in hard disk 21 to ensure fast access. SCSI interface 22 is connected to a transfer interface 23. Transfer interface 23 has first and second memories 24 and 25 to be accessed by CPU 11 , and a transfer controller 26. Each of first and second memories 24 and 25 is comprised of a dual-port fast memory like a 2-port SRAM memory., First ports of first and second memories 24 and 25 areconnected to CPU 11 by a second bus 27. CPU 1 reads or writes data from or in those memories 24 and 25 through the first ports. Second bus 27 conforms to the EISA standards, for example. Transfer controller 26 is connected to second ports of first and second memories 24 and 25, SCSI interface 22 and second bus 27, and controls data transfer between hard disk 21 and first and second memories 24 and 25 under the control of CPU 11. As shown in Fig. 2, transfer controller 26 has a SCSI port 31 , a CPU port 32, a first port 33, a second port 34, registers 35, a first transfer circuit 36, a FIFO (First In First Out memory) 37, a second transfer circuit 38, a first address counter 39, a second address counter 40 and a controller 41. SCSI port 31 is connected via an exclusive line to SCSI interface 22. CPU port 32 is connected to second bus 27. The first port 33 is connected via exclusive lines to the second port of first memory 24. Second port 34 is connected via exclusive lines to the second port of second memory 25. Flags, data indicative of writing or reading, the head address and so forth set by CPU 11 are set in registers 35. First transfer circuit 36 transfers data between FIFO 37 and SCSI interface 22 (hard disk 21 ). Second transfer circuit 38 transfers data between FIFO 37 and first memory 24 or second memory 25. First transfer circuit 36 and second transfer circuit 38 are constituted by, for example, DMA (Direct Memory Access) circuits. First transfer circuit 36 operates in accordance with the operation clock of, e.g., 20 MHz, and second transfer circuit 38 operates in accordance with the operation clock of, e.g., 40 MHz. FIFO 37 buffers the difference between the data transfer rate of first transfer circuit 36 and that of second transfer circuit 38, and intervenes between first and second transfer circuits 36 and 38 for data exchange therebetween. First address counter 39 counts the address of first memory 24. Second address counter 40 counts the address of second memory 25. Controller 41 controls the operations of the individual sections of the internal circuit of transfer controller 26. The basic operation of transfer interface 23 will now be described. To begin with, a description will be given of the case where a vast amount of data is read from hard disk 21 to be processed by CPU 11. CPU 11 supplies an instruction indicative of data reading, the head (start) address of the area in hard disk 21 where data to be read is stored, and a transfer request signal (DMA request) to transfer controller 26 via second bus 27. The transfer request signal (DMA request) includes data indicating which one of first and second memories 24 and 25 data should be stored in first. Controller 41 sets data, flags and the like, which are included in the transfer request signal in the associated registers 35, and sets the individual sections in the associated operation modes. Controller 41 initializes first and second address counters 39 and 40. The transfer request signal is also supplied to SCSI interface 22. When completing the setting, controller 41 sends out an acknowledge signal ACK to CPU 11. This signal ACK frees CPU 11 from the data transfer operation and allows CPU 11 to execute other processing. In response to the transfer request from CPU 11 , SCSI interface 22 instructs hard disk 21 to read data. In response to this instruction, hard disk 21 starts to reads data from this head address and sends the data to SCSI interface 22 via the exclusive line. Every time data is supplied from SCSI interface 22, first transfer circuit 36 sends the data to FIFO 37. Second transfer circuit 38 sequentially acquires data input to FIFO 37, and sends it to the memory specified by CPU 11 , e.g., first memory 24. First memory 24 stores the supplied data at the position specified by first address counter 39. Every time second transfer circuit 38 transfers data once, first address counter 39 updates the count value (address value). The renewed value corresponds to the number of bytes of data to be transferred in a single transfer process. Thereafter, data is sequentially read from hard disk 21 and is stored in first memory 24. As data transfer progresses and the transfer of a predetermined amount, e.g., 64 Kbytes, of data is completed, transfer controller 26 sends a transfer end interrupt signal INT to CPU 1 1 via second bus 27. In an interrupt process in response to the interrupt signal INT, CPU 11 outputs a transfer request signal including information like the head position of the area from which data is to be read next, and reactivates transfer controller 26. This reactivation causes data to be transferred again. As data transfer progresses and first memory 24 is filled with the transferred data, transfer controller 26 supplies the interrupt signal INT to CPU 11. In an interrupt process in response to the interrupt signal INT, CPU 11 outputs a transfer request signal indicating second memory 25 as the target memory to transfer controller 26. Controller 41 initializes the count value of second address counter 40. Thereafter, data read from hard disk 21 is sequentially transferred to second memory 25. While data is stored in second memory 25, CPU 11 reads data from first memory 24 and processes it. When the data transfer to second memory 25 and the processing of data stored in first memory 24 are both completed, CPU 11 sends out a transfer request signal indicating data transfer to first memory 24, the reading position and the like to transfer controller 26. In accordance with this request signal, controller 41 initializes first address counter 39. As a result, the data which has been read from hard disk 21 is sequentially stored in first memory 24 during which time CPU 11 processes data stored in second memory 25. The same operation will be repeated thereafter. More specifically, CPU 11 processes data stored in first and second memories 24 and 25 alternatively and repeatedly. And, transfer controller 26 previously transfers data to be processed next into the memory other than the memory to which CPU 11 is accessing. When the interrupt signal INT, indicating that the transfer of the last block of data to be transferred, is sent to CPU 11 , the data transfer is terminated. The processing timings of the above-described operation are illustrated in Fig. 3. As apparent from this diagram, the period of CPU 11 to wait for transferred data after the generation of the request to process data in hard disk 21 is only the period in which first memory 24 is filled first. Thereafter, data to be processed is previously prepared in the associated memory. Therefore, fast data processing is possible without being restricted by the data transfer rate. When the processing of CPU 11 is completed before the transfer of data to be processed is finished, CPU 11 executes other processing and returns to the data processing in accordance with the interrupt signal INT indicating the end of the transfer. When the transfer of data to be processed next is completed before the processing of CPU 11 is finished, transfer controller 26 waits for the next instruction from CPU 11. A description will now be given of the case where a vast amount of data processed by CPU 11 is sequentially transferred to hard disk 21 to be stored there. First, CPU 11 executes data processing and stores data in first or second memory 24 or 25. When a predetermined amount of data is produced, CPU 11 sends a instruction indicating data-writing and a transfer request signal to transfer controller 26 via second bus 27. The transfer request signal indicates that data in first memory 24 should be transferred first, the head address of the writing area and so forth. Controller 41 sets the individual sections in the associated modes. CPU 11 also informs SCSI interface 22 of the mode of writing data and the head address of the target writing area in hard disk 21. When the setting is completed, controller 41 sends out the acknowledge signal ACK to CPU 11. This signal ACK frees CPU 11 from the data transfer operation, resumes data processing and writes data originating from the data processing in second memory 25. In accordance with the transfer request signal, second transfer circuit 38 sequentially reads out data from the position in first memory 24 specified by address counter 39, and stores the data in FIFO 37. First transfer circuit 36 acquires data from FIFO 37 and provides SCSI interface 22 with that data. SCSI interface 22 sequentially writes the supplied data from the specified head address. The same operation will be repeated thereafter, so that every time one block of data is transferred, the interrupt signal INT is sent to CPU 11. In response to the interrupt signal INT, CPU 11 requests data transfer again. When the transfer of stored data in first memory 24 is completed and the writing of data in second memory 25 is completed, CPU 11 switches the transfer memory to second memory 25 and the writing memory to first memory 24. Second transfer circuit 38 sequentially reads data from the position pointed by second address counter 40 and inputs the data in FIFO 37. Meanwhile, first transfer circuit 36 sequentially reads data from FIFO 37 and supplies it to SCSI interface 22. SCSI interface 22 supplies the received data to hard disk 21 and writes it there. The same operation will be repeated thereafter. In writing data, while CPU 11 is accessing one memory 24 or 25 and preparing data, data already prepared in the other memory 25 or 24 is read and transferred to hard disk 21. CPU 11 can therefore execute data processing without being bothered by the time needed for data exchange with hard disk 21. Therefore, CPU 11 can process a huge amount of data like the processing of image data at a fast speed. Unlike disk caching, this data transfer does not require the determination of hit or unhit of data or replacing or the like in the case of data being unhit, thus simplifying the structure of the control system and improving the operation speed. The general operation of the data processing apparatus will now be specifically described with reference to the case where a window is opened on an image like a map and the window is displayed while being moving on the map. It is to be noted that raster type (bit map type) map data is sequentially stored in hard disk 21 in this embodiment. Map data is divided into a plurality of blocks each consisting of a matrix of 512 x 512 bits, as shown in Fig. 4. Each piece of data has a depth (number of bits) of eight bits. In accordance with the control programs stored in ROM 13, CPU 11 forms a window 52 on a large virtual map 51 which is defined by map data, and displays a part of map 51 through window 52. Window 52 and map 51 on window 52 are developed in the bit map form and displayed on display device 15. Under this situation, a user instructs the upper rightward scroll (by which the window moves upper rightward and the map appears to move lower leftward), CPU 11 shifts window 52 on map 51 every given period by a predetermined amount as shown in Fig. 6. The amounts of shifting of window 52 on map 51 in the X and Y directions are denoted by Δx and Δy. As window 52 moves, CPU 11 acquires the data blocks that newly become necessary to display map 51. That is, CPU 11 detects that data of blocks B1 to B16 are needed. To read those data from hard disk 21 , CPU 11 sends the transfer request signal, which indicates the reading of data, the head address of block B1 , the prewriting of read data in first memory 24 and the like, to transfer controller 26 and SCSI interface 22 via second bus 27. In response to this information, hard disk 21 sequentially reads data of block B1 and supplies the data to transfer controller 26 via SCSI interface 22. First transfer circuit 36 in transfer controller 26 sequentially stores map data, supplied piece by piece from SCSI interface 22, into FIFO 37. Second transfer circuit 38 sequentially reads data from FIFO 37, and stores the data at the position pointed by first address counter 39 of first memory 24. While the data of block B1 is being transferred to first memory 24 from hard disk 21 , CPU 11 is released from the data transfer processing and executes a process of shifting map data in VRAM 14. More specifically, the map data of the individual bits on window 52 in VRAM 14 are sequentially shifted to the positions where the X addresses are shifted by -Δx and the Y addresses are shifted by -Δy and written accordingly as shown in Fig. 7, so that the window is shifted from the state in Fig. 8A to the state in Fig. 8B. When receiving the interrupt signal indicating the end of the transfer of block B1 from transfer controller 26 during this shifting process, CPU 11 executes the interrupt process and issues the transfer request signal for reading the next block B2. In accordance with this transfer request signal, transfer controller 26 and SCSI interface 22 sequentially read the data of block B2 from hard disk 21 and write the data in an empty area in first memory 24. When the shifting of the map data on window 52 in VRAM 14 is completed and the interrupt signal INT indicative of the end of the transfer is supplied from transfer controller 26, CPU 11 outputs the transfer request signal for reading the next block B3. In accordance with this transfer request signal, transfer controller 26 and SCSI interface 22 sequentially read the data of block B3 from hard disk 21 and write the data in second memory 24 from the head position in order. While transfer controller 26 is reading data, CPU 11 cuts away the necessary portion (which is to be displayed on window 52) from the map data of block B1 read out into first memory 24, and writes it in the associated portion in VRAM 14. Likewise, CPU 11 writes the portion of block B2 to be displayed in the associated area in VRAM 14. Thereafter, pre-reading of a block to be processed next into one memory and writing the necessary portion of data read into the other memory in VRAM 14 are executed in parallel and alternately in the same manner. When all the necessary map data are read into first and second memories 24 and 25, the transfer operation is ended, while when the writing of the necessary data into window 52 in VRAM 14 is finished, a single shift operation is completed. The above-described shifting process is repeatedly executed every given period while the shifting of window 52 on map 51 is kept instructed. Of blocks B1 to B16, blocks B11-B16 are data used at the time of displaying window 52 at the previous position. When the data of blocks B11- B16 are stored in first memory 24 or second memory 25, therefore, the data will not be re-read from hard disk 21 and the shifting process will be executed using the data remaining in the memory. A description will now be given of the case where raster data is read from hard disk 21 and is combined with a vector image to form a new raster image and this new raster image is written again in hard disk 21. In this case, for example, the raster image is registered in first memory 24 after which the raster image is registered in second memory 25. While the raster image is being registered in second memory 25, vector data is developed to be combined with raster data previously stored in first memory 24. Subsequently, while the raster data in second memory 25 and the newly developed vector image are being combined, the combined data in first memory 24 is transferred to hard disk 21 and then data to be processed next is read from hard disk 21. According to this embodiment, in short, two memories are prepared so that while the CPU is accessing one memory, data is transferred between the other memory and the hard disk, and data processing and data transfer are executed in parallel and alternately for the individual memories. The CPU can therefore access to data in the hard disk at the speed close to the speed of accessing a fast memory. Particularly, this feature is effective at the time of processing a vast amount of image data at a high speed or a similar case. The number of memories is not fixed, and three or more memories may be provided. The number of memories should be increased as the speed of CPU 11 gets slower with respect to the data transfer rate, and the optimal number of memories should be used according to the specifications of each system. The same is true of the capacity of each memory. Although the above-described embodiment uses separate first bus 12 and second bus 27 for the high-speed operation, both buses may be replaced with a common bus as shown Fig. 9. As described above, this invention can ensure fast data transfer between an external storage device and a CPU, thus accomplishing fast data processing. Second embodiment In the first embodiment, the FIFO is provided between first and second memories and the external memory device. A modification may be made to transfer data between first and second memories and the external memory device using a timing adjustment circuit. The second embodiment using the timing adjustment circuit will be described below. Fig. 10 is a block diagram showing a computer system 100 incorporating a data transfer device of the present invention. System 100 comprises a bus 108 connecting a CPU (central processing unit) 102, internal memory 104, and a data transfer device 110. In the present invention, bus 108 refers to one or more buses typically found in a computer system. Examples of buses are a system bus and peripheral bus (e.g., PCI, local bus, ISA, and EISA buses typically found in IBM compatible personal computers). In the present invention, internal memory 104 could be any memory addressable via bus 108. For example, memory 104 can be the system memory (typically connected to a system bus) or video memory (typically connected to a peripheral bus). Data transfer device 110 can be implemented as a peripheral board or encapsulated in a semiconductor chip. In one embodiment of the present invention, memory 104 and CPU 102 are connected to a system bus while device 110 is a peripheral board connected to an ISA bus. Computer system 100 also comprises a hard disk 112 containing data. One aspect of the present invention is a system for rapidly transferring data between hard disk 112 and memory 104. As explained below, a pair of random access memory (RAM) inside device 110, labelled as RAM A and RAM B, is used to temporarily store the data transferred between hard disk 112 and memory 104. The structure of data transfer device 110 is now described. Device 110 contains a bus interface 106 for connecting circuits inside device 110 to bus 108. Bus interface 106 allows data and control signals to be communicated between these circuits on one hand and memory 104 and CPU 102 on the other hand. Device 110 contains a "small computer system interface" (SCSI) controller 122, which communicates data and control information with hard disk 112 in the standard SCSI protocol. The design of such a controller is well known in the art and will not be discussed here. SCSI controller 122 is preferably in the form of a semiconductor chip. SCSI controller 122 is connected to a SCSI processing circuit 124. SCSI processing circuit 124 is connected to bus interface 106 and a timing adjustment circuit 130. SCSI processing circuit 124 performs the following operations: (1) receives commands and status information from CPU 102 via bus interface 106; (2) controls hard disk 112 (through SCSI controller 122) in accordance with these commands and status information; (3) in cooperation with timing adjustment circuit 130, transfer data to and from a RAM processing circuit 132; and (4) sends status information to CPU 102 via bus interface 106. For example, SCSI processing circuit 124 can activate and deactivate the transfer of data to and from hard disk 112. The status signals generated by SCSI processing circuit 124 could be used by a software driver which is designed to work with data transfer device 110. The operation of this driver will be explained in detaii below in connection with Figs. 11 and 12. In this embodiment of the present invention, hard disk 112 conforms to the SCSI standard. However, the present invention is equally applicable to hard disks conforming to other standards, e.g., IDE (integrated drive electronics) or EIDE (enhanced integrated drive electronics). In the present invention, data is not directed transferred between hard disk 112 and internal RAM 104 of computer system 100. Instead, data is temporarily stored in a pair of random access memory devices inside data transfer device 110 (shown as RAM A and RAM B). Data transfer by RAM A and RAM B is fast. On the other hand, data transfer by hard disk 112 is typically slow and not synchronous to the data transfer of RAM A and RAM B. Timing adjustment circuit 130 serves to coordinate and synchronize the hard disk and RAM A RAM B data transfers. In order to be able to achieve the above described functions, SCSI processing circuit 124 contains a status processing circuit 146 (for receiving, processing and generating status signals) and a data flow circuit 148 (for controlling the transfer of data to and from hard disk 112). The design of these circuits should be within the skill of persons skilled in circuit design art. Timing adjustment circuit 130 is connected to a RAM processing circuit 132. This RAM processing circuit 132 is also connected, via bus interface 106, to CPU 102 and internal RAM 104. In addition, RAM processing circuit 132 is connected to RAM A and RAM B inside data transfer device 110. RAM processing circuit 132 comprises a switch 134 for connecting RAM A and RAM B on one hand to timing adjustment circuit 130 and bus interface 106 on the other hand. Specifically, if it is desirable to transfer data between SCSI processing circuit 124 to either RAM A or RAM B, switch 134 causes timing adjustment circuit 130 to be connected to the appropriate memory. Similarly, if it is desirable to transfer data between internal RAM 104 to either RAM A or RAM B, switch 134 causes bus interface 106 to be connected to the appropriate memory device in data transfer device 110. It should be note that RAM A may be connected to either timing adjustment circuit 130 or bus interface 106 at a given time, but cannot be simultaneously connected to both timing adjustment circuit 130 and bus interface 106. Similarly, RAM B may be connected to either timing adjustment circuit 130 or bus interface 106 at a given time, but cannot be simultaneously connected to both timing adjustment circuit 130 and bus interface 106. Also, data cannot be directly transferred between timing adjustment circuit 130 and bus interface 106. The detailed operation of switch 134 in connection with the transfer of data will be described below. In order to monitor the amount of data in RAM A and RAM B, RAM processing circuit 132 contains two byte processing units. Each unit contains a counter and means for matching the electrical signal between RAM A or RAM B and RAM processing unit 132. These units will be referred to as counters 136 and 138. RAM processing circuit 132 monitors the transfer of data from/to RAM A and RAM B and decrement/increment the value of counters 136 and 138, respectively. As a result, the values of counters 136 and 138 provide an indication of the amount of data stored in RAM A and RAM B, respectively. Another function of RAM processing circuit 132 is to receive commands and status information from CPU 102 via bus interface 106. RAM processing circuit 132 then controls the transfer of data between internal RAM 104 on one hand and RAM A and RAM B on another hand in accordance with the received commands and status information. RAM processing circuit 132 may also send status signals to CPU 102. These signals could be used by software modules which are designed to use data transfer device 110. A status processing circuit 152 is included in RAM processing circuit 132 to perform these functions. Because it is desirable to optimize the access time of RAM A and RAM B, static RAMs are preferably used. However, other types of RAMs (such as dynamic RAM) could be used, and the present invention is not limited to a specific type of RAM. The transfer of data between internal RAM on one hand and RAM A and RAM B on the other hand can be handled by CPU 102 directly (e.g., by issuing data transfer instructions to the CPU) or via conventional direct memory access (DMA). For processors which lack powerful data transfer instructions, such transfer is most efficiently handled by DMA. For processors which have powerful data transfer operations (e.g., burst mode transfer and string transfer instructions), such transfer is most efficiently handled by the CPU itself. In one embodiment of the present invention, SCSI processing circuit 124, RAM processing circuit 132, timing adjustment circuit 130, and bus interface 106 are fabricated on a single semiconductor chip 140. One of the functions of hard disk 112 is to store data and/or program used by application programs or operating systems. In order to fully utilize the advantages of device 110 in transferring data between hard disk 112 and the application programs (or the operating systems), a software driver is preferably used to coordinate the operation between them. This software driver can respond to status signals generated by device 110 and send commands thereto. This software driver can also send messages to an application software or the operating system. The operation of computer system 100 is now described. In a first example, an application software issues instructions to the software driver to retrieve a certain amount of data from hard disk 112 and transferred to internal memory 104. A flow chart S180 in Fig. 11 is used in connection with this example. The software driver issues an initialization command to SCSI processing circuit 124 and RAM processing circuit 132 (step S182). SCSI processing circuit 124 then initializes (through SCSI controller 122) hard disk 112 so that it is ready to retrieve and transfer data. RAM processing circuit 132 sets the values of counters 136 and 138 to zero and sets switch 134 to connect timing adjustment circuit 130 to RAM A. RAM processing circuit 132 retrieves data SCSI processing circuit 124 (after processed by timing adjustment circuit 130) and transfers the same to RAM A. As a result, data is read from hard disk 112 and loaded into RAM A (step S184). During step S184, CPU 102 is not involved. Thus, it can perform other functions, including executing Windows or other software modules. RAM processing circuit 132 uses counter 136 to determine whether the amount of data in RAM A has reached a predetermined value (step S186). If this value is not reached (i.e., RAM A has room to accept additional data), data from SCSI processing circuit 124 (and hard disk 112) continues to flow to RAM A, after processed by timing adjustment circuit 130 (step S188). When RAM A is not able to accept data, RAM processing circuit 132 causes switch 134 to connect timing adjustment circuit 130 to RAM B. As a result, data is read from hard disk 112 and loaded into RAM B (step S190). At this time, RAM processing circuit 132 sends a status signal (e.g., an interrupt) to the software driver informing it that data in RAM A can be transferred to memory 104 (step S192). In step S194, the software driver then determines whether CPU 102 is busy (i.e., not ready to transfer data). If CPU 102 is busy in performing other tasks, the software driver will wait. If CPU 102 is available for processing data, the software driver sends a command to RAM processing circuit 132, which causes switch 134 to connect bus interface 106 to RAM A (step S196). At this time, data can be transfer from RAM A to internal memory 104 (step S198). Note that the above described step S190 (i.e., transfer data from hard disk 112 to RAM B) can be performed simultaneously with steps S192 to S198. Typically, the time for performing step S190 is longer than the time for performing steps S192-S198. RAM processing circuit 132 can send a status signal to the software driver when step S198 (i.e., transfer data from RAM A to internal RAM) is completed (step S199). The software driver can then perform other tasks (or causes other software modules to perform other tasks). Turning attention to RAM B, RAM processing circuit 132 uses counter 138 to determine whether the amount of data in RAM B has reached a predetermined value (step S200). If this value is not reached (i.e., RAM B has room to accept data), data continues to be loaded into RAM B from hard disk 112 (step S204). When RAM B Is not able to accept data, RAM processing circuit 132 causes switch 134 to connect timing adjustment circuit 130 to RAM A again. Flow chart S180 branches back to step S184 via a path S206, and the above described steps regarding transferring of data to RAM A will be performed. At the same time, RAM processing circuit 132 sends a status signal to the software driver informing it that data in RAM B can be transferred to memory 104 (step S210). In step S212, the software driver then determines whether CPU 102 is busy (i.e., cannot transfer data out of RAM B). If CPU 102 is busy in performing other tasks, the software driver will wait. If CPU 102 is available, the software driver sends a command to RAM processing circuit 132, which causes switch 134 to connect bus interrace 106 to RAM B (step S214). As a result, the data stored in RAM B can be transferred to internal memory 104 (step S216). As pointed out before, steps S210-S216 could occur simultaneously with the transferring of data from hard disk 112 to RAM A. Typically, the time for transferring data from hard disk 112 to RAM A is longer than the time for performing steps S210-S216. Upon completing step S216, RAM processing circuit 132 can send a status signal to the software driver (step S217). The software driver can then perform other tasks (or causes other software modules to perform other tasks). The application software (through the software driver) determines the amount of data to be transferred from hard disk 112 to memory 104. The above described cycles continue until all the required data is transferred to internal memory 104. Typically, the time to transfer data stored in RAM A and RAM B to internal memory 104 is very short when compared to the disk data transferring time. Thus, RAM A and RAM B are always available for disk data transferring because the data stored the memory should have already been transferred to internal memory 104. If both RAM A and RAM B are not available for disk data transfer, the software driver should delay disk transferring operation until one of them is available. In a second example, data is retrieved from internal memory 104 and stored to hard disk 112. A flow chart S230 in Fig. 12 is used in connection with this example. In this example, an application software issues instructions to the software driver, which causes data to be retrieved from internal memory 104 and transferred to hard disk 112. The software driver issues an initialization command to SCSI processing circuit 124 and RAM processing circuit 132 (step S232). SCSI processing circuit 124 then initializes (through SCSI controller 122) hard disk 112 so that it is ready to retrieve and transfer data. RAM processing circuit 132 sets the values of counters 136 and 138 to zero and sets switch 134 to connect bus interface 106 to RAM A. Data is transferred from internal memory 104 to RAM A (step S234). Counter 136 is used to determine whether the size of data in RAM A has reached a predetermined value (step S236). If RAM A is able to accept additional data, data will continue to be retrieved from internal memory 104 and stored in RAM A (step S238). When RAM A is not able to accept additional data, RAM processing circuit 132 causes switch 134 to connect RAM A to timing adjustment circuit 130. SCSI processing circuit 124 transfers data from RAM processing circuit to hard disk 112 under the control of timing adjustment circuit 130 (step S240). At the same time, RAM processing circuit 132 determines whether RAM B is available for storing data (step S242). When RAM B is being accessed for the first time, it should be available for storing data. However, it may not be available later because there may not be enough time to completely transfer the data stored therein to hard disk 112 (which is a relatively slow process) prior to filing up RAM A (which- is a fast semiconductor-to-semiconductor transfer). If RAM B is not available, RAM processing circuit 132 sends a status signal to the software driver regarding the unavailability (step S244). Upon receiving the status signal, the software driver notifies the application software (or the operating system) to perform other tasks (step S246). If RAM B is available, RAM processing circuit 132 sends a status signal to the software driver regarding the availability (step S250). In step S252, the software driver determines whether CPU 102 is busy (i.e., not available to transfer data). If CPU 102 is not available, the software driver will wait. If CPU 102 is available, the software driver sends a commend to RAM processing circuit 132 causing switch 134 to connect bus interface 106 to RAM B. Data is transferred from internal memory 104 to RAM B (step S254). Counter 138 is used to determine whether the size of data in RAM B has reached a predetermined value (step S256). When the value is not reached (i.e., RAM B is able to accept additional data), step S254 is repeated and data will continue to be retrieved from internal memory 104 and stored in RAM B (step S260). When RAM B is not able to accept additional data, RAM processing circuit 132 causes switch 134 to connect RAM B to timing adjustment circuit 130. SCSI processing circuit 124 transfers data to hard disk 112 under the control of timing adjustment circuit 130 (step S262). RAM processing circuit 132 also determines whether RAM A is now available to accept data (step S264). If RAM A is not available (e.g., data has not yet been transferred to hard disk 112 because of the comparable low transfer rate), RAM processing circuit 132 sends a status signal to the software driver, which temporarily suspends the transferring of data from internal memory 104 (step S266). The software driver then notify the application software (or the operating system), which can now perform other tasks because there is no need to transfer data (step S268). If and when RAM A is ready to accept data, RAM processing circuit 132 sends a status signal to the software driver (step S270). The software driver determines whether CPU 102 is busy (step S272). If it is busy (i.e., not available to transfer data), the software driver waits until CPU 102 is busy. If CPU 102 is not busy, RAM processing circuit 132 causes switch 134 to connect bus interface 106 to RAM A again. Data can now be transferred from internal memory 104 to RAM A. Flow chart S230 branches to step S234, and the whole algorithm is repeated again. The transfer of data from internal memory to RAM A can proceed simultaneously with the transfer of data from RAM B to hard disk 112. The application software (through the software driver) determines the amount of data to be transferred from memory 104 to hard disk 112. The above described cycies continue until all the required data is transferred to hard disk 112. One feature of the present invention is that the transfer of data from and to hard disk 112 is handled by data transfer device 110 instead of CPU 102. All CPU 102 needs to do is to issue high-level commands (e.g., start and terminate the transferring process) to data transfer device 110. There is no need for CPU 102 to monitor and process the details of the data transfer. As a result, CPU 102 can perform other tasks while data is transferred between hard disk 112 and RAM A or RAM B. Fig. 13 shows the relative timing between SCSI cycles and internal memory cycles of computer system 100 in Fig. 10. Timing diagram 280 shows the transfer of data between hard disk 112 and RAM A/RAM B. In Fig. 13, reference numerals 282 and 283 correspond to time intervals for transferring data between hard disk 112 and RAM A while reference numerals 286 and 287 correspond to time intervals for transferring data between hard disk 112 and RAM B. Time intervals for switching between RAM A and RAM B, designated as reference numeral 285, are much shorter than the time intervals for transferring data. This is because the switching is performed electronically using semiconductor elements in RAM processing circuit 132. Timing diagram 270 shows the transfer of data between internal memory 104 and RAM A/RAM B. In Fig. 13, reference numerals 272 and 273 correspond to time intervals for transferring data between internal memory 104 and RAM A while reference numerals 278 and 277 correspond to time intervals for transferring data between internal memory 104 and RAM B. Note that the time intervals 272, 273, 276, and 277 (for internal memory transferring) are much shorter than time intervals 282, 283, 286 and 287 (for hard disk transferring). As pointed out above, computer system 100 can perform other functions (e.g., executing operating system or application programs) during time intervals 282, 283, 286 and 287 for hard disk transferring. As a result, the throughput of computer system 100 is much higher than conventional systems. The size of RAM A and RAM B is a function of performance and cost. It is found that a memory size of 128 kilobytes for RAM A and RAM B gives adequate performance at reasonable cost. It should be appreciated that RAM A and RAM B could have different sizes, and that the full sizes of RAM A and RAM B do not have to be used. For example, the predetermined values in steps S186 and S200 of Fig. 11 and steps S236 and S256 of Fig. 12 could be less than the full size (e.g., 128 kilobytes) of RAM A and RAM B. It should be appreciated that RAM A and RAM B are not cache memory. Thus, there is no need to include circuit for detecting hits and misses and for replacing a portion of the memory in accordance with the frequency of hits. The circuit of the present invention is simple and fast. There are prior art systems which use buffers for the purpose of speeding up disk transfer. For example, many hard disks use semiconductor memory as buffers to improve throughput. Some computer systems use a portion of their system memory as buffers. However, these systems do not use the RAM A/RAM B architecture and the associated software driver. Consequently, their performance is inferior to the performance of the system of the present invention. One of the applications of the present invention is to retrieve graphic files stored in a hard disk at high speed for use by Microsoft ("MS") Windows-based software applications. In many modern computer designs, a display memory (such as video RAM. or 'VRAM") is used to store the digital image of information which will be converted to analog signals and displayed on a display device (such as a computer monitor). Under MS Windows, applications can appear as windows on a computer screen. The size of the windows could range from the full size of the monitor to a small fraction of the display area of the monitor. Thus, all or a small fraction of the display memory may be used to store the digital image. The graphic file used to illustrate the present invention is a large file containing many megabytes of graphic data. It is stored in a hard disk. On the other hand, the size of VRAM in a typical computer system is around 1 megabyte. If the display window containing the graphic image is a small window, the amount of VRAM devoted to the digital image is much less than 1 megabyte. In both cases, the graphic file in the hard disk is much larger than the size of the digital image in the VRAM. If it is desirable to scroll the image in the window, data of the graphic file stored in the hard disk needs to be downloaded to the display memory. The speed of scrolling is often limited by the speed of downloading of graphic data. Thus, it is desirable to have a system for fast transferring of data between the hard disk and the display memory. In a variation of the above embodiment, system RAM is used as intermediate storage area because the available size of system RAM (typically at least four megabytes in computer capable of running MS Windows) can be larger than the size of the VRAM. The amount of graphic data retrieved from a hard disk and loaded into the system RAM could exceed the size of the VRAM, When the portion of the graphic data needs to be displayed differs only slightly from the graphic data being displayed in the display window, the graphic data can be transferred from the system RAM to the VRAM. As a result, there is no 5 need to initiate disk data transfer in this situation. The transferring of graphic data between system RAM and VRAM is quite fast because the overhead in hardware and software for RAM to RAM transfer is quite low. Thus, this variation can increase the throughput to a certain extent. However, if the speed of scrolling is fast so that graphic data not yet loaded into the system RAM is l o frequently needed, disk data transfer cannot be avoided. In the IBM compatible personal computer, hard disk operation is provided by a ROM based device service routine (DSR). This routine is part of the "basic input/output system" (BIOS) software, which composes of the operating system, device drivers and shell. The hard disk DSR is accessed by invoking 15 an INT 13 function. The DSR communicates with and controls an industrial standard hard disk controller. It allows an application program to perform many operations to the hard disk, including read, write, initialize, test, format, etc. It also returns status information (e.g., error codes) to the application program. Many software applications, including those operating in some versions of 20 MS Windows, use INT 13 for the purposes of transferring data between a hard disk and system RAM. However, this method leads to very slow data transferring. One of the reasons is that the CPU needs to spend many cycles in executing MS Windows codes, thus cannot drive the hard disk to its maximum capability. As a result, the hard disk has to pause and wait for CPU cycles during data transfer. Another reason is that INT 13 and conventional hard disk interface require many CPU cycles to handle the transferring of data, thereby using valuable CPU resources for basic operations. As a result, the application programs will run slowly because they have to compete with the BIOS for CPU resources. In order to improve the data transfer between hard disk and the system RAM (or VRAM), the data transfer device of the present invention can be advantageously used in this system. Fig. 14 shows a schematic diagram of a computer system 340 designed to transfer graphic data using the present invention in a MS Windows environment. Computer system 340 comprises a personal computer 356 having a mother board (not shown), a monitor (not shown) and a keyboard (not shown). Computer system 340 also comprises MS Windows 342 running on top of an operating system 354 (such as Microsoft's MS-DOS working in combination with the computer's BIOS). Operating system 354 monitors and controls the resources of personal computer 356. MS Windows is a complicated software containing many program modules and layers of procedure calls, shown schematically in Fig. 14 as dashed lines 344-347. System 340 also contains a conventional hard disk 360 connected to a conventional hard disk interface 364. This interface can be a printed circuit board inserted to a peripheral bus (e.g., an ISA or PCI bus) in personal computer 356. It contains electronic components (such as a hard disk controller chip) allowing personal computer 356 to control and communicate with hard disk 360. A conventional software program 366, typically called a hard disk driver, allows an application program to control and access hard disk 360 without knowing the details of the organization and structure of hard disk 360 and the hard disk controller. As pointed out above, hard disk driver could be embedded in the BIOS of computer 356. However, it is also possible to have a separate hard disk driver software running separately from the operating system. Applications, such as an applications 380 and 381 , run on top of MS Windows 342. In this example, one of the applications, such as application 380, is used to illustrate the present invention. Application 380 communicates with hard disk driver 366 through a lengthy chain of program modules in MS Windows 342 and operating system 354. Thus, in Fig. 15, HD driver 366 is shown schematically as a component positioned below dashed lines 344-347 and a portion of operating system 354. As pointed out above, prior art hard disk drivers are not efficient in transferring data to and from hard disk. In addition, communication between application 380 and hard disk driver 366 has to go through the MS Windows modules and at least a portion of operating system 354. As a result, data transfer is very slow. The disk processing system in accordance with the present invention comprises a hard disk 370, a data transfer interface 372, and a data transfer (software) driver 374. Data transfer interface 372 corresponds to data transfer device 110 of Fig. 10. In the present invention, it is desirable to minimize the interaction between data transfer driver 374 on one hand and MS Windows 342 and operation system 354 on the other hand. It is found that this arrangement improves execution speed because less overhead is required. In Fig. 14, data transfer driver 374 is shown schematically to be positioned below only dashed line 344. Thus, application 380 can access data transfer driver 374 without going through a long chain of MS Windows modules. In the present system, data transfer driver 374 comprises two program modules entitled FGB.DLL and MDC.DRV. MDC.DRV is a driver program which controls hard disk 370 directly. FGB.DLL is a Windows dynamic link library module which provides an interface between application 380 and MDC.DRV. In this system, MDC.DRV replaces a conventional hard disk driver and associated disk-related routines embedded in operating system 354, MDC.DRV interacts with data transfer interface 372 in accordance with the flow charts in Figures 11 and 12. Fig. 15 is a flow chart S400 showing the interaction between application 380 with hard disk 370 in accordance with the present invention. In this illustrative example, it is assumed that the "predetermined values," shown in Figs. 11 and 12, have been set to the full size (i.e., 128 kilobytes) of RAM A and RAM B. It is also assumed, for illustrative purposes, that graphic data is written into VRAM directly instead of using an intermediate storage medium such as the system RAM. Application 380 determines the size of the display window under MS Windows and the location of the associated graphic data file in hard disk 370 (e.g., directory/filename). Application 380 calls FGB.DLL and sends appropriate parameters thereto (step S404). Examples of the parameters are the directory/filename, size of graphic data desired, location of the window, etc. FGB.DLL then calls MDC.DRV (step S406). As pointed out above, MDC.DRV controls data transfer interface 372 directly without using operating system calls. MDC.DRV sends commands to data transfer interface 372 to request header information from hard disk 370 (step S408). Header information is typically located at a predetermined position of hard disk 370, and contains information such as directory names, file names, size of each file, and the start address of each file. The header information is delivered to FGB.DLL via MDC.DRV (step S412). Upon receiving the header information, FGB.DLL determines the location and size of graphic data needed to be send to the VRAM. In step S416, FGB.DLL sends commands to MDC.DRV requesting the required amount of graphic data from a specified location in hard disk 370. Because RAM A and RAM B are both 128 kilobytes in size, MDC.DRV then controls data transfer interface 372 to read 128 kilobytes of data from hard disk 370 (step S418). MDC.DRV notifies FGB.DLL or MS Windows to perform other tasks during the retrieval of data from hard disk 370 because this operation could take many CPU cycles (step S420). As a result, the retrieval of data can run concurrently with other MS Windows modules of other applications. Data transfer interface 372 continues to monitor (through its counters) whether the RAM A or RAM B therein is full (step S422). If the hard disk has not yet retrieved the 128 kilobytes of data, the CPU resources can continue to be used by other software programs. When 128 kilobytes of data is retrieved, data transfer interface 372 notifies MDC.DRV (step S424). MDC.DRV determines whether more data needs to be retrieved from hard disk 370 (step S426). If more data is needed, MDC.DRV sends a command to data transfer interface 372 asking it to retrieve another 128 kilobytes of data from hard disk 370 and transfer to a different one of RAM A/RAM B (step S428). MDC.DRV delivers the previously retrieved 128 kilobytes of data (stored in RAM A or RAM B) to FGB.DLL (step S430), which in turn transfers the data to the VRAM (step S432). Flow chart S400 branches to step S420 (i.e., notifying and allowing other software to run). If there is no need to retrieve additional data from hard disk 370, MDC.DRV delivers the previously retrieved 128 kilobytes of data (stored in RAM A or RAM B) to FGB.DLL (step S436), which in turn transfers the data to the VRAM (step S438). FGB.DLL returns to application 380 (step S440). The division of labor between FGB.DLL and MDC.DRV can vary from that described in the above flow chart. In the above example, FGB.DLL informs MDC.DRV the required amount of data and let MDC.DRV makes decision to terminate the data transfer when the required amount is retrieved. In other embodiments, it may be desirable for this operation to be performed by FGB.DLL, i.e., FGB.DLL could make the decision to terminate data transfer. These and other variations should be easily made by a person skilled in programming, and will not be further described here. MDC.DRV can also handle the transfer of data from VRAM or system RAM to hard disk 370. A flow chart for this situation can easily be drawn by persons skilled in the art using the information shown in flow chart S400 of Fig. 15 and flow chart S230 of Fig. 12. Consequently, this flow chart will not be shown here. It can be seen from the above description that data transfer interface 372 (hardware) and the associated data transfer driver 374 (software) work synergistically to increase the throughput of data transfer between hard disk 370 and the VRAM (or system RAM). The hardware, standing along, is able to increase the throughput. However, the software driver allows other software applications and the operating system to fully utilize the resources of the computer. The invention has been described with reference to a specific exemplary embodiment thereof. Various modification and changes may be made thereunto without departing from the broad spirit and scope of the invention. For example, the present invention could be used in various computers, both presently available and developed in future, such as Apple's computer and different versions of Microsoft's Windows (e.g., versions 3.1, 3.11 , NT and Windows 95). The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense; the invention is limited only by the provided claims.

Claims: claims 1. A data processing apparatus comprising: an external storage device (21); first and second memories (24, 25); data processing means (11 ) for alternately accessing said first and second memories to process data; and data transfer means (26), connected to said first and second memories and said external storage device, for transferring data between that one of said first and second memories to which said data processing means is not accessing, and said external storage device in accordance with an instruction from said data processing means. 2. The data processing apparatus according to claim 1 , wherein when said data processing means instructs data reading from said external storage device, said data transfer means reads data to be processed by said data processing means from said external storage device and prestores said data into that one of said first and second memories to which said data processing means is not accessing, in accordance with the instruction from said data processing means. 3. The data processing apparatus according to claim 1, wherein when said data processing means instructs data writing into said external storage device, said data transfer means reads processed data from that one of said first and second memories to which said data processing means is not accessing, transfers said processed data to said external storage device and preforms an area into which data is writable by said data processing means, in accordance with the instruction from said data processing means. 4. The data processing apparatus according to any one of claims 1 to 3, wherein said data transfer means comprises: first transfer means (36) for exchanging data with said external storage device; second transfer means (38) for exchanging data with said first and second memories; and a buffer memory (37) for performing data transfer between said first and second transfer means. 5. The data processing apparatus according to any one of claims 1 to 3, wherein said data transfer means comprises: first transfer means (124, 148) for exchanging data with said external storage device (112); second transfer means (132) for exchanging data with said first and second memories (RAM A, RAM B); and a timing adjustment circuit (130) for adjusting differences in transfer rates between said first and second transfer means. 6. An interface circuit comprising: a port (31 ) to be connected to an external storage device; first and second memories (24, 25); a port (32) to be connected to data processing means for alternately accessing said first and second memories to process data; and data transfer means (26), connected to said first and second memories and said external storage device, for transferring data between that one of said first and second memories to which said data processing means is not accessing, and said external storage device in accordance with an instruction from said data processing means. 7. A system for transferring data in a computer system having a CPU 5 (102), an external memory device (112) and internal memory (104), comprising: a first memory device (RAM A); a second memory device (RAM B); a first counter (136) coupled to said first memory device for determining an o amount of data stored in said first memory device; a second counter (138) coupled to said second memory device for determining an amount of data stored in said second memory device; means (152) for generating a first signal when the amount of data stored in said first memory device exceeds a first predetermined value; 5 means (152) for generating a second signal when the amount of data stored in said second memory device exceeds a second predetermined value; a first circuit for communicating data with said external memory device; a second circuit for communicating data with said internal memory; and a data switching circuit (134) for alternatively coupling said first memory 0 device to one of said first and said second circuits in response to said first signal and for alternatively coupling said second memory device to one of said first and said second circuits in response to said second signal. 8. The system of claim 7 wherein said external memory device is a hard disk and wherein said first circuit further comprises a controller (122) for controlling operations of said hard disk. 9. The system of claim 8 further comprising a timing adjustment circuit (130), coupled between said first circuit and said data switching circuit, for adjusting differences in transfer rates between said hard disk and said first and said second memory devices. 10. The system of claim 7 wherein said second circuit includes means for causing said CPU to transfer data between said internal memory and said first and said second memory devices. 11. The system of claim 10 wherein said means for causing contains means for generating a control signal, said system further including a software routine responsive to said control signal for transferring data between said internal memory and said first and said second memory devices. 12. The system of claim 7 wherein said first and said second memory devices are static random access memory devices. 13. A system for transferring data between an external memory device (112) and internal memory (104) in a computer having a CPU (102) and at least one application program executing therein, comprising: a first memory device (RAM A); a second memory device (RAM B); a first circuit for communicating data with said external memory device; a status signal circuit (152) for generating status signals in response to activities in said first and said second memory devices and said first circuit; a data switching circuit (134) for alternatively coupling said first memory device to one of said first circuit and said internal memory and for alternatively coupling said second memory device to one of said first circuit and said internal memory; and a software routine responsive to a first one of said status signals for causing said CPU to execute said at least one program during a portion of time when data is transferred between said external memory device and one of said first and said second memory devices. 14. The system of claim 13 wherein said software routine responds to a second one of said status signals for causing data to be transferred between said internal memory and said first memory during a portion of time when data is transferred between said external memory device and said second memory. 15. The software of claim 14 further comprising means for determining whether said CPU is available for transferring data between said internal memory and said first memory, and for causing said transfer when said CPU is available. 16. The system of claim 13 further containing a first counter (136) coupled to said first memory device for determining an amount of data stored in said first memory device and a second counter (138) coupled to said second memory device for determining an amount of data stored in said second memory device, said status signal circuit generating status signals when the amount of data stored in said first memory device exceeds a first predetermined value and when the amount of data stored in said second memory device exceeds a second predetermined value. 17. The system of claim 13 wherein said external memory device is a hard disk and wherein said first circuit further comprises a controller (122) for controlling operations of said hard disk. 18. The system of claim 17 further comprising a timing adjustment circuit (130), coupled between said first circuit and said data switching circuit, for adjusting differences in transfer rates between said hard disk and said first and said second memory devices. 19. A method for transferring data between an external memory device and internal memory in a computer system, said system further containing at least one application program executing therein, a CPU, a first memory device and a second memory device, said method comprising the steps of: providing a first switchable data transfer path between said first memory device and said external memory device and a second switchable data transfer path between said second memory device and said external memory device; connecting, using said first data transfer path, said external memory device to said first memory device; switching to said second data transfer path, when the amount of data in said first memory device exceeds a first predetermined value, to allow data transfer between said external memory device and said second memory device; switching to said first data transfer path, when the amount of data in said second memory device exceeds a second predetermined value, to allow data transfer between said external memory device and said first memory device; and executing said application program during a portion of time when data is communicating between said external memory device and one of said first and said second memory devices. 20. The method of claim 19 further comprising the steps of: providing a third switchable data transfer path between said first memory device and said internal memory device and a fourth switchable data transfer path between said second memory device and said internal memory device; 5 allowing data transfer between said internal memory and said first memory device using said third data transfer path only after said external memory device has been connected to said second memory device via said second data transfer path; and allowing data transfer between said internal memory and said second l o memory device using said fourth data transfer path only after said external memory device has been connected to said first memory device via said first data transfer path. 21. The method of claim 19 wherein said step of allowing data transfer between said internal memory and one of said first and said second memory 15 devices occurs during a fraction of time needed for data to be transferred between said external memory device and one of said second and said first memory devices.

Inventors: NAKAJIMA ICHIRO, SHOJI WATARU, TABUCHI DAISUKE, NAKAJIMA, ICHIRO, SHOJI, WATARU, TABUCHI, DAISUKE
Applicants: SOFMAP FUTURE DESIGN CO LTD, SOFMAP FUTURE DESIGN CO., LTD.
Application year: 1996
Main classification: G06F3
IPC codes: G06F3, G06F5