Control system for processor

Abstract: A computer controlled apparatus includes a program counter for manifesting program count values and a processor for executing a prestored program in accordance with the program count values. The apparatus includes a read only memory with a prestored program that is accessible in response to generation of a span of program count values. Auxiliary memory includes a prestored program segment. A control circuit is coupled to the program counter and stores a predetermined program count value within the span of program count values in ROM. The control circuit is responsive to a match of a program count value from the program counter and the determined program count value to cause the program counter to be loaded with a branch program count value. That value enables the processor to immediately access and execute the prestored program segment from the auxiliary memory in lieu of a subspan of program count addresses in the ROM. The processor responds to the branch program count value as though it is a next program count value from a previous program count value, thereby seamlessly executing the second prestored program.

Description: The invention relates to apparatus for controlling a device operable under the control of a computer program and is particularly but not exclusively related to a microprocessor that is operated in accord with a read only memory (ROM) program and, to a system for enabling such a microprocessor to branch to an alternate program source when a portion of the ROM program is superseded. A microprocessor normally includes a program counter for controlling the sequence of executed program steps. The program counter increments through instruction addresses in the order in which they are to be executed. Each program counter output causes an instruction fetch from the program that controls the microprocessor. When a microprocessor is operated by ROM code, the program counter output increments down through the program addresses in the ROM, causing output of a sequence of ROM-contained instructions to the microprocessor for execution. Such a microprocessor is sometimes termed a "mask-programmed" processor. A mask-programmed microprocessor may also employ additional external ROM or downloadable random access memory (RAM). When a ROM is employed for processor control, techniques are required for the handling of program errors or superseded program sequences. It is known that programs in external ROM/RAM can be more easily updated than a mask-programmed ROM and can further be employed as back-up in case errors are determined in the mask-programmed ROM. As is known from: Patents Abstracts of Japan, vol. 013, no.284 (P-892), 29 June 1989 & JP 01 070831 A (NIPPON Telegr & Teleph Corp), 16 March 1989, and "Field-programmable patches simplify firmware maintenance", EDN-Electrical Design News, vol.26, no. 9, 29 April 1981, Boston US, pages 139-144; errors have been handled in the prior art by initially identifying the code within the mask-programmed ROM that is to be superseded. Then, upon reaching an initial code line of the superseded code, a signal is generated to a non-maskable interrupt input of the microprocessor, causing the microprocessor to respond with an interrupt, followed by a branch address. Such an operation requires a number of clock cycles to implement the interrupt state, fetch and execute the branch address, recover from the interrupt state, etc. Broadly stated, the invention provides apparatus for controlling a device operable under the control of a computer program comprising first and second memories for holding respectively first and second programs executable in respectively identifiable steps in dependence upon identifying means for identifying respectively, in sequence, the steps to be performed, the identifying means being responsive to control means operable to recognise a match between a step identified by the identifying means and a predetermined step of the first program, to identify a predetermined step of the second program and a processor responsive to the identifying means operable to executed the first and second programs in accordance with the steps identified by the identifying means wherein said control means is further responsive to a match between a step identified by the identifying means and a predetermined step of the second program, to identify a further predetermined step of the first program. The invention has particular application to superseding a portion of a first program held in a ROM with a second program segment, wherein the identifying means comprises a program counter for manifesting program count values, the processor means is coupled to said program counter for executing the program steps in accordance with said program count values, one of said first and second memory means comprises read only memory means coupled to said processor means and includes said first program that is addressable in accordance with a span of program count values, and the other of said memory means comprises auxiliary memory means coupled to said processor means to include a program segment that comprises said second program, wherein the control means is coupled to said program counter and said processor means and stores both a determined program count value within said span of program count values and an initial program count value that enables access to said program segment, said control means being responsive to a match of a program count value manifested by said program counter and said determined program count value to cause said program counter to output said initial program count value, said processor means responding to said initial program count value by executing said program segment and said control means also being responsive to a match of a program count value manifested by said program counter and a further determined program count value corresponding to an end code line of said program segment to cause said program counter to output a next address value in said first program at which said processor reverts to executing said first program, thereby seamlessly executing the second prestored program. The invention thus provides an efficient means for providing substitute code for superseded ROM code. The invention further provides a system for providing a substantially seamless jump to substitute code when superseded code is reached in a ROM. The Figure is a block diagram of an example of a system that implements the invention. The Figure is a block diagram of a computer apparatus which includes a central processing unit (CPU) 10 that is connected by a bus system 12 to remaining components of the apparatus. A ROM 14 is connected to bus 12 and includes an operating program 15 which is executed by CPU 10. A random access memory (RAM) 16 is connected to bus 12 and provides a volatile data storage facility for the apparatus. An input/output (I/O) module 18 provides access to an auxiliary storage module 20 which stores a segment of code that is to be substituted for a portion of code in operating program 15. Auxiliary storage module 20 may be configured as either a RAM or a ROM. The circuitry which enables CPU 10 to know when to branch to the code listing in auxiliary storage module 20 comprises an address comparator 22, a branch control register 24, a program counter load controller 26 and a program counter 28. As will be understood hereafter, plural branch control registers (e.g. 24') can be provided. For purposes of the description below, it is assumed that the operating program 15 in ROM 14 includes 200 lines of code having addresses 1-200. It is further assumed that addresses 101-125 have been superseded by substitute code that is present in auxiliary storage module 20 at addresses 301-325. Branch control register 24 is initially loaded with a program count value at which a branch action is to occur to an alternate address. In addition, branch control register may include a register position for receiving a next program count value from a last code line of a substitute code segment from auxiliary storage module 20. Without this register position, the substitute code must include, as its last entry, a "branch-to" instruction which causes a return to the original code listing. Branch control register 24 may be loaded via an external interface (not shown) that is connected to bus system 12, such as a JTAG, DMA or other comparable access circuit. Under normal circumstances, CPU 10, in combination with ROM 14, executes succeeding lines of code in operating program 15 under control of program count outputs from program counter 28 (that are applied to bus 12 via line 30). Each program count value is also fed via line 32 to address comparator 22. Previously, registers within address comparator 22 have been loaded with address values which define the count at which a branch action is to commence and the end count of the branch action. At all times other than when an address match occurs in address comparator 22, signals fed from CPU 10 via line 34 cause program counter load controller 26 to increment program counter 28 in the normal fashion. When the program count output from program counter 28 matches the pre-loaded address value in address comparator 22, a control output issues therefrom and is fed to program counter load controller 26. In response, program counter load controller 26 causes the value stored in branch control register 24 to be loaded into program counter 28. As a result, the next output program count is the value that was previously stored in branch control register 24. In response, CPU 10 is fed the branch control register value as the next instruction count. Hence, program execution continues in a seamless fashion from the address specified by the branch control register. At the termination of the branch program, program counter 28 (which has continued to be incremented) reaches the end count of the substitute program. When that value issues on line 32, address comparator 22 (which as indicated above has been loaded with the end count value) recognizes a match and causes program counter load controller 26 to load a next address value in operating program 15 into program counter 28. Accordingly, CPU 10 accesses the next address value in operating program 15 and continues to run in a seamless fashion until completion. As indicated above, this latter action may be superseded if the substitute code includes a last "branch-to" instruction. Such a branch instruction causes a return to the main program in a slightly slower fashion but saves a branch control register for another use. Turning to the exemplary address values illustrated in the Fig., CPU 10 will normally access addresses 1-200 from operating program 15 and executes them in the serial fashion. Each time an address is accessed, program counter 28 is incremented to a next value. Assume, however, that addresses 101-125 in ROM 14 have been replaced by addresses 301-325 in auxiliary storage module 20. When program counter 28 manifests a value of 101, that value is determined by address comparator 22 to match a prestored value of 101 therein. As a result, address comparator 22 issues a control signal to program counter load controller 26 which causes a program count of 301 to be written from branch control register 24 into program counter 28. CPU 10 then responds to program count 301 (which issues from program counter 28) by accessing, via I/O module 18, address 301 in auxiliary storage module 20. Program counter 28 continues to be incremented as CPU 10 steps down through addresses 301-325. When program counter 28 reaches address 325, that value is passed to address comparator 22 into which the value 325 has also been previously loaded (as the end count of the substitute program). Upon determining a match, address comparator 22 issues a signal to program counter load controller 26 which causes a program count of 126 to be loaded from branch control register 24 into program counter 28. When CPU 10 next accesses program counter 28, address value 126 is outputted onto line 30. CPU 10 thus access's address 126 in operating program 15 in ROM 14. The program then continues down the remaining addresses in operating program 15 until its termination. Additional branching operations can be implemented by utilizing additional branch control registers 24' and assuring that address comparator 22 is appropriately loaded with both the beginning and end count values of the code to be replaced. While it has been assumed that the replacement code resides in auxiliary storage module 20, the correction software can alternatively be downloaded into RAM 16 for execution. Hence, an external processor can be utilized to download the necessary code via I/O module 18. Further, while RAM 16 is shown as internal to the computer apparatus, it may be external memory which stores the replacement code for execution purposes. The correction software can also be programmed into a small internal EEPROM or a flash ROM in order to avoid having to download RAM 16 after every power-down/up. The software in the flash ROM or EEPROM can also be run at every power-up to initialize the addresses within address comparator 22 and branch control register 24. It should be understood that the foregoing description is only illustrative of the invention. Various alternatives and modifications can be devised by those skilled in the art without departing from the invention. Accordingly, the present invention is intended to embrace all such alternatives, modifications and variances which fall within the scope of the appended claims. The present invention includes any novel feature or combination of features disclosed herein either explicitly or any generalisation thereof irrespective of whether or not it relates to the claimed invention or mitigates any or all of the problems addressed.

Claims: Apparatus for controlling a device operable under the control of a computer program comprising: first and second memories (14;16;20) for holding respectively first and second programs executable in respectively identifiable steps in dependence upon identifying means (28) for identifying respectively, in sequence, the steps to be performed, the identifying means (28) being responsive to control means (22) operable to recognise a match between a step identified by the identifying means (28) and a predetermined step of the first program, to identify a predetermined step of the second program; and a processor (10) responsive to the identifying means (28) and operable to execute the first and second programs in accordance with the steps identified by the identifying means (28) characterised in that said control means (22) is further responsive to a match between a step identified by the identifying means (28) and a predetermined step of the second program, to identify a further predetermined step of the first program to be executed by the processor. Apparatus according to claim 1, wherein the identifying means comprises a program counter (28) for manifesting program count values, the processor means (10) is coupled to said program counter for executing the program steps in accordance with said program count values, one of said first and second memory means comprises read only memory means (14) coupled to said processor means (10) and includes said first program (15) that is addressable in accordance with a span of program count values and the other of said memory means comprises auxiliary memory means (16,20) coupled to said processor means (10) to include a program segment that comprises said second program, wherein the control means (22) is coupled to said program counter (28) and said processor means (10) and stores both a determined program count value within said span of program count values and an initial program count value that enables access to said program segment, said control means (22) being responsive to a match of a program count value manifested by said program counter (28) and said determined program count value to cause said program counter to output said initial program count value, said processor means (10) responding to said initial program count value by executing said program segment and said control means (22) also being responsive to a match of a program count value manifested by said program counter (28) and a further determined program count value corresponding to an end code line of said program segment to cause said program counter (28) to output a next address value in said first program (15) at which said processor (10) reverts to executing said first program (15). The apparatus as recited in claim 2 wherein said control means (22) comprises an address comparator which, upon determining a match of a program count value from said program counter (28) and respectively either said one or said further determined program count values, causes a corresponding branch program count value to be loaded into said program counter (28), said processor means (10) responding to said branch program count value by next executing a first line of code in said program segment or a next address value in said first program (15) respectively. The apparatus as recited in claim 3 wherein said control means (22) further includes a branch control register (24) for storing said branch program count value, said branch control register (24) responsive to a match output from said address comparator to load said branch program count value into said program counter (28). The apparatus as recited in claim 4 wherein said branch control register (24) further includes an end branch program count value which, together with said branch program count, define a length of lines of code that comprise said program segment. The apparatus as recited in claim 5 wherein said branch control register (24) is connected so as to be accessible from an external source to enable loading of addresses thereinto. The apparatus as recited in any preceding claim, wherein said auxiliary memory means (20) is coupled to said computer apparatus via an input/output port (18).

Inventors: HAGQVIST JARI, RANTA JUKKA, HAGQVIST, JARI, RANTA, JUKKA
Applicants: NOKIA CORP, NOKIA CORPORATION
Application year: 1996
Main classification: G06F9
IPC codes: G06F9