SYNTHESIS SHELL GENERATION AND USE IN ASIC DESIGN

Abstract: A practical approach for synthesis for million gate ASICs is based on the use of synthesis shells (101). The synthesis shell is generated by beginning with a gate level description of a fully characterized and optimized block. This gate level description is reduced by removing internal gates to produce a synthesis shell of the synthesized block. The synthesis shell preserves input load and fanout for the block, output delay relative to clock for the block, setup/hold constraints on input signals relative to the clock for the block, and delay from input to output for pass through signals for the block. Such a synthesis shell can be used as a substitute for original design netlists and can be used for hierarchical synthesis in a customer's design environment. The synthesis shell comprises a gate level description (103) which is a subset of the synthesis block. This description is reduced by deleting elements of the gate level description according to a set of pre-specified criteria.

Description: SYNTHESIS SHELL GENERATION AND USE IN ASir DESIG LIMITED COPYRIGHT WAIVER A portion of the disclosure of this patent document contains material to which the claim of copyright protection is made. The copyright owner has no objection to the facsimile reproduction by any person of the patent document or the patent disclosure, as it appears in the U.S. Patent and Trademark Office file or records, but reserves all other rights whatsoever. BACKGR T IND OF THE INVENTION Field of the Invention The present invention relates to development of integrated circuits; and more particularly to the tools used in design and development of application specific integrated circuits. Description of Related Art Automated design tools for application specific integrated circuit (ASIC) designs enable ASIC designs involving millions of usable gates in a single chip. The process of development of such complex ASICs relies on the development and verification tools executed in data processing systems which automate the design. These tools are provided by major electronic design automation or ASIC vendors, such as LSI Logic Corporation, the assignee of the present application. For instance, LSI Logic provides a product known as the C-MDE (trademark) design tools, which provide all the functions necessary to take a design to working silicon. The design tools in commercially available design automation systems include timing analysis tools, floor planning tools, layout tools, synthesis tools, packaging tools and more. The design process typically involves specification of an ASIC with a behavioral (or register transfer level) description. In a process known as synthesis, the behavioral description is then processed to create an optimized gate-level netlist for the design. With millions of gates in a single design, the netlist becomes very large. Because synthesis is a recursive process, the entire netlist must be stored in the data processing system and processed before h is created in its final form. As ASIC designs become increasingly more dense, the available computing capability is having difficulty in keeping pace. Thus, systems executing tools for ASIC design require powerful computers with large amounts of memory. As the number of usable gates explodes, speed and memory bottlenecks are created which substantially slow down the development process of complex designs. In order to address this problem, one electronic design automation vendor, known as Synopsys, provides for a "model" using which a hierarchical design can be converted into library cells with delay information for the cells in the form of timing arcs. This model is substituted for the original design and the original design can be removed from memory during the bottom up synthesis process for the design. This technique proves to be inaccurate, not only on its own environment, but also when the model is transported to a new environment. The synthesis relying on such model results in designs very different from that obtained using the actual gate level netlists of the modeled block. An unacceptable amount of accuracy is lost according to this technique while trying to reduce memory requirements. Also, as the ASIC industry matures, many vendors provide proprietary core blocks of circuits to users of the ASIC design tools. These proprietary circuits substantially reduce the design time required for ASIC development However, the vendor of such circuits must disclose details of the design of the core circuit for use in synthesis of the entire ASIC. This results in undesirable disclosure of proprietary information which might otherwise be held confidential. Accordingly, it is desirable to provide a tool which aids in improving compilation speed and reduces memory requirements during hierarchical synthesis of large ASIC designs without sacrificing accuracy. Further, it is desirable that the result of execution of such a tool is portable across design environments and synthesis tools to facilitate design re-use. Furthermore, it is desirable to provide information about a proprietary module in a format which protects the intellectual property of the owner of the module, while allowing accurate synthesis of ASICs using the module. SUMMARY OF THE INVENTION The present invention provides a practical approach for synthesis of million gate ASICs based on the use of synthesis shells. The synthesis shell is generated by beginning with a gate level description of a fully characterized block. This gate level description is reduced by removing internal gates to produce a gate level synthesis shell which is a subset of the synthesized block. The synthesis shell preserves input load and fanout for the block, output delay relative to clock for the block, output drive of die block, setup/hold constraints on input signals relative to the clock for the block, and delay from input to output for pass through signals for the block. Such a synthesis shell can be used as a substitute for original design netlists. Thus, the synthesis shell can be used for hierarchical synthesis in a customer's design environment, or as a deliverable from a provider of ASIC services in order to protect the intellectual property of such a provider. Since all the information that is needed by a synthesizer is available in the synthesis shell in netlist form, and additional information is provided to reconstruct original loading and area information, the shell is extremely accurate. The synthesis shell as mentioned above comprises a gate level description which is a subset of the synthesized block. This reduced description is obtained by deleting elements of the gate level description according to a set of criteria including the following: preserve combinatorial paths from an input port to a first storage element; preserve combinatorial paths from a last storage element to an output port; preserve direct combinatorial paths from an input port to an output port; preserve clock distribution paths; preserve feedback paths from an output port to a storage element, along with the storage element; preserve feedback paths to direct combinatorial paths in the design; preserve asynchronous RAM if a write signal to the asynchronous RAM is traced to an input port, else treat the asynchronous RAM like combinatorial logic, and treat synchronous RAMs like storage elements; preserve storage elements generating internal clocks, if any storage element clocked by an internal clock so generated is connected to an input port or an output port, either through combinatorial logic or directly; and preserve asynchronous paths like reset, clear, et cetera. Generation of the synthesis shell also includes the step of generating area difference data indicating differences between the area needed for the original block, and the area needed for preserved elements in the synthesis shell, and including the area difference data with the synthesis shell. Further, load information is stored with the synthesis shell indicating the loads within the synthesis shell relevant to the synthesis process, including the loads on each node in a path from a last storage element to an output in the block, and incremental loads on clock and asynchronous paths, where an incremental load is a load on a net compensating for removal of gates connected to the net. The straightforward implementation of a shell is represented in the form of a netlist, albeit a subset of the original netlist for the block subject of the shell. The shell maintains enough information in the subset of the netlist such that if the original netlist was replaced by this subset it would make no difference to the synthesizer and it would still continue to have access to aD the information that it could have obtained from the original netlist The size of the shell netlist is much smaller, as it is by construction a subset of the original netlist Thus memory requirements to store the shell netlist are lesser. The shell, which is portable across different process, voltage, and temperature (PVT) conditions, can be made for delivery by a vendor to designers of integrated circuits, or it can be generated by a designer during hierarchical synthesis. Thus, the present invention can be characterized as a method for synthesizing a gate level description of an integrated circuit module which includes a plurality of blocks from a behavioral or register transfer level description of the module. The method includes propagating design constraints to synthesize the first block in the plurality from the behavioral description of the block. This synthesized, gate level description is reduced to a synthesis shell as discussed above. Next, the method involves synthesizing a second block in the plurality of blocks by processing the behavioral description of the second block with reference to the synthesis shell to produce a gate level description of the at least one other block. The method of synthesizing the integrated circuit module may further include synthesizing yet another block in the plurality by processing the behavioral description of the other block with reference to the synthesis shells of the first and second blocks in a recursive fashion until the entire design is completed. Furthermore, the process may include the steps of merging synthesis shells of two blocks into a higher level synthesis shell. The merged file is then reduced into a merged synthesis shell which can replace the combination of lower level synthesis shells. The present invention can also be characterized as a machine which includes resources to execute the method described above to create synthesis shells and or stores a synthesis shell made according to the methods described above, and which also includes processing resources for executing synthesis algorithms which utilize synthesis shells. Accordingly, a practical technique is provided to reduce lhe amount of processing time, and memory required for synthesizing large ASICs having millions of gates. According to the prior art, synthesis of large designs has caused the compute capacity available to burst at the seams, creating speed and resource bottlenecks. The primary reasons for these bottlenecks is the fact that the entire design netlist has to be kept in memory according to the prior art while synthesis takes place, even blocks in which optimization has been completed. The presence of a synthesized block in memory is required because it may have an impact on the characterization of other blocks under synthesis. The synthesis shell according to the present invention is based on an extraction of the relevant information from a synthesized block such that the characterization of another block under synthesis is still accurate. The advantage gained from this shell is a dramatic decrease in the memory requirement to store the extracted block as opposed to storing the entire netlist of the synthesized block in memory. Accordingly, the advantages of the present invention include the following: 1. reduction in memory requirements; 2. reduction in run time; 3. exact substitute for original design in terms of accuracy of representation and accuracy of use in hierarchical design synthesis; 4. relies on a netlist approach to the synthesis shell which is portable across the synthesis tools and design environments; 5. preserves accuracy of information for use in systems that provide previously designed cells to designers for use in their own ASICs; 6. fits hierarchical top down characterization and bottom up optimization methodologies used in synthesis of an ASICs; 7. protects the intellectual property for proprietary cores represented by the shells. Other aspects and advantages of the present invention can be seen upon review of the figures, the detailed description, and the claims which follow. BRIEF DESCRIPTION OF THE FIGURES Fig. 1 is a simplified block diagram of a system including processing resources for generating synthesis shells, and for synthesis based on synthesis shells according to the present invention. Fig. 2 illustrates the process of ASIC design including synthesis based on the use of synthesis shells, and synthesis shell generation according to the present invention. Fig. 3 is a flow chart of a recursive synthesis process based on synthesis shell generation according to the present invention. Fig. 4 is an example block diagram used for illustration of synthesis flow according to the present invention. Fig. 5 is an example circuit diagram used for illustrating the deletion of cells based on pre-specified rules for shell generation. Fig. 6. is an example circuit diagram used for illustration of the preservation of internally generated clocks as one rule according to the present invention. Fig. 7 is an example illustrating merged shells according to one aspect of the present invention. Fig. 8 is a flow chart illustrating the process of shell generation according to the present invention. Fig. 9 is a flow chart illustrating a technique for area balancing during shell generation according to the present invention. Fig 10 is a flow chart illustrating a technique for preserving load information on particular nets in the synthesis shell. Figs. 1 1 through 16 are schematics of a representative circuit block, and shell of a circuit block as represented by the code samples in the Appendices to describe an example of the synthesis shell process according to the present invention. DETAILED DESCRIPTION The detailed description of preferred embodiments of the present invention is provided with respect to Figs. 1 through 10, in which Fig. 1 provides a perspective of a machine used in generating synthesis shells, and utilizing synthesis shells in ASIC synthesis according to the present invention. Figs 11 through 16 are used to illustrate the full netlist and synthesis shell examples in the Appendices. The machine shown in Fig. 1 includes a central processing unit 10 which is coupled to a bus 11. Also coupled to the bus 11 are input/output devices 12 and a display system 13. In the machine, a data memory 14 and an instruction memory 15 are provided and connected to the bus 11 for use by the CPU 10. The data memory according to the present invention includes a register transfer level or other behavioral description of an ASIC under development. Also, the data memory is used to store a gate level description of the ASIC after synthesis, and a synthesis shell or shells of circuit blocks within the ASIC under development This block diagram provides a heuristic view of a machine which stores and processes the synthesis shells and processes according to the present invention. It is meant to represent, for instance, the components of commercial work stations and personal computers including additional elements described herein. According to the present invention, the instruction memory 15 includes a synthesis tool, widi synthesis shell generation processes and area balancing processes for generation of synthesis shells according to the present invention. Further, the synthesis tool is capable of synthesizing blocks within the ASIC under development relying on synthesis shells for blocks already synthesized. The instruction memory thus includes development and verification tools used to implement a hardware description language such as VERILOG or VHDL. The design tools provide all the functions necessary to take a design from the hardware description level to working silicon. These functions include synthesis tools, timing analysis tools, floor planning tools, layout tools, packaging tools, and more. According to the present invention, these functions also include synthesis shell generation with area balancing as discussed in more detail below. Fig. 2 illustrates the context of synthesis shell generation and use according to the present invention. Thus, Fig. 2 illustrates the design flow for development of an ASIC which comprises generation of specifications of the ASIC (block 100), synthesis of the gate level description of the ASIC based on the specification (block 101), and layout of the resulting gate level description (block 102) for use in manufacturing of the ASIC. The present invention provides an improvement in the synthesis resources. Thus, synthesis includes providing a behavioral description of die ASIC using a hardware description language, for instance, at a register transfer level (RTL) (block 103). This behavioral description is translated and optimized (block 104). The result of the translate and optimize step is a gate level netlist for the ASIC (block 1 5). According to the present invention, synthesis shells are used during translation and optimization of synthesis. According to synthesis methodology, a behavioral code, e.g. RTL code, and design constraints for the ASIC are supplied (block 106). Based on this information, die ASIC is characterized and optimized to give a gate level description (block 107). Finally, a synthesis shell netlist is obtained for the block under synthesis (block 108). The shell is marked "do not touch", and is stored for synthesis of further blocks of the ASIC (block 109). The synthesis shell netlist is obtained using a shell generation process which involves reading die optimized block (block 110). Rules applying a set of criterion are applied to remove gates from the synthesized design for the circuit block (block 111). Finally, the shell netlist and other files necessary for the shell are written for use in synthesis of the balance of the ASIC and die original block is removed (block 1 12). The rules applied at block 1 11 include basic shell generation rules, which result in removal of gates from the interior of the circuit block which are not necessary for synthesis of die balance of d e ASIC (block 113). Special cases and hierarchy considerations are then applied to die resulting gate list level shell (block 114). Loads on nets which are necessary for further synthesis are restored in the synthesis shell (block 115). The area information for the original gate level description for die circuit block is preserved in the reduced netlist used as the synthesis shell by area balancing (block 116). Finally, die syndiesis shell results can be used for further synthesis of other blocks (block 117). Fig. 3 provides more detailed block diagram of a synthesis process according to the present invention. Thus, Fig. 3 defines a syndiesis flow used to characterize and synthesize large designs. The input/output attributes and timing constraints are supplied to characterize a module (block 200). Characterization is a top down process which provides for calculation of all I/O attributes on die pins of the module being characterized. This process is executed by propagating the I/O characteristics of die top level module and die effect of the rest of die circuitry to the inputs and outputs of d e modules being characterized. Characterization is a top down process because the characteristics of a module on die top level of hierarchy has to be determined before d e characteristics of a sub-module can be determined. Having characterized die module, the process proceeds to optimize die module (block 201 ). Optimization is a bottom up process beginning with small blocks of the design. A syndiesis shell for a module is created as soon as die module has been fully optimized and mapped to gates, that is, synthesized in d e current environment. This is also die point where the modules are marked "do not touch". If the timing and other constraints are met after delay prediction and timing analysis, as indicated at block 202, tiien the "do not touch" attribute is applied to d e module (block 203) and die syndiesis shell is created, and the module is replaced with this shell (block 204). If the timing or other constraints are not met at block 202, then d e shell is re-optimized beginning at block 201. The synthesis shell is created at block 204 by a rule based technique which reduces the gate level description of die optimized block based on a set of criteria. The module for which the shell is to be generated must meet the following constraints: 1. Must be fully synchronous. 2. Must be fully verified to meet all design constraints. 3. Must be at gate level. 4. Must be optimized to e point at which it can be marked "do not touch". If these constraints are met, then the module can be converted to a synthesis shell. The synthesis shell must preserve the following information: 1. input load and fanout; 2. output delay relative to clock; 3. set-up/hold constraints on the input signals relative to clock; 4. delay from input to output for all pass through signals. Fig.4 is a circuit diagram used for providing an example of synthesis flow based on a syndiesis shell according to die present invention. Initially die circuit shown in Fig. 4 is defined at a behavioral level. The object is to optimally synthesize the circuit The hierarchy defined in the circuit block "A" includes a top level having block "B", and shells "C" and "D". Shells "C" and "D" are shown in die figure to emphasize that a syndiesis process may rely on shells already created. Block "B" contains another level of hierardiy defined by blocks "E" and "F". The connectivity is indicated by arrows, where arrow II is an input supplied to block "A", block "B", and block "E". 12 is an input connected to block "A", block "B", block "E", and block "F". Also, 12 is supplied as an input to shell "D" and shell "C". 13 is an input to block "A", and to shell "C". Input 14 is an input to block "A" and to shell "D". The outputs Ol through 03 are connected as follows. Output Ol is an output from block "E", block "B", and "A". Output 02 is an output from shell "C" and block "A". Output 03 is produced in shell "D" and supplied as an output from block "A". Internal nets Nl and N2 are connected as follows. Net Nl is generated in block "E" and supplied to block "F". Net N2 is generated in block "F", supplied as an output from block "B", and connected as inputs to shell "C" and shell "D\ In this example, input 12 represents the clock. All other inputs and outputs are specified relative to die clock. In this case the following process of syndiesis and characterization is followed to provide an optimal circuit In die following list of steps, shells "C" and "D" are created from actual blocks "C" and "D". (Note that timing analysis can be performed as soon as a gate level netlist of a block is available.) Characterize all blocks top down (e.g. B followed by E and F). Syntiiesize E and floorplan it and re-characterize E. Re-characterize B followed by F. Synthesize F and floorplan it and re-characterize F. Re-characterize E. Timing analyze E and F. Re-synthesize and re-characterize E if needed. Same with F. (Note: This could end up being a non convergent iterative process and thus criteria to stop the process are applied.) Mark E and F "do not touch." Create "shells" for E and F and replace them with their respective shells. Re-characterize B. Synthesize B and floorplan it (this may change die floor planning of E and F). Re-characterize B and perform timing analysis. Re-syndiesize and floorplan B if necessary. Mark B "do not touch." Create "shell" for B and replace B with its shell. Re-characterize C and D. Syntiiesize C and floorplan it and re-characterize C. Re-characterize D. Synthesize D and floorplan it and re-characterize D. Timing analyze C and D. Re-synthesize and re-characterize C if needed. Same with D (Note: This could end up being a non convergent iterative process and thus criteria to stop die process are applied.) Mark C and D "do not touch." Create "shells" for C and D and replace them with their respective shells. Syntiiesize A and floorplan it (this may change he floor planning of B, C, and D). Timing analyze A (everything should work at this point). PAGE MISSING AT THE TIME OF FILING The output of register 318 is supplied through inverter 314 and inverter 321 to generate the output Outl . The output of register 320 is supplied to inverter 322 to supply the output Out2, and through buffer 323 as an input to AND gate 324. The second input to the AND gate 324 is the Out2 signal. The output of the AND gate 324 supplies the signal Out4. The input signal 302 is supplied through inverter 325 to a combinatorial cloud 326 which generates the signal OuO. Widi reference to Fig. 5, the timing rules for deleting the cells from the gate list can be discussed. In Fig. 5, elements marked widi an "X" are not preserved for die shell. 1. Any combinatorial path from an input port to the first storage element on the path in die circuit needs to be preserved. This is necessary to rr instruct ar.y input delay and calculate the setup and hold time of die storage elemer_„ Thus for instance, the cells along the arrow Kl in Fig. 5 need to be preserved, including NAND gate 305, AND gate 306, and register 310. In a similar manner, gate 304, gate 308, and register 309 need to be preserved. Note that the net from the output of register 309 to the input of gate 306 is not preserved. 2. Any combinatorial path from a last storage element to an output port needs to maintained. This is necessary to allow a reconstruction of die data arrival time for a block that is dependent on this output port, and die delay after which the data would be available at the output port. Thus, the elements near the arrow K2 in Fig. 5 need to be preserved. That is, register 320 and gate 322 should be preserved according to this rule. Also, register 318, gate 314, and gate 321 should be preserved. 3. Any direct combinatorial path from an input port to an output port of the block for which the shell is made needs to be preserved. This is essential to reconstruct die data arrival times on inputs of otiier blocks that are dependent on this output from the shell. Thus, die elements along die arrow 3 of Fig. 5 need to be preserved. Therefore, the inverter 325 and die combinatorial cloud 326 should be preserved. 4. Clock distribution networks need to be preserved. Thus, the net defined by line 303 needs to be preserved. 5. Feedback paths originating from an output port which is not buffered affect the setup times of storage elements that they are connected to based on output loading. Thus, such feedback paths should be preserved along widi d e affected storage elements. Thus, for example, the elements on the branch of die root defined by output Outl, along die path K4 of Fig. 5 need to be preserved. This results in preservation of die gate 307, along with gate 304, gate 308, and register 309. 6. Feedback paths from outputs that comprise pure combinatorial logic need to be preserved. Thus, in Fig. 5, the buffer 323 and d e AND gate 324 along widi d e branch from die output Out2 to the input of the AND gate 324 along arrow KS are preserved. 7. Asynchronous structures like reset and set need to be preserved. Thus, if any of die registers in die circuit of Fig. 5 included set or reset inputs, then die nets used to generate those signals should be preserved in die syndiesis shell. Although not shown in Fig. 5, in the case of memory elements the following special cases need to be considered. 1. If the memory cell is an asynchronous RAM, it should be treated like any other combinatorial logic, and should not be deleted unless die data feeding it comes from a storage element This special case occurs when die write signal for die RAM can be traced to an input port In such case, d e RAM should be preserved. 2. Synchronous RAMs are treated like storage elements. If all the signals that arrive and leave the RAM are latched, then die RAM can be deleted; otherwise, it should be preserved. 3. Flip-flops generating internal clocks need to be preserved if any of die storage elements that diey clock are connected to an input port or an output port, either through combinatorial logic or directly. This case is illustrated in Fig. 6, which includes a combinatorial cloud 360 which receives the input "A" on line 361. The clock signal is supplied on line 362 which clocks a register 363. The output of register 363 is supplied through a combinatorial cloud 364 which supplies the data input to a register 365. This register is clocked by die signal on line 322. The output of this register 365 is used to clock a register 366. The data input to the register 366 is supplied at the output of the combinatorial cloud 360. Thus, the element 365 needs to be preserved, because it clocks register 366 which receives its data from input "A" through combinatorial logic. According to die foregoing criteria, cells can be deleted from a gate level description of a circuit block to create a syndiesis shell. In addition, many blocks can be optimized and made into shells. In this case, interconnected shells can be merged into one. The two shells are then viewed from a top level and the preceding rules are applied to a get a super shell of the existing sub- shells as illustrated in Fig. 7. Thus, a first shell 400 and a second shell 401 as shown in Fig. 7 are combined into a merged shell 402. The first shell 400 includes die storage element 403 and die storage element 404 which supplies an output through a combinatorial logic 405. The output of the logic 405 is supplied out of die first shell 400 as an input to die second shell 401. The second shell includes die input register 406 and a register 407 which supplies an output through combinatorial logic 408. The merged shell is created which results in deleting die registers 404 and 406 and the combinatorial logic 405 for the super shell 402. In addition, a path that needs to be preserved based on the rule set laid down above, and which has some deleted gates in its transitive fanout, that is, gates which are deleted that are connected to nodes in die path but are not needed to be stored in the shell, needs to be load restored. Such load balancing is needed in cases where internal feedback gates from a buffered output are deleted, because die load on die path leading from die storage device to an output is affected. The load on each node in a path from die last storage element to an output port needs to be restored. Thus, die capacitance on die net heuristically represented by the capacitor 351 in Fig. 5 needs to be restored to satisfy this case, where gate 315 is a deleted internal feedback gate, which affects the load on Outl . The incremental loads that appear along the clock net need to be dumped out to perform load restoration on the clock net Thus, the incremental loads on die clock net 303 which compensate for removal of elements 312 and 316 needs to be preserved. Since the two primary goals of synthesis are area and timing, he area of the shell as estimated by the synthesizer needs to be die same as that of the original net list from which the shell was produced. The original area is available based on the original gate level description, and so is the area of the reduced netlist generated for the shell. Thus, by modeling a dummy cell widi no functionality and an area parameter set equal to die difference in areas between die original and reduced netlists, and instantiating the dummy cell in the reduced netlist, the area balance is provided. Three types of areas are estimated by d e synthesizer. They are combinatorial area, non-combinatorial area, and net area. The combinatorial , non-combinatorial , and net area can be restored by instantiating a dummy combinatorial cell, a dummy sequential cell, and a dummy net These dummy elements have no functionality but provide area information. The dummy cells are specific to each design technology and should therefore be modeled as library files and compiled into die user's home directory: Since wireload modules actually determine die net area and only one wireload module can be chosen for each level of hierarchy, the area balancing cells should be instantiated as a separate block in die shell netiist. Thus under the assumption that the top level design possesses one level of hierarchy where three blocks (block 1 , block2, and block3) exist, invoking a syndiesis shell generation routine with a syndiesis shell option produces die following files under die following options results in: 1. A synthesis shell netlist containing die gates remaining after rule based deletion of gates and inclusion of dummy gates for area balancing. This netlist also contains a separate level of hierarchy under top level called duxn_area, which instantiates three components dum_comb, dum_seq and dum_net The dum_comb cell is connected to die dum_seq cell by means of a single net The description of these components is available in the library file. 2. A library file in synopsys format, or any synthesis tool format. This should have one combinatorial cell called dum comb which possesses no functionality but has an area equal to die area of the deleted combinatorial cells. It should also contain a cell called dum_seq which possesses no functionality but has an area equal to die total area of the non-combinatorial cells deleted from the design. The dum net is a wireload model which possesses the same wireload area per unit fanout as the difference between the estimated net area of the original and die gate eaten netlist 3. A block loading file containing die loading information for all the components and nets of die original design. In die case of merged shells, the synthesis shell program collapses blockl and block2 into a single level of hierarchy and makes a shell. As far as the output files are concerned the program will produce two files, a collapsed netlist for block 1, and a collapsed netlist for block2. The only difference between die original shell netlist and die collapsed nedist files is that in the case of the original shell netlist files, die netlist is generated assuming a single top level. The collapsed nedist file however is the netlist generated after combining two or more levels into shells as described above widi reference to Fig. 7. Figs. 8, 9, and 10 provide the shell generation flow, area balancing, and load restoration for use in shell generation according to the present invention. The following terminology has been used in Fig. 8 for the purpose of helping understand die concepts behind shell generation: "Root". Any input port or output port of a circuit block is termed a root. For example, in Fig. 5, nodes 300, 301, and 302 are roots. Also, the outputs Outl, Out2, Out3, and Out4 are roots. "Branch". A branch is fanout arising from a root Thus, with reference to Fig. 1 , the path from point 300 to the input of gate 304 represented by line 353 is a branch as well as the path from node 300 to the input of gate 305 represented by net 354 is a branch because it is a fanout of the input port 300. "Shoot". The shoot is fanout arising from a macrocell. In Fig. 5, the input of die inverter 321 which spans out to inverter 314 and inverter 313 is a shoot "Shoot In". A shoot in is a shoot connected to d e input of die cell. For instance, the net Sinl in Fig. 5 is a shoot in to gate 313. "Shoot Out". A shoot out is a shoot connected to the output of a cell. For example, die net labeled Soutl in Fig. 5 is a shoot out to gate 314. "Leaf'. A leaf is any storage element where a timing path terminates. All flip-flops and latches in a design are leaves. Fig. 8 provides die process flow for shell generation. The algorithm begins widi die start (block 500). The first step is to locate the next root to be processed and identify whether it is an input or an output (block 501). Next, the algorithm determines whedier the root carries a clock, set or clear signal (block 502). If it is not a clock, set or clear signal at block 502, then the algorithm locates the next (or first) branch on die root (block 503). For this branch, die cell on the branch is marked to be kept (block 504). Next, it determines whether the cell is a leaf (block 505). If it is not a leaf, then a level index "i" is set to 1 (block 516) and the next shoot on die cell is located for this level (block 507). Next, the algorithm determines whether die corresponding root is an input root (block 508). If it is not an input, then it determines whedier die shoot is a shoot in (block 509). If it is a shoot in at block 509, then die cell is marked for load restoring (block 510), algoritiim loops back to block 507 to locate the next shoot. If it is not a shoot in, or die corresponding root was an input at block 508, then d e algorithm marks the cell to be kept (block 511). Next, the algorithm determines whedier die cell marked to be kept is a leaf (block 512). If it is not a leaf, then d e index "i" as incremented (block 513), else the index "i" is not changed . Next, the algorithm determines whether all shoots on this index level "i" have been processed (block 514). If not, the algorithm loops back to block 507 to process the next shoot. If all the shoots have been processed for this level, at block 514, then the algorithm determines whether the index "i" is zero (block 515). If "i" is not zero, then "i" is decremented by one (block 516) and die algorithm loops to block 514. If "i" is zero at block 515, the algorithm determines whether all d e branches for the root have been processed at block 517. If not, it loops back to block 503 to process the next branch. If all the branches on the root have been processed, then die algorithm determines whether all of the roots have been processed (block 518). If not, the algorithm branches back to point A at block 501 as shown in die figure. If all the roots have been processed, then die algorithm is finished as indicated by the end (block 519). If at block 502 it was determined that die root was a clock, set or clear signal, tiien the algorithm locates the next (or first) branch to be processed (block 520). Next, it is determined whether die cell on this branch is a leaf (block 521). If it is a leaf, the algorithm determines whedier there are other branches on the root (block 530). If all branches on die root have not been processed, the algoritiim loops back to block 520. If at block 530 it is determined that all branches for the root are done, tiien it branches to block 501 to process the roots. If the cell is not a leaf at block 521, then die algorithm branches to block 522, where an index "i" is set to zero. Then die algorithm marks the cell to be kept (block 523), and increments the index "i" by one (block 524). After incrementing die index, die algorithm locates the first or next shoot at the level "i" (block 525). Then it is determined whether die cell on die shoot is a leaf (block 526). If the cell is not a leaf, the algorithm branches to block 523 to mark the cell to be kept. If d e cell is a leaf, then die algorithm determines whether all the shoots at level "i" have been processed (block 527). If not, then die algorithm moves back to block 525 to process the next shoot If all die shoots have been processed, then die algorithm tests whether the index "i" is equal to one (block 528). If the index is not one, tiien it is decremented by one (block 529), and die algoritiim moves back to block 527 to process other shoots at the lower level. If at block 528, die index "i" is equal to one, then the algorithm branches to block 530 to determine whedier all branches have been processed. If not, die algorithm moves back to block 520 to proceed widi die next branch. If all branches have been processed at block 530, then the algorithm loops back to block 501 to continue processing. Fig. 9 illustrates die area balancing processes for the timing shell nedist. This process begins with die start block 600. The first step involves reading the technology libraries for the circuit block being synthesized (block 601). Next, the combinatorial , non-combination, and net area of the original design is determined (block 602). Next, d e combinatorial , non-combinatorial , and net area of the shell created are determined (block 603). The difference between these two files is written into die library files (block 604). Next the dummy cells for the combinatorial , non-combinatorial , and net area of the shell are created by compiling die library files (block 605). These dummy cells are inserted in die timing shell and die process ends (block 606). Figure 10 illustrates a process of load restoration for the syndiesis shell generated according to Figures 8 and 9. This algorithm begins widi die start block 600. The first step involves locating die first or next leaf in die circuit (block 601). The next step involves determining whedier this leaf had been marked for keeping in die cell generation process (block 602). If not, then die load on clock, clear and set nets for the leaf are restored (block 603). If it had been marked for keeping, men die algorithm loops back to block 601. After block 603, then die algorithm determines whedier all the leaves have been processed (block 604). If not, then d e algorithm loops back to block 601 to process the next leaf. If all die leaves had been processed at block 604, then the algorithm proceeds to block 605, where the loads on the cells marked for load restoration in die shell generation process are load restored. After this process, the algorithm ends (block 606). Attached hereto as Appendices A, B, and C, where Appendix A is a sample of behavioral code in VERILOG language for an adder, Appendix B is a synthesized netlist in NDL format for die adder represented by the code in Appendix A, and Appendix C is a syndiesis shell in NDL format which is produced according die present invention. The full syntiiesizcd nedist shown in Appendix B describes a circuit having 28 macrocells. For reference, Figs. 11, 12, and 13 provide a top level schematic of this synthesized nedist. As can be seen in Fig. 11, there are 14 registers labeled FD1 plus two adder sub-blocks labeled BIT ADD in die top level schematic. Fig. 12 shows the first adder sub- block having 5 gates, and Fig. 13 shows die second adder sub-block having 9 gates. This corresponds to the 28 gates defined by the full gate level netlist of the adder described in Appendix B. Appendix C shows the reduced netlist for a syndiesis shell according to die present invention. This reduced netlist has only 14 gates and a dummy cell represented by the schematic in Fig. 14. As can be seen, Fig. 14 has 14 gates, and 2 gate eaten blocks. The gate eaten blocks can be represented by die schematics shown in Figs. 15 and 16. As can be seen, Figs. 15 and 16 are simply die inputs and outputs of the sub-block in die circuit. Thus Appendix C, shows a resulting synthesis shell in netlist format. In Appendix C, the dummy cell is represented by line 71. As mentioned above, this dummy cell provides a reference to a cell library in which the description of the dummy cell for the reduced netlist is provided. A representative dummy module begins on line 122 of Appendix C. Line 128 points to d e fake cell fk arseqO in die area balancing library for sequential area, line 129 points to the fake cell fk_ar_com0 fo combinatorial area. The net defined in the dummy module is die area balancing "dum_net" described above. Accordingly a new tool to aid in syndiesis of large scale integrated circuits has been provided based on a synthesis shell construct used in data processing environment The synthesis shell can be delivered to customers relying on die represented circuit block for design of an ASIC, or can be generated as part of die syndiesis of a large scale integrated circuit The use of a syndiesis shell vastly reduces die processing requirements in terms of time and memory consumption for synthesis of large ASICs. The foregoing description of a preferred embodiment of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to die precise forms disclosed. Obviously, many modifications and variations will be apparent to practitioners skilled in this art It is intended that die scope of the invention be defined by the following claims and their equivalents. What is claimed is: APPENDIX A Copyright LSI Logic 1995 module bitadd (sumout, carryout, ain, bin, cin, elk); input [3:0] ain, bin; input cin, elk output [3:0] sumout; output carryout; reg [3:0] sumout, a_tmp, b_tmp; reg carryout, cin_tmp; wire [3:0] ain, bin, s_tmp; wire cin, c_tmp; always @(posedge elk) begin carryout = c_tmp; sumout — s_tπ_p; cin_tmp = cin; a_tmp = ain; b_tmp - bin; end assign {c_tmp, s_tmp} — a_tmp + b_tmp + cin_tmp; endmodule APPENDIX B Copyright LSI Logic 1995 1 compile; 2 directory master; 3 /*___**** technology used: lca300k **** ♦ */ 4 module bitadd_dw01_add_5_0; 5 inputs a_4,a_3,a_2,a_l,a_0,b_4,b_3,b_2,b_l,b_0,ci; 6 outputs sum_4,sum_3,sum_2,sum_l,sum_0,co; 7 level function; 8 define 22 ul (carry_l_=z) - an2(b_0_=a^_0_=b); 23 u2(sum_0_=z) = eo(a_0_=a,b_0_=b); 24 u3 (sum_3_=s,sum_4_=co) = fal a(caπy_3_=ci^_3_=a,b_3_=b); 25 u4(sum_2_=s,carry_3_=co) = fala(carτy_2_= B ci,a_2_=a,b_2_-b); 26 u5(sum_l_=s,carry_2_=co) = fala(carry_l_-ci,a_l_""a,b_l_-b); 27 end module; 28 module bitadd_dw01_add_5_l; 29 inputs a_4,a_3,a_2,a_l,a_0,b_4,b_3,b_2,b_l,b_0,ci; 30 outputs sum_4,sum_3,sum_2,sum_l,sum_0,co; level function; define a_4_ = (a_ .4); a_3_ - (a " 3); a_2_ = (a 2); a_l_ = (a_ .1); a_0_ = (a ); b_0_ - (b .0); sum_4_ = (sum_4) sum_3_ = (sum_3) sum_2_ β (sum_2) sum_l_ β (sum_l) sum 0 = (sum_0): u7(carry_l_=z) = an2(b_0_=a _0_=b); u8(sum_0_=z) - - eo(a_0_=a,b_0_=b); u9(sum_4_=z) - eo(caπy_4_—a I a_4_— b); ul (caπy_4_*z) i = an2(a_3_=a,carτy_3_=b); u2(sum_3_=z) = eo(caιτy_3_=a^ι_3_=b); u5 (carry _2_ « z) - an2(a_l_ β a,caπy_l_=l u6(sum_l_=z) eo(carry_ l_=a^_l_=b); end module; module bitadd; inputs ain_3_^m_2^ain_l^ain_0_,b__n_3_,bin_2_,bin_l_,bin_0_,cin,clk; outputs sumout_3_,sumout_2_^umout_l_,sumout_0_,caιτ out; level function; define sumout_3_ = (sumout_3_) sumout_2_ = (sumout_2_) sumout_l_ = (sumout_l_): sumout_0_ = (sumout_0_) carryout - (cany out); ain_3_= (ain_3_); ain_2_ = (ain_2_); n90 = (nc/0/); n91 = (nc/0 ); carry out_reg(caπyout=q) = fdl (canyout_tmp=d,clk=cp); sumout_reg_3_(sumout_3_ » q) =• fdl (sumout_tmp_3_=d,clk=cp); add_20(caπyout_tmp=^ιιm_4,sumout_tmp_3_=_amι_3^ι__mout_tmp_2_=sx__m_2, sumout_tmp_l _=sum_l ,sumout_tmp_0_=sum_0) = bitadd_dw01_add_5_l(n72_l_= sumout_reg_2_(sumout_2_=q) = fdl (sumout_tπ_p_2_-d,clk-cp); sumout_reg_l_(sumout_l_=q) = fdl (sumout_tmp_l_=d,clk =B cp); bin_tmp_reg_3_(bin_tmp_3_=q) = fdl (bin_3_=d,clk=cp); sumout_reg_0_(sumout_0_=q) -* fdl(sumout_tmp_0_«d,clk=cp); bin_tmρ_reg_2_(bin_tmρ_2_=q) = fd 1 (bin_2_=d,clk=ep); bin_tmp_reg_l_(bin_tmp_l_=q) = fdl (bin_l_=d,clk=cp); cin_tmp_reg(cin_tmp=q) = fdl(cin=d,clk=cp); bin_tmp_reg_0_(bin_tmp_0_=q) - fdl (bin_0_ > -d,clk-cp); add_20_l (n72_l_-sum_4^ι72_2_=sum_3^ι72_3_=sum_2^ι72_4_=sum_l^ι72_ 5_=sum_0 ) = bitadd_dw01_add_5_0(n90=a_4,ain_tmp_3_^_3,ain_trnp_2_=a_2, ain_tmp_q59_l _=a_l ,ain_tmp_0_=a_0^ι90 ss b_4,bin_tmp_3_=b_3,bin _B p_2_=b_2, bin mp_l_=b_l,bin_tmρ_0_-b_0,n90-ci); ain_tmp_reg_0_(ain_tmp_0_=q) - fdl (ain_0_=d,clk=cp); ain_tmp_reg ^ l_(am_tmp_q59_l_=q) = fdl(ain_l_=d,clk=cp); ain_tnψ_reg_2_(ain_tmp_2_=q) = fdl (ain_2_=d,clk=cp); ain_tmp_reg_3_(ain_tmp_3_=q) = fdl(ain_3_=d,clk= s cp); end module; end compile; end; APPENDIX C Copyright LSI Logic 1995 compile; directory master; / ****** technology used: lca300k ******/ module bitadd_dw01_add_5_l; inputs a_4,a_3,a_2,a_l,a_0,b_4,b_3,b_2,b_l,b_0,ci; outputs sum_4, sum_3, sum_2, sum_l, sum_0, co; level function; define b_3 = 0>_4) b_2 = (b_4) b_l » (b_4) ci = (b_4); sum_0 - (sum_0_ sum_l = (sum_ l_) sum_2 — (sum_2_) sum_3 - (sum_3_) sum_4 = (sum_4_ b_0 = (b_0 a_0 = (a_0 a_l SB (a_lJ a_2 - (a_2 J a_3 = (a_3 a_4 - (a_4 end module; module bitadd_dw01_add_5_0; inputs a_4^_3,a_2^_l^_0,b_4,b_3,b_2,b_l ,b_0,ci; outputs sum_4,sum_3,sum_2,sum_ l,sum_0,co; level function; define b_4 = (a_4); ci = (a_4); sum_0 - (sum_0_); sum_l • (sum_l_); sum_2 = (sum_2_); sum_3 = (sum_3_); sum_4 = (sum_4_); b_0 = (b_0J; b_l = (b_l _); b_2 = (b_2J; b_3 = (b_3J; a_0 - (a_0_); a_l = (a_l_); a_2 = (a_2J; a_3 = (a_3 J; end module; module bitadd; inputs ain_3_^in_2^ain_l^ain_0_,bin_3^bin_2^bin_l_,bin_0_,cin,clk; outputs sumout_3_,sumout_2_,sumout_l_,sumout_0_,carryout; level chip; define caτryout_reg(ca_rτyout=q, carryout_reg.qn=qn) = fdl (caπyout_tmp=d, clk=ep); sumout_reg_3_(sumout_3_ ϊ =q, sumout_reg_3_.qn=qn) =fd 1 (sumout_tmp_3_=d, clk=cp); add_20(carτyout_tmp-sum_4, sumout_tmp_3_"sum_3, sumout_tmp_2_=sum_2, sumout_tmp_l _=sum_l , sumout_tmp_0_=sum_0) ■ bitadd_dw01_add_5^1(n72_l_=a_4, n72_2_=a_3, n72_3_=a_2, n72_4_=a_l , n72_5_=a_0, nc/0/=b_4,nc/0/=b_3, nc/0/=b_2, nc/0/=b_l ,cin_tmp=b_0, nc 0/=ci); sumout_reg_2_(sumout_2_=q^umout_reg_2_.qn=qn) » fd 1 (sumout_tmp_2_=d, clk=cp); sumout_reg_l_(sumout_l_=q^umout_reg_l_.qn sa qn) = fdl(sumout_tmp_l_=d, clk=cp); bin_tmp_reg_3_(bin_tmp_3 =q, bin_tmp_reg_3_.qn=qn) = fdl(bin_3_=d, clk=cp); sumout_reg_0_(sumout_0_ ; =q^umout_reg_0_.qn a =qn) = fdl(sumout_tmp_0_=d, clk=cp); bin_tmp_reg_2_(bin_tπφ_2_=q,bin_tmp_reg_2_.qn=qn) » fd 1 (bin_2_-d, clk=cp); bin_tmp_reg_l_(bin_tmp_l_=q,bin_tmp_reg_l_.qn= jn) — fdl(bin_l_=d, clk=cp); cin_tmp_reg(cin_tmp s= q, cin_tmp_reg.qn=qn) = fd 1 (cύr^d, clk=cp) ; 71 dummy_cell = dummy; 72 bin_tmp_reg_0_(bin_tmp_0_'=q,bin_tmp_reg 0_.qn"-qn) "" fdl(bin_0_ ' -d, 73 clk=cp); 74 add_20_l(n72_l_=sum_4 ι72_2_=sum_3^ι72_3_=sum_2^ι72_4_=sum_l ,n72 75 5_=sum_0) = bitadd_dw01_add_5_0(nc/i5/=a_4, ain_tmp_3_=a_3, 76 ain_tmp_2_=a_2, ain_tmp_q59_l _=a_ 1 , ain_tmp_0_=a_0, nc/0/ ss b_4, 77 bin_tmp_3_-b_3, bin_tmp_2_=b_2, bin_tmp_l_ e b_l , 78 bin_tmp_0_=b_0, nc/0/=ci); 79 ain_tmp_reg_0_(aih_tmp_0_=q, ain_tmp_reg_0_.qn=qn) = fdl (ain_0_=d, 80 clk=cp); 81 ain_tmp_reg_l_(ain_tmp_q59_l_=q,ain_tmp_reg_l_.qn==qn) - fdl(ain_l _=d, 82 clk=cp); 83 ain_tmp_reg_2_(ain_tmp_2_==q,ain_tmp_reg_2_.qn==qn) - fdl(ain_2_=d, 84 clk=cp); 85 ain_tmp_reg_3_(ain_tmp_3_-q,ain_tπφ_reg_3_.qn β qn) *- fd 1 (ain_3_=d, 86 clk=cp); 87 ain_3_ = (ain_3 J; 88 ain_2_ - (ain_2 J; 89 ain_l_ = (ain_l J; 90 ain_0_ = (ain_0 J; 91 ain_tmp_0_ = (ain_tmp_0_); 92 ain_tmp_q59_l_ = (ain_tmp_q59_l _); 93 ain_tmp_2_ = (ain_tmp_2_); 94 ain_tmp_3_ — (ain_tmp_3_); 95 bin_tmp_0_ = (bin_tmp_0 _); 96 bin_0_ ■ (bin_0J; 97 cin » (cin); 98 bin_tmp_l_ ■ (bin_tmp_l ; 99 bin_l_ = (bin_lj; 100 bin_tmp_2_ = (bin_tπφ_2 J; 101 bin_2_ = (bin_2J; 102 sumout_0_ = (sumout_0_); 103 bin_tmp_3_ = (bin_tmp_3_); 104 bin_3_= (bin_3_); 105 sumout_l_ - (sumout_l_); 106 sumout_2_ = (sumout_2_); 107 sumout_tmp_0_ = (sumout_tmp_0_) ; 108 sumout_tmp_ 1 _ = (sumout_tmp_l _); 109 sumout_tmp_2_ = (sumout_unp_2_) ; 110 cin_tmp = (cin_tmp); 111 n72_5_ = (n72_5J; 112 n72_4_ = (n72_4 J; 113 n72_3_ = (n72_3 J;

Claims: CLAIMS 1. A method for synthesizing a gate level description of an integrated circuit module including a plurality of circuit blocks from a behavioral description of the module, comprising: synthesizing a first block in the plurality of blocks by processing die behavioral description of die first block to produce a gate level description of the first block; reducing die gate level description of die first block to a synthesis shell which preserves input load and fanout for die first block, output delay relative to clock for the first block, output drive of the first block, setup/hold constraints on input signals relative to clock for the first block, and delay from input to output for pass through signals for the first block; and syntiiesizing at least one other block in the plurality of blocks by processing the behavioral description of d e at least one otiier block with reference to the syndiesis shell to produce a gate level description of die at least one other block. 2. The metiiod of claim 1 , wherein the gate level description of the first block includes parameters specifying area needed for die first block, die step of reducing includes: generating area difference data indicating differences between die area needed for the first block, and area needed for elements in the syndiesis shell, and including die area difference data with the synthesis shell. 3. The method of claim 1 , wherein die step of reducing includes: storing information indicating loads on each node in a path from a last storage element to an output port, and incremental loads on clock and asynchronous paths. 4. The method of claim 1, wherein the syndiesis shell comprises a gate level description which is a subset of the first block, and the step of reducing includes deleting elements of die gate level description of die first block according to a set of criteria. 5. The method of claim 4, wherein die gate level description of die first block specifies area needed for the first block, the step of reducing includes: generating area difference data indicating differences between the area needed for the first block, and area needed by elements in the syndiesis shell, and associating the area difference data with the synthesis shell for use in synthesis of at least one other block in the plurality of blocks. 6. The method of claim 4, wherein die set of criteria includes: preserve combinatorial paths from an input port to a first storage element 7. The method of claim 4, wherein die set of criteria includes: preserve asynchronous RAM if a write signal to die asynchronous RAM is traced to an input port, else treat the asynchronous RAM like combinatorial logic. 8. The method of claim 4, wherein the set of criteria includes: preserve storage elements generating internal clocks, if any storage element clocked by an internal clock so generated is connected to an input port or an output port, either through combinatorial logic or directly. 9. The method of claim 4, wherein die set of criteria includes: preserve combinatorial paths from a last storage element to an output port 10. The method of claim 4, wherein the set of criteria includes: preserve direct combinatorial paths from an input port to an output port 11. The method of claim 4, wherein the set of criteria includes : preserve clock distribution paths. 12. The method of claim 4, wherein the set of criteria includes: preserve feedback paths from an output port to a storage element, widi the storage element. 13. The method of claim 4, wherein die set of criteria includes: preserve feedback paths to patiis consisting of combinatorial logic. 14. The method of claim 4, wherein the set of criteria includes: preserve asynchronous paths. 15. The method of claim 4, wherein the set of criteria includes : preserve combinatorial paths from an input port to an first storage element; preserve combinatorial paths from an last storage element to an output port; preserve direct combinatorial paths from an input port to an output port preserve clock distribution paths; preserve feedback paths from an output port to a storage element, with the storage element; preserve feedback paths to paths consisting of combinatorial logic; preserve asynchronous RAM if a write signal to the asynchronous RAM is traced to an input port, else treat the asynchronous RAM like combinatorial logic; preserve storage elements generating internal clocks, if any storage element clocked by an internal clock so generated is connected to an input port or an output port, either through combinatorial logic or directly; and preserve asynchronous patiis. 16. The method of claim 1 , wherein the step of synthesizing the at least one other block includes: reducing die gate level description of a second block to a second syndiesis shell which preserves input load and fanout for the second block, output delay relative to clock for the second block, output drive for die second block, setup/hold constraints on input signals relative to clock for the second block, and delay from input to output for pass through signals for the second block; and syntiiesizing anotiier block in die plurality of blocks by processing a behavioral description of the other block with reference to the synthesis shell of the first block and die second syndiesis shell of the second block to produce a gate level description of the at least one otiier block. 17. The method of claim 16, including: reducing die syndiesis shells of the first and second blocks to a merged syndiesis shell which preserves input load and fanout for the first and second blocks, output delay relative to clock for the merged first and second blocks, output drive for the merged first and second blocks, setup/hold constraints on input signals relative to clock for the merged first and second blocks, and delay from input to output for pass through signals for the merged first and second blocks. 18. A metiiod for producing a synthesis shell of a gate level description of a circuit block, comprising: processing the gate level description to delete elements of die gate level description of the circuit block according to a set of criteria which preserves input load and fanout for die circuit block, output delay relative to clock for the circuit block, output drive for the circuit block, setup/hold constraints on input signals relative to clock for the circuit block, and delay from input to output for pass through signals for the circuit block; and storing a gate level description of remaining elements in the circuit block as the synthesis shell. 19. The method of claim 18, wherein the gate level description of the circuit block specifies area needed for the circuit block, the step of processing includes: generating area difference data indicating differences between die area needed for the circuit block, and area needed by elements in the synthesis shell, and including the area difference data widi die syndiesis shell. 20. The method of claim 18, wherein die step of processing includes: storing information indicating loads on each node in a path from a last storage element to an output port, and incremental loads on clock and asynchronous paths. 21. The method of claim 18, wherein the set of criteria includes : preserve combinatorial paths from an input port to a first storage element in the circuit block; preserve combinatorial paths from a last storage element to an output port of the circuit block; preserve direct combinatorial paths from an input port to an output port of the circuit block; preserve clock distribution paths in the circuit block; preserve feedback paths from an output port of the circuit block to a storage element in the circuit block, with die storage element; preserve feedback paths in the circuit block to paths consisting of combinatorial logic; preserve asynchronous RAM if a write signal to die asynchronous RAM is traced to an input port, else treat the asynchronous RAM like combinatorial logic; preserve storage elements generating internal clocks, if any storage element clocked by an internal clock so generated is connected to an input port or an output port, eitiier through combinatorial logic or directly; and preserve asynchronous paths in the circuit block. 22. The method of claim 18, wherein die circuit block includes a first sub-block and a second sub-block, and die step of processing includes processing die gate level description to read elements of die gate level description of the first sub-block according to die set of criteria, processing the gate level description to delete elements of the gate level description of the second sub-block according to the set of criteria, and then processing the gate level description of a combination of the gate level descriptions of die remaining elements of the first and second sub-blocks to generate the syndiesis shell. 23. The method of claim 18, wherein die step of processing includes: recursively examining input and output ports for die circuit block, and if a signal on the port is not a clock, set or clear signal, then examine branches of the port for each branch, mark a cell on the branch to be kept and determine whether the cell is a leaf; if the cell is not a leaf, then examine shoots for the cell until a leaf is reached on each shoot, by examining the shoots and if a shoot on the cell is an output of another cell, or the port being examined is an mput, then mark the otiier cell to be kept, else mark die cell on die shoot to be load restored; if a signal on the port is a clock, set or clear signal, then examine branches of the port, then mark cells to be kept up to a leaf on each branch of the port or each shoot on kept cells; add dummy cell to the resulting gate level description to balance area for the syndiesis shell; and store data for restoring load on all clock, clear and set nets in die gate level description , and on all cells marked for load restoring. 24. A machine including memory which stores a syndiesis shell of a gate level description of a circuit block, made by a method comprising: processing the gate level description to delete elements of the gate level description of the circuit block according to a set of criteria which preserves input load and fanout for the circuit block, output delay relative to clock for the circuit block, output drive for die circuit block, setup/hold constraints on input signals relative to clock for the circuit block, and delay from input to output for pass through signals for the circuit block; and storing a gate level description of remaining elements in the circuit block as the syndiesis shell. 25. The machine of claim 24, wherein die gate level description of die circuit block specifies area needed for the circuit block, the step of processing includes: generating an area difference data indicating differences between the area needed for die circuit block, and area needed by elements in the synthesis shell, and including die area difference data widi die syndiesis shell. 26. The machine of claim 24, wherein die step of processing includes: storing information indicating loads on each node in a path from a last storage: element to an output port in the circuit block, and incremental loads on clock and asynchronous nets in die circuit block. 27. The machine of claim 24, wherein the set of criteria includes: preserve combinatorial paths from an input port to a first storage element in the circuit block; preserve combinatorial paths from a last storage element to an output port of the circuit block; preserve direct combinatorial paths from an input port to an output port of the circuit block; preserve clock distribution paths in the circuit block; preserve feedback paths from an output port of die circuit block to a storage element in die circuit block, with die storage element; preserve feedback patiis in die circuit block to paths consisting of combinatorial logic; preserve asynchronous RAM if a write signal to the asynchronous RAM is traced to an input port, else treat the asynchronous RAM like combinatorial logic; preserve storage elements generating internal clocks, if any storage element clocked by an internal clock so generated is connected to an input port or an output port, either through combinatorial logic or directly; and preserve asynchronous paths in the circuit block. 28. The machine of claim 24, including processing resources for synthesizing a gate level description of an integrated circuit module which comprises the circuit block subject of die synthesis shell and other circuits, from the syndiesis shell and a behavioral description of the other circuits in the module.

Inventors: ADKAR SANJAY, AGRAWAL SARIKA, JOLY CHRISTIAN, RAMACHANDRAN RAVICHANDRAN, SARKARI ZARIR, ADKAR, SANJAY, AGRAWAL, SARIKA, JOLY, CHRISTIAN, RAMACHANDRAN, RAVICHANDRAN, SARKARI, ZARIR
Applicants: LSI LOGIC CORP, LSI LOGIC CORPORATION
Application year: 1996
Main classification: G06F17
IPC codes: G06F17, H01L21, H01L27