A PARALLEL AND SCALABLE INSTRUCTION SCANNING UNIT

Abstract: An instruction scanning unit for a superscalar microprocessor is disclosed. The instruction scanning unit processes start and end byte information associated with a plurality of contiguous instruction bytes. The processing of start byte information and end byte information is performed independently and in parallel, and the instruction scanning unit produces a plurality of scan values which identify valid instructions within the plurality of contiguous instruction bytes. Additionally, the instruction scanning unit is scalable. Multiple instruction scanning units may be operated in parallel to process a larger plurality of contiguous instruction bytes. Furthermore, the instruction scanning unit detects certain error conditions. Error information may be used by external logic to determine the proper course of action in light of the detected error.

Description: TITLE: A PARALLEL AND SCALABLE INSTRUCTION SCANNING UNIT BACKGROUND OF THE INVENTION 1 Field of the Invention This invention relates to the field of instruction scanning mechanisms within superscalar microprocessors and, more particularly, to parallel and scalable instruction scanning mechanisms within superscalar microprocessors 2 Description of the Relevant Art Superscalar microprocessors are capable of attaining performance characteristics which surpass those of conventional scalar processors by allowing the concurrent execution of multiple instructions Due to the widespread acceptance of the x86 family of microprocessors, efforts have been undertaken by microprocessor manufacturers to develop superscalar microprocessors which execute x86 instructions Such superscalar microprocessors achieve relatively high performance characteristics while advantageously maintaining backwards compatibility with the vast amount of existing software developed for previous microprocessor generations such as the 8086, 80286, 80386 and 80486 1 he x86 instruction set is relatively complex and is characterized by a plurality of variable byte length instructions A generic format illustrative of the x86 instruction set is shown in Figure 1 As illustrated in the figure, an x86 instruction consists of from one to five optional prefix bytes 102, followed by an operation code (opcode) field 104, an optional addressing mode (Mod R/M) byte 106, an optional scale- index-base (SIB) byte 108, an optional displacement field 1 10, and an optional immediate data field 1 12 The opcode field 104 defines the basic operation for a particular instruction The default operation of a particular opcode may be modified by one or more prefix bytes For example, a prefix byte may be used to change the address or operand size for an instruction, to override the default segment used in memory addressing, or to instruct the processor to repeat a string operation a number of times The opcode field 104 follows the prefix bytes 102, if any, and may be one or two bytes in length I he addressing mode (Mod R/M) byte 106 specifies the registers used as well as memory addressing modes The scale-index-base (SIB) byte 108 is used only in 32-bit base-relative addressing using scale and index factors A base field of the SIB byte specifies which register contains the base value for the address calculation, and an index field specifies which register contains the index value A scale field specifies the power of two by which the index value will be multiplied before being added, along with any displacement, to the base value The next instruction field is the optional displacement field 1 10, which may be from one to four bytes in length The displacement field 1 10 contains a constant used in address calculations The optional immediate field 1 12, which may also be from one to four bytes in length, contains a constant used as an instruction operand The shortest x86 instructions are only one byte long, and comprise a single opcode byte The 80286 sets a maximum length for an instruction at 10 bytes, while the 80386 and 80486 both allow instruction lengths of up to 15 bytes The complexity of the x86 instruction set poses difficulties in implementing high performance x86 compatible superscalar microprocessors One difficulty arises from the fact that instructions must be scanned and aligned with respect to the parallel-coupled instruction decoders of such processors before proper decode can be effectuated In contrast to most RISC instruction formats, since the x86 instruction set consists of variable byte length instructions, the start bytes of successive instructions within a line are not necessarily equally spaced, and the number of instructions per line is not fixed As a result, employment of simple, fixed-length shifting logic cannot in itself solve the problem of instruction alignment Although scanning logic has been proposed to dynamically find the boundaries of instructions during the decode pipeline stage (or stages) of the processor, such a solution typically requires that the decode pipeline stage of the processor be implemented with a relatively large number of cascaded levels of logic gates and/or the allocation of several clock cycles to perform the scanning operation A further solution to instruction alignment and decode within x86 compatible superscalar microprocessors is described within the copending, commonly assigned patent application entitled "Superscalar Instruction Decoder", Serial No 08/146,383, filed October 29 1993 by Witt et al , the disclosure of which is incorporated herein by reference in its entirety The solution proposed within the above-referenced patent application involves a translation of each variable length x86 instruction into one or more fixed-length RISC-like instructions Upon translation, each fixed-length RISC-like instruction is aligned with respect to an allocated instruction decoder While this solution has been quite successful, it too typically requires a relatively large number of cascaded levels of logic gates This correspondingly limits the maximum overall clock frequency of the superscalar microprocessor An instruction scanning mechanism which detects instruction boundaries and identifies valid instructions prior to the decode stage is desired Furthermore, an instruction scanning mechanism which may be implemented in a relatively small number of cascaded levels of logic gates is desired to facilitate high frequency operation SUMMARY OF THE INVENTION The problems outlined above are in large part solved by an instruction scanning unit in accordance with the present invention The instruction scanning unit processes start and end byte information associated with a plurality of contiguous instruction bytes The processing of start byte information and end byte information is performed independently and in parallel, and the instruction scanning unit produces a plurality of scan values The scan values identify valid instructions within the plurality of contiguous instruction bytes Since the start and end byte information is processed in parallel the instruction scanning unit may be implemented in a relatively small number of cascaded logic levels Therefore, the instruction scanning unit may be advantageously employed in high frequency superscalar microprocessors Furthermore, performance of the superscalar microprocessor may be advantageously increased since multiple instructions are identified in a given clock cycie and therefore may be dispatched and executed concurrently Additionally, the instruction scanning unit is scalable. Multiple instruction scanning units may be advantageously operated in parallel to process a larger plurality of contiguous instruction bytes. A larger number of instructions may be identified per clock cycle, allowing for a higher performance superscalar microprocessor. Particularly, instructions which overflow from a prior instruction scanning unit are detected as well as instructions which overflow to a subsequent instruction scanning unit. The scalability functions may also be used by external logic to gather portions of instructions from one clock cycle for use in the subsequent clock cycle when a single instruction scanning unit is employed or when an overflow occurs from the last instruction scanning unit. Furthermore, the instruction scanning unit detects certain error conditions. In one embodiment, start and end byte information is examined for at least two error conditions. First, the condition of having two successive start bytes without an intervening end byte is detected. This condition indicates the beginning of a new instruction prior to the previous instruction ending. Second, the condition of having an end byte without a subsequent start byte is detected. Instructions are normally placed one after another, and therefore this condition is an error. The condition indicates an instruction ending without a subsequent instruction beginning. Error information may be used by external logic to determine the proper course of action in light of the detected error. The present invention contemplates an instruction scanning unit for scanning a block of predecode information associated with a plurality of contiguous instruction bytes. The block of predecode information includes start byte information indicative of bytes which start instructions as well as end byte information indicative of bytes which end instructions. The instruction scanning unit comprises an input bus, a first subunit, and a second subunit. Coupled to both the first and the second subunits is the input bus, which is configured to convey the block of predecode information. The first subunit is configured to receive the end byte information and to generate a plurality of instruction valid values. Each of the plurality of instruction valid values is indicative of a potential valid instruction starting at a particular byte within the plurality of contiguous instruction bytes and ending at a byte specified by the end byte information. The first subunit is configured to convey the plurality of instruction valid values on a plurality of instruction valid buses. The second subunit is configured to receive the start byte information and to generate a plurality of instruction start counts. Each of the instruction start counts is indicative of a number of instructions which start between a first one of the plurality of contiguous instruction bytes and a particular one of the plurality of contiguous instruction bytes. The second subunit is configured to convey the plurality of instruction start counts on a plurality of instruction start count buses, and the first second subunits operate in parallel. BRIEF DESCRIPTION OF THE DRAWINGS Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which: Figure 1 is a block diagram of a generic x86 instruction format Figure 2 is a block diagram of a superscalar microprocessor including an instruction cache Figure 3 is a block diagram of an instruction scanning unit included within the instruction cache of Figure 2 Figure 4A is a logic diagram of portions of an IVAL generation subunit shown in Figure 3 Figure 4B is a logic diagram of portions of a PCSTART generation subunit shown in Figure 3 Figure 4C is a logic diagram of portions of an NSTART generation subunit shown in Figure 3 Figure 4D is a logic diagram of portions of a Scan Bus generation subunit shown in Figure 3 Figure 4E is a logic diagram of portions of a Special Checking subunit shown in Figure 3 While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail It should be understood, however, that the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed, but on the contrary the intention is to cover all modifications, equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims DETAILED DESCRIPTION OF THE INVENTION Referring next to Figure 2, a block diagram of a superscalar microprocessor 200 including an instruction cache 204 in accordance with the present invention is shown As illustrated in the embodiment of Figure 2, superscalar microprocessor 200 includes a prefetch predecode unit 202 and a branch prediction unit 220 coupled to an instruction cache 204 Instruction alignment unit 206 is coupled between instruction cache 204 and a plurality of decode units 208A-208D (referred to collectively as decode units 208) Each decode unit 208A-208D is coupled to respective reservation station units 210A-210D (referred to collectively as reservation stations 210), and each reservation station 210A-210D is coupled to a respective functional unit 2I2A-212D (referred to collectively as functional units 212) Decode units 208, reservation stations 210, and functional units 212 are further coupled to a reorder buffer 216, a register file 218 and a load/store unit 222 A data cache 224 is finally shown coupled to load/store unit 222 and an MROM unit 209 is shown coupled to instruction alignment unit 206 Generally speaking, instruction cache 204 is a high speed cache memory provided to temporarily store instructions prior to their dispatch to decode units 208 In one embodiment, instruction cache 204 is configured to cache up to 32 kilobytes of instruction code organized in lines of 16 bytes each (where each byte consists of 8 bits). During operation, instruction code is provided to instruction cache 204 by prefetching code from a main memory (not shown) through prefetch/predecode unit 202. It is noted that instruction cache 204 could be implemented in a set-associative, a fully-associative, or a direct-mapped configuration. Prefetch/predecode unit 202 is provided to prefetch instruction code from the main memory for storage within instruction cache 204. In one embodiment, prefetch/predecode unit 202 is configured to burst 64-bit wide code from the main memory into instruction cache 204. It is understood that a variety of specific code prefetching techniques and algorithms may be employed by prefetch/predecode unit 202. As prefetch/predecode unit 202 fetches instructions from the main memory, it generates three predecode bits associated with each byte of instruction code: a start bit. an end bit, and a "functional" bit. The predecode bits form tags indicative of the boundaries of each instruction. The predecode tags may also convey additional information such as whether a given instruction can be decoded directly by decode units 208 or whether the instruction must be executed by invoking a microcode procedure controlled by MROM unit 209, as will be described in greater detail below. A set of start bits conveyed with a group of contiguous instruction bytes forms start byte information for that group of contiguous instruction bytes. Similarly, a set of end bits conveyed with a group of contiguous instruction bytes forms end byte information for that group of contiguous instruction bytes. Table 1 indicates one encoding of the predecode tags. As indicated within the table, if a given byte is the first byte of an instruction, the start bit for that byte is set. If the byte is the last byte of an instruction, the end bit for that byte is set. If a particular instruction cannot be directly decoded by the decode units 208, the functional bit associated with the first byte of the instruction is set. On the other hand, if the instruction can be directly decoded by the decode units 208, the functional bit associated with the first byte of the instruction is cleared. The functional bit for the second byte of a particular instruction is cleared if the opcode is the first byte, and is set if the opcode is the second byte. It is noted that in situations where the opcode is the second byte, the first byte is a prefix byte. The functional bit values for instruction byte numbers 3-8 indicate whether the byte is a MODRM or an SIB byte, or whether the byte contains displacement or immediate data. Table 1 Encoding of Start. End and Functional Bits Instr Start End Byte Bit Bit Number Value Value 1 1 X 1 1 X 2 0 X 0 3-8 0 X 3-8 0 X 1-8 X 1-8 As stated previously, in one embodiment certain instructions within the λ86 instruction set may be directly decoded by decode unit 208 These instructions are referred to as "fast path" instructions The remaining instructions of the x86 instruction set are referred to as "MROM instructions" MROM instructions are executed by invoking MROM unit 209 More specifically, when an MROM instruction is encountered, MROM unit 209 parses and serializes the instruction into a subset of defined fast path instructions to effectuate a desired operation A listing of exemplary x86 instructions categorized as fast path instructions as well as a description of the manner of handling both fast path and MROM instructions will be provided further below Instruction alignment unit 206 is provided to channel variable byte length instructions from instruction cache 204 to fixed issue positions formed by decode units 208A-208D Instruction alignment unit 206 independently and in parallel selects instructions from three groups of instruction bytes provided by instruction cache 204 and arranges these bytes into three groups of preliminary issue positions Each group of issue positions is associated with one of the three groups of instruction bytes 1 he preliminary issue positions are then merged together to form the final issue positions, each of which is coupled to one of decode units 208 Before proceeding with a detailed description of the scanning of instructions within instruction cache 204, general aspects regarding other subsystems employed within the exemplary superscalar mic r oprocessor 200 of Figure 2 will be described For the embodiment of Figure 2, each of the decode units 208 includes decoding circuitry for decoding the predetermined fast path instructions referred to above In addition, each decode unit 208A-208D routes displacement and immediate data to a corresponding reservation station unit 210A-210D Output signals from the decode units 208 include bit-encoded execution instructions for the functional units 212 as well as operand address information, immediate data and/or displacement data The superscalar microprocessor of Figure 2 supports out of order execution, and thus employs reorder buffer 216 to keep track of the original program sequence for register read and write operations, to implement register renaming, to allow for speculative instruction execution and branch misprediction recovery, and to facilitate precise exceptions As will be appreciated by those of skill in the art, a temporary storage location within reorder buffer 216 is reserved upon decode of an instruction that involves the update of a register to thereby store speculative register states Reorder buffer 216 may be implemented in a fϊrst-in- first-out configuration wherein speculative results move to the "bottom" of the buffer as they are validated and written to the register file, thus making room for new entries at the "top" of the buffer Other specific configurations of reorder buffer 216 are also possible, as will be described further below If a branch prediction is incorrect the results of speculatively-executed instructions along the mispredicted path can be invalidated in the buffer before they are written to register file 218 The bit-encoded execution instructions and immediate data provided at the outputs of decode units 208 A-208D are routed directly to respective reservation station units 21 OA-210D In one embodiment, each reservation station unit 210A-210D is capable of holding instruction information (I e , bit encoded execution bits as well as operand values, operand tags and/or immediate data) for up to three pending instructions awaiting issue to the corresponding functional unit It is noted that for the embodiment of Figure 2, each decode unit 208A-208D is associated with a dedicated reservation station unit 21 OA-210D, and that each reservation station unit 210A-210D is similarly associated with a dedicated functional unit 2 I2A-212D Accordingly, four dedicated "issue positions" are formed by decode units 208, reservation station units 210 and functional units 212 Instructions aligned and dispatched to issue position 0 through decode unit 208 A are passed to reservation station unit 210A and subsequently to functional unit 2 I2A for execution Similarly, instructions aligned and dispatched to decode unit 208B are passed to reservation station unit 210B and into functional unit 212B, and so on Upon decode of a particular instruction, if a required operand is a register location, register address information is routed to reorder buffer 216 and register file 218 simultaneously Those of skill in the art will appreciate that the x86 register file includes eight 32 bit real registers (i e , typically referred to as EAX, EBX, ECX, EDX, EBP, ESI, EDI and ESP) Reorder buffer 216 contains temporary storage locations for results which change the contents of these registers to thereby allow out of order execution A temporary storage location of reorder buffer 216 is reserved for each instruction which, upon decode, is determined to modify the contents of one of the real registers Therefore, at various points during execution of a particular program, reorder buffer 216 may have one or more locations which contain the speculatively executed contents of a given register If following decode of a given instruction it is determined that reorder buffer 216 has a previous location or locations assigned to a register used as an operand in the given instruction, the reorder buffer 216 forwards to the corresponding reservation station either: 1) the value in the most recently assigned location, or 2) a tag for the most recently assigned location if the value has not yet been produced by the functional unit that will eventually execute the previous instruction. If the reorder buffer has a location reserved for a given register, the operand value (or tag) is provided from reorder buffer 216 rather than from register file 218. If there is no location reserved for a required register in reorder buffer 216, the value is taken directly from register file 218. If the operand corresponds to a memory location, the operand value is provided to the reservation station unit through load/store unit 222. Details regarding suitable reorder buffer implementations may be found within the publication "Superscalar Microprocessor Design" by Mike Johnson, Prentice-Hall, Englewood Cliffs, New Jersey, 1991 , and within the co-pending, commonly assigned patent application entitled "High Performance Superscalar Microprocessor", Serial No. 08/146,382, filed October 29, 1993 by Witt, et al. These documents are incorporated herein by reference in their entirety. Reservation station units 21 OA-210D are provided to temporarily store instruction information to be speculatively executed by the corresponding functional units 212A-212D. As stated previously, each reservation station unit 21 OA-210D may store instruction information for up to three pending instructions. Each of the four reservation stations 21 OA-210D contain locations to store bit-encoded execution instructions to be speculatively executed by the corresponding functional unit and the values of operands. If a particular operand is not available, a tag for that operand is provided from reorder buffer 216 and is stored within the corresponding reservation station until the result has been generated (i.e., by completion of the execution of a previous instruction). It is noted that when an instruction is executed by one of the functional units 212A- 212D. the result of that instruction is passed directly to any reservation station units 210A-210D that are waiting for that result at the same time the result is passed to update reorder buffer 216 (this technique is commonly referred to as "result forwarding"). Instructions are issued to functional units for execution after the values of any required operand(s) are made available. That is, if an operand associated with a pending instruction within one of the reservation station units 210A-210D has been tagged with a location of a previous result value within reorder buffer 216 which corresponds to an instruction which modifies the required operand, the instruction is not issued to the corresponding functional unit 212 until the operand result for the previous instruction has been obtained. Accordingly, the order in which instructions are executed may not be the same as the order of the original program instruction sequence. Reorder buffer 216 ensures that data coherency is maintained in situations where read-after-write dependencies occur. In one embodiment, each of the functional units 212 is configured to perform integer arithmetic operations of addition and subtraction, as well as shifts, rotates, logical operations, and branch operations. It is noted that a floating point unit (not shown) may also be employed to accommodate floating point operations. Each of the functional units 212 also provides information regarding the execution of conditional branch instructions to the branch prediction unit 220. If a branch prediction was incorrect, branch prediction unit 220 flushes instructions subsequent to the mispredicted branch that have entered the instruction processing pipeline, and causes prefetch/predecode unit 202 to fetch the required instructions from instruction cache 204 or main memory. It is noted that in such situations, results of instructions in the original program sequence which occur after the mispredicted branch instruction are discarded, including those which were speculatively executed and temporarily stored in load/store unit 222 and reorder buffer 216. Exemplary configurations of suitable branch prediction mechanisms are well known. Results produced by functional units 212 are sent to the reorder buffer 216 if a register value is being updated, and to the load/store unit 222 if the contents of a memory location is changed. If the result is to be stored in a register, the reorder buffer 216 stores the result in the location reserved for the value of the register when the instruction was decoded. As stated previously, results are also broadcast to reservation station units 210A-210D where pending instructions may be waiting for the results of previous instruction executions to obtain the required operand values. Generally speaking, load/store unit 222 provides an interface between functional units 212A-212D and data cache 224. In one embodiment, load/store unit 222 is configured with a load/store buffer with eight storage locations for data and address information for pending loads or stores. Decode units 208 arbitrate for access to the load/store unit 222. When the buffer is full, a decode unit must wait until the load/store unit 222 has room for the pending load or store request information. The load/store unit 222 also performs dependency checking for load instructions against pending store instructions to ensure that data coherency is maintained. Data cache 224 is a high speed cache memory provided to temporarily store data being transferred between load/store unit 222 and the main memory subsystem. In one embodiment, data cache 224 has a capacity of storing up to eight kilobytes of data. It is understood that data cache 224 may be implemented in a variety of specific memory configurations, including a set associative configuration. Turning now to Figure 3, an embodiment of an instruction scanning unit 300 (which is a part of instruction cache 204) is shown. Instruction scanning unit 300 receives a start bit bus 302 and an end bit bus 304 from instruction cache 204, and produces a SCANO previous line bus 306, a scan overflow bus 308, an error detection bus 310, and a scan bus 312. SCANO previous line bus 306, scan overflow bus 308, error detection bus 310, and scan bus 312 are coupled to instruction alignment unit 206. Instruction scanning unit 300 is configured with several subunits which perform various tasks. An IVAL generation subunit 314 is coupled to end bit bus 304 and to an IVAL bus 324. A PCSTART generation subunit 316 is included, coupled to start bit bus 302 and a PCSTART bus 318. Also coupled to PCSTART bus 318 and to an NSTART bus 320 is an NSTART generation subunit 322. NSTART bus 320 is further coupled to a scan bus generation subunit 326 and to a special checking subunit 328. Further coupled to scan bus generation subunit 326 is start bit bus 302 and IVAL bus 324. Coupled to special checking subunit 328 are start bit bus 302, end bit bus 304. SCANO previous line bus 306, scan overflow bus 308, error detection bus 310, and IVAL bus 324. Generally speaking, instruction scanning unit 300 is configured to scan start byte information and end byte information associated with a plurality of contiguous instruction bytes The start byte information is conveyed on start bit bus 302 and the end byte information is conveyed on end bit bus 304 Start bit bus 302 and end bit bus 304 together form an input bus to instruction scanning unit 300 Instruction scanning unit 300 produces a set of scan values on scan bus 312 which are indicative of the boundaries of instructions within the plurality of contiguous instruction bytes In one embodiment, start and end byte information is conveyed for eight contiguous instruction bytes Instruction scanning unit 300 scans the start byte information independently and in parallel with the end byte information in PCSTART generation subunit 316, NSTART generation subunit 322, and IVAL generation subunit 314 The information so generated is combined in scan bus generation subunit 326, producing a set of masks on scan bus 312 A mask is a field of bits, each bit being associated with one instruction byte within the plurality of contiguous instruction bytes being scanned If a particular bit of a mask is set, the associated byte is a portion of the instruction identified by that mask If a particular bit of a mask is clear, the associated byte is not a portion of the instruction identified by that mask Each mask identifies instruction bytes which form a valid instruction In one embodiment, scan bus 312 conveys four eight-bit masks identifying the first four valid instructions found within the eight bytes associated with the start and end byte information conveyed to instruction scanning unit 300 The masks produced on scan bus 312 are conveyed to instruction alignment unit 206, along with information on SCANO previous line bus 306, scan overflow bus 308 error detection bus 310, for use in locating valid instruction bytes from a plurality of instructions associated with the start and end byte information processed by instruction scanning unit 300 Special checking subunit 328 is included to generate error information associated with start and end byte information as well as to provide scalability functionality Scalability functionality is functionality that allows multiple instruction scanning units similar to instruction scanning unit 300 to operate simultaneously on a larger plurality of contiguous instruction bytes In one embodiment, the scalability functionality of special checking subunit 328 includes detecting that an instruction ends in the eight bytes being scanned but does not begin in that eight bytes, and detecting that an instruction begins in the eight bytes being scanned by does not end in that eight bytes. As mentioned above, IVAL generation subunit 314 receives end byte information associated with a plurality of contiguous instruction bytes IVAL generation subunit 314 generates an instruction valid value associated with each byte m the plurality of contiguous instruction bytes Instruction valid values are values which identify bytes which may form a valid instruction In one embodiment, the instruction valid values generated by IVAL generation subunit 314 are masks as described above Each instruction valid value generated by IVAL generation subunit 314 identifies a potentially valid instruction beginning at the associated byte within the contiguous instruction bytes being scanned The potentially valid instruction ends at the byte associated with the first end bit encountered in the associated end byte information subsequent to the byte position of the associated byte Furthermore, the end bit corresponding to the associated byte is included in determining the end of the potentially valid instruction Since the start byte information is not available to IVAL generation subunit 314, an instruction valid value is generated for each byte being scanned as if that byte were a start byte Therefore, the instruction valid values identify potentially valid instructions The correct instruction valid values may then be selected from this set of instruction valid values according to the start byte information, as will be described below PCSTART generation subunit 316 and NSTART generation subunit 322 are a pair of subunits which generate an instruction start count for each byte being scanned The instruction start count for a particular byte indicates the number of instructions which start within the eight bytes being scanned but prior to the particular byte This information, along with the start byte information, may be used to determine which of the instruction valid values generated from IVAL generation subunit 314 are the correct instruction valid values In one embodiment, PCSTART generation subunit 316 generates intermediate instruction start counts according to a set of scan regions within the plurality of contiguous instruction bytes being scanned In one embodiment, four scan regions are used The first scan region comprises the first byte of the contiguous instruction bytes being scanned The second scan region includes the second through fourth bytes, while the third scan region includes the fifth through seventh bytes Finally, the fourth scan region comprises the eighth byte being scanned For a particular byte within the contiguous bytes being scanned, the associated intermediate instruction start count indicates the number of instructions which start prior to that particular byte but within the scan region that includes the particular byte Additionally, an instruction which starts in the last byte of the scan region prior to the scan region that includes the particular byte is included in the associated intermediate instruction start count By generating these intermediate instruction start counts, the logic gates embodying the function may be advantageously limited to a relatively small number of inputs while still utilizing a parallel scanning technique as will be explained in more detail below In one embodiment, the intermediate instruction start counts are decoded counts such that a bit set in one position of the count indicates zero prior start bytes, a bit set in another position of the count indicates one prior start byte, etc These intermediate instruction start counts are conveyed on PCSTART bus 318 to NSTART generation subunit 322 NSTART generation subunit 322 accepts the intermediate instruction start counts generated by PCSTART generation subunit 316 and generates the instruction start counts mentioned above A particular instruction start count is generated by shifting the instruction start count of the last byte of the previous scan region by the intermediate instruction start count associated with a particular byte of the current scan region Since the intermediate instruction start count values and the instruction start count values are decoded, the shifting adds the intermediate instruction start count of each byte to the instruction start count of the last byte of the previous scan region In this manner, the correct instruction start count for each byte may be generated In one embodiment, the instruction start counts and intermediate instruction start counts convey a value between zero and three Furthermore, a value may be conveyed indicative of four or more instruction starts NSTART generation subunit 322 conveys the instruction start counts to scan bus generation subunit 326 on NSTART bus 320 Scan bus generation subunit 326 selects a plurality of scan bus values from the instruction valid values conveyed on IVAL bus 324. The plurality of scan bus values are conveyed on scan bus 312. In one embodiment, up to four scan bus values are selected corresponding to the first four valid instructions contained within the plurality of contiguous instruction bytes being scanned. A particular instruction valid value is selected by scan bus generation subunit 326 if the start byte information indicates that the associated byte is a start byte and the instruction start count associated with that byte is between zero and three. The first scan value conveys the instruction valid value associated with an instruction start count of zero. Therefore, the first scan value identifies a valid instruction associated with the first start byte within the plurality of contiguous instruction bytes being scanned (i.e. the first valid instruction within the plurality of contiguous instruction bytes). The second, third, and fourth scan values similarly identify the second, third, and fourth valid instructions within the plurality of contiguous instruction bytes being scanned, if that many valid instructions may be located. As will be appreciated by one skilled in the art, at most four instruction valid values will be selected in this manner. Additionally conveyed on scan bus 312 is an overflow instruction valid value which is connected to the instruction valid value associated with the first byte of the plurality of contiguous instruction bytes. This overflow value is indicative of the bytes which form a portion of an instruction which ends within the plurality of contiguous bytes currently being scanned but does not begin within the plurality of bytes currently being scanned. Instruction scanning unit 300 is a parallel instruction scanning unit which (as will be shown below) may be implemented in relatively few cascaded levels of logic. Advantageously, such an instruction scanning unit identifies multiple valid instructions per clock cycle and may allow a short clock cycle design. In parallel with the above subunits, special checking subunit 328 provides the aforementioned error checking and scalability functionality. In one embodiment, special checking subunit checks for two types of errors. First, between each two bytes indicated as start bytes, one end byte should exist. Special checking subunit 328 detects two successive start bytes without an intervening end byte. Furthermore, each byte which is indicated as the end of an instruction should be immediately followed by a start byte. Special checking subunit 328 also ensures that this relationship is true for each end byte within the plurality of contiguous instruction bytes being scanned. Exemplary logic circuits for providing these checks will be described below with respect to Figure 4E. Additionally, special checking subunit 328 provides scalability functionality. If several instruction scanning units 300 were to be used in parallel to process a larger number of contiguous instruction bytes, then instructions may have some bytes scanned by one instruction scanning unit and other bytes scanned by another instruction scanning unit. This may happen if an instruction begins in the plurality of contiguous bytes scanned by one instruction scanning unit and ends in the plurality of contiguous bytes scanned by another instruction scanning unit. The instruction scanning unit detects instructions which begin in the plurality of contiguous instruction bytes being scanned but which do not end within the plurality of contiguous instruction bytes being scanned. If such a condition is detected, a signal associated with the scan bus value for which the condition is detected is asserted on scan overflow bus 308 Therefore, scan overflow bus 308 includes a signal associated with each scan value conveyed on scan bus 312 Furthermore, instruction scanning unit 300 detects instructions which end in the plurality of contiguous instruction bytes currently being scanned but do not begin in these bytes This detection is provided by detecting whether or not the first byte of the plurality of contiguous bytes is the start of an instruction If it is the start of an instruction, then no instruction that ends in the current line begins in the previous line If it is not the start of an instruction and no error condition is detected, then the bytes up to the first end byte are the end of an instruction which begins in a previous plurality of contiguous bytes The instruction valid value indicative of these bytes is conveyed on the overflow portion of scan bus 312 1 he overflow detection is conveyed on SCANO previous line bus 306 As will be appreciated by those of skill in the art, special checking subunit 328 allows a number of instruction scanning units to be used in parallel Each instruction scanning unit indicates when an instruction overflows to the next instruction scanning unit and provides an instruction valid value indicative of the bytes within its plurality of contiguous bytes that form a portion of the overflowing instruction The subsequent instruction scanning unit indicates that an instruction has overflow ed from the previous unit and provides an instruction valid value on the overflow portion of scan bus 312 (as noted above) which is indicative of the bytes which form the remainder of the overflowing instruction This information could be advantageously used to form the identified instruction Additionally, these values may be used by circuits outside of instruction scanning unit 300 to capture the first portion of an overflowing instruction The remainder of the overflowing instruction would be indicated by the instruction scanning unit in the following cycle, and the external logic could then form the overflowing instruction from the two sets of bytes The operation of instruction scanning unit 300 may be further illuminated through the use of an example The example will be presented for the embodiment of instruction scanning unit 300 that scans eight contiguous instruction bytes and provides up to four scan bus values per clock cycle Therefore, this embodiment generates eight instruction valid values on IVAL bus 324 (one for each of the eight instruction bytes) These buses will be labeled IVAL0, IVALl , IVAL2, IVAL3, 1VAL4, IVAL5, IVAL6, IVAL7, and IVAL8 Also, the four scan regions described above will be processed by PCSTART generation subunit 316 The values of the intermediate instruction start counts will be conveyed on PCSTART0, PCSTART1 , PCSTART2, PCSTART3, PCSTART4, PCSTART5, PCSTART6, and PCSTART7 Each value includes four bits which indicate the number of start bytes prior to the current byte If bit 0 is set, there are zero start bytes prior to the current byte If bit 1 is set, there is one start byte prior to the current byte If bit 2 is set, there are two start bytes prior to the current byte If bit 3 is set there are three start bytes prior to the current byte If no bits are set, there are four or more start bytes prior to the current byte The instruction start counts generated by NSTART generation subunit 322 are conveyed on NSTART0, NSTART 1, NSTART2, NSTART3, NSTART4, NSTART5, NSTART6, and NSTART7 Finally, the scan bus values are conveyed on SCANO, SCAN 1 , SCAN2, and SCAN3 In each of the above assigned names, the number indicates the associated byte Therefore, IVAL0, PCSTART0, and NSTART0 are associated with the first of the eight contiguous instruction bytes (l e byte 0) Similarly, IVALl , PCSTART 1 , and NSTART 1 are associated with the second of the eight contiguous instruction bytes (i e byte 1 ), etc SCANO is the scan value indicating the first valid instruction within the eight contiguous instruction bytes Similarly, SCAN 1 is the scan value indicating the second valid instruction within the eight contiguous instruction bytes, etc For this example, the start byte and end byte information indicates the following values Byte position 01234567 Start byte information 10001 1 10 End byte information 0001 1 101 In this embodiment, the start byte information and end byte information comprises a bit for each byte If the bit is set, the corresponding byte is a start (or end) byte If the bit is clear, the corresponding byte is not a start (or an end) byte Therefore, for this example the first valid instruction begins at byte 0 and ends at byte 3 The second valid instruction begins and ends at byte 4 (therefore, the second valid instruction is a single byte) Similarly, the third valid instruction begins and ends at byte 5 Finally, the fourth valid instruction begins at byte 6 and ends at byte 7 The correct scan bus values for this example would be Byte position 01234567 SCANO 1 1 1 10000 SCAN 1 00001000 SCAN2 00000100 SCAN3 0000001 1 When the aforementioned start and end byte values are conveyed to instruction scanning unit 300, IVAL generation subunit 314 generates eight instruction valid values as described above IVAL0 generates binary ones beginning in byte 0 and ending at the occurrence of the next end bit, which is at byte 3 IVALl generates binary ones beginning at byte 1 and ending at the occurrence of the next end bit, again at byte 3 IVAL4 generates binary ones beginning at byte 4 and ending at the occurrence of the next end bit (now at byte 4) A list of the generated instruction valid values is shown below PCSTART generation subunit 3 16 generates intermediate start counts according to the scan regions defined above Therefore, PCSTART0 contains a zero start count since no bytes precede PCSTART0 PCSTART3, however, contains a count of one since PCSTART0 is a start byte, it is the last byte of the previous scan region, and no other start bits occur in the current scan region PCSTART5 contains a count of one as well, since byte position three (the last byte position of the second scan region) is not a start bit and one start bit exists in third scan region prior to byte five (1 e byte 4) The values for the intermediate instruction start counts are shown below for this example NSTART generation subunit 322 receives the intermediate instruction start counts and generates the instruction start counts Since the counts for the first and second scan regions already contain information about each start byte prior to the associated position (the counts in the second scan region include the last and only byte of the first scan region), these counts are unchanged by NSTART generation subunit 322 The intermediate instruction counts in the third region (l e PCSTART4, PCSTART5, and PCSTART6) provide shift amounts for the count in PCSTART3 In this example, PCSTART3 contains a count of one, PCSTART4 a count of zero, PCSTART5 a count of one, and PCSTART6 a count of two Therefore, NSTART4 conveys PCSTART3 shifted by zero (i e one), NSTART5 conveys PCSTART3 shifted by one (I e two), and NSTART6 conveys PCSTART3 shifted by two (l e three) NSl ART7 conveys NSTART6 shifted by two (the amount on PCSTART7) This causes NSl ART7 to convey a value of 4 binary zeros, indicative of four or more start bits prior to byte 7 The values for each instruction start count are shown below for this example Scan bus generation subunit 312 receives the NSTART and IVAL values shown above as its instruction start counts and instruction valid values along with the original start byte information, as noted above Scan bus generation subunit 312 then generates its four scan values from the received values Since byte zero is a start byte and its associated instruction start count (NSTARTO) is zero, the instruction valid value associated with byte zero (IVALO) is selected as SCANO Byte four is also a start byte, and its associated instruction start count (NSTART4) is one Therefore, the instruction valid value associated with byte four (IVAL4) is selected as SCANl Similarly, IVAL5 and IVAL6 are selected as SCAN2 and SCANS, respectively Therefore, the final scan values are shown below and equal the expected results for the example Byte position 01234567 SCANO 1 1 1 10000 SCAN l 00001000 SCAN2 00000100 SCAN3 0000001 1 The preceding example contained a full complement of four valid instructions The following example contains two valid instructions, and will be presented in tabular format below It is noted that exemplary register transfer level (RTL) code is included in this disclosure Byte position 01234567 Start byte information 10010000 End byte information 00100010 Therefore, the expected scan bus results would be Byte position 01234567 SCANO 1 1 100000 SCANl 0001 1 1 10 SCAN2 00000000 SCAN3 00000000 The instruction valid values generated by IVAL generation subunit 314 with this example of end byte information are 1VAL7 00000001 The intermediate instruction start counts generated by PCST ART generation subunit 316 according to this example's start byte information are The instruction start counts generated by NSTART generation subunit 322 according to this examples PCSTART values would then be Therefore, since byte 0 is a start byte and NSTARTO indicates zero previous start bytes, SCANO is selected to be IVALO Byte 3 is a start byte and NSTART3 indicates one previous start byte, so SCAN l is selected to be IVAL3 There are no other start bits, so SCAN2 and SCAN3 are selected to be zero Byte position 01234567 SCANO 1 1 100000 SCAN l 0001 1 1 10 SCAN2 00000000 SCAN3 00000000 Turning next to Figures 4A through 4E, exemplary logic diagrams of portions of the subunits shown in Tigure 3 are shown Figure 4 A shows an exemplary logic diagram of a portion of IVAL generation subunit 314 Exemplary logic circuits for the generation of IVALO and IVAL l are shown IVALO is a portion of IVAL bus 324 conveying the instruction valid value associated with the first of the eight contiguous instruction bytes, and IVALl is a portion of IVAL bus 324 conveying the instruction valid value associated with the second of the eight contiguous instruction bytes Other logic circuits (not shown) generate the instruction valid values associated with the other instruction bytes The instruction valid values for these bytes are conveyed on IVAL2 through IVAL7 The values conveyed on IVALO through IVAL7 form IVAL bus 324, as shown in Figure 4A End bit bus 304 is shown as eight conductors 304A-304H in Figure 4A, indicative of the eight contiguous instruction bytes scanned by this embodiment of instruction scanning unit 300 Conductor 304A conveys the end bit for the first of the eight contiguous instruction bytes (referred to as byte 0), conductor 304B conveys the end bit for the second of the eight contiguous instruction bytes (referred to as byte 1 ), etc An examination of the exemplary circuits shows that a particular bit for an instruction valid value is generated as the logical NOR of the end bits between the byte associated with the instruction valid value and the byte prior to the byte associated with the particular bit, inclusive Therefore, the first bit of IVALO is a constant one (since there are no end bits to examine) Furthermore, the second bit of IV ALO is the inverted end bit for byte 0 (i e the logical NOR of a single bit is an inversion) The third bit of IVALO is the NOR of the end bits for bytes 0 and 1 , etc Inverter 400 provides the second bit of IVALO, and NOR gate 401 provides the third bit of IVALO The NOR function for the fourth bit of IVALO is provided by NOR gate 402, while NOR gate 402, inverter 403, and AND gate 405 provide the NOR function for the fifth bit of IVAl 0 Similarly, the sixth bit of IVALO is generated from NOR gate 402, NOR gate 404, and AND gate 408 1 he seventh bit of IVALO is generated by NOR gate 402, NOR gate 406, and AND gate 409 Finally the eighth bit of IV ALO is provided by NOR gate 402, NOR gate 406, inverter 407 and AND gate 410 Similarly, the third bit of IVALl is the inverted end bit for byte 1 Note that the first bit (a constant zero) is not shown in Figure 4 A, and the second bit is a constant one The fourth bit of IVALl is the NOR of the end bit for bytes 1 and 2, etc In this way, the first end bit that is detected following the associated byte causes the subsequent bits in the instruction valid value to be cleared Bits between the associated byte and the first end bit are set Exemplary logic circuits for generating IVALl are shown in Figure 4 A The first bit of IVALl is not shown, since it is a constant zero The second bit is a constant one Inverter 41 1 provides the third bit of IVALl , while the fourth bit is provided by NOR gate 412 The fifth bit of IVALl is generated by NOR gate 413 The sixth bit of lVALl is generated by NOR gate 413, inverter 414, and AND gate 417 NOR gate 413, NOR gate 415, and AND gate 418 combine to form the NOR function for the seventh bit of IVALl Finally, NOR gate 413, NOR gate 416. and AND gate 419 form the NOR function for the eighth bit of IVALl It is noted that the embodiment of IVAL generation subunit 314 shown m Figure 4A employs eight bits of information forming IVALO but seven bits of information forming IVALl In fact, IVAL2 is comprised of six bits. IVAL3 of five bits, etc This is because the bits representing bytes prior to the byte position for which the instruction valid value is generated are constant zeros and therefore may be omitted Turning now to Figure 4B, exemplary logic circuits forming a portion of PCSTART generation subunit 316 are shown PCSTART generation subunit 316 receives start bit bus 302 from instruction cache 204 Start bit bus 302 is shown in Figure 4B as eight separate conductors which convey the eight start bits associated with the contiguous instruction bytes being scanned Conductor 302 A conveys the start bit associated with the first of the contiguous bytes (referred to as byte 0), conductor 302B conveys the start bit associated with the second of the contiguous bytes (referred to as byte 1 ), etc Figure 4B shows exemplary logic circuits for generating PCSTART3 and PCSTART5 PCSTART3 is the intermediate instruction start count for byte 3 (l e the fourth byte) of the eight contiguous bytes PCSTART5 is the intermediate instruction start count for byte 5 (I e the sixth byte) of the eight contiguous bytes Since PCSTART3 and PCSTART5 are in different scan regions, the portions of end bit bus 302 on which they operate are separate Other logic circuits (not shown) generate intermediate instruction start counts for other bytes within the contiguous instruction bytes scanned by instruction scanning unit 300 For the following discussion with respect to Figure 4B, the term "previous start bit" refers to a start bit within the scan region associated with a particular intermediate instruction start count and to the start bit associated with the last byte of the previous scan region In this embodiment, each intermediate instruction byte count and each instruction byte count are decoded values The first bit, when set, indicates that zero start bytes exist prior to the current byte The second bit, when set, indicates that one start byte exists prior to the current byte, etc Therefore, for intermediate start count generation, the first bit is set if none of the previous start bits are set This is a NOR function of the associated previous start bits, and is shown as NOR gate 430 for PCSTART3 and NOR gate 431 for PCSTART5 The second bit of an intermediate instruction start count indicates one previous start bit is set Therefore, an AND/OR network may provide the value where each of the input terminals of the AND gate are inverted except for one In this manner, if one and only one previous start bit is set, then the resulting intermediate instruction start count bit will be set This function is provided by AND gate 432, AND gate 433, AND gate 434, and OR gate 435 for PCSTART3 AND gate 436, AND gate 437 and OR gate 438 provide a similar function for PCSTART5 generation Two previous start bits being set is indicated by setting bit two of the intermediate instruction start counts An AND/OR network similar to the network for bit 1 may provide the value, except that two of the input terminals of the AND gates are not inverted In this manner, if any two previous start bits are set but no more than two are set, then the resulting intermediate instruction start count bit will be set AND gate 439, AND gate 440, AND gate 441 , and OR gate 442 provide this function for the embodiment shown in Figure 4B for PCSTART3 Similarly, AND gate 443 provides the function for PCSTART5 Finally, three previous start bits being set is indicated by setting bit three of the intermediate instruction start counts AND gate 444 provides this function for PCSTART3 However, PCSTART5 can not have three previous start bits set in this embodiment PCSTART5 has bits 3 and 4 of start bit bus 302 as its previous start bits, and so the largest number of previous start bits is two Therefore, bit three of PCSTART5 is set to a constant zero Turning now to Figure 4C, exemplary logic circuits for a portion of an embodiment of NSTART generation subunit 322 are shown The generation of the instruction start count associated with byte four (I e the fifth byte) of the plurality of contiguous instruction bytes scanned by instruction scanning unit 300 is depicted (referred to as NSTART4) As noted above, the instruction start counts for the first two scan regions are unmodified from the intermediate instruction start counts These unmodified counts are shown in Figure 4C as buses 450, 451 452, and 453, respectively As noted above, NSTART4 is PCSTART3 shifted by the value generated on PCSTART4 Multiplexor 454 is configured to provide this shifting If the first bit of PCSTART4 is set, indicating zero previous start bits, then port 0 of multiplexor 454 will be selected and NSTART4 will be equal to PCSTART3 If, however, the second bit of PCSTART4 is set indicating one previous start bit, then port 1 of multiplexor 454 will be selected and NSTART4 will be equal to PCSTART3 shifted by one value Ports 2 and 3 of multiplexor 454 are operated similarly with respect to the third and fourth bits of PCSTART4 Circuits for generating NSTART5, NSTART6, and NSTART7 are configured similarly Turning next to Figure 4D, exemplary logic circuits for a portion of one embodiment of scan bus generation subunit 326 are depicted In particular, logic circuits suitable for generating the first scan bus value (SCANO) are shown Multiplexor 460 is coupled to each instruction valid value generated by IVAL generation subunit 314 The corresponding start bits are received from instruction cache 204 on start bit bus 302, and the corresponding instruction start counts are received on NSl ART bus 320 As noted above, an instruction valid value is selected as SCANO if the corresponding start bit on start bit bus 302 is set and the corresponding instruction start count indicates that there are no previous instruction starts found within the plurality of contiguous instruction bytes scanned by instruction scanning unit 300 Therefore, an AND function of the corresponding start bit and the first bit of the corresponding instruction start count provides each select signal for multiplexor 460 AND network 461 provides the select signals for each port of multiplexor 460 Similar networks may be used to AND the start bits and the corresponding second bits of instruction start counts to select the instruction valid value for the second scan bus value (SCAN 1 ) Furthermore, similar networks may form the selects for multiplexors selecting SCAN2 and SCAN3 SCANO, SCAN 1 , SCAN2, and SCAN3 are conveyed on scan bus 312 along with the value conveyed as IVALO (which is used for the an instruction overflowing from a previous plurality of contiguous instruction bytes) Turning now to Figure 4E, exemplary logic circuits for implementing an embodiment of special checking subunit 328 are shown Inverter 470 is used to generate SCANO previous line bus 306 As noted above, SCANO previous line bus 306 is indicative of an instruction which ends in the plurality of contiguous instruction bytes scanned by instruction scanning unit 300 but does not start in these bytes This situation is detected by noting that an instruction does not start at the first byte of the bytes being scanned Also generated by special checking subunit 328 is the error detection bus 310 This bus conveys signals indicative of an error associated with the start and end information provided on start bit bus 302 and end bit bus 304 A first set of signals on error detection bus 3 10 indicates that an end byte is detected for a byte within the bytes being scanned and the subsequent byte is not indicated as a start byte AND gate 471 provides this check for the case where byte 0 is an end byte and byte 1 is not a start byte Similar logic circuits may provide this check for other bytes These signals may be advantageously used by external logic circuits (not shown) to detect which bytes within the plurality of contiguous bytes being scanned should be returned to predecode unit 202 A second set of signals on error detection bus 310 are indicative of more than one start byte being indicated before an end byte is indicated 1 his encoding is an error since the encoding indicates a new instruction is starting before the previous instruction ends OR gate 472 and AND gate 473 provide this functionality for checking start bytes associated w ith bytes 4 and 5 of the instruction bytes being scanned when byte 3 is a start byte and bytes 4 and 5 are prior to an end bit (as indicated by bit 5 of IVAL3) If bit 5 of IVAL3 is set, then no end bytes exist between byte 3 and byte 4 Therefore, if byte 4 or byte 5 is a start byte, an error condition exists Similar circuits may provide this check for other combinations of start and end byte information Further included within special checking subunit 328 as shown in F igure 4E are exemplary logic circuits for detecting an instruction overflowing to a subsequent plurality of contiguous instruction bytes For example, if byte seven is a start byte and is not an end byte, then the instruction starting at byte seven overflows to the subsequent plurality of instruction bytes If the instruction associated with byte seven is selected as the first scan bus value (as indicated by the associated instruction start count), then the associated scan overflow bus signal should be asserted AND gate 474 provides this functionality, and OR gate 475 allows similar gates to provide a similar check for the other instruction bytes Similar AND and OR gates may be used for the second, third, and fourth scan bus values It is noted that for other instruction bytes, a NOR function of the end byte information between that instruction byte and the seventh instruction byte may be performed prior to AND gate 474 It is noted that Figures 4A-4E have used a standard symbol for combining bus conductors into a single bus or for splitting bus conductors from a single bus For example, horizontal line 476 of Figure 4E is an indication that eight NSTART buses (NSTART0-NSTART7) form NSTART bus 322 These symbols have been included to keep the drawings uncluttered to facilitate understanding These symbols should not be construed to indicate any physical device As will be appreciated by those skilled in the art, a bus is simply a collection of conductors which are logically grouped together to form a value Disclosed below is an exemplary RTL description of one embodiment of the instruction scanning unit described above module ICSCAN_8 (S[70], E[70], SCAN0[70], SCANl [70], SCAN2[70] SCAN3[70], SCAN_OVFL_PREV[70], VAL_OVFL_PREV, VAI OVFL_NEXT[30], VALID[30], INV_PRED_POS[70] ), input [70] S, input [70] E, output [70] SCANO, output [70] SCANl, output [70] SCAN2, output [70]SCAN3, output [70] SCAN OVFL PREV, output V AL_0 VFL PRE V , output [30] VAL_OVFL_NEXT, output [30] VALID. output [70] INV_PRED_POS, reg [70] SCANO,// scan bits for position 0 reg [70] SCAN 1 ,// scan bits for position 1 reg [70] SCAN2,// scan bits for position 2 reg [70] SCAN3,// scan bits for position 3 reg [70] SCAN OVFL PREV,// scan bits for instruction that // started m previous line reg [30] VAL OVFL NEXT, / to indicate that the last //instruction has end bit in the next line reg VAL OVFL PREV, // to validate the scan bits in the //SCAN_OVFL_PREV reg [30] VALID,// valid bits for the 4 scan positions reg [70] INV PRED POS, // position where the predecoding //should start again for the line j******* ***************************************** ********** INTERNAL REGISTERS ****** t *************************************************** j reg [70] IVALO, // internal valid bits for instruction // starting at byte 0 reg [7:0] IVALl ; // internal valid bits for instruction // starting at byte 1 reg [7:0] IVAL2; // internal valid bits for instruction // starting at byte 2 reg [7:0] IVAL3; // internal valid bits for instruction // starting at byte 3 reg [7:0] IVAL4; // internal valid bits for instruction // starting at byte 4 reg [7:0] IVAL5; // internal valid bits for instruction // starting at byte 5 reg [7:0] IVAL6; // internal valid bits for instruction // starting at byte 6 reg [7:0] IVAL7; // internal valid bits for instruction // starting at byte 7 reg [7:0] SS NVALID0; // internal invalid bits for // instruction starting at byteO reg [7:0] SSJNVALID1 ; // internal invalid bits for // instruction starting at byte 1 reg [7:01 SSJNVALID2: // internal invalid bits for // instruction starting at byte2 reg [7:0] SSJNVALID3; // internal invalid bits for // instruction starting at byte3 reg [7:0] SS INVALID4; // internal invalid bits for // instruction starting at byte4 reg [7:0] SSJNVALID5; // internal invalid bits for // instruction starting at byte5 reg [7:0] SSJNVALID6; // internal invalid bits for // instruction starting at byte6 reg [7:0] SS INVALID7; // internal invalid bits for // instruction starting at byte7 /* what NSTART_x means NSTART_x[0] = 1 => there are exactly 0 bytes prior to byte x NSTART_x[ l] = I => there are exactly 1 bytes prior to byte x NSTART_x[2] = 1 => there are exactly 2 bytes prior to byte x NSTART_x[3] = 1 => there are exactly 3 bytes prior to byte x */ reg[3:0]NSTART_0 // count of start byte before byte 0 reg[3:0]NSTART_l // count of start byte before byte 1 reg [3:0] NSTART_2 // count of start byte before byte 2 reg [3:0] NSTART 3 // count of start byte before byte 3 reg[3:0]NSTART_4 // count of start byte before byte 4 reg[3:0]NSTART_5 // count of start byte before byte 5 reg [3:0] NSTART _6 // count of start byte before byte 6 reg [3:0] NSTART_7 // count of start byte before byte 7 reg[3:0]PCSTART_4 // count of start byte before byte // 4 and after byte 3 reg[3:0]PCSTART_5; // count of start byte before byte // 5 and after byte 3 reg [3:0] PCSTART_6; // count of start byte before byte // 6 and after byte 3 reg [3:0] PCSTART 7; // count of start byte before byte // 7 and after byte 6 reg [7:0] OFLOW; // to indicate instruction starting at a // certain byte position overflows to // the next line. I***** * ************************************************** LOGIC BEGINS HERE ********************************************************* / always @(TCLK2) begin // generating IVALO // worst case delay is for IVAL0[7] = 1 gate IVAL0[0] = l'bl; IVAL0[1]=!(E[0]); IVAL0[2] = !(E[0]||E[1]); IVAL0[3] = !(E[0]||E[1]||E[2]); IVAL0[4] = !(E[0]||E[1]||E[2]||E[3]); IVAL0[5] = !(E[0] || E[l] || E[2] || E[3] || E[4]); I VAL0[6] = !(E[0] || E[ 1 ] || E[2] || E[3] || E[4] || E[5]); IVAL0[7] = !(E[0] || E[l] || E[2] || E[3] || E[4] || E[5] || E[6]); OFLOW[0] = !(E[0] || E[l] || E[2] || E[3] || E[4] || E[5] || E[6] || E[7]); // generating SS JNVALIDO // worst case delay is for SS JNVALID0[7] = 2 gates SS_INVALIDO[0] = 1'bO; SSJNVALIDOf l] = IVALOf l ] && (S[l]); SS_INVALID0[2] = IVAL0[2] && (S[l] || S[2]); SS_INVALID0[3] = IVAL0[3] && (S[l] || S[2] [| S[3]); SS_INVALID0[4] = IVAL0[4] && (S[l ] || S[2] || S[3] || S[4]); SS_INVALID0[5] = IVAL0[5] && (S[l] || S[2] || S[3] || S[4] || S[5]); SS_INVALID0[6] = IVAL0[6] && (S[l] || S[2] || S[3] || S[4] || S[5] || S[6]), SS_INVALID0[7] = IVAL0[7] && (S[ l] || S[2] || S[3] || S[4] || S[5] |> S[6] || S[7]); // generating IVALl // worst case delay is for IVALl [7] = 1 gate IVAL1 [0] = 1 'bO; IVALI [ 1] = I'bl ; IVALl [2] = (E[l ]); IVALl [3] = E[2]); IVALl [4] = E[2] || E[3]); IVALl [5] = E[2] || E[3] || E[4]); IVALl [6] = E[2] || E[3] || E[4] || E[5]); IVALl [7] = E[2] || E[3] || E[4] || E[5] || E[6]), OFLOW[l] = !(E[1 ] || E[2] || E[3] || E[4] || E[5] || E[6] || E[7J). // generating SSJN VALID 1 // worst case delay is for SS INVALID 1 [7] = 2 gates SS_INVAL1D1 [0] = 1 'bO; SS_INVALID1 [1] = 1'bO; SSJNVALID 1 [2] = IVALl [2] && (S[2]); SSJNVALID 1 [3] = IVAL1 [3] && (S[2] || S[3]); SS_INVALID1 [4] = IVALl [4] && (S[2] || S[3] || S[4]); SSJNVALID 1 [5] = IVALl [5] && (S[2] || S[3] || S[4] || S[5]), SSJNVALID1 [6] = IVALl [6] && (S[2] || S[3] || S[4] || S[5] || S[6]), SSJNVALID1 [7] = IVALl [7] && (S[2J || S[3] || S[4] || S[5] || S[6] || S[7]); // generating IVAL2 // worst case delay is for IVAL2[7] = 1 gate IVAL2[0] = 1'bO; 1VAL2[1 ] = 1'bO; IVAL2[2] = l'bl ; IVAL2[3] = !(E[2]); IVAL2[4] = !(E[2] || E[3]); IVAL2[5] = !(E[2] || E[3] || E[4]); IVAL2[6] = !(E[2] || E[3] || E[4] || E[5]); IVAL2[7] = !(E[2] || E[3] || E[4] || E[5] || E[6]); OFLOW[2] = !(E[2] || E[3] || E[4] || E[5] || E[6] || E[7]); // generating SSJNVALID2 // worst case delay is for SS IN VALID2[7] = 2 gates SSJNVALID2[0] = 1'bO; SSJNVALID2[1 ] = I 'bO; SSJNVALID2[2] = 1'bO; SS JNVALID2[3] = IVAL2[3] && (S[3]); SSJNVALID214] = I VAL2[4] && (S[3] || S[4]); SSJNVALID2[5] = IVAL2[5] && (S[3] || S[4] || S[5]); SS JNVALID2[6] = IVAL2[6] && (S[3] || S[4] || S[5] || S[6]); SSJNVALID2[7] = IVAL2[7] && (S[3] || S[4] || S[5] || S[6] || S[7]); // generating IVAL3 // worst case delay is for IVAL3[7] = 1 gate IVAL310] = 1'bO; IVAL3[1 ] = 1'bO; IVAL3[2] = 1 'bO; IVAL3[3] = l 'bl ; 1VAL3[4] = !(E[3]); IVAL3[5] = !(E[3] || E[4]); IVAL3[6] = !(E[3] || E[4] || E[5]); IVAL3[7] = !(E[3] || E[4] || E[5] || E[6]); OFLOW[3] = !(E[3] || E[4] || E[5] || E[6] || E[7]); // generating SSJNVALID3 // worst case delay is for SSJNVALID3[7] = 2 gates SSJNVALID3[0] = 1'bO; SSJNVAL1D3[1 ] = 1'bO; SSJNVALID3[2] = 1'bO; SSJNVALID3[3] = 1'bO; SSJNVALID3[4] = IVAL3[4] && (S[4]); SSJNVALID3[5] = 1VAL3[5] && (S[4] || S[5]); SSJ VALID3[6] = IVAL3[6] && (S[4] || S[5] || S[6]); SSJNVALID3[7] = IVAL3[7] && (S[4] || S[5] || S[6] || S[7]); // generating IVAL4 // worst case delay is for IVAL4[7] = 1 gate IVAL4[0]= 1'bO; IVAL4[1]= 1'bO; IVAL4[2]= I'bO; IVAL4[3] = l'bO; IVAL4[4]= l'bl; IVAL4[5] = !(E[4]); IVAL4[6] = !(E[4] || E[5]) ; IVAL4[7] = !(E[4] || E[5] || E[6]); OFLOW[4] = !(E[4] || E[5] || E[6] || E[7]); // generating SS JNVALID4 // worst case delay is for SS JNVALID4[7] = 2 gates SSJNVΛLID4[0] = I'bO; SSJNVALID4[1]= I'bO; SSJNVALID4[2] = I'bO; SSJNVALID4[3] = l'bO; SSJNVALID4[4] = I'bO; SSJNVALID4[5] = IVAL4[5] && (S[5]); SSJNVALID4[6] = IVAL4[6] && (S[5] || S[6]); SSJNVALID4[7] = IVAL4[7] && (S[5] || S[6] || S[7]); // generating IVAL5 // worst case delay is for IVAL5[7] = 1 gate IVAL5[0]= I'bO; IVAL5[l]=l'bO; IVAL5[2]= I'bO; IVAL5[3] = I'bO: IVAL5[4]= I'bO: IVAL5[5]= l'bl: IVAL5[6] = !(E[5]); IVAL5[7] = !(E[5] || E[6]); OFLOW[5] = !(E[5] || E[6] || E[7]); // generating SS JNVALID5 // worst case delay is for SS JNVALID5[7] = 2 gates SSJNVALID5[0] = I'bO; SSJNVALID5[1]= I'bO; SSJNVALID5[2] = I'bO; SSJNVALID5[3] = I'bO; SSJNVALID5[4] = I'bO; SSJNVALID5[5] = I'bO; SSJ VALID5[6] = IVAL5[6] && (S[6]); SSJNVALID5[7] = IVAL5[7] && (S[6] || S[7]); // generating IVAL6 // worst case delay is for IVAL6[7] = 1 gate IVAL6[0]= I'bO; IVAL6[1]= I'bO; IVAL6[2]= I'bO; IVAL6[3]= I'bO; IVAL6[4] = l'bO; IVAL6[5]= I'bO; IVAL6[6]= l'bl; IVAL6[7] = !(E[6]); 0FL0W[6] = !(E[6] || E[7]); // generating SSJNVALID6 // worst case delay is for SS I VALID6[7] = 2 gates SSJNVALID6[0] = I'bO; SSJNVALID6[1]= I'bO; SSJNVALID6[2] = I'bO; SSJNVALID6[3] = I'bO; SSJNVALID6[4] = I'bO; SSJNVALID6[5]=l'bO; SSJNVALID6[6] = I'bO; SSJNVALID6[7] = IVAL6[7] && (S[7]) ; // generating IVAL7 // worst case delay is for IVAL7[7] = 1 gate 1VAL7[0]= I'bO; IVAL7[1]= I'bO IVAL7[2]= I'bO IVAL7[3] = I'bO, IVAL7[4] = I'bO, IVAL7[5] = I 'bO, IVAL7[6] = I'bO, IVAL7[7] = l'bl , OFLOW[7] = '(E[7]), // generating SS INVALID7 // worst case delay is for SSJNVALID7[7] = 0 gates SSJNVALID7[0] = I 'bO, SSJNVALID7[1 ] = I'bO, SSJNVALID7[2] = I 'bO, SSJNVALID7[3] = I'bO, SSJNVALID7[4] = I 'bO, SSJNVALID7[5] = I 'bO, SSJNVALID7[6] = I'bO, SSJNVALID7[7] = I'bO, /* generate 1NV PRED POS There are 2 cases when there can be this problem, either there is an instruction when there are two start bytes before we encounter an end byte, or the case when there is no start byte following an endbyte Since the start and end bytes have ben qualified by the start pointer for the line the end bytes preceding the first start byte in the line will be 0 */ INV_PRED_POS[0] = (S[0] && SSJNVALIDO) || (»S[0]), INV PRED_POS[ l ] = (S[l] && SSJNVALID 1 ) || ('S[ l ] && E[0]), lNV_PREDJ J OS[2] = (S[2] && SSJNVALJD2) || ('S[2] && E[ 1 ]), INVJPREDJ OS[3] = (S[3] && SSJNVAL1D3) || ('S[3] && E[2]), INV_PRED_POS[4] = (S[4] && SSJNVALID4) || ('S[4] && E[3]) rNVJ > R£DJ > OS[5] = (S[5] && SSJNVALID5) || ('S[5] && E[4]) INV_PRED_POS[6] = (S[6] && SSJNVALID6) || ('S[6] && E[5]), INVJ^RED^OSf?] = (S[7] && SSJNVALID7) || ("S[7] && E(6]), *************** THE THING **************** Now S[ι] & IVALι[7 0] will give me the valid bits for all the instructions in the cache line But we have to position them in the correct positions l e we have to assign these to the 4 valid bits sets for the 8-bytes This can be done if we have information about the number of start bytes in the cache line prior to this byte /* These count bits are generated in 2 stages First we evaluate the number of start bits in 4-bytes of the line Then using these count we evaluate the numbers for the second set of 4-bytes NSTART_0 = bO, NSTART =b0 + bl, NSTART_2 = bO + bl + b2, NSTART_3 = b0 + bl +b2→ b3, NSTART_4 = NSTART J + b4, NSTART 5 = NSTART 3 + (b4 + b5), NSTART_6 = NSTART_3 + (b4 + b5 + b6), NSTART 7 = NSTART 3 + (b4 + b5 + b6 + b7), */ NSTART _0[0] = 1 , NSTART_0[I] = 0, NSTART 0[2] = 0, NSTART_0[3] = 0, NSTART 1[0]=IS[0], NSTARTJ[1] = S[0], NSTARTJ [2] = 0, NSTART_1[3] = 0, NSTART_2[0] = i(S[0]||S[l]), NSTART_2[1] = (S[0] Λ S[l]), NSTART_2[2] = S[0]&&S[1], NSTART >[3] = 0, NSTART_3[0] = i(S[0] || S[l] || S[2]), NSTART_3[1] = (S[0] && 'S[l] && »S[2]) || (>S[0J && S[l] && >S[2]) || ('S[0] && >S[1] && S[2]), NSTART_3[2] = (S[0] && S[l] && 'S[2]) || ('S[0] && S[l] && S[2]) || (S[0] && 'S[l] && S[2]), NSTART_3[3] = S[0] && S[l] && S[2], PCSTART_4[0] = »S[3], PCSTART_4[1] = S[3], PCSTART_4[2] = 0; PCSTART_4[3] = 0; PCSTART _5[0] = !(S[3] || S[4]); PCSTART [1] = S[3] Λ S[4]; PCSTART 5[2] = S[3] && S[4]; PCSTART _5 [3] = 0; PCSTART 5[0] = !(S[3] || S[4] || S[5]); PCSTART _6[1] = (S[3] && !S[4] && !S[5]) || (!S[3] && S[4] && !S[5]) || (!S[3] && !S[4] && S[5]); PCSTART J3[2] = (S[3] && S[4] && !S[5]) || (!S[3] && S[4] && S[5]) || (S[3] && !S[4] && S[5]); PCSTART _6[3] = S[3] && S[4] && S[5]; NSTART_4[0] = NSTART_3[0] && PCSTART_4[0]; NSTART_4[1] = (NSTART_3[0] && PCSTART_4[1]) || (NSTART 3[1] && PCSTART_4[0]) NSTART_4[2] = (NSTART_3[2] && PCSTART_4[0]) || (NSTART_3[1] && PCSTART_4[1]) NSTART_4[3] = (NSTART_3[2] && PCSTART_4[1]) || (NSTART_3[3] && PCSTART_4[0]): NSTART 5[0] = NSTART_3[0] && PCSTART 5[0]; NSTART_5[1] = (NSTART_3[0] && PCSTART_5[1]) || (NSTART_3[I] && PCSTART_5[0]); NSTART 5[2] = (NSTART_3[0] && PCSTART_5[2]) || (NSTART_3[1] && PCSTART 5[l]) I (NSTART 3 [2] && PCSTART _S[0]); NSTART_5[3] = (NSTART_3[1] && PCSTART_5[2]) || (NSTART [2] && PCSTART_5[1]) (NSTART_3[3] && PCSTART 5[0]); NSTART _6[0] = NSTART_3[0] && PCSTART 5[0]; NSTART_6[1] = (NSTART_3[0] && PCSTART_6[1]) || (NSTART_3[1] && PCSTART_6[0]); NSTART_6[2] = (NSTART_3[0] && PCSTART _6[2]) || ( START_3[1] && PCSTART_6[1]) (NSTART [2] && PCSTART_6[0]); NSTART_6[3] = (NSTART_3[1] && PCSTART_6[2]) || (NSTART [2] && PCSTART_6[1]) | (NSTART [3] && PCSTART_6[0]); PCSTART_7[0] = !S[6]; PCSTARTJ7[1] = S[6]; PCSTART_7[2] = 0; PCSTART J7[3] = 0; NSTART 7[0] = NSTART_6[0] && PCSTART 7[0]; NSTART _7[1] = (NSTART_6[0] && PCSTART_7[1]) || (NSTART_6[1] && PCSTART 7[0]); NSTART 7[2] = (NSTART_6[2] && PCSTART 7[0]) || (NSTART_6[1] && PCSTARTJ7[1]); NSTART 7[3] = (NSTART_6[2] && PCSTART_7[1]) || (NSTART_6[3] && PCSTART 7[0]); /4 ,***** 4 ********** N ow TO MUX THE VALID BITS ************/ VAL OVFL NEXT = 4'b0; case (l'bl) (S[0] && NSTART OfO]): begin VALID[0]=l'bl; SCANO = IVALO; if (OFLOWfO]) VAL_OVFLJ EXT[0] = l'bl; end (S[l]&& NSTARTJ [0]): begin VALID[0]= l'bl; SCANO = IVALl; if (OFLOW[ 1 ]) V AL_0 VFL JMEXT[0] = 1 'b 1 ; end (S[2] && NSTART >[0]): begin VALID[0] = l'bl; SCANO = IVAL2; if (0FL0W[2]) VAL_OVFL_NEXT[0] = l'bl ; end (S[3] && NSTART [0]): begin VALID[0] = l'bl; SCANO - IVAL3; if (OFLOW[3]) VALJDVFL_NEXT[0] = l'bl; end (S[4] && NSTART_4[0]): begin VALID[0]=l'bl; SCANO = IVAL4; if (OFLOW[4]) VAL_OVFLJ^EXT[0] = l'bl; end (S[5] && NSTART_5[0]): begin VALID[0] = l'bl; SCANO = IVAL5; if (OFLOW[5]) VAL OVFL _NEXT[0] = l'b 1 ; end (S[6] && NSTART_6[0]): begin VALID[0]=l'bl; SCANO = IVAL6; if(OFLOW[6]) VAL_OVFL_NEXT[0] = l'bl; end (S[7] && NSTART 7[0]): begin VALID[0]= l'bl; SCANO = 1VAL7; if(OFLOW[7]) VAL_OVFLJMEXT[0] - l'bl: end default: begin VALID[0]= I'bO; SCANO = 8'bO; VAL_OVFL_NEXT[0] = I'bO; end endcase case (l'bl) (S[l] && NSTARTJ [1]): begin VALID[I]= l'bl; SCANl = IVALl; if(OFLOW[l]) VAL OVFLJ EXTfl] = l'bl; end (S[2]&& NSTART >[1]): begin VALID[l]=l'bl; SCANl =IVAL2; if(OFLOW[2]) VALJDVFLJMEXTfl] = l'bl: end (S[3] && NSTART 3[1]): begin VALID[I]= l'bl; SCANl =IVAL3; if (OFLOW[3]) VALJDVFL_NEXT[1] = l'bl; end (S[4]&&NSTART_4[1]): begin VALID[l] = l'bl; SCANl =IVAL4; if (OFLOW[4]) VALJDVFLJJEXT[1] = l'bl; end (S[5]&& NSTART _5[ I]): begin VALID[l] = l'bl; SCANl =IVAL5; if (OFLOW[5]) VAL_OVFL_NEXT[l] = l'bl, end (S[6]&&NSTART_6[1J): begin VALID[l] = l'bl; SCANl =IVAL6; if(OFLOW[6]) VAL_OVFL_NEXT[l] = l'bl, end (S[7] && NSTARTJ7[1])' begin VALID[1]= l'bl; SCANl =IVAL7; if (0FL0W[7]) VAL OVFL _NEXT[1] = l'bl; end default: begin VALID[l] = l'b0; SCANl =8'b0; VAL_OVFL_NEXT[l] = I'bO; end endcase case (l'bl) (S[2] && NSTART 2[2]): begin VALID[2]=l'bl; SCAN2 = IVAL2; if (OFLOW[2]) V ALJ3VFL_NEXT[2] = l'b 1 ; end (S[3] && NSTART_3[2]): begin VALID[2] = l'bl; SCAN2 = IVAL3; if(0FL0W[3]) VAL DVFL_NEXT[2] = l'bl; end (S[4] && NSTART_4[2]): begin VALID[2]=l'bl; SCAN2 = IVAL4; if (0FL0W[4]) VAL_0VFL_NEXT[2] = l'bl; end (S[5] && NSTART i[2]): begin VALID[2]= l'bl; SCAN2 = IVAL5; if(0FL0W[5]) VAL_OVFLJJEXT[2] = l'bl; end (S[6] && NSTART_6[2]): begin VALID[2]= l'bl; SCAN2 = IVAL6; if (OFLOW[6]) VAL DVFL_NEXT[2] = l'bl; end (S[7] && NSTART '[2]): begin VALID[2]=l'bl; SCAN2 = IVAL7; if (OFLOW[7]) VAL_OVFL_NEXT[2] = l'bl ; end default: begin VALID[2] = l'b0; SCAN2 = 8'b0; VAL_OVFLJ^EXT[2] = I'bO; end endcase case (l'bl) (S[3] && NSTART_3[3]): begin VALID[3]= l'bl; SCAN3 = IVAL3; if (OFLOW[3]) VAL_OVFL_NEXT[3] = l'bl; end (S[4] && NSTART_4[3]): begin VALID[3] = l'bl; SCAN3 = IVAL4; if (OFLOW[4]) VAL_OVFL_NEXT[3] = l'bl; end (S[5] && NSTART_5[3]): begin VALID[3]= l'bl; SCAN3 = IVAL5; if (OFLOW[5]) VΛL DVFLJ<JEXT[3] = l'bl; end (S[6] && NSTART_6[3]): begin VALID[3] = l'bl; SCAN3 = IVAL6; if (OFLOW[6]) VAL DVFL_NEXT[3] = l'bl; end (S[7]&& NSTART J7[3]): begin VALID[3] = l'bl; SCAN3 = IVAL7; if (OFLOW[7]) V AL DVFL_NEXT[3] = l'b 1 ; end default: begin VALID[3]= I'bO; SCAN3 = 8'bO, VAL_OVFL_NEXT[3] = I'bO, end endcase /* OVERFLOW of instruction from previous line or to the next line The case of the instruction overflowing from the previous set of 8 bytes, this can be detected by the case in which there is no start byte in byte 0 The case of the valid instruction overflowing to the next line can be found by the case in which E[7] = 0 an there is at least one valid bit set */ case (l 'bl ) CS[0]) begin SCAN DVFL PREV = IVALO, VAL OVFL PREV = l 'bl , end default begin SCAN_OVFLJ > REV = 8'bO, VAL OVFL PREV = I 'bO, end endcase end endmodule It is noted that the above discussion described an embodiment of instruction scanning unit 300 which scans eight contiguous instruction bytes for up to four instructions Other embodiments may vary the number of contiguous instruction bytes as well as the maximum number of instructions scanned for Figures 4A through 4E and the RTL description are also exemplary embodiments of instruction scanning unit 300 Many other embodiments are possible and specifically contemplated In accordance with the above disclosure, a parallel and scalable instruction scanning unit has been described The instruction scanning unit utilizes two gate delays and three multiplexor delays to perform the scanning function, which may allow high frequency operation while advantageously locating multiple instructions in a single cycle. Both performance and frequency may be increased for a superscalar microprocessor implementing a similar instruction scanning unit. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be interpreted to embrace all such variations and modifications.

Claims: WHAT IS CLAIMED IS: 1 An instruction scanning unit for scanning a block of predecode information associated with a plurality of contiguous instruction bytes wherein said block of predecode information includes start byte information indicative of bytes which start instructions and wherein said block of predecode information further includes end byte information indicative of bytes which end instructions, said instruction scanning unit comprising an input bus configured to convey said block of predecode information, a first subunit coupled to said input bus wherein said first subunit is configured to receive said end byte information, and wherein said first subunit is configured to generate a plurality of instruction valid values, and wherein each of said plurality of instruction valid values is indicative of a potential valid instruction starting at a particular byte within said plurality of contiguous instruction bytes and ending at a byte specified by said end byte information, and wherein said first subunit is configured to convey said plurality of instruction valid values on a plurality of instruction valid buses, and a second subunit coupled to said input bus wherein said second subunit is configured to receive said start byte information, and wherein said second subunit is configured to generate a plurality of instruction start counts, and wherein each of said instruction start counts is indicative of d number of instructions which start between a first one of said plurality of contiguous instruction bytes and a particular one of said plurality of contiguous instruction bytes and wherein said second subunit is configured to convey said plurality of instruction start counts on a plurality of instruction start count buses, and wherein said first subunit and said second subunit operate in parallel 2 The instruction scanning unit as recited in claim 1 further comprising a third subunit coupled to said input bus, said plurality of instruction valid buses, and said plurality of instruction start count buses wherein said third subunit is configured to select a plurality of scan bus values from said plurality of instruction valid values, and wherein said third subunit is configured to convey said plurality of scan bus values on a plurality of scan buses 3 The instruction scanning unit as recited in claim 2 wherein said third subunit is configured to select said plurality of scan bus values according to said start byte information and said plurality of instruction start counts 4 The instruction scanning unit as recited in claim 3 wherein a first of said plurality of instruction valid values is selected as a first of said plurality of scan bus values if said start byte information indicates that said particular byte associated with said first of said plurality of instruction valid values is a byte in which an instruction starts and if a first of said plurality of instruction start counts indicates that zero instructions start prior to said particular byte 5 The instruction scanning unit as recited in claim 3 wherein a second of said plurality of instruction valid values is selected as a second of said plurality of scan bus values if said start byte information indicates that said particular byte associated with said second of said plurality of instruction valid values is a byte in which an instruction starts and if a second of said plurality of instruction start counts indicates that one instruction starts prior to said particular byte 6 The instruction scanning unit as recited in claim 3 wherein a third of said plurality of instruction valid values is selected as a third of said plurality of scan bus values if said start byte information indicates that said particular byte associated with said third of said plurality of instruction valid values is a byte in which an instruction starts and if a third of said plurality of instruction start counts indicates that two instructions start prior to said particular byte 7 The instruction scanning unit as recited in claim 3 wherein a fourth of said plurality of instruction valid values is selected as a fourth of said plurality of scan bus values if said start byte information indicates that said particular byte associated with said fourth of said plurality of instruction valid values is a byte in which an instruction starts and if a fourth of said plurality of instruction start counts indicates that three instructions start prior to said particular byte 8 The instruction scanning unit as recited claim 1 wherein said each of said plurality of instruction valid values comprises a mask of binary zeros and binary ones, and wherein said binary ones are contiguous to each other 9 The instruction scanning unit as recited in claim 8 wherein said binary ones are indicative of bytes which comprise said potential instruction 10 The instruction scanning unit as recited in claim 1 wherein each of said plurality of instruction start counts is a value indicative of between zero and three instructions 1 1 The instruction scanning unit as recited in claim 1 wherein said second subunit further comprises a pair of subunits. and wherein a first of said pair of subunits is coupled to said input bus, and wherein a second of said pair of subunits is coupled to said first of said pair of subunits and to said plurality of instruction start count buses 12 The instruction scanning unit as recited in claim 1 1 wherein said first of said pair of subunits is configured to generate a plurality of intermediate instruction start counts wherein each of said plurality of intermediate instruction start counts is indicative of a number of instructions which start between a second one of said plurality of contiguous instruction bytes and a third one of said plurality of contiguous instruction bytes. 13. The instruction scanning unit as recited in claim 12 wherein said second of said pair of subunits is configured to receive said plurality of intermediate instruction counts and is configured to generate said plurality of instruction start counts. 14. The instruction scanning unit as recited in claim 13 wherein said second of said pair of subunits is configured to generate one of said plurality of instruction start counts by adding one of said plurality of intermediate instruction start counts to another one of said intermediate instruction start counts. 15. The instruction scanning unit as recited in claim I further comprising a fourth subunit coupled to said input bus wherein said fourth subunit is configured to provide scalability functionality. 16. The instruction scanning unit as recited in claim 15 wherein said scalability functionality comprises detection of an instruction which starts within said plurality of contiguous instruction bytes but does not end within said plurality of contiguous instruction bytes. 17. The instruction scanning unit as recited in claim 15 wherein said scalability functionality comprises detection of an instruction which ends within said plurality of contiguous instruction bytes but does not start within said plurality of contiguous instruction bytes. 18. The instruction scanning unit as recited in claim 15 wherein said scalability functionality comprises detecting that said first one of said plurality of contiguous instruction bytes is not a start byte. 19. The instruction scanning unit as recited in claim 15 wherein said fourth subunit is further configured to provide error checking functionality. 20. The instruction scanning unit as recited in claim 19 wherein said error checking functionality comprises detection of a second start byte subsequent to a first start byte but prior to an end byte. 21. The instruction scanning unit as recited in claim 19 wherein said error checking functionality comprises detection of an end byte and a byte subsequent to said end byte is not a start byte. 22. A method of identifying valid instructions within a plurality of instruction bytes comprising: creating a plurality of masks wherein each one of said plurality of masks is associated with a respective one of said plurality of instruction bytes, and wherein said each one of said plurality of masks is indicative of an instruction beginning at said respective one of said plurality of instruction bytes and ending at a subsequent one of said plurality of instruction bytes, and selecting one of said plurality of masks when said respective one of said plurality of instruction bytes is the beginning of an instruction 23 The method as recited in claim 22 wherein said creating is performed using end byte information indicative of which of said plurality of instruction bytes are end bytes 24 The method as recited in claim 23 wherein said subsequent one of said plurality of instruction bytes is indicated by said end byte information to be an end byte 25 The method as recited in claim 23 wherein said end byte information comprises a plurality of end bits, and wherein a respective one of said plurality of end bits is associated with said respective one of said plurality of instruction bytes, and wherein said respective one of said plurality of end bits being set is indicative of said respective one of said plurality of instruction bytes being an end byte 26 The method as recited in claim 22 wherein said selecting is performed using start byte information indicative of which of said plurality of instruction bytes are start bytes 27 1 he method as recited in claim 26 wherein said start byte information comprises a plurality of start bits, and wherein a respective one of said plurality of start bits is associated with said respective one of said plurality of instruction bytes, and wherein said respective one of said plurality of start bits being set is indicative of said respective one of said plurality of instruction bvtes being a start byte 28 The method as recited in claim 22 wherein said selecting further comprises generating a plurality of instruction start counts wherein a respective one of said plurality of instruction start counts is indicative of a number of instructions beginning prior to said respective one of said plurality of instruction bytes 29 The method as recited in claim 28 wherein said creating and said generating are performed in parallel 30 The method as recited in claim 28 wherein said selecting is performed by locating a start byte associated with one of said plurality of instruction start counts wherein said one of said plurality of instruction start counts is indicative of zero instructions beginning prior to said start byte 31 The method as recited in claim 28 wherein said selecting is performed by locating a start byte associated with one of said plurality of instruction start counts wherein said one of said plurality of instruction start counts is indicative of one instruction beginning prior to said start byte 32. The method as recited in claim 28 wherein said selecting is performed by locating a start byte associated with one of said plurality of instruction start counts wherein said one of said plurality of instruction start counts is indicative of two instructions beginning prior to said start byte. 33. The method as recited in claim 28 wherein said selecting is performed by locating a start byte associated with one of said plurality of instruction start counts wherein said one of said plurality of instruction start counts is indicative of three instructions beginning prior to said start byte. 34. The method as recited in claim 22 further comprising conveying said one of said plurality of masks to an instruction alignment unit configured to select instruction bytes according to a mask. 35. The method as recited in claim 22 further comprising checking for errors within start byte information and end byte information associated with said plurality of instruction bytes. 36. The method as recited in claim 35 wherein said checking comprises detecting the beginning of a second instruction subsequent to detecting the beginning of a first instruction but prior to detecting the end of said first instruction. 37. The method as recited in claim 35 wherein said checking comprises detecting the end of an instruction and detecting the lack of a beginning of a subsequent instruction. 38. The method as recited in claim 22 further comprising generating scalability functionality such that said plurality of instruction bytes may be identified in parallel with a second plurality of instruction bytes. 39. The method as recited in claim 38 wherein said scalability functionality comprises detection of an instruction beginning within said plurality of instruction bytes but not ending within said plurality of instruction bytes. 40. The method as recited in claim 38 wherein said scalability functionality comprises detection of an instruction ending within said plurality of instruction bytes but not beginning within said plurality of instruction bytes. 41. A superscalar microprocessor comprising an instruction cache including an instruction scanning unit wherein said instruction scanning unit comprises: an input bus for conveying start byte information and end byte information associated with a plurality of instruction bytes; a first subunit coupled to said input bus for receiving said end byte information wherein said first subunit is configured to generate a plurality of masks, and wherein each one of said plurality of masks is associated with a respective one of said plurality of instruction bytes, and wherein said each one of said plurality of masks is indicative of an instruction beginning at said respective one of said plurality of instruction bytes and ending at a subsequent one of said plurality of instruction bytes, and wherein said subsequent one of said plurality of instruction bytes is indicated by said end byte information to be the end of an instruction; a second subunit coupled to said input bus for receiving said start byte information wherein said second subunit is configured to generate a plurality of instruction start counts, and wherein a respective one of said plurality of instruction start counts is indicative of a number of instructions beginning prior to said respective one of said plurality of instruction bytes, and wherein said plurality of instruction start counts are generated from said start byte information; and a third subunit coupled to said first subunit for receiving said plurality of masks, and coupled to said second subunit for receiving said plurality of instruction start counts, and coupled to said input bus for receiving said start byte information, wherein said third subunit is configured to select a plurality of scan bus values from said plurality of masks according to said plurality of instruction start counts and said start byte information. 42. The superscalar microprocessor as recited in claim 41 further comprising a fourth subunit coupled to said input bus wherein said fourth subunit is configured to provide scalability functionality and error checking functionality. 43. The superscalar microprocessor as recited in claim 41 wherein said instruction cache further includes an instruction storage array including a plurality of storage locations for storing instruction bytes. 44. The superscalar microprocessor as recited in claim43 further comprising a predecode unit coupled to said instruction cache wherein said predecode unit is configured to fetch instruction bytes from main memory, to generate predecode information including said start byte information and said end byte information, and to store said instruction bytes and said predecode information into said instruction storage array. 45. The superscalar microprocessor as recited in claim 43 further comprising an instruction alignment unit coupled to said instruction cache wherein said instruction alignment unit is configured to receive said plurality of instruction bytes and said plurality of scan bus values, and wherein said instruction alignment unit is configured to select instructions from said plurality of instruction bytes according to said plurality of scan values. 46 The superscalar microprocessor as recited in claim 45 further comprising a plurality of decode units coupled to said instruction alignment unit wherein said instruction alignment unit is configured to convey at most one instruction to each of said plurality of decode units during a clock cycle 47 The superscalar microprocessor as recited in claim 46 wherein said plurality of decode units are configured to decode instructions 48 The superscalar microprocessor as recited in claim 46 further comprising a plurality of reservation stations wherein each one of said plurality of reservation stations is coupled to a respective one of said plurality of decode units, and wherein said plurality of decode units are configured to convey decoded instructions to said plurality of reservation stations 49 The superscalar microprocessor as recited in claim 48 wherein said reservation stations are configured to store said decoded instructions 50 The superscalar microprocessor as recited in claim 48 further comprising a plurality of functional units wherein each one of said plurality of functional units is coupled to a respective one of said plurality of reservation stations and wherein said plurality of reservation stations are configured to convey said decoded instructions to said functional units 51 The superscalar microprocessor as recited in claim 50 further comprising a reorder buffer coupled to said plurality of decode units and to said plurality of functional units wherein said plurality of functional units are configured to execute said decoded instructions and to forward results to said reorder buffer, and wherein said reorder buffer is configured to store said results 52 The superscalar microprocessor as recited in claim 51 further comprising a register file for storing non- speculative register values wherein said register file is coupled to said reorder buffer and to said plurality of decode units 53 A method of identifying an instruction within a plurality of contiguous bytes comprising creating a plurality of masks wherein each of said plurality of masks is indicative of a potential instruction beginning at a respective one of said plurality of contiguous bytes and ending at a subsequent one of said plurality of contiguous bytes, and selecting one of said plurality of masks if said respective one of said plurality of contiguous bytes corresponding to said one of said plurality of masks is the beginning of said instruction A superscalar microprocessor comprising an instruction cache configured to store a plurality of bytes, corresponding start byte information identifying which ones of said plurality of bytes form a start byte of an instruction, and corresponding end byte information identifying which ones of said plurality of bytes form an end byte of an instruction, wherein said instruction cache includes an instruction scanning unit which, upon fetch of said plurality of bytes, is configured to scan said end byte information to create a plurality of masks indicative of potential instructions beginning at a respective one of said plurality of bytes and ending at a subsequent byte within said plurality of bytes, said subsequent byte identified by said end byte information as an end byte of an instruction, and wherein said instruction scanning unit is further configured to scan said start byte information in parallel with scanning said end byte information, and wherein said instruction scanning unit is configured to select certain ones of said plurality of masks corresponding to respective ones of said plurality of bytes which are identified by said start byte information as a start byte of said instruction, and an instruction alignment unit coupled to receive said plurality of bytes and said certain ones of said plurality of masks, wherein said instruction alignment unit is configured to route particular ones of said plurality of bytes to one of a plurality of decode units in accordance with one of said certain ones of said plurality of masks

Applicants: ADVANCED MICRO DEVICES INC, RAMMOHAN NARAYAN, ADVANCED MICRO DEVICES, INC., RAMMOHAN, NARAYAN
Application year: 1996
Main classification: G06F9
IPC codes: G06F9, G06F11