Method to prevent disturbances during the programming and erasing phases in a non-volatile memory device

Abstract: The invention concerns a method of avoiding disturbance during the step of programming and erasing an electrically programmable, semiconductor integrated non-volatile memory device which comprises a matrix of memory cells divided into sectors and programmable in a byte mode. An operation of verification of the contents of the byte to be programmed, to be carried out for each individual bit, is provided even before the first program pulse is applied. The invention further provides for the parallel erasing of several sectors during an erase step, and a verification of the erase step for each sector in the matrix. If the verification shows that a sector has been erased, the sector is applied no further erase pulses.

Description: This invention relates to a method of avoiding disturbance during the step of programming an electrically programmable semiconductor non-volatile memory device. More particularly, the invention relates to a method for application to a semiconductor integrated non-volatile memory device having a single power supply and comprising a matrix of memory cells divided into sectors, and being programmable electrically in a byte mode, but the considerations made hereinafter would equally apply to any other type of flash memory, including flash memories with dual power supplies. As is well known, read-only memories of the flash type, albeit non-volatile, do allow information contained therein to be modified electrically, both during the write or program step and the erase step. Memories of this type are constructed as matrices of cells arranged into rows, or word lines, and columns, or bit lines. Each cell comprises basically a floating gate transistor having a drain region and a source region formed on a semiconductor substrate and isolated by a channel region. The floating gate is formed over the substrate and isolated from the latter by a thin layer of gate oxide. A control gate is coupled capacitively to the floating gate through a dielectric layer, and metallic electrodes are provided for contacting the drain, source, and control gate, in order to have predetermined voltage values applied to the memory cell. Cells in the same word line have the electric line in common which drives their respective control gates, while cells in the same bit line have the drain terminals in common. Background Art When suitable voltage values are applied to cell terminals, the cell state can be altered by changing the amount of the charge present at the floating gate. The operation whereby charge is stored into the floating gate is called "programming", and consists of biasing the control gate and drain terminal at a predetermined higher value than the electric potential of the source terminal. For example, each individual cell can be programmed by a hot electron injection process that allows electrons to become trapped within the floating gate when the control gate is applied a relatively high voltage Vg in the 9 to 12V range. Concurrently therewith, the source terminal is connected to ground and the drain terminal is biased at a voltage Vb in the 4 to 7V range. The programming of a flash memory can be performed either by the sector (page mode) or the byte (byte mode). In the former case, all the cells in one row of the matrix are addressed simultaneously. In the latter case, a single byte of the many available in one row is addressed. The use of positive voltages Vg and Vb with relatively high values poses more than one problem from the standpoint of possible disturbance to cells adjacent to those being programmed, such as those cells in the same bit line which are not to be programmed and have their control gates connected to ground. This phenomenon may result in spurious erasing of the stressed cells. In all cases, programming noise is apt to make retention of the charge after prolonged read cycles less secure. A first prior art solution is disclosed in the EP application No. 0 432 481 wherein it is disclosed a method for avoiding disturbance during the programming step of a non-volatile memory device, EPROM type. This memory may be programmed in a byte mode and the method provides for a verification step of the content of the byte to be programmed even before the first programming pulse is applied. A second prior art solution is disclosed in the PCT application No. WO 90 12400 that relates to a method of programming a matrix of memory cells in a byte mode. This document provides for an operation of verification of the content of the byte (chunk) to be programmed even before the first programming pulse is applied. An EEPROM having a single 3V power supply is disclosed in the article: "Developpments in programming Flash at 3V" Electronic Engineering, vol. 65, no. 798, 1 June 1993, pages 62, 65-66. All the above prior art references, while disclosing the possibility to check the byte content before applying the first programming pulse, don't consider the possibility to perform this check phase during the rise transient of a programming voltage. It is a primary object of the present invention to solve this problem. The underlying technical problem of this invention is to provide a method of preventing, during the programming step, disturbance of an integrated memory device as previously indicated, the method having such performance characteristics as to extend the useful life of the memory device and overcome the drawbacks of state-of-art programming and erasing techniques. Summary of the Invention The solution idea on which this invention stands is one of carrying out a verify operation on a byte to be programmed, prior to it being applied the first program pulse wherein the solvent idea provides a break in the rising transient of a programming voltage for reading the byte to be programmed. Based on this solution idea, the technical problem is solved by a method as previously indicated and as defined in claim 1 and by a memory device as defined in claim 4, all claims appended to this specification. The features and advantages of a method according to the invention will be apparent from the following detailed description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings. Brief Description of the Drawing In the drawing: Figure 1 is a diagramatic representation of an algorithm for implementing a byte programming mode in accordance with the method of this invention. Detailed Description Referring to the drawing figure, the method of this invention for preventing disturbance during the programming of an electrically programmable semiconductor non-volatile memory device will now be described. The inventive method is particularly, but not exclusively, intended for a single power supply integrated memory device which comprises a matrix of memory cells having multiple sectors and respective device-resident program algorithms. Each memory cell comprises a floating gate MOS transistor having an additional control gate. The cells are organized as rows or word lines, and columns or bit lines. The cells of one word line share the electric line driving their respective control gates, while the cells in one bit line having their drain terminals in common. The method of this invention is particularly, but not solely, useful with a flash memory having a single power supply at a supply voltage Vcc of 5V. The invention has been applied to a memory implemented with double-well technology and erased by a negative voltage to the cell gates. The cell matrix is a four-Mbyte matrix divided into eight sectors of 512 kbytes each, with memory words of sixteen bits. Shown in Figure 1 is a flow chart for a program algorithm 1 used in practicing the inventive method. This algorithm 1 includes a starting step START directly followed by a test step 2 for ascertaining the need to have a byte of the memory device programmed. If this test step 2 fails (N), the algorithm 1 is interrupted, and control is transferred onto other algorithms; otherwise, the procedure is continued to allow the programming voltage Vpcy to rise which is to be applied to the i-th column of the matrix memory being programmed. This step is illustrated by block 3. The programming voltage Vpcy attains a steady-state value of 12V. The algorithm 1 also provides for the rise of a second programming voltage Vpcx, to be applied to the j-th row in the matrix. This second voltage value, indicated in block 4, attains 7V as a steady state value. At this time, according to the invention, a read/verify step 5 is carried out for the byte being programmed. Reading lasts approximately a hundred nanoseconds and effected to advantage during the rise transient of the second programming voltage Vpcx. This is followed by a test step 6 to find out whether the data contained in the byte being programmed contains preprogrammed bits. This check is performed individually for each of the bits. If this checks out favorably (Y), that is when each of the bits within the byte carry a value of "zero", the algorithm is interrupted. This is illustrated by the STOP terminal. On the other hand, if the byte being programmed does not contain zero-programmed bits, a program pulse is enabled as illustrated by block 7. Thereafter, the number of program attempts is checked at the end of the program pulse through test block 8. If this check reveals a lower number than a predetermined value, the test checks out unfavorably (N), and the algorithm 1 cycle is resumed from a point ahead of block 4. Where the number of program attempts reaches the predetermined limit, an error signal FAIL is issued. The method of this invention affords a number of advantages, the foremost of which is that no program pulse is applied to a previously written bit. Each bit of a given byte is checked on an individual basis, and a byte is only applied a minimum number of program pulses. Thus, the cells in one bit line of the byte being programmed will be unstressed, even if the user utilizes the algorithm 1 incorrectly. Overwriting an existing "zero" with another zero would still place no stress on the drain terminal of the involved memory cell. Where an application only requires the incremental writing of a byte or a memory word, such as if the change in the informational contents of a byte is of the following type: 11111110 => 11111101 => 11111100, this can be done without entailing any problems of reliability.

Claims: A method of avoiding disturbance during a programming step of an electrically programmable, semiconductor integrated non-volatile memory device which comprises a matrix of memory cells divided into sectors and programmable in a byte mode, and wherein an operation of verification of the contents of the byte to be programmed is carried out before a first programming pulse is applied wherein a first programming voltage (Vpcy) is raised until it attains its steady state value, and said first programming voltage (Vpcy) is applied to a column of the memory matrix, the method being characterized in that a short break in the rise transient of a second programming voltage (Vpcx) of the memory cells is provided during which said byte to be programmed is read , said second programming voltage (Vpcx) is applied to rows of the memory matrix. A method according to Claim 1, characterized in that said operation of verification is carried out individually for each bit. A method according to Claim 1, characterized in that said operation of verification is effective to check whether the data contained in the byte to be programmed already includes bits programmed at a "zero" value. An electrically programmable, semiconductor integrated non-volatile memory device of the type having a single power supply and comprising a matrix of memory cells divided into sectors and programmable in a byte mode, characterized in that it includes a resident program operating according to the method as claimed in Claim 1.

Inventors: BARTOLI SIMONE, DALLABORA MARCO, DEFENDI MARCO, VILLA CORRADO, BARTOLI, SIMONE, DALLABORA, MARCO, DEFENDI, MARCO, VILLA, CORRADO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1996
Main classification: G11C16
IPC codes: G11C16