PMOS memory cell with hot electron injection programming and tunnelling erasing

Abstract: A P-channel MOS memory cell has P+ source (14) and drain (16) regions formed in an N-well (18). A thin tunnel oxide (24) is provided between the well surface and an overlying floating gate (22). In one embodiment, the thin tunnel oxide (24) extends over a substantial portion of the active region (12) of the device. An overlying control gate (26) is insulated from the floating gate (22) by an insulating layer (28). The device is programmed via hot electron injection from the drain end of the channel region (12) to the floating gate (22), without avalanche breakdown, which allows the cell to be bit-selectable during programming. Erasing is accomplished by electron tunneling from the floating gate (22) to the N-well (18) with the source (14), drain (16), and N-well (18) regions equally biased. Since there is no high drain/well junction bias voltage, the channel length of the cell may be reduced without incurring and destructive junction stress.

Description: This invention relates to generally to non-volatile memory devices and specifically the very high density and high speed non-volatile devices. Early semi-conductor memories employed P-channel floating-gate avalanche-injection MOS (FAMOS) devices. These devices are programmed by applying a 35 volt reverse bias across the N-well/drain junction such that high energy electrons generated by avalanche breakdown are injection from the depletion layer to the floating gate. The floating gate is typically erased, i.e., discharged, using UV radiation. In addition to having relatively slow operating speeds, the large reverse bias required for avalanche programming undesirably necessitates the on-chip generation of high voltages and also limits the extent to which the device size may be minimized. As NMOS technology improved, manufacturers were able to take advantage of the faster intrinsic mobility of electrons, as compared with that of holes, and began fabricating N-channel memory devices such as EPROMs and EEPROMs which were faster and required lower programming voltages than FAMOS cells. A floating gate EPROM cell, such as the ETOX Flash EPROM cell manufactured by Intel Corporation of Santa Clara, CA, is charged by the hot injection of electrons from the N-channel/N+ drain junction region without an avalanche breakdown of the junction. Such programming may be realized for instance, by applying 12 volts to the control gate and 7 volts to the drain while grounding the source region. This electrical bias causes electrons to accelerate across the channel region toward the drain. The high energy electrons created near the N-channel/N+ drain junction by the resulting impact ionization are attracted by the more positive control gate voltage and are injected into the floating gate. Erasing is typically accomplished via electron tunneling by applying 12 volts to the source while grounding the control gate. Programming via hot carrier injection allows such an EPROM cell to be bit-programmable and therefore eliminates the need for a select transistor. However, charging the floating gate via hot electron injection from the N-channel/N+ drain region requires high programming currents and, therefore, results in high power consumption. Further, the ETOX Flash ERPOM cell described above suffers from read disturb and may have long term reliability problems as a result of high N+ source/P- substrate junction voltages during erasing. Moreover, erasing by bend to bend tunneling at the N+ source/P- substrate junction results in a high erase current, thereby consuming an undesirable amount of power during erasing. The floating gate of a typical EEPROM memory cell is charged by the tunneling of electrons through a thin oxide layer insulating the floating gate from the source, drain, and channel. For instance, such an EEPROM cell may be erased by applying 20 volts to the control gate while the source, drain, and substrate are grounded. The resultant electric field causes electrons to tunnel through the oxide layer from the source, drain, and channel to the floating gate. Programming, i.e., discharging the floating gate, may be accomplished by holding the control gate at ground while applying 20 volts to the drain, thereby reversing the electric field and pulling electrons from the floating gate to the drain. The EEPROM cell suffers from several drawbacks. First, in order to facilitate electron tunneling, a tunnel window must be opened in a region of the gate oxide primate to the drain. This tunnel opening not only increases the size of the storage cell but also increases fabrication complexity and cost. Second, each EEPROM cell requires its own select transistor in order to be bit addressable during programming and reading. Further, such EEPROM cells require relatively high programming and erasing voltages of approximately 20 volts. The application of such high programming and erasing voltages across P/N junction within the EEPROM cell undesirably limits the amount by which the cell size may be reduced. In addition, high programming and erasing voltages can cause current to leak between ádjacent memory cells, resulting in a decrease in read current and read speed. European Patent Application 0 618 621 to Hayakawa discloses a NAND type EEPROM array for increasing the read current and read speed. However, the device of Hayakawa still utilizes high programming and erasing voltages. More recently, P-channel memory cells have been manufactured and used where programming and erasing of this cell occur in the enhancement mode, such as the P-channel NVRAM cell disclosed in IBM technical disclosure bulletin, Volume 35, number 5, of October 1992, pages 339 to 340 and the P-channel MOS device disclosed in EP patent publication 0 255 489. However, these types of memory cells are programmed in the enhancement mode, therefore the amount of programming control for the cell, in addition to the current available for read operations, are limited. Methods of operating a semiconductor memory cell to programme said cell or to erase said cell are defined in claims 1-4 of the accompanying claims. The invention will now be described by was of example only, with reference to the accompanying drawings, in which: Figure 1 is a cross-sectional view of a memory cell as used in accordance with the present invention; Figures 2A and 2B are cross-sectional views of a portion of the cell of Figure 1 illustrating programming of the cell; Figure 2C is a cross-sectional view of a portion of the cell of Figure 1 illustrating erasing of the cell; Figure 3 is an array employing the cells of Figure 1; Figure 4 is a cross-sectional view of the cell of Figure 1 implemented as part of a NOR cell; Figure 5 is an array employing the cells of Figure 4; Figure 6 is a cross-sectional view of the cell of Figure 1 implemented as part of a Flash cell; Figure 7 is an array employing the cells of Figure 6; Figure 8 is a cross-sectional view of the cell of Figure 1 implemented as part of an EEPROM cell; Figure 9 is an array employing the cells of Figure 8; and Figures 10-13 illustrate the fabrication of a P-channel memory cell in accordance with the present invention. Referring to Figure 1, a flash memory cell 10 has a channel 12 extending between P+ source 14 and P+ drain 16 regions formed in an N- well 18 of a P-substrate 20. Note that although shown in Figure 1 as being formed in N- well 18, cell 10 in other embodiments may be formed in any other suitable underlying N- type structure. A floating gate 22 is insulated from the surface of N- well 18 by a thin tunneling oxide layer 24. In the device shown in Figure 1, tunneling oxide layer 24 has a thickness of approximately 80-130 Å and extends over the entire length of channel 12 and portions of both P+ source 14 and P+ drain 16. It is to be understood, however, that in other embodiments tunneling oxide layer 24 may of other varying lengths, length being in the direction indicated by arrow 25. For instance, in one device (not shown), tunneling oxide layer 24 extends only over a portion of P+ drain 16, wherein the remaining surface of N- well 18 has a thick gate oxide layer formed thereon. A control gate 26 is insulated from floating gate 22 by an insulating layer 28 having a thickness of approximately 180-350 Å. In this device, cell 10 should, in its normal or erased state, have a threshold voltage V T equal to approximately -1.0 to -5.0 V depending upon the particular cell and the configuration of its associated array. The particular value of V T may be altered by conventional ion implanting of dopants into channel region 12. The operation of cell 10 is as follows. To program cell 10, approximately 8 V is applied to P+ source 14 and N- well 18 while drain 16 is held at 2V. The voltage at control gate 26 is ramped up from V cc to approximately 12 V. Acceptable ranges for these programming voltages are listed below in Table 1. Now referring also to Figure 2A, positively charged holes near source 14 and channel 12 are attracted to the less positive voltage on P+ drain 16 and are accelerated through channel region 12 towards P+ drain 16, as indicated by arrow 1. These holes collide with electrons and lattice atoms in a drain depletion region 30, thereby resulting in image ionization, as indicated by star 2. The high energy electrons generated from impact ionization, attracted by the positive voltage on control gate 26, are injected from depletion region 30 into floating gate 22, as indicated by arrow 3. The resultant negative charge on floating gate 22 depletes channel region 12 and forces cell 10 into deep depletion. In the preferred embodiment, cell 10 has, in its programmed state, a V T equal to approximately 4 V. The programming voltages mentioned above and listed in Table 1, by effecting such a low channel current PMOS hot electron injection (LCCPHEI) programming, allow cell 10 to be bit-selectable during programming. In a preferred embodiment, cell 10 may be programmed by hot electron injection without a channel current. Referring now to Figures 1 and 2B, approximately 8 V is applied to an N-well 18, approximately 12 V is applied to control gate 26, and approximately 2 V is applied to P+ drain 16. P+ source 14 is at a floating potential. The reverse bias across the P+ drain 16 and N-well 18 junction, combined with the positive voltage coupled to floating gate 22 via control gate 26, creates a sufficiently high electric field in a region 31 near the interface of tunnel oxide layer 24 and depletion region 30 to generate high energy electrons which are injected from region 31 into floating gate 22, as indicated by arrow 3. In this manner, hot electron injection is induced by bend-to-bend tunneling. To erase cell 10, approximately 17 volts is applied to P+ source 14, P+ drain 16, and N- well 18 while control gate 26 is grounded. Acceptable ranges for these erase voltages are listed below in Table 1 under "Erase Option 1". Referring also to Figure 2C, the equal bias voltages applied to P+ source 14, P+ drain 16, and N- well 18 attract electrons stored in floating gate 22 (Figure 2A). Electrons tunnel from floating gate 22 across the entire length of tunneling oxide layer 24 into channel 12, source 14, and drain 16, thereby returning the threshold voltage of cell 10 to that of its erased state. Note that electrons will tunnel from floating gate 22 and thereby erase cell 10 only if the drain 16 voltage is approximately 17 volts. In another embodiment, cell 10 may be erased by applying approximately 8 volts to P+ source 14, P+ drain 16, and N- well 18 and applying approximately -8 volts to control gate 26. Acceptable ranges for such voltages are listed below in Table 1 as "Erase Option 2". The application of Option 2 erase voltages, which results in an erasing of cell 10 in manner identical to that described above with respect to Option 1, allows erasing voltages of only 8 volts to be used without any degradation in performance of cell 10. In this manner, cell 10 allows for High Endurance Selectable Channel (HESC) erasing. Where it is desired to read cell 10, V cc is applied as a read voltage to source 14 and N-well 18. A voltage between 0 and V cc , depending upon the associated array configuration, is applied to control gate 26. A voltage less than V cc is applied to P+ drain 16. Cell 10 will conduct a channel current only if cell 10 is programmed, i.e., only if charge is stored in floating gate 22. Thus, the voltage on floating gate 22 will be lower than the voltage on P+ source 14, P+ drain 16, and N-well 18. Further, when cell 10 is in an erased state, the voltage on floating gate 22 remains lower than the voltage on P+ source 14, P+ drain 16, and N-well 18. As a result, cell 10 does not suffer from read disturb problems characteristic of conventional NMOS memory devices. Note that the voltage on floating gate 22 will be lower than the voltage on P+ source 14, P+ drain 16, and N-well 18 as long as the V t of cell 10, with floating gate 22 uncharged, is less than or equal to approximately -4.5 V and the read voltages shown in Table 1 are utilized. Drain Control gate Source N-well programming (with channel current) 0V to 2V V cc ramped up to 16V floating 5V to 15V programming (without channel current) 0V to 2V 5V to 16V 5V to 15V 5V to 15V erase (option 1) 15V to 22V 0V 15V to 22V 15V to 22V erase (option 2) 3V to 15V (-15V) to (-3V) 3V to 15V 3V to 15V Read Less than VCC 0V to V cc VCC V cc The above-described operation of cell 10 utilizes PMOS characteristics to achieve numerous other advantages over conventional semiconductor memory cells. The characteristic gate current for P-channel devices is approximately 100 times that of N-channel devices. Thus, unlike conventional NMOS memory cells which typically require approximately a 0.5 milli-amp programming current to charge the floating gate, cell 10 requires a programming current of only a few micro-Amps. Requiring a programming current two orders of magnitude smaller than that of conventional NMOS memory cells such as EPROMs not only allows cell 10 to reduce power consumption during programming but also allows for page writing, i.e., to simultaneously write to numerous ones of cells 10 in a row of an associated memory array (not shown). It is known that the channel of conventional NMOS flash memory cells must be of a sufficient length to tolerate the typically high reverse bias voltage across the P-well/N+ drain junction (as well as the resultant high electric field) required during erasing via electron tunneling. As a result, it is difficult to further reduce the size of such conventional cells without incurring destructive junction stress which, in turn, may lead to reliability problems. Since, however, the operation of cell 10 neither requires nor utilizes such high junction biases during erasing (see Table 1), minimizing the channel length of cell 10 is not so limited. This feature allows cell 10 to be fabricated using technology, sub-micron technology, and in particular, technology producing feature sizes less equal to or less than 0.7 µ m. Avoiding such high junction biases during erasing also advantageously results in a more durable and reliable memory cell. Note that as the channel length of an NMOS transistor falls below approximately 0.7 µ m, electron mobility saturates. In PMOS devices, however, hole mobility continues to increase as the channel length decreases below 0.7 µ m and becomes comparable to electron mobility as the gate length is further decreased. Accordingly, minimizing the channel length of cell 10 also advantageously results in a hole mobility comparable to that of electrons, thereby increasing the speed of cell 10. Further, note that when programmed, cell 10 is in deep depletion. This allows for a higher read current and thus for faster read speeds. Cell 10 may be employing in an array configuration a portion of which is shown in Figure 3. The sources 14 of cells 10a-10d are coupled to a common source node CS. The control gate 26 of cells 10 in a row are coupled to a word line for that row, and the drains 16 of cells 10 in a column are coupled to a bit line BL for that column. The bias conditions for programming and reading for instance cell 10a (and for erasing all of cells 10) are provided below in Tables 2A-2D. Cell 10A voltages Drain Source Control Gate N-well Program 0 Floating 4-10V 3.5-7V Erase 3-15V 3-15V -3 to -15V 3-15V Read less than V cc V cc 0 V cc Cell 10B voltages Drain Source Control Gate N-well Program Floating Floating 4-10V 3.5-7V Erase 3-15V 3-15V -3 to -15V 3-15V Read Floating V cc 0 V cc Cell 10C voltages Drain Source Control Gate N-well Program Floating Floating 0 3.5-7V Erase 3-15V 3-15V -3 to -15V 3-15V Read less than V cc V cc V cc V cc Cell 10D voltages Drain Source Control Gate N-well Program 0 Floating 0 3.5-7V Erase 3-15V 3-15V -3 to -15V 3-15V Read Floating V cc V cc V cc The above described cell 10 may be employed as part of a larger NOR memory array. Figure 4 shows a 2-transistor memory cell 30 including a P-channel MOS transistor 32 as the bit line select transistor 32 and cell 10 as the storage transistor. Select transistor 32 includes a P+ source 16 (note that P+ region 16 also serves as drain 16 for cell 10) and a P+ drain 34 formed in N-well 18. Current flow through select transistor 32 is controlled by a gate 36. A bit line BL is coupled to drain 34 of select transistor 32. The electric bias conditions for programming, erasing, and reading cell 30 are summarized below in Table 3. Since cell 30 includes P-channel cell 10 and P-channel select transistor 32, cell 30 realizes all the advantages discussed above with respect to cell 10. When provided as part of a NOR memory array, cell 10, when programmed, operates as a depletion device. Bit line select gate control gate Source N-well programming (with channel-current) 0V 0V vcc ramp up to 16V 5 V to 15V range 5V to 15V range programming (without channel current) 0V 0V 5V to 16V range 5V to 15V range 5V to 15V range erase (option 1) 15V to 22V range 0V 0V 15V to 22V range 15v to 22V range erase (option 2) 3V to 15V range 0V (-15V) to (-3V) range 3V to 15V range 3V to 15V range Read Less than Vcc 0V 0 to Vcc Vcc Vcc Figure 5 shows a portion of a NOR array 40 employing as memory elements cell 30. The sources 14 of each of cells 10 in array 40 are coupled to a common source node CS. In one embodiment P+ sources 14 of cells 10 may be shorted to N-well 18 by N+ pick-up implants (not shown). The drain 34 of each bit line select transistor 32 in a column are coupled to a bit line BL for that column. The control gates 26 of cells 10 in a row are coupled to a control gate line CG for that row, while the gates of bit line select transistors 32 in a row are coupled to a word line WL for that row. Array 40 is bit programmable using low voltages and low current, and may be erased in bulk using low voltages and low current. Note that the control gates 26 of cells 10 may be held at the same potential and thus do not need to be decoded, i.e., the selected and unselected control gates may be held at the same potential. This allows for a simpler design. The preferred bias conditions and acceptable ranges for bias conditions operating NOR array 40 employing cells 30 in accordance with the present invention are listed below in Tables 4A and 4B, respectively, where NOR array 40 is operating on a supply voltage (not shown) V cc . Bit Line Word Line Cell Gate CG C'mon Source N-well selected unselected selected unselected read V cc - 2V Floating 0 V cc V cc -2V V cc V cc erase 8V n/a 0 n/a -8V 8V 8V program 0 8V or floating 0 8V 0V ramped to 12V 8V 8V Bit Line Word Line Cell Gate CG C'mon Source N-well selected unselected selected unselected read less than V cc Floating 0-2V V cc less than V cc V cc V cc erase 3-15V n/a 0 n/a -3 to -15V 3-15V 3-15V program 0 5-15V 0 5-15V 0V ramped to 12V 5-15V 5-15V The above described embodiments may also be employed as part of a larger flash memory array. Figure 6 shows a 2-transistor memory cell 50 including a P-channel MOS transistor 52 as the source select transistor and cell 10 as the storage transistor. Select transistor 52 includes a P+ source 54 formed in N-well 18 and a gate 56. Source 14 of cell 10 serves as a drain for select transistor 52. A bit line BL is coupled to drain 16 of storage cell 10. Since cell 50 includes P-channel cell 10 and P-channel source select transistor 52, cell 50 realizes all the advantages discussed above with respect to cell 10. Figure 7 shows a portion of a Flash array 60 employing as memory elements cell 50. The source 54 of each of source select transistor 52 of cells 10 in array 60 is coupled to a common source node CS. In one embodiment P+ sources 14 of cells 10 may be shorted to N-well 18 by N+ pick-up implants (not shown). The drain 16 of each of cells 10 in a column is coupled to a bit line BL for that column. The gates 56 of source select transistors 52 in a row are coupled to a first word line WL1 for that row. The control gates 26 of cells 10 in a row are coupled to a second word line WL2. Array 60 is bit programmable and may be erased in either bulk or sector modes. In the operation of array 60, both the first word line WL1 and the second word line WL2 voltages need to be decoded. Note that provided as part of a flash memory array, cell 10, when programmed, operates as a depletion device. The preferred bias conditions and acceptable ranges for bias conditions for operating array 60 employing cells 50 in accordance with the present invention are listed below in Tables 5A and 5B, respectively, where array 60 is operating on a supply voltage (not shown) V cc . Bit Line Word Line 1 Word Line 2 CS N-well select unselect select unselect select unselect read V cc -1.5V Float V cc -2V V cc -2V 0 V cc V cc V cc sector erase 8V 0 8V 8V -8V -8V 8V 8V bulk erase 8V 0 0 0 -8V -8V 8V 8V p'gram 0 6V 0 6V ramp from 0 to 10V 0 6V 6V Bit Line Word Line 1 Word Line 2 CS N-well select unselect select unselect select unselect read less than V cc Float less than V cc less than V cc 0 V cc V cc V cc sector erase 3-15V 0 3-15V 3-15V -3 to -15V -3 to -15V 3-15V 3-15V bulk erase 3-15V 0 0 0 -3 to -15V -3 to -15V 3-15V 3-15V p'gram 0 4-12V 0 4-12V ramp from 0 to 10V 0 4-12V 4-12V The above described embodiments may also be employed as part of a larger flash EEPROM memory array. Referring now to Figure 8, a 3-transistor memory cell 70 including storage cell 10 and both P-channel bit line select transistor 32 and P-channel source select transistor 52 which, as discussed earlier are connected to the drain and source, respectively, of cell 10. The drain 34 of bit line select transistor 52 is connected to bit line BL. Cell 70 realizes all the advantages discussed above with respect to cell 10. Figure 9 shows a portion of an array 80 employing as memory elements EEPROM cells 70. The source 54 of each of source select transistor 52 of cells 10 in array 80 is coupled to a common source node CS. The drain of each of bit line select transistors 32 in a column is coupled to a bit line BL for that column. The gates 36 of bit line select transistors 32 in a row are coupled to a first word line WL1 for that row. The control gates 26 of cells 10 in a row are coupled to a control gate line CG. The gates 56 of each of source select transistors 52 in a row are coupled to a second word line WL2 for that row. Array 80 is bit programmable and erasable in either bulk, sector, or bit modes and may be operated using low programming voltages and currents. Each of word lines WL1 and WL2 and control gate line CG may be advantageously held at the same potential and thus do not need to be decorded. Note that cell 10, when programmed, operates as a depletion device. The preferred and acceptable ranges for bias conditions for operating array 80 employing cells 70 in accordance with the present invention are listed below in Tables 6A and 6B, where array 80 is operating on a supply voltage (not shown) V cc . Bit Line Word Line 1 Word Line 2 CG CS N-well select unselect select unselect select unselect read V cc -2V Float 0 V cc 0 0 to V cc V cc -2V V cc V cc erase 8V 0 0 8V 8V 0 -8V 0 8V p'gram 0 8V 0 8V 0 0 or 8V ramp 0 to 12V 8V 8V Bit Line Word Line 1 Word Line 2 CG CS N-well select unselect select unselect select unselect read less than V cc Float 0 V cc 0 less than V cc less than V cc V cc V cc erase 3-15V 0 0 3-15V 3-15V 0 -3 to -15V 0 3-15V p'gram 0 5-15V 0 5-15V 0 0 or 5-15V ramp 0V to 12V 5-15V 5-15V The fabrication of a cell 10 in accordance with the present invention will be discussed below in the context of a larger memory structure 100 which includes, in addition to a plurality of cells 10, a peripheral circuit having NMOS and PMOS transistors. Although the fabrication of cell 10 is described below as a twin-well process, cell 10 may also be fabricated according to an N-well process without departing from the scope of the present invention. Referring now to Figure 10, structure 100 includes a P-type substrate 102 having formed by conventional means therein an N- well 104 and a P- well 106. The resistivity and thickness of N- well 104 and P- well 106 will depend upon the desired characteristics of the devices to be formed therein. Field oxide regions 108 approximately 7500 Å thick and a layer of pad oxide 110 approximately 240 Å thick are formed on a top surface of substrate 102 by any suitable means. A masking layer 112, which may be photo-resist or any other suitable masking material, is formed and then selectively etched using conventional methods to form the pattern shown in Figure 10. N-type dopants such as Arsenic is implanted at an energy of approximately 100 keV (or Phosphorus at 50 keV) and a dosage of approximately 2E13 ions/cm 2 into a portion 111 of N-well 104 which will become in later steps channel 111 of cell 10. Masking layer 112 is then removed by a suitable etchant. After forming a tunnel oxide layer 114 approximately 80-130 Å thick, a poly-silicon layer is deposited over structure 100 and selectively etched to form floating gate 116. An ONO insulating layer 118 is formed and then selectively etched, as indicated in Figure 11, so as to completely overlie floating gate 116. Portions of pad oxide 110 are removed using suitable etching techniques and a double layer of gate oxide 120 approximately having thicknesses of 120 Å and 250 Å, respectively, grown therein. A second poly-silicon layer is deposited and selectively etched to form control gate 122 of cell 10, gates 124 and 126 of PMOS peripheral transistors 10a and 10b, respectively, and gate 128 of NMOS peripheral circuit 10c. Note that PMOS peripheral transistors 10a and 10b and NMOS peripheral transistor 10c are representative of PMOS and NMOS peripheral circuitry, respectively, of cell 10's associated memory array (not shown). Referring now to Figure 12, PMOS cell 10 and PMOS transistors 10a and 10b are masked. N-type dopants such as Phosphorus is implanted at an energy of approximately 40 keV and a dosage of approximately 3E13 ions/cm 2 into P-well 106 to form N- regions 130 and 132 which will serve as source and drain regions, respectively, of NMOS peripheral transistor 10c. This mask is removed. NMOS transistor 10c is then masked and P-type dopants such as BF 2 are implanted at an energy of approximately 60 keV and a dosage of approximately 7E12 ions/cm 2 into N-well 104 to form P-regions 134, 136, 138, and 140. Sidewall oxide spacers 142 are then formed by conventional means on the sides of control gate 122 and gates 124, 126, and 128. PMOS cell 10 and PMOS transistors 10a and 10b are again masked and N-type dopants, which are preferably Arsenic, are implanted at an energy of 80 keV and a dosage of 5E15 ions/cm 2 into P-well 106 to form N+ diffusion regions 130a and 132a, as shown in Figure 13. The PMOS mask is then removed. Structure 100 is again masked and the sidewall spacers 142 on either side of control gate 122 are dipped. This ensures that in a subsequent doping step the source and drain regions of cell 10 will be of a P+ diffusion structure, as opposed to the lightly doped drain (LDD) structure of P-/P+ diffusion region 134/134a. After this mask is removed, NMOS transistor 10c is masked and P-type implants, preferably BF 2 , are implanted at an energy of 50 keV and a dosage of 2E15 ions/cm 2 into N-well 104 to form P+ regions 134a, 136a, 138a, and 140a. Thus, P+ diffusion regions 136a and 138a serves as the source and drain regions, respectively, of cell 10. The N-/N+ diffusion regions 130/130a and 132/132a will serve as the source and drain regions, respectively, of NMOS transistor 10c, P-/P+ diffusion regions 134/134a and 136/136a will serve as the source and drain regions, respectively, of PMOS peripheral transistor 10a, and P-/P+ diffusion regions 138/138a and 140/140a will serve as the source and drain regions, respectively, of PMOS peripheral transistor 10b. The remaining portions of structure 100 may be completed according to well known fabrication techniques. The process described above with respect to Figures 10-13 requires fewer masking steps than do conventional processes used in the fabrication of N-channel memory cells. The source and drain regions of cell 10 may be of the same dopant concentration and depth as the source and drain regions of PMOS peripheral transistors 10a and 10b. Accordingly, a single masking-etching-doping sequence may be used to form the P+ source and P+ drain regions of cell 10 and the P+ source and P+ drain regions of PMOS peripheral transistors 10a and 10b, as described above. The fabrication of an N-channel memory cell requires an additional masking step since the source and drain regions of a conventional N-channel flash cell must be of a different dopant concentration than the source and drain regions of the NMOS peripheral transistors associated therewith. Note that the above-described process may also be used to form cell 10 and associated peripheral transistors 10a to 10c in an N-well structure.

Claims: A method of operating a semiconductor memory cell having an N-type well region (18) having formed therein a P+ source (14), a P+ drain (16), and a channel region (12) extending between said source and said drain; a first insulating layer (24) overlying said well region; a floating gate (22) overlying said first insulating layer; a second insulating layer (28) overlying said floating gate; and a control gate (26) overlying said second insulating layer, said method comprising: programming said cell by applying between approximately 5-15 volts to said P+ source (14) and to said N-type well region (18), applying approximately 0 to 2 volts to said P+ drain (16), and applying a voltage which ramps from a supply voltage to as high as approximately 16 volts to said control gate (26). A method of operating a semiconductor memory cell having an N-type well region (18) having formed therein a P+ source (14), a P+ drain (16), and a channel region (12) extending between said source and said drain; a first insulating layer (24) overlying said well region; a floating gate (22) overlying said first insulating layer; a second insulating layer (28) overlying said floating gate; and a control gate (26) overlying said second insulating layer, said method comprising: programming said cell by applying between approximately 5-15 volts to said N-type well region (18), coupling said P+ source (14) to a floating potential, applying approximately 0 to 2 volts to said P+ drain (16), and applying between approximately 5-16 volts to said control gate (26). A method of operating a semiconductor memory cell having an N-type well region (18) having formed therein a P+ source (14), a P+ drain (16), and a channel region (12) extending between said source and said drain; a first insulating layer (24) overlying said well region; a floating gate (22) overlying said first insulating layer; a second insulating layer (28) overlying said floating gate; and a control gate (26) overlying said second insulating layer, said method comprising: erasing said cell by applying between approximately 15-22 volts to said P+ source (14), to said N-type well region (18), and to said P+ drain (16) and grounding said control gate (26). A method of operating a semiconductor memory cell having an N-type well region (18) having formed therein a P+ source (14), a P+ drain (16), and a channel region (12) extending between said source and said drain; a first insulating layer (24) overlying said well region; a floating gate (22) overlying said first insulating layer; a second insulating layer (28) overlying said floating gate; and a control gate (26) overlying said second insulating layer, said method comprising: erasing said cell by applying between approximately 3-15 volts to said P+ source (14), to said N-type well region (18), and to said P+ drain (16), and applying between approximately -3 to -15 volts to said control gate (26). The method of Claim 1, wherein said cell further comprises a select transistor (32) formed in said N-type well region (18), said select transistor comprising a select gate (36) coupled to a word line, a P+ source coupled to said P+ drain (16) of said cell, and a P+ drain (34) coupled to a bit line, and a channel region extending between said P+ source and said P+ drain of said select transistor, wherein said cell operates on a supply voltage, and wherein said cell is programmed by applying between approximately 5-15 volts to said P+ source (14) and to said N-type well region (18), grounding said word line and said bit line, and applying a voltage which ramps from 0 to approximately 10 volts to said control gate (26). The method of Claim 4, wherein said cell further comprises a select transistor (32) formed in said N-type well region (18), said select transistor comprising a select gate (36) coupled to a word line, a P+ source coupled to said P+ drain (16) of said cell, and a P+ drain (34) coupled to a bit line, and a channel region extending between said P+ source and said P+ drain of said select transistor, wherein said cell operates on a supply voltage, and wherein said cell is erased by applying between approximately 3-13 volts to said P+ source (14), to said N-type well region (18), and to said bit line, grounding said word line, and applying approximately - 3 to -15 volts to said control gate (26). The methods of Claim 1, wherein said cell further comprises a bit line select transistor (32) having a P+ source coupled to said P+ drain (16) of said cell, a P+ drain (34) coupled to a bit line, and a select gate (32) coupled to a first word line; and a source select transistor (52) having a P+ source (54), a P+ drain coupled to said P+ source (14) of said cell, and a gate (56) coupled to a second word line, wherein said structure operates on a supply voltage, and wherein said cell is programmed by applying between approximately 5 to 15 volts to said P+ source (54) of the source select transistor and to said N-type well region (18), grounding said first and second word lines and said bit line, and applying a voltage which ramps from 0 to as high as approximately 16 volts to said control gate (26). The methods of Claim 4, wherein said cell further comprises a bit line select transistor (32) having a P+ source coupled to said P+ drain (16) of said cell, a P+ drain (34) coupled to a bit line, and a select gate (32) coupled to a first word line; and a source select transistor (52) having a P+ source (54), a P+ drain coupled to said P+ source (14) of said cell, and a gate (56) coupled to a second word line, wherein said structure operates on a supply voltage, and wherein said cell is erased by applying between approximately 3-15 volts to said N-type well region (18), to said second word line, and to said bit line, grounding said fist word line and said P+ source (54) of the source select transistor, and applying approximately -3 to -15 volts to said control gate (26).

Inventors: CHANG SHANG-DE T, CHANG, SHANG-DE T.
Applicants: PROGRAMMABLE MICROELECTRONICS, PROGRAMMABLE MICROELECTRONICS CORPORATION
Application year: 1996
Main classification: H01L29
IPC codes: H01L27, H01L29, H01L21, G11C16