MOSFET WITH REDUCED LEAKAGE CURRENT

Abstract: A metal-oxide-semiconductor field effect transistor (MOSFET) with reduced leakage current includes drain and source regions separated by a channel, a drain terminal over a portion of the drain region, a source terminal over a portion of the source region and a gate terminal opposite the channel. An oxide layer is deposited over the remaining portions of the drain and source regions, as well as on the adjacent vertical sides and top edges of the drain, source and gate terminals. A silicide layer is deposited over the gate terminal between the oxide-covered top edges thereof and over the drain and source terminal up to the oxide-covered top edges thereof. With oxide over the drain source regions instead of silicide, parasitic Schottky diodes are avoided, thereby eliminating leakage current due to such parasitic elements. Additionally, the oxide layer over the drain and source regions blocks pldd and nldd diffusions, thereby preventing impingement of the drain and source regions under the gate and adjacent oxide spacers and thereby significantly reducing leakage current due to band-to-band tunneling.

Description: MOSFET WITH REDUCED LEAKAGE CURRENT BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to integrated circuits with metal oxide semiconductor field effect transistors (MOSFETs), and in particular, to MOSFETs with reduced leakage current. 2. Description of the Related Art Integrated circuits (ICs) containing digital, short channel, silicided complementary metal oxide semiconductor (CMOS) and combination bipolar and CMOS (BiCMOS) transistors are seeing increasing use in linear applications. However, whereas digital applications tend to be forgiving with respect to slight variations in voltage levels and charge accumulation or leakage, many linear applications have much more stringent requirements. One linear application in particular which has stringent device requirements is a charge pump for phase lock loop (PLL) circuits. A charge pump requires extremely low leakage since the frequency of the voltage controlled oscillator (VCO) that it drives will vary as leakage causes charging or discharging of the control capacitor between the charge pump and the VCO input. Leakage problems are exacerbated by the fact that the charge pump output components driving the VCO are typically large because of drive, output resistance, operating range and margin requirements. It is becoming increasingly common for leakage current limits to be less than one nanoampere, with total output device widths of 6000 microns (3600 microns for PMOS plus 2400 microns for NMOS). (Further discussion of such charge pump circuits can be found in copending, commonly assigned U.S. Patent Application Serial No. 08/335,091, filed November 7, 1994, and entitled "Cascode Switched Charge Pump Circuit", the disclosure of which is incorporated herein by reference.) Referring to Figure 1, a cross section of a conventional BiCMOS IC using short channel, contactless, silicided devices is shown. This cross sectional view depicts resistors and bipolar, PMOS and NMOS transistors up through the silicidation step in process flow. It can be seen that both the polysilicon and single crystal silicon are silicided. As is well known, the suicide (e.g. titanium suicide, TiSi2) reduces the resistance of the polysilicon gate and single crystal silicon source and drain (e.g. to approximately two ohms per square). However, whereas the reduced polysilicon and single crystal silicon resistance due to the suicide is generally desirable, such silicidation introduces a problem to which some linear applications are particularly sensitive. Where the suicide overlays the P-type source and drain regions, parasitic Schonky diodes are formed in those areas where the source or drain has been consumed by the suicide. These parasitic Schottky diodes which are formed are of the field plate type, due to field oxide walling, and are known to be high leakage devices. Further, an additional problem, albeit somewhat unrelated to the silicide per se, is drain-to-well leakage due to band-to-band tunneling caused by impingement of the source and drain regions under the gate oxide and oxide spacer edges. Accordingly, it would be desirable to have a digital, short channel CMOS or BiCMOS IC having the advantages of silicided polysilicon while also having significantly reduced leakage currents compatible with the stringent device requirements of many linear applications. SUMMARY OF THE INVENTION In accordance with the present invention, a MOSFET with reduced leakage current can be realized which avoids the creation of parasitic Schottky diodes, thereby eliminating leakage current due to such parasitic elements, and further by blocking p+ s/d and n+ s/d diffusions into the drain and source region thereby preventing impingement of the drain and source regions under the gate and adjacent component spacers and thereby significantly reducing leakage current due to band-to-band tunneling. A MOSFET with reduced leakage current in accordance with one embodiment of the present invention includes a semiconductor substrate with drain and source regions separated by a channel, a drain terminal over a portion of the drain region, a source terminal over a portion of the source region and a gate terminal opposite the channel. A first silicide layer is on the drain terminal, a first nonsilicid e.g. oxide, layer covers another portion of the drain region and a second silicide layer is on the gate terminal. In one preferred embodiment of a MOSFET with reduced leakage current in accordance with the present invention, a second nonsilicide, e.g. oxide, layer covers another portion of the source region. In another prefeπed embodiment, the silicide layers over the drain and gate terminals are narrower than the drain and gate terminals and do not extend to at least one of the edges thereof. In yet another preferred embodiment, the source terminal has a third silicide layer which is narrower than the source terminal an does not extend to at least one of the edges thereof. These and other features and advantages of the present invention will be understood upon consideration of the following detailed description of the invention and the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a cross sectional view of a portion of a conventional BiCMOS IC. Figure 2 is a cross sectional view of a portion of a BiCMOS IC with complementary MOSFETs i accordance with one embodiment of the present invention up to the oxidation step in the process flow. Figure 3 illustrates the IC of Figure 2 following the depositing of resist material. Figure 4 illustrates the IC of Figure 3 following the removal of exposed oxide. Figure 5 illustrates the IC of Figure 4 during the implantation step following the removal of the resist material. Figure 6 is a cross sectional view of a portion of a BiCMOS IC with complementary MOSFETs having nested silicide atop the polysilicon gate, source and drain terminals in accordance with one embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION Referring to Figure 2, a cross section of a portion 100 of a BiCMOS IC with complementary MOSFETs 101, 102 in accordance with one embodiment of the present invention is shown at the oxidation step in the process flow. (In a preferred embodiment of the present invention, the process flow is as disclosed in the following U.S. Patents, the disclosures of which are incorporated herein by reference: 4,727,046; 5,079,182; 5,081,518; 5,082,796; 5,107,321; 5,219,784; 5,338,694; and 5,338,696.) The substrate 103 has had the P+ and N+ tubs implanted for the NMOS and PMOS devices, respectively. The P-type lightly doped diffusion (pldd) 108 and N-type lightly doped diffusion (nldd) 110 are in place within the P+ 104 and N+ 106 tubs, respectively. Surrounding these tubs 104, 106, are oxide spacers 112. Forming the drain terminals is a deposit of P+ polysilicon 114. Forming the source terminals are deposits of N+ polysilicon 116, 118. Forming the gate terminals are deposits of N+ polysilicon 120, 122 separated by gate oxides 124, 126 from the channels 121, 123 within the pldd 108 and nldd 110 regions. Deposited over all of these elements is a layer of oxide 128 (e.g. silicon dioxide, S^). Referring to Figure 3, the next step is to deposit resist material 130 over the drain regions 132, 134 and source regions 136, 138 of the NMOS 101 and PMOS 102 devices. Referring to Figure 4, the next step is to remove the oxidation 128 areas overlaying much of the polysilicon 114, 1 16, 118 forming the gate source and drain terminals, as well as over some of the spacer oxide 112. However, portions 140 of the oxide material 128 are left overlapping the top edges of the polysilicon 1 14, 116, 118. In a preferred embodiment of the present invention, this overlap is approximately one-half micron wide (e.g. for a two micron channel). Referring to Figure 5, the resist material 130 (Figure 4) is removed and the normal source/drain implantation 142 is performed. However, due to the presence of the remaining oxide 128, no additional source/drain implantation takes place within the drain 132, 134 and source 136, 138 regions of the pldd 108 and nldd 110 areas of these MOSFETs 101, 102. As should be recognized, this advantageously prevents impingement of source/drain implants beneath the gate oxides 124, 126 and edges of the oxide spacers 112. Accordingly, leakage due to band-to-band tunneling is significantly reduced, if not eliminated. Referring to Figure 6, the next step is to deposit the silicide 144 atop the polysilicon 114, 1 16, 1 18, 120, 122 adjacent and between the ends 140 of the remaining oxide 128. Alternatively, in accordance with the foregoing discussion, MOSFETs in accordance with the present invention can be optimized as desired by removing the oxide 128 from and allowing silicide 1 to form over the source regions which are intended to be grounded within the circuit. From the foregoing, a number of advantages of a MOSFET in accordance with the present invention should be evident. For example, by retaining regions of silicide 144 nested within the oxide 128, reduced polysilicon resistance is maintained. Further, by preventing formation of silicide on the surfaces of the single crystal silicon, i.e. those areas overlying the drain 132, 134 and source 136, 138 regions, no parasitic Schottky diodes are formed, thereby eliminating leakage components due to such elements. Further still, by retaining the oxide 128 over the drain 132, 134 and source 136, 138 region and thereby blocking the source/drain implantation, impingement of source/drain implants is prevented from occurring beneath the gate oxides 124, 126 and edges of the spacer oxides 112, thereby significa reducing, if not eliminating, leakage due to band-to-band tunneling. Moreover, only mask changes are needed for fabricating MOSFETs in accordance with the present invention, i.e. no material changes in process flow per se are required. Various other modifications and alterations in the structure and method of operation of this invention will be apparent to those skilled in the art without departing from the scope and spirit of the invention. Although the invention has been described in connection with specific preferred embodime it should be understood that the invention as claimed should not be unduly limited to such specific embodiments. It is intended that the following claims define the scope of the present invention and th structures and methods within the scope of these claims and their equivalents be covered thereby.

Claims: WHAT IS CLAIMED IS: 1. An apparatus including a metal-oxide-semiconductor field effect transistor (MOSFET) with reduced leakage current, said MOSFET comprising: a semiconductor substrate; a drain region within said semiconductor substrate with first and second drain region surfaces; a drain terminal adjacent said first drain region surface with opposing first and second drain terminal surfaces, wherein said first drain terminal surface is adjacent said first drain region surface; a first silicide layer adjacent said second drain terminal surface; a first nonsilicide layer adjacent said second drain region surface; a source region within said semiconductor substrate with first and second source region surfaces; a source terminal adjacent said first source region surface with opposing first and second source terminal surfaces, wherein said first source terminal surface is adjacent said first source region surface; a channel region within said semiconductor substrate between said drain and source regions; a gate terminal with opposing first and second gate terminal surfaces, wherein said first gate terminal surface is disposed near said substrate and opposite said channel region; and a second silicide layer adjacent said second gate terminal surface. 2. An apparatus as recited in Claim 1, further comprising a second nonsilicide layer adjacent said second source region surface. 3. An apparatus as recited in Claim 1, wherein said first silicide layer has a first width, said second drain terminal surface has a second width and said first width is less than said second width. 4. An apparatus as recited in Claim 3, wherein said second drain terminal surface has opposing edges and said first silicide layer is between said opposing edges and does not extend to one thereof. 5. An apparatus as recited in Claim 1, wherein said second silicide layer has a first width, said second gate terminal surface has a second width and said first width is less than said second width. 6. An apparatus as recited in Claim 5, wherein said second gate terminal surface has opposing edges and said second silicide layer is between said opposing edges and does not extend to one thereof. 7. An apparatus as recited in Claim 1, further comprising a third silicide layer adjacent said second source terminal surface. 8. An apparatus as recited in Claim 7, wherein said third silicide layer has a first width, said second source terminal surface has a second width and said first width is less than said second width. 9. An apparatus as recited in Claim 8, wherein said second source terminal surface has opposing edges and said third silicide layer is between said opposing edges and does not extend to one thereof. 10. An integrated circuit including a metal-oxide-semiconductor field effect transistor (MOSFET) with reduced leakage current, said MOSFET comprising: a drain region; a drain terminal disposed on a first portion of said drain region; a first silicide layer disposed on said drain terminal; a first oxide layer disposed on a second portion of said drain region; a source region; a source terminal disposed on a first portion of said source region; a channel region between said drain and source regions; a gate terminal disposed opposite said channel region; and a second silicide layer disposed on said gate terminal. 11. An integrated circuit as recited in Claim 10, further comprising a second oxide layer disposed on a second portion of said source region. 12. An integrated circuit as recited in Claim 10, wherein said drain terminal is wider than said first silicide layer. 13. An integrated circuit as recited in Claim 12, wherein said drain terminal has opposing edge and said first silicide layer is disposed between said opposing edges and does not extend to one thereof. 14. An integrated circuit as recited in Claim 10, wherein said gate terminal is wider than said second silicide layer. 15. An integrated circuit as recited in Claim 14, wherein said gate terminal has opposing edges and said second silicide layer is disposed between said opposing edges and does not extend to one thereof. 16. An integr. i circuit as recited in Claim 10, further comprising a third silicide layer disposed on said source terminal. 17. An integrated circuit as recited in Claim 16, wherein said source terminal is wider than said third silicide layer. 18. An integrated circuit as recited in Claim 17, wherein said source terminal has opposing edges and said third silicide layer is disposed between said opposing edges and does not extend to one thereof. 19. A method of fabricating an integrated circuit including a metal-oxide-semiconductor field effect transistor (MOSFET) with reduced leakage current, said method comprising the steps of: providing an integrated MOSFET which includes: a drain region; a drain terminal, with opposing sides and opposing edges, connected to a first portion of said drain region; a source region; a source terminal, with opposing sides and opposing edges, connected to a first portion of said source region; a channel region between said drain and source regions; a gate terminal, with opposing sides and opposing edges, disposed opposite said channel; depositing an nonsilicide layer on a second portion of said drain region; and depositing a silicide layer on said drain terminal and on said gate terminal. 20. A method as recited in Claim 19, wherein said step of depositing a nonsilicide layer further comprises depositing said nonsilicide layer on a second portion of said source region. 21. A method as recited in Claim 19, wherein said step of depositing a silicide layer on said drain terminal comprises depositing a silicide layer which is narrower than said drain terminal. 22. A method as recited in Claim 21, wherein said step of depositing a silicide layer which is narrower than said drain terminal comprises depositing a silicide layer between said opposing drain terminal edges without extending to one thereof. 23. A method as recited in Claim 19, wherein said step of depositing a silicide layer on said gate terminal comprises depositing a silicide layer which is narrower than said gate terminal. - 7 - BAD ORIGINAL 24. A method as recited in Claim 23, wherein said step of depositing a silicide layer which is narrower than said gate terminal comprises depositing a silicide layer between said opposing gate terminal edges without extending to one thereof. 25. A method as recited in Claim 19, wherein said step of depositing a silicide layer further comprises depositing a silicide layer on said source terminal. 26. A method as recited in Claim 25, wherein said step of depositing a silicide layer on said source terminal comprises depositing a silicide layer which is narrower than said source terminal. 27. A method as recited in Claim 26, wherein said step of depositing a silicide layer which is narrower than said source terminal comprises depositing a silicide layer between said opposing source terminal edges without extending to one thereof.

Inventors: LUICH THOMAS M, LUICH, THOMAS, M.
Applicants: NAT SEMICONDUCTOR CORP, NATIONAL SEMICONDUCTOR CORPORATION
Application year: 1996
Main classification: H01L21
IPC codes: H01L21, H01L29