ATM ADAPTER PORT FOR CONSTANT BIT RATE (CBR) DATA

Abstract: A constant bit rate adapter for use with an ATM switch so that CBR source data of any type can be transmitted via an ATM system. The CBR data is converted into one or more words of an ATM data cell. Clock information for the CBR sources and data type information are also converted to words of an ATM data cell. The words are stored in a shared buffer memory (Buffer Memory) of the ATM switch. When transmission is available, the ATM data cell, including the CBR data, is retrieved from the buffer memory and transmitted. When such ATM data cells are received, they are decoded to recover the CBR data.

Description: ATMADAPTER PORTFORCONSTANTBITRATE (CBR) DATA Related Applications This application is a continuation-in-part of Applicant's co-pending U.S. Pat. application Ser. No. 08/249,792, filed May 25, 1994, for a "Shared Buffer Switching Module", which is a continuation-in-part of Applicant's co-pending U.S. Pat. application Ser. No. 07/766,062, filed September 26, 1991 , for "Channel Allocation System for Distributed Digital Switching Network". The entire disclosure of each patent application is incorporated herein by reference. Background of the Invention Existing ATM (Asynchronous Transfer Mode) switch implementations cover link speeds from Tl up to OC12. Commercially available SAR chips may be used to generate ATM cells from data, and may be presented to a port of the switch. A method for creating cells from constant bit rate inputs is needed to complement these facilities. Chips which build cells from Tl or El bit streams (the COBRA chip from Transwitch for example) are becoming available, but these assume that the bit stream of a single Tl or El is to be transmitted as an AAL1 constant bit rate service, which will be satisfactory for many purposes. There are two bit streams within the Tradenet MX for which this is not satisfactory: the basic rate interfaces of the BRIC card and the MX transmission links themselves. It will also be more cost effective to have a single interface chip to such constant bit rate services which will interface to the shared central buffer ram highway of the proposed switch, rather than requiring the use of chips of the COBRA style of design in series with a switch chip port. An object of this invention is to provide an adapter chip for interfacing a variety of constant bit rate services to the central buffer data bus of an ATM switch using a shared central buffer memory. Definition of Terms AAL = ATM Adaption Layer BAC = Buffer Address Counter BDAS = Buffer Distributor Address Stack BRIC = Basic Rate Interface Card BRI = Basic Rate ISDN Interface BWB = Buffer Word Bins Byte = An eight bit group or entity; this usually signifies a datum, as distinct from an octet, which usually signifies a PCM sample. CBR = Constant Bit Rate: used to identify a service which purports to emulate a physical connection supplying a continuous bit stream. COBRA = A Constant Bit Rate Adapter (chip): a trademark used by Transwitch DACS = Digital Access Control Switch: A trademark used by AT&T to identify a mechanism which breaks down Tl bit streams into their constituent octets, and recombines them into different Tl bit streams. This action is known as "grooming", and is somewhat equivalent to creating permanent virtual circuits in an ATM. MX = Tradenet MX; a trademark of IPC which identifies a voice switch and key system, having very high performance and reliability. Octets = eight bit groups or entities intended to identify both data and PCM samples, often used synonymously with bytes. QPS = Quad Port Switch (chip); one of a set of chips which may be used to construct an ATM switch TDM = Time Division Multiplex VC = Virtual Connection: contains both a virtual path identifier and a virtual circuit identifier. Summary of the Invention An ATM switch can be based on the use of a time division access by a set of ports to a central buffer memory. Incoming cells are assigned to a buffer space in the buffer memory, and are written into it in a series of 4 octet words, one word being transferred for each time slot assigned to the incoming port. Similarly, an outgoing cell is fetched from its buffer by the outgoing port, one 4 octet word at a time, for each time slot access by the port. The chip set for such a switch consists of a quad port switch chip (QPS), an intelligent FIFO chip which serves the outgoing ports of a quad port chip and a buffer control and VC translation control chip. The number of QPS chips and ports in a given switch is selectable, so that an interface adapter card may be constructed using perhaps two (2) QPS chips. One or more of the ports would be used for the cell transmission into and out of the CBR adapter according to this invention, and the other ports on the chips could be used to interface to constant bit rate cell assembly/disassembly chips, or SAR chips for data cell assembly/disassembly. The use of CBR cell assembly/disassembly chips in series with the port chips adds additional cost to a system. The CBR adapter according to this invention is interfaced directly to the central buffer memory bus to provide a more cost effective arrangement. CBR chips, which are connected to an output link directly, and which consequently deliver one cell at a time, are limited to meeting the AAL1 specifications from the ATM Forum, which are designed to serve either one cell per channel, or one VC for all cells which may contain channel sequences from a TDM bit stream. All AAL1 cells are defined to be filled (with 47 PCM octets and a residual time stamp octet), which means 47 channels delay (or almost 6ms) in the case of a single channel per cell using companded PCM and proportionally longer for compressed PCM channels. For basic rate PCM bit streams there are presently no standards, and for proprietary bit streams which have larger then 8 bit PCM channels neither format may be satisfactory. There is thus a need to provide the opportunity for proprietary cell formats in which cells may not always be filled. Moreover, it may be advantageous to be able to place portions of a TDM bit stream into a number of different cells with different VCs. This is accomplished according to this invention by having an adapter port interfacing directly to the cell buffer TDM bus. With such a technique it will be possible to place consecutive 32-bit words from a TDM bit stream into different cell buffers in a "scatter write" style, and even build cells with words from a number of different TDM streams. This may be further extended to disassemble cells and reassemble them with different contents in a different order to perform a DACS style function. Brief Description of the Drawings The foregoing objects and features are achieved as described in the following specification which include the drawings as follows: Figure 1 is a block diagram of an ATM switch with a shared buffer memory and CBR (Constant Bit Rate) adapter chips; Figure 2 is a block diagram showing details of the CBR adapter chip; Figure 3 is a diagram illustrating the byte command format; Figure 4 is a table for the action cycle for a quad port chip; Figure 5 is a table for the action cycles for a CBR (Constant Bit Rate) chip; Figure 5A is a diagram of the AAL1 SAR PDU format; Figure 5B is a diagram of the structure data CS-PDUs; Figure 6 is a diagram illustrating a communication network using ATM reflection switches; Figure 7 is a diagram illustrating another ATM-type communication switching network; and Figure 8 is a diagram illustrating CBR adaptor chips according to the invention interfaced between a telephone system and an ATM network. Figure 9 is a diagram illustrating the concept of providing channel rearrangement and switching in the ATM cell domain. Detailed Description of the Preferred Embodiments Figure 1 is a block diagram illustrating a shared buffer memory ATM switch including CBR (Constant Bit Rate) adaptor chips according to the invention. ATM (Asynchronous Transfer Mode) data cells are received via ATM incoming ports 1 through N. The ATM data cell includes 48 data octets (bytes) plus a header indicating destination and priority, among other things. The header of an incoming cell is translated in the HAL (Header Analysis Logic) to determine the appropriate priority and outgoing port. The BML (Buffer Management Logic) locates a free address in the buffer memory, stores the data portion of the incoming ATM cell at the free memory address and stores the address in an appropriate FIFO (First In First Out) register at the appropriate ATM outgoing port N-l through M. When an outgoing port is free for transmitting, the data cell corresponding to the highest priority address is fetched from the buffer memory, assembled with an appropriate header, and transmitted. Data is transferred to and from the buffer memory in a series of 4-octet words via a 32-bit data bus, one such word being transferred for each time slot assigned to the port. In addition to the ATM incoming and outgoing ports, the switch illustrated in Fig. 1 includes an incoming serial TDM to CBR cell adapter and an outgoing CBR cell to serial TDM adapter. These adapters according to the invention are described in greater detail in Figure 2 and are used to convert CBR data into an ATM format for storage in the buffer memory and for converting data cells retrieved from the buffer memory back into CBR data. An outline of a functional block diagram of an adapter chip according to the invention is shown in Figure 2. The chip interfaces to a variety of serial TDM links which must include the Mitel ST bus, Tl, El, ISDN Primary Rate, and, if possible, T3 and E3. These will be described in more detail hereinafter. In the input port (line to ATM), the line clock must first be extracted, and then used to extract a frame start if it is not provided externally. Both of these are then used in conjunction with a reference clock to generate a residual time stamp for AAL1 as required. The line input stream for each line is written into the related Alignment Buffer (A), and the related line sync pulse used to ensure that all line data from the four ports is frame aligned when it is read out to the Serial to Parallel Buffers (B). The counter reset signal resets both the command counter and the start of frame take off from the Alignment Buffers. Although there are four input ports, only two will be equipped to support T3 or E3 inputs because of the length of the frame alignment buffer for synchronization. This is discussed in more detail hereinafter. The line data is assembled into octets in the Serial to Parallel Buffers (B). These buffers will be two octets deep, so that a new octet may be assembled before the previous one has been taken. Failure to take the first before the second is complete will cause an error condition alarm. Four octet groups are assembled in a set of 32 buffer word bins under the direction of commands from the byte command stack. When a buffer word is full, it will be written into the required position in a cell using the cell buffer address counter in the cell buffer address stack which corresponds to the word buffer to be written. In the Byte Command Stack, as the sequence of bytes or octets in a frame are assembled in the alignment buffers, the Byte Distributor determines the source of the next byte to be loaded into register C, and the destination of the selected byte within the Buffer Word Bins. The three sources for filling register C are (1) the Serial to Parallel Buffers B, (2) the Residual Time Stamp generator, and (3) the Byte Command Stack itself. The words in the Byte Command Stack behave as a program file containing a set of instructions or commands which will control the operation of the input half of the Adapter chip. The format for these instructions is shown in Figure 3. The commands in the Byte Command Stack are used to assemble the incoming octets from the TDM bit streams into cells. This is done this in two steps: (1) First, octets are assembled into 4 octet words in the Buffer Word Bins. To accomplish this commands select the source for each octet in each bin using either a Literal from within the command stack, or OP CODE 000 for octets from the input streams or the Residual Time Stamp Counter. There will be 32 Word Bins. The execution of this command type will take place as soon as the related port serial to parallel buffer has completed a new octet. (2) Full bins are then placed in cells using OP CODE 001 which selects the Address Counter of the required cell buffer in the central buffer memory. There will be 32 of these Address Counters. The commands may be held in a stack within the chip which may be loaded through a microprocessor port, or held in an external command stack. They are accessed as fast as the commands can be executed. The Literals are bytes which can contain values such as voice quiet, zero, or symbols for purposes some of which are identified hereinafter. The Address Counter Registers each contain both an address counter and a register containing a destination cell header. The set of cell counters allows the scatter write of buffer words to a selection of cell buffers, so that a number of ports may collaborate on generating cells for a variety of destinations. The address counters each contain a VC address associated with the counter which is used to cause the switch incoming translator to assign a fresh buffer space when required using a command with OP CODE 010. These cell header values may be loaded through the microprocessor port. Because of the scatter write nature of the cell assembly which may be followed, the cells are not completed in the same orderly manner as cells from an ATM link source. This has two consequences: (1) The buffer addresses of outgoing cells may not be released until the cells are complete, otherwise the outgoing link may try to send an incomplete cell. (2) Requests for new buffer addresses can come in bursts, rather than in a well-defined position in the switch cycles. The normal sequence of actions in an ATM input port and output port are shown in Figure 4. For a CBR port the output port actions of reading the header have no meaning since the cell is going no further, and therefore a new header is not needed. One of these cycles may be used to read the incoming header of the cell which has just been completed so that the output port set may again be generated by the HAL logic for transmitting to the cell pointer FIFOs as the cell is now complete and may be sent. This deals with the first consequence. In order to deal with the second consequence, the number of cycles for the port is doubled as shown in Figure 5. This allows four opportunities for requesting a new header where previously there would have only been one. The opportunities which are not used are no different than having a null cell arrive on a normal port of the Quad Port Chip. The possibility of having two opportunities to fetch new outgoing cells where previously there was only one can be used or ignored as the traffic flow and FIFO usage in the outgoing port dictate. The sequence of the commands in the byte command stack are accessed using the command counter shown in Figure 2. The total number of commands depends on the type of links being serviced, and so the command counter must be reset, using a command for this purpose, when the end of the sequence is reached. The formats for the cells specified by the ATM Forum for AAL1 cells are shown in Figures 5A and 5B. The command sequence depends on the data format being served, and the function to be performed. If a straightforward structured TDM bit stream is being converted to cells, then a command stream long enough to service an odd and even cell sequence will be sufficient. However, if switching is being performed, then the command sequence must be long enough to start with the frame start at the first user location in the first cell and continue until this coincidence occurs again. In each case the sequence numbers and pointer values are generated by the residual time stamp logic block, since it has access to both the clock and the frame boundary information. Some examples are given in Table 1 below: TABLE 1 Command Sequence TDM Stream Frame Size Unswitched Switched Tl - D4 24 127 1009 T# - 28 x Tl plus overhead 127 Because there are four ports, and for non switched operation each port will need 127 commands, the internal command stack will be 512 locations long. To leave plenty of room for future switching requirements, the sequence counter will have the capability of addressing 64K commands, that is, 16 bits. There are four output ports (ATM to line), served by an intelligent FIFO chip, to supply cell buffer addresses. Alternatively, a small amount of cell buffer address FIFO may be included with this chip, since there will only be one priority level (priority 1 for CBR) for all ports on this chip. The Buffer Address Counter (BAC) is used to fetch a cell whenever a port requests one and is able to supply a cell buffer start address. The cell is placed in the One Cell FIFO for that port at the full switch transfer rate. Because this transfer rate is so much faster than the rate at which the serial port can remove it, a single BAC serves all the output ports. There will be twice as many port time slots as would normally be expected for the speed of the external link, so that the single BAC should be able to keep up. The four octet words in the cell FIFO are placed in turn in the Byte Distributor Address Stack (BDAS) and are then distributed in turn according to the address in the BDAS. The possible destinations are: (1) the clock and residual time stamp function; (2) the swing frame buffers; and (3) the "bit bucket" for fill bytes. These values may be loaded through a microprocessor port. In another mode the fill byte may be used to place the remaining three bytes in the swing buffers. The command structure will be similar to that for the input port, and once again there should be 512 locations for the internal stack and addressing capacity for 64K external commands. The AAL1 services for CBR virtual connections must be provided for Tl, El, T3 and E3, and any other speeds below 52Mb/s. and will follow the ATM Forum specifications. To service E3 the BDAS will need at least 1024 locations, the exact number to be determined. This size should be sufficient for Tl and El, since the pattern repeats every 8 cells or 384 bytes. The exact number used will be determined by placing the counter reset bit in the last location. The residual time stamp generator will provide the time stamp, the cell sequence numbers with their protection bits, and the pointer bytes. The CBR adapter according to the invention is capable of servicing interfaces which do not follow the AAL1 specifications. Such interfaces are, for example, the Mitel ST bus for the ISDN Basic rate connections, and internal communication links that may occur in the special direct line communication networks used in the financial community are often referred to as "trader turrets". An example of such a trader turret product is the commercial MX product generally described in U.S. Patent No. 5,255,264 for "Distributed Control Switching Network for Multi-line Telephone Communications" . If the Mitel ST bus data were to be transmitted complete, it would be possible to use the El format for transmission over AALl . However, the various four byte basic rate groups carried by the Mitel bus structure must be capable of being distributed over several different destinations. There are three possible ways of achieving this: (1) El formatting can be used and multicast to all destinations. This will use up to 10 cells per 1.5 frames, and will require the use of a Mitel switch chip at the destination to pick out the relevant BRI groups. This requires a processor to set up the switch at the far end, which would be difficult to control from the transmitter end. (2) Form a cell per destination, and wait for it to fill before sending it. This could introduce up to 1.5ms delay in each direction and would be difficult to unpack at the destination because it looks like a contiguous ST frame, which it is not. The additional round trip delay of 3ms is also unfortunate, since the operation is often time critical. (3) Send one cell per destination per frame, containing only those BRI groups which are required, and leaving the rest of the cell empty. This uses potentially 10 cells per frame, which increases traffic density, but should not be of concern on 25 Mhz links. This later scheme uses the least amount of equipment, and is easiest to control and so is the recommended approach. Accordingly, each BRIC can contain two ST buses and the 10 potential destinations would use one BWB each, and fill the rest of the cell with blanks from the fill byte stack. The management of clocks is to be determined. One configuration example for an MX type trader turret interface to an ATM system is shown in Figure 6, and a second is shown in Figure 7. In both cases the interface between the MX and ATM networks is at the links leaving the Section switches. These links are normally fiber optic, and contain 32 channels with 30 bits per channel at an 8 khz frame rate resulting in a link rate of 7.68 Mhz. Internally in each switch there is a 5:4 code conversion giving 32 channels per frame of 24 bits per channel. The nature of the switch path set up algorithms and the traffic distribution obtains maximum traffic capacity ensuring that each link from a section switch to a reflection switch contains channels destined for each and every other section switch in the system. These channels are then normally re-arranged in a reflection switch to collect together those channels to a particular section switch destination. Such rearrangement of internal channels is not presently contemplated by the ATM community, and so a non-standard approach must be taken to achieve the desired result. There are two methods of achieving this with the adapter according to the preferred embodiment of the invention: (1) Collect channels for a particular destination section switch into cells directly addressed to that destination. (2) Collect channels into cells as in option 1, but in addition, direct the cells to specific ATM links to selected destinations as in Figure 7. Alternatively, channel re-arrangement in the ATM could be provided as a replacement for the reflection switches, as shown in Figure 6. The primary requirement for an ATM interface with the MX is to provide a switch which can be partitioned and scattered globally, without compromising the existing internal network path management mechanisms. The path management mechanisms which need to be considered are conferencing, clocks, and path set-up. As to conferencing, although it is clear that the conferencing technique used in the MX cannot be supported in the switching nodes of an ATM network, the delay for constant bit rate connections should be sufficiently constant that the existing echo cancellation technique would still support the conferencing up to the limit of the delay buffers in the DSPs in the interface cards. If this proves not to be the case, then each section unit must become a conference island. This requires network echo cancelling in each link and so it would be of great benefit if each pair of input and output links were served by a digital signal processor on the adapter chip. It also requires the provision of bridge ports at the MX side of the adapter chip, which may cause some logistic difficulties. As to clocks, the MX has a distributed clock system which encompasses the whole of an MX installation. If the MX is distributed globally, one of the following three possibilities may be required: (1) The clock may be extracted from the incoming links and used to source the MX clock. (2) The clock may be extracted from the incoming links and used as the reference clock for the residual time stamp mechanism. (3) The link interfaces could be treated in the same way as Tls are treated; that is, by providing an elastic buffer function with controlled slips between each section unit and its neighbors connected to the ATM network. As to the path set-up, the interface between the MX and the ATM network is shown in Figure 8. The MX path set command is carried in channel and will be sent to the microprocessor port as a destination from the BDAS (using one of the reserved OP codes). There it may be analyzed by a controller processor in a way similar to the MX controller, and a suitable new value placed in the BDAS. In commercial equipment the MX channels occupy 3 octets. It is therefore convenient to add one fill byte, so that one channel will fill a BWB in the adapter chip. To emulate an MX link, and thus preserve the basic switch path control, a virtual MX connection will be represented by 3 ATM cells. These Cells will be transmitted every MX frame time from the same three buffers. As a consequence the third buffer and cell will only be half full. The existing MX path set command will appear on a hitherto empty channel, and will be routed to the microprocessor port. There it can be collected by the microprocessor which can perform routing actions similar to the MX controller. As a consequence of the mechanisms hereabove described it is possible to be able to place portions of a TDM bit stream into a number of different cells with different VCs. This is accomplished according to this invention by having an adapter port interfacing directly to the cell buffer TDM bus. With such a technique it will be possible to place consecutive 32-bit words from a TDM bit stream into different cell buffers in a "scatter write" style, and even build cells with words from a number of different TDM streams this is illustrated in Figure 9. This may be further extended to disassemble cells and reassemble them with different contents in a different order to perform a DACS style function. Approximate gate count and pinouts for the adapter chip according to the invention are provided in Table 2 below. TABLE 2 Function Gates Repeat # Total Gates Frame Alignment Buffers 7136 X 5 35,680 Serial to Parallel Buffers 96 4 400 Clock Extract 200 4 800 Sync Circuit 200 4 800 Residual Time Stamp 250 4 1,000 Command Counter 160 1 160 Byte Command Stack 33,000 1 33,000 Buffer Word Bins 4,100 1 4,100 Address Counters 3,600 1 3,600 Header Registers 4,100 1 4, 100 Data and Address Buffers 240 2 500 One Cell FIFO 450 4 1,800 Register D 200 4 800 Byte Distributor Stack 33,000 1 33,000 Programmable Counter 160 1 160 Swing Frame Buffers 4,800 4 19,200 Residual Time Stamp 350 4 1 ,400 Bus Cycle Sequencer 400 5 2,000 Miscellaneous Cycle 2,000 1 2,000 TOTAL 144,000 A description of the suggested implementation for each function is provided below in support of the gate estimates given in the table. The Frame Alignment Buffer consists of a shift register having as many bits as are expected in the largest structured element to be serviced, i.e., a T3 frame, which contains 5,592 bits. The first port is the master for sync purposes, and consequently only a few locations, say 8, are needed, while the others need the full length of a frame. Because of the length of a T3 frame, only equip port 2 needs this size buffer, and the MX would be allowed to dictate the size of the remaining two ports. This results in one port of 8 bits, one port of 5592, and two ports of 768 bits, giving a total of 7136 bits in the alignment buffer. There must also be a frame bit counter and a decode to be able to select the position within the frame to select for output to the serial to parallel buffers. The shift register and decode can be done in 5 gate equivalents per bit. The Serial to Parallel buffer consists of two 8 bit registers with shift between, serial in, parallel output. There will be 16 bits at 6 gates per bit, giving 96 bits per port. The Clock Extract and Sync Circuit will utilize approximately 200 gates each. The Residual Time Stamp block contains two functions: clock comparison and pointer generation. The clock comparison is of the order of 100 gates, and the pointer must include a 13-bit counter at 10 gates per bit, giving a total of approximately 250 gates. The Command Counter is a 16-bit counter, at 10 gates per bit, giving 160 gates. The Byte Command Stack has been defined as 512 words of 16 bits each, plus operation decode to 16 bits. Stack words require 4 gates per bit with decode from counter. Function decode requires 16 gates per bit, a total of 512x16x4+ 16x16=34000 approximately. In the Buffer Word bins there are 32 words of 32 bits at 4 gates per bit. This results in approximately 4,100 gates. The Address Counters each have a 12-bit register concatenated with a 4-bit counter. The register is estimated at 4 gates per bit, and the counter at 8 gates per bit giving a total of 112 gates per counter. There are 32 counters giving a total of 3,600 gates approximately. The Header Registers are assigned one per address counter. They contain 32 bits each at 4 gates per bit giving a total of 4, 100 gates approximately. The Data and Address Buffers are provided for access to the central cell buffer pool. Each requires 32 bits for data and 16 bits for address, giving 48 bits at 5 gates per bit for a total of 240 gates each. The One Cell FIFO holds 12 words at 32 bits per word. This FIFO requires 450 gates approximately. Register D is a 32 bit register at 5 gates per bit, giving approximately 200 gates. The Byte Distributor Stack is similar to the byte command stack at 33,000 gates. The Programmable Counter is the same as the command counter at about 160 gates. The Swing Frame Buffers are to provide two complete frames of buffering for each port so that an elastic buffer function can be provided, or, for the MX case, the frames may be assembled from multiple cells by placing the octets out of order according to the distributor commands. Two frames of MX are therefore provided per port, which should be adequate for all rates below 6.2Mb/s. Each pair of swing buffers requires 1,536 bits or approximately 1 ,600 bits. These require 4 gates per bit, giving 4,800 gates per swing buffer pair. The Residual Time Stamp is expected to contain a PLL as well as the equivalent circuitry to the incoming RTS at approximately 350 gates. A Bus Cycle Sequencer (not shown on Figure 2) may be added, and consists of two 32 bit registers with one two-input AND gate for each bit plus a 16 bit counter and some miscellaneous gates. These are per port with a per chip circuit of approximately equivalent complexity. Each of these will require 80 bits at 5 gates per bit, giving 400 gates per instance. The following table (Table 3) itemizes the approximate pin counts. TABLE 3 Interface Pins Repeat # Total TDM Input Ports 4 4 16 TDM Output Ports 4 4 16 Buffer Highway Access [2 ports mux] 48 1 [mux] 48 Command Distributor/Stack and Address 35 1 [mux] 35 Processor Access: 32 data, 8 add. 4 contr 44 1 44 Buffer FIFO Access 14 1 14 Switch Clock 6 1 6 TOTAL Basic 179 Power and Ground @ 15% 28 TOTAL 208 Spare 1 As should be obvious to those skilled in the art, there are numerous variations of the preferred embodiments within the scope of the invention. For example, by looping the output and input serial ports together, a virtual time/space switch can be formed. This allows the redistribution of channels carried on DBR virtual circuits in the same way that a DACS redistributes real channels on real TDM circuits. The invention is more particularly defined in the appended claims.

Claims: Claims We claim: 1. A constant bit rate (CBR) adapter for an ATM switch comprising: means for receiving data from a plurality of CBR sources; means for assembling said CBR source data into one or more words of an ATM data cell; means for assembling reference clock information and CBR data type information into one or more words of an ATM data cell; a shared buffer memory for the ATM switch; means for storing said words in said shared buffer memory to form stored ATM data cells including therein stored CBR data; means for retrieving said stored ATM data cells and transmitting the same. 2. A constant bit rate (CBR) adapter for a shared memory ATM switch comprising: means for receiving data from a plurality of CBR sources; means for assembling said CBR source data into one or more words of an ATM data cell; means for assembling reference clock information and CBR data type information into one or more words of an ATM data cell; a shared buffer memory for the ATM switch; means for storing said words in said shared buffer memory to form stored ATM data cells including therein stored CBR data; means for retrieving said stored ATM data cells and transmitting the same. 3. A constant bit rate (CBR) adapter for an ATM switch according to claim 1 further including: means for decoding received data cells including CBR data to recover the CBR data therein. 4. A constant bit rate (CBR) adapter for a shared memory ATM switch according to claim 2 further including: means for decoding received data cells including CBR data to recover the CBR data therein. 5. All the separate features disclosed in the specification hereof.

Inventors: COTTON JOHN M, COTTON, JOHN, M.
Applicants: IPC INFORMATION SYSTEMS INC, IPC INFORMATION SYSTEMS, INC.
Application year: 1996
Main classification: H04L12
IPC codes: H04L12, H04Q3