COMPUTER SYSTEM WHICH INCLUDES A LOCAL EXPANSION BUS AND A DEDICATED REAL-TIME BUS FOR INCREASED MULTIMEDIA PERFORMANCE

Abstract: A computer system optimized for real-time applications which provides increased performance over current computer architectures. The system includes a standard local bus, such as the PCI bus, and also includes a dedicated real-time bus or multimedia bus. The PCI bus and the multimedia bus are comprised on the motherboard and include connector slots for receiving add-in cards. Multimedia device expansion cards each include two connectors which correspond to the PCI bus and the multimedia bus. Thus multimedia devices such as video cards, audio cards, etc., as well as communications devices, transfer real-time data through a separate bus without requiring arbitration for the PCI bus. The computer suystem of the present invention thus provides much greater performance for real-time applications than prior systems.

Description: Title: Computer System Which Includes a Local Expansion Bus and a Dedicated Real-Time Bus for Increased Multimedia Performance BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a computer system which includes a local expansion bus such as the Peπpheral Component Interconnect (PCI) bus and which also includes a separate real-time bus for use by multimedia and communication devices coupled to the PCI bus. thereby increasing multimedia and real-time application performance Description of the Related Art Computer architectures generallv include a plurality of devices interconnected by one or more various buses For example, modern computer systems typically include a CPU coupled through bridge logic to main memory The bridge logic also typically couples to a high bandwidth local expansion bus. such as the peπpheral component interconnect (PCI) bus or the VESA (Video Electronics Standards Association) VL bus Examples of devices which can be coupled to local expansion buses include video accelerator cards, audio cards, telephony cards SCSI adapters, network interface cards, etc An older type expansion bus is generally coupled to the local expansion bus Examples of such expansion buses included the industry standard architecture (ISA) bus, also referred to as the AT bus, the extended industry standard architecture (EISA) bus, or the microchannel architecture (MCA) bus Various devices may be coupled to this second expansion bus, including a fax/modem sound card, etc Personal computer systems were originally developed for business applications such as word processmg and spreadsheets, among others However, computer systems are currently being used to handle a number of real time applications, including multimedia applications having video and audio components, video capture and playback telephony applications, and speech recognition and synthesis, among others These real time applications typically require a large amount of system resources and bandwidth One problem that has arisen is that computer svstems originally designed for business applications are not well suited for the real-time requirements of modem multimedia applications For example, modern personal computer system architectures still presume that the majority of applications executing on the computer system are non real-time business applications such as word processing and/or spreadsheet applications, which execute primarily on the main CPU In general, computer systems have not traditionally been designed with multimedia hardware as pan of the system, and thus the system is not optimized for multimedia applications Rather, multimedia hardware is typically designed as an add-in card for optional insertion in an expansion bus of the computer svstem wherein the expansion bus is designed for non-realtime applications In many cases, multimedia hardware cards situated on an expansion bus do not have the required access to system memory and other system resources for proper operation For example, a multimedia hardware card situated on the PCI expansion bus must first arbitrate for control ofthe PCI bus before the device can access svstem memor> In addition since the computer system architecture is not optimized for multimedia, multimedia hardware cards generally do not make efficient use of system resources As an example, multimedia hardware cards typically include their own memory in addition to system memory For example, video accelerator cards are typically configured with one to four Megabytes of video RAM Audio cards, video capture cards, and other multimedia cards are also generally configured with dedicated on-board memory This requirement of additional memory adds undesirable cost to the system As multimedia applications become more prevalent, multimedia hardware will correspondingly become essential components in personal computer systems Therefore, an improved computer svstem architecture is desired which is optimized for real-time multimedia and communications applications as well as for non-realtime applications In addition, improved methods are desired for transferring reai-time data to multimedia hardware Applicant is aware of two new graphics standards from the Video Electronics Standards Association (VESA) which are designed to improve digital video transfers in computer systems These two standards are referred to as the VESA advanced feature connector (VAFC) and the VESA media channel (VMC) A third standard has been proposed by Intel and ATI referred to as the shared frame buffer interconnect (SFBI) The VAFC standard is a 32 bit replacement for prior 8 bit VGA connectors which supports video at much higher resolutions and in better color The VMC standard also offers a 32 data path and suppoπs up to 15 video streams simultaneously The VMC standard comprises a dedicated channel for real-time video, and peripherals can communicate independent without slowing the system CPU The VMC standard also decouples the memory subsystem from the video transfer specification, allowing graphics board manufacturers to offer a variety of boards with differing types of graphics memory The SFBI standard combines frame buffers and memory use by each multimedia svstem into a single shared memory pool The SFBI standard also includes a protocol for arbitrating among devices attempting to access the memory However, one drawback to this standard is that the standard is designed to maintain all of the components on a single board The SFBI standard does not provide an external feature connector unless SFBI cards are connected to another over the host bus In addition, SFBI cards can mclude a VMC or VAFC connector for connecting to a VMC or VAFC card Summarv of the Invention The present invention comprises a computer system and method optimized for real-time applications which provides increased performance over current computer architectures The system includes a standard local bus, such as the PCI bus. and also includes a dedicated real-time bus or multimedia bus The PCI bus and the multimedia bus are comprised on the motherboard and include connector slots for receiving add-in cards Multimedia device expansion cards each include two connectors which correspond to the PCI bus and the multimedia bus Thus multimedia devices such as video cards, audio cards, etc , as well as communications devices, transfer real-time data through a separate bus without requiring arbitration for the PCI bus The computer system of the present invention thus provides much greater performance for real-time applications than prior systems The computer system comprises a motherboard including a CPU coupled through chip set or bridge logic to main memory The bridge logic couples to a local bus such as the PCI bus The motherboard comprises a plurality of PCI expansion bus connector slots connected to the PCI bus for receiving add-in devices The motherboard also includes a real-time expansion bus compnsmg a plurality of connector slots The real-time expansion bus connector slots correspond to respective ones ofthe PCI expansion bus connector slots The computer system fuπher includes one or more modular add-in cards adapted for insertion into the PCI connector slots and the real-time expansion bus slots Expansion cards or add-in cards each include a first edge O 97/10550 PC17US96/10299 connector for mechanically and electrically connecting to a PCI expansion bus slot, and a second edge connector tor mechanically and electrically connecting to a corresponding real-time bus slot Various devices may be connected to the PCI bus. inciuding a video card, sound card. MPEG decoder card, etc In a second embodiment of the invention, the computer system includes a multimedia memory coupled to each of the PCI local expansion bus and the real-time bus One or more multimedia devices may be coupled to the PCI local expansion bus and the reai-time bus Each of these devices accesses the multimedia memory to retrieve necessary code and data to perform respective operations The multimedia devices preferably include an arbitration protocol for accessing the multimedia memory using the real-time bus Therefore, the present invention comprises a novel computer system architecture and method which standardizes a real-time bus with a local expansion bus to increase the performance of real-time peripherals and applications The present invention also provides improved access for real-time devices to a shared local memory O 97/10550 Brief Description of the Drawings A better understanding of the present invention can be obtained when the following detailed description of the preferred embodiment is considered in conjunction with the following drawings, in which Figure 1 is a block diagram of a computer system including a local expansion bus and a real-time bus according to the present invention. Figure 2 is a block diagram of the motherboard ofthe computer system of Figure 1 Figure 3 is a block diagram of an alternate embodiment ofthe computer system of Figure 1. Figure 4 illustrates a modular add-m card including a local expansion bus connector and a real-time bus connector according to the present invention Figure 5 is a block diagram of a computer system including a local expansion bus and a real-time bus and including a multimedia memory according to an alternate embodiment of the present invention, Figure 6 is a block diagram ofthe motherboard of the computer system of Figure 5, Figure 7 illustrates the address space ofthe main memorv and the multimedia memory, and Figure 8 is a flowchaπ diagram illustrating operation ot data transfers from the mam memory to the multimedia memory Detailed Description of the Preferred Embodiment Incoφoration bv Reference PCI Svstem Architecture by Tom Shanley and Don Anderson and available from Mindshare Press, 2202 Buttercup Dr Richardson, TX 75082 (214) 231-2216, is hereby incoφorated by reference in its entirety The Intel Peripherals Handbook, 1994 and 1995 editions available from Intel Coφoration. are hereby incoφorated by reference in their entirety Also, data sheets on the Intel 82430FX PClset chipset also referred to as the Triton chipset, are hereby incoφorated b\ reference in their entirety, including the 82430 Cache Memory Subsystem data sheet (Order No 290482-004), the 82420/82430 PClset ISA and EISA bridge data sheet (Order No 290483-004). and the Intel 82430FX PClset Product Brief (Order No 297559-001 ), all of which are available from Intel Coφoration, Literature Sales, P O Box 7641. Mt Prospect. IL 60056-7641 ( 1-800-879-4683), and all of which are hereby incoφorated by reference in their entirety The Video Electronics Standards Association (VESA) VESA advanced feature connector (VAFC) specification and the VESA media channel (VMC) specification are incoφorated by reference in their entirety The Intel-ATI shared frame buffer interconnect (SFBI) specification is also hereby incoφorated by reference in its entirety Computer Svstem Block Diagram Referring now to Figure 1 a block diagram of a computer system according to the present invention is shown As shown, the computer system includes a central processing unit (CPU) 102 which is coupled tnrough a CPU local bus 104 to a host/PCI/cache bridge or chipset 106 The chipset 106 includes arbitration logic 107 according to the present invention The chipset 106 is preferably similar to the Triton chipset available from Intel Coφoration. including ceπain arbiter modifications to accommodate the real-time bus of the present invention A second level or L2 cache memory (not shown) may be coupled to a cache controller in the chipset, as desired The bridge or chipset 106 couples through a memorv bus 108 to main memory 1 10 The main memory 1 10 is preferably DRAM (dynamic random access memory) or EDO (extended data out) memory, or other types of memory, as desired The chipset logic 106 preferably includes a memory controller for interfacing to the main memory 1 10 and also includes the arbitration logic 107 The chipset logic 106 preferably includes various peripherals, including an inteπupt system a real time clock (RTC) and timers, a direct memory access (DMA) system and ROM/Flash memory (all not shown) Other peripherals (not shown) are preferably comprised in the chipset 106, including communications poπs. diagnostics poπs, command/status registers, and non-volatile static random access memory (NVSRAM) The host/PCI/cache bridge or chipset 106 also interfaces to a local expansion bus 120 In the preferred embodiment, the local expansion bus 120 is the peripheral component interconnect (PCI) bus 120 However, it is noted that other local buses may be used, such as the VESA (Video Electronics Standards Association) VL bus Various types of devices may be connected to the PCI bus 120 The computer system shown in Figure I also includes a real-time bus, also referred to as a multimedia bus 130 The real-time bus 130 preferably includes a 32 or 64 bit data path and may also include address and control poπions In the preferred embodiment, the real-time bus 130 includes only a 32 bit or 64 bit data path and does not include address or control poπions In one embodiment, devices use the PCI bus 120 for addressing and control and use the multimedia or real-time bus 130 tor high speed data transfers One or more PCI devices 142, 144, and 146 are coupled to each of the PCI bus 120 and the real-time bus 130 The PCI devices 142-146 include standard PCI interface circuitry for communicating on the PCI bus 120 One or more of the PCI devices 142-146 also include interfaces to the real-time bus 130 The PCI devices 142-146 use the real-time bus 130 to communicate data between the respective devices As described fuπher below, one or more of the PCI devices 142-146 are comprised on modular expansion cards adapted for inseπion into respective slots of each ofthe real-time bus 130 and PCI bus 120 In one embodiment, arbitration logic 149 is coupled to the real-time bus 130 and performs arbitration for the devices 142 - 146 on the bus 130 In this embodiment, the PCI devices 142 - 146 provide request signals on the real-time bus 130. and the arbitration logic 149 grants bus access according to a desired arbitration method Alternatively, the arbitration logic 149 is not included, and the PCI devices 142 - 146 use the PCI bus arbitration to gam control ofthe real-time bus 130 The PCI devices 142- 146 may be any of various types of input/output devices, including multimedia devices and communication devices For example, the PCI devices 142-146 may comprise video accelerator or graphics accelerator cards, video playback cards, MPEG decoder cards, sound cards, network interface cards, SCSI adapters for interfacing to various input/output devices, such as CD-ROMS and tape drives, or other devices as desired Thus, the PCI devices 142- 146 communicate with each other via the PCI bus 120 and also communicate with the CPU and main memory 1 10 via the PCI bus 120. as is well known in the aπ The PCI devices 142-146 also communicate data between each other using the real-time bus or multimedia bus 130 When the PCI devices 142- 146 communicate using the real-time bus 130. the devices are not required to obtain PCI bus mastership and they do not consume PCI bus cycles O 97/10550 PC17 1 Expansion bus bridge logic 150 may also be coupled to the PCI bus 120. The expansion bus bridge logic 150 interfaces to an expansion bus 152 The expansion bus 152 may be any of varying types, including the industry standard architecture (ISA) bus also referred to as the AT bus the extended industry standard architecture (EISA) bus. or the microchannel architecture (MCA) bus Various devices may be coupled to the expansion bus 152, such as expansion bus memory or a modem (both not shown) Figure 2 - Motherboard Referring now to Figure 2, a block diagram of motherboard 200 of the computer system of Figure 1 is shown As shown, the vaπous devices and buses are preferably comprised on the motherboard 200 The motherboard 200 comprises the CPU 102, the chipset logic 106. the main memory 1 10. the PCI bus 120, and the real-time or multimedia bus 130 In one embodiment, the PCI devices (real-time devices) 142 - 146 are also comprised on the motherboard 200 In the preferred embodiment, as discussed below, the PCI devices 142 - 146 are modular expansion cards adapted for inseπion into connector slots located on the motherboard 200 The motherboard 200 also includes a plurality of PCI bus connector slots 122 which are electrically connected to the PCI bus 120 The connector slots 122 are adapted for receiving a corresponding or mating edge connector of an expansion card that is adapted for inseπion into the PCI connector slots 122 The motherboard 200 also includes a plurality of real-time bus connector slots 132 which are adapted to receive corresponding or mating edge connectors of expansion cards As shown, each of the multimedia bus connector slots 132 conesponds to a respective one of at least a subset of the PCI bus connector slots 122 In one embodiment, the motherboard 200 includes a first plurality of PCI bus connector slots 122 and a second lesser plurality of multimedia bus connector slots 132 Figure 4 - Expansion Card Referring now to Figure 4. an expansion card or add-in card 400 is shown, which comprises one ofthe PCI devices 142- 146 As shown a PCI expansion card 400 according to the present invention includes a PCI bus connector 402 which is adapted for inseπion into a PCI expansion bus connector slot 122 for electrically coupling to the PCI bus 120 The adapter card 400 also includes a real-time bus connector 404 according to the present invention which is adapted tor inseπion into connector slot 132 ofthe real-time bus 130 Thus, one or more of the PCI devices 142-146 are comprised on a modular expansion card 400 mcludmg PCI bus connector 402 and real-time bus connector 404 This configuration allows for more modular and upgradeable expansion options in the computer system This also provides the benefits ofa PCI local expansion bus coupled with a real-time bus 130 for additional data bandwidth and multimedia real-time data transfer capabilities The present invention is also backwards compatible with existing PCI devices For example, existing prior aπ PCI devices include PCI bus connector 402 but do not include a real-time bus connector 404 These prior aπ PCI devices are simply inseπed into a respective PCI expansion slot 122, and the corresponding real-time connector slot 132 is not used for that respective PCI expansion slot 122 Thus, the computer svstem motherboard 200 shown in Figure 2 may receive prior aπ PCI devices or may receive new expansion cards 400 according to the present invention which include both a PCI bus connector 402 and real-time bus connector 404 Figure 3 - Alternate Embodiment Referring now to Figure 3, an alternate embodiment of the computer system of Figure 1 is shown In the embodiment of Figure 3, chipset logic 106A is connected to both the local expansion bus 120 as well as real-time bus 130A In this embodiment, the real-time bus 130A may be different from the real-time bus 130 shown in Figure 1 to accommodate CPU accesses through the chipset logic 106A to the real-time bus 130A, and also to accommodate peripheral device accesses through the real-time bus I 30A and chipset logic 106A to main memory 1 10 Also, multimedia devices 142A - 146A which are coupled to the PCI bus 120 and the real-time bus 130A may be different from the multimedia devices 142 - 146 in Figure 1 to accommodate accesses through the real-time bus 130A to main memory 1 10 Thus, in this embodiment, the chipset logic 106A can communicate directly to the PCI bus 120, and can aiso communicate directly with the real-time bus 130 This facilitates operation of the CPU 102 communicating with the PCI devices 142A - 146A through both the PCI bus 120 and the real-time bus 130 A In addition, one or more of the PCI devices 142-146 can use the real-time bus 130A to interface through the chipset logic 106A to the main memory 1 10 as desired In this embodiment, the arbitration logic 149 is preferably not included, and arbitration logic 107 A in the chipset 106A preferably performs arbitration for both the PCI bus 120 and the real-time bus 130 Figure 5 - Multimedia Memorv Embodiment O 97/10550 PCΪ7US96/1029 Referring now to Figure 5. a block diagram of the computer system according to an alternate embodiment of the present invention and including a multimedia memory 160 is shown The computer system of Figure 5 is similar to the computer system of Figure 1 However, the computer system of Figure 5 includes a multimedia memory 160 coupled to each of the PCI bus 120 and to the real-time bus 130 In the following description, elements which are identical to elements previously descπbed include the same reference numerals for convenience As shown, the computer system includes a central processing unit (CPU) 102 which is coupled through a CPU local bus 104 to a host/PCI/cache bridge or chipset 106B The chipset 106B includes arbitration logic 107B according to the present invention The chipset 106B is preferably similar to the Triton chipset available from Intel Coφoration. including ceπain arbiter modifications to accommodate the real-time bus I 30B and the multimedia memory 160 of the present invention A second level or L2 cache memory (not shown) may be coupled to a cache controller in the chipset, as desired The bridge or chipset 106B couples through a memory bus 108 to mam memory 1 10 The main memory 1 10 is preferably DRAM (dynamic random access memory) or EDO (extended data out) memory, or other types of memory, as desired The chipset logic 106B preferably includes a memory controller for interfacing to the main memory 1 10 and also includes the arbitration logic 107B The chipset logic I06B preferably includes a direct memory access (DMA) system or engine 164 which performs various DMA operations The chipset logic 106B preferably includes other various peripherals, including an interrupt system, a real time clock (RTC) and timers, and ROM/Flash memory (all not shown) Other peripherals (not shown) are preferably comprised in the chipset 106B, including communications poπs. diagnostics poπs, command/status registers, and non-volatile static random access memory (NVSRAM) The host/PCI/cache bridge or chipset 106B interfaces to a local expansion bus 120 In the preferred embodiment, the local expansion bus 120 is the peripheral component interconnect (PCI) bus 120 However, it is noted that other local buses may be used, such as the VESA (Video Electronics Standards Association) VL bus Various types of devices may be connected to the PCI bus 120 The computer system shown in Figure 5 also includes a real-time bus. also referred to as a multimedia bus 130B The real-time bus 130B preferably includes a 32 or 64 bit data path and may also include address and control poπions The real-time bus 130B may be identical to either the real-time bus 130 shown in Figure 1 or the real-time bus 130 A shown in Figure 1 Alternatively, the real-time bus 130B includes various address and control signals for accessing the multimedia memory 160 Multimedia memory 160 is coupled to each ofthe PCI bus 120 and the real-time bus I30B In the embodiment of Figure 5, the multimedia memory 160 is preferably dual poπed memory In this embodiment, a first poπ of the memory 160 couples to the PCI bus 120 The second poπ ofthe multimedia memory 160 couples to the real-time bus 30B The multimedia memory 160 preferably comprises high speed dual poπed VRAM (video random access memory), or dual poπed DRAM (dynamic random access memory) The multimedia memory 160 may also comprise SRAM (static random access memory) or EDO (extended data out) DRAM The computer system preferably includes a dual poπ DRAM memory controller 162 for controlling the dual poπ memory functions ofthe multimedia memory 160 For more mformation on the operation of a dual poπ memory controller, please see the Intel 8207 Dual-Poπ Dynamic RAM Controller Data Sheet (Order No 210463-007). available from Intel Coφoration which is hereby incoφorated by reference In the preferred embodiment, the real-time bus 130B includes only a 32 bit or 64 bit data path and does not include address or control poπions In one embodiment, devices use the PCI bus 120 for addressing and control and use the multimedia or real-time bus 130B for high speed data transfers between each other and also to/from the multimedia memory 160 Thus, in one embodiment, devices use the PCI bus 120 to provide addressing and control signals to the multimedia memory 160 and use the multimedia or real-time bus 130 for high speed data transfers to and from the multimedia memory 160 One or more PCI devices 142B. 144B. and 146B are coupled to each of the PCI bus 120 and the real-time bus 130B The PCI devices 142B - I46B include standard PCI interface circuitry for communicating on the PCI bus 120 The PCI devices 142B - 146B also include interfaces to the real-time bus 130B The PCI devices 142B - 146B use the real-time bus 130B to communicate data between the respective devices As described fuπher below, one or more of the PCI devices 142B - 146B may be comprised on modular expansion cards adapted for inseπion into respective slots of each ofthe real-time bus 130B and PCI bus 120 In one embodiment, arbitration logic 151 is coupled to the real-time bus 130B and performs arbitration for the devices 142B - 146B on the bus 130B In this embodiment, the PCI devices 142B - 146B provide request signals on the real-time bus 130B. and the arbitration logic 151 grants bus access according to a desired arbitration method Alternatively, the arbitration logic 151 is not included, and the PCI devices 142B - 146B use the PCI bus arbitration to gain control ofthe real-time bus 130B The PCI devices I42B - 146B may be any of various types of input/output devices, including multimedia devices and communication devices For example, the PCI devices 142B - I46B may comprise video accelerator or graphics accelerator cards, video playback cards. MPEG decoder cards, sound cards, network interface cards, SCSI adapters for interfacing to various input output devices, such as CD-ROMS and tape drives, or other devices as desired Thus, the PCI devices 142B - 146B communicate with each other via the PCI bus 120 and communicate with the CPU and main memory 1 10 via the PCI bus 120. as is well known in the an The PCI devices I42B - I46B also communicate data between each other and the multimedia memory 160 using the real-time bus or multimedia bus 130B When the PCI devices 142B - 146B communicate using the real-time bus 130B, the devices are not required to obtain PCI bus mastership and they do not consume PCI bus cycles In one embodiment, the PCI devices 142B - I46B communicate with the multimedia memory 160 using either or both of the real-time bus 130B and the PCI bus 120 Expansion bus bridge logic (not shown) may also be coupled to the PCI bus 120 The expansion bus bridge logic interfaces to a secondary expansion bus (also not shown) The expansion bus may be any of varymg types, including the industry standard architecture (ISA) bus. aiso referred to as the AT bus. the extended industry standard architecture (EISA) bus, or the microchannel architecture (MCA) bus Various devices may be coupled to the expansion bus. such as expansion bus memory or a modem (both not shown) In the embodiment of Figure 5. each of the multimedia devices I42B - I46B include PCI interface logic for coupling to the PCI bus 120 and also include real-time bus interface logic for interfacing to the real-time bus 130B Each of the multimedia devices 142B - I46B also include arbitration logic for gaming control of the real-time bus 130 and fuπher include logic which gains access to the multimedia memory 160 Thus, each of the multimedia devices 142b - 146B can gain control of the real-time bus 130B and access the multimedia memory 160 to retrieve desired code and data In the embodiment of Figure 5, the multimedia memory 160 is mapped to the main memory address space and thus comprises a poπion of the main memory address space, as shown in Figure 7 Thus the multimedia memory 160 is available to store non-multimedia data as needed In other words, if the main memorv 1 10 becomes full and additional memory is needed, the CPU 102 can store code and data in the multimedia memory 160 Thus, in the embodiment the multimedia memory 160 is used for real-time or multimedia data and is also used by the CPU 102 as overflow memory space In the embodiment shown in Figure 5. one or more of the multimedia devices 142B - I46B includes at least one DSP engine 210 which preferably performs a multimedia or communications function, such as video and audio processing functions In the preferred embodiment, the DSP engine 210 is a general puφose DSP engine that is programmable to perform either video or audio processing functions as well as other real-time functions In one embodiment, the DSP engine 210 includes one or more ROMs or RAMs which store microcode or instructions corresponding to video and audio processing instructions or commands When programmed as a graphics accelerator, the DSP engine 210 preferably performs video and graphics functions such as polygon rendering and texture mapping, among others When programmed as a sound card, the DSP engine 210 preferably performs audio functions such as MIDI and wavetable synthesis, among others The DSP engine 210 may also be programmed to perform communication functions, such as ISDN connectivity or modem functionality, as desired In the embodiment shown in Figure 5. the chipset 106B preferably includes DMA transfer engine 164 which performs data transfers between the main memory 1 10 and the multimedia memory 160 The DMA transfer engine 164 preferably transfers data from the main memory 1 10 to the multimedia memory 160 contemporaneously with operations performed by the one or more multimedia devices 142B - 146B In one embodiment, the multimedia memory 160 is paπitioned into two or more separate address spaces or buffers, and the DMA engine 164 transfers data from mam memory 1 10 to a first address space or buffer in the multimedia memory 160 while one ofthe PCI devices 142B - 146B accesses commands and data from the other address space or buffer As mentioned above, the main memory 1 10 and the multimedia memory 160 preferably share a common address space Figure 7 illustrates the main memory address space, wherein the multimedia memory 160 comprises pan o the mam memory address space Thus the multimedia memory 160 is available to store non-multimedia data as needed In this embodiment, each of the multimedia devices I42B - 146B and CPU 102 must also arbitrate for access to the multimedia memory 160 The multimedia devices 142B - 146B preferably have priority access to the multimedia memory 160 In one embodiment, a multimedia device simply writes one or more bits to a register in the arbitration logic 107B in the chipset 106B to gain control of the multimedia memory 160. and the CPU 102 is only granted access to the multimedia memory 160 after a ceπain starvation period Computer Svstem Operation Figure 8 is a flowchaπ diagram illustrating operation of the present invention In the preferred embodiment, the main memory 1 10 stores the operating system and applications software as well as driver software, including video drivers and audio drivers The CPU 102 executes applications software and driver software from the main memory 1 10 and generates real-time or multimedia data In the present disclosure, the term "multimedia data" refers to video or graphical data, audio data, telephony data, and other types of real-time or communication data When an application executing on the CPU 102 generates multimedia data, the CPU 102 preferably writes the multimedia data to the main memory 1 10 in step 502 The multimedia data includes data and may include one or more commands that perform operations on the data In an alternate embodiment, the CPU 102 provides the multimedia data directly to the multimedia memory 160. and operation proceeds directly to step 512 The CPU 102 then provides a data structure directly to the DMA engine 164 in the chipset logic 106B in step 504 The data structure comprises location information regarding the multimedia data, including the beginning address of the data, the length or number of bytes of the data, as well as other information Alternatively, the CPU 102 provides the data structure to buffers within the DMA engine 164 The data structure may also include high level instructions or commands regarding the nature or puφose ofthe data In step 506 the DMA engine 164 prioritizes the data structure with other real-time data structures that have already been received Thus the DMA engine 164 intelligently prioritizes received multimedia data structures based on a desired priority scheme and the available resources Thus, the video and audio components of a multimedia presentation may receive a higher priority than a telephony application that can be performed in the background In an alternate embodiment, the DMA engine 164 does not prioritize received data structures or commands, but rather merely acts as a slave and executes received data structures in the order thev are received In step 508 the DMA engine 164 arbitrates for access to the main memory 1 10 This involves asseπing a bus request signal to the arbitration logic 107B in the chipset 106B The DMA engine 164 may also provide a priority byte to the arbitration logic 107B which is used by the arbitration logic 107B in determining the arbitration Once the DMA engine 164 achieves access to main memory 1 10, the DMA engine 164 uses the data structure received from the CPU 102 to access the real-time data from main memory 1 10 and store the data in the multimedia memory 160 in step 510 In one embodiment, the CPU 102 writes video or audio instructions or commands to the main memory 1 10 in conjunction with the corresponding video and/or audio data In this embodiment, the CPU 102 writes only pointer information to the DMA engine 164 which points to the beginning address in main memory 1 10 where the data and commands reside The pointer information includes the beginning address of the data, the length or number of bytes of the data, as well as other information In step 510 the DMA engine 164 uses the pointer information to retrieve the commands and data from main memory 1 10 into the multimedia memory 160 Once real-time or multimedia data and commands have been placed in the multimedia memory 160. either by the CPU 102 or retrieved from main memory 1 10, in step 512 one or more of the multimedia devices 142B - 146B read the commands and data from the multimedia memory 160 and in step 514 perform the necessary graphics and audio processing functions The respective multimedia device 142B - 146B then generates the appropriate video and audio signals to the video and audio poπs in step 516 In one embodiment, the multimedia memory 160 is paπitioned into separate address spaces for commands and data, and the multimedia device retrieves commands trom a first address space and retrieves data from a second address space The CPU 102 preferably writes video and/or audio commands and data to the main memory 1 10 instead of directly to the multimedia memory 160 in order to minimize CPU accesses to the multimedia memory 160 This ensures that the multimedia devices 142B - 146B have full access to the multimedia memory 160 for real-time processing Fuπher. the multimedia devices 142B - 146B retrieve commands and data from the main memory 1 10 only when necessary, and the multimedia devices I42B - I46B are not "locked out" of the multimedia memory 160 due to CPU writes to the multimedia memory 160 In an alternate embodiment, as mentioned above, the CPU 102 writes video and/or audio data and commands directly to the multimedia memory 160 In this embodiment, the CPU 102 executes applications software and driver software from the main memorv 1 10 and writes any associated video and audio data directly to the multimedia memory 160 The driver software aiso writes high level commands directly to the multimedia memory 160 Thus, the video drivers write high level commands to the multimedia memory 160 in a similar manner to current PCI-based graphics acceleration cards In one embodiment, the multimedia memory 160 is separated into two or more address spaces or buffers, and the CPU 102 writes to one address space or buffer while the one or more multimedia devices 142B - 146B accesses commands and data from the other address space or buffer This ensures that the multimedia devices 142B - I46B have uninterrupted access to commands and data in the multimedia memory 160 while also allowing the CPU 102 to directly write real-time commands and data to the multimedia memory 160 Conclusion Therefore, the present invention comprises a novel computer system architecture which increases the performance of real-time applications The computer system includes a PCI local bus and a real-time bus A dedicated multimedia engine is coupled directly to the mam memory, and the multimedia engine includes dedicated multimedia memory which is pan of the mam memory address space This allows the multimedia memory to be used for multimedia data as well as for additional main memory storage Although the system and method of the present invention has been described in connection with the preferred embodiment, it is not intended to be limited to the specific form set foπh herein, but on the contrary, it is intended to cover such alternatives, modifications and equivalents, as can be reasonablv included within the spirit and scope ofthe invention as defined bv the appended claims

Claims: Claims 1 A computer system, comprising a motherboard. a CPU comprised on said motherboard. main memory coupled to the CPU which stores data accessible by the CPU, bridge logic comprised on said motherboard coupled to said CPU and said main memory, wherein said bridge logic includes expansion bus bridge logic, an expansion bus comprised on said motherboard coupled to the expansion bus bridge logic, wherein said expansion bus includes a plurality of data lines and control lines, a plurality of expansion bus connector slots comprised on said motherboard and coupled to said expansion bus for receiving add-in cards, a multimedia bus comprised on said motherboard, wherein said multimedia bus includes a plurality of data lines for transmitting data. a plurality of multimedia bus connector slots comprised on said motherboard and coupled to said multimedia bus for receiving add-in cards, wherein said plurality of multimedia bus slots correspond to at least a subset of said plurality of expansion bus slots, and one or more add-in cards adapted for coupling to said expansion bus connector slots and said multimedia bus connector slots, wherein each of said one or more add-in cards includes a first edge connector for mechanically and electrically connecting to one of said plurality of expansion bus connector slots, and each of said one or more add-in cards fuπher includes a second edge connector for mechanically and electrically connecting to a corresponding one of said plurality of multimedia bus connector slots 2 The computer system of claim 1 , fuπher comprising multimedia bus arbitration logic coupled to said multimedia bus wherein said multimedia bus arbitration logic receives multimedia bus access requests from one or more of said add-in cards and grants multimedia bus access to one of said one or more add-in cards 3 The computer system of claim 2. wherein said multimedia bus is an isochronous bus. wherein said multimedia bus arbitration logic receives multimedia bus bandwidth requests from one or more of said add-in cards and grants said requested amount of multimedia bus bandwidth to one of said one or more add-m cards 4 The computer system of claim 1 , wherein said bridge logic fuπher comprises expansion bus arbitration logic coupled to said CPU and said expansion bus. wherein said expansion bus arbitration logic receives expansion bus access requests from one or more of said add-in cards and grants expansion bus access to one of said one or more add-in cards 5 The computer system of claim 4. wherein said expansion bus arbitration logic is fuπher coupled to said multimedia bus wherein said expansion bus arbitration logic further receives multimedia bus access requests from one or more of said add-in cards and grants multimedia bus access to one of said one or more add-in cards 6 The computer system of claim 1 wherein said one or more add-in cards are coupled to said expansion bus and said multimedia bus wherein said one or more add-in cards communicate multimedia data over said data lines of said multimedia bus 7 The computer system of claim 6. wherein said one or more add-in cards include a peripheral interface add-m card coupled to said expansion bus and said multimedia bus for coupling to an mputyoutput peripheral device, a decoder add-in card coupled to said expansion bus and said multimedia bus for decompressing data, wherein said computer system fuπher comprises a peripheral device coupied to said peripheral interface add-m card, wherein said peripheral device stores data in a compressed format. wherein said peripheral device transmits compressed data to said peripheral interface add-in card, and said peripheral interface add-in card transmits said compressed data over said multimedia bus to said decoder add-in card herein said decoder add-in card decodes said data to produce decoded data The computer system of claim 7. wherein said peripheral device comprises a CD-ROM drive 9 The computer system of claim 7, wherein said peripheral device stores video data in a compressed format wherein said one or more add-in cards fuπher include a video interface add-in card coupled to said expansion bus and said multimedia bus which performs video and graphical functions. wherein said computer system further comprises a video monitor coupled to said video add-in card, wherein said video monitor displays video data in response to signals provided from said video interface add-in card wherein said peripheral device transmits said compressed video data to said peripheral interface add-m card, and said peripheral interface add-in card transmits said compressed video data over said multimedia bus to said decoder add-in card, wherein said decoder add-in card decodes said data to produce decoded data, and wherein said decoder add-in card transmits said decoded data over said multimedia bus to said video interface add- in card wherein said video interface add-in card provides signals to said video monitor and said video monitor displays video data in response to said signals provided from said video interface add-in card 10 The computer system of claim 7 wherein said peripheral device stores audio data in a compressed format wherein said one or more add-in cards further include an audio interface add-in card coupled to said expansion bus and said multimedia bus which performs audio functions wherein said computer system further comprises one or more speakers coupled to said audio add-in card, wherein said one or more speakers generate sound in response to signals provided from said audio interface add-in card. wherein said peripheral device transmits said compressed audio data to said peπpheral interface add-in card, and said peripheral interface add-in card transmits said compressed audio data over said multimedia bus to said decoder add-in card, wherein said decoder add-in card decodes said data to produce decoded data, and wherein said decoder add-in card transmits said decoded data over said multimedia bus to said audio interface add- in card, wherein said audio add-m card provides signals to said one or more speakers, wherein said one or more speakers generate sound in response to signals provided from said audio interface add-in card 1 1 The computer system of claim 1 , wherein said expansion bus is the peripheral component interconnect (PCI) bus 12 The computer system of claim 1 , further comprising at least one add-in card adapted for coupling to one of said expansion bus connector slots, wherein said at least one add-in card includes only said first edge connector for mechanically and electrically connecting to one of said plurality of expansion bus connector slots, wherein said at least one add-in card which includes only said first edge connector is coupled to said expansion bus

Inventors: BARNES BRIAN, GULICK DALE E, HEWITT LARRY, LAMBRECHT ANDY, WEBB MIKE, BARNES, BRIAN, GULICK, DALE, E., HEWITT, LARRY, LAMBRECHT, ANDY, WEBB, MIKE
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1996
Main classification: G06F13
IPC codes: G06F13