METHOD AND APPARATUS FOR TESTING SEMICONDUCTOR DICE

Abstract: A method and apparatus for testing unpackaged semiconductor dice includes a mother board (10) and a plurality of interconnects (12) mounted on the mother board (10) and adapted to establish a temporary electrical connection with the dice (14). The interconnects (12) can be formed with a silicon substrate (20) and raised contact members (16) for contacting the bond pads (22) of a die (14). Alternately the interconnects (16) can be formed with micro bump contact members (16) mounted on an insulating film (74). The mother board (10) allows each die (14) to be tested separately for speed and functionality and to also be burn-in tested in parallel using standard burn-in ovens. In an alternate embodiment testing is performed using a mother board/daughter board arrangement. Each daughter board (82) includes interconnects (12) that allow the dice (14) to be tested individually for speed and functionality. Multiple daughter boards (82) can then be mounted to the mother board (10) for burn-in testing using standard burn-in ovens.

Description: METHOD AND APPARATUS FOR TESTING SEMICONDUCTOR DICE Field of the Invention: This invention relates to semiconductor manufacture and more particularly to an improved method and apparatus for testing unpackaged semiconductor dice. Background of the Invention: Microelectronic packages called "multi chip modules" or "hybrids" are assembled using unpackaged semiconductor dice. Prior to the assembly procedure, each unpackaged die must be tested to measure its quality and reliability. This has led to the development of test procedures suitable for testing unpackaged semiconductor dice. Known-good-die (KGD) refers to an unpackaged die having the same quality and reliability as the equivalent packaged die. Testing includes burn-in testing wherein the dice are heated while the integrated circuits are electrically biased. In addition, the dice are subject to speed and functionality tests to check the performance of the integrated circuits and devices formed on the dice. Among the parameters tested are input and output voltages, capacitance and current specifications. Memory chips are also put through logic tests wherein data storage, retrieval capabilities and response times are measured. For testing and burning-in unpackaged dice, temporary carriers have been used in the manufacturing process in place of conventional single chip packages. This type of carrier typically includes a base for retaining and housing a single die. The carrier also includes an interconnect that allows a temporary electrical connection to be made between an individual die and external test circuitry. Carriers for testing unpackaged dice are disclosed in U.S. Patent No. 4,899,107 to Corbett et al. and U.S. Patent No. 5,302,891 to Wood et al., which are commonly assigned with the present application. This type of carrier allows tests to be performed on an unpackaged die without damaging the die. The bond pads of a die are particularly susceptible to damage during the testing procedures. Although these types of carriers are suitable for testing a singulated unpackaged die, it would be advantageous to be able to test multiple dice at the same time. This would simplify the handling and test procedures and allow testing to proceed without a separate carrier for each die. In addition, it would be advantageous to perform both burn-in, speed and functionality testing using a common test fixture. In view of the foregoing, it is an object of the present invention to provide an improved method and apparatus for test and burn-in of unpackaged dice. It is a further object of the present invention to provide an improved method and apparatus for testing unpackaged dice that permits multiple dice to be tested at the same time. It is a further object of the invention to provide an improved method and apparatus for testing unpackaged dice that are simple, inexpensive and compatible with volume manufacturing processes and equipment. It is yet another object of the present invention to provide a method and apparatus for performing speed and functionality testing as well as burn-in testing of multiple dice with a single test fixture. Other objects, advantages, and capabilities of the present invention will become more apparent as the description proceeds. SUMMARY OF THE INVENTION In accordance with the present invention, an improved method and apparatus for testing unpackaged semiconductor dice are provided. The method, generally stated, includes: forming a mother board with a plurality of interconnects; assembling multiple dice with the interconnects to establish temporary electrical connections for testing; and then testing the dice by applying signals through the mother board and interconnects to the dice. The mother board can be used for speed and functionality testing the dice individually and also as a burn-in board for burn-in testing the dice using standard burn-in ovens. The mother board includes a separate interconnect for each die. A large number of interconnects are attached to the mother board in electrical communication with conductive traces and with an external electrical connector for the entire mother board. The conductive traces on the mother board form circuit paths to each interconnect to allow the dice assembled with the interconnects to be tested. In addition, the conductive traces can be electrically connected to conducting strips that connect multiple dice in parallel to allow bum-in testing using standard bum-in ovens. A force distribution mechanism is associated with each interconnect for securing the dice to the interconnects and biasing these two components together. In an alternate embodiment multiple dice are attached to daughter boards mountable to the mother board. Each die is retained on a daughter board in contact with an interconnect formed on the daughter board. The mother board and daughter board include means for establishing an electrical connection therebetween, and means for securing the daughter boards to the mother board. With this arrangement, the daughter boards can be used for testing the speed and functionality of the dice. Each die on the daughter board can be electrically isolated for speed and functionality. The daughter boards can then be mounted on the mother board for bum-in testing using a standard bum-in oven. In either embodiment, the interconnects are formed with a substrate, such as silicon or ceramic, sized for mating engagement with a die. The substrates include raised contact members for establishing a temporary electrical connection to the bond pads on the die. The raised contact members can be etched into a substrate formed of a silicon and then overlaid with a conductive layer patterned to form conductive traces. Alternately the raised contact members can be formed as microbump contact members on an insulating film patterned with metallic conductive traces. Such a microbump interconnect can be electrically attached to the mother board using techniques similar to those used in tape automated bonding (TAB). The method of the invention broadly stated includes the steps of: forming a mother board; forming conductive traces on the mother board in electrical communication with an external connector; forming an interconnect having raised contact members for contacting contact locations on a semiconductor die; assembling multiple interconnects on the mother board with the raised contact members on the interconnect in electrical communication with the conductive traces on the mother board; forming a force distribution mechanism for biasing each die to an interconnect; assembling the dice, interconnects and force distribution mechanisms together with the raised contact members on the interconnects in electrical communication with the contact locations on the dice; and testing the dice using the mother board. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic plan view of a mother board constructed in accordance with the invention; Figure 2 is an enlarged plan view of a portion of Figure 1 showing an interconnect wire bonded to conductive traces formed on the mother board; Figure 3 is a cross sectional view showing the mother board and an interconnect along with a force distribution mechanism for securing a die to the interconnect for testing; Figure 3 A is a cross sectional view, with parts removed, showing an altemate embodiment mother board wherein the interconnect is mounted on a base that plugs into the mother board; Figure 4 is a cross sectional view showing a raised contact member of an interconnect electrically engaging a bond pad of a semiconductor die; Figure 5 is a partial cross sectional view of an altemate embodiment mother board formed with sockets and electrical clips for mounting the interconnects to the mother board; Figures 6 and 6A are cross sectional views of an altemate embodiment interconnect formed with microbump contact members; Figure 7 is a cross sectional view showing a microbump contact member electrically engaging a bond pad on a semiconductor die; Figure 8 is a schematic plan view of a mother board showing conducting strips for electrically connecting multiple interconnects in parallel for bum-in testing using standard bum-in ovens; and Figure 9 is a schematic plan view of an altemate embodiment mother board adapted for use with daughter boards for testing multiple semiconductor dice. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring to Figure 1, a mother board 10 suitable for practicing the method of the invention is shown. The mother board 10 is formed of an electrically insulating material similar to those used to form printed circuit boards. Suitable materials for the mother board 10 include high temperature glass filled plastics, ceramics and polyimides. A large number of interconnects 12 are mounted to the mother board 10. Each interconnect 12 is adapted to establish an electrical connection with a semiconductor die 14 (Figure 3). As shown in Figure 4, this type of interconnect 12 includes a substrate 20 formed of a material such as silicon or ceramic. These materials have a coefficient of thermal expansion (CTE) that closely matches the CTE for a semiconductor die 14. The interconnect 12 includes raised contact members 16 formed integrally with the substrate 20 using an etching process. The raised contact members 16 are formed with a size and spacing that matches the size and spacing of the bond pads 22 on the die 14. In addition, the raised contact members 16 are formed with projections 18 adapted to penetrate into the bond pads 22 but with a self limiting penetration depth. The projections 18 pierce any native oxide covering the bond pad 22 to establish an ohmic contact. An insulating layer 24, such as SiO 2 , is formed on the substrate 20 of the interconnect 12 including over the raised contact members 16. A conductive layer 26, formed of a highly conductive metal, is formed on the insulating layer 24 over the raised contact members 16. The conductive layer 26 is placed in electrical communication with conductive traces 28 formed on the surface of the substrate 20. As shown in Figure 2, the conductive traces 28 extend to the edges of the interconnect 12 and are formed with bond sites 30. A bond wire 32 is wire bonded to the bond sites 30 to establish an electrical path to the mother board 10. By way of example the conductive layer 26 and conductive traces 28 for the interconnects 12 can be formed by depositing and patterning a highly conductive metal such as aluminum or copper. The bond wires 32 are wire bonded at the opposite end to conductive traces 34 (Figure 2) formed on the mother board 10. The mother board 10 includes a pattern of conductive traces 34 to each interconnect 12 attached to the mother board 10. The conductive traces 34 on the interconnect 12 terminate at an extemal connector 36 (Figure 1) formed on the mother board 10. The extemal connector 36 is formed as a male or female member adapted for mating engagement with a corresponding male or female member (e.g., plug/ socket). This arrangement establishes an electrical path from the bond pads 22 on the die 14, through the raised contact members 16 on the interconnect 12, through the conductive traces 28 on the interconnect 12, through the bond wires 32, through the conductive traces 34 on the mother board 10 and to extemal test circuitry. Alternately, in place of wire bonding this electrical path can to established using a mechanical connection 38 (Figure 4) such as spring clips. The bond wires 32 not only establish an electrical connection between the interconnects 12 and mother board 10 but also help to secure the interconnects 12 to the mother board 10. An adhesive 40 can also be used to secure the interconnects 12 to the mother board 10. Referring now to Figure 3, the die 14 is shown secured to the interconnect 12 during a test procedure. A force distribution mechamsm 42 is associated with each interconnect 12 for biasing the die 14 and the interconnect 12 together. The force distribution mechanism 42 removably attaches to a pair of openings 50 formed on the mother board 10. The force distribution mechanism 42 includes a pressure plate 44, a spring 46 and a bridge clamp 58 for biasing the die 14 against the interconnect 12 with an evenly distributed biasing force. The pressure plate 44 functions to evenly distribute the load applied by the spring 46. In addition, the pressure plate 44 functions to dissipate heat from the die 14 during the test procedures. However, a force distribution mechamsm can also be constructed to function without a pressure plate 44. The spring 46 of the force distribution mechanism 42 is formed of an elastically resilient material such as spring steel. The spring 46 is sized and shaped to exert a predetermined spring force on the pressure plate 44. This force is evenly distributed by the pressure plate 44 over the back surface of the die 14 and biases the die 14 against the interconnect 12. The spring 46 and pressure plate 44 are formed with openings 51 that permit access for an assembly tool. Still referring to Figure 3, the bridge clamp 58 is a flexible structure formed of a resilient material such as steel. The bridge clamp 58 includes mounting tabs 52. During the assembly procedure the mounting tabs 52 are placed through the openings 50 in the mother board 10. The structure of the mounting tabs 52 and the bridge clamp 58 under tensioning from the spring 46 cooperate to secure the bridge clamp 58 to the mother board 10. Another set of tabs 54 can be formed on the bridge clamp 58 to limit the downward movement of the bridge clamp 58. This arrangement functions to secure the die 14 to the mother board 10 and to bias the die 14 and interconnect 12 together with a predetermined force. The bridge clamp 58 also includes downwardly extending tabs 56 for attaching the spring 46 to the bridge clamp 58 by physical contact or a fastening mechamsm such as spot welds. The longitudinal upper edges of the bridge clamp 58 are bent at a 90 degree angle to form stiffener members 58 on either side. In addition, a central opening 60 is formed in the bridge clamp 48 as an access opening for an assembly tool. During the assembly procedure the raised contact members 16 (Figure 4) on the interconnect 12 are aligned with the bond pads 22 on the die 14 using an aligner bonder tool. At the same time an assembly tool is used to secure the bridge clamp 48 to the mother board 10. Referring now to Figure 3 A, an altemate embodiment mother board 10A is shown. In the altemate embodiment mother board 10A, the interconnect 12A is mounted in a base 62 secured to the mother board 10A. The interconnect 12 A is secured to a recess 66 formed in the base 62 using an adhesive. The base 62 includes electrical pins 64 that fit into corresponding holes in the mother board 10A. The base 62 is formed such that the pins 64 are in electrical communication with the bond wires 32 from the interconnect 12A. In addition, the mother board 10A is formed such that the plugged in pins 64 are in electrical communication with the conductive traces 34 formed on the mother board 10A. The altemate embodiment mother board 10A functions substantially the same as the mother board 10 previously described. The base 42 permits the force distribution mechanism 42 to be secured to the base 62 rather than to the mother board 10A. With reference to Figure 5, another altemate embodiment mother board 10B is shown. The mother board 10B includes a socket 68 formed integrally with the mother board 10B for retaining and mounting the interconnects 12B. Each socket 68 has a peripheral configuration that matches but is slightly larger than the peripheral configuration of the interconnects 12B. Each socket 68 includes a plurality of electrical clips 70 for securing the interconnects 12B and establishing an electrical connection with the conductive traces 28B on the interconnects 12B. Each conductive trace 28B formed on the interconnects 12B will have an associated -8- electrical clip 70. The electrical clips 70 are in electrical communication with an extemal connector (not shown) equivalent to the extemal connector 36 (Figure 1) for the mother board 10 previously described. The electrical clips 70 provides an alternative for the wire bonding arrangement previously described and shown in Figure 2 for mother board 10. The electrical clips 70 are formed of a conductive elastic material, such as metal. The electrical clips 70 in addition to establishing an electrical path also function to clamp the interconnects 12B to the mother board 10B. The electrical clips 70 are adapted to pivot as indicated by directional arrow 72 for releasing the interconnects 12B. The electrical clips 70 can be formed integrally with the mother board 10B using injection molding. Alternately a lamination process can be used. The mother board 10B is adapted for use with a force distribution mechanism 42 (Figure 3) as previously described. Referring now to Figures 6, 6 A and 7, another altemate embodiment mother board 10C is shown. In the altemate embodiment, mother board 10C microbump contact members 16C are formed on an interconnect 12C. Microbump contact technology is used for tape automated bonding (TAB). Microbump contacts are commercially available from Nitto Denko America, Inc. and are sold under the trademark ASM AT™. Microbump contacts are also commercially available from Packard-Hughes Interconnect, Irvine, California and are sold under the trademark Gold Dot™. U.S. Patent No. 5,072.289 to Sugimoto et al. describes a method for forming microbump contact members. Rather than being used to provide a permanent connection, the microbump contact members 16C are used in the present case as shown in Figure 7, to establish a non-bonded temporary electrical connection to the die 14. The microbump interconnects 12C include an insulating substrate formed of a rigid material such as silicon or ceramic. A nonconductive and electrically insulating film 74 (e.g., polyimide) is attached to the interconnect 12C using an adhesive 76 (Figure 7). The insulating film 74 has a metallic foil (e.g., Cu) attached thereto. The foil is patterned and etched to form conductive traces 28C. Holes are etched through the insulating film 74 in contact with the conductive traces 28C. The microbump contact members 16C are formed as metal bumps (e.g., Ni, Au, solder, Cu) in contact with the conductive traces 28C. The conductive traces 28C on the microbump interconnect 12C are equivalent to the conductive traces 28 previously described for the interconnect 12 (Figure 2). In the embodiment illustrated in Figure 6, the conductive traces 28C take the place of a portion of the conductive traces 34 (Figure 2) on the mother board 10 previously described. Bond wires 32 as previously described, or tape automated bonding can be used to bond the conductive traces 28C (Figure 7) on the microbump interconnect 12C to the conductive traces 34 on the mother board IOC. Tape automated bonding can be fusible contacts that can be soldered or otherwise bonded to mating connection points using heat, pressure or ultrasonic energy. Conductive adhesive such as z-axis anisotropic adhesives can also be used to provide an electrical connection. During use of the mother board IOC, a force distribution mechanism can be used as previously described, to bias the microbump contact members 16C against the bond pads 22 on the die 14. The adhesive 76 functions as a compressible member to provide compliancy and accommodate height variations between the bond pads 22 and microbump contact members 16C. Figure 6A shows an embodiment wherein the insulating film 74 wraps around the interconnect 12D and establishes an electrical connection between the interconnect 12D and mother board 10D using tape automated bonding or a conductive adhesive. In this embodiment the mother board 10D includes conductive traces (not shown) similar to the conductive traces 34 (Figure 2) previously described for mother board 10. Heat and pressure can be used to fuse microbump contact members formed on the insulating film 72 to conductive traces formed on the mother board 10D. Conductive adhesives such as z-axis anisotropic adhesives can also be used to form an electrical path between the conductive traces on the mother board 10D and the microbump contact members 16C. The function of the mother board 10D is otherwise the same as the mother board IOC. Referring now to Figure 8, another aspect of the mother board 10 (Figure 1) originally described is illustrated. During the manufacture of Known Good Die (KGD), it is necessary to test each die to certify functionality and reliability. Full functionality and reliability testing includes both bum-in and speed testing. A problem occurs because the equipment used for bum-in testing is not suitable for speed and functionality testing. As an example, bum-in ovens manufactured by Micron Systems Integration under the trademark AMBYX include bum-in boards for testing a large number of packaged dice at once. The leads on the packaged dice are connected or plugged into corresponding electrical connectors on the bum- in board. The bum-in boards include a power grid to establish a temporary electrical connection to multiple dice at one time (e.g., 64). The bum-in ovens thus use "shared resources" to test a large number of dice. However, the same resources cannot be used for speed and functionality testing because of the time variables introduced by interconnecting multiple dice. The mother board 10 constructed in accordance with the invention can be used for speed and functionality testing and also for bum-in testing. The mother board 10 can include the interconnects 12 formed as previously described. In addition, the mother board 10 includes connection pads 78 represented by the dots around each interconnect 12. The connection pads 78 permit each die to be accessed separately for speed and functionality testing using separate pogo pin connectors. Pogo pin connectors are manufactured by Pogo Instruments, Inc. Kansas City, Kansas. For bum-in testing removable conducting strips 80 are attached to the mother board 10 for interconnecting all of the interconnects 12 on the mother board 10 in parallel. Such a parallel connection arrangement can be used for bum-in testing the dice using a shared resources bum-in oven. The same mother board 10 can thus be utilized for both full functionality testing and bum-in testing. Referring now to Figure 9, another altemate embodiment mother board 10E is shown. The mother board 10E is adapted for mounting multiple daughter boards 82. Each daughter board 82 includes multiple interconnects 12 mounted as previously described using wire bonding, electrical clips or microbump contacts. In this embodiment the daughter boards 82 can be formed substantially the same as the mother board 10 previously described. The daughter boards 82 each include an electrical connector 84 that plugs into a mating connector on the mother board 10E. This establishes an electrical connection between the daughter boards 82 and mother board 10E. Using the mother board lOE/daughter board 82 arrangement, multiple dice can be loaded onto a daughter board 82 and tested for full functionality. Multiple daughter boards can then be loaded onto the mother board 10E for bum-in testing using standard bum-in equipment. While the invention has been described with reference to certain preferred embodiments, as will be apparent to those skilled in the art, certain changes and modifications can be made without departing from the scope of the invention as defined by the following claims.

Claims: CLAIMS What is claimed is: 1. A method for testing a plurality of unpackaged semiconductor dice comprising: providing a plurality of unpackaged semiconductor dice; forming a first board; forming a plurality of interconnects on the first board, each interconnect having contact members for contacting contact locations on a respective die; placing the dice and interconnects together to form an assembly with the contact locations of each said die positioned in temporary electrical communication with the contact members of a respective said interconnect; and testing the dice by applying signals to the dice through the first board. 2. The method according to claim 1 further comprising electrically isolating each die on the first board and conducting a functionality test of said electrically isolated dice. 3. The method according to claims 1 or 2 further comprising connecting a first plurality of dice in parallel on the first board, and conducting a bum-in test of said first plurality of dice at an elevated temperature. 4. The method according to claim 1 further including forming said interconnects to include contact members comprising raised silicon projections formed on a silicon substrate and covered with a conductive material. 5. The method according to claim 1 wherein the interconnects are formed to comprise a substrate, an insulating film adhesively attached to the substrate and metal microbumps mounted to the insulating film to form the contact members. 6. The method according to claim 5 further including establishing an electrical path between the microbumps and first board by forming first conductive traces on the insulating film and second conductive traces on the first board and electrically connecting the first conductive traces with the second conductive traces using tape automated bonding. 7. The method according to claim 5 further including establishing an electrical path between the microbumps and first board by forming first conductive traces on the insulating film and second conductive traces on the first board and electrically connecting the first conductive traces with the second conductive traces using a conductive adhesive. 8. The method according to claim 1 further including establishing an electrical path between the interconnects and the first board by wire bonding first conductive traces formed on the interconnects to second conductive traces formed on the first board. 9. The method according to claim 1 further including positioning the interconnects in respective bases attached to the first board. 10. The method according to claim 3 further comprising electrically connecting the interconnects in parallel using conducting strips removably attached to the first board. 11. The method according to claim 1 further including forming a conductive path on the first board to an extemal electrical connector with the contact members on the interconnects being in electrical communication with the conductive path. 12. The method according to claim 11 further including wire bonding the contact members to the conductive path to establish an electrical communication. 13. The method according to claim 11 further including interconnecting the contact members to the conductive path by means of an electrical clip. 14. The method according to claim 11 further including forming each force distribution mechanism to include a bridge clamp attachable to the first board and a spring for biasing a said die. 15. The method according to claim 1 further including: forming a plurality of force distribution mechanisms for securing each die to a corresponding interconnect; and assembling the plurality of dice, interconnects and force distribution mechanisms together, with the contact members on the interconnects contacting the contact locations on the dice to establish a temporary electrical connection therebetween. 16. The method according to claim 1 further including forming each interconnect with raised contact members on a silicon substrate. 17. The method according to claim 1 further including forming each interconnect to comprise a substrate, an insulating film adhesively attached to the substrate, micro bump contact members formed on the insulating film and conductive traces in electrical communication with the contact members. 18. The method according to claim 1 further including: duplicating said assembly to form a plurality of assemblies; providing a second board; mounting said assemblies on said second board; forming a conductive path between the contact members on the interconnects of each said assembly and an extemal connector on the second board; and testing the dice by applying electrical signals through the second board to the dice. 19. The method according to claim 18 further comprising forming said contact members to comprise raised silicon projections covered with a conductive material. 20. The method according to claim 18 further including establishing an electrical path between the interconnects and the first boards by wire bonding conductive traces formed on the interconnects to conductive traces formed on the first boards. 21. The method according to claim 18 further comprising forming the contact members on the interconnects to include metal microbumps mounted to an insulating film. 22. The method according to claim 21 further including connecting the microbumps to conductive traces formed on the first boards using tape automated bonding. 23. The method according to claim 18 further including performing full functionality testing on the dice using the assemblies. 24. The method according to claims 18 or 23 further including performing bum-in testing on the dice using the second board. 25. The method according to claim 18 further including biasing the dice against their rejection interconnects using a force distribution mechanism including a bridge clamp attachable to a respective first board and a spring to exert a predetermined biasing force. 26. The method according to claim 1, further including biasing said dice and said interconnects together to effect said temporary electrical communication. 27. The method according to claim 26, wherein said biasing being provided by affixing a plurality of force distribution mechamsms to said first board with a die and its respective interconnect disposed therebetween. 28. An apparatus for testing a plurality of unpackaged semiconductor dice comprising: a first board including an extemal electrical connector; a plurality of interconnects mounted to the first board, each said interconnect including a plurality of contact members for contacting contact locations on a respective die, said contact members in electrical communication with a conductive path formed on the first board to the extemal electrical connector; and a force distribution mechanism for biasing each die to a corresponding interconnect with the contact members on the interconnects contacting the contact locations on the die to establish a temporary electrical connection therebetween for testing the die using the first board, said first board, plurality of interconnects and form distribution mechanism forming a first assembly. 29. The apparatus according to claim 28 wherein the contact members on the interconnects comprise raised silicon projections formed on a silicon substrate and covered with a conductive material. 30. The apparatus according to claim 28 wherein each interconnect comprises a substrate, an insulating film adhesively attached to the substrate and metal microbumps mounted to the insulating film to form the contact members. 31. The apparatus according to claim 30 further including conductive traces on the insulating film, bonded to the conductive path on the first board by . means of tape automated bonding. 32. The apparatus according to claim 30 and further comprising conductive traces on the insulating film, electrically connected to the conductive path on the first board by means of a conductive adhesive. 33. The apparatus according to claim 28 further comprising conductive traces formed on the interconnects and wire bonded to the conductive path on the first board. 34. The apparatus according to claim 28 wherein the interconnects include bases attached to the first board. 35. The apparatus according to claim 28 further including conducting strips removably attached to the first board for electrically connecting the interconnects in parallel. 36. The apparatus according to claim 28 wherein the force distribution mechamsm includes a spring for biasing a respective die and interconnect with a predetermined biasing force. 37. The apparatus according to claim 36 wherein the force distribution mechanism includes a pressure plate for evenly distributing the biasing force across the die. 38. The apparatus according to claim 28 wherein the first board includes sockets and the interconnects are retained within the sockets by electrical clips. 39. The apparatus according to claim 28 further including: a second board including an extemal principal electrical connector; a plurality of second assemblies, each said second assembly being structurally identical to said first assembly, said assemblies being removably mounted to the second board and including a conductive path in electrical communication with the extemal principal electrical connector; and said contact members of each said assembly being in electrical communication with the conductive path formed on the assembly and the extemal principal electrical connector on the second board. 40. The apparatus according to claim 39 wherein the conductive path on the second board includes means for electrically isolating each die. 41. The apparatus as claimed in claim 39 and wherein the conductive path on each of the first boards includes means for electrically connecting the dice positioned on said first board in parallel.

Inventors: AKRAM SALMAN, FARNWORTH WARREN M, HEMBREE DAVID R, WOOD ALAN G, AKRAM, SALMAN, FARNWORTH, WARREN, M., HEMBREE, DAVID, R., WOOD, ALAN, G.
Applicants: MICRON TECHNOLOGY INC, MICRON TECHNOLOGY, INC.
Application year: 1996
Main classification: G01R31
IPC codes: G01R1, G01R31, H01L21