A code sequence generator apparatus for a CDMA modem

Abstract: A CDMA modem includes a modem transmitter having: a code generator which provides an associated pilot code signal and which generates a plurality of message code signals; a spreading circuit which produces a spread-spectrum message signal by combining each of the information signals with a respective one of the message code signals; and a global pilot code generator that provides a global pilot code signal to which the message code signals are synchronized. The CDMA modem also includes a modem receiver having an associated pilot code generator and a group of associated pilot code correlators for correlating code-phase delayed versions of the associated pilot signal with a receive CDM signal to produce a despread associated pilot signal. The code phase of the associated pilot signal is changed responsive to an acquisition signal value until a pilot signal is received. The associated pilot code tracking logic adjusts the associated pilot code signal in phase responsive to the acquisition signal so that the signal power level of the despread associated pilot code signal is maximized. Finally, the CDMA modem receiver includes a group of message signal acquisition circuits, each including a plurality of receive message signal correlators which correlate respective local received message code signal to the CDM signal to produce a respective despread received message signal.

Description: BACKGROUND OF THE INVENTION Providing quality telecommunication services to user groups which are classified as remote, such as rural telephone systems and telephone systems in underdeveloped countries, has proved to be a challenge over recent years. The past needs created by these services have been partially satisfied by wireless radio services, such as fixed or mobile frequency division multiplex (FDM), frequency division multiple access (FDMA), time division multiplex (TDM), time division multiple access (TDMA) systems, combination frequency and time division systems (FD/TDMA), and other land mobile radio systems.Often, these remote services are faced with more potential users than can be supported simultaneously by their frequency or spectral bandwidth capacity. Recognizing these limitations, recent advances in wireless communications have used spread spectrum modulation techniques to provide simultaneous communication by multiple users. Spread spectrum modulation refers to modulating a information signal with a spreading code signal; the spreading code signal being generated by a code generator where the period Tc of the spreading code is substantially less than the period of the information data bit or symbol signal. The code may modulate the carrier frequency upon which the information has been sent, called frequency-hopped spreading, or may directly modulate the signal by multiplying the spreading code with the information data signal, called direct-sequence spreading (DS). Spread-spectrum modulation produces a signal with bandwidth substantially greater than that required to transmit the information signal, and synchronous reception and despreading of the signal at the receiver demodulator recovers the original information. The synchronous demodulator uses a reference signal to synchronize the despreading circuits to the input spread-spectrum modulated signal in order to recover the carrier and information signals. The reference signal can be a spreading code which is not modulated by an information signal. Spread-spectrum modulation in wireless networks offers many advantages because multiple users may use the same frequency band with minimal interference to each user's receiver. Spread-spectrum modulation also reduces effects from other sources of interference. In addition, synchronous spread-spectrum modulation and demodulation techniques may be expanded by providing multiple message channels for a user, each spread with a different spreading code, while still transmitting only a single reference signal to the user. One area in which spread-spectrum techniques are used is in the field of mobile cellular communications to provide personal communication services (PCS). Such systems desirably support large numbers of users, control Doppler shift and fade, and provide high speed digital data signals with low bit error rates. These systems employ a family of orthogonal or quasi-orthogonal spreading codes, with a pilot spreading code sequence synchronized to the family of codes. Each user is assigned one of the spreading codes as a spreading function. Related problems of such a system are: supporting a large number of users with the orthogonal codes, handling reduced power available to remote units, and handling multipath fading effects. Solutions to such problems include using phased-array antennas to generate multiple steerable beams, using very long orthogonal or quasi-orthogonal code sequences which are reused by cyclic shifting of the code synchronized to a central reference, and diversity combining of multipath signals. JP 7-86982 describes an asynchronous pseudo-noise (PN) code sequence generating circuit which generates a plurality of PN code sequences. A feedback type PN code generator generates a master PN code sequence and code converters for each of N channels convert the master PN sequence to a PN code sequence in accordance with a mask pattern. The mask patterns for each channel are stored in the corresponding mask memory. SUMMARY OF THE INVENTION The present invention provides a code sequence generator apparatus according to claim 1. Further preferred aspects are provided according to the dependent claims. In accordance with the present invention, a code sequence generator apparatus generates a plurality of spreading code sequences including a master spreading code sequence. The spreading code sequences having mutual cross correlation within a range, and a mutual code phase relationship. A linear feedback shift register (LFSR) provides tap signals to logic circuitry which in turn produces a feedback spreading code signal, applied to a first stage of the LFSR. The LFSR responds to a sequence of spreading-code sequence bit values. The LFSR sequentially transfers each of a plurality of tap signals from one stage to the next stage and for transfers the feedback spreading code value to the first stage, and each successive one of the tap values of the last stage defines the master spreading code sequence. A second memory responds to a clock signal for providing a repetitive even code sequence having a cross correlation with the master spreading sequence which is within a predetermined range and has an even number of chip spreading values. A plurality of cascade connected feedforward circuits receive the master spreading code sequence and provide a plurality of distinct code sequences. A plurality of code sequence combiners combine respective spreading code sequence with said even code sequence to produce a plurality of relatively long spreading code sequences, with each long spreading code sequence having a greater number of elements than any one of the plurality of spreading code sequences. To generate large families of nearly mutually orthogonal codes used by the CDMA modems, the exemplary modem includes a code sequence generator. The code sequences are assigned to a respective logical channel of the spread-spectrum communication system, which includes In-phase (I) and Quadrature (Q) transmission over RF communication channels. One set of sequences is used as pilot sequences that are transmitted without being modulated by a data signal. The code sequence generator circuit includes a long code sequence generator including a linear feedback shift register, a memory which provides a short, even code sequence, and a plurality of cyclic shift, feedforward sections, each of which provides a respective code sequence in the family of code sequences. The code sequence generator further includes a group of code sequence combiners for combining each generated code sequence with the short, even code sequence to produce a group, or family, of long code sequences having relatively low mutual correlation. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a block diagram of a code division multiple access communication system according to the present invention. Figure 2a is a block diagram of a 36 stage linear shift register suitable for use with long spreadingcode of the code generator of the present invention. Figure 2b is a block diagram of circuitry which illustrates the feed-forward operation of the code generator. Figure 2c is a block diagram of an exemplary code generator of the present invention including the circuit for generating spreadingcode sequences from the, long spreadingcode and the short spreadingcodes. Figure 2d is an alternate embodiment of the code generator circuit including delays to compensate for electrical circuit delays. Figure 3a is a graph of the constellation points of the pilot spreadingcode QPSK signal. Figure 3b is a graph of the constellation points of the message channel QPSK signal. Figure 3c is a block diagram of exemplary circuitry which implements the method of tracking the received spreadingcode phase of the present invention. DESCRIPTION OF THE EXEMPLARY EMBODIMENT An exemplary system which includes a modem according to the present invention provides local-loop telephone service using radio link between one or more base stations and multiple remote subscriber units. In the exemplary embodiment, the radio link is described for a base station communicating with a fixed subscriber unit (FSU), but the system is equally applicable to systems including multiple base stations with radio links to both FSUs and Mobile Subscriber Units (MSUs). Consequently, the remote subscriber units are referred to herein as Subscriber Units (SUs). Referring to Figure 1, in the exemplary system, the Base Station (BS) 101 provides call connection to the local exchange (LE) 103 or other and telephone network switching interface, and includes the Radio Carrier Station RCS (104). One or more RCSs 104, 105, 110 connect to the Radio Distribution Unit (RDU) 102 through the links 131, 132, 137, 138, 139, and the RDU 102 in turn interfaces with the LE 103 by transmitting and receiving call set-up, control, and information signals through telco links 141, 142, 150. The SUs 116, 119 communicate with the RCS 104 through radio links 161, 162, 163, 164, 165. Both the RCS and the SUs include CDMA modems which establish and maintain the radio links. Alternatively, another embodiment of the invention may include several SUs and a "master" SU which functions in much the same was as the RCS to allow communication among the SUs. Such embodiment may or may not have connection to a local telephone network. Although the described embodiment uses different spread-spectrum bandwidths centered around a carrier for the transmit and receive spread-spectrum channels, the present method is readily extended to systems using multiple spread-spectrum bandwidths for the transmit channels and multiple spread-spectrum bandwidths for the receive channels. Alternatively, because spread-spectrum communication systems have the inherent feature that one user's transmission appears as noise to another user's despreading receiver, an embodiment can employ the same spread-spectrum channel for both the transmit and receive path channels. In other words, Uplink and Downlink transmissions can occupy the same frequency band. The spread binary symbol information is transmitted over the radio links 161 to 165 using Quadrature Phase Shift Keying (QPSK) modulation with Nyquist Pulse Shaping in the present embodiment, although other modulation techniques may be used, including, but not limited to, Offset QPSK (OQPSK) and Minimum Shift Keying (MSK). The RCS and the SUs each contain CDMA modems according to the present invention for transmission and reception of telecommunication signals including information signals and connection control signals. A CDMA modem which includes an embodiment of the present invention includes a modem transmitter having: a code generator which provides an associated pilot code signal and which generates a plurality of message code signals; a spreading circuit which combines each of the information signals, with a respective one of the message code signals to generate a spread-spectrum processed message signal; and a global pilot code generator that provides a global pilot code signal to which the message code signals are synchronized. The exemplary CDMA modem also includes a modem receiver having associated pilot code acquisition and tracking logic. The associated pilot code acquisition logic includes an associated pilot code generator and a group of associated pilot code correlators for correlating code-phase delayed versions of the associated pilot signal with a receive CDM signal to produce a despread associated pilot signal. The code phase of the associated pilot signal is changed responsive to an acquisition signal value until a detector indicates the presence of the despread associated pilot code signal by changing the value of the acquisition signal. The associated pilot code signal is synchronized to the global pilot signal. The associated pilot code tracking logic adjusts the associated pilot code signal in phase responsive to the acquisition signal so that the signal power level of the despread associated pilot code signal is maximized. Finally, the CDMA modem receiver includes a group of message signal acquisition circuits. Each message signal acquisition circuit includes a plurality of receive message signal correlators which correlate the local received message code signal with the CDM signal to produce a respective despread received message signal. Referring to Fig. 1, the radio links 161 to 165 incorporate Broadband Code Division Multiple Access (B-CDMA™) as the mode of transmission in both the Uplink and Downlink directions. CDMA (also known as Spread Spectrum) communication techniques used in multiple access systems are well-known. The described exemplary system uses the Direct Sequence (DS) spreading technique. In each modem, one or more CDMA modulators performs the spread-spectrum spreading code sequence generationln addition, the modems generate, for example, a pseudonoise (PN) spreading sequence; and pefrorm complex DS modulation to produce quadrature phase shift keying (QPSK) signals for the In-phase (I) and Quadrature (Q) channels. Pilot signals are generated and transmitted with the modulated signals. The pilot signals of the present embodiment are spreading codes which are not modulated by data. The pilot signals are used for system synchronization, carrier phase recovery, and for estimating the impulse response of the radio channel. Each SU includes a single pilot generator and at least one CDMA modulator and demodulator, called a CDMA modem. Each RCS 104, 105, 110 has a single pilot generator plus sufficient CDMA modulators and demodulators for all the logical channels in use by all SUs. The CDMA demodulator despreads the signal, with appropriate processing to combat or exploit multipath propagation effects. Parameters concerning the received power level are used to generate the Automatic Power Control (APC) information which, in turn, is transmitted to the other end (i.e. from the SU to the RCS or from the RCS to the SU). The APC information is used to control transmit power of the automatic forward power control (AFPC) and automatic reverse power control (ARPC) links. In addition, each RCS 104, 105 and 110 may perform Maintenance Power Control (MPC), in a manner similar to APC, to adjust the initial transmit power of each SU 111, 112, 115, 117 and 118. Diversity combining at the radio antennas of the RCS 104, 105 and 110 is not necessary because CDMA has inherent frequency diversity due to the spread bandwidth. Receivers may include Adaptive Matched Filters (AMFs) (not shown in Figure 1), however, which combine the multipath signals. In the exemplary embodiment, AMFs perform Maximal Ratio Combining. Logical Communication Channels A 'channel' of the prior art is usually regarded as a communications path which is part of an interface and which can be distinguished from other paths of that interface without regard to its content. In the case of CDMA, however, separate communications paths are distinguished only by their content. The term 'logical channel' is used to distinguish the separate data streams, which are logically equivalent to channels in the conventional sense. All logical channels and sub-channels of the present invention are mapped to a common 64 kilo-symbols per second (ksym/s) QPSK stream. Some channels are synchronized to associated pilot codes which are generated in the same way and perform much the same function as the system Global Pilot Code. The system pilot signals are not, however, considered logical channels. Several logical communication channels are used over the RF communication link between the RCS and SU. Each logical communication channel has either a fixed, pre-determined spreading code or a dynamically assigned spreading code. For both pre-determined and assigned codes, the code phase is in synchronism with the Pilot Code. Logical communication channels are divided into two groups: the Global Channel (GC) group includes those channels which are either transmitted from the base station RCS to all the remote SUs or from any SU to the RCS of the base station regardless of the SU's identity, These channels contain for all users and include the channels used by SUs to gain access to message communication channels. Channels in the Assigned Channels (AC) group are those channels which are dedicated to communication between the RCS and a particular SU. The Global Channels (GC) group provides for 1) Broadcast logical channels, which provide point to multipoint services for broadcasting messages to all SUs and paging messages to SUs; and 2) Access Control logical channels which provide point to-point services on global channels for SUs to access the system and obtain assigned channels. An Assigned Channel (AC) group contains the logical channels that control a single telecommunication connection between the RCS and a SU. The functions developed when an AC group is formed consists of a pair of power control logical message channels for each of the Uplink and Downlink connections, and depending on the type of connection, one or more pairs of traffic channels. The Bearer Control function performs the required forward error control, bearer rate modification, and encryption functions. The logical channels which constitute the BC and AC groups are summarized below in Table 1. Logical Channels and sub-channels of the B-CDMA Air Interface Channel name Abbr. Brief Description Direction (forward or reverse) Bit rate Max BER Power level Pilot Global Channels Fast Broadcast Channel FBCH Broadcasts fast-changing system information F 16 kbit/ s 1e-4 Fixed GLPT Slow Broadcast Channel SBCH Broadcasts paging messages to FSUs and slow-changing system information F 16 kbit/ s 1e-7 Fixed GLPT Access Channels AXCH(i) For initial access attempts by FSUs R 32 kbit/ s 1e-7 Controlled by APC LAXPT (i) Control Channels CTCH(i) For granting access F 32 kbit/ s 1e-7 Fixed GLPT Assigned Channels 16 kbit/s POTS TRCH /16 General POTS use F/R 16 kbit/ s 1e-4 Controlled by APC F-GLPT R-ASPT 32 kbit/s POTS TRCH /32 General POTS use F/R 32 kbit/ s 1e-4 Controlled by APC F-GLPT R-ASPT 64 kbit/s POTS TRCH /64N POTS use for in-band modems/fax F/R 64 kbit/ s 1e-4 Controlled by APC F-GLPT R-ASPT Traffic channel TRCH /64L ISDN B channel or F/R 64 kbit/ s 1e-7 Controlled by APC F-GLPT R-ASPT @ 64 kbit/s-low BER LL D channel TRCH /16L ISDN D channel F/R 16 kbit/ s 1e-7 Controlled by APC F-GLPT R-ASPT Order wire channel OW assigned signaling channel F/R 32 kbit/ s 1e-7 Controlled by APC F-GLPT R-ASPT APC channel APC carries APC commands F/R 64 kbit/ s 2e-1 Controlled by APC F-GLPT R-ASPT The APC data is sent at 64 kbit/sec. The APC logical channel is not FEC coded to avoid delay and is transmitted at a low power level to minimize capacity used for APC. Alternatively, the APC and order wire (OW) data may be separately modulated using complex spreading code sequences, or they may be time division multiplexed with a 16 kbit/s traffic channel. The Spreading Codes The CDMA code generators used to encode the logical channels of the present invention employ Linear Shift Registers (LSRs) with feedback logic which is a method well known in the art. The code generators of the present embodiment of the invention generate 64 synchronous unique sequences. Each RF communication channel uses a pair of these sequences for complex spreading (in-phase and quadrature) of the logical channels, so the generator gives 32 complex spreading sequences. The sequences are generated by a single seed which is initially loaded into a shift register circuit. The Generation of Spreading Code Sequences and Seed Selection The spreading code period of the present invention is defined as an integer multiple of the symbol duration, and the beginning of the code period is also the beginning of the symbol. The relation between bandwidths and the symbol lengths chosen for the exemplary embodiment of the present invention is: BW(MHZ) L(chips/symbol) 7 91 10 130 10.5 133 14 182 15 195 The spreading code length is also a multiple of 64 and of 96 for ISDN frame support. The spreading code is a sequence of symbols, called chips or chip values. The general methods of generating pseudorandom sequences using Galois Field mathematics is known to those skilled in the art; hoever, the inventor has derived a unique set, or family, of code sequences for the present invention. First, the length of the linear feedback shift register to generate a code sequence is chosen, and the initial value of the register is called a "seed". Second, the constraint is imposed that no code sequence generated by a code seed can be a cyclic shift of another code sequence generated by the same code seed. Finally, no code sequence generated from one seed can be a cyclic shift of a code sequence generated by another seed. The inventor has determined that the spreading code length of chip values of the present invention is: 128 x 233415 = 29877120 The spreading codes are generated by combining a linear sequence of period 233415 and a nonlinear sequence of period 128 The nonlinear sequence of length 128 is implemented as a fixed sequence loaded into a shift register with a feed-back connection. The fixed sequence can be generated by an m-sequence of length 127 padded with an extra logic 0, 1, or random value as is well known in the art. The linear sequence of length L=233415 is generated using a linear feedback shift register (LFSR) circuit with 36 stages. The feedback connections correspond to a irreducible polynomial h(n) of degree 36. The polynomial h(x) chosen by the inventor for the exemplary embodiment of the present invention is h(x) = x 36 + x 35 + x 30 + x 28 + x 26 + x 25 + x 22 + x 20 + x 19 + x 17 + x 16 + x 15 + x 14 + x 12 + x 11 + x 9 + x 8 + x 4 + x 3 + x 2 + 1 A group of "seed" values for a LFSR representing the polynomial h(x) of equation (2) which generates code sequences that are nearly orthogonal with each other is determined. The first requirement of the seed values is that the seed values do not generate two code sequences which are simply cyclic shifts of each other. The present invention includes a method to increase the number of available seeds for use in a CDMA communication system by recognizing that certain cyclic shifts of the previously determined code sequences may be used simultaneously. The round trip delay for the cell sizes and bandwidths of the present invention are less than 3000 chips. In one embodiment of the present invention, sufficiently separated cyclic shifts of a sequence can be used within the same cell without causing ambiguity for a receiver attempting to determine the code sequence. This method enlarges the set of sequences available for use. By implementing the tests previously described, a total of 3879 primary seeds were determined by the inventor through numerical computation. These seeds are given mathematically as d n modulo h(x) where 3879 values of n are listed in the appendix, with d = (00,...00111). When all primary seeds are known, all secondary seeds of the present invention are derived from the primary seeds by shifting them multiples of 4095 chips modulo h(x). Once a family of seed values is determined, these values are stored in memory and assigned to logical channels as necessary. Once assigned, the initial seed value is simply loaded into LFSR to produce the required spreading code sequence associated with the seed value. Epoch and Sub-epoch Structures The long complex spreading codes used for the system of the current invention have a number of chips after which the code repeats. The repetition period of the spreading sequence is called an epoch. To map the logical channels to CDMA spreading codes, the present invention uses an Epoch and Sub-epoch structure. The code period for the CDMA spreading code to modulate logical channels is 29877120 chips/code period which is the same number of chips for all bandwidths. The code period is the epoch of the present invention, and the Table 2 defines the epoch duration for the supported chip rates. In addition, two sub-epochs are defined over the spreading code epoch and are 233415 chips and 128 chips long. The 233415 chip sub-epoch is referred to as a long sub-epoch, and is used for synchronizing events on the RF communication interface such as encryption key switching and changing from global to assigned codes. The 128 chip short epoch is defined for use as an additional timing reference. The highest symbol rate used with a single CDMA code is 64 ksym/sec. There is always an integer number of chips in a symbol duration for the supported symbol rates 64, 32, 16, and 8 ksym/s. Bandwidths, Chip Rates, and Epochs Bandwidth (MHz) Chip Rate, Complex (Mchip/sec) number of chips in a 64 kbit/sec symbol 128 chip sub-epoch duration (µs) 233415 chip sub-epoch duration* (ms) Epoch duration (sec) 7 5.824 91 21.978 40.078 5.130 10 8.320 130 15.385 28.055 3.591 10.5 8.512 133 15.038 27.422 3.510 14 11.648 182 10.989 20.039 2.565 15 12.480 195 10.256 18.703 2.394 Cyclic sequences of the prior art are generated using linear feedback shift register (LFSR) circuits. This method, however, does not generate sequences of even length. One embodiment of the spreading code sequence generator using the code seeds generated previously is shown in Figure 2a, Figure 2b, and Figure 2c. The exemplary system uses a 36 stage LFSR 201 to generate a sequence of period N'=233415=3 3 x5x7x13x19, which is C o in Figure 2a. In the Figures 2a. 2b, and 2c the symbol ⊕ represents a binary addition (EXCLUSIVE-OR). A sequence generator designed as above generates the in-phase and quadrature parts of a set of complex sequences. The tap connections and initial state of the 36 stage LFSR determine the sequence generated by this circuit. The tap coefficients of the 36 stage LFSR are determined such that the resulting sequences have the period 233415. Note that the tap connections shown in Figure 2a correspond to the polynomial given in equation (2). Each resulting sequence is then overlaid by binary addition with the 128 length sequence C* to obtain the epoch period 29877120. Figure 2b shows a Feed Forward (FF) circuit 202 which is used in the code generator. The signal X[n-1] is output of the chip delay 211, and the input of the chip delay 211 is X[n]. The code chip C[n] is formed by the logical adder 212 from the input X[n] and X[n-1]. Figure 2c shows the complete spreading code generator. From the LFSR 201, output signals go through a chain of up to 63 single stage FFs 203 cascaded as shown. The output of each FF is overlaid with the short, even code sequence C* which has a period of 128=2 7 . the short code sequence C* is stored in code memory 222 and exhibits spectral characteristics of a pseudorandom sequence to obtain the epoch N=29877120 when combined with the sequences provided by the FFs 203. This sequence of 128 is determined by using an m-sequence (PN sequence) of length 127=2 7 -1 and adding a bit-value, such as logic 0, to the sequence to increase the length to 128 chips. The even code sequence C* is input to the even code shift register 221, which is a cyclic register, that continually outputs the sequence. The short sequence is then combined with the long sequence using an EXCLUSIVE-OR operation 213, 214, 220. As shown in Figure 2c, up to 63 spreading code sequences C o through C 63 are generated by tapping the output signals of FFs 203 and logically adding the short sequence C* in a binary adders 213, 214, and 220, for example. One skilled in the art would realize that the implementation of the FF 203 create a cumulative delay effect for the code sequences produced at each FF stage in the chain. This delay is due to the nonzero electrical delay in the electronic components of the implementation. The timing problems associated with the delay can be mitigated by inserting additional delay elements into the FF chain. An exemplary FF chain with additional delay elements is shown in Figure 2d. The code-generators in the exemplary system are configured to generate either global codes, or assigned codes. Global codes are CDMA codes that can be received or transmitted by all users of the system. Assigned codes are CDMA codes that are allocated for a particular connection. When a family of sequences is generated from the same generator as described, only the seed of the 36 stage LFSR is specified. Sequences for all the global codes, are generated using the same LFSR circuit. Therefore, once an SU has synchronized to the Global pilot signal from an RCS and knows the seed for the LFSR circuit for the Global Channel codes, it can generate not only the pilot sequence but also all other global codes used by the RCS. The signal that is upconverted to RF is generated as follows. The spreading sequences produced by the above shift register circuits are converted to an antipodal sequence (0 maps into +1, 1 maps into -1). The Logical channels are initially converted to QPSK signals, which are mapped as constellation points as is well known in the art. The In-phase and Quadrature channels of each QPSK signal form the real and imaginary parts of the complex data value. Similarly, two spreading codes are used to form complex spreading chip values. The complex data and complex spreading code are multiplied to produce a spread-spectrum data signal. Similarly, for despreading, the received complex data is correlated with the conjugate of the complex spreading code to recover the data signal. Short Codes Short codes are used for the initial ramp-up process when an SU accesses an RCS. The period of the short codes is equal to the symbol duration and the start of each period is aligned with a symbol boundary. Both the SUs and the RCS derive the real and imaginary parts of the short codes from the last eight feed-forward sections of the sequence generator to produce the global codes for that cell. The signals represented by these short codes are known as Short Access Channel pilots (SAXPTs) Mapping of Logical Channels to Spreading Codes The exact relationship between the spreading code sequences and the CDMA logical channels and pilot signals is documented in Table 3a and Table 3b. Those signal names ending in '-CH' correspond to logical channels. Those signal names ending in '-PT' correspond to pilot signals, which are described in detail below. Spreading code sequences and global CDMA codes Sequence Quadrature Logical Channel or Pilot Signal Direction C 0 I FBCH Forward (F) C 1 Q FBCH F C 2 ⊕C* I GLPT F C 3 ⊕C* Q GLPT F C 4 ⊕C* I SBCH F C 5 ⊕C* Q SBCH F C 6 ⊕C* I CTCH (0) F C 7 ⊕C* Q CTCH (0) F C 8 ⊕C* I APCH (1) F C 9 ⊕C* Q APCH (1) F C 10 ⊕C* I CTCH (1) F C 11 ⊕C* Q CTCH (1) F C 12 ⊕C* I APCH (1) F C 13 ⊕C* Q APCH (1) F C 14 ⊕C* I CTCH (2) F C 15 ⊕C* Q CTCH (2) F C 16 ⊕C* I APCH (2) F C 17 ⊕C* Q APCH (2) F C 18 ⊕C* I CTCH (3) F C 19 ⊕C* Q CTCH (3) F C 20 ⊕C* I APCH (3) F C 21 ⊕C* Q APCH (3) F C 22 ⊕C* I reserved - C 23 ⊕C* Q reserved - ···· ···· ···· ···· ···· ···· ···· ···· C 40 ⊕C* I reserved - C 41 ⊕C* Q reserved - C 42 ⊕C* I AXCH(3) Reverse (R) C 43 ⊕C* Q AXCH(3) R C 44 ⊕C* I LAXPT(3) SAXPT(3) seed R C 45 ⊕C* Q LAXPT(3) SAXPT(3) seed R C 46 ⊕C* I AXCH(2) R C 47 ⊕C* Q AXCH(2) R C 48 ⊕C* I LAXPT(2) SAXPT(2) seed R C 49 ⊕C* Q LAXPT(2) SAXPT(2) seed R C 50 ⊕C* I AXCH(1) R C 51 ⊕C* Q AXCH(1) R C 52 ⊕C* I LAXPT(1) SAXPT(1) seed R C 53 ⊕C* Q LAXPT(1) SAXPT(1) seed R C 54 ⊕C* I AXCH(0) R C 55 ⊕C* Q AXCH(0) R C 56 ⊕C* I LAXPT(0) SAXPT(0) seed R C 57 ⊕C* Q LAXPT(0) SAXPT(0) seed R C 58 ⊕C* I IDLE - C 59 ⊕C* Q IDLE - C 60 ⊕C* I AUX R C 61 ⊕C* Q AUX R C 62 ⊕C* I reserved - C 63 ⊕C* Q reserved - Spreading code sequences and assigned CDMA codes. Sequence Quadrature Logical Channel or Pilot Signal Direction C 0 ⊕C* I ASPT Reverse (R) C 1 ⊕C* Q ASPT R C 2 ⊕C* I APCH R C 3 ⊕C* Q APCH R C 4 ⊕C* I OWCH R C 5 ⊕C* Q OWCH R C 6 ⊕C* I TRCH(0) R C 7 ⊕C* Q TRCH(0) R C 8 ⊕C* I TRCH(1) R C 9 ⊕C Q TRCH(1) R C 10 ⊕C* I TRCH(2) R C 11 ⊕C* Q TRCH(2) R C 12 ⊕C* I TRCH(3) R C 13 ⊕C* Q TRCH(3) R C 14 ⊕C* I reserved - C 15 ⊕C* Q reserved - ···· ···· ···· ···· ···· ···· ···· ···· C 44 ⊕C* I reserved - C 45 ⊕C* Q reserved - C 46 ⊕C* I TRCH(3) Forward (F) C 47 ⊕C* Q TRCH(3) F C 48 ⊕C* I TRCH(2) F C 49 ⊕C* Q TRCH(2) F C 50 ⊕C* I TRCH(1) F C 51 ⊕C* Q TRCH(1) F C 52 ⊕C* I TRCH(0) F C 53 ⊕C* Q TRCH(0) F C 54 ⊕C* I OWCH F C 55 ⊕C* Q OWCH F C 56 ⊕C* I APCH F C 57 ⊕C* Q APCH F C 58 ⊕C* I IDLE - C 59 ⊕C* Q IDLE - C 60 ⊕C* I reserved - C 61 ⊕C* Q reserved - C 62 ⊕C* I reserved - C 63 ⊕C* Q reserved - Pilot Signals As described above, the pilot signals are used for synchronization, carrier phase recovery, and for estimating the impulse response of the radio channel. The RCS 104 transmits a forward link pilot carrier reference as a complex pilot code sequence to provide a time and phase reference for all SUs 111, 112, 115, 117 and 118 in its service area. The power level of the Global Pilot (GLPT) signal is set to provide adequate coverage over the whole RCS service area, which area depends on the cell size. With only one pilot signal in the forward link, the reduction in system capacity due to the pilot energy is negligible. Each of the SUs 111, 112, 115, 117 and 118 transmits a pilot carrier reference as a quadrature modulated (complex-valued) pilot spreading code sequence to provide time and phase reference to the RCS for the reverse link. The pilot signal transmitted by the SU of one embodiment of the invention is 6 dB lower than the power of the 32 kbit/s POTS (plain old telephone service) traffic channel. The reverse pilot channel is subject to APC. The reverse link pilot associated with a particular connection is called the Assigned Pilot (ASPT). In addition, there are pilot signals associated with access channels, and these are called the Long Access Channel Pilots (LAXPTs). Short access channel pilots (SAXPTs) are also associated with the access channels and used for spreading code acquisition and initial power ramp-up. All pilot signals are formed from complex codes, as defined below: GLPT (forward) = {C 2 ⊕C*) + j.(C 3 ⊕C*)} . {(±1) + j.(0)} { Complex Code } . { Carrier } The complex pilot signals are de-spread by multiplication with conjugate spreading codes: {(C 2 ⊕C*) - j.(C 3 ⊕C*)}. By contrast, traffic channels are of the form: TRCH n (forward/reverse) = ((C k ⊕C*) + j.(C 1 ⊕C*)} . { (±1) + j(±1) } { Complex Codes } . { Data Symbol } which thus form a constellation set at π / 4radians with respect to the pilot signal constellations. The GLPT constellation is shown in Figure 3a, and the TRCHn traffic channel constellation is shown in Figure 3b. Logical Channel Assignment of the FBCH, SBCH, and Traffic Channels The fast broadcast channel (FBCH) is a global forward link channel used to broadcast dynamic information about the availability of services and access channels (AXCHs). The messages are sent continuously, and each message lasts approximately 1 ms. The FBCH message is 16 bits long. repeated continuously, and epoch aligned. The FBCH is formatted as defined in Table 4. FBCH format Bit Definition 0 Traffic Light 0 1 Traffic Light 1 2 Traffic Light 2 3 Traffic Light 3 4-7 service indicator bits 8 Traffic Light 0 9 Traffic Light 1 10 Traffic Light 2 11 Traffic Light 3 12-15 service indicator bits For the FBCH, bit 0 is transmitted first. A traffic light corresponds to an Access Channel (AXCH) and indicates whether the particular access channel is currently in use (red) or not in use (green). A logic '1' indicates that the traffic light is green, and a logic '0' indicates the traffic light is red. The values of the traffic light bits may change from octet to octet, and each 16 bit message contains distinct service indicator bits which describe which types of service are available for the AXCHs. One embodiment of the present invention uses service indicator bits as follows to indicate the availability of services or AXCHs. The service indicator bits {4,5,6,7,12,13,14,15} are interpreted as an unsigned binary number, with bit 4 as the MSB and bit 15 as the LSB. Each service type increment has an associated nominal measure of the capacity required, and the FBCH continuously broadcasts the available capacity. This is scaled to have a maximum value equivalent to the largest single service increment possible. When an SU requires a new service or an increase in the number of bearers), it compares the capacity required to that indicated by the FBCH, and then considers itself blocked if the capacity is not available. The FBCH and the traffic channels are aligned to the epoch. Slow Broadcast Information frames contain system or other general information that is available to all SUs, and Paging Information frames contain information about call requests for particular SUs. Slow Broadcast Information frames and Paging Information frames are multiplexed together on a single logical channel which forms the Slow Broadcast Channel (SBCH). As previously defined, the code epoch is a sequence of 29 877 20 chips having an epoch duration which is a function of the chip rate defined in Table 5 below. In order to facilitate power saving, the channel is divided into N "Sleep" Cycles, and each Cycle is subdivided into M Slots, which are 19 ms long, except for 10.5 Mhz bandwidth which has slots of 18 ms. SBCH Channel Format Outline Bandwidth (MHz) Spreading Code Rate (MHz) Epoch-Length (ms) Cycles/ Epoch N Cycle Length (ms) Slots/ Cycle M Slot Length (ms) 7.0 5.824 5130 5 1026 54 19 10.0 8.320 3591 3 1197 63 19 10.5 8.512 3510 3 1170 65 18 14.0 11.648 2565 3 855 45 19 15.0 12.480 2394 2 1197 63 19 Sleep Cycle Slot #1 is always used for slow broadcast information. Slots #2 to #M-1 are used for paging groups unless extended slow broadcast information is inserted. The pattern of cycles and slots in one embodiment of the present invention run continuously at 16 kbit/s. Within each Sleep Cycle the SU may power-up the receiver and re-acquire pilot code to achieve carrier lock to a sufficient precision for satisfactory demodulation and Viterbi decoding. This settling time may be up to 3 Slots in duration. For example, an SU assigned to Slot #7 may power up the Receiver at the start of Slot #4. Having monitored its Slot the SU either recognizes its Paging Address and initiates an access request, or fails to recognize its Paging Address in which case it reverts to the Sleep mode. Spreading code Tracking and AMF Detection in Multipath Channels Spreading code Tracking Three CDMA spreading code tracking methods in multipath fading environments are described which track the code phase of a received multipath spread spectrum signal. The first method uses the prior art tracking circuit which simply tracks the spreading code phase of the detector having the highest output signal value, the second method uses a tracking circuit that tracks the median value of the code phase of the group of multipath signals, and the third method of the present invention, is the centroid tracking circuit which tracks the code-phase of an optimized, least mean squared weighted average of the multipath signal components. The following describes the algorithms by which the spreading code phase of the received CDMA signal is tracked. A tracking circuit has operating characteristics that reveal the relationship between the time error and the control voltage that drives a Voltage Controlled Oscillator (VCO) of a spreading code phase tracking circuit. When there is a positive timing error, the exemplary tracking circuit generates a negative control voltage to offset the timing error. When there is a negative timing error, the exemplary tracking circuit generates a positive control voltage to offset the timing error. When the tracking circuit generates a zero value, this value corresponds to the perfect time alignment called the 'lock-point'. Figure 3c shows the basic tracking circuit. Received signal r(t) is applied to matched filter 301, which correlates r(t) with a local code-sequence c(t) generated by Code Generator 303. The output signal of the matched filter x(t) is sampled at the sampler 302 to produce samples x[nT] and x[nT + T/2]. The samples x[nT] and x[nT + T/2] are used by a tracking circuit 304 to determine if the phase of the spreading code c(t) of the code generator 303 is correct. The tracking circuit 304 produces an error signal e(t) as an input to the code generator 303. The code generator 303 uses this signal e(t) as an input signal to adjust the code-phase it generates. In a CDMA system, the signal transmitted by the reference user is written in the low-pass representation as where c k represents the spreading code coefficients, P Te ( t ) represents the spreading code chip waveform, and T e is the chip duration. Assuming that the reference user is not transmitting data, only the spreading code modulates the carrier. Referring to Figure 3, the received signal is Here, a i is due to fading effect of the multipath channel on the i-th path and τ i is the random time delay associated with the same path. The receiver passes the received signal through a matched filter, which is implemented as a correlation receiver and is described below. This operation is done in two steps: first the signal is passed through a chip matched filter and sampled to recover the spreading code chip values, then this chip sequence is correlated with the locally generated code sequence. Figure 3c shows the chip matched filter 301, matched to the chip waveform P Tc (t) , and the sampler 302. The signal x(t) at the output terminal of the chip matched filter is where g(t) = P Tc (t)*h R (t) Here, h R (t) is the impulse response of the chip matched filter and '*' denotes convolution. The order of the summations, can be rewritten as: where In the multipath channel described above, the sampler samples the output signal of the matched filter to produce x(nT) at the maximum power level points of g(t). In practice, however, the waveform g(t) is often severely distorted because of the effect of the multipath signal reception, and a perfect time alignment of the signals is not available. When the multipath in the channel is negligible and a perfect estimate of the timing is available, i.e., a 1 = 1, τ 1 = 0, and a i = 0, i = 2,...,M, the received signal is r(t) = s(t). Then, with this ideal channel model, the output of the chip matched filter becomes When there is multipath fading, however, the received spreading code chip value waveform is distorted, and has a number of local maxima that can change from one sampling interval to another depending on the channel characteristics. For multipath fading channels with quickly changing channel characteristics, it is not practical to try to locate the maximum of the waveform f(t) in every chip period interval. Instead, a time reference can be obtained from the characteristics of f(t) that may not change as quickly. Three tracking methods are described based on different characteristics of f(t). 0 67 134 201 268 335 402 469 536 603 670 737 1 68 135 202 269 336 403 470 537 604 671 738 2 69 136 203 270 337 404 471 538 605 672 739 3 70 137 204 271 338 405 472 539 606 673 740 4 71 138 205 272 339 406 473 540 607 674 741 5 72 139 206 273 340 407 474 541 608 675 742 6 73 140 207 274 341 408 475 542 609 676 743 7 74 141 208 275 342 409 476 543 610 677 744 8 75 142 209 276 343 410 477 544 611 678 745 9 76 143 210 277 344 411 478 545 612 679 746 10 77 144 211 278 345 412 479 546 613 680 747 11 78 145 212 279 346 413 480 547 614 681 748 12 79 146 213 280 347 414 481 548 615 682 749 13 80 147 214 281 348 415 482 549 616 683 750 14 81 148 215 282 349 416 483 550 617 684 751 15 82 149 216 283 350 417 484 551 618 685 752 16 83 150 217 284 351 418 485 552 619 686 753 17 84 151 218 285 352 419 486 553 620 687 754 18 85 152 219 286 353 420 487 554 621 688 755 19 86 153 220 287 354 421 488 555 622 689 756 20 87 154 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7076 7143 5439 5506 6675 6742 6809 6876 6943 7010 7077 7144 5440 5507 6676 6743 6810 6877 6944 7011 7078 7145 5441 5508 6677 6744 6811 6878 6945 7012 7079 7146 5442 5509 6678 6745 6812 6879 6946 7013 7080 7147 5443 6612 6679 6746 6813 6880 6947 7014 7081 7148 5444 6613 6680 6747 6814 6881 6948 7015 7082 7149 5445 6614 6681 6748 6815 6882 6949 7016 7083 7150 5446 6615 6682 6749 6816 6883 6950 7017 7084 7151 5447 6616 6683 6750 6817 6884 6951 7018 7085 7152 5448 6617 6684 6751 6818 6995 6952 7019 7086 7153 5449 6618 6685 6752 6819 6886 6953 7020 7087 7154 5450 6619 6686 6753 6820 6887 6954 7021 7088 7155 5451 6620 6687 6754 6821 6888 6955 7022 7089 7156 5452 6621 6688 6755 6822 6889 6956 7023 7090 7157 5453 6622 6689 6756 6823 6890 6957 7024 7091 7158 5454 6623 6690 6757 6824 6891 6958 7025 7092 7159 5455 6624 6691 6758 6825 6892 6959 7026 7093 7160 5456 6625 6692 6759 6826 6893 6960 7027 7094 7161 5457 6626 6693 6760 6827 6894 6961 7028 7095 7162 5458 6627 6694 6761 6828 6895 6962 7029 7096 7163 5459 6628 6695 6762 6829 6896 6963 7030 7097 7164 5460 6629 6696 6763 6830 6897 6964 7031 7098 7165 5461 6630 6697 6764 6831 6898 6965 7032 7099 7166 5462 6631 6698 6765 6832 6899 6966 7033 7100 7167 5463 6632 6699 6766 6833 6900 6967 7034 7101 7168 5464 6633 6700 6767 6834 6901 6968 7035 7102 7169 5465 6634 6701 6768 6835 6902 6969 7036 7103 7170 5466 6635 6702 6769 6836 6903 6970 7037 7104 7171 5467 6636 6703 6770 6837 6904 6971 7038 7105 7172 5468 6637 6704 6771 6838 6905 6972 7039 7106 7173 5469 6638 6705 6772 6839 6906 6973 7040 7107 7174 5470 6639 6706 6773 6840 6907 6974 7041 7108 7175 5471 6640 6707 6774 6841 6908 6975 7042 7109 7176 5472 6641 6708 6775 6842 6909 6976 7043 7110 7177 5473 6642 6709 6776 6843 6910 6977 7044 7111 7178 5474 6643 6710 6777 6844 6911 6978 7045 7112 7179 5475 6644 6711 6778 6845 6912 6979 7046 7113 7180 5476 6645 6712 6779 6846 6913 6980 7047 7114 7181 5477 6646 6713 6780 6847 6914 6981 7048 7115 7182 5478 6647 6714 6781 6848 6915 6982 7049 7116 7183 5479 6648 6715 6782 6849 6916 6983 7050 7117 7184 5480 6649 6716 6783 6850 6917 6984 7051 7118 5481 6650 6717 6784 6851 6918 6985 7052 7119 5482 6651 6718 6785 6852 6919 6986 7053 7120 5483 6652 6719 6786 6853 6920 6987 7054 7121 5484 6653 6720 6787 6854 6921 6988 7055 7122 5485 6654 6721 6788 6855 6922 6989 7056 7123 5486 6655 6722 6789 6856 6923 6990 7057 7124

Claims: A code sequence generator apparatus (303) for generating a plurality of spreading code sequences including a master spreading code sequence, the plurality of spreading code sequences having mutual cross correlation within a predetermined range, and having a predetermined mutual code phase relationship, comprising: a clock generator means for generating a clock signal; a linear feedback shift register LFSR (201), responsive to the clock signal and having a plurality of stages including a first stage and a last stage, each stage defining a respective tap, each tap producing a tap signal to a logic circuitry such that a predetermined group of the tap signals including the tap signal of the last stage are applied to the logic circuitry and the logic circuitry being adapted to combine the tap signals to produce a feedback spreading code signal, said feedback spreading code signal applied as an input signal to the first stage of the LFSR (201); first memory means (223) for storing a plurality of spreading-code seeds, each spreading-code seed comprising a set of spreading-code sequence bit values, and said first memory being connected to the LFSR (201) and being responsive to a load signal for transferring each one of a predetermined set of the spreading-code sequence bit values of a selected one of the plurality of spreading-code seed into a respective one of the shift register stages of the LFSR; and code generator controller means for selecting one of the plurality of spreading code seeds to determine the plurality of spreading code sequences and for providing the load signal indicating said one spreading-code seed, wherein said LFSR (201) is responsive to the clock signal to sequentially transfer each respective tap signal from one stage to the next stage, from the first stage to the last stage and for transferring the feedback spreading code value to the first stage, and each successive one of the tap values of the last stage defines the master spreading code sequence, characterized in that the code sequence generator further comprises: second memory means (222) being responsive to the clock signal for providing a repetitive even code sequence, said even code sequence having a cross correlation with the master spreading sequence which is within the predetermined range and having an even number of chip spreading values; a plurality of cascade connected feedforward means (203), coupled to receive the master spreading code sequence, for providing a plurality of code sequences, each code sequence being a distinct spreading code sequence of said plurality of spreading code sequences, each of said feedforward means (203) being responsive to the clock signal, to provide a respective one of the plurality of spreading code sequences; and a plurality code sequence combining means, each code sequence combining means for combining each respective spreading code sequence with said even code sequence to produce a plurality of relatively long spreading code sequences, each long spreading code sequence having a greater number of elements than any one of the plurality of spreading code sequences. The code sequence generator apparatus of claim 1, wherein the plurality of cascade connected feedforward means (203) includes: receiving means for receiving the master spreading sequence; a feedforward circuit (202) having a plurality of cascade connected feedforward logic sections, each logic section defining a tap which provides one of the plurality of spreading code sequences, including a first feedforward logic section and a last feedforward logic section and connected sequentially from the first feedforward logic section to the last feedforward logic section, each feedforward logic section comprising a single delay element (211) having an input terminal which receives an input signal and an output terminal which provides an output signal, and logic combining means (220) for logically combining the input signal with the output signal to produce the respective spreading code sequence. The code sequence generator apparatus claim 2, wherein the code sequence combining means comprises an EXCLUSIVE-OR logic circuit. The code sequence generator apparatus of claim 2, wherein the logic combining means comprises an EXCLUSIVE-OR logic circuit for performing modulo-2 addition.

Inventors: FATIH OZLUTURK, LOMP GARY, SILVERBERG AVI, FATIH, OZLUTURK, LOMP, GARY, SILVERBERG, AVI
Applicants: INTERDIGITAL TECH CORP, INTERDIGITAL TECHNOLOGY CORPORATION
Application year: 1996
Main classification: H04J13
IPC codes: H04L1, H04B7, H04J13, H04L27, H04B1, H04L25, H04J11, H03K3, H04L7, H04W52, H04B17