CLOCK SIGNAL DISTRIBUTION AND SYNCHRONISATION IN A DIGITAL SYSTEM

Abstract: The invention relates to a method and a device for increasing the working speed of synchronous digital systems comprising a number of system parts (A - D) placed at a distance from each other and communicating with at least one other of the other system parts. A common signal for the system with a reference frequency (2) is distributed to all the system parts. The system parts are each equipped with their own internal clock signal oscillator (5) which is phase-adjusted individually for the different system parts in relation to the signal received from the reference frequency (2) so that the communication between the communicating system parts takes place with the same phase relationship but can take place in different periods.

Description: Clock signal distribution and synchronisation in a digital system The present invention concerns a process ofthe type which is mentioned in the preamble of claim 1, and a device for carrying out the process. Large synchronous electrical systems, such as e.g. computers, are traditionally constructed so that each desired function is successively broken down into smaller and smaller partial functions or operations. In the end there is a collection of opera¬ tions which each can be executed within one clock period. The transmission ofthe results to a subsequent operation should timewise be included in the same clock period. Alternatively, the transmission can take place in the subsequent clock period but in this case the performance ofthe system is reduced. In order to insure that all the parts of the system work synchronously, a common reference signal or clock signai is distributed for the whole system. This traditional construction means that an upper limiting frequency for the system is obtained which is inversely proportional to the area ofthe system. Nowadays the ambition is to have faster and faster systems with higher and higher clock frequencies, preferably in the order of several GHz in order to be able co in- crease the performance ofthe system. The clocks in this case can work within a certain propagation area where the propagation time for the clock signal is relatively short in relation to the cycle time. It is easy tc estimate the limiting frequency for a digital system with a physical size of 30 cm x 30 cm. An example of such a system is a portable PC (Personal Compu¬ ter), but it should be noted that the invention is not at all intended to be limited to computers but applies to any digital system whatsoever. With the assumption that the system is built upon a circuit board with a dielectric constant e = 5, the propaga¬ tion speed v = c <=, where c = the speed of light in a vacuum. The transport time from one circuit block in one corner to a circuit block in a diametrically opposite corner can in this case be T d =- 2L/v. where L is the length ofthe sides ofthe system, if the conductors run along the sides. In this case T will be approximately 4.5 ns. It is assumed that for every block the input signal is stable before the beginning of the current clock period, and that the operation is performed and transported to the subsequent block within the clock period. Just taking account of tlie propagation speed ofthe signal means that the clock period is limited down to about 9 ns. This gives a maximal theoretical clock frequency of approximately 100 MHz for the system. The time for the performance ofthe operations, the limited drive capacity ofthe components, RC-delays etc often reduce the maximal clock frequency to 10 - 40 MHz. The constituent components can often work at considerably higher frequencies, in the order of several GHz, and it is obvious that the traditional wav of construction and traditional assumptions result in the performance for the system which by a long way does not correspond to the performance ofthe constituent components. This problem has been noticed earlier and a solution is suggested in DE-Al - 44 12 419. A system which can be divided into partial circuits is shown here. In each partial circuit there is at least one signal buffer. The part system receives a reterence clock signal as an input signal and has a sequential connection which is driven as a reaction to a clock signal which is synchronized with the reference clock signal. An output signal from the sequential connections is fed back to the input. With a phase-locked connection the timing signal is synchronized with the reference clock signal to the sequential connection through the clock signal being phase- controlled. This means that it is the reference clock signal source which directly gives the clock signal for the partial circuit and that it is the incoming clock signal which is phase-shifted. A circuit, e.g. comprising internal registers, which is equipped with its own clock signal generator with a phase-locked loop is shown in US-A-5,204,555. The clock signal generator is not phase-adjustable. It receives a reference clock signal from the -* surroundings and converts the reference clock signal frequency to a higher (or lower) frequency. The object of this arrangement is to be able to make for example intemal registers work faster than the surrounding circuits. No phase-shifting is necessary in such a connection. THE OBJECTS OF THE INVENTION An object ofthe invention is to produce a process and/or device where the perform¬ ance of a digital system approaches the performance ofthe constituent components ofthe system. Another object of the invention is to produce a process and/or device which makes it possible to work with higher clock frequencies even in large size digital systems. The above mentioned objects are achieved v/ith a method which has the features mentioned in the main claim. Further characteristics and further developments of the invention and a device for performing the process are given in the other claims. Consequently, the invention is based upon that a reference signal, e.g. a clock signal which is the same for the whole system, is distributed to all parts ofthe system as a common frequency reference. However, there does not exist a common phase posi¬ tion for the reference signal. This means that within the system there are no restric¬ tions concerning the transport time for the reference signal to the different parts of the system. The reference frequency is, however, itself phase-stable. The reference frequency does not have to be the same as the clock frequencies ofthe parts and does not, therefore, need to be high frequency but it can, for many reasons, such as power requirements, sensitivity to disturbances etc. be appropriate to let the reference fre¬ quency be a low frequency clock. It is. however, preferable that the clock frequen¬ cies ofthe parts are whole number multiples ofthe frequency ofthe reference signal. Each part ofthe system, which can be a circuit board, a chip or altematively a part of a chip, is equipped with a Phase Locked Loop (PPL). The phase position of each part of the system is individually adjustable so that a secure point-to-point-communica¬ tion is achieved with the part ofthe system with which it is communicating at the moment. For the sake of simplicity the systems parts are called blocks below. The number of point-to-point-connections for which the phase positions should be adjustable depends on the block structure for the system in question. Consequently, the constituent parts ofthe system often work with a phase shift of a whole number of periods in relation to one another but have the same relative phase position when they communicate with each other. It should be noted that even if the description is firstly directed towards a digital system, even systems working in an analogue manner are included in the invention. or the system can equally well be a hybrid system with both digital and analogue parts, e.g. comprising digital signal processing of analogue sensor signals. A system construction formed in accordance with the invention differs from tradi¬ tional system constructions where all the blocks are constructed in order to be able to be connected v/ith each other. irrespective of whether a connection is required or not. In the construction of systems where the method according to the invention is used, the communication channels and the cooperation between different blocks is some- thmg which the constructor must consider in order to optimize the performance of the system. The method according to the invention permits synchronization of very large digital systems where each part ofthe system can work with very high clock frequencies. The reference signal can, however, " have a considerably lower frequency which is preferable. The system as such can, however, work synchronously at a clock fre¬ quency of the order of several GHz, e.g. 1 - 5 GHz. The methods which are tradi¬ tionally used today limit the clock frequency ofthe system to about 10 - 40 MHz. Consequently, a system constructed using the principles ofthe invention can work 20 - 100 times faster, for example, by using the same basic technology as in the manufacturing ofthe digital chips. The method according to the invention is not technology-dependent but can be used with the traditional system construction of circuit boards which use integrated circuits of different types and manufactured according to all technologies, such as CMOS, ECL etc. 5 The invention has many fields of application, preferably calculation-intensive appli¬ cations, such as computers, image processing, radar signal processing etc. Other fields of applications are where large quantities of data have to be sorted, such as in telephone exchanges, telecommunications etc. 0 BRIEF DESCRIPTION OF THE FIGURES The invention is described more closely below with reference to the appended drawings, where Figure 1 illustrates some selected parts in a system, which is equipped with an embodiment of the device according to the invention, and 5 Figure 2 shows an altemative embodiment illustrating one ofthe blocks in Figure 1. DETAILED DESCRIPTION OF THE DRAWINGS As is evident from Figure 1. a digital system 1 comprises a number of blocks A-D 0 which each are intended to work at a high frequency, for example in the GHz region. For the sake of clarity only a few such circuits are shown. The system can also include circuits with different performances concerning high frequency, which can cooperate with the other circuits while using the principles ofthe invention. For -> example, extemal communications can take place with different performances. The system is equipped with a reference frequency source 2 connected amongst others to blocks A and D, which are intended to have signal communications with each other. These are each equipped with their own intemal clock signal oscillator 5. which are individually phase-adjusted for the different system parts in relation to the signal 30 from the reference frequency source 2 so that the communication between the communicating system parts takes place with the same intemal phase relationship but can take place within different periods. The reference frequency source 2 can in its turn be controlled by an extemal signal received from another system not shown in Figure 1. The communication from block A to block D can take place via two transmission channels, where one is via block B and the other via block C. The reference frequency source 2 is also connected to block B and C. Block A can comprise a number of logic blocks IA - NA, e.g. in the form of a chip or part of a chip. The intemal communication in block A takes place with a high clock frequency, e.g. several GHz, which it is desired that the system shall work at. In the same way, block D can comprise a number of logic blocks ID - ND, which can have an intemal communication with preferably the same high clock frequency. It is also conceivable to have different clock frequencies in the different blocks, but in this case these blocks must have the ability to change frequences at the input and/or the output, so that the transmission communications have a transmission frequency which is adapted so that the receiving block can process the transmitted signals. The reference frequency source 2 has preferably a considerably lower block frequency, e.g. approximately 10 MHz. than the higher clock frequency for the circuit blocks. In this way, the system becomes relatively interference-insensitive. The power consumption ofthe system is lower if the source 2 has a lower frequency. In the invention each of blocks A to D is equipped with a phase-locked loop. In the embodiment shown in Figure 1, it comprises a phase comparator 3 which has an input coupled to the reference frequency source 2. The phase-shifted feedbacked, divided, intemal clock frequency is connected to the second input on the circuit 3. The output signal from the phase comparator is inputted via a filter 4 to a clock signal oscillator 5, which is controlled to give a completely stable high clock fre¬ quency. The filter 4 is a slow bandpass filter and filters around the loop frequency in the loop. Such a control is wellknown in the art and is therefore not described in more detail. Preferably a voltage-controlled dock signal oscillator 5, from now on called a VCO (Voltage Controlled Oscuiator) is used. The clock signal oscillator 5 shall give the high working frequency which is phase- locked to the reference source. Each separate VCO in each block consequently will form a high frequency with a certain phase position (time position) ΔT, which is individual for the block. This ΔT can according to the invention be adaptively individually servo-regulated and the output on the VCO is therefore connected to a division circuit 7 (frequency divider) in order to phase-lock to a frequency which is N times the reference frequency. The output from the circuit 7 is connected to a con- trollable phase-adjustment circuit 6 which changes the phase position ofthe high working frequency (from the VCO) relative to the phase position ofthe reference frequency which reaches the partial block. The output ofthe circuit 6 is connected to the regulating input ofthe phase comparator 3. Circuit 6 and 7 can change places with each other wherein such a case ΔT is dependent on the wavelength of the VCO instead ofthe reference frequency source 2. Altematively circuits 6 and 8 can be moved from the regulation loop and connected to the input ofthe phase comparator 3 which is connected to the reference frequency source 2, as is shown in Figure 2, which is a changed partial view of block D. The circuits 60 and 80 with the corresponding functions of circuits 6 and 8 are connected between the reference frequency source 2 and the lower input on the phase compara¬ tor 3. The phase adjustment circuit 6 (or 60) is controlled by a phase control circuit 8 (or 80), which comprises a register, where the manufacturer ofthe system individually, e.g. with the help of a computer, when the system is completed, can adjust the phase position for all the blocks, so that the phases mutually correspond berween the different units which are to communicate with each other. Consequently, it is that which is written in the individual registers 8 (or 80), which in practice determines the phase position in each block. The phase adjustments for the different blocks can be compared to the buming-in of a fixed memory. Altematively. the adjustment can ιaκe place adaptively while me system is in use. it should be noted that tlie function ' " register" is not necessarily a physical or digital register but can for example be an algorithm in e.g. a processor or a processing circuit of another, e.g. analog, type. It should be noted that the frequency Fref from the reference source 2 to ihe different blocks is mutually phase-shifted between the blocks, but that the phase-regulating circuit 3 - 8 in the block is phase-locked to a certain part ofthe reference frequency, for example a flank if the reference frequency is a square signal, or to a zero- transition or the like. It should be noted that there can be a difference of several clock signal periods between the blocks but that they shall work at the same phase position. The register in the phase control circuit 8 (or 80) adaptively regulates the time delay ofthe phase adjustment circuit 6 (or 60) so that its phase position is always held at ΔT. In this way the high clock signals from NCO 5 will lie in the right phase position for the block in relation to the phase ofthe incoming signal. Blocks consisting of individual chips can naturally during development be equipped with the phase-locked loop directly, but the phase-locked loop can naturally also be a connected unit, for example in the form of a separate chip connectable to another chip. During the initiation of the system all the delays in the phase-locked loops are adjusted so that a secure point-to-point communication is obtained. It should be noted that it is irrelevant how many dock periods it takes for the data to be trans¬ ported from block A via block B to block D or via block C to block D. The connec- tions between the blocks can be formed from transmission lines for which the trans¬ port time can be more than one or more clock periods. Each delay is adjusted in the phase-locked loop so that the total delay is a whole number and secure communica¬ tion is obtained. As is niustrated in Figure 1, tne system can contain parallel transmission channels which means certain complications. Assume that both the transmission channels shown in Figure 1 are to be used simultaneously to transfer associated partial results processed in blocks B and C to the two communication inputs on block D. Block B and C delay the transmitted signals in different ways in the delaying means which is schematically illustrated as FB and FC; block B can for example be a processor and block C a writable memory (RAM). The delaying ofthe incoming signals must be adapted to this so that the time difference between the time points for the data from blocks B and C to block D are calibrated away. Each block, or altematively some selected blocks can, for this purpose, have a controllable delay circuit FA. FB, FC. FDL FD2 on its/their communication inputs. Each of them can, just like register 8 (or 80) be adjusted to the right delay in the system by the constructor ofthe system with the help of an adjustment algorithm which can be implemented in a computer. This adjusts the incoming data for the block in question which can come in from several different directions, so that they get the same phase position and also the same clock frequency position (correct number of whole clock periods) in the case that this is important. In the case of several steps and/or parallel communication channels a linear combination of delays can, for example, be introduced which ensure synchronous data transfer. As mentioned above it is also possible to have blocks which work with different mutual frequencies. In such a case a buffer memory can be connected to the block with the different working frequency. The above mentioned delay circuits FA. FB etc can be formed from this buffer circuit. The incoming signal is stored in the buffer memory with the incoming frequency and is read out ofthe memory with the block's own frequency. This buffer memory in this case functions as a delay unit. In this case the reading out takes place with the phase position which is installed for the block. Such a block in this case can also have the same type of buffer memory at its output, which in Figure 2 is illustrated by the circuit BFU, where the output data are written in with the working frequency ofthe block and are read at the working frequency of the biocks witii which this block communicates. However, it is normally so that most ofthe blocks in a system work with the same high working frequency and in this case buffer memories of said type is only placed on blocks with a differing frequency. If the system has many blocks each having their own individual working frequency, it can be practical to equip most ofthe blocks with the above mentioned type of buffer memory, and in this case appropriately at their inputs. The phase regulating circuits 3 - 8 in each block A - D can be a separately connected part ofthe block, possibly in the form of a connectable chip, or be connected to a circuit or to the individual circuits on a chip during the manufacturing ofthe chip. The relationship with the individually adjustable delay circuits is the same. It should be noted that an adjustment ofthe different phase-regulating circuits and delay circuits can be redone after a system with the characteristics according to the invention has been put into service, if it is shown that the adjustment has become wrong or if the system has changed. This adjustment can possibly be performed automatically by servo regulating (following an algorithm) of e.g. the register 8 or the phase adjustment circuit 6 with a phase comparison between the incoming transfer signal and the inner clock signal ofthe system. Sensing for this servo regulating can for example take place in the phase delaying circuits shown. The adjustment can also be performed externally after a warning signal of a malfunction has been given to a malfunction circuit (not shown) from any of the blocks in the system. The function of sensing that there is a malfunction in the system can be performed with the above described phase comparison between the incoming signal and the intemal clock signal and a warning issued instead ofthe above described servo regulation. It is also possible to equip the whole system with an error correction circuit (not shown , which comes into action upon receipt of a warning from any ofthe constituent part systems (blocks A - D).

Claims: Claims 1. Method for increasing the working speed in a synchronous digital system comprising a number of system parts placed at a distance from each other with communication between at least one ofthe other system parts, wherein a common signal with a reference frequency (2) is distributed to all the system parts, characterized in that the system parts are provided each with their own intemal clock signal osδillator (5) which is individually phase-adjusted for the different system parts in relation to the signal received from the reference frequency (2) so that communication between communicating system parts takes place with the same intemal phase relationship. 2. Method according to Claim 1, characterized in that the reference frequency is lower than the frequency ofthe intemal clock frequency oscillator of each system part. 3. Method according to Claim 1 or 2, characterized in that the individual phase position for the clock frequency oscillator in each system part in a system is permanently adiusted after the configuration ofthe system is ready and the system is built. 4. Process according to Claim 1 or 2, characterized in that the individual phase position for the clock signal oscillator (VCO) in each system part in a system is adaptively adjusted while the system is operative. 5. Device for increasing the working speed in a synchronous digital system comprising a number of system parts placed at distance from each other with com¬ munication with at least one ofthe other system parts and a common reference frequency source (2) for the system parts, characterized in that each system part (A,B,C,D), which is arranged to have communication with at least other system part, comprises an individual clock signal oscillator (5) and a clock signal circuit (3,4,6-8) connected to tlie reference frequency source (2), which clock signal circuit adjusts the phase ofthe clock signal oscillator (5) to the phase ofthe incoming signal from the reference frequency source (2). 5 6. Device according to Claim 5, characterized in that for the system part, the clock signal oscillator (5) and the reference frequency source (2) have different frequencies. 7. Device according to Claim 5 or 6, characteπzed in that the clock 0 signal circuit comprises a register (8) in which the individual phase adjustment position for the system part in question (A,B,C,D) is writable. 8. Device according to any of Claims 5 - 7, characterized in that at least one ofthe system parts is provided with at least one adjustable delay circuit 5 (FA.FB,FC,FD1,FD2) on its input. 9. Device according to any of Claims 5 - 8. characterized in that in each system part which communicates with at least one other system part, the individual clock signal circuit (3,4.6-8) comprises: 0 a controllable phase comparator (3) which has an input connected to the reference frequency source (2), a division circuit (7) which divides the frequency ofthe intemal clock signal oscil¬ lator (5) by a number N, which is the same as the ratio between the frequency ofthe clock signal oscillator (5) and the frequency ofthe reference frequency source (2). o ς adjustable phase adjustment means (6,8), wherein the division circuit (7) and the phase adjustment means (6.8) are connected between the internal clock signal oscillator (5) and another input on the phase comparator (3) connected to phase-adjust the intemal clock signal oscillator (5). 10. Device according to any of Claims 5 - 8. characterized in that in each system part which communicates with at least one other ofthe system parts, the individual clock signal circuit (3,4,6-8) comprises: a controllable phase comparator (3) which has an input connected to the reference frequency source (2), a division circuit (7) which divides the frequency ofthe intemal clock signal oscillator (5) by a number N which is ihe same as the ratio between the frequency of the clock signal oscillator (5) and the frequency ofthe reference frequency source (2), adjustable phase adjustment means (60,80), wherein the division circuit is connected between the intemal clock signal oscillator (5) and another input on the phase comparator (3), which is connected to phase adjust the internal clock signal oscillator (5), and the phase adjustment means (60,80) is connected to the input of the phase comparator (3) which is connected to the reference frequency source (2). 11. Device according to Claim 9 or 10, characterized in that the phase adjustment means (6.8:60.80) comprises an adjustable register in a phase-controlled circuit (8;80). 12. Device according to any of Claims 9 - 11, characterized in that a filter (4), preferably ofthe bandpass or lowpass type, is connected between the phase comparator (3) and a phase adjustment input on the clock signal oscillator (5). 13. Device according to any of Claims 5 - 12, characterized in that at least one buffer memory (FD1 FD2) is connected to the input of a block in order to store incoming signals and read out the stored signal in step with and in phase with the intemal clock signal ofthe circuit. 14. Device according to any of Claims 5 - 13, characterized in that at least one buffer memory (BFU) is connected to the output of a block in order to store outgoing signal and read out the stored signal in step with a clock signal adapted for another block with which the block communicates. 15. Device according to Claim 13 or 14, characterized in that buffer memories ofthe mentioned type only are provided at blocks with a different frequency in relation to the block with which they communicate.

Inventors: SOEDERQUIST INGEMAR, SOEDERQUIST, INGEMAR
Applicants: SAAB DYNAMICS AKTIEBOLAG, SOEDERQUIST INGEMAR, SOEDERQUIST, INGEMAR
Application year: 1996
Main classification: G06F1
IPC codes: G06F1, H03K5, H03L7