Solid-state image pickup device and method of operating the same

Abstract: There is disclosed a solid-state image pickup device provided with plural blocks, each comprising at least two pixels 11 and allowing to read the signals of the pixel blocks at a high speed and without loss. The output signals of the blocks are connected in common, respectively through block buffers 83, thereby providing the maximum or minimum value of the pixels. The block buffer 83 has an input at the base of a self-biased transistor and an output in an emitter follower circuit. Also there are provided first photoelectric conversion elements for reading out the photoelectric conversion charges of respective pixels and second photoelectric conversion elements for reaching out the photoelectric conversion charges respectively in blocks, each composed of plural pixels, and the outputs of the second photoelectric conversion elements are connected in common to a common line through maximum output circuits.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a solid-state image pickup device. Related Background Art With the recent remarkable progress in the semiconductor technology, the solid-state image pickup device represented by the CCD has shown significant improvement in performance and has been applied in various products such as facsimile and scanner. In such trend, there are emerging stronger requirements for the solid-state image pickup device, not only for a higher performance such as a higher sensitivity or a higher resolving power, but also for drivability with a lower voltage. As a result, in the field of CCD, there have appeared products drivable with a 5 V power source and developments are being made to achieve drivability with a lower voltage. Also with a higher sensitivity, there is expected the application for a photodetector capable of detecting very weak light that has not been detectable and effecting signal processing on thus detected light. Also as a highly advanced ability of the solid-state image pickup device, there is required an ability to detect whether a certain light is present, and, upon detection of the light, to provide a detailed image output of the region of such light. An example of a known bipolar solid-state image pickup device is shown in Figs. 1 and 2. Fig. 1 is an equivalent circuit diagram of a unit pixel, which is composed of an NPN bipolar phototransistor 14, a pixel separating-resetting PMOS transistor 11, a base potential control capacitor 13, a three-value pulse supply terminal PR, and a bias reset supply terminal VBR. Fig. 2 shows a solid-state image pickup device consisting of a one-dimensional array of four bipolar photoelectric converting elements explained above. While a three-value pulse from a three-pulse terminal 1 is in the LOW level state, a reset pulse is supplied from a reset terminal 2 to render the PMOS transistors 11 conductive, whereby the NPN transistors 14 are reset. When the three-value pulse from the three-value pulse terminal 1 is shifted to the MIDDLE level state, the gate-source voltage VGS of the PMOS transistors 11-1 to 11-4 becomes lower than the threshold value Vth of the transistors, whereby these transistors are rendered non-conductive and a first resetting operation is completed. Then, when the reset terminal 33 is shifted to the high level state, the NMOS transistors 22 are rendered conductive and the emitters of the NPN transistors 14 are reset. Subsequently the three-value pulse terminal 1 is shifted to the high level state, whereby the bases of the NPN transistors 14 are shifted toward the forward bias state through the control capacitances 13, and, when the three-value terminal 1 is shifted to the middle level, there is initiated the accumulation of the photon charges by photoelectric conversion. Subsequently, after the lapse of a predetermined time, a transfer terminal 32 is shifted to the high level state, whereby the NMOS transistors 23 are rendered conductive, and the charges accumulated in the bases are transferred to transfer capacitances 24 by the application of a high-level pulse to the three-value pulse terminal 1. Then a horizontal shift register 29, receiving a start pulse 30 and scanning pulses 31, releases scanning signals for rendering scanning NMOS transistors 25 conductive in succession, whereby the charges of the transfer capacitances 24 are in succession transferred to an output line 42 and released to an output terminal 28 after amplification in an amplifier 41. After each signal output from the transfer capacitance 24, a reset pulse is applied to the reset terminal 27 whereby the remaining charge on the output line 42 is dissipated to the ground through an NMOS transistor 26. The image of a line can be released through the above-explained operations, and the function as an area sensor can be achieved by repeating the above-explained operations in combination with a movement of the sensor. As explained in the foregoing, the signals of the different pixels are first read into the transfer capacitances C24-1 to C24-4 and are then serially transferred to the output terminal by the function of the scanning circuit. The gain GT and the output voltage VO at the transferring operation are represented by: GT = (CT)/(CT + CH) VO = (CTVi)/(CT + CH) (i = 1, 2,...) wherein CT: capacity of transfer capacitances C24-1 to C24-4; CH: parasite capacitance including the capacity of the output line; and Vi: signal voltage stored in the transfer capacitances C24-1 to C24-4. The capacitance CH is composed of the drain capacitance and the gate overlapping capacitance of the scanning transistors 25-1 to 25-4 and the resetting transistor 26, the input capacitance of the output amplifier and the parasite capacitance of the output wiring, and is heavily dependent on the number of pixels and the manufacturing process. It is in the order of several picofarads in case of several hundred pixels. On the other hand, CT is composed of the capacitances of the MOS device and of junctions, and is designed in the order of several picofarads in the actual integrated circuit. Consequently the above-mentioned transfer gain is usually in the order of 0.3 to 0.4, and a larger gain leads to an increased cost because of an increased chip size. Consequently a gain of several times is applied in the subsequent stages if a larger signal value is required, but a sufficient gain is difficult to obtain in a low-voltage drive because of the limited input/output dynamic range. Also the image taking will not be required if the brightness of the image is low and does not reach the sensitivity of the pixels, but, if the image has a certain level of brightness, it is often required to obtain details of the illuminated area. The image detection with a line sensor under such condition requires the scanning operation over the entirety of the pixels, thus requiring a long time for the scanning operation with a large power consumption, and, if such brightness appears briefly, it is difficult to detect the brief bright area. Also in the configuration shown in Fig. 2, the time for one cycle is principally used for pixel resetting, signal read-out and serial signal transfer, and the significant part is usually used for the serial transfer. This time becomes longer with the increase in the number of pixels, and, in case of an area sensor with plural lines, most of the cycle time is occupied by the signal transfer time. Consequently, in the application for a detector for detecting the presence or absence of an image at a high speed, it is an important issue how to reduce this time. The present inventors have disclosed, in JP-A- 6-268920, that this signal transfer time can be reduced by releasing a signal averaged over plural pixels. However, in the above-mentioned invention, though the signal averaging is easy in the horizontal direction of the area sensor, it can normally be made for 2 to 4 pixels in the vertical direction, as a larger averaging leads to an increase in the chip size. Consequently an inexpensive high-speed detector has been extremely difficult to realize with an area sensor. US-A-5335008 discloses a CCD image sensing device in which pixels are arrayed in two dimensions. Each pixel is read out through an amplifying transistor to a vertical line. The signals on the vertical line are connected through a noise eliminating capacitor which, together with a clamping switch, constitutes a correlation double sampling circuit. The output of the capacitor is stored in a sample and hold circuit, and the sample and hold circuits of the vertical lines are read to horizontal output lines by a horizontal scanning circuit. EP-A-0627847 discloses a photoelectric conversion device in which each pixel includes a bipolar transistor which accumulates a photoelectric conversion signal at its base and provides an output from its emitter. Embodiments are disclosed in which the pixels are arranged in two dimensions and provide peak signals for blocks of pixels (e.g. the peak for each row of pixels and/or the peak for each column of pixels), and signals can also be read from individual pixels. SUMMARY OF THE INVENTION The present invention provides a solid-state image pick-up device as set out in claim 1. Optional features are set out in claims 2 to 18. The present invention also provides operating methods as set out in claims 19 to 22. An embodiment of the invention provides a solid-state image pickup device capable, for resolving the above-mentioned drawbacks, of outputting both an output signal obtained by pre-processing of the signals of the pixels and an output from each pixel, wherein the above-mentioned pre-processed output signal is output through output means for the signal of each pixel. Embodiments of the present invention will now be described in conjunction with the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram of a known photo-electric converting element; Fig. 2 is a circuit diagram of a known solid-state image pickup device; Fig. 3 is a schematic block diagram of an embodiment of the present invention; Fig. 3 is a block diagram showing the working principle of an embodiment of the present invention; Fig. 4 is a block diagram showing the working principle of another embodiment of the present invention; Fig. 5 is a circuit diagram of an embodiment of the present invention; Fig. 6 is a timing chart showing the functions of the embodiments shown in Figs. 5, 8 and 9; Fig. 7 is a timing chart showing other functions of the embodiments shown in Figs. 5, 8 and 9; Fig. 8 is a circuit diagram of an embodiment of the present invention; Fig. 9 is a circuit diagram of an embodiment of the present invention; Fig. 10 is a circuit diagram of a block-structured embodiment of the present invention; Fig. 11 is a circuit diagram of another block-structure embodiment of the present invention; and Figs. 12 to 16 are circuit diagrams of still other block-structured embodiments of the present invention. In the following the function and effect of a 1st embodiment will be briefly explained with reference to Fig. 3, wherein shown are unit pixels 51-1 to 51-8; transfer means 50-1 to 50-8 for storing the pixel signals of the unit pixels 51-1 to 51-8 in transfer capacitances and then serially outputting the pixel signals to an output line 55; pre-process means 52-1 to 52-8 connected to the unit pixels 51-1 to 51-8 for effecting a pre-process; buffer means 53-1 to 53-8 for buffering the signals from the pre-process means; and switching means 54-1 to 54-8 connecting the transfer means 50-1 to 50-8 with the buffer means 53-1 to 53-8. The buffer means 53-1 to 53-8 may be dispensed with if unnecessary. In the present embodiment, the signals of the unit pixels 51-1 to 51-8 are transferred to the transfer means 50-1 to 50-8 for storing the signal of each pixel, and are output to a terminal 57 through an output line 55 and an output circuit 56. Also they are subjected to a suitable pre-processing in the pre-process means 52-1 to 52-8, then transferred to the transfer means 50-1 to 50-8 through the buffer means 53-1 to 53-8, and released to the terminal 57. Naturally the unprocessed signals and the pre-processed signals have to be released in different periods. It is also possible to form the unprocessed signals and the pre-processed signals into blocks in the transfer means 50-1 to 50-8 and to output these signals by serial transfer after mixing thereof. The transfer means 50-1 to 50-8 can be realized, for example, by the transfer capacitances 24-1 to 24-4, the switch means 25-1 to 25-4 and the scanning circuit 29 shown in Fig. 2, and the pre-process circuit can be composed of an FPN (fixed pattern noise) elimination circuit utilizing a clamping circuit to be explained later. Also in a configuration shown in Fig. 4, in which components same as those in Fig. 3 are represented by same numbers, the signals pre-processed in the pre-process means 52-1 to 52-8 are buffered by the buffer means 53-1 to 53-8, and plural columns are formed into a block, of which signal is transferred to store/transfer means. This configuration allows to reduce the amount of pixel signals and to significantly reduce the cycle time, and the store/transfer circuits and the output circuit can be used in common for the unprocessed signals, so that a major increase in the chip size is not required. It is therefore possible to provide a high-speed and inexpensive solid-state image pickup device of a low power consumption by usually reading out the block signal and effecting the detecting operation based on this block signal, and reading out the signals from each pixel only when necessary. Such function will be explained in detail in the following embodiment. Fig. 5 shows a 2nd embodiment of the present invention, employing four bipolar photoelectric conversion elements shown in Fig. 1, arranged in a linear array. In Fig. 5, components equivalent to those in Fig. 2 are represented by same numbers. In addition, the present embodiment is provided, as explained in the foregoing embodiment shown in Fig. 3, with pre-processing means composed of coupling capacitances 105-1 to 105-4 and NMOS transistors 106-1 to 106-4; buffer means composed of buffer capacitances 107-1 to 107-4 and NMOS transistors 109-1 to 109-4; and switch means composed of NMOS transistors 116-1 to 116-4. In the following, the function of the present embodiment will be explained with reference to a timing chart shown in Fig. 6. First, high level pulses are supplied to terminals 205, 204 and 207 to render the NMOS transistors 109-1 to 109-4, 106-1 to 106-4 and 111-1 to 111-4 conductive. At a time T0, a low level pulse is supplied to a terminal 201 to render the PMOS transistors 101-1 to 101-4 conductive whereby the base areas of the photoelectric conversion elements are reset to a voltage given to a terminal 202 (first resetting). Then the pulse to the terminal 201 is shifted to the middle level to reduce the gate-source voltage VGS of the PMOS transistors 101-1 to 101-4 to a value not exceeding the threshold value Vth thereof, whereby these PMOS transistors are rendered non-conductive and the first resetting operation is completed. Then, at a time T1, a high level pulse is applied to a terminal 206 to render the NMOS transistors 110-1 to 110-4 conductive, whereby the emitter of the NPN transistors of the pixels is reset to a reset potential (ground in the illustrated configuration). Then, at a time T2, a high level pulse is applied to the terminal 201 to elevate the base potential of the NPN transistors by the capacitative coupling through the capacitances 102-1 to 102-4 thereby generating a forward bias between the bases and the emitters, while the PMOS transistors 101-1 to 101-4 are retained in the non-conductive state, whereby the NPN transistors 103-1 to 103-4 effect an emitter follower operation. As a result the holes on the base areas in the floating state effect recombination and the base potential is reset (second resetting operation). At a time T3 after this resetting operation, the pulse to the terminal 201 is shifted down to the middle level to shift the base potentials of the pixels downwardly , whereby a reverse bias state is generated between the bases and the emitters and an accumulating operation is thereby initiated (first accumulating operation). At a time T4 after a predetermined accumulation time, the pulse to the terminal 206 is shifted down to the low level state to render the NMOS transistors 110-1 to 110-4 non-conductive, whereby the emitters of the pixel transistors 103-1 to 103-4 and the capacitances 112-1 to 112-4 are shifted to a floating state. Then, at a time T5, a high level pulse is applied to a terminal 201 to shift the base potentials of the pixels upwardly through the capacitances 102-1 to 102-4, thereby generating a forward bias between the bases and emitters of the NPN transistors 103-1 to 103-4 of the pixels. Consequently the signals obtained by photoelectric conversion in the respective pixels and accumulated in the base areas are respectively transferred to the transfer capacitances 112-1 to 112-4 and the coupling capacitances 105-1 to 105-4. Then, at a time T6 immediately before the completion of the readout operation, the pulse to the terminal 205 is shifted down to render the NMOS transistors 109-1 to 109-4 non-conductive. Subsequently, at a time T7, the pulse to the terminal 201 is shifted down to turn off the NPN transistors 103-1 to 103-4 through the capacitances 102-1 to 102-4 whereby the readout operation is terminated. Then, at a time T8, a high level pulse is again applied to the terminal 206 to reset the emitters of the pixel NPN transistors 103-1 to 103-4 to the reset potential (ground in the illustrated configuration), whereby the voltages of the buffer capacitances 107-1 to 107-4 are shifted downwardly by the capacitative coupling of the coupling capacitances 105-1 to 105-4. There stands the following relationship between the signal V R transferred to the coupling capacitances 105-1 to 105-4 and the signal V R ' after the above-mentioned downward shifting: V R ' = -C C × V R /(C C + C T + C S ) wherein C C : capacity of the coupling capacitances 105-1 to 105-4; C T : capacity of the buffer capacitances 107-1 to 107-4; and C S : parasite capacity including the gate capcitance of the NMOS transistors 106-1 to 106-4. As the NMOS transistors 110-1 to 110-4 are turned on, the signals transferred to the transfer capacitances 112-1 to 112-4 are also reset. Then, in a period from a time T9 to T14, there are conducted operations similar to those in the period from T0 to T4, except that the NMOS transistors 109-1 to 109-4 are turned off, whereby the photoelectric conversion elements are reset and the photocarriers are accumulated (second accumulating operation). Then, at a time T14, there is executed a signal readout operation to provide signal voltages, added to the voltages obtained according to the equation (3). As a result, difference signals between the photoelectric conversion signals obtained in the first accumulation time and those obtained in the second accumulation time are stored in the buffer capacitances 107-1 to 107-4. Then, at a time T16, a high level pulse is applied to the terminal 206 to reset the transfer capacitances 112-1 to 112-4 again, and, at a time T17, a high level pulse is applied to a terminal 213 to render the NMOS transistors 116-1 to 116-4 conductive, whereby the signals in the buffer capacitances 107-1 to 107-4 are transferred to the transfer capacitances 112-1 to 112-4. Then at a time T18, the terminals 204, 207 are shifted to the low level state to turn off the NMOS transistors 106-1 to 106-4 and 111-1 to 111-4, and then the low level is applied to terminal 213 whereby the NMOS transistors 116-1 to 116-4 are rendered non-conductive. Then, starting from a time T19, a scanning circuit 130 is activated with the resetting of an output line 140, thereby serially transferring the signals of the transfer capacitances 112-1 to 112-4 to an output terminal 211, and the operations of a series are thus completed. It is also possible to eliminate the FPN (fixed pattern noise) in these operations, by selecting a very short first accumulation time to obtain a signal corresponding to the dark area, and calculating the difference of the above-mentioned signal and the signal obtained in the second accumulation. Also by selecting the same accumulation time in the first and second accumulating operations and irradiating the object with the light from a light source such as an LED in the course of the second accumulation time, there can be eliminated the component of the external light even in an outdoor situation, whereby an exact object detection can be achieved. In the foregoing there has been explained the output of the pre-processed signals, but the unprocessed signals may also be obtained according to a timing chart shown in Fig. 7. The operations shown in Fig. 7, corresponding to a partial modification of those in Fig. 6, effect two accumulations while maintaining the terminal 213 at the low level state even at the time T17 to finally provide the signals obtained in the second accumulation, so that the period from T0 to T9 may be totally dispensed with. In Fig. 7, the terminal 213 is always maintained at the low level state, whereby the NMOS transistors 116-1 to 116-4 are always in the non-conductive state. Consequently the calculation in the clamping circuits does not at all affect the transfer capacitances 112-1 to 112-4, so that, in the readout operation, the pixel signals are directly read out to the transfer capacitances 112-1 to 112-4 as in the conventional configuration, and they are not reset but are serially output by the scanning circuit 130. Such direct readout of the sensor signals is effective for improving the detecting sensitivity, for example in case of detecting an object of relatively low luminance, as in an indoor situation, since the clamping process reduces the output as represented by the equation (3). In the configuration shown in Fig. 5, the pre-processing circuit is composed of a difference calculating circuit utilizing a clamping circuit, but it is also possible, as shown in Fig. 8, to effect signal averaging among the adjacent pixels as the pre-processing, by providing retaining capacitances 118-1 to 118-8, grouped in pairs and connected respectively to the vertical output lines through switch means 117-1 to 117-4, also providing switch means for connecting the retaining capacitances between the adjacent pixels and connecting the outputs of these switch means to the emitters of the NPN transistors 103-1 to 103-4 through transfer switches 116-1 to 116-4. It is also possible to serially read the signals of different accumulation periods, as shown in Fig. 9, into the capacitances 112-1 to 112-4 and 135-1 to 135-4. Specifically, at first, the signals of an accumulation period are read into the capacitances 112-1 to 112-4 and the signals of another accumulation period are read into the capacitances 135-1 to 135-4. After the signals retained in the capacitances 112-1 to 112-4 are serially read out to the output line 140, the signals in the capacitances 135-1 to 135-4 are transferred to the capacitances 112-1 to 112-4 and output to the line 140 in the same manner. Also by arranging the pixels in a two-dimensional array in the present embodiment, it is rendered possible to store the maximum signals of the pixels in the respective vertical columns in the capacitances 135-1 to 135-4 and to output these signals at a timing different from that of output of the pixel signals. Also the pre-processing circuit may be composed of a calculation circuit utilizing an operational amplifier. Fig. 10 shows a 3rd embodiment of the present invention, wherein components equivalent to those in Figs. 1 to 9 are represented by same numbers and will not be explained further. In this embodiment the NPN transistors 103-1 to 103-4, provided in the photoelectric conversion elements, each have two emitters. One of the two emitters is connected in common among the pixels constituting a pixel block, whereby the maximum voltage of the pixels constituting the block is stored in a respective one of the buffer capacitances 107-1, 107-2. Such maximum voltages are transferred to the transfer capacitances 112-1, 112-3 and output from the terminal 211 through the function of the scanning circuit 130. The driving method of the present embodiment is similar to that explained in Fig. 6 or 7, whereby the terminal 203 is driven simultaneously with the terminal 206 to effect resetting and accumulation. Consequently, the output of each block representing the highest output level within the block, is read out, and the detecting operation is executed by this output in the ordinary state. It is also possible, based on the result of such detecting operation, to read out the signals of every pixel if necessary. As there is obtained the output of the pixel of highest output level among the plural pixels within the block, there can be achieved an improvement in the detecting precision and a significant reduction in the amount of signals, leading to a reduced cycle time and a reduction in the power consumption. Fig. 11 shows a 4th embodiment of the present invention, wherein components equivalent to those in Figs. 1 to 10 are represented by same numbers and will not be explained further. The present embodiment, corresponding to an improvement on the 3rd embodiment, provides the buffer capacitances 107-1, 107-2 at the output of the clamping circuits, with NPN transistors 108-1, 108-2 of which emitters are connected in common and further connected to a constant current source 115 and an output terminal 212. In the present embodiment, after the clamping operation, the maximum value of the signals transferred to the buffer capacitances 107-1, 107-2 is immediately output to the terminal 212 without the function of the scanning circuit 130, so that the cycle time and the power consumption can be further reduced in comparison with the 3rd embodiment. Instead of the NPN transistors employed in the present embodiment, there may be employed PNP transistors in emitter follower circuits to provide the minimum value of the block signals at the terminal 212. Consequently the present embodiment can achieve a function of detecting whether the signal is higher (or lower) than a predetermined level and then reading out the signals of the blocks or pixels based on the result of such detection according to the need so that the photoelectrically converted output can be obtained, matching the intention of photoelectric conversion. Also in Fig. 11, the buffer capacitances 107-1, 107-2 are reset to the ground potential by the NMOS transistors 109-1 and 109-2, but it is more effective for reading out small output voltages, as shown in Fig. 12, to provide a reset power source terminal 231 in order to generate a sufficient forward bias voltage between the bases and the emitters of the NPN transistors 108-1, 108-2. Also in the configuration shown in Fig. 11, the signals of the buffer capacitances 107-1, 107-2 are read out by the emitter follower circuits utilizing the constant current source 115, so that the signal voltage of the buffer capacitance declines, during a readout time TR, by: {(I0/β) × TR}/CB wherein β is the current amplification factor of the NPN transistors 108-1, 108-2, I0 is the current of the constant current source 115, and CB is the capacity of the buffer capacitance. Such loss in the signal voltage can be reduced to: {(I0/β 2 ) × TR}/CB by employing Darlington emitter follower circuits as shown in Fig. 13, and can be brought to practically zero, by selecting a current amplification factor β of about 1000, an I0 of several microamperes and a CB value of several picofarads. Fig. 14 shows a 5th embodiment of the present invention, wherein components equivalent to those in Figs. 1 to 13 are represented by same numbers and will not be explained further. In the 2nd to 4th embodiments, the buffer capacitances 107-1 to 107-4 and the transfer capacitances 112-1 to 112-4 are connected through the switches 116-1 to 116-4, so that the transfer gain, represented by: C T /(C T + C T2 + C S2 ) is in the order of 0.3 to 0.4, wherein: C T : capacity of the buffer capacitances 107-1 to 107-4; C T2 : capacity of the transfer capacitances 112-1 to 112-4; C S2 : parasite capacity between the buffer capacitances 107-1 to 107-4 including the gate capacitances of the NMOS transistors 116-1 to 116-4 and the transfer capacitances 112-1 to 112-4. In the present embodiment, the buffer capacitances 107-1, 107-2 are provided with emitter follower circuits utilizing NPN transistors 108-1, 108-2 and the outputs thereof are connected to the transfer capacitances 112-1, 112-3 through the switches 116-1, 116-2. Consequently, regardless of the capacity of the parasite capacitance C S2 the signals can be transferred to the transfer capacitances 112-1 to 112-4 almost without loss. Such configuration is effective in case the signals from the sensors are small. Fig. 15 shows a 6th embodiment of the present invention, wherein components equivalent to those in Figs. 1 to 14 are represented by same numbers and will not be explained further. The present embodiment corresponds to a combination of the 4th and 5th embodiments, wherein the emitters of the NPN transistors 108-1, 108-2 of the 5th embodiment are connected by an NMOS transistor 117 to provide the maximum block output from the terminal 212. As explained in the 4th embodiment, the signal of the buffer capacitance 107-2 can be immediately obtained as the maximum block output, and the signal of the buffer capacitance 107-1 can also be obtained by the subsequent application of a high level pulse to the terminal 214. In this manner the block outputs can be read out without loss. Fig. 16 shows an 7th embodiment of the present invention, wherein components equivalent to those in Figs. 1 to 15 are represented by same numbers and will not be explained further. The present embodiment, corresponding to a modification of the 6th embodiment, provides a two-dimensional array of the photoelectric conversion elements, wherein a block is formed by two pixels in the vertical direction and two pixels in the horizontal direction. Fig. 16 shows a 4 × 4 area sensor with 2 × 2 blocks, of which outputs are transferred through clamping circuits to the capacitances 107-1 to 107-4, while the pixel signals are transferred to the transfer capacitances 112-1 to 112-4 driven by a vertical shift register 131. Time-sequential three-level pulses are applied from a terminal 101 to control the timing of resetting and accumulation of the pixels. The vertical shift register 131, receiving clock signals and timing signals from terminals 215, 216, releases pulses signals in succession, thereby scanning the pixels by turning on and off the switches. In response to these scanning signals and the pulses supplied from various terminals, the photocarrier output signals accumulated in the bases of the NPN transistors 103-1 to 103-16, each having two emitters and constituting the pixels, are transferred to the transfer capacitances 112-1 to 112-4 and also, in a blockwise operation, to the buffer capacitances 107-1 to 107-4 through the coupling capacitances 105-1 to 105-4. Thus, in response to a high level pulse to the terminal 206, the transfer capacitances 112-1 to 112-4 are reset and the maximum block charges in the buffer capacitances 107-1 to 107-4 are transferred through the switch means 116-1 to 116-4 and output in succession from the terminal 211. Also in response to a pulse applied to the terminal 214, there can be obtained, from the terminal 212, an output corresponding to the maximum among all the 16 pixels. The present embodiment can provide a wider image pickup area than in the 6th embodiment, by the addition of the photoelectric conversion pixels and the vertical scanning circuit, thereby enabling more precise detection with a higher sensitivity. Also the average value of the vertical pixels can be obtained without additional cycle time, by forming each vertical column of the present embodiment into a block and accumulating the average of the pixel signals in a buffer capacitance. In the foregoing embodiment, the block signals are detected by the peak signals utilizing the NPN transistors 108-1, 108-2, but there may also be employed PNP transistors for detecting the minimum signals. Also these two configurations may both be employed for achieving finer detection, according to the purpose of the photoelectric conversion device. Also the foregoing embodiments have been constructed with the bipolar photoelectric conversion elements, but similar effects can also be obtained with other photoelectric conversion elements such as CMOS, CMD, AMI or FGA. As explained in the foregoing, the devices of the present embodiments, capable of releasing both output signals obtained by pre-processing of the pixel signals and output signals from each pixel, can reduce the serial transfer time by such pre-processed signal output, in addition to the signal output in the conventional scanning operation. Also the presence or absence of the image can be speedily detected, without extension of the cycle time by the addition of the signal transfer time, even in the case of a large number of pixels or in the case of an area sensor with plural rows and columns. Also the fixed pattern noise can be effectively eliminated by the clamping circuits constituting the pre-processing circuits. Also the block formation of plural columns allows to reduce the amount of pixel signals and the cycle time, and the store/transfer circuits and the output circuit can be used in common for the unprocessed signals. Thus there can be provided a high-speed and inexpensive solid-state image pickup device of a low power consumption without a major increase in the chip size.

Claims: A solid-state image pick-up device comprising: a plurality of pixels (51; 103); pre-process means (52; 105,106,109) for pre-processing signals from the pixels; and an output line (55; 140), the pixels being connected to provide signals along a first path to the said output line not via the pre-process means, and the pixels also being connected to provide signals along a second path to the pre-process means for pre-processing, said second path being distinct from said first path, characterised in that : the pre-process means are connected to provide pre-processed signals along a third path (116) to the first path and thereby to the output line, said third path being distinct from said second path. A device according to claim 1, in which the pre-process means pre-processes signals from individual pixels separately. A device according to claim 1 in which the pre-process means pre-processes signals from a plurality of pixels in combination. A device according to claim 1 in which the pre-process means performs subtraction processing on the signals. A device according to claim 1 in which the pre-process means performs averaging processing on the signals. A device according to claim 3 in which the pre-process means performs minimum or maximum peak detection processing on a group of pixels. A device according to any one of the preceding claims in which the pixels are arranged in a one-dimensional array. A device according to any one of claims 1 to 6 in which the pixels are arranged in a two-dimensional array. A device according to claim 1 comprising means (107) for storing a signal in the pre-processing means. A device according to claim 9 in which the means for storing a signal in the pre-processing means comprises a capacitance (107). A device according to claim 1 in which the pre-process means comprises a clamping circuit. A device according to any one of the preceding claims which comprises switch means (116) for blocking and unblocking the signal path from the pixels to the output line via the pre-process means. A device according to any one of the preceding claims which comprises storage means (112) for storing a signal before it is output on the output line. A device according to claim 13 in which the storage means for storing a signal before it is output on the output line comprises a capacitance (112). A device according to claim 13 or claim 14 which comprises scanning means (130) for reading out signals onto the output line in turn from a plurality of said storage means (112). A device according to any one of claims 1 to 15, in which a signal provided via the pre-process means and a signal provided not via the pre-process means are output to the output line (140) through common read-out means (113). A device according to claim 16 when dependent on any one of claims 1 to 14, comprising a plurality of said common read-out means, wherein the plurality of common read-out means are connected to the output line (140) in common and are scanned sequentially by scanning means (130). A device according to any one of the preceding claims in which each pixel comprises an NPN transistor having a first emitter connected to the first path to provide signals to the said output line not via the pre-process means and a second emitter connected to the second path to provide signals to the pre-process means. A method of operating a device according to claim 12, comprising outputting signals from the pixels along the first path not via the pre-process means when the switch means (116) has blocked the said signal path, and outputting pre-processed signals from the pre-process means along the third path when the switch means (116) has unblocked the said signal path. A method of operating a device according to claim 13, comprising dissipating charge from the storage means (112) and subsequently transferring a pre-processed signal from the pre-process means to the storage means. A method according to claim 20 in which a signal is read from a pixel to the pre-process means before the step of dissipating charge. A method of operating a device according to claim 12 in which the switch means (116) is operated to unblock the signal path for a plurality of pre-processed signals at the same time.

Inventors: UENO ISAMU, UENO, ISAMU
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1996
Main classification: H04N3
IPC codes: H04N3