MULTIPLEXING OVER TWISTED PAIRS

Abstract: A method and apparatus for transmitting and receiving signals for at least four channels between a telephone company location and a customer premises over a single twisted pair. At least four signal sources output at least four signals to a central office terminal unit or line card at the telephone company location. The line card receives and converts the at least four signals into a 288 kbps multiplexed binary signal, converts the multiplexed binary signal into a 2B1Q or 4B3T signal for transmission to the customer premises over a single twisted pair for use by a remote terminal.

Description: MULTIPLEXINGOVER TWISTEDPAIRS BACKGROUND OF THE INVENTION The present invention relates to the field of telephone communications. More particularly, in one embodiment the present invention provides a method and apparatus for transmitting and receiving information between a central office and subscriber premises for at least four channels over a single twisted pair line, thereby providing a 4:1 pair gain savings. A variety of problems exist in multiplexing telephone communication systems despite advances in the multiplexing techniques. For example, some multiplexing techniques continue to require complex and, therefore, uneconomical equipment. This equipment is particularly unsuitable for individual or small office users. Further, some systems require that the user replace existing two-wire connections with less conventional connections and/or are limited in the distance of twisted pair line over which information may be transmitted. In fact, most local switching units continue to provide a single analog signal over a single twisted pair to a typical home or office. Since copper is a limited and expensive telecommunication resource, telephone companies often encounter economic problems in providing quality telephone service to those customer service areas which experience growth in demand for service. That is, providing additional copper twisted pair lines can be very expensive and unfeasible, due to rising installation/labor costs to lay down additional cables, as well as to rising copper costs. It is desirable to have an economic and flexible ability to provide as many additional telephone service lines over a minimal number of copper twisted pair lines. This is especially true, for example, in situations where additional cables cannot be laid down or are very expensive to lay down and accordingly existing twisted pair lines must be relied upon. Since copper is a valuable telephone company resource that is often extremely expensive to provide, pair gain savings while providing the capability for increased telephone services without overprovisioning is needed. It is desirable to provide at least four channels over a single twisted pair without the use of data compression methods, so as to provide telephone service which is without service or quality limitations with a 4:1 pair gain savings in copper. SUMMARY OF THE INVENTION According to the present invention, a method and apparatus is provided to convert signals for at least four channels into multiplexed digital signals for transmission over a single twisted pair telephone line between a telephone company location and a customer premises. The present invention provides an easy to install remote terminal and central office terminal unit (e.g., a line card) to convert a single twisted pair telephone line into a more capable facility, useable for transmission and reception of digital signals representing a combination of the four channels. In a specific embodiment, the present invention provides a method of transmitting and receiving signals for at least four channels between a telephone company location and a customer premises over a single twisted pair. The present method includes steps of providing at least four telephone signals to a central office terminal unit at a telephone company location, and converting signals corresponding to the send-direction portions of the at least four telephone signals into a multiplexed binary signal, which may be 288 kbps in a 4B+D format. The present method further includes converting the multiplexed binary signal into an outgoing digital signal, and transmitting the outgoing digital signal to the customer premises over the single twisted pair. The method further includes receiving an incoming digital signal at said central office terminal unit from said customer premises over the single twisted pair, converting the incoming digital signal into a multiplexed binary signal, andconverting the multiplexed binary signal into the receive-direction portions corresponding to the at least four telephone signals. An alternative specific embodiment provides an apparatus for transmitting signals for at least four channels between a telephone company location and a customer premises over a single twisted pair. The present apparatus includes at least four signal sources outputting at least four analog signals at the telephone company location. The present apparatus also includes a line card coupled to the at least four signal sources. The line card receives and converts the at least four analog signals into an outgoing multiplexed binary signal, converts the higher rate multiplexed binary signal into an outgoing formatted digital signal for transmission to the customer premises over a single twisted pair. A further alternative specific embodiment provides a method of converting a single twisted pair into multiplexed digital use of at least four channels between a telephone company location and a customer premises. The present method includes installing a central office terminal unit, line card or the like at a telephone company location. The present central office terminal unit is adapted to receive and convert at least four telephone signals into a formatted digital signal, and adapted to transfer the formatted digital signal to a customer premises over a single twisted pair. The present method also includes installing a remote terminal at the customer premises. The present remote terminal is adapted to receive the formatted digital signal from the single twisted pair, and is adapted to convert the formatted digital signal into at least four channels for use by subscriber equipment at the customer premises. A further understanding of the nature and advantages of the present invention may be realized by reference to the specification and attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is an overall block diagram of the system according to an embodiment of the invention; Fig. 2 is a simplified block diagram of a 4-VF line card (4-VF LC) according to an embodiment of the invention; Fig. 3a is a more detailed illustration of a portion of 4-VF LC 100, according to an example of the specific embodiment; Fig. 3b is a simplified diagram of the basic frame format of the multiplexed transmission according to an embodiment of the invention; Fig. 4 is a simplified block diagram of a 4-VF remote terminal (4-VF RT) according to an embodiment of the invention; Fig. 5a is a simplified illustration of the overall hierarchy of the LC software showing the control flow of modules in the LC software according to an embodiment of the invention; Fig. 5b illustrates state diagrams for link conditions and line status according to an embodiment of the invention; Fig. 5c is a diagram of a portion of the LC software according to an embodiment of the invention; Fig. 5d illustrates a simplified flow diagram of the operation of HDSL link handler 507 according to an embodiment of the invention; Fig. 6a is a simplified illustration of the overall hierarchy of the RT software showing the control flow of modules in the RT software according to an embodiment of the invention; and Fig. 6b illustrates a portion of the RT software hierarchy involving operation of line handlers according to an embodiment of the invention. DETAILED DESCRIPTION OF SPECIFIC EMBODIMENTS I. General An improved method and apparatus for transmitting and receiving data for up to at least four telephone line connections over a single twisted pair wire are disclosed herein. The method and apparatus will find particular utility and is illustrated herein as it is applied in the transmission of multiple voice and analog data signals (which may have 200 Hz to 3.4 kHz bandwidth) over an existing twisted pair line which can be used to connect homes, offices, and the like to local switching facilities, or central offices, but the invention is not so limited. The invention will find use in a wide variety of applications where it is desired to transmit multiple voice and/or data signals over a single twisted pair including, for example, facsimile, computer data, alarms, and/or low-speed video signals, without quality or service limitations. In accordance with an embodiment of the invention, the system described herein is a 4:1 pair gain system. The system provides four channels, which may be used for four telephone channels (VF) or Message Telephone Services (MTS) (a/k/a POTS lines) , over a single copper twisted pair. According to an embodiment of the invention, the system uses 2B1Q line format to transport the signal, and is line powered. Of course, the system also may use 4B3T line format to transmit the signal. The 2B1Q line format supports four 64 kbps channels and a 32 kbps overhead channel (4B+D, the derivative Basic Rate ISDN framing format) over a high- speed digital subscriber line (HDSL) , which is a single twisted pair. The 32 kbps overhead channel implements an ISDN standard 16 kbps framing channel and a 16 kbps data (D) channel. The framing channel is used for command and indication (C & I) data and monitor signal data. The D- channel is used for maintenance messages and for out-of- band signalling codes (which in the specific embodiment are used for each VF channel to indicate idle, ring, open, battery reversals, metering, and off-hook/on-hook status used in dial pulsing) , and the like (for example, remote terminal configuration, status request, various testing, and error checking messages) . Fig. 1 is an overall block diagram of the system, according to a specific embodiment of the invention. As shown in Fig. 1, the system includes a 4- VF central office terminal (COT) unit, e.g. a line card (4-VF LC) or the like 100, connected at a telephone company location 102 (such as a central office or others) to a high-speed digital subscriber line (HDSL) 104, which is connected to a 4-VF remote terminal (4-VF RT) 106 at customer premises. Each LC-RT pair and its associated HDSL constitute a line set (LS) . Of course, 4-VF LC 100 can be placed in a local switching location, a central office, or other telephone company equipment facility at the terminus of HDSL 104, which is connected at its other terminus to 4-VF RT 106 installed at, in, or near a business, office, residence, or the like. According to an embodiment 4-VF LC 100 is easily installed by being plugged into a shelf and is compatible with equipment at the central office. 4-VF LC 100 may have a form factor similar to that of a conventional line card on a shelf at the central office, and has about a 5.25 inch height (3UI) but with a width of about an inch, i.e. the width of one dual channel line card. The line cards may be plugged into a powered backplane that provides -48 V and -48 V return of telephone company battery power. Each 4-VF LC 100 may be equipped with its own power supply circuitry which converts the telephone company battery power to produce all voltages necessary to run the line card and to line power HDSL 104, providing power to 4-VF LC 106. Alternatively, each 4-VF LC 100 may be powered via the backplane and a common single shelf power supply which converts the telephone company battery power to provide the voltages needed to run the line set. Depending on whether each 4-VF LC 100 relies on its own shelf power supply circuitry or on a common single shelf power supply with a reserve power supply, a 23 inch shelf at the central office may be provisioned with 18 line cards (or 16 line cards if the shelf is equipped with a reserve power supply card) . Similarly, a 19 inch shelf at the central office may be provisioned with 14 or 12 line cards (since a common single shelf power supply and reserve takes up two line card spaces on a shelf) . 4-VF LC 100 has a faceplate that includes four green "Line Active" light emitting diodes (LEDs) , one for each VF line, as well as having a green "HDSL Link" LED, a green "LC Self-Test" LED, and a yellow "Minor Alarm" LED showing an ALARM condition. A push button for "Lamp Test" function also may be provided on the faceplate. 4-VF RT 106 supports the connection of at least four analog POTS terminals 108, respectively connected to subscriber equipment 110. Each of several line cards 100 is connected to the exchange 112 in the central office by four analog subscriber lines 114, each analog subscriber line being a twisted pair. Each 4-VF LC 100 interfaces four loop-start VF circuits at the central office and multiplexes them onto HDSL 104, which is a single twisted pair. HDSL 104 carries 288 kbps information (four 64 kbps B-channels and 32 kbps overhead channel which includes 16 kbps framing data and 16 kbps D-channel) using 2B1Q transmission encoding. According to an embodiment of the invention, the system provides full-duplex communication for up to at least four VF channels, over a single twisted pair between the central office and the customer premises. II. Data Transmission Hardware A. LC Hardware Fig. 2 is a simplified block diagram of 4-VF LC 100 according to an embodiment of the present invention. 4-VF LC 100 includes hybrid transformers 201, amplifier circuits 203 and 205, codec filters 207, a multiplexer/framer circuit 209, a microprocessor 211, a HDSL transceiver circuit 213, a DSL transformer 215, a DSL power injection circuit 217, and a power supply circuit 219, among other elements. First, 4-VF LC 100 will be described primarily in reference to four outgoing analog signals from a telephone company location. Each of the four outgoing analog signals enters its respective hybrid transformer 201 via respective lines 114 from an exchange at the central office. Each outgoing analog signal is provided from the central office via tip (T) and ring (R) lines, i.e., a twisted pair line 114. Of course, each line 144 for a VF channel is equipped with ring detect circuitry (not shown in Fig. 2 ) coupled to microprocessor 211. Hybrid transformer 201 provides isolation, conditions, impedance matches, and separates the outgoing analog signal into send and receive-direction signals for transmission to and from the respective codec filter 207 over lines 230 and 232 respectively. In a specific embodiment, active impedance matching is used, however passive impedance matching may also be used. Hybrid transformer 201 converts the outgoing analog signals from a two-wire format into a 4- wire format. Amplifier circuits 203 provided on lines 230 amplify the signal levels of the send-direction signals of the outgoing analog signals before they enter codec filter 207 (and amplifier circuits 205 provided on lines 232 amplify the signal levels of the receive- direction signals of the outgoing analog signals before transmission from the respective codec filter 207 to the respective hybrid transformer 201) . Each codec filter 207 converts the send- direction signal of the outgoing analog signal from the hybrid transformer 215 into a send-direction pulse code modulation (PCM) encoded digital signal using a sampling rate of 8,000 times a second with 8-bits per sample. Each send-direction PCM encoded digital signal is a 64 kbps unipolar TTL binary serial bit stream that exits a corresponding codec filter 207 via a corresponding line 240. (Each codec filter 207 also converts a receive- direction PCM encoded digital signal into the receive- direction signal of the outgoing analog signal in the other direction. Each receive-direction PCM encoded digital signal is a 64 kbps unipolar TTL binary serial bit stream that enters a corresponding codec filter 207 via a corresponding line 242.) Each codec filter 207 operates on a 64 kHz clock (CLK) signal and an 8 kHz synchronization clock signal provided from multiplexer/framer circuit 209. The 8 kHz synchronization clock signal provides the timing for the send and receive operation of codec filters 207. The 64 kHz clock (CLK) signal provides clocking for taking the values of the PCM encoded digital 8-bit words per sample, 8000 times per second. Multiplexer/framer circuit 209 is coupled to each codec filter 207 via lines 240 and 242, to microprocessor 211 via lines 245, and to HDSL transceiver 213 via line 250. Multiplexer/framer circuit 209 provides clocking and data handling features. Multiplexer/framer circuit 209 receives a 288 kHz clock signal from HDSL transceiver 213. Multiplexer/framer circuit 209 divides the synchronized 288 kHz clock signal down to a 64 kHz clock signal, and generates the 8 kHz synchronization clock signal from the 64 kHz clock signal. Multiplexer/framer circuit 209 also provides the 64 kHz clock signal and the 8 kHz synchronization clock signal for use by codec filters 207. Besides clocking features, multiplexer/framer circuit 209 receives the four send-direction PCM encoded digital signals serially transmitted via lines 240 from codec filters 207 (multiplexer/framer circuit 209 also transmits four receive-direction PCM encoded digital signals in serial mode to codec filters 207 via lines 242 in the direction of the central office) . More specifically, multiplexer/framer circuit 209 multiplexes the four 64 kbps send-direction PCM encoded digital signals from codec filters 207 together with a 32 kbps overhead signal into a multiplexed binary signal over line 250. (Multiplexer/framer circuit 209 also demultiplexes the multiplexed binary signal received from the RT into four 64 kbps receive-direction PCM encoded digital signals for use in codec filters 207 and a 32 kbps overhead signal) . The 32 kbps overhead signal includes a 16 kbps framing channel and a 16 kbps D- channel. In addition to framing, the framing channel may be used for embedded operations channels (EOC) , cyclic redundancy checking (CRC), error detection, or the like. The D-channel is used for maintenance messages, for out- of-band signalling codes which are used for each VF channel to indicate idle, ringing, open, reverse battery detection, metering, off-hook/on-hook status, and the like (for example, remote terminal configuration, status request, various testing, and error checking messages) . Monitor data, ring data, and other data which microprocessor 211 polls from multiplexer/framer circuit 209 are made available to microprocessor 211 via lines 245. Line 250 is a simplified representation of the signal flow of the multiplexed transmission, between multiplexer/framer circuit 209 and HDSL transceiver 213, of the data in the four B channels and the overhead channel. The total bit rate of the multiplexed binary signal from the four 64 kbps channels and the 32 kbps overhead channel is 288 kbps. The signal flow is described in further detail below. HDSL transceiver 213 performs adaptive echo cancellation and adaptive equalization functions, as well as automatic polarity adaption, automatic gain control, and frame and bit synchronized clock recovery modes. HDSL transceiver 213 receives the 288 kbps multiplexed binary signal from multiplexer/framer circuit 209 via line 250 for conversion into an outgoing digital 2B1Q signal sent to DSL transformer 215. The outgoing digital 2B1Q signal is transmitted at an information rate of 288 kbps (i.e., a symbol rate of 144 kbaud, as a 2B1Q signal has four voltage levels with two bits of information encoded per level) . (HDSL transceiver 213 also converts an incoming digital 2B1Q signal from DSL transformer 215 into the 288 kbps multiplexed binary signal received by multiplexer/framer circuit 209.) Of course, the invention may also be adapted to use, for example, a 4B3T digital signal at a 288 kbps information rate (i.e., a symbol rate of 216 kbaud, as a 4B3T signal has three voltage levels with four bits of information encoded per level) . According to a specific embodiment, HDSL transceiver 213 uses an external 9.216 MHz voltage- controlled crystal oscillator (VCXO) to generate a master clock (MCLK) signal. The master clock signal is provided to multiplexer/framer circuit 209. Multiplexer/framer circuit 209 uses the master clock signal to provide the 8 kHz synchronization clock signal and the 64 kHz clock signal to codec filters 207. The master clock signal is also used internally by HDSL transceiver 213 to produce a 288 kbps clock signal that is provided to multiplexer/framer circuit 209. Multiplexer/framer circuit 209 generates the 8 kHz synchronization clock signal and the 64 kHz clock signal used by codec filters 207. HDSL transceiver 213 sends the outgoing digital 2B1Q signal via line 260 into DSL transformer 215 which conditions and impedance matches the outgoing digital 2B1Q signal for transmission over HDSL 104, which is a single twisted pair. The span of HDSL 104 may be up to at least 15 kilo-feet on a 26 gauge twisted pair, and may even extend up to at least 28 kilo-feet and even greater on a thicker gauge twisted pair. 4-VF LC 100 also includes a DSL power injection circuit 217 coupled to receive power from a power supply circuit 219 for injection into HDSL 104 via DSL transformer 215. In a specific embodiment, power supply circuit 219 receives -48 V and -48 V return telephone company battery power from the central office. Power supply circuit 219 converts the telephone company battery power into about -135 V and -135 V return for use by power injection circuit 217, and into about +/-5 V and +/-12 V for supplying power to various portions of 4-VF LC 100. Power injection circuit 217 receives and injects -135 V and -135 V return from power supply circuit 219 into HDSL 104 via DSL transformer 215, thereby line powering 4-VF RT 106 according to the specific embodiment. Of course, other embodiments of the invention may inject other than -135 V and -135 V return into HDSL 104. The functionality of 4-VF LC 100 is overseen by microprocessor 211. A clock provides timing information for microprocessor 211 and the other components in 4-VF LC 100 and, ultimately, 4-VF RT 106. Microprocessor 211 also performs various testing, status, and control functions. For example, status indications are provided by, for example, lights, alarms, or the like, under control of microprocessor 211. Microprocessor 211 is also coupled to control HDSL transceiver 213 via direct control leads 255. Additionally, microprocessor 211 oversees conventional Mechanized Loop Testing (MLT) functions, HDSL bypassing, line card power up and powering status, and alarm status, among others. Furthermore, when the ring detectors (not shown in Fig. 2) detect an incoming ring signal from switch lines 114 by AC coupling, microprocessor 211 sends an appropriate ring signal encoded in the line control data so as to ring a line at 4-VF RT 106. According to an aspect of the specific embodiment, codec filters 207 may be individually powered down, under the control of microprocessor 211 if a respective telephone line remains inactive (i.e. on-hook) for a certain amount of time. Incoming digital signals from HDSL 104 to the 4-VF LC 100 are processed in a similar but reverse method as the outgoing signals. In particular, an incoming 2B1Q signal enters DSL transformer 215 via HDSL 104 which isolates, conditions, and impedance matches the incoming 2B1Q signal (which is at a 288 kbps information rate, or a 144 kbaud symbol rate) for use in HDSL transceiver 213. The incoming 2B1Q signal enters HDSL transceiver 213 from DSL transformer 215 via line 260. HDSL transceiver 213 converts the incoming digital 2B1Q signal into a multiplexed binary signal at a transmission rate of 288 kbps for use in multiplexer/framer circuit 209 via line 250, as discussed above. HDSL transceiver 213 sends the multiplexed binary signal (containing data of four receive-direction PCM encoded digital signals, along with framing and messaging data) to multiplexer/framer circuit 209. Multiplexer/framer circuit 209 then demultiplexes the 288 kbps multiplexed binary signal into four separate 64 kbps receive-direction PCM encoded digital signals (which are unipolar TTL binary serial bit streams) , along with the framing and messaging signals. Each receive-direction PCM encoded digital signal enters the corresponding codec filter 207 via corresponding line 242 from multiplexer/framer circuit 209. Each codec filter 207 converts the receive-direction PCM encoded digital signal into an analog voice signal " for transmission via a corresponding line 232 to a corresponding hybrid transformer 201. Hybrid transformers 201 condition the analog voice signals and transmit the conditioned analog voice signals via lines 114 to the exchange at the central office. Examples Fig. 3a is a more detailed illustration of a portion of 4-VF LC 100, according to examples of the specific embodiment. Fig. 3a illustrates in more detail multiplexer/framer circuit 209, microprocessor 211, HDSL transceiver 213, DSL transformer 215, and HDSL 104 as discussed above for Fig. 2. Of course, Fig. 3a and accompanying text also illustrate the equivalent circuits for 4-VF RT 106. In an example of the specific embodiment, multiplexer/framer circuit 209 includes a Xilinx 3090 Programmable Gate Array (PGA) 301, coupled to an Intel R27C256 Read Only Memory (ROM) 303 via lines 305. PGA 301 performs the multiplexer/framer functions, and ROM 303 configures PGA 301 into multiplexer/framer circuitry upon power up. However, it would be noted by one of ordinary skill in the art that other types of integrated circuit (s) and the like may also be used. For example, multiplexer/framer circuit 209 may be any application specific integrated circuit (ASIC) such as a gate array, a field programmable gate array, or the like. Of course, multiplexer/framer circuit 209 can also be a variety of other integrated circuit chips, such as a custom integrated circuit chip which integrates the functionality of the present PGA 301 and ROM 303 into a single chip. As described further later, multiplexer/framer circuit 209 performs framing and multiplexing functions for the four B-channels for use by HDSL transceiver 213. In accordance with the example, microprocessor 211 is coupled to multiplexer/framer circuit 209 via UDATA bus line 307, which is a parallel 8-bit bus line. Microprocessor 211 includes a processor chip 309, a random access memory (RAM) , an erasable programmable read only memory (EPROM) , and input/output (I/O) interfaces. Processor chip 309 may be an Intel 80C31 or the like. In this example, microprocessor 211 includes a Wafer Scale Integration (WSI) Programmable Logic Device PSD411A2 (PLD) 311 to function as RAM and EPROM, as well as to provide increased input/output (I/O) capability for processor chip 309. Processor chip 309 and PLD 311 are also coupled via UDATA bus line 307, and via addressing lines 313. Processor chip 309 is coupled to an external 11.0592 MHz clock for timing purposes. PLD 311 includes various I/O lines 315 to implement microprocessor 211 functions including codec filter power down, loopback testing, LED line status indications, ring detect status, forward disconnect, and MLT testing, among others. Of course, these various functions could differ for equivalent circuitry in 4-VF RT 106. Processor chip 309 also includes various lines 317 for control signals to various components of the system, such as to PLD 311 and to HDSL transceiver 213. Of course, microprocessor 211 may be implemented with other parts, combining or separating functionalities, as well known by one of ordinary skill in the art, without departing from the scope of the invention. According to the example, UDATA bus line 307 (a three-state bus) is coupled to chip 319, which may be a Texas Instruments 74HC245 or the like. Chip 319 acts as a latch for signal flow between multiplexer/framer circuit 209 and HDSL transceiver 213, serving as an extension of a DATA bus line 321 to HDSL transceiver 213. In this example, DATA bus line 321 (also a three-state bus) is a parallel 8-bit bus line. Microprocessor 211 oversees the READ and WRITE transfer of data over the bus lines between multiplexer/framer circuit 209 and HDSL transceiver 213. HDSL transceiver 213 performs adaptive echo cancellation and adaptive equalization functions, as well as automatic polarity adaption, automatic gain control, and frame and bit synchronized clock recovery modes. HDSL transceiver 213 converts the received 288 kbps multiplexed binary signal from multiplexer/framer circuit 209 into a 2B1Q signal sent to DSL transformer 215 via line 260. In the example, HDSL transceiver 213 includes a transceiver chip 323, an analog front end 325, and an analog-to-digital (A/D) converter chip 327. Transceiver chip 323 is coupled to DATA bus line 321. Transceiver chip 323 is a Brooktree 8952, and A/D converter chip 327 is a Brooktree 8920. Analog front end 325 is coupled to transceiver chip 323 via DACOUT and /DACOUT lines 329, and via AGAINO and AGAIN1 lines 331. Analog front end 325 is coupled to A/D converter chip 327 via INP line 333, and transceiver chip 323 is coupled to A/D converter chip 327 via ADC bus line 335, which is a parallel 16-bit bus line. Analog front end 325 includes amplifying and filtering circuitry 337 for signals from lines 329. Analog front end 325 also includes a gain adjust chip 339, which is coupled to transceiver chip 323 via AGAINO and AGAIN1 lines 331. Coupled to additional amplifying and filtering (not shown) , gain adjust chip 339 makes adjustments of the gain for different loop lengths, based on control signals via AGAINO and AGAIN1 signal lines 331 from transceiver chip 323. Transceiver chip 323 determines what amount of gain is needed to handle different loop lengths. Gain adjust chip 339 also is coupled to A/D converter chip 327 via INP signal line 333. Of course, HDSL transceiver 213 may be implemented with other parts, combining or separating functionalities, as well known by one of ordinary skill in the art, without departing from the scope of the invention. For instance, the functionality of transceiver chip 323, A/D converter chip 327, gain adjust chip 339, and analog front end 325 may be combined into a custom integrated circuit chip. The signal flow through the components shown in Fig. 3a is first described with reference to signals flowing in the direction away from the central office toward 4-VF RT 106. As seen in Fig. 3a, four binary serial bit streams representing the PCM digital encoded signals of the four channels enter multiplexer/framer circuit 209 via lines 240 from codec filters 207 for framing and multiplexing. Each bit stream contains 8-bit binary PCM words, each word representing a sample of the analog signal entering the corresponding codec filter. (With a sampling rate of 8 kHz with 8-bits for a sample, each binary serial bit stream is a 64 kbps.) Multiplexer/framer circuit 209 takes the serial outputs from the four codec filters 207, stores data from the four binary bit streams, D-channel bits, and remaining overhead bits, in multiple registers. In particular, multiplexer/framer circuit 209 takes the serial outputs from four codec filters 207 and stores them. At the end of a 125 microsecond interval, multiplexer/framer circuit 209 outpulses the data from each channel in turn. At the end of the process, multiplexer/framer circuit 209 outputs two D-channel bits along with two framing bits in a 1.5 millisecond full frame format. One of the D-channel bits is dedicated to repeating the on-hook/off-hook status of each channel. The on-hook/off-hook status is repeated in real-time such that 4-VF RT 106 virtually sees the status in real-time. Multiplexer/framer circuit 209 using its stored data creates a multiplexed binary signal which is transmitted in parallel 8-bit byte segments over UDATA bus line 307. Fig. 3b illustrates the basic frame format of the multiplexed binary signal used in the system. Each basic frame 350 contains 432 bits and is 1.5 milliseconds. Eight basic frames make up a superfra e which is 12 milliseconds. In basic frame 350, bits 1-18 are framing bits used for synchronization purposes. The synchronization pattern may be a first pattern at the beginning of the superframe, or a second pattern at the beginning of any basic frame. Bits 19-426 include the 4B+D information. Each basic frame includes twelve (4B+D) elements 360x (x=l to 12) . Each element 360 includes four 8-bit samples (one 8-bit sample per B- channel) plus two bits (D-channel) . Bits 427-432 make up the remaining six overhead bits 370, to complete basic frame 350. Each basic frame in the multiplexed binary signal contains 432 bits in 1.5 milliseconds, resulting in a 288 kbps information rate. Multiplexer/framer circuit 209 transmits the multiplexed binary signal which is transmitted in parallel 8-bit byte segments over UDATA bus line 307. The 8-bit bytes are latched by chip 319 which transmits the parallel 8-bit bytes to transceiver chip 323. Bit positions 1-432 are converted by HDSL transceiver 213 into quat positions 1-216 for encoding onto the 2B1Q signal. That is, transceiver chip 323 converts the bits making up the multiplexed binary signal into the appropriate voltage levels representing the dibits of the outgoing 2B1Q signal over DACOUT and /DACOUT lines 329, which enter amplifying and filtering circuitry 337 before being transmitted via line 260 to DSL transformer 215 over HDSL 104. For signal flow in the reverse direction or toward the central office, an incoming 2B1Q signal is received by DSL transformer 215 over HDSL 104. The incoming 2B1Q signal is transmitted via line 260 to gain adjust chip 339, which transmits the 2B1Q signal over INP line 333 to A/D converter chip 327. A/D converter chip 327 performs oversampling on the 2B1Q signal to convert the voltage levels (each level representing a quat of information) of incoming 2B1Q signal via the 14-bit A/D into digital data for 288 kbps transmission to transceiver chip 323 via ADC bus line 335, which is a parallel 16-bit bus line. Transceiver chip 323 performs filtering, equalization, and signal processing on the digital data which is converted into parallel 8-bit byte format for transmission over DATA bus line 321 via chip 319 to framer/multiplexer circuit 209. PGA 301 receiving the 8-bit bytes demultiplexes the 288 kbps data stream into the four binary serial bit streams containing PCM digital signals for the four channels for transmission over lines 242 to codec filters. B. RT Hardware Fig. 4 is a simplified block diagram of 4-VF RT 106 according to a specific embodiment of the invention. 4-VF RT 106 includes system elements such as a DSL transformer 401, a power extraction circuit 403, a HDSL transceiver 405, a microprocessor 407, a multiplexer/framer circuit 409, codec filters 411, a ring generator circuit 413, subscriber loop interface circuits with protection circuits (SLIC & protection circuits) 415, and other elements. 4-VF RT 106 is coupled to HDSL 104, and also is coupled to tip (T) and ring (R) lines, i.e., twisted pair line 108. 4-VF RT 106 may be placed at the customer premises, which is often a business, residence, or the like. 4-VF RT 106 easily installs at the customer premises with use of simple line tools and the like. Details of signal flow through the system elements will first be described primarily with reference to an incoming signal received by 4-VF RT 106 from the telephone company location (or central office) . Incoming 2B1Q signal (at a 288 kbps information rate, i.e., at a 144 kbaud symbol rate) from HDSL 104 enters 4-VF RT 106 via DSL transformer 401. DSL transformer 401 isolates, conditions, and impedance matches the incoming 2B1Q signal from HDSL 104 for use at HDSL transceiver 405. Of course, the invention may also be adapted to use, for example, a 4B3T digital signal at a 288 kbps information rate (i.e., a symbol rate of 216 kbaud) . Power extraction circuit 403, coupled to DSL transformer 401, extracts line power from HDSL 104 and converts the line power into voltages for powering 4-VF RT 106. In a specific embodiment, power extraction circuit 403 receives about -135 V and -135 V return representing transmitted telephone company battery power from HDSL 104 via DSL transformer 401. Power extraction circuit 403 generates about +/-5 V, +/-12 V, -24 V, +41 V, -89 V, and -48 V used to supply power to portions of 4-VF RT 106 from the transmitted telephone company battery power. The incoming 2B1Q signal enters HDSL transceiver 405 from DSL transformer 401 via line 430. Similar to that in 4-VF LC 100, HDSL transceiver 405 performs adaptive echo cancellation and adaptive equalization functions, as well as automatic polarity adaption, automatic gain control, and .frame and bit synchronized clock recovery modes. HDSL transceiver 405 converts the 288 kbps incoming 2B1Q digital signal into a multiplexed binary signal at 288 kbps for transmission via line 440 to multiplexer/framer circuit 409. The multiplexed binary signal includes user data corresponding to receive-direction signals of the four VF channels, as well as framing and messaging data. According to a specific embodiment, HDSL transceiver 405 slaves its timing to the incoming 288 kbps bit stream by phase locking its internal clocks to the incoming 288 kbps 2B1Q signal. HDSL transceiver 405 uses an external 9.216 MHz voltage-controlled crystal oscillator (VCXO) to generate a "slaved" RT master clock (MCLK) signal, which is provided to multiplexer/framer circuit 409. The slaved RT MCLK signal is also used internally by HDSL transceiver 405 to produce a 288 kbps clock signal that is provided to multiplexer/framer circuit 409. From the slaved RT MCLK signal, HDSL transceiver 405 also provides other selected clock frequencies (such as 64 kHz and 8 kHz clocks) for use in 4-VF RT 106. Line 440 is a simplified representation of the signal flow of the multiplexed transmission, between HDSL transceiver 405 and multiplexer/framer circuit 409, of the data in the four B channels and the overhead channel. The total bit rate of the multiplexed binary signal from the four 64 kbps channels and the 32 kbps overhead channel is 288 kbps. Multiplexer/framer circuit 409 in 4-VF RT 106 operates in a similar manner as in 4-VF LC 100, and provides clocking and data handling features. Multiplexer/framer circuit 409 uses the master clock signal from HDSL transceiver 405 to provide the 8 kHz synchronization clock signals and the 64 kHz clock signal to codec filters 411. Besides clocking, multiplexer/framer circuit 409 demultiplexes the multiplexed binary signal into four 64 kbps receive- direction PCM encoded digital signals (which are unipolar TTL binary serial bit streams) , and the framing and messaging signals. (Multiplexer/framer circuit 409 also multiplexes four 64 kbps send-direction PCM encoded digital signals, the framing and messaging signals into the multiplexed binary signal.) The four 64 kbps receive-direction PCM encoded digital signals enter respective codec filters 411 via respective lines 450 from multiplexer/framer circuit 409. (The 64 kbps send-direction PCM encoded digital signals leave respective codec filters 411 via respective lines 452 to multiplexer/framer circuit 409.) Codec filters 411 relying upon the 64 kbps clock signal (Clk) provided from multiplexer/framer circuit 409 convert the receive- direction 64 kbps PCM encoded digital signals into receive-direction analog signals (codec filters 411 also convert send-direction analog signals into 64 kbps send- direction PCM encoded digital signals) . The receive-direction analog signals from codec filters 411 enter SLIC & protection circuits 415 via lines 460 (the send-direction analog signals from SLIC & protection circuits 415 enter codec filters 411 via lines 462) . Each SLIC & protection circuit 415 conditions its respective analog telephone signal for use by subscriber equipment, such as a telephone or the like. In particular, the SLIC portions convert the receive and send directions of the analog signals from a 4-wire format to a 2-wire format for use by subscriber equipment, while the protection portions supply protection of the analog telephone lines. The functionality of 4-VF RT 106 is overseen by microprocessor 407, which is similar to that in 4-VF LC 100. A clock provides timing information for microprocessor 407 and the other components in 4-VF RT 106. Microprocessor 407 also performs various testing, status, and control functions. Microprocessor 407 controls HDSL transceiver 405 via direct control leads 433. Additionally, microprocessor 407 also oversees HDSL bypassing, and ring status, among others. For example, based on an appropriate ring signal encoded in the line control data by microprocessor 211, microprocessor 407 controls ringing generator 413 to ring the appropriate telephone lines coupled to 4-VF RT 106. Also, codec filters 411 may be individually powered down, under the control of microprocessor 407 if a respective telephone line remains inactive (i.e. on-hook) for a certain amount of time. This results in power savings at the central office. Ring generator 413, which is coupled to each line 108 via relays (not shown in Fig. 4) to a ring bus 465, is only connected to a line 108 via the appropriate relay when it is desired for a phone to ring, under the direction of microprocessor 407 coupled to ring generator 413. Ring generator 413 is not active under normal states, and is activated and connected to lines 108 via appropriate relays only when a ring signal activation command is transmitted (in digital form) over HDSL 104. Power extraction circuit 403 provides general power and ring power to subscriber equipment at lines 108 at appropriate times. Outgoing signals are processed through 4-VF RT 106 in a similar but reverse method as the incoming signals. In particular, each outgoing analog signal originates at subscriber equipment via tip (T) and ring (R) lines, i.e., twisted pair line 108, and enters SLIC δ protection circuit 415. SLIC & protection circuits 415 protect and condition the outgoing analog signals from subscriber equipment. Each SLIC & protection circuit 415 performs 2-wire format to 4-wire format conversion of an outgoing analog signal, and the send-direction signals of outgoing analog signals are transmitted to codec filters 411 via lines 462. Codec filters 411 convert the send- direction analog signals into send-direction PCM digital signals (which are 64 kbps unipolar TTL binary serial bit streams) . Multiplexer/framer circuit 409 receives the 64 kbps send-direction PCM digital signals from codec filters 411 via lines 452. Multiplexer/framer circuit 409 multiplexes the four 64 kbps send-direction PCM digital signals, as well as C & I, monitor, and messaging signals, into a 288 kbps multiplexed binary signal. The multiplexed binary signal is transmitted between multiplexer/framer circuit 409 and HDSL transceiver 405 via line 440. HDSL transceiver 405 converts the 288 kbps multiplexed binary signal into a quaternary signal in the 2B1Q format at a transmission rate of 288 kbps (i.e., at a symbol rate of 144 kbaud) . The outgoing 2B1Q formatted digital signal from HDSL transceiver 405 enters DSL transformer 401 via line 430. DSL transformer 401 isolates, impedance matches, and conditions the outgoing 2B1Q digital signal for transmission over HDSL 104, which is a single twisted pair telephone line, for use at a central office location. More detailed descriptions of microprocessor 407, multiplexer/framer circuit 409, and HDSL transceiver 405 and signal flow for 4-VF RT 106 are similar to those described earlier with respect to equivalent circuitry and signal flow in 4-VF LC 100 as described in further detail in Figs. 3a-3b and accompanying text. C. LC/RT Components Without in any way limiting the scope of the invention, Table 1 provides a list of commercially available components which are useful in the operation of 4-VF LC 100 and 4-VF RT 106 according to the above embodiments. It will be apparent to those of ordinary skill in the art that the components listed in Table 1 are merely representative of those which may be used in association with the inventions herein and are provided for the purpose of facilitating assembly of an apparatus in accord with a specific embodiment of the invention. A wide variety of components readily known and available to those of ordinary skill in the art could readily be substituted or functionality could be combined or even separated. As a further example, the four codec filters may be substituted with two dual-channel codec filters or even with one four-channel codec filter. It should be noted that CMOS-based integrated circuits have been utilized where possible so as to reduce power consumption of 4-VF RT 106 in particular. Table 1 4-VF LC/RT Components HDSL transceiver Brooktree 8952; Brooktree 8920; Maxim DG409 Multiplexer/framer circuit Xilinx 3000 Series; Intel 27C256 Codec filter Fujitsu MB6021 Microprocessor Intel 80C31, 80C51, 87C51; Wafer Scale Integration (WSI) PSD411A2 Latch Texas Instruments 74HC245 SLIC (RT only) Ericsson 3764A/4 III. Software/Microprocessor Functionality According to an embodiment of the invention, the code in C programming language for 4-VF LC 100 and 4-VF RT 106 discussed above is adapted for and has been used on an Intel 80C31 processor, although it will be apparent that the invention could be applied to a wide variety of processors . LC and RT software for control and communication with Brooktree chips in the LC and RT discussed above is provided by Brooktree Corporation. According to embodiments of the invention, a general description of LC and RT software is provided below. A.LC Software Figs. 5a to 5d illustrate overall operation of the LC software. In particular, Fig. 5a is a simplified illustration of the overall hierarchy of the LC software showing the control flow of modules in the LC software according to an embodiment of the invention. As seen in Fig. 5a, the LC software includes a LC manager 501, line handlers 503, a message handler 505, a HDSL link handler 507, a remote start handler 509, an input and output (I/O) handler/driver 511, a HDSL transceiver handler 513 (i.e., Brooktree transceiver handler), a power handler 515, a framer handler 517, a framer driver 519, a performance monitor 521, a LC bypass handler 523, and a light emitting diode (LED) handler 525. Acting as the main section of the LC software, LC manager 501 is the highest level coordinator that manages the major functions performed by the LC software, such as link (i.e., when RT and LC are logically connected and exchange digital information) establishment, line signal processing, and testing. LC manager 501 initializes line handlers 503, HDSL link handler 507, and test related handlers (test related handlers will be described in later portions of the specification) . In addition, LC manager 501 resets line handlers 503, HDSL link handler 507, and test handlers when the link- goes from active to inactive. LC manager 501 includes a data base to keep track of link conditions (LINK_ACTIVE or LINK_INACTIVE) and current status of the lines (IDLE, ACTIVE, or TESTING) . When these conditions change, LC manager 501 updates the data base accordingly. HDSL link handler 505, line handler 503, and test related handlers also are able to access the data base thereby ensuring that linking, call processing, and testing do not occur at the same time for the same line. Additionally, only one of the lines may be under test at a time. Fig. 5b illustrates state diagrams for link conditions and line status. When the link becomes inactive (i.e. linked state is lost) from any state 528, LC manager 501 instructs the line handlers 503 or the test handlers to stop, as indicated by line 529. When the link is in an inactive or unlinked state 530, an unlinked test 531 may be operated until the test ends, whereby the link returns to the unlinked state 530. When the link becomes active from an inactive state, LC manager 501 instructs line handlers 503 or test handlers to start, as indicated by line 532. The link then remains in an idle state 533, until at least one of the lines is either active or testing as indicated by line 534. When any line that is in either an active or testing state 535 then becomes inactive (i.e., all lines are idle as indicated by line 536) , then the line handler or test handler returns to the idle state 533. When line N goes from an active state 537 to inactive as indicated by line 538, line N is in an idle state 539. If line N leaves the idle state 539, line N may move to either the active state 537 as shown by line 540, or move to a test state 541 as shown by line 542. If line N attempts to become active while in the test state 541, LC manager 501 instructs the appropriate line handler 503 to stop as shown by line 543, until the test is completed. Once the test is completed, LC manager 501 instructs the appropriate line handler 503 to start, as shown by line 544, so that line N which returns to the idle state 539 may move to the active state 537. As seen in Fig. 5a, line handler 503 is responsible for managing all the call processing activities for a line. There are four instances of line handler 503, one for each line. Line handler 503 monitors ring and battery conditions from input handler 511 and loop conditions from message handler 505. Line handler 503 also provides status messages of the LC to message handler 505 to be transmitted to the RT. After line handler 503 gets LC status (such as ring and battery condition) by receiving messages from input handler 511, line handler 503 calls functions in framer driver 519 to encode and transmit the signalling. Line handler 503 also gets loop conditions by receiving messages from message handler 505, performs filtering on the loop condition, then passes the loop condition to output handler 511. When an off-hook condition or ring condition has occurred on any of the lines, the corresponding line handler 503 instructs LED handler 525 to turn on the appropriate line's LED. The line handler 503 reports to LC manager 501 that the line is active. When instructed by LC manager 501 to become inactive, line handler 503 goes to an inactive state. When inactive, line handler 503 sets signaling to idle and loop to open, and also turns the line LED off and powers down the line's codec filter. Message handler 505 is responsible for implementing the protocol used to support reliable communication between the LC and RT. Fig. 5c is a diagram of a portion of the LC software according to an embodiment of the invention. As shown in Fig. 5c, message handler 505 includes three modules: a message_XMIT driver 545, a message_RCV driver 546, and a message handler 547. Message_XMIT driver 545 and message_RCV driver 546 initialize, read, and write the three first-in-first-outs (FIFOs) : READY_XMIT_FIFO, XMIT_FIFO, and RCV_FIFO. Message handler 547 receives internal messages from other handlers (such as a LC configuration handler 548, a RT model handler 549, or line handlers 503) or from LC manager 501, requesting that a message be sent over HDSL 104 from the LC to the RT. Message handler 547 assembles the received message according to the protocol and puts it into the XMIT_FIF0. Message handler 547 makes a function call to message_XMIT driver 545 which writes the XMIT_FIFO to framer driver 519 and reads RCV_FIF0. Message handler 547 checks the RCV_FIFO to determine if the acknowledge is correct. If the acknowledge is not correct, message handler 505 sends the message again, retrying up to a set maximum limit. If the acknowledge is correct, message handler 505 may consider sending an internal message to the requesting handler. Message handler 505 makes sure that only one message is sent at a time and that a correct acknowledgement is received before sending another message. A message which is ready to be sent is put into READY_XMIT_FIFO. Message_RCV driver 546 of message handler 505 may also be called by framer driver 519 to read the RCV_FIFO with a message from the RT and send out an acknowledge message in RCV_FIF0. Framer driver 519 includes an interrupt routine to handle framer transmission and reception. Framer driver 519 provides functions for line handlers 503 to access signaling information through its registers. Framer driver 519 accesses FIFOs in message handler 505, getting data from one FIFO to transmit to the RT via HDSL 104 and putting data received from the RT into another FIFO. As seen in Fig. 5a, HDSL link handler 507 performs high level coordination of handlers related to the linking process, such as HDSL transceiver handler 513, power handler 515, and framer handler 517. HDSL link handler 507 monitors the state of the DSL, power, framer, and HDSL transceiver to keep track of operation modes such as DSL linked, power failure, and frame synchronization of the system. HDSL link handler 507 ensures that framer handler 517, power handler 515, and HDSL transceiver handler 513 operate in coordination with each other. In addition to being responsible for starting and stopping framer driver 519, framer handler 517 reports framer conditions (such as framer errors) to HDSL link handler 507. Fig. 5d illustrates a simplified flow diagram of the operation of HDSL link handler 507. When LC manager 501 sets or resets the LC, HDSL link handler 507 is called at step 550. At step 552, HDSL link handler 507 first calls power handler 515. Power handler 515 is responsible for managing the supply of power to the RT, as well as running the power test at the beginning of the system set up or reset . Power handler 515 includes a power test module, which checks power injection circuit 217 for proper operation (FET test) , and a DSL short handler, which determines the condition of HDSL 104 when the power is up. Power handler 515 also responds to DSL SHORT messages while power is being applied to HDSL 104. In addition, power handler 515 indicates POWER_ON when supplying power to HDSL 104, and POWER_OFF when not supplying power. As seen in Fig. 5d, if power injection circuit 217 operates properly and the power test is otherwise passed, the process of linking the LC and RT begins with step 554, providing power to HDSL 104 and activating framer handler 517 and HDSL transceiver handler 513. HDSL link handler 507 also ensures that HDSL transceiver handler 513 and power handler 515 operate asynchronously and concurrently so that power handler 515 provides adequate power to the RT to let HDSL transceiver handler 513 start its handshaking procedure, until a linked state is reached at step 560. If power injection circuit 217 does not operate properly or the power test is otherwise not passed, then power handler 515 becomes inactive at step 556 and an appropriate error message (such as BAD_RT, DSL_SHORT, or BAD_FET) is sent to LC manager 501 at step 558. Normally, the linking operation goes through power tests, link start, and linked state. At step 562 in Fig. 5d, HDSL transceiver handler 513 ensures that the link condition is stable for a set time limit (e.g., about 500 milliseconds) before reporting it to link handler 503 at step 564. If the link condition is not stable for the set time limit, there may be link failure. At step 566, power handler 515 runs its power tests to detect if link failure has occurred. If no link failure occurred, the link time is tested again against the set time limit as in step 562. In the event of linking failure, at step 568 HDSL link handler 507 sends one of the appropriate error messages (such as DSL_FAIL, BYPASS, BAD_RT, DSL_SHORT, or BAD_DSL) to LC manager 501 to indicate the type of linking error. HDSL link handler 507 may filter the LINK_UP/LINK_DOWN condition before reporting the link condition (LINK_ACTIVE/LINK_INACTIVE respectively) to LC manager 501. Upon receiving link condition reports from HDSL link handler 507, LC Manager 501 notifies LED handler 525 of any changes in the link condition. Power handler 515 also performs functions involving LC bypass handler 523. While power is applied to HDSL 104 and a STOP_POWER message is received from HDSL link handler 507, power handler 515 removes power from HDSL 104 and places the LC in bypass mode. While power is applied to HDSL 104 and an OVER_CURRENT message is received from I/O driver 511, power handler 515 removes power from HDSL 104, places the LC into bypass mode, and additionally sends a DSL_SHORT message to HDSL link handler 507. On instruction by power handler 515, LC bypass handler 523 provides a metallic bypass under one of the following conditions: no link established, FET testing, power test failure, existence of a test request. LC bypass handler 523 also removes the metallic bypass at the request of power handler 515. When the LC is bypassed or the bypass is removed, LC manager 501 causes the bypass or bypass removal to be reported to LED handler 525. LED handler 525 manages the faceplate LEDs used to provide visible user interface to indicate the link, power, or line status. As an indication of the line set's inability to handle calls due to powering problems, LED handler 525 turns on the yellow "Minor Alarm" LED when it receives POWER_OFF from power handler 515 and LINK_INACTIVE from LC manager 501. To indicate state of attempting to link with power applied to the RT, LED handler 525 flashes the yellow "Minor Alarm" LED when it receives POWER_ON from power handler 515 and LINK_INACTIVE from LC manager 501. To show the HDSL link condition, LED handler 525 turns on the green "HDSL Link" LED when it receives LINK_ACTIVE from LC manager 501. To indicate a LC bypass, LED handler 525 flashes the "HDSL Link" LED every 500 milliseconds when it receives a report of LC bypass from LC manager 501. When instructed by the appropriate line handler 503 that line N is active, LED handler 525 turns on the "Line N" LED. When the test related handlers indicate that testing is occurring, LED handler 525 turns on the green "LC Self- Test" LED. Remote start handler 509 is used by LC manager 501 to ascertain when an RT remote start-up is being requested, by detecting when either ring or tip of HDSL 104 is grounded but not both. Remote start handler 509 also informs LC manager 501 when a phone is connected and in use, to prevent a HDSL link attempt. If current flow is detected through both the ring and tip wires of HDSL 104, remote start handler 509 tells LC manager 501 not to attempt a HDSL link at that time. If either the tip or ring wire is grounded for an interval of about 5 seconds then released, remote start handler 509 sends a message to LC bypass handler 523 to leave the bypass mode. I/O handler 511 detects signalling information from the line interface circuits in the LC and reproduces the loop condition of the RT. I/O handler 511 also provides functions to filter the signalling before reporting signalling changes to the appropriate line handler 503. I/O handler 511 also provides interface functions to turn on or off the LEDs on the faceplate. I/O handler 511 detects for lamp test buttons and toggles the LEDs for the duration of the button's depression. In addition, I/O handler provides functions to access other various input/output signals. LC software also includes an MLT test handler that supports the LC standard MLT test equipment, a watchdog driver which resets the watchdog timer periodically (for example, about every 600 milliseconds) to prevent a deadlock situation, by generating a negative pulse (the Watchdog strobe) for about at least 10 microseconds. Additionally, LC software includes LC configuration handler 548, which maintains the LC configuration information and is used to give this information to message handler 505 only when the LC is reset. Also a part of LC software, RT model handler allows the LC to check for a compatible revision level of RT, and is also a check for the RT's ability to provide an indication of its ability to function properly. LC software also includes performance monitor 521 which receives performance data of the framer and the HDSL transceiver, monitors the transmission and reception errors between the LC and RT, and causes the HDSL transceiver or the framer to be reset when needed. Performance monitor 521 becomes inactive when the link is down, as reported by HDSL link handler 507. B.RT Software Figs. 6a and Fig. 6b describe the overall operation of the RT software. In particular, Fig. 6a is a simplified illustration of the overall hierarchy of the RT software showing the control flow of modules in the RT software according to an embodiment of the invention. As seen in Fig. 6a, the RT software includes a RT manager 601, line handlers 603, a message handler 605, a HDSL link handler 607, a test supervisor 608, an input and output (I/O) handler/driver 609, ring handlers 611, a ring generator 613, SLIC drivers 615, a framer driver .617, a HDSL transceiver handler 619 (i.e., Brooktree transceiver handler) , a LC Severely Errored Seconds (SES) handler 620, a RT bypass handler 621, a framer handler 623, and a performance monitor 625. Acting as the main section of the RT software, RT manager 601 is responsible for coordinating the major functions performed by the RT software, such as link (i.e., when RT and LC are logically connected and exchange digital information) establishment, line signal processing, bypass, and test support. RT manager 601 also provides coordination for HDSL link handler 607, line handlers 603, and framer handler 623, so that the link, messaging, framer, and line signal processing may operate in a mutually exclusive manner. In addition, RT manager 601 resets all line interface related handlers including line handlers 603, ring handlers 611, and SLIC drivers 615 when the link is inactive. HDSL link handler 607, line handlers 603, and framer handler 623 may only perform as permitted by RT manager 601, and inform the status of the lines to RT manager 601 so that RT manager 601 can monitor the current line status. As seen in Fig. 6a, HDSL link handler 607 coordinates the operation of handlers related to the linking process, such as HDSL transceiver handler 619, RT bypass handler 621, and framer handler 623. The process of linking the LC and RT involves extracting power from HDSL 104 and activating framer handler 623 and HDSL transceiver handler 619. When the power is up, HDSL transceiver handler 619 loads all of the necessary parameters/registers to the HDSL transceiver for desired operation. HDSL transceiver handler 619 then participates in the handshaking procedure with its counterpart in the RT, until a linked state is reached. If a link is established, HDSL transceiver handler 619 reports the link condition (LINK_ACTIVE) to HDSL link handler 607 which in turn reports the link condition to RT manager 601. In addition, when the link is up, LC SES handler 620 which receives transmission and reception error data from message handler 605, tells HDSL transceiver handler 619 to tear down and then reestablish the link between the LC and RT if the SES exceeds a specified threshold and all the lines are not providing services. LC SES handler 620 is inactive when the link is down. If a link cannot be established, HDSL transceiver handler 619 reports the link condition (LINK_INACTIVE) and the appropriate link error codes to HDSL link handler 607. HDSL link handler 607 in turn reports the LINK_INACTIVE condition to RT manager 601. In addition, framer handler 623 reports framer conditions such as framer error conditions to HDSL link handler 607. HDSL link handler 619 monitors the reported conditions from framer handler 623 and HDSL transceiver handler 619 in order to perform re-link attempts when deemed necessary. While the HDSL is linked, HDSL link handler 619 maintains a BYPASS_OUT condition to RT bypass handler 621, and maintains a BYPASS_IN condition while not linked. On instruction by HDSL link handler 607, RT bypass handler 621 provides a metallic bypass when the HDSL link is not present . Also at the request of HDSL link handler 607, RT bypass handler 621 removes the metallic bypass periodically to attempt re-link. RT software also includes performance monitor 625 which receives performance data of the framer and the HDSL transceiver, monitors the transmission and reception errors between the LC and RT, and causes the HDSL transceiver or the framer to be reset when needed. Performance monitor 625 becomes inactive when the link is down, as reported by HDSL link handler 607. Framer driver 617 includes an interrupt routine to handle framer reception and transmission between the RT and LC. Framer driver 617 provides functions for line handlers 603 to access signaling information through its registers, in a similar manner as previously discussed for the LC software. I/O handler/driver 609 detects signalling information from the line interface circuits in the RT and reproduces the loop condition of the RT. I/O handler 609 also provides functions to filter the signalling data before reporting signalling changes to the appropriate line handler 603. In addition, I/O handler provides functions to access other various input/output signals. Fig. 6b illustrates a portion of the RT software hierarchy involving operation of line handlers 603 according to an embodiment of the invention. Once the link is up, line handler 603 manages call processing activities for a line. There are four instances of line handlers 603, ring handlers 611, SLIC drivers/handlers 615, ring detect handlers 640, and line voltage handlers 650, a respective one for each line. Line handlers 603, ring handlers 611, SLIC drivers/handlers 615, ring detect handlers 640, and line voltage handlers 650 are all inactive when the link is inactive. Upon becoming inactive, line handler 603 resets ring generator 613 and issues a LINE_N_DOWN message to the appropriate SLIC handler/driver 615. Via I/O handler 609, line handler 603 gathers RT status information including whether SLICs are detected (LINE_N_CLOSE or LINE_N_OPEN) from loop detect handlers 630 and whether a ring is detected (LINE_N_RING_ON or LINE_N_RING_OFF) from ring detect handlers 640. Loop detect handlers 630 detect the loop condition and inform the appropriate line handler 603 when a change in the loop condition occurs. Ring detect handlers 640 detect for ring condition during ring state and report changes to the ring condition to the appropriate line handler 603. Line handlers 603 also indicate to line voltage handlers 650 the line voltage condition (VBATT_ON or VBATT__OFF) so that a battery condition generator may reproduce the battery condition of the LC on the RT side. Upon receipt of LC ring condition change information from line handler 603, ring handler 611 in conjunction with ring generator 613 produces the ring signal of the LC in the RT side. Line handlers 603 maintain a database of the RT status information in order to keep track of changes in the RT status. On receiving a clock interrupt, line handler 603 assembles the RT status information, which may have changed since the last clock interrupt, into a correct format for transmission to the LC via message handler 605. Line handler 603 also analyzes the LC status messages received from the LC to monitor changes in the ring condition (RINGJDN or RINGJDFF) , metering condition (METER_ON or METERJDFF) , line polarity (V_POS or V_NEG) , and line voltage condition (VBATT DN or VBATT OFF) of the RT so that notification of the changes may be sent to the appropriate generator handlers. In addition, to reduce power drawn by the RT through the HDSL, line handler 603 sets the line voltage high to -48 V while line N is inactive (0N_H00K) , and sets the line voltage low to -24 V while line N is active (OFF_HOOK) . Line handler 603 also analyzes acknowledgement messages received from the LC by the RT to determine whether the last transmitted message requires retransmission. When a line is seized, the appropriate line handler 603 reports that the line is active (LINE_N_ACTIVE) to RT manager 601. Line handler 603 also reports to RT manager 601 if a line is inactive (LINE_N_INACTIVE) . Message handler 605 is responsible for implementing the protocol used to support reliable communication between the LC and RT, and between various software modules within the RT itself. Message handler 605 receives internal messages from line handlers 603, RT manager 601 or other handlers, requesting that a message be sent over HDSL 104 to the LC from the RT. Message handler 605 assembles the received message according to the protocol for transmission to the LC and checks for the correct acknowledgement before sending another message. Message handler 605 may also be called by framer driver 617 to read a message from the LC and send out an acknowledge message. Message handler 605 operates in a similar fashion as its counterpart in the LC, as discussed in detail above. Besides supporting tests performed at the central office, the RT software supports testing of the RT alone, as well as loopback testing. RT software includes test supervisor 608 which reports to RT manager 601 when a line is under test. Test supervisor 608 coordinates the various test handlers (compatible with for example 4Tel testing, MLT testing, VanderHoff testing) such that the line set (RT linked with LC) may be tested by one kind of test at a time. Additionally, test supervisor 608 may function so as to allow only one line to be under any kind of test at a time. RT software also includes a watchdog handler driver which resets WatchDog periodically to prevent a deadlock situation and allowing malfunctioning RT software to be reset for normal operation when needed. IV. Conclusion It is to be understood that the above description is intended to be illustrative and not restrictive. Many embodiments will be apparent to those of skill in the art upon reviewing the above description. By way of example the inventions herein have been illustrated primarily with regard to transmission of four voice signals (POTS) but they are not so limited. For example, the inventions could be applied in the transmission and reception of radio and TV signals, telephoto, teletype, facsimile, and other signals. By way of further example, the inventions have been illustrated above with reference to the simultaneous transmission of four VF signals over a single twisted pair, but the inventions could readily be extended to transmit greater than four VF signals simultaneously over a single twisted pair. Also, the present invention may be adapted to provide digital data service (DDS) by replacing some of the components of the invention such as codec filters, hybrid transformers, and SLIC circuits with alternate circuitry such as DDS interfaces or the like to provide up to 64 kbps channel data instead of voice data. Additionally, any combination of voice, DDS, or other interfaces may be used to provide any combination of voice, DDS, analog data service, and/or video signals. By way of still further example, the invention has been illustrated in conjunction with specific integrated circuits and operating speeds, but the invention is not so limited. The scope of the inventions should, therefore, be determined not with reference to the above description, but should instead be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims: WHAT IS CLAIMED IS: 1. A method of transmitting and receiving signals for at least four telephone lines between a telephone company location and a customer premises over a single twisted pair, said method comprising steps of: providing at least four telephone signals to a central office terminal unit at said telephone company location; converting signals corresponding to the send- direction portions of said at least four telephone signals into a multiplexed binary signal, the multiplexed binary signal being 288 kbps in a framed 4B+D format; converting the multiplexed binary signal into an outgoing digital signal; transmitting said outgoing digital signal from said central office terminal unit to said customer premises over said single twisted pair; receiving an incoming digital signal at said central office terminal unit from said customer premises over said single twisted pair; converting said incoming digital signal into a multiplexed binary signal; and converting the multiplexed binary signal into the receive-direction portions corresponding to said at least four telephone signals. 2. The method of claim 1 wherein said outgoing and incoming digital signals are 2B1Q signals at 144 kbaud symbol rate. 3. The method of claim 1 wherein said outgoing and incoming digital signals are 4B3T signals at 216 kbaud symbol rate. 4. The method of claim 1 wherein said central office terminal unit comprises a line card. 5. The method of claim 1 wherein said telephone signals are selected from a group consisting of voice signals, video signals, and data signals. 6. The method of claim 1 wherein said telephone signals include voice signals, video signals, and data signals. 7. The method of claim 4 wherein said single twisted pair has a span of at least 15 kilo-feet span. 8. Apparatus for transmitting and receiving signals for at least four channels between a telephone company location and a customer premises over a single twisted pair, said apparatus comprising: at least four signal sources at said telephone company location, said at least four signal sources outputting at least four analog signals; and a line card, said line card coupled to said at least four signal sources, said line card receiving said at least four analog signals for conversion into a multiplexed binary signal, converting said multiplexed binary signal into an outgoing formatted digital signal, and transmitting said outgoing formatted digital signal to said customer premises over said single twisted pair. 9. The apparatus of claim 8, said apparatus further comprising: a remote terminal, said remote terminal coupled to said single twisted pair, said remote terminal receiving said outgoing formatted digital signal for conversion to at least four analog signals for use by subscriber equipment at said customer premises. 10. The apparatus of claim 9 wherein said outgoing formatted digital signal is selected from a group consisting of a 2B1Q signal and a 4B3T signal. 11. The apparatus of claim 9 wherein said multiplexed binary signal is a 288 kbps signal that includes 4B+D and framing data. 12. The apparatus of claim 11 wherein said outgoing formatted digital signal is a 144 kbaud 2B1Q signal. 13. The apparatus of claim 11 wherein said outgoing formatted digital signal is a 216 kbaud 4B3T signal. 14. The apparatus of claim 11 wherein said single twisted pair has a span of at least about 15 kilo-feet. 15. The apparatus of claim 11 wherein said analog signals include voice signals, video signals, or data signals. 16. A method of converting a single twisted pair into multiplexed digital use of at least four channels between a telephone company location and a customer premises, said method comprising steps of: installing a central office terminal unit at said telephone company location, said unit adapted to receive and convert at least four telephone signals into a formatted digital signal, and said unit adapted to transfer said formatted digital signal to said customer premises over said single twisted pair; and installing a remote terminal at said customer premises, said remote terminal adapted to receive said formatted digital signal from said single twisted pair, and said remote terminal adapted to convert said formatted digital signal into at least four channels for use by subscriber equipment at said customer premises. 17. The method of claim 16 wherein said formatted digital signal is a 288 kbps signal that includes 4B+D and framing data. 18. The method of claim 17 wherein said formatted digital signal is a 144 kbaud 2B1Q signal. 19. The method of claim 17 wherein said formatted digital signal is a 216 kbaud 4B3T signal. 20. The method of claim 17 wherein said unit comprises a line card.

Inventors: BALATONI NICHOLAS A, BALATONI, NICHOLAS, A.
Applicants: BALATONI NICHOLAS A, RAYCHEM CORP, BALATONI, NICHOLAS, A., RAYCHEM CORPORATION
Application year: 1996
Main classification: H04L5
IPC codes: H04L5