SINGLE CHIP MICROPROCESSOR, MATH CO-PROCESSOR, RANDOM NUMBER GENERATOR, REAL-TIME CLOCK AND RAM HAVING A ONE-WIRE INTERFACE

Abstract: A secure electronic data module containing a monolithic semiconductor chip of the type having a microprocessor, a math co-processor, a random number generator, a real-time clock, a nonvolatile data memory, a program memory, and a one-wire bus interface. The monolithic semiconductor chip is protected by a combination of hardware and software mechanisms such that unauthorized access to the data stored in the memory is prevented. The monolithic semiconductor chip comprises a plurality of solder bumps for attaching the chip to a substrate that may be a printed circuit board or another chip; and a multilevel interlaced power and ground lines using minimum geometries. Large-volume data transfer over the one-wire bus between the electronic data module and a master is effectuated by using intermediate product registers in the math co-processor so that transfer time load on the microprocessor is minimized.

Description: SINGLE CHIP MICROPROCESSOR, MATH CO-PROCESSOR, RANDOM NUMBER GENERATOR, REAL-TIME CLOCK AND RAM HAVING A ONE-WIRE INTERFACE PRIORITY UNDER 35 ϋ.S.C. §119 (e) & 37 C.F.R. §1.78 (a) This nonprovisional application claims priority based upon the following prior U.S. Provisional Patent Applications: (i) entitled "Method And Apparatus For Encryption Key Creation," Serial No.: 60/001,277 (Attorney Docket Number 20661/00421), filed July 20, 1995, in the names of Wendell Little and Stephen Curry; (ii) entitled "Microcircuit With Memory That Is Protected by Both Hardware and Software," Serial No. : 60/001,279 (Attorney Docket Number 20661/00420), filed July 20, 1995, in the names of Wendell Little, Rick Fieseler, Steve Hass, and Brad Harrington; (iii) entitled "Single Chip Microprocessor, Math Co-Processor, Random Number Generator, Real-Time Clock, and RAM Having A 1-Wire Interface," Serial No.: 60/001,278 (Attorney Docket Number 20661/00423), filed July 20, 1995, in the names of Wendell Little and Andreas Curiger. CROSS-REFERENCE TO RELATED APPLICATIONS This application hereby incorporates by reference the following co-assigned patent applications, concurrently filed herewith, which describe related subject matter: Serial No. / Title Inventor(s) Docket No. 20661-00420 Microcircuit With Little, et al . Memory That Is Protected By Both Hardware And Software 20661-00421 Method and Apparatus Schweitzer, For Encryption Key et al . Creation 20661-00432 Secure Module With Little, et al. Microprocessor And Co-Processor BACKGROUND OF THE INVENTION Technical Field of the Invention The present invention relates to secure integrated circuits and, ih particular, to microcircuits with encryption capability. Description of Related Art. In today's emerging area of electronic commerce, security of data that is stored in a semiconductor memory is a burgeoning issue with which authorized owners of such data must contend. In general, authorized access to electronic data is governed by hardware and software verification schemes involving passwords, personal identification numbers and the like. To further reduce the probability of successful unauthorized access to data, component manufacturers have also resorted to such techniques as data encryption. In particular, incorporating data encryption techniques in portable data carriers has been found to be an attractive avenue in such diverse fields as electronic commerce involving electronic cash ("e-cash") transactions, access control, electronic signature authentication and verification, and software metering and monitoring. However, because many data encryption algorithms, for example, the well-known Rivest-Shamir-Adleman ("RSA") public-key algorithm, are computationally intensive owing to their mathematical requirements, present solutions involving encryption techniques in portable data carriers are beset with problems ranging from unacceptably long time periods for data transfer between a data carrier and its master to integrating cryptological computation capability within a relatively small Silicon foot-print. For example, as can be readily appreciated by those skilled in the art, the RSA system which involves an encryption transformation E{M} = M a mod n, and a decryption transformation D{C} = {E{M}} b mod n, where "a" and "n" constitute the public key and "b" and "n" constitute the private key, requires exponentiation in finite fields having extremely large numbers in order to be impervious to unauthorized deciphering. In such situations, for example, where the keys are stored within a portable data carrier, it is thus necessary to be able to transfer key data between the carrier and its master without any degraded transfer rates. Accordingly, it can be readily appreciated that there is a need for a solution that successfully combines cryptographic techniques in a data carrier system wherein: (a) data transfer time periods are not unduly degraded, and (b) the integration of cyptographic capability does not compromise the data carrier's portability. The present invention, described and claimed hereinbelow, provides such a solution by integrating into a single semiconductor chip, disposed in an electronic data module, a microprocessor or microcomputer, a co¬ processor, a random number generator, a real-time clock, a nonvolatile memory, and a one-wire interface. SUMMARY OF THE INVENTION An exemplary embodiment of the present invention comprises an 8-bit microprocessor with peripheral functions which includes random number generation capabilities, mathematical co-processing capability, real¬ time clock capability, and nonvolatile RAM capability in a single integrated circuit with a one-wire interface. In essence, the novelty of the invention includes these qualities coming together into a single product . Such a product can be encased in a small hardware and software protected container. Focusing specifically on the math co-processor, the registers of the co-processor can be loaded in a novel fashion via the one-wire interface. By loading the registers automatically through the one-wire interface, the microprocessor does not have to be heavily involved in handling the data. There is an interface between the one-wire circuitry and the intermediate product of the co¬ processor such that the co-processor can be loaded either by the microprocessor in a traditional fashion, but also by a more direct fashion for higher speed and manipulation, the co-processor can be loaded through a one-wire circuitry relationship. In an exemplary embodiment, data, which is received by the one-wire interface can proceed through a Universal Asynchronous Receiver/Transmitter ("UART") such that the data is loaded into a set of registers that the microprocessor can access. This is a traditional UART/microprocessor relationship. The exemplary embodiment, because it is handling extremely large numbers, may not operate efficiently using the traditional UART/microprocessor relationship because the UART's storage area would have to be very large in order to handle extremely large numbers. Thus, when an exemplary embodiment of the present invention is handling extremely large numbers, intermediate product registers within multiplier circuitry act as a depository of data received by the one-wire interface. The data is then directly transferred from the intermediate product registers to the co-processor. This technique avoids time loads on the UART and the microprocessor. The present invention's novel combination of microprocessor and peripheral electronic capabilities, identified above, on a single circuit die as a whole is more valuable than the individual circuits on separate dies because of the miniaturization of the overall circuity, the saving of mathematical computation time, and the lessened amount of time required for loading and writing very large numbers to and from a one-wire interface circuit and co-processor circuit. An exemplary embodiment can be contained, for example, in a useful, small portable ONE-TOUCH™ device, IBUTTON™, or MICRO-IN- A-CAN™ device and be used for sophisticated cryptographic techniques. The numeric co-processor of the present exemplary embodiment is specifically designed to accelerate the arithmetic operations required for the RSA asymmetric encryption algorithm so that the algorithm can be performed in less than a second when encrypting with a reasonably secure key size. It is understood that other encryption algorithms, such as Data Encryption Standard ("DES") , can be accomplished easily and quickly with an exemplary co-processor. In a further aspect of the present invention, the co¬ processor of the preferred embodiment is used to perform mathematical calculations with extremely large numbers (i.e. binary numbers generally greater than 1,024 bits long) . As briefly mentioned hereinabove, the RSA encryption algorithm basically requires two mathematical equations to be calculated with very large numbers. The basic equation being: a * b mod n. More specifically an encryption equation is c = m a mod n; and a decryption equation is m = c b mod n wherein "a" and "n" are part of public key and "b" is part of a private key. Thus, according to the basic equation two numbers are multiplied together (a * b) and then divided by n to thereby provide a remainder. As is known in the art, "a", "b", and "n" can all be extremely large numbers. It is understood that the RSA encryption algorithm is a known algorithm, but the implementation of the algorithm within the exemplary co¬ processor without consuming UART and microprocessor time is an important aspect of the present invention. In a yet another aspect of a presently preferred exemplary embodiment, the present invention includes a housing with a cavity, within which is disposed a substrate with a top surface and a bottom surface; a semiconductor chip of the type having a monolithic integrated microcircuit, the semiconductor chip being affixed to the substrate by a plurality of solder bumps. In a still further aspect of the present invention, the semiconductor chip comprises a multi-layered interlaced conductive grid, drawn with minimum geometry and overlaying a microcircuit, the microcircuit further comprising a microprocessor or microcomputer; a math co¬ processor; a random number generator; a real-time clock; a nonvolatile data memory; a program memory; and a one- wire interface. BRIEF DESCRIPTION OF THE DRAWINGS A more complete understanding of the present invention may be had by reference to the following Detailed Description when taken in conjunction with the accompanying Drawings wherein: FIG. 1 is a cross-section of an exemplary embodiment of an electronic data module that may be used for encasing a semiconductor chip comprising a monolithic integrated circuit with memory, a microprocessor, a co-processor, a random number generator and a real-time clock; FIG. 2 is an enlarged cross-sectional view of a presently preferred exemplary embodiment of a solder bump; FIG. 3 is a schematic diagram of a one-wire control interface for effectuating multiplexed transfer of data and power between a master and an exemplary electronic data module; FIG. 4 is a signal diagram depicting multiplexed operation of a one-wire interface between a master and an exemplary electronic data module ; FIG. 5A illustrates a functional block diagram of an exemplary embodiment of a monolithic semiconductor chip in accordance with the teachings of the present invention; FIG. 5B illustrates a functional block diagram of another exemplary embodiment of a monolithic semiconductor chip in accordance with the teachings of the present invention; FIG. 5C illustrates a functional block diagram of yet another exemplary embodiment of a monolithic semiconductor chip in accordance with the teachings of the present invention; FIG. 6 illustrates a block diagram of a one-wire Universal Asynchronous Receiver/Transmitter (UART) used in a presently preferred semiconductor chip; FIG. 7 depicts a block diagram of a co-processor optimized for modular arithmetic operations in accordance with the teachings of the present invention; and FIG. 8 depicts presently preferred memory maps of program memory, data memory and Special Function Register (SFR) memory for use in a semiconductor chip in accordance with the teachings of the present invention. DETAILED DESCRIPTION OF THE DRAWINGS Referring now to the Drawings wherein like or similar elements are designated with identical reference numerals throughout the several views, and wherein the various elements depicted are not necessarily drawn to scale, and more particularly to FIG.1, there is shown a cross- sectional view of a presently preferred exemplary embodiment of an electronic data module 100 having a semiconductor chip 135 that includes memory, a microprocessor/microcomputer, a real-time (or, true time) clock, a math co-processor, and a random number generator according to the teachings of the present invention. The electronic data module 100, which may be substantially token-shaped or button-shaped, is designed to hermetically house the monolithic semiconductor chip 135. A housing 160 of the electronic data module 100 preferably comprises a male conductive surface 110 and a female conductive surface 105 that are designed so that the male conductive surface 110 is inserted into the female conductive surface 105 which is lined with an insulator 115. In a presently preferred exemplary embodiment, both the female conductive surface 105 and the male conductive surface 110 comprise stainless steel surfaces. According to the teachings of the present invention, the monolithic semiconductor chip 135 is affixed to a substrate 130 by means of a plurality of solder bumps, for example, solder bump 140, such that a top passivated side 155 of the monolithic semiconductor chip 135 is positioned facing the substrate 130. According to the present invention, a back side or bulk side 150 of the monolithic semiconductor chip 135 is preferably encapsulated with a conventional epoxy resin (not shown) . Further, the gap 145 between the monolithic semiconductor chip 135 and the substrate 130 is also preferably filled with a conventional resinous filling medium by capillary phenomenon. Also affixed to the substrate 130 of the presently preferred exemplary electronic data module 100 are a crystal 125 to at least provide a time base, and a battery 120. It can be readily appreciated that the substrate 130 of the present invention may be a conventional printed circuit board or the like. Also, in an additional aspect of the present invention, the substrate 130 may be another semiconductor chip disposed on a printed circuit board that is affixed to the cavity created by the housing 160. In a yet another aspect, the substrate 130 may be a printed circuit board disposed on a top surface of another semiconductor chip, thereby creating a "semiconductor sandwich" in the cavity of the housing 160. FIG. 2 depicts an enlarged cross-sectional view of a presently preferred solder bump 140, a plurality of which may be used for affixing the monolithic semiconductor chip 135 to the substrate 130. It is seen that the top passivated side 155 of the monolithic semiconductor chip 135 comprises an interlaced conductive grid 305 of power and ground lines that may preferably be interspersed with a di-electric substance such as Silicon Dioxide (Si0 2 ) . Although it is shown in this FIG. that the interlaced conductive grid 305 is a single layer, it is contemplated herein that it will be obvious to persons of ordinary skill in the art to fabricate and employ a multi¬ level interlaced conductive grid to further enhance the security and integrity of electronic data computed pursuant to encryption calculations according to the teachings of the present invention. In addition, it is envisaged that the interlaced conductive grid 305, which can be either single-level, double-level, or multi-level, may be fabricated according to known processes including but not limited to sputtering of such conventional metals and compositions thereof as Aluminum, Titanium, Tungsten or Titanium-Tungsten. The interlaced conductive grid 305 is preferably fabricated using minimum design geometries, that is, minimum dimensions for lines and spaces to be used for a specific semiconductor process architecture, so as to specifically minimize at least two things. First, the probability of reaching inner conductive layers of the storage memory for the purpose of reading the logic levels corresponding to the stored data via the various conventional failure analysis techniques such as emission electron microscopy, voltage-contrast or liquid crystal methods, beam-induced current detection et cetera, is minimized because of the physical barrier that is created by the interlaced conductive grid 305. The detector circuits of these conventional techniques are designed to sense such subtle differences as associated with the presence of charge on a programmed memory cell in photon emission, or voltage, or induced current, or visible spectral phase etc. However, the presence of the interlaced conductive grid 305 effectively creates a resistive barrier that will interfere with the detection signal so that reliable reading of the logic levels of the storage memory is impeded. Furthermore, because of the tight geometries of the interlaced conductive grid 305, the probability of successfully de-layering the monolithic semiconductor chip 135, using conventional chemical etching techniques or focused-ion beam ("FIB") methods is also minimized. It will become obvious to one skilled in the art upon reference hereto that the interlaced conductive grid 305 thereby enhances the security of the data stored in the memory associated with the exemplary electronic data module 100 (shown in FIG. 1) . Continuing to refer to FIG. 2, a polyimide layer 310 covers the interlaced conductive grid 305 in the presently preferred semiconductor chip. The exemplary solder bump 140 is preferably a multi-layer structure having a Chromium layer 330 abutting the interlaced conductive grid layer 305, a Chromium-Copper alloy layer 325 deposited on the Chromium layer 330, and a Copper layer 320 deposited on the Chromium-Copper alloy layer 325. The multi-layer structure is then capped with conventional solder material 315, thereby creating the "bump," with which the semiconductor chip 135 is affixed to the substrate 130. Using a plurality of solder bumps, for example, the exemplary solder bump 140, for adhesion between the semiconductor chip 135 and the substrate 130 achieves at least two purposes. First, because of direct bonding of the semiconductor chip 135 to the substrate 130, precious board area savings are realized by ultimate reduction in packaged chip foot print. For example, in a presently preferred exemplary embodiment of the present invention, a Silicon-to-board ratio of over 40% is achieved. Second, because the monolithic semiconductor chip 135 is facing down, that is, it is "flipped" on the substrate 130, access to conductive layers of the semiconductor chip 135 by conventional de-layering is impeded. Referring now to FIG. 3, an exemplary embodiment of a one-wire control interface 205 between a master (not shown) and the electronic data module 100 is schematically depicted. While the female conductive surface 105 of the electronic data module 100 is electrically connected to a ground terminal 305, the male conductive surface 110 of the electronic data module 100 is electrically connected to a data/power terminal 300. The terminals 305 and 300, which comprise a one-wire™ bus, are electrically connectable to terminals 210 and 215, respectively, which form a portion of the one-wire control interface 205. Continuing to refer to FIG. 3, the data/power terminal 300 is connected to a one-wire UART 540 which is further connected to an N-channel Metal Oxide Semiconductor ("NMOS") transistor 295 via its gate node. As can be readily seen, while the source of the NMOS transistor 295 is connected to the ground terminal 305, its drain is connected to the data/power terminal 300. Further, a microcomputer/microprocessor 265, a co¬ processor 525, a power control block 285 and a real-time clock (or, a true time clock, as it is also known) 535 are electrically disposed on a power line 101 that is connected to the data/power terminal 300 through a parasitic diode 260 that is in parallel relationship to a low impedance P-channel Metal Oxide Semiconductor ("PMOS") transistor 290. Still continuing to refer to FIG. 3, the terminal 215 of the control interface 205 is connected via a resistor 220 and a PMOS pull-up device 225 to a power supply 224. In a presently preferred embodiment of the control interface 205, a resistance value of about 1.5 K ohms is chosen for the resistor 220. The data and power lines, 231 and 232, respectively, of the control interface 205 are connected conbinationally to logic gates 230, 235 and 240. The data line 231 and the power line 232 which is inverted by the inverter 235 are provided as inputs to the NAND gate 230. The output of the NAND gate 230 is then provided to the gate of the PMOS pull-up device 225. The inverted power line 232 is further provided to another PMOS device 255 whose source is connected to the data/power terminal 215 of the control interface. Furthermore, the data line 231 and the power line 232 are supplied as inputs to the NOR gate 240 whose output is connected to the gate of an NMOS device 250. It can be seen that the source of NMOS device 250, which is grounded, is connected to the ground terminal 210 of the control interface 205. The general operation of the electronic data module 100 can now be readily understood, taking FIGS. 3 and 4 together. The microcomputer/microprocessor 265 and the one-wire UART 540 in the electronic data module 100 are designed to operate in a multiplexed fashion via the one- wire control interface 205. Simply put, the one-wire UART 540 operates on incoming data while the microcomputer/microprocessor 265 and the co-processor 525 remain in a STOP mode, as seen in time periods B and D, shown in FIG. 4. Once data has been transferred, the microcomputer/microprocessor 265 and the co-processor 525 are enabled to process the data during the time period C, shown in FIG. 4. After the data processing has been completed, the microcomputer/microprocessor 265 and the co-processor 525 return to a low power STOP mode and the resulting data is then extracted from the one-wire UART 540 by the control interface 205 during the time period D. As can be readily appreciated, the amount of data and the required calculations associated with the data will govern the number of time periods B and C that the master and the electronic data module 100 will use to transfer and process data. Further, the time associated with period C depends on the assigned task. Power to the electronic data module 100, during the one-wire communication period, is supplied through the PMOS pull-up device 225 and the series resistor 220. To improve both the voltage and current characteristics required for computational load following the one-wire data transfer, the low impedance PMOS device 255 in the control interface 205 and the low impedance PMOS device 290 in the electronic data module 100 (as can be readily understood by those skilled in the art, the PMOS devices 255 and 290 are in series) are enabled to provide a direct connection to the power supply 224 in the master upon the completion of data transfer so that full power may be provided to the microcomputer/microprocessor 265 and the co-processor 525. Switching between parasitic power mode and full power mode is controlled in the presently preferred exemplary embodiment via at least one interrupt command following the completion of a data transfer segment. FIGS. 5A, 5B and 5C depict three architectural embodiments of the monolithic semiconductor chip 135 (shown in FIG. 1) in accordance with the teachings of the present invention. Broadly, the three embodiments include a power monitor 575, a one-wire UART 540, a true time clock (or, a real-time clock) 535, a co-processor 525, and a timed access block 520. Further, each of the three embodiments also includes a program/data pointer block 565 and an accumulator/arithmetic logic unit ("ALU") block 555 such that both blocks 565 and 555 are coupled to a data bus 500. Further, a program memory 510, which may preferably be of read-only-memory ("ROM") type, and a battery-backed nonvolatile data memory 515 are operably disposed on the data bus 500. An address bus 505 is provided for addressing the memory locations in the program memory 510 and the data memory 515. Also provided in each of the embodiments is an SFR memory 545 that is decoded by an SFR decoder 550. It can be readily seen that the SFR decoder 550 is electrically connected to the data bus 500. FIG. 8 depicts exemplary memory maps for the program memory 510, the SFR memory 545, and the data memory 515. In a presently preferred configuration, the program memory 510 is implemented as an 8K X 8 ROM, the SFR memory 545 comprises 256 bytes of static RAM ("SRAM") , and the data memory 515 is implemented as a 3K X 8 nonvolatile SRAM. Referring again to FIGS. 5A, 5B, and 5C, the true time clock 535 is connected to two crystals, 571 and 572. In a presently preferred implementation, the true time clock 535 comprises a 47-bit counter and two groups of byte-wide registers (not shown) , one group for seconds and the other for subseconds. Preferably, the true time clock 535 is not programmable, but is designed to start from an all-zero point when enabled during the manufacturing of a product embodying the present invention. The true time clock 535 is further designed to provide an alarm that is used to establish an interrupt to the chip 135 (shown in FIG. 1) to indicate that the microcomputer/microprocessor 265 (shown in FIG. 3) and the co-processor 525 are directed to enter into a STOP mode and wait for the one- wire control interface 205 (shown in FIG. 3) to begin a one-wire communication segment with the one-wire UART 540. Once the communication segment has been completed, the control interface 205 will issue an interrupt/command to restart the microcomputer/microprocessor 265 and the co¬ processor 525. Continuing to refer to FIGS. 5A, 5B and 5C, the timed access block 520, which is disposed on the data bus 500, is designed to provide system control verification of system functions which are considered vital to proper system-level operation of the semiconductor chip 135 (shown in FIG. 1) . The purpose of the timed access block 520, in presently preferred implementation, is to guarantee that the microcomputer/microprocessor 265 (shown in FIG. 3) is under system software control when writing to specific SFR control bits. The power monitor 575 monitors the presence of voltage internal to the chip 135 in the electronic data module 100. During the one-wire data transfer mode the internal voltage is supplied via the diode 260 (shown in FIG. 3) . After the microcomputer/microprocessor 265 is enabled upon completion of the data transfer segment, the internal power is directly connected to the master voltage supply 224 for effectuating full power operations such as encryption-related computations. The internal voltage is referenced against an internal bandgap reference, Vrst, such that whenever the internal voltage falls below Vrst, a RESET signal is issued to halt any program code that is being executed at that time and place the microcomputer/microprocessor 265 and the co-processor 525 in a STOP mode. The one-wire UART 540 and the co-processor 525 of the three embodiments depicted in FIGS. 5A, 5B and 5C will be described in greater detail below in specific reference to FIGS. 6 and 7, respectively. Referring now specifically to FIG. 5A and 5B, a circular redundancy check ("CRC") generator 530 and a random number generator 560 are operably disposed on the data bus 500. In presently preferred implementation, the CRC generator 530 is provided as a 16-bit CRC, although it can be appreciated that a 32-bit CRC may also be provided within the scope of the present invention. As is well-known in the art, the mechanism of memory verification of either the 16-bit CRC or 32-bit CRC is accomplished essentially in a similar manner. Continuing with FIGS. 5A and 5B, the random number generator 560 is implemented by utilizing the random power-up relationship of the electronic data module 100 for sampling the output of the true time clock 535. As the electronic data module 100 is subjected to a number of power-up and power-down conditions, the monolithic chip 135 in the electronic data module 100 will be able to accumulate a large collection of random values which can then be transmuted into a single random number having a large value, for example, a value that is expressible as a 1024-bit long binary number. As will be seen below, such large random numbers will be operated upon by the co¬ processor 525 for creating necessary keys for encryption. It can be readily appreciated that since the mathematical numbers that will be used for the modular arithmetic computations by the co-processor 525 are so large that there is no chance that the numbers will repeat themselves. The architectural embodiment depicted in FIG. 5B comprises an extension of the data bus 500 so that an emulation/test interface block 590, a multiplexed emulation address/data block 585 and a port logic block 580 are operably disposed thereon. The emulation/test interface block 590 is connected to a plurality of terminals or pads, for example, pad 596, for providing electrical control signals between an external emulation/test circuit (not shown) that may be used for testing and emulating external memory and the semiconductor chip 135 of the electronic data module 100. The emulation address/data block 585 is preferably a 8-bit multiplexed bus for providing an address/data path therebetween, of which a single pad 597 is labeled. Further, the port logic block 580 is preferably provided with three port pins, 593, 594, 595, such that the semiconductor chip 135 may be externally connectable to other known compatible electronic devices in a known manner. Referring now to FIG. 6, reference numeral 600 refers to a block diagram of a presently preferred one-wire UART 540 for use in the three architectural embodiments (shown in FIGS. 5A, 5B and 5C) of the microcircuit of the semiconductor chip 135 (shown in FIG. 1) . In one implementation for use in the embodiment shown in FIG. 5B, a one-wire-slave-UART ("OWSU") pin 630 is connected to a one-wire front end block 625 which is provided for external verification of the unique serial identification number that may preferably be provided with the microprocessor/microcomputer 265 (shown in FIG. 3) . The one-wire front end block 625 is connected to a control logic block 615 which provides overall control over full bi-directional data flow. For this purpose, the control logic block 615 is connected to an input register block 605, an output register block 610, an UART status register 620, and a microprocessor/microcomputer status register 635. Each of the input register block 605, the output register block 610, the UART status register 620, and the microprocessor/microcomputer status register 635 is further connected to the data bus 500. The control logic block 615 is further provided with a data path 650 for facilitating data transfer to an intermediate product register ("IPR") 640 in the co-processor 525. In a presently preferred embodiment, the input register block 605 and the output register block 610 are implemented as circular data buffers. Because of the data path 650 between the IPR 640 and the control logic block 615, the one-wire UART 540 allows the master (not shown) to directly load or unload data to/from the IPR 640 thereby relieving the microprocessor/microcomputer 265 from the burden of involvement with actual data transfer. However, this transfer of data must be authorized first by the microprocessor/microcomputer 265. Once the microprocessor/microcomputer 265 has given control of loading or unloading of the co-processor 525 to the UART 540, entire blocks of up to 1024 bits can be loaded or unloaded allowing a much faster data transmission via the one-wire bus. Referring now to FIG. 7, reference numeral 700 refers to a block diagram of a co-processor 525 optimized for modular arithmetic operations for use in accordance with the present invention. The long-word registers 705, 710, 715 and 640 are used for storing the modulus "n", multiplier "a", multiplicand "b" and the product "P", respectively, as computed pursuant to a known public key encryption scheme such as the RSA scheme, where the modular multiplicative relationship {P = a * b mod n} is used in a known manner. Continuing to refer to FIG. 7, the IPR 640 is connected to the data bus 500 and to a three-input adder 730. The three-input adder 730 has additionally as its inputs an output from a SHIFT block 720, and an output from an ADD block 725. Because of the iterative relationship (P(i+1) = 2 * {P(i) + a(i)*b -k*n} } , where "k" is a subtraction constant, the output from the IRP 640 is supplied as an input to an exponentiation block 735, the modulus register 705, the multiplier register 710, and the multiplicand register 715. Further, the exponentiation block 735 is in data communication with a controller/SFR block 734 which is disposed on the data bus 500. The IRP 640 is in data communication with the one-wire UART 540, via the data path 650, as discussed in detail in reference to FIG. 6, for facilitating bulk data transfer between the master (not shown) and the co-processor 525. In a presently preferred embodiment of the present invention, the co-processor 525 is able to compute a 1024- bit RSA encryption key in 1536 * 1031 = 1,583,616 clock cycles on average. From the foregoing detailed description, it can be appreciated that the present invention advantageously provides a single semiconductor chip of the type having a microprocessor/microcomputer, an optimized math co- processor, a random number generator, a real-time clock, a nonvolatile data memory, and a one-wire interface, that is suitable for portable data carrier applications with encryption requirements. It can be readily seen that although the semiconductor chip of the present invention is of such small form factor that it can be encased in an electronic data module, the chip provides computational capability required for encryption applications without degrading the data transfer time periods. This beneficial aspect of the present invention is realized because of the novel loading of the intermediate product register provided with the co-processor which facilitates high speed transmission of large volumes of encryption data. Although a preferred embodiment of the present invention has been illustrated in the accompanying Drawings and described in the foregoing Detailed Description, it will be understood that the invention is not limited to the embodiment disclosed, but is capable of numerous rearrangements, modifications and substitutions without departing from the spirit of the invention as set forth and defined by the following claims. For example, as a further enhancement to the presently preferred exemplary embodiment, it would be advantageous to structure the data memory 515 (shown in FIGS. 5A, 5B, 5C) into a plurality of segments wherein one or more segments are intentionally left vacant when the data is stored in the rest, and further wherein the data periodically migrates to the unoccupied segments. Clearly, when coupled with a combination of known hardware and software barriers, the "fluid" encryption data in the data memory 515 is even more impervious to unauthorized access. Additionally, the substrate 130 (shown in FIG. 1) can be another semiconductor chip to which the monolithic semiconductor chip 135 may be bonded via the solder bumps 140, thereby integrating security with added functionality such as, for example, increased memory capacity. It is therefore envisaged that these and other modifications and enhancements are within the scope of the present invention as set defined hereinbelow.

Claims: WHAT IS CLAIMED IS: 1. A secured data module apparatus comprising: a housing with a cavity; and a semiconductor chip comprising a monolithic integrated circuit, said semiconductor chip being disposed in said cavity of said housing. 2. The secured data module apparatus of claim 1, wherein said housing comprises a metallic container. 3. The secured data module apparatus of claim 1, wherein said monolithic integrated circuit further comprises : a microprocessor, said microprocessor being operably connected to a data bus; a co-processor, said co-processor being disposed on said data bus; a random number generator, said random number generator being disposed on said data bus; a circular redundancy check generator, said circular redundancy generator being disposed on said data bus; and a real-time clock, said real-time clock being disposed in said data bus. 4. The secured data module apparatus of claim 1, wherein said housing comprises: a first surface, said first surface having at least an electrically conductive portion; a second surface, said second surface having at least an electrically conductive portion; and an electrically nonconductive structure being disposed between said at least an electrically conductive portion of said first surface and said at least an an electrically conductive portion of said second surface. 5. The secured data module apparatus of claim 1, wherein said monolithic integrated circuit further comprises at least a memory, said at least a memory at least for storing an encryption key, said encryption key for controlling an operation, said operation being at least one of reading a value from said monolithic integrated circuit and writing a value to said monolithic integrated circuit. 6. The secured data module apparatus of claim 1, wherein said monolithic integrated circuit further comprises at least a register, said at least a register for storing a value, said at least a register being write- protected after storing a value. 7. The secured data module apparatus of claim 1, further comprising: a one-wire bus having a data line and a ground line, said one-wire bus being in an electrically conductive relationship with said housing; and a Universal-Asynchronous-Receiver-Transmitter, said Universal-Asynchronous-Receiver-Transmitter being electrically connected to said one-wire bus. 8. A system, comprising: a secured housing; and an integrated circuit having a one-wire interface disposed in said housing. 9. The system as set forth in claim 8, further comprising: a substrate, said substrate disposed in said secure housing, said integrated circuit being affixed to said substrate. 10. The system as set forth in claim 8, wherein said integrated circuit further comprises : a microprocessor, said microprocessor being operably connected to a data bus; a co-processor, said co-processor being disposed on said data bus; a random number generator, said random number generator being disposed on said data bus; a circular redundancy check generator, said circular redundancy generator being disposed on said data bus; and a real-time clock, said real-time clock being disposed in said data bus. 11. The system as set forth in claim 8, wherein said housing further comprises : a first electrically conductive surface; a second electrically conductive surface; and an electric insulator, said electric insulator being disposed between said first electrically conductive surface. 12. The system as set forth in claim 10, wherein said co-processor is optimized for a modular arithmetic operation.

Inventors: CURIGER ANDREAS, LITTLE WENDELL L, CURIGER, ANDREAS, LITTLE, WENDELL, L.
Applicants: DALLAS SEMICONDUCTOR, DALLAS SEMICONDUCTOR CORPORATION
Application year: 1996
Main classification: G06F1
IPC codes: G06F7, G06F21, G07F7, G11C5, G11C7, G11C8, H01L23, H04L9, H04L25