Phase-locked loop circuit for reproducing clock signals synchronized with transmitter in receiver

Abstract: A phase-locked loop circuit comprising a received data counter (11) for counting received clock signals reproduced according to sent data count values output from a transmitter, a subtracter (12) for subtracting the output of the received data counter (11) from an entered sent data count value, first and second attenuators (13, 14) for attenuating the output of the subtracter (12), an integrator (15) for integrating the output of the second attenuator (14), an adder (16) for adding the output of the first attenuator (13) to the output of the integrator (15), a converter (17) for converting the output of the adder (16) into the corresponding voltage signal, and a voltage control oscillator (18) that is controlled by the output of the converter (17) and outputs a received clock signal to be supplied to the received data counter (11).

Description: The present invention relates to a phase-locked loop (hereinafter referred to as the "PLL") circuit used in a receiver to reproduce clock signals synchronized with a transmitter in a communications system, in particular, to a PLL circuit for reproducing clocks from time data sent at random temporal intervals. DESCRIPTION OF THE RELATED ART As a typical means for reproducing clocks synchronized with a transmitter in a receiver in a communications system, a PLL method is used which reproduces clocks by demodulating, in the receiver, temporal data modulated and superposed on sent signals in the transmitter. The PLL method is, for example, described in document ITU-T (recommendation H.220.0). Particularly, when digital signals are used to transmit data between a transmitter and a receiver, a digital signal processing type PLL (hereinafter referred to as the "DPLL") method is applied which converts analog phase data into the corresponding digital data, then performs digital signal processing for clock reproduction. The DPLL method is, for example, described in a document, "Response of an All Digital Phase-locked Loop" (Joseph Garodnick, et al, IEEE TRANS. COMM. Vol. COM-22, No. 6, June 1974, pp751-764). The reference PROCEEDINGS OF THE IEEE, vol. 69. no.4, 1.April 1981, pages 410-431, Lindsey et al: "A Survey Of Digital Phase-Locked Loops" presents a systematic survey on several classes of DPLL implementations viewed from the analog PLL structure comprising a phase detector means, a loop filter means and an oscillator means in its basic sense. US-5,390,180 discloses a desynchronizer for a data stream in a synchronous optical network (SONET), which comprises a numerically controlled oscillator and a clock circuit for providing a desynchronized clock for smoothly adapting two data rates by using a microcontroller. The clock circuit is driven by a control signal which is generated in response of an offset signal and a count signal so as to adjust a second frequency of a desynchronized clock such that a difference between a first and a secound count is maintained at a predetermined value. This method is used to manage data buffers and tolerances in timing e.g. from the effects of regions employing different timing references. EP-0 590 323 discloses a digital implementation of a filter within a control loop, especially of a PLL, wherein the bandwidth can be digitally adjusted according to the different bandwith requirements in the dynamic and stationary states of the control process, by using a first order integrator representation. US-3,944,940 relates to a clock pulse generating system based on simple digital logic gates for recovery of binary read data from magnetic record media by using a PLL for tracking data pulses. The system comprises hardwired means for phase error detection, third order filtering and a VCO which includes a Flip-Flop at its output to produce a square wave feedback signal to the phase detection gates and to a data recovery circuit. EP-0 615 360 discloses a clock synchronizing circuit capable of producing a stable output clock signal even when the phase of an input clock signal changes or the input clock signal is interupted. This is achieved by expanding the standart PLL-structure with an digital filter comprising a decision unit for deciding between an advanced and retarded phase, an temperature compensation, clock interrupt detection and a phase and frequency compensation for generating the control signals with respect of the characteristics necessary to drive an analog VCO. The above phase-locked loop methods based on prior art including DPPL are accompanied by the problem that they cannot control phase fluctuation (jitters) that occurs in the vicinity of a sampling frequency. This means that an asynchronous communications network cannot be used as a communications network for connecting a transmitter and a receiver. For example, as shown in Fig. 9 where a transmitter and a receiver are connected via an ATM (async transfer mode) communications network 94, time data is read in the transmitter at random intervals from a timer counter 91 that counts time according to clocks with frequency fs (Hz) from a send reference clock source (OSC) 92, and sent to the ATM communications network 94 as time data 93. The time data 93 is read from the timer counter 91 at certain random intervals within Ts seconds, and its value (height) indicates elapsed time T from the previous reading. The receiver receives time data 93 as received time data 95 via the ATM communications network 94. And clocks are reproduced by a PLL circuit 96. The time when received time data 95 arrives is varied by cell delay variation (hereinafter referred to as "CDV") in the ATM communications network 94. Now that time data is expressed as 2 π fs . nT, CDV in the ATM communications network 94 appears as phase fluctuation (jitters) 97. The past DPLL circuit based on prior art cannot control such phase fluctuation and, thus, causes signal quality deterioration. An async communications network cannot, therefore, be used as a communications network for connecting a transmitter and a receiver. It is well known that a second-order PLL circuit has been developed which can implement control over same P-P value jitters. Also, a third-order PLL circuit that can reduce system pull-in time very much has been designed successfully. But, the past third-order PLL circuit that uses a dual integrator as the filter suffers the problem that it is not stable against high jitters. SUMMARY OF THE INVENTION It is the first objective of the present invention to provide a PLL circuit that can control phase fluctuation occurring in the vicinity of a sampling frequency and that can reproduce high-accuracy stable clocks even if an async communications network is used as a communications network for connecting a transmitter and a receiver. It is the second objective of the present invention to implement the stable reproduction of high-accuracy clocks as the first objective by a simple circuit configuration. It is the third objective of the present invention to provide a third-order PLL circuit that is highly stable against high jitters and that can very much reduce system pull-in time in comparison with a second-order PLL circuit implementing control over same P-P value jitters. It is the fourth objective of the present invention to implement the third-order PLL circuit as the third objective by a simple circuit configuration. According to one aspect of the invention, a phase-locked loop circuit in a receiver for reproducing clock signals synchronized with a transmitter, comprises a received data counter for counting received clock signals reproduced according to a sent data count value output from said transmitter; a subtracter for subtracting the output of said received data counter from an entered sent data count value; first and second attenuators for attenuating the output of said subtracter; an integrator for integrating the output of said second attenuator; an adder for adding the output of said first attenuator to the output of said integrator; a converter for converting the output of said adder into the corresponding voltage signal; and a voltage control oscillator that is controlled by the output of said converter and outputs said received clock signal to be supplied to said received data counter. In the preferred construction, the integrator comprises a memory circuit for temporarily storing an input signal to be output; a delay circuit for delaying the output of said memory circuit by one sample; and an adder for adding the output of said second attenuator to the output of said delay circuit for supply to said memory circuit. In another preferred construction, the received data counter has the same configuration as a timer counter for outputting time data according to reference clocks in a transmitter, and outputs time data according to received clocks generated in said voltage control oscillator. According to another aspect of the invention, a phase-locked loop circuit in a receiver for reproducing clock signals synchronized with a transmitter; comprises a received data counter for counting reproduced received clock signals according to sent data count values output from said transmitter; a subtracter for subtracting the output of said received data counter from an entered sent data count value; a first-order low-pass filter for filtering the output of said subtracter; first and second attenuators for attenuating the output of said first-order low-pass filter; an integrator for integrating the output of said second attenuator; an adder for adding the output of said first attenuator to the output of said integrator; a converter for converting the output of said adder into the corresponding voltage signal; and a voltage control oscillator that is controlled by the output of said converter and outputs said received clock signals to be supplied to said received data counter. In the preferred construction, the integrator comprises a memory circuit for temporarily storing an input signal to be output; a delay circuit for delaying the output of said memory circuit by one sample; and an adder for adding the output of said second attenuator to the output of said delay circuit for supply to said memory circuit. Also, the first-order low-pass filter comprises a plurality of delay circuits connected in series for delaying and issuing output of said subtracter in sequence and for shifting a held value to the next-stage delay circuit in sequence whenever the output of said subtracter is entered; and an adder/divider for adding and summing up the output of said subtracter and the output of said delay circuits and for dividing the result of this addition by the number of stages in said delay circuits. In another preferred construction, the first-order low-pass filter comprises a plurality of delay circuits connected in series for delaying and issuing the output of said subtracter in sequence and for shifting a held value to the next-stage delay circuit in sequence whenever the output of said subtracter is entered; and an adder/divider for adding and summing up the output of said subtracter and the output of said delay circuit and for dividing the result of this addition by the number of stages in said delay circuits; and the integrator comprises a memory circuit for temporarily storing an input signal to be output; a delay circuit for delaying the output of said memory circuit by one sample; and an adder for adding the output of said second attenuator to the output of said delay circuit for supply to said memory circuit. Also, the first-order low-pass filter comprises a delay circuit for delaying input by one sample; first multipliers for multiplying the output of said delay circuit; a subtracter for subtracting the output of said first multipliers from the output of said subtracter and for supplying the result of this subtraction to said delay circuit; an adder for adding the output of said first multipliers to the output of said subtracter; and a second multiplier for multiplying the output of said adder. In another preferred construction, the first-order low-pass filter comprises a delay circuit for delaying input by one sample; first multipliers for multiplying the output of said delay circuit; a subtracter for subtracting the output of said first multipliers from the output of said subtracter and for supplying the result of this subtraction to said delay circuit; an adder for adding the output of said first multipliers to the output of said subtracter; and a second multiplier for multiplying the output of said adder; and the integrator comprises a memory circuit for temporarily storing an input signal to be output; a delay circuit for delaying the output of said memory circuit by one sample; and an adder for adding the output of said second attenuator to the output of said delay circuit for supply to said memory circuit. Other objectives, feature and effects of the present invention will be clearly understood from the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be understood more fully from the detailed description given herebelow and from the accompanying drawings of the preferred embodiment of the invention, which, however, should not be taken to be limitative to the invention, but are for explanation and understanding only. In the drawings: Fig. 1 provides a block diagram that illustrates the configuration of a conventional PLL circuit; Fig. 2 provides a block diagram that shows the configuration of an integrator used in the first preferred embodiment; Fig. 3 provides a block diagram that illustrates the configuration of a PLL circuit as the second preferred embodiment of the present invention; Fig. 4 provides a block diagram that shows the configuration of a first-order low-pass filter used in the second preferred embodiment of the present invention; Fig. 5 illustrates frequency characteristics of the first-order low-pass filter shown in Fig. 4; Fig. 6 provides a block diagram that shows another configuration of the first-order low-pass filter used in the second preferred embodiment of the present invention; Fig. 7 illustrates frequency characteristics of the first-order low-pass filter shown in Fig. 6; Fig. 8 compares frequency response characteristics of the PLL circuits as the first and second preferred embodiments; Fig. 9 provides a conceptual schema for a typical phase synchronization system. DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiment of the present invention will be discussed hereinafter in detail with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be obvious, however, to those skilled in the art that the present invention may be practiced without these specific details. In other instance, well-known structures are not shown in detail in order to unnecessary obscure the present invention. Fig. 1 provides the block diagram that shows the phase-locked loop circuit as the first preferred embodiment of the present invention. This preferred embodiment covers a PLL circuit for a receiver in a phase synchronization system connected via an ATM communications network shown in Fig. 9. As shown in Fig. 1, the PLL circuit as the first preferred embodiment comprises a received data counter 11, a subtracter 12 which subtracts the output out of the received data counter 11 from a sent data count value in, attenuators 13 and 14 which attenuate the output of the subtracter 12, an integrator 15 which integrates the output of the attenuator 14, an adder 16 which adds the output of the attenuator 13 to the output of the integrator 15, a converter 17 which converts the output of the adder 16 into the corresponding voltage signal, and a voltage control oscillator 18 that is controlled by the output of the converter 17 and outputs a clock signal ψout (fv). In Fig. 1, only the characteristic configuration is covered, and the other general configurations are omitted. The received data counter 11 counts received clock signals ψout (fv) generated in the voltage control oscillator 18. The received data counter has the same configuration as a timer counter (see Fig. 9) that outputs time data in a transmitter according to reference clocks. The adder 12 receives sent data count value in as time data out of output signals from the transmitter acquired via an ATM communications network. Whenever a count value is received, count value out as the output of the received data counter 11 is subtracted from sent data count value in. The attenuator 13 attenuates the output of the subtracter 12 by gain k1. The attenuator 14 attenuates output Δf1 of the attenuator 13 by gain k2. The adder 16 adds output Δf1 of the attenuator 13 to output Δf2 of the integrator 17. The converter 17 converts the output of the adder 16 into the corresponding voltage signal to be output. The output of the converter 17 is held until next sent data count value in is received and a new output signal of the adder 16 is entered and converted into the corresponding voltage signal. The voltage control oscillator 18, which provides gain A, generates and outputs received clock signal ψout (fv) with a certain frequency according to a voltage signal entered from the converter 17. Fig. 2 provides the block diagram that shows the configuration of the integrator 15. As shown therein, the integrator 15 comprises a memory circuit 22 that temporarily stores an input signal to be output as Δf2, a delay circuit 23 that delays output Δf2 of the memory circuit 22 by a sampling period, and an adder 21 which adds the output of the attenuator 14 to the output of the delay circuit 23 for entry to the memory circuit 22. By the integrator, the output of the attenuator 14 is integrated in sequence, being issued as output Δf2. Next, the operation of this preferred embodiment is explained by referring to Figs. 1 and 2. When sent data count value in is received from the transmitter, count value out is read from the received data counter 11, and subtracted from sent data count value in in the subtracter 12. The result of this subtraction, or differential output e corresponding to the phase difference between sent data count value in and count value out, is entered to the attenuator 13, becoming output Δf1 attenuated by gain k1. And output Δf1 is supplied to the attenuator 14 and the adder 16. Output Δf1 of the attenuator 13 entered to the attenuator 14 is further attenuated by gain k2, and entered to the integrator 15. The result of integration by the integrator 15, or output Δf2, is obtained. In the adder 16, output Δf1 of the attenuator 13 is added to output Δf2 of the integrator 15. The result of this addition is converted by the converter 17 into the corresponding voltage signal, which is supplied to the voltage control oscillator 18. Thus, clock signal ψout (fv) with the frequency corresponding to the output of the adder 16 is reproduced and output from the voltage control oscillator 18 as a received clock. Count value out is updated in sequence in the received data counter 11 according to clock signal ψout (fv). Actually, phase transfer characteristics Y2(S) of the PLL circuit as the first preferred embodiment are obtained by the Laplace transformation of a phase ratio of in and out as expressed in formula (1). Those characteristics are transfer characteristics of the typical second-order PLL circuit. Y 2( S ) = Φ out Φ in = S k 2 + 1 1 + S k 2 + S 2 A · k 1· k 2 Damping factor ζ and angular natural frequency ω are given by formula (2). Now, transfer characteristics of the typical second-order PLL circuit are obtained as shown in formula (3). Replacing jω by S leads to formula (4) for square gain |Y(ω)| 2 . Furthermore, jitter band Bj for the PLL circuit is given by formula (5). Thus, the typical second-order PLL circuit is implemented by the first preferred embodiment shown in Figs. 1 and 2. Pull-in time Tc for the entire system, which can be considered as being the superposition of the first- and second-order loops, is given by formula (6). T1 indicates the pull-in time of the first-order loop, while T2 indicates the pull-in time of the second-order loop. Fig. 3 provides the block diagram that shows the configuration of the PLL circuit as the second preferred embodiment of the present invention. As shown therein, the PLL circuit as the second preferred embodiment comprises a received data counter 11, a subtracter 12 which subtracts output out of the received data counter 11 from sent data count value in, a first-order low-pass filter 31 that filters the output of the subtracter 12, attenuators 13 and 14 which attenuate the output of the first-order low-pass filter 31, an integrator 15 which integrates the output of the attenuator 14, an adder 16 which adds the output of the attenuator 13 to the output of the integrator 15, a converter 17 which converts the output of the adder 16 into the corresponding voltage signal, and a voltage control oscillator 18 that is controlled by the output of the converter 17 and outputs clock signal ψout (fv). Only the characteristic configuration of the preferred embodiment is covered in Fig. 1, and the other general configurations are omitted. In the above configuration, the received data counter 11, the subtracter 12, the attenuators 13 and 14, the integrator 15, the adder 16, the converter 17, and the voltage control oscillator 18 are the same as those in the first preferred embodiment shown in Fig. 1. Those components are assigned the same numbers as for the first preferred embodiment, and their explanation is omitted. Fig. 4 provides the block diagram that shows the configuration of the first-order low-pass filter 31. The first-order low-pass filter 31 covered in Fig. 4 comprises a moving average calculation circuit having delay circuits 41 to 4n connected in series and an adder/divider 40. The delay circuits 41 to 4n shift a held value to the next-stage delay circuit whenever output e of the subtracter 12 is entered. In other words, the values held in delay circuits 41 to 4n-1 are shifted to the next-stage delay circuits 42 to 4n, respectively. The adder/divider 40 adds and sums up output e of the subtracter 12 and the output of the delay circuits 41 to 4n, and divides the result by the number of stages of delay circuits 41 to 4n. Then, calculations of moving average processing are output to the attenuator 13. Fig. 5 shows frequency characteristics of the first-order low-pass filter covered in Fig. 4. Frequency fτ is expressed by the inverse of τ = n x Δt where Δt stands for the average sampling interval, or mean temporal data arrival time, and n for the number of delay circuit stages. Fig. 6 provides the block diagram that shows another configuration of the first-order low-pass filter 31. As shown in Fig. 6, the first-order low-pass filter comprises a subtracter 61, a delay circuit 62, multipliers 63, 64 and 66, and an adder 65. A value entered to the delay circuit 62 is delayed by one sample, and passed via the multipliers 63 and 64 to the subtracter 61 and the adder 65, respectively. Whenever output e of the subtracter 12 is received, the subtracter 61 subtracts the output of the multiplier 63 from output e, and supplies the result of this subtraction to the delay circuit 62 and the adder 65. Whenever output e of the subtracter 12 is received, the adder 65 adds the output of the subtracter 61 to the output of the multiplier 66, and outputs the result of this addition via the multiplier to the attenuator 13. Fig. 7 illustrates frequency characteristics of the first-order low-pass filter shown in Fig. 6. Fig. 7 tells that, if time data is periodic data, characteristics are looped back and unstable at the 1/2 point of the arrival frequency of time data. If characteristics of the first-order low-pass filter are written as H(S), phase transfer characteristics of the PLL circuit as the second preferred embodiment are expressed actually by formula (7), indicating transfer characteristics of the third-order PLL circuit. Y 3( S ) = Φ out Φ in = S k 2 + 1 1 + S k 2 + S 2 H ( S )· A · k 1· k 2 First-order low-pass cut-off characteristics H(S) are given by formula (8), where τ1 stands for a filter time constant. Now that damping factor ζ and angular natural frequency ω are given by formula (2), transfer characteristics of the third-order PLL circuit are obtained from formula (9). H ( S ) = 1 τ1· S +1 Replacing jω by S provides formula (10) for |Y(ω)| 2 . This formula can be applied practically if conditions covered in formula (11) are satisfied. In the way described above, the third-order PLL circuit can be implemented by the second preferred embodiment covered in Figs. 3, 4 and 6. Pull-in time Tc for the entire system, which can be considered as being the sum of pull-in time in subsystems, can be expressed by formula (12). Hence, the first and second preferred embodiments of the present invention provide frequency response characteristics as shown in Fig. 8. Fig. 8 shows damping factor ζ, angular natural frequency ωn and filter time constant τ1 under the same conditions. As shown in Fig. 8, while the second-order PLL circuit as the first preferred embodiment provides jitter control characteristics of 20 dB/dec in the range over the cut-off frequency, the third-order PLL circuit as the second preferred embodiment implements jitter control characteristics of 40 dB/dec. The past third-order PLL circuit that uses a dual integrator as the filter is accompanied by the problem that it is unstable against high jitters. But, the third-order PLL circuit as the second preferred embodiment is highly stable against amplitude jitters since one integrator 15 is located in the preceding stage of the converter 17 and the first-order low-pass filter is installed. Moreover, the third-order PLL circuit as the second preferred embodiment can significantly reduce system pull-in time in comparison with the second-order PLL circuit that controls same P-P value jitters. As explained above, the PLL circuit of the present invention feeds back a received data count value generated according to a reproduced received clock signal for comparison with a sent data count value in an input signal and for the timely correction of a received clock signal. Phase fluctuation (jitter) occurring in the vicinity of a sampling frequency can, therefore, be controlled. Thus, for example, even if an ATM (async transfer mode) communications network is used to connect a transmitter and a receiver, clocks can be reproduced accurately and stably. Furthermore, the integrator used to correct received clock signals comprises the memory circuit for temporarily storing input, the delay circuit for delaying output from the memory circuit by one sample, and the adder for adding an input signal and an output signal form the delay circuit for supply to the memory circuit. The PLL circuit can, therefore, be implemented by a relatively simple circuit configuration. In addition, the first-order low-pass filter for low-pass filtering the differential signal between a received data count value and a sent data count value is installed to implement the third-order PLL circuit. Hence, the third-order PLL circuit is significantly stable against high jitters, and can remarkably reduce system pull-in time in comparison with the second-order PLL circuit that can control same P-P value jitters. Moreover, since the first-order low-pass filter comprises the moving average calculation circuit having the delay circuits 41 to 4n connected in series and the adder/divider 40, the third-order PLL circuit can be implemented by a relatively simple circuit configuration. Also, the first-order low-pass filter comprises the delay circuit for delaying input by one sample, the first multiplier for multiplying the output of the delay circuit, the subtracter for subtracting the output of the first multiplier from an input signal value and for supplying the result of this subtraction to the delay circuit, the adder for adding the output of the first multiplier to the output of the subtracter, and the second multiplier for multiplying the output of the adder. The third-order PLL circuit can, therefore, be implemented by a relatively simple circuit configuration.

Claims: A third-order digital phase-locked loop circuit in a receiver for reproducing clock signals synchronized with a transmitter; comprising a loop filter means with an integrator means, an adder (16) and an oscillator means; characterized in that said loop filter means comprises a received data counter (11) for counting reproduced received clock signals, according to sent data count values output from said transmitter; a subtracter (12) for subtracting the output of said received data counter (11) from said sent data count value; a first-order low pass filter (31) used for filtering the output of said subtracter (12) ; first attenuator (13) for attenuating the output of said first-order low-pass filter (31); second attenuator (14) for attenuating the output of said first attenuator (13) ; said integrator (15) for integrating the output of said first attenuator (13); said adder (16) being for adding the output of said first attenuator (13) to the output of said integrator (15); a converter (17) for converting the output of said adder (16) into a corresponding voltage signal; said oscillator means comprising a voltage control oscillator (18) used for generating said received clock signals to be supplied to said received data counter (11) with a certain frequency according to the output of said converter (17); and a memory circuit (22) for temporarily storing an input signal to be output; a delay circuit (23) for delaying the output of said memory circuit (22) by one sample; and an adder (21) for adding the output of said second attenuator (14) to the output of said delay circuit (23) for supply to said memory circuit (22). A phase-locked loop circuit as set forth in Claim 1, said integrator (15) comprising: a memory circuit (22) for temporarily storing an input signal to be output; a delay circuit (23) for delaying the output of said memory circuit (22) by one sample; and an adder (21) for adding the output of said second attenuator (14) to the output of said delay circuit (23) for supply to said memory circuit (22). A phase-locked loop circuit as set forth in Claim 1, said first-order low-pass filter (31) comprising: a plurality of delay circuits (41-4n) connected in series for delaying and issuing output of said subtracter (12) in sequence and for shifting a held value to the next-stage delay circuit in sequence whenever the output of said subtracter is entered; and an adder/divider (40) for adding and summing up the output of said subtracter (12) and the output of said delay circuits and for dividing the result of this addition by the number of stages in said delay circuits. A phase-locked loop circuit as set forth in Claim 1, said first-order low-pass filter (31) comprising: a plurality of delay circuits (41-4n) connected in series for delaying and issuing the output of said subtracter (12) in sequence and for shifting a held value to the next-stage delay circuit in sequence whenever the output of said subtracter is entered; and an adder/divider (40) for adding and summing up the output of said subtracter (12) and the output of said delay circuit and for dividing the result of this addition by the number of stages in said delay circuits; and said integrator (15) comprising: a memory circuit (22) for temporarily storing an input signal to be output; a delay circuit (23) for delaying the output of said memory circuit (22) by one sample; and an adder (21) for adding the output of said second attenuator (14) to the output of said delay circuit (23) for supply to said memory circuit (22). A phase-locked loop circuit as set forth in Claim 1, said first-order low-pass filter (31) comprising: a delay circuit (62) for delaying input by one sample; first multipliers (63, 64) for multiplying the output of said delay circuit; a subtracter (61) for subtracting the output of said first multipliers from the output of said subtracter and for supplying the result of this subtraction to said delay circuit (62); an adder (65) for adding the output of said first multipliers to the output of said subtracter (12); and a second multiplier (66) for multiplying the output of said adder (65). A phase-locked loop circuit as set forth in Claim 1, said first-order low-pass filter (31) comprising: a delay circuit (62) for delaying input by one sample; first multipliers (63, 64) for multiplying the output of said delay circuit (62); a subtracter (61) for subtracting the output of said first multipliers from the output of said subtracter and for supplying the result of this subtraction to said delay circuit (62); an adder (65) for adding the output of said first multipliers to the output of said subtracter (61); and a second multiplier (66) for multiplying the output of said adder; and said integrator (15) comprising: a memory circuit (22) for temporarily storing an input signal to be output; a delay circuit (23) for delaying the output of said memory circuit (22) by one sample; and an adder (21) for adding the output of said second attenuator (14) to the output of said delay circuit for supply to said memory circuit (22).

Inventors: YOSHINORI ROKUGO, YOSHINORI, ROKUGO
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1996
Main classification: H03L7
IPC codes: H03L7, H04L7, H04J3