SELF-ALIGNMENT TECHNIQUE FOR SEMICONDUCTOR DEVICES

Abstract: An improved method for fabricating a semiconductor structure which may contain, for example, bipolar and CMOS devices, is disclosed which overcomes problems in the art. A method in accordance with one embodiment of the present invention may be used to self-align P+ isolation regions (28), P-wells (24), P-type base regions (34), and N+ collector contacts (38). In this improved method, the P+ isolation regions, P-wells, P-type base regions, and N+ collector contacts are defined using a single masking step (20) and are thus automatically self-aligned. Since this self-alignment eliminates several critical mask alignments (and hence several alignment tolerances), valuable die area is conserved, thereby allowing for increased component density.

Description: SELF-ALIGNMENT TECHNIQUE FOR SEMICONDUCTOR DEVICES FIELD OF THE INVENTION This invention relates a method for forming self- aligned regions in a semiconductor substrate, where the regions are used for a variety of transistor structures. BACKGROUND OF THE INVENTION One of the continuing goals of the semiconductor industry is to fabricate smaller integrated circuits at lower manufacturing costs. Any process used in the fabrication of semiconductor devices which can achieve this goal will thus be very valuable. It is often desirable to construct an integrated circuit which contains both bipolar devices and CMOS devices. In conventional processes used in the fabrication of such BiCMOS devices, the process steps of one technology are integrated into the process steps of the other technology. In one such conventional method used to fabricate, for instance, a structure containing both NPN and NMOS transistors, a P-type substrate has formed thereon an N+ buried layer and an N- epitaxial layer. In a first masking and doping step, P+ isolation regions (which electrically isolate adjacent devices) are defined and formed. In a second masking and doping step, P-wells are formed. In a third masking and doping step, P-type base regions are formed. Gates are then formed. N+ regions, suitable as collector contacts, and source/drain regions, and P+ regions suitable as contact regions and source/drain regions, are then formed in subsequent masking and doping steps. The efficient fabrication of such a device using a process as described above requires precise alignment of the various masks used to define and form the P+ isolation regions, P-wells, P-type base regions, and N+ regions. Each masking step requires that an alignment tolerance be factored into the lateral dimensions of the semiconductor structure. These alignment tolerances, each of which may be on the order of 1-2 μm, are necessary to compensate for alignment errors. In the case of a complex BiCMOS process where a high component density is desired, these alignment tolerances become more significant and undesirably increase the lateral dimensions of the semiconductor structure, thereby resulting in a wasting of valuable die area. SUMMARY An improved method for fabricating a semiconductor structure which may contain, for example, bipolar and CMOS devices, is disclosed which overcomes problems in the art discussed above. A method in accordance with one embodiment of the present invention may be used to self-align P+ isolation regions, P-wells, P-type base regions, and N+ collector contacts (for the epitaxial tub) . In this improved method, the P+ isolation regions, P-wells, P-type base regions, and N+ collector contacts are defined using a single masking step and are thus automatically self-aligned. Since this self- alignment eliminates several critical mask alignments (and hence several alignment tolerances) , valuable die area is conserved, thereby allowing for increased component density. In another embodiment, P+ regions, to be used as source/drain regions for a PMOS transistor or emitter/collector regions for a PNP transistor, are also defined using the above-mentioned single masking step. In one embodiment of this improved method, a P- type substrate has formed thereon an N+ buried layer and an N- epitaxial layer. A layer of oxide is then formed over the epitaxial layer and selectively etched during a first masking step to form a pattern. The patterned oxide layer defines where self-aligned P+ isolation regions, P-wells, P-type bases, and N+ contact regions will be formed. A first oversized mask is then formed to leave exposed only those previously defined portions of the epitaxial layer which will in later steps become P- wells. This mask need only be roughly aligned to the previously defined P-well areas since the oxide pattern already precisely defines the boundaries of the P- wells. P-type dopants are then implanted into the unmasked epitaxial layer to form P-wells. In a next masking and etching step, a second mask similar to the first oversized mask is formed to mask all but those previously defined portions of the epitaxial layer which overlie the intended P+ isolation regions. This oversized mask is roughly aligned to the previously defined P+ isolation region areas since the oxide pattern precisely defines the boundaries of the P+ isolation regions. P-type dopants are then implanted into the unmasked epitaxial layer to form self-aligned P+ isolation regions. The P-type base regions and N+ contact regions (as well as any other regions defined by the oxide pattern) are then formed during subsequent masking and doping steps similar to those discussed above. The masks used during these subsequent steps are also oversized and require only rough alignment. Since the P-type base regions and the N+ contact regions are initially defined during the patterning of the oxide layer, the P-type base regions and the N+ contact regions are also self-aligned with the other regions. Since the precise boundaries of the various wells and regions are all initially defined by a single patterning step in the oxide layer, the oversized masks used in the formation of the P-wells, P+ isolation regions, P-type bases, and N+ contact regions do not require precise mask alignments, and any alignment tolerances for these oversized masks do not add to the size of the resulting integrated circuit. Accordingly, the above method conserves die area and increases component density. BRIEF DESCRIPTION OF THE DRAWINGS Figures 1-7 are cross-sectional views of a semiconductor structure illustrating various steps in the fabrication of a semiconductor structure in accordance with the present invention. DETAILED DESCRIPTION This improved method will be discussed below with reference to the fabrication of a particular semiconductor structure 10 capable of containing bipolar and MOS transistors, although other embodiments will become apparent to those skilled in the art after reading this disclosure. Figure 1 shows structure 10 having a P-type substrate 12 over which is formed an N+ buried layer 14 and an N- epitaxial layer 16. The thickness and dopant concentration of epitaxial layer 16 may vary depending upon the desired characteristics of devices to be formed in epitaxial layer 16. The conductivity types discussed thus far as well as those discussed hereinafter may be reversed while still realizing the benefits of the present invention. A layer of oxide 18 approximately 11,000 A thick is formed on the surface of epitaxial layer 16. Oxide 18 may be grown or deposited. A layer of resist 20 is then spun on the top surface of oxide layer 18, then exposed using a first mask and developed to form the resist 20 pattern shown in Figure 1. Using resist 20 as a mask, oxide 18 is then selectively etched using a suitable wet etchant to form the oxide 18 pattern shown in Figure 2. Resist 20 is then removed. A thin layer (e.g. 1000 A) of oxide (oxide portions 18a-f) is then grown over the exposed epitaxial layer 16 to protect epitaxial layer 16 from impurities in subsequent resist layers. Cuts 19a-f in oxide 18 define the boundaries of self-aligned P-wells, P+ isolation regions, P-type bases, and N+ contact regions. The specific oxide 18 pattern shown in Figure 2 is merely illustrative; other patterns may be formed in oxide 18 depending upon the particular components desired to be formed. The oxide 18 may also define shallow P+ regions to be used as source/drain regions for a PMOS transistor and/or shallow P- regions to be used as MOS resistors. A second resist layer is spun-on, then exposed using a second mask and developed to form an oversized mask 22 which leaves only thin portion 18e of oxide 18 exposed, as shown in Figure 2. Oversized mask 22 need only be roughly aligned since the thick portions of oxide layer 18 adjacent to thin portion 18e precisely define the boundaries of the doped region to be formed underlying portion 18e. P-type dopants such as Boron ions are then implanted at an energy of approximately 70 keV and a dosage of approximately 1 E13 ions/cm 2 through portion 18e of oxide layer 18 into epitaxial layer 16, thereby forming P-well 24. Drive-in of the P-well 24 impurities is performed during a subsequent heating step. Since P-well 24 is initially defined by cut 19e in oxide 18, the alignment tolerance of oversized mask 22 does not add to the lateral dimensions of the resulting integrated circuit. Mask 22 is then removed by a suitable stripper. A third resist layer is spun on the top surface of oxide 18, then exposed using a third masking step and developed to form an oversized mask 26 as shown in Figure 3. P-type dopants such as Boron ions * are implanted at an energy of approximately 70 keV and a dosage of approximately 7.5 E15 ions/cm 2 into epitaxial layer 16 (through thin oxide regions 18a, 18d, 18f) to form P+ isolation regions 28a, 28b, 28c, respectively. Mask 26 is then removed using any suitable stripper. Since the boundaries of P+ isolation regions 28a-c are defined by patterned oxide 18, as was P-well 24, P+ isolation regions 28a-c are automatically self-aligned with respect to P-well 24. Accordingly, the alignment tolerance of mask 26 does not add to the lateral dimensions of the integrated circuit. As shown in Figure 4, the wafer is placed in an oxygen environment to grow an additional oxide layer over the existing oxide 18, thereby causing oxide 18 to become thicker. The oxide will grow faster over the thin oxide portions 18a-f than over the thick oxide portions 30. In the preferred embodiment, the thinner oxide portions 18a-f are now approximately 4000 A thick and the thick oxide portions 30 are now approximately 11,000 A thick. P-well 24 and P+ isolation regions 28a, 28b, and 28c are then driven-in during a heating step. A fourth resist layer is spun on and selectively removed during a fourth masking step to form the mask 32 pattern shown in Figure 4. P-type dopants such as Boron ions are implanted at an energy of approximately 180 keV and a dosage of approximately 6.4 E14 into epitaxial layer 16 (through oxide portion 18c) to form a P-type base 34. Oversized mask 32 and the thick oxide portions adjacent thin oxide portion 18c ensure that the dopants are deposited only into P-type base 34. Growing the additional layer of oxide over oxide portion 18c enables better control over the implant depth of the Boron ions (and resulting impurity concentration) so that the characteristics of the resulting NPN transistor will be more predictable. Like the previously formed P-well 24 and P+ isolation regions 28a-c, the P-type base 34 boundary is defined by the pattern etched in oxide 18 and is thus self-aligned to P-well 24 and P+ isolation regions 28a- c. Accordingly, the alignment tolerance of mask 32 does not require any increase in the size of the resulting integrated circuit. After formation of P-type base 34 is complete, mask 32 is completely removed using a suitable stripper. P-well 24, P+ isolation regions 28a-c, and P-type base 34 are then simultaneously driven-in such that P+ isolation regions 28a-c contact substrate 12. In one embodiment, P-well 24, P+ isolation regions 28a- c, and P-type base 34 are driven-in to have final depths of approximately 3.5μm, 7 μm, and 3.0 μm, respectively. A fifth resist layer is spun on, then exposed during a fifth masking step and developed to form a mask 36 pattern as illustrated in Figure 5. Openings 36a-d denote those portions of the resist layer removed during the etching step. Masked oxide 18 is then selectively etched using any suitable wet or dry etchant to form the oxide 18 pattern shown in Figure 6A. The oxide etching process is timed so that the thin oxide portions are completely etched away while the thick oxide portions remain as a mask. N-type dopants such as Phosphorus are introduced in a conventional predeposition furnace operation. The Phosphorus forms a self-aligned N+ contact region 38 in epitaxial layer 16, an N+ emitter 40 within P-type base region 34, and N+ type source/drain regions 42 within P-well 24, respectively. N+ contact region is defined by cut 19b etched in oxide 18 during the initial masking and etching of oxide 18 (see Fig. 2). Since P-well 24, P+ isolation regions 28a-c, and P-type base 34 were also defined during this initial masking and etching of oxide 18, N+ contact region 38 is automatically self-aligned to the previously formed P-well 24, P+ isolation regions 28a- c, and P-type base region 34. Note that during the oxide etching step illustrated in Figure 6A, only those portions of epitaxial layer 16 which immediately underlie the exposed thin portions (e.g., 18a) of oxide 18 are ultimately exposed after the etching step to allow for the self-aligned deposition of dopants. The thick portions of oxide 18 adjacent to the thin portion 18a remain thick enough after the etching step so as prevent dopants from being deposited into regions of epitaxial layer 16 adjacent to N+ contact region 38. Since N+ contact region 38, N+ emitter 40, and N+ source/drain regions 42 were defined and formed during the same masking and etching steps, N+ contact region 38, N+ emitter 40, and N+ source/drain regions 42 will be precisely aligned with respect to one another. Note, however, N+ emitter 40 and N+ source/drain regions are not self-aligned to P-well 24, P+ isolation regions 28a-c, or P-type base 34. If self-aligned P+ contact regions or P+ source/drain regions were desired to be formed in epitaxial layer 16, oxide 18 in Figure 1 would have been initially patterned to also define these P+ regions. In one such embodiment, oxide 18 may be patterned as shown in Figure 6B. Figure 6B illustrates another area of the substrate shown in Figure 6A. An additional oversized mask 46 would then be formed, followed by a thin oxide etching step, similar to that in Figure 6A to expose the self-aligned P+ regions. P- type dopants would then be implanted to form the various P+ regions, such as source region 48 and drain region 50 and any contact regions. In another such embodiment, oxide 18 in Figure 1 may be initially patterned to define additional P-type base regions (see Figure 4) . These additional base regions (not shown for simplicity) may then serve as either P-type source/drain regions for a PMOS device or as P-type contact regions. In this particular embodiment, no additional masking, etching, or doping steps are required to form the P-type source/drain regions and P- type contact regions. Conventional processing techniques may now be used to complete fabrication of various devices within structure 10. For instance, Figure 7 shows a completed structure 10 which includes an NMOS transistor and an NPN transistor. To form an MOS transistor in a P-well or in an epitaxial tub, at least the epitaxial area between source and drain regions would be exposed and a gate oxide grown over the exposed silicon. Polysilicon or metal would then be deposited and etched to form the gates 52. Oxide 54 would then be grown or deposited and contact holes formed therein. A conventional metallization step is then conducted to form the various metal contacts 56. This improved self-alignment method may be used in the fabrication of numerous other structures. For instance, self-aligned resistors of varying conductivity may be fabricated in accordance with the above-described method using steps similar to those used to form P-well 24 or base 34. Using structure 10 as way of illustration, in one embodiment resistor diffusion regions may be defined by additional cuts (not shown) in oxide 18 during the initial masking and etching of oxide 18 (in which the P+ isolation regions 28a-c, P-well 24, P-type base 34, and N+ contact regions 38 are also defined) . These resistor diffusion regions may then be independently doped using oversized masks and implant steps, as discussed above. Additional oversized masks and doping steps may be used to create a variety of resistors of varying conductances or of different conductivity types. The formation of such resistors in accordance with this improved method does not require any additional area to accommodate for alignment tolerances and thereby allows for increased component density. In another embodiment in accordance with the present invention, the resistor diffusion areas may be formed without any additional masking steps. A blanket implant of P-type dopants is used immediately following the simultaneous drive-in of P-well 24, P+ isolation regions 28a, 28b, 28c, and P-type base 34 to form these resistor diffusion areas. This blanket implant should be conducted at a minimum dosage such that the blanket implant does not substantially change the dopant concentration of the P-type base 34. In yet another embodiment in accordance with the present invention, the oxide 18 may be etched in the initial masking and etching step to define regions which in subsequent masking and doping steps will become self-aligned deep P+ regions suitable for use as, for example, emitter and collector regions of a PNP transistor or a body contact region of a DMOS transistor formed within epitaxial layer 16. The formation of structure 10 or any other structure using the improved method as described above eliminates several critical masking alignments, since all regions initially defined by the pattern etched in oxide 18 are self-aligned. This automatic self- alignment thus saves die area since no die enlargement ia necessary to accommodate alignment tolerances. As the complexity of an integrated circuit desired to be fabricated increases, the savings in die area realized by using the present invention become more significant. While particular embodiments of the present invention have been shown and described, it will be obvious to those skilled in the art that changes and modifications may be made without departing from this invention in its broader aspects and, therefore, the appended claims are to encompass within their scope all such changes and modifications as fall within the true spirit and scope of this invention.

Claims: CLAIMS What is claimed is: 1. A method for forming a semiconductor structure comprising the steps of: (1) forming a first insulating layer overlying a semiconductor material of a first conductivity type; (2) forming a pattern in said first insulating layer to substantially expose portions of said semiconductor material; (3) forming a patterned first masking layer over said first insulating layer such that only first ones of said portions remain substantially exposed; (4) depositing dopants into said first ones of said portions to form first regions; (5) removing said first masking layer, but not removing said first insulating layer; (6) forming a second masking layer overlying said first insulating layer such that only second ones of said portions remain substantially exposed; and (7) depositing dopants into said second ones of said portions to form second regions, said first and second regions being self-aligned in accordance with said pattern in said first insulating layer. 2. The method of Claim 1 further comprising the steps of: (8) removing said second masking layer; (9) forming a third masking layer overlying said first insulating layer such that only third ones of said portions of said semiconductor material remain substantially exposed; and (10) depositing dopants into said third ones of said portions of said semiconductor material to form third regions, said third regions being self-aligned to said first regions and to said second regions. 3. The method of Claim 2 wherein said semiconductor material is an epitaxial layer of said first conductivity type formed over a substrate of said second conductivity type and wherein said first regions are well regions of said second conductivity type, said second regions are isolation regions of said second conductivity type extending from a top surface of said epitaxial layer to said substrate, and said third regions are base regions of said second conductivity type. 4. The method of Claim 2 further comprising the steps of: (11) removing said third masking layer; (12) forming a fourth masking layer overlying said second insulating layer such that only fourth ones of said portions of said semiconductor material are substantially exposed; (13) depositing dopants of into said fourth ones of said portions to form fourth regions, said fourth regions being self-aligned to said first regions, to said second regions, and to said third regions. 5. The method of Claim 4 wherein said fourth masking layer selectively masks said first and third regions, said dopants of step 12 being deposited into portions of said first regions and into portions of said third regions not masked by said fourth masking layer to form fifth regions and sixth regions within said first region and a seventh region within said third region. 6. The method of Claim 5 further comprising the steps of: before said step of forming said fourth masking layer, forming a second insulating layer overlying said first insulating layer, wherein said second layer is contiguous to said first insulating layer such that said second insulating layer has formed therein a pattern similar to said pattern formed in said first insulating layer; and after said step of forming said fourth masking layer and before said step of doping said fourth ones of said portions, selectively etching said first and second insulating layers to substantially expose said portions of said first regions and said portions of said third regions not masked by said fourth masking layer. 7. The method of Claim 5 wherein said fifth regions and sixth regions formed within said first region serve as source and drain regions, respectively. 8. The method of Claim 7 wherein said third region is a base region and said seventh region formed within said third region is an emitter, said emitter being self-aligned to both said source and drain regions. 9. The method of Claim 8 wherein said emitter, said source and said drain regions are N-type. 10. The method of Claim 8 wherein said emitter, said source and said drain regions are P-type. 11. The method of Claim 5 wherein said first regions comprise P-wells. 12. The method of Claim 5 wherein said first regions comprise N-wells. 13. The method of Claim 5 wherein said second regions comprise isolation regions. 14. The method of Claim 13 wherein said isolation regions are P-type. 15. The method of Claim 13 wherein said isolation regions are N-type. 16. The method of Claim 4 wherein said fourth regions comprise contact regions. 17. The method of Claim 16 wherein said contact regions are N-type. 18. The method of Claim 16 wherein said contact regions are P-type. AMENDED CLAIMS [received by the International Bureau on 16 July 1996 (16.07.96); original claims 1-18 replaced by amended claims 1-10 (3 pages)] 1. A method for forming a semiconductor structure comprising the steps of: (1) forming a first insulating layer overlying a semiconductor material of a first conductivity type; (2) forming a pattern in said first insulating layer to substantially expose portions of said semiconductor material; (3) forming a patterned first masking layer over said first insulating layer such that only first ones of said portions remain substantially exposed; (4) depositing dopants into said first ones of said portions to form one or more well regions; (5) removing said first masking layer, but not removing said first insulating layer; (6) forming a second masking layer overlying said first insulating layer such that only second ones of said portions remain substantially exposed; (7) depositing dopants into said second ones of said portions to form one or more isolation regions; (8) removing said second masking layer; (9) forming a third masking layer overlying said first and second insulating layers such that only third ones of said portions of said semiconductor material remain substantially exposed; (10) depositing dopants into said third ones of said portions of said semiconductor material to form one or more base regions; (11) removing said third masking layer; (12) forming a fourth masking layer overlying said first and second insulating layers such that only fourth ones of said portions of said semiconductor material are substantially exposed; and (13) depositing dopants of into said fourth ones of said portions to form one or more collector contact regions, said one or more well regions, said one or more isolation regions, said one or more base regions, and said one or more collector contact regions being self-aligned with respect to one another in accordance with said pattern in said first insulating layer. 3. The method of Claim 1 wherein said semiconductor material is an epitaxial layer of said first conductivity type formed over a substrate of said second conductivity type and wherein said one or more well regions are of said second conductivity type, said one or more isolation regions are of said second conductivity type and extend from a top surface of said epitaxial layer to said substrate, said one or more base regions are of said second conductivity type, and said one or more collector contact regions are of said first conductivity type. 4. The method of Claim 1 further comprising the steps of : (11) removing said third masking layer; (12) forming a fourth masking layer overlying said second insulating layer such that only fourth ones of said portions of said semiconductor material are substantially exposed; (13) depositing dopants into said fourth ones of said portions to form fourth regions, said fourth regions being self-aligned to said first regions, to said second regions, and to said third regions. 5. The method of Claim 1 wherein said fourth masking layer selectively masks said one or more well regions and said one or more base regions, said dopants of step 12 being deposited into portions of said one or more well regions and into portions of said one or more base regions not masked by said fourth masking layer such that said fourth regions comprise source regions and drain regions within said one or more well regions and emitter regions within said one or more base regions. 6. The method of Claim 1 further comprising the steps of: before said step of forming said third masking layer, forming a second insulating layer overlying said first insulating layer, wherein said second layer is contiguous to said first insulating layer such that said second insulating layer has formed therein a pattern similar to said pattern formed in said first insulating layer. 9. The method of Claim 6 wherein said emitters, said source regions, and said drain regions are N-type. 10. The method of Claim 6 wherein said emitters, said source regions, and said drain regions are P-type. STATEMENT UNDER PCT ARTICLE 19 The claims in the above-referenced application have been amended for clarity and to distinguish over references cited by the United States Patent Office during prosecution of the corresponding U.S. patent application. As amended, Applicants' Claim 1 recites a method which allows for the formation of self-aligned bipolar transistors and MOS devices, wherein the base and collector contact of the bipolar device are self-aligned not only with respect to each other but also with respect to P-well and isolation regions. As recited in Claim 1, a single masking layer is used to substantially expose portions of the semiconductor material which in subsequent processing steps will become "said one or more well regions, said one or more isolation regions, said one or more base regions, and said one or more collector contact regions." Thus, by defining such well regions, isolation regions, base regions, and said collector contact regions in "said first insulating layer" using a single mask, the well regions, isolation regions, base regions, and said collector contact regions are automatically self-aligned. The first of the two references listed in the International Search Report as being relevant to the scope of the claims, US 5,141,881 (Takeda et al) , teach that a new Si0 2 layer of uniform thickness is formed over the substrate after formation of base region 60 and before formation of collector contact 57, thereby necessarily requiring separate masking steps to define the base 60 and the collector contact 75. As a result, base 60 and collector 75 disclosed in Takeda et al cannot be self- aligned. Accordingly, Applicants' Claim 1 distinguishes over Takeda et al. The second of such references, US 4,721,686 to Contiero et al, also fails to disclose or teach defining well regions, isolation regions, base regions, and collector contact regions in an insulating layer using a single mask such that the well regions, isolation regions, base regions, and said collector contact regions are automatically self-aligned. Thus, Applicants' Claim 1 also distinguishes over US 4,721,686. Claims 3-6 and 9-10 depend from independent Claim 1 and therefore distinguish over the cited references for at least the same reasons as does independent Claim 1. It is believed that none of the amendments require changes to the Title, Abstract, or Specification. In view of the foregoing, Applicant submits that the claimed invention is novel and includes an inventive step, as defined in Article 33(2) and (3) . Accordingly, the amendments to the claims and the new claims do not go beyond the disclosure in the international application as filed. Therefore, the amendments are within the scope provided under Article 19(2) .

Inventors: ALTER MARTIN J, GARNETT MARTIN E, MOYER JAMES C, ALTER, MARTIN, J., GARNETT, MARTIN, E., MOYER, JAMES, C.
Applicants: MICREL INC, MICREL, INCORPORATED
Application year: 1996
Main classification: H01L21
IPC codes: H01L21, H01L27