Semiconductor memory device and method of manufacturing the same

Abstract: A semiconductor memory device is disclosed including at least one memory cell (Mmn) having a floating gate electrode (F.G.) storing an electric charge and a switching element (Qmn) charging the floating gate electrode (F.G.) with the electric charge and switching so as to discharge the charged electric charge.

Description: Background of the Invention The present invention relates to a semiconductor memory, and more particularly, to a semiconductor memory device and a method of manufacturing the same, which can be used as a dynamic random access memory (DRAM) cell having no capacitor. Recently, a semiconductor memory market has been prosperous. In company with this, researches about the ultra large scale integration have been advanced actively. However, to realize the ultra large scale integration and large capacity with the current basic structure has its limit. Accordingly, a memory device of new model is required. In general, there are several memory devices having the respective characteristics. For example, a DRAM memory device is not limited in its cycling, but is inferior in the density aspect because an unit cell is composed of one storage capacitor and one transistor. On the other hand, an electrically erasable programmable read only memory (EEPROM) device is composed of one stacked transistor. Through one thin tunnel oxide film, a floating gate is charged with electrons or the electrons charged are discharged from the floating gate, to thereby perform "programming" or "erasure" of the cell. Accordingly, the density is good, but the cycling is limited to about 10 7 . Among the conventional memory devices, the DRAM and EEPROM will be described below with reference to the attached drawings. Fig.1 is a circuit diagram of a general DRAM cell. Fig.2 is a cross-sectional view showing the structure of the general DRAM cell. The conventional DRAM cell is constructed including one bit line (B/L), one word line (W/L), one access transistor (M1), one storage capacitor (Cs), and one sense amplifier (SA). Referring to the structure, a gate (G) of access transistor (M1) is connected to word line (W/L). A drain (D) of access transistor (M1) is connected to bit line (B/L). A source (S) of access transistor (M1) is connected to a first electrode of storage capacitor (Cs). A second electrode of storage capacitor (Cs) is connected to a polysilicon cell plate. Bit line (B/L) is connected to one input terminal of sense amplifier (SA). Another input terminal of sense amplifier (SA) is connected to a reference voltage (Vref). The structure of the DRAM cell having the aforementioned circuit construction is shown in Fig.2. That is, a P-type silicon substrate 1 is divided into a field region and an active region, and a field oxide film 2 is formed on the field region. A gate insulating film 3 and a gate electrode 4 are stacked sequentially on the active region of P-type silicon substrate 1. Source/drain regions (S,D), which are N-type impurity regions, are formed in the substrate on both sides of gate electrode 4, thereby making access transistor (M1). Further, a first electrode 6 of the capacitor is formed on source region (S) of access transistor (M1). A dielectric film 7 and a second electrode 8 are stacked on the surface of first electrode 6 of the capacitor. Moreover, bit line (B/L) is connected to drain region (D) of access transistor (M1). Here, undescribed reference numerals show insulating films 5 and 9. The operation of the conventional DRAM cell constructed as described above will be explained below. To begin with, let it be supposed that P-type silicon substrate 1 is grounded and a voltage of Vcc (5V) is applied to second electrode 8 of the capacitor, during the operation. If so, in the surface of the P-type silicon region under second electrode 8, electrons are accumulated, together with the formation of an inversion layer. Under the inversion layer, one depletion layer is formed. Accordingly, in order to write a data "1" in any one cell, 5V are applied to the bit line connected to drain (D) of access transistor (M1) of the above cell. At the same time, a voltage pulse of 5-6V is applied to the word line connected to gate (G) of access transistor (M1) of the above cell. If so, the access transistor is in a state of "on", so that the potential of the access transistor source of the above cell is raised to 5V. At this time, the potential of the inversion layer formed in the surface of the P-type silicon region under second electrode 8 will be somewhat lower than 5V. This is because the voltage of 5V applied to second electrode 8 is dropped in some degree through the dielectric film of the storage capacitor located below second electrode 8. Accordingly, the electrons accumulated in the inversion layer formed in the P-type silicon substrate surface under second electrode 8 flow into the source region of access transistor (M1) whose electron energy state is low. Thus, an empty potential well is formed in the surface of the P-type silicon region under second electrode 8. Such state shows a logic "1" in the binary system. In order to write a data "0" in any one cell, bit line (B/L) connected to the drain of the access transistor of the above cell is grounded. At the same time, a voltage pulse of 5~6V is applied to word line (W/L) connected the gate of the access transistor of the above cell. If so, the electrons flow from source region (S) of access transistor (M1) having a high electron energy to the empty potential well formed in the surface of the P-type silicon substrate, thereby filling the empty potential well. Accordingly, the electrons are accumulated in the inversion layer formed in the surface of the P-type silicon substrate under the capacitor. Such state shows a logic "0" in the binary system. In order to read a data from one cell, bit line (B/L) of the above cell is precharged to 0.5Vcc (-2.5V), and then, a voltage pulse of 5~6V is applied to the word line of the above cell. If so, the electric charges charged in the storage capacitor of the above cell flow to bit line (B/L), thereby changing the potential of bit line (B/L). Since sense amplifier (SA) is one comparative circuit, if the potential of the bit line is higher than the reference voltage (-0.5Vcc), the logic "1" is read. If the above potential is lower than the reference voltage, the logic "0" is read. At this time, a displacement potential (ΔV) of bit line (B/L) is expressed by the following equation (1). ΔV = ± 0.5Vcc (Cs) / (Cs + Cb) Here, Cs represents the static capacity of the storage capacitor, and Cb represents the static capacity of the bit line. Further, in the equation (1), (+) symbol corresponds to the case where the logic "1" is stored in the cell. (-) symbol corresponds to the case where the logic "0" is stored in the cell. Accordingly, if the minimum voltage difference between the reference voltage and the bit line voltage, which can be distinguished by one sense amplifier, is a "distinction ability" of the sense amplifier, the distinction ability of the sense amplifier was about 150~200mV in the previous case of 1M DRAM. Therefore, in case that Vcc is 5V in the equation (1), the ratio of the bit line static capacity (Cb) and the storage capacitor static capacity (Cs) (r=Cb/Cs) must be lower than 15 in order to make ΔV higher than 150mV. According to the paper published previously, in case of 1M DRAM, Cs was 30~60fF and Cb was 250~500fF. Further, r was maintained to 7~15. In such general DRAM cell, the integration is increased steadily, thereby reducing the size of the cell area. However, the distinction ability of the sense amplifier and the static capacity of the bit line cannot be decreased, as compared to the decrement of the cell size. Further, the static capacity of the storage capacitor is not decreased, as compared to the decrement of the size of the cell area. Moreover, in order to prevent the "soft error" problem which is one among the most important reliability problems in DRAM, it is necessary to maintain the constant size of the static capacity of the storage capacitor. Due to this reason, the reduction of the static capacity of the storage capacitor is small, in spite of the steady increase of the DRAM integration and the reduction of the cell area size. For example, in case of 256K DRAM, a design rule of about 2mm was used. In case of 256M DRAM, a design rule of about 0.25µm has been used. Accordingly, the cell area was decreased to about 100 times. However, if the static capacity of the storage capacitor is compared, it was about 40fF in 256K DRAM and about 25fF in 256M DRAM. Thus, the static capacity is decreased to about 1.5 times. In such general DRAM, the static capacity of the storage capacitor must be maintained to almost same size, in spite of the increase of the integration. Therefore, there was a problem that the integration has its limit. Further, in order to form the storage capacitor while minimizing the cell area, a trench is formed in the substrate to thereby form the storage capacitor, or a stacked capacitor structure is used to form the storage capacitor. Thus, the semiconductor manufacturing process becomes complicate. In company with this, there was a problem that the semiconductor manufacturing process cost is increased seriously. Meantime, Fig.3 is a circuit diagram of a general flash EEPROM cell. Fig.4 is a cross-sectional view showing the structure of the general flash EEPROM cell. The general EEPROM cell is comprised of a floating gate avalanche injection metal oxide semiconductor (FAMOS) having a stacked gate transistor structure. A control gate of each cell is connected to one word line (W/L). A drain (D) of each cell is connected to one bit line (B/L). A source (S) of each cell is connected to one common source line (C.S). Further, each bit line (B/L) is connected to one input terminal of one sense amplifier (SA). Another input terminal of sense amplifier (SA) is connected to a reference voltage (Vref) . The structure of the general EEPROM cell having the aforementioned circuit construction is shown in Fig.4. That is, a floating gate (F.G) and a control gate (C.G) are stacked sequentially on a P-type silicon substrate 1. A source region (S) and a drain region (D) of N-type impurity regions are formed in P-type silicon substrate 1 on both sides of floating gate (F.G). Here, an insulating film is formed between silicon substrate 1, floating gate (F.G) and control gate (C.G). Between floating gate (F.G) and control gate (C.G), it is formed to a thickness corresponding to the thickness of a gate insulating film of general transistor. Between floating gate (F.G) and silicon substrate 1, a tunnel oxide film is formed to a thickness of about 100Å and less. The operation of such general EEPROM is as follows. To begin with, in order to write a data "1" in one cell, 7~8V are applied to bit line (B/L) corresponding to the above cell. A voltage pulse of 12~13V is applied to word line (W/L). The source (S) and substrate are grounded. If so, the avalanche breakdown occurs in P-N junction between the drain (D) and substrate, thereby generating hot electrons. A part of the hot electrons generated as described above obtain an energy higher than the energy potential height (about 3.2eV) between the substrate and gate oxide film. Then, from the substrate, they go over the gate oxide film and enter floating gate (F.G), so that they are stored therein. At this time, as the number of electrons stored in floating gate (F.G) is gradually increased, the threshold voltage of the cell is increased. In general, "writing" is performed so that the cell threshold voltage is more than 7V. If the electrons are once stored in floating gate (F.G), the natural electron discharge quantity is negligibly small because the energy potential height between floating gate (F.G) and the insulating film fully surrounding floating gate (F.G). Therefore, the quantity of the stored electrons is almost maintained without changing during several years. Such state of the cell shows a logic "1" in the binary system. Erasing the data written in one cell as described above is as follows. That is, the substrate and control gate (C.G) are grounded. A voltage pulse of 12~13V is applied to common source line (C.S). If so, due to the tunneling phenomenon, the electrons stored in floating gate (F.G) pass the thin gate oxide film from floating gate (F.G) and then, are discharged to source (S). At this time, as the discharge quantity of the electrons stored in floating gate (F.G) is gradually increased, the threshold voltage of the cell begin to decrease. In general, the cell threshold voltage must be 3V and less. Accordingly, such state shows a logic "0" in the binary system. Meantime, reading the data stored in one cell is as follows. That is, 1~2V are applied to bit line (B/L) connected to drain (D) of the cell. The substrate and source (S) are grounded. Then, a voltage pulse of 3~5V is applied to word line (W/L) connected to control gate (C.G) of the cell. At this time, in case that a data "1" is stored in the cell, the cell becomes a state of "OFF", so that the electric charges charged in bit line (B/L) are not discharged and remain as it is. Thus, the previously applied potential of 1~V is maintained as it is. Further, in case that a data "0" is stored in the cell, the cell becomes a state of "ON", so that all electric charges charged in bit line (B/L) are discharged to source (S) through the cell. Thus, the potential of bit line (B/L) is in a ground state. Sense amplifier (SA) connected to bit line (B/L) recognizes such potential difference of bit line (B/L), thereby reading the stored data of the cell. In case of such general flash EEPROM, it is unnecessary to form the storage capacitor required in the DRAM cell, so that the area of the unit cell can be decreased. In addition, the process can be simplified. However, in the DRAM, the number of times of programming/erasure of data is unlimited. On the other hand, in the EEPROM, the possible times of programming/erasure of data is generally limited to 10 7 and less. Therefore, there was a problem that the flash EEPROM cannot be used in most application, instead of DRAM. This is because, during programming and erasing data, a part of the injected electrons are captured in the gate oxide film when the electrons pass the gate oxide film. Due to the increase of programming/erasure times of data, the captured quantity is gradually increased, thereby causing the deterioration of the gate oxide film. If the gate oxide film is deteriorated as described above, the speed of programming and erasure is reduced. If the time of programming and erasure is not controlled, the programming threshold voltage is decreased and the erasure threshold voltage is increased, together with the increase of programming/erasure times of data. Accordingly, so-called window-closing phenomenon occurs, so that the device cannot perform the programming/erasure of data when exceeding a predetermined times. The paper of Kitaura et al. (Int. Conf. Solid state Mat. & Dev. 1993, pgs. 449-451) discloses a memory cell having a floating gate that consists of three portions each of which is associated with its own control gate. The first portion forms a tunnel junction for charge injection, the second portion, forms a charge transfer transistor for transferring injected charges from the first portion to the third portion that is a storage portion. Thus, this memory cell comprises a memory cell transistor and a passing transistor that is connected with the floating gate of the memory cell transistor for charging and discharging the storage portion of the floating gate using a tunneling effect. US 5,336,937 discloses a memory cell transistor having a control gate, a floating gate and source and drain electrodes, as well as a passing transistor arrangement for supplying programming pulses via programming line to floating gate of transistor. JP-5-41525 discloses a memory cell that is just the same as that discussed in connection with the paper of Kitaura et al. Summary of the Invention It is an object of the present invention to provide a semiconductor memory device wherein each cell is composed of one transistor by using only merits of DRAM and EEPROM, so that the integration is improved and the number of times of programming/erasure of a data is not limited. This object is achieved by the semiconductor memory device of claim 1 and the method of claim 17. Brief Description of the Attached Drawings Fig.1 is a circuit diagram of a general DRAM cell; Fig.2 is a cross-sectional view showing the structure of the general DRAM cell; Fig.3 is a circuit diagram of a general flash EEPROM cell; Fig.4 is a cross-sectional view showing the structure of the general flash EEPROM cell; Fig.5 is a circuit diagram of a semiconductor memory device according to the present invention; Fig.6 is a layout diagram of a semiconductor memory device according to a first embodiment of the present invention; Fig.7 is a cross-sectional view showing the structure of the semiconductor memory device according to the present invention, taken along line A-A' in Fig.6; Fig.8 is a cross-sectional view showing the structure of the semiconductor memory device according to the present invention, taken along line B-B' in Fig.6; Fig.9 is a cross-sectional view showing the structure of the semiconductor memory device according to the present invention, taken along line C-C' in Fig.6; Fig.10 is a cross-sectional view showing the structure of the semiconductor memory device according to the present invention, taken along line D-D' in Fig.6; Figs.11a to 11j are cross-sectional views for illustrating a method of manufacturing the semiconductor memory device according to the present invention, taken along the line A-A' in Fig.6; Figs.12a to 12j are cross-sectional views for illustrating a method of manufacturing the semiconductor memory device according to the present invention, taken along the line B-B' in Fig.6; Figs.13a to 13j are cross-sectional views for illustrating a method of manufacturing the semiconductor memory device according to the present invention, taken along the line C-C' in Fig.6; and Figs.14a to 14j are cross-sectional views for illustrating a method of manufacturing the semiconductor memory device according to the present invention, taken along the line D-D' in Fig.6. Detailed Description of the Invention Hereinafter, a semiconductor memory device of the present invention will be described with reference to the attached drawings. Fig.5 is a circuit diagram of a semiconductor memory device according to the present invention. Fig.6 is a layout diagram of a semiconductor memory device according to a first embodiment of the present invention. Fig.7 is a cross-sectional view of the semiconductor memory device according to the present invention, taken along line A-A' in Fig.6. Fig.8 is a cross-sectional view of the semiconductor memory device according to the present invention, taken along line B-B' in Fig.6. Fig.9 is a cross-sectional view of the semiconductor memory device according to the present invention, taken along line C-C' in Fig.6. Fig.10 is a cross-sectional view of the semiconductor memory device according to the present invention, taken along line D-D' in Fig.6. To begin with, in the circuit structure of a semiconductor memory device according to the present invention, a plurality of memory cells (stacked transistors M11~Mn3 for use as data memory) having a floating gate (F.G) and a control gate (C.G) are arranged. Corresponding to stacked transistors (M11~Mn3) for use as data memory, there are formed passing transistor Q11~Qn3 which switch so as to charge each floating gate (F.G) of stacked transistor (M11~Mn3) for use as data memory with electric charges and to discharge the charged electric charges and perform the programming or erasure of the cell. Further, in the semiconductor memory device constructed as described above, control gates (C.G) of each stacked transistor for use as data memory of the same column are connected to one word line (W/L1~W/Ln). Drains (D) of each stacked transistor for use as data memory of the same row and sources of each stacked transistor for use as data memory of the neighboring row are connected to the respective bit lines (B/L1~B/L3) in common. Further, one input terminal of a sensing amplifier (SA) is connected to each bit line (B/L1~B/L3) and a reference voltage is applied to another input terminal. End terminal of each bit line (B/L1~B/L3) is floated. Each passing transistor (Q11~Qn2) of the same column is connected to one gate line (G/L1~G/Ln). Each passing transistor of the same row is connected in series. A drain terminal of the tip is floated. The structure of a semiconductor memory device according to one embodiment of the present invention having such circuit construction is shown in Fig.6, Fig.7, Fig.8, Fig.9 and Fig.10. That is, as shown in Fig.6, a plurality of high concentration N-type impurity regions 12, which will be used as bit lines, are spaced apart by a constant distance and formed in a P-type silicon substrate in one direction. On the P-type silicon substrate between the respective high concentration N-type impurity regions 12, a plurality of floating gate semiconductor layers (polycrystalline silicon) 13 for storing electric charges are formed so as to be isolated from the P-type silicon substrate. Further, on the substrate, a plurality of control electrodes 14 used as word lines (W/L) are formed spaced apart by a constant distance in the perpendicular direction with respect to floating gate semiconductor layer 13. On the substrate between the respective control electrodes 14, there are formed a plurality passing gate electrodes 15 for controlling each passing transistor (M11~Mn2). Here, each floating gate semiconductor layer 13 under control electrode 14 is formed as a high concentration N-type impurity layer (N + ). Each floating gate semiconductor layer 13 under passing gate electrode 15 is formed as a P-type impurity layer (P). Further, in the silicon substrate under the portion where passing gate electrode 15 are floating gate semiconductor layer 13 cross, a field oxide film 16 is formed with an island shape. The semiconductor memory device of the present invention having the aforementioned layout will be described in more detail, as follows. To begin with, the cross-section of the control electrode in Fig.6 is shown in Fig.7. High concentration N-type impurity regions 12 which will be used as bit lines are formed in a P-type silicon substrate 11, being spaced apart by a constant distance. A first gate insulating film 17 is formed on the entire surface of P-type silicon substrate 11. A floating gate semiconductor layer 13 is formed on first gate insulating film 17 between the respective high concentration N-type impurity regions 12. A second gate insulating film 18 is formed on the entire surface of P-type silicon substrate 11 including floating gate semiconductor layer 13. A control electrode 14 is formed on second gate insulating film 18. Further, the cross-section of the passing gate electrode direction in Fig.6 is shown in Fig.8. High concentration N-type impurity regions 12 which will be used as bit lines are formed in P-type silicon substrate 11, being spaced apart by a constant distance. A field oxide film 16 of an island shape is formed on P-type silicon substrate 11 at the portion where each floating gate semiconductor layer 13 and each passing gate electrode cross. First gate insulating film 17 is formed on the entire surface of P-type silicon substrate 11. Floating gate semiconductor layer 13 is formed on first gate insulating film 17 between the respective high concentration N-type impurity regions 12. Second gate insulating film 18 is formed on the entire surface of P-type silicon substrate 11 including floating gate semiconductor layer 13. A passing gate electrode 15 is formed on second gate insulating film 18. Further, the cross-section of the floating gate semiconductor layer direction in Fig.6 is shown in Fig.9. Field oxide film 16 of an island shape is formed on P-type silicon substrate 11 at the portion where the floating gate semiconductor layer and passing gate electrode cross. First gate insulating film 17 is formed on the entire surface of P-type silicon substrate 11. Floating gate semiconductor layer 13 is formed on first gate insulating film 17. Second gate insulating film 18 is formed on the entire surface of P-type silicon substrate 11 including floating gate semiconductor layer 13. A plurality of control electrodes 14 are formed on second insulating film 18, being spaced apart by a constant distance. A plurality of passing gate electrodes 15 are formed on second gate insulating film 18 between the respective control electrodes 14, so as to be isolated by control electrode 14 and insulating film 19. Further, the cross-section of the high concentration N-type impurity region direction in Fig.6 is shown in Fig.10. High concentration N-type impurity regions 12 which will be used as bit lines are formed in a P-type silicon substrate 11. First gate insulating film 17 and second gate insulating film 18 are formed on the entire surface of P-type silicon substrate 11. A plurality of control electrodes 14 are formed on second gate insulating film 18, being spaced apart by a constant distance. A plurality of passing gate electrode 15 are formed on second gate insulating film 18 between the respective control electrodes 14, so as to be isolated by control electrode 14 and insulating film 19. A method of manufacturing the semiconductor memory device of the present invention having the aforementioned structure will be below described. Figs.11a to 11j are cross-sectional views for illustrating a method of manufacturing the semiconductor memory device according to the present invention, taken along the line A-A' in Fig.6. Figs.12a to 12j are cross-sectional views for illustrating a method of manufacturing the semiconductor memory device according to the present invention, taken along the line B-B' in Fig.6. Figs.13a to 13j are cross-sectional views for illustrating a method of manufacturing the semiconductor memory device according to the present invention, taken along the line C-C' in Fig.6. Figs.14a to 14j are cross-sectional views for illustrating a method of manufacturing the semiconductor memory device according to the present invention, taken along the line D-D' in Fig.6. To begin with, as shown in Fig.11a, Fig.12a, Fig.13a and Fig.14a, a buffer oxide film 20, a nitride film 21 and a first resist film 22 are formed sequentially on a P-type silicon substrate 11. A field region of an island shape is defined through the exposure and development process, thereby selectively removing nitride film 21 of the field region. As shown in Fig.11b, Fig.12b, Fig.13b and Fig.14b, P-type silicon substrate 11 is thermally oxidized, thereby forming a field oxide film 16 in the field region. Then, first resist film 22, nitride 21 and oxide film 20 are removed. Here, instead of using field oxide film 16, it is possible to form the channel isolation region by implanting P-type ion. As shown in Fig.11c, Fig.12c, Fig.13c and Fig.14c, a second resist film 23 is deposited. Through the exposure and development process, a bit line region is defined so as to be spaced apart by a constant distance. A high concentration N-type ion is implanted on P-type silicon substrate 11, thereby forming a high concentration N-type impurity region 12. At this time, an oxide film 20a is formed on the portion where high concentration N-type impurity region 12 is formed. As shown in Fig.11d, Fig.12d, Fig.13d and Fig.14d, second resist film 23 is removed. On the entire surface of P-type silicon substrate 11 including field oxide film 16, a first gate insulating film (oxide film) 17 is deposited to a thickness of about 70~200Å (10Å = 1nm). As shown in Fig.11e, Fig.12e, Fig.13e and Fig.14e, a P-type polycrystalline silicon layer 13a and a third resist film 24 are deposited sequentially on first gate insulating film 17. Through the exposure and development process, third resist film 24 is patterned so as to expose P-type polycrystalline silicon layer 13a at the.portion where a control electrode 14 and a floating gate semiconductor layer 13 cross. Then, using patterned third resist film 24 as a mask, an N-type impurity ion is implanted on exposed P-type polycrystalline silicon layer 13a. At this time, the P-type impurity concentration of P-type polycrystalline silicon layer 13a is about 10 15 ~10 18 atoms/cm 3 . The N-type impurity ion-implantation concentration is about 10 18 ~10 21 atoms/cm 3 . As shown in Fig.11f, Fig.12f, Fig.13f and Fig.14f, third resist film 24 is removed. Then, a fourth resist film 25 is deposited again on P-type polycrystalline silicon layer 13a. A floating gate region is defied through the exposure and development process. P-type polycrystalline silicon layer 13a is selectively removed, thereby forming a floating gate semiconductor layer 13 on first gate insulating film 17 between respective high concentration N-type impurity regions 12. Here, it does not matter to change the processes of (e) and (f) in Fig.11, Fig.12, Fig.13 and Fig.14. That is, P-type polycrystalline silicon layer 13a is deposited and removed selectively, thereby forming floating gate semiconductor layer 13. Then, N-type impurity ion is selectively implanted on the portion where floating gate semiconductor layer 13 and control electrode 14 cross. As shown in Fig.11g, Fig.12g, Fig.13g and Fig.14g, a second gate insulating film 18 is deposited on the entire surface of first gate insulating film 17 including floating gate semiconductor layer 13. Then, a first N-type polycrystalline silicon layer 14a, a cap insulating film 29 (oxide film or nitride film) and a fifth resist film 26 are deposited sequentially. At this time, as second gate insulating film 18, an oxide film may be used. Alternatively, a structure where nitride film/oxide film are stacked or a structure where oxide film/nitride film/oxide film are stacked may be used. The N-type impurity concentration of first N-type polycrystalline silicon layer 14a is about 10 18 ~10 21 atoms/cm 3 . As shown in Fig.11g, Fig.12h, Fig.13h and Fig.14h, a control electrode region is defined through the exposure and development process. Then, cap insulating film 29 and first N-type polycrystalline silicon layer 14a are selectively removed, thereby forming a control electrode 14. Here, instead of using first N-type polycrystalline silicon layer 14a, it is possible to use a metal. As shown in Fig.11i, Fig.12i, Fig.13i and Fig.14i, an insulating film is deposited on the entire surface of second gate insulating film 18 including control electrode 14 and etched back, thereby forming an insulating sidewall 27 on the sidewall of control electrode 14. At this time, most of exposed second gate insulating film 18 are removed. As shown in Fig.11j, Fig.12j, Fig.13j and Fig.14j, a third gate insulating film 19, a high concentration second N-type polycrystalline silicon 15a and a sixth resist film 28 are deposited on first gate insulating film 18 including control electrode 14. Then, a passing gate region is defined through the exposure and development process. Second N-type polycrystalline silicon layer 15a is selectively removed, thereby forming a passing gate electrode 15. Here, a metal may be used as a material constituting passing gate electrode 15. The operation of the semiconductor device of the present invention manufactured as described above will be below described. To begin with, a method of recording a data in each cell will be below described. When a data is recorded, a voltage of 2-10V is applied to the substrate. All control electrodes 14 are floated, and the corresponding bit line is grounded. A voltage of 5V is applied to the gate electrode of all passing transistors (Q11~Qn2), to thereby turn on the all passing transistor. A voltage corresponding to a data which will be recorded in a memory cell of the lowest row (n) is applied to a source terminal of the passing transistor. If we want to record a data "1", "-3V" are applied to the source terminal of the corresponding passing transistor. If want to record a data "0", "0V" is applied to the source terminal of the corresponding passing transistor. Accordingly, the data is recorded in the memory cell of one row at the same time. If the data is recorded in the cell of the lowest row (n) as described above, 0V is applied to the gate electrode of the lowest (n) passing transistor of each column. Alternatively, the gate electrode is floated. Thus, the lowest (n) passing transistor is turned off. Further, according to a data which will be recorded in a memory cell of the directly previous row (n-1), a voltage is applied to the source terminal of the corresponding passing transistor through the method as described above. Using the aforementioned method, a data is recorded in all cells and all passing transistors are turned off. In another embodiment, when a data is recorded, a voltage of -2~-7V is applied to the corresponding bit line and the substrate is grounded. Thus, the data can be recorded by the aforementioned method. Meantime, a method of reading the data recorded as described above will be below described. If supposing that we want to read the data of the stacked transistor (M22) for use as data memory in Fig.5, a second bit line (B/L2) is precharged by 2V in a state where all passing transistors (Q11~Qn2) are turned off. A third bit line (B/L3) is grounded, and the same voltage as that to bit line (B/L2) is applied to a first bit line (B/L1). Alternatively, first bit line (B/L1) is floated. A voltage is applied to the word line (W/L2) of a memory cell (M22) required to read, thereby reading the data through sensing amplifier (SA). If a data "1" is recorded in the stacked transistor (M22) for use as data memory, since a channel is not formed between the source and drain of the cell, a voltage of 2V applied to the first bit line is detected by the sensing amplifier and produced. Thus, the data "1" is read. Further, in case that a data "0" is recorded in the stacked transistor (M22) for use as data memory, since the channel is formed between the source and drain of the stacked transistor (M22), a voltage of 2V applied to the second bit line passes to the third bit line. Thus, the data "0" is read in the sensing amplifier (SA). Here, even if the data "1" or "0" is recorded in the stacked transistor (M12) for use as data memory, the channel is not formed between the source and drain of the stacked transistor (M12) because the first bit line (B/L1) is floated. Thus, there is no problem of reading the data. In addition to such method, a data can be recorded and read by several methods, according to the design condition. The semiconductor memory device according to the present invention as described above has the following effects. First, the present invention uses the stacked transistor as a memory element, as in the general flash EEPROM. However, unlike the structure of the general flash EEPROM, the programming or erasure of the cell is performed by using the passing transistor, so as to charge the floating gate of the stacked transistor with electrons or to precharge the charged electrons in the floating gate. Since the capture of the electron is not generated in the gate insulating film, the programming or erasure of the data is not limited. Thus, the present invention can be used as DRAM in future. Secondly, the capacitor is used as a memory element in the general DRAM. On the other hand, no capacitor is used in the present invention. Thus, as compared to the DRAM, the area of the unit cell can be reduced, thereby improving the integration. Thirdly, in the general DRAM, the process is complicated because the capacitor is formed with the trench or crown shape in order to obtain the large capacitance in the unit area. However, no capacitor is used in the present invention, thereby simplifying the process.

Claims: A semiconductor memory device having a memory cell array a unit cell of which comprises: a memory cell transistor (Mm,n) with a floating gate (F.G, 13), a control gate (C.G; 14) connected to a wordline (W/Ln), and drain and source electrodes (12) connected to respective bitlines (B/Ln, B/Ln+1), and a passing transitor (Qm,n) with a source connected with the floating gate for applying a voltage thereto in accordance with a data to be stored, a drain connected with the floating gate (F.G, 13) and intended to be in a floating condition, and a gate electrode connected to a gate line (G/Ln) provided substantially in parallel with the wordline (W/Ln); wherein the drain of the passing transistor (Qmn) of a unit cell of one row and one column is connected to the source of the passing transistor (Qm+1,n) of the adjacent unit cell of the next row of the same column. The semiconductor device as claimed in claim 1, wherein a sensing amplifier (SA) is connected to each bit line (B/Ln). The semiconductor memory device as claimed in claim 1 or 2, wherein an end terminal of each of said bit lines (B/Ln) is intended to be floating. The semiconductor memory device as claimed in one of the claims 1 to 3, comprising: a semiconductor substrate (11). a plurality of impurity regions (12) formed on said semiconductor substrate (11) in one direction and spaced apart by a constant distance, a plurality of floating gate electrodes (13) formed on said semiconductor substrate (11) between said impurity regions (12) for storing electric charge, said floating gate electrodes (13) having impurity regions of the first and the second conductivity type alternately repeated therein, a plurality of control electrodes (14) spaced apart by a constant distance on each floating gate electrode (13) and said semiconductor substrate (11) and formed in the perpendicular direction with respect to said floating gate electrode (13), and a plurality of gate electrodes (15) of passing transistors spaced apart by constant distance on each floating gate electrode (13) and said semiconductor substrate (11) and formed between said respective control electrodes (14). The semiconductor memory device as claimed in claim 4, wherein said semiconductor substrate (11) is formed of a first conductivity type and said impurity region (12) is formed of a second conductivity type. The semiconductor memory device as claimed in claim 5, wherein said semiconductor substrate (11) is formed of a P-type and said impurity region is formed of an N-type. The semiconductor memory device as claimed in claim 4 or 5, wherein said floating gate electrode (13) under said control electrode (14) is formed of a second conductivity type and said floating gate electrode (13) under said gate electrode (15) of said passing transistor is formed of a first conductivity type. The semiconductor memory device as claimed in claim 7, wherein said floating gate electrode (13) under said control electrode (14) is formed of an N-type and said floating gate electrode (13) under said gate electrode (15) of said passing transistor is formed of a P-type. The semiconductor memory device as claimed in any one of claims 4-8, wherein said floating gate electrode (13) on both sides of said gate electrode (15) of said passing transistor is used as source and drain regions. The semiconductor memory device as claimed in any one of claims 4-9, wherein a field insulating film (16) is formed on said semiconductor substrate (11) at a portion where said gate electrode of said passing transistor and said floating gate electrode (13) cross. The semiconductor memory device as claimed in claim 10, wherein a channel isolating impurity region is formed instead of said field insulating film (16). The semiconductor memory device as claimed in any one of claims 4-11, wherein said floating gate electrode (13) is formed of a poly-crystalline silicon. The semiconductor memory device as claimed in any one of claims 4-12, wherein said control electrode (14) is formed of an impurity-doped polycrystalline silicon. The semiconductor memory device as claimed in any one of claims 4-12, wherein said control electrode (14) is formed of a metal. The semiconductor memory device as claimed in any one of claims 4-14, wherein said gate electrode (15) of said passing transistor is formed of an impurity-doped polycrystalline silicon. The semiconductor memory device as claimed in any one of claims 4-14, wherein said gate electrode (15) of said passing transistor is formed of a metal. A method of manufacturing a semiconductor memory device having a memory cell array, comprising the steps of: forming field insulating films (16) of an island shape on a semiconductor substrate (11) of a first conductivity type; forming impurity regions (12) of a second conductivity type on the semiconductor substrate (11) in a column direction between the field insulating films (16); forming a first gate insulating film (17) on the entire surface of the resultant structure; forming floating gate electrodes (13) so that impurity regions of the first conductivity type and the second conductivity type are repeated therein, on the first gate insulating film (17) including the field insulating films (16) in the column direction between the impurity regions (12) of the second conductivity type; forming a second gate insulating film (18) on the entire surface of the resultant structure; forming control electrodes (14) on the second gate insulating film (12) between the field insulating films in a perpendicular direction of the floating gate electrodes (13); and forming gate electrodes (15) of passing transistors between the control electrodes (14). The method of manufacturing a semiconductor memory device as claimed in claim 17, wherein a method. of forming said field insulating film (16) comprises the step of: depositing a buffer oxide film, a nitride film and a resist film on said semiconductor substrate of said first conductivity type; defining a field region of an island shape through exposure and development process, to thereby selectively remove said nitride film in said field region; thermally oxidizing said silicon substrate of said first conductivity type to form a field oxide film on said field region; and removing said resist film, said nitride film and said buffer oxide film. The method of manufacturing a semiconductor memory device as claimed in claim 17, wherein a first conductivity type ion is implanted to form a channel isolation region, instead of using said field insulating film. The method of manufacturing a semiconductor memory device as claimed in claim 19, wherein a method of forming said field isolation region comprises the steps of: depositing a resist film on said semiconductor substrate of said first conductivity type; defining a field region of an island shape through exposure and development process, to thereby selectively expose said semiconductor substrate of said first conductivity type; implanting a first conductivity type impurity ion on said exposed semiconductor substrate of said first conductivity type, to thereby form a channel isolation region; and removing said resist film. The method of manufacturing a semiconductor memory device as claimed in claim 17, wherein said first gate insulating film is formed to a thickness of 70~200Å, 10Å = 1nm. The method of manufacturing a semiconductor memory device as claimed in claim 17, wherein an impurity concentration of said impurity region of .said second conductivity type is 10 18 ~10 21 atoms/cm 3 . The method of manufacturing a semiconductor memory device as claimed in claim 17, wherein a method of forming said floating gate electrode (13) comprises the steps of: depositing a semiconductor layer of said first conductivity type and a resist film on said first gate insulating film, sequentially; exposing said first conductivity type semiconductor layer of a portion excluding the upper side of said field insulating film, through exposure and development process; implanting an impurity ion of said second conductivity type on said exposed semiconductor layer of said first conductivity type; and removing said resist film and patterning so that said first conductivity type semiconductor layer wherein said ion is implanted is left only on said first gate insulating film between said impurity region of said second conductivity type, through a lithography process. The method of manufacturing a semiconductor memory device as claimed in claim 23, wherein said semiconductor layer of said first conductivity type is formed of a P-type polycrystalline silicon. The method of manufacturing a semiconductor memory device as claimed in claim 23 , wherein an impurity concentration of said semiconductor layer of said first conductivity type is 10 15 ~10 18 atoms/cm 3 . The method of manufacturing a semiconductor memory device as claimed in claim 23, wherein an impurity concentration of said second conductivity type impurity ion is 10 18 ~10 21 atoms/cm 3 . The method of manufacturing a semiconductor memory device as claimed in claim 17, wherein a method of forming a floating gate electrode (13) comprises the steps of: depositing a semiconductor layer of said first conductivity type on said first gate insulating film; patterning said semiconductor layer of said first conductivity type so as to be left only on said first gate insulating film between said second conductivity type impurity regions; and selectively implanting an impurity ion of said second conductivity type on a portion formed between said field insulating films in said patterned semiconductor layer of said first conductivity type. The method of manufacturing a semiconductor memory device as claimed in claim 27, wherein said semiconductor layer of said first conductivity type is formed of a P-type polycrystalline silicon. The method of manufacturing a semiconductor memory device as claimed in claim 27, wherein an impurity concentration of said semiconductor layer of said first conductivity type is 10 15 ~10 18 atoms/cm 3 . The method of manufacturing a semiconductor memory device as claimed in claim 27, wherein an impurity concentration of said second conductivity type impurity ion is 10 18 ~10 21 atoms/cm 3 . The method of manufacturing a semiconductor memory device as claimed in claim 17, wherein said second gate insulating film is formed of an oxide film, a structure where nitride film/oxide film are stacked, or a structure where oxide film/nitride film/oxide film are stacked. The method of manufacturing a semiconductor memory device as claimed in claim 17, wherein a method of forming said control electrode (14) comprises the steps of: forming a semiconductor layer of said second conductivity type and a cap insulating film on said second gate insulating film, sequentially; selectively removing said cap insulating film and said semiconductor layer of said second conductivity type so as to be left between said field insulating films in the perpendicular direction with respect to said floating gate electrode; and forming an insulating sidewall on the sidewall of said cap insulating film and semiconductor layer of said second conductivity type. The method of manufacturing a semiconductor memory device as claimed in claim 32, wherein said semiconductor layer of said second conductivity type is formed of an N-type polycrystalline silicon. The method of manufacturing a semiconductor memory device as claimed in claim 33, wherein an impurity concentration of said N-type polycrystalline silicon is 10 18 ~10 21 atoms/cm 3 . The method of manufacturing a semiconductor memory device as claimed in claim 32, wherein a metal is used instead of said semiconductor layer of said second conductivity type. The method of manufacturing a semiconductor memory device as claimed in claim 17, wherein a gate electrode (15) of said passing transistor is formed of a semiconductor layer of said second conductivity type. The method of manufacturing a semiconductor memory device as claimed in claim 36, wherein said semiconductor layer of said second conductivity type is formed of an N-type polycrystalline silicon. The method of manufacturing a semiconductor memory device as claimed in claim 37, wherein an impurity concentration of said N-type polycrystalline silicon is 10 18 ~10 21 atoms/cm 3 . The method of manufacturing a semiconductor memory device as claimed in claim 36, wherein a metal is used instead of said semiconductor layer of said second conductivity type.

Inventors: PARK KEUN HYUNG, PARK, KEUN HYUNG
Applicants: LG SEMICON CO LTD, LG SEMICON CO., LTD.
Application year: 1996
Main classification: H01L27
IPC codes: H01L21, G11C14, H01L29, H01L27