A METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE COMPRISING AN IMPLANTATION STEP

Abstract: A method for producing a semiconductor device having a semiconductor layer (2) of SiC comprises at least the steps of applying an insulating layer (1) on said semiconductor layer, implantation of an impurity dopant into said semiconductor layer and annealing this layer at such a high temperature that the implanted impurities are activated. Said insultating layer is applied before and maintained on said semiconductor layer during said annealing step. A material having AlN as major component is applied on said semiconductor layer as said insulating layer.

Description: A method for producing a semiconductor device compri- sing an implantation step TECHNICAL FIELD OF THE INVENTION AND PRIOR ART The present invention relates to a method for produc¬ ing a semiconductor device having a semiconductor layer of SiC, said method comprising at least the steps of applying an insulating layer on said semi¬ conductor layer, implantation of an impurity dopant -Into said semiconductor layer and annealing this layer at such a high temperature that the implanted impurities are activated, said insulating layer being applied before and maintained on said semiconductor layer during said annealing step. The production of all types of semiconductor devices is comprised, such as for example different types of diodes, transistors and thyristors. Such devices are particularly used in applications in which it is possible to benefit from the superior properties of SiC in comparison with especially Si, namely the capability of SiC to function well under extreme conditions. SiC has a high thermal stability due to a large band gap energy, such that devices fabricated from said material are able to operate at high temperatures, namely up to 1000 K. Furthermore, it has a high thermal conductivity, so that SiC- devices can dissipate a high power without overheat¬ ing. SiC also has a more than five times higher breakdown field than Si , so that it is well suited as a material in high power devices operating under con¬ ditions where high voltages may occur in the blocking state of a device . However, this extreme chemical and physical stability of the SiC necessitates an annealing after said implantation at comparatively high temperatures , mostly above 1500 °C and not seldom above 1700 ° C, for activating implanted impurities , which makes it impos s ible to leave said insulating layer on the semiconductor layer during this heat treatment would traditional insulating materials , such as Siθ 2 , be used . One type of method according to the introduction is known through US patent 5 384 270, which describes a method of producing a silicon carbide MOSFET using a so called self alignment technique, i.e. the implan- tation of impurity dopants into said semiconductor layer of SiC is made while using layers comprising the device itself, here the gate electrode, as a mask for the ion implantation. Accordingly, the insulating layer has to be there before the ion implantation and will also be there during the following annealing step. In this case Siθ2 is accordingly used as insulating layer and the annealing temperature required for efficient activation after an implanta¬ tion will damage the insulating layer, so that a semiconductor device produced in the way described in this US patent will not have an appropriate function, especially will the insulating properties be degraded and the conductivity in the inversion channel will be reduced. The same problem exists in all types of methods in which an implantation step is carried out and it is desired or absolutely necessary that an insulating layer remains on the SiC-layer during the annealing step, for instance for being left on the device for passivation purposes. SUMMARY OF THE INVENTION The object of the present invention is to provide a method according to the introduction, which makes it possible to produce semiconductor devices having a semiconductor layer of SiC by using ion implantation while solving the problems discussed above. This object is in accordance with the invention obtained by applying a material having AIN as major component on said semiconductor layer as said insu¬ lating layer. AIN can be made stable at least up to 2000 K and thus well capable of withstanding the high temperature activation anneal following the implanta- tion step, so that this insulating layer will not be destroyed by said annealing. Furthermore, AIN has a very good lattice match with SiC with a misfit of only 0,7% and it has nearly the same coefficient of thermal expansion as SiC, so that it will be possible to grow an insulating layer having AIN as a major component with a high quality on the SiC semiconduc¬ tor layer, and this insulating layer will not be negatively affected by the high annealing tempera¬ tures required for activating impurities implanted in SiC. The expression "as major component" means that it will be possible to add some other components to AIN for forming said insulating layer, such as smaller amounts of other Group III B-nitrides should this be desired, but such additions will decreasing the lattice match with SiC. The use of a material having AIN as major component as an insulating layer in a method for producing a semiconductor device of this type has many advantages, which will appear from the discussion of preferred embodiments of the invention following below, wherein said insulating layer may be used for utilising the self aligned technology for isolated gate devices, as a mask for said implantation and be left on the device as a pas¬ sivation layer and so on. According to another preferred embodiment of the in- vention the material is Al x B ( i__ x) N. By adding B to AIN the lattice match of the insulating layer to SiC may be improved. A theoretical perfect lattice match will be obtained when x is about 0,96, i.e. the B- content is about 4%. A B-content in AIN will also in- crease the bandgap and the breakdown voltage thereof. Furthermore, AIBN is more resistent to oxidation than AIN. According to a preferred embodiment of the invention said method comprises at least a step of self aligned implantation, and said insulating layer is present during this step. Thus, it will be possible to use such a layer having AIN as major component as the in¬ sulating dielectric for the production of isolated gate devices, since the insulating layer is not degraded by the activation anneal, so that this very advantageous technique for the production of semicon¬ ductor devices may be used also for the production of isolated gate devices with a semiconductor layer of SiC. This technique is very advantageous with respect to other production techniques, since you do not need any realignment between the different steps . Another advantage of this technique is that the correct alignment obtained thereby enables the reduction of parasitic losses due to limits otherwise placed in the device structure, for example capacitances resulting from overlaps. According to another preferred embodiment of the in¬ vention a gate material, this material being a suit¬ able refractory metal, for example Ta, layer for said semiconductor device is applied on said insulating layer before said step of self aligned implantation, said gate material layer leaving at least one opening for the penetration of the implanted impurity dopant into said semiconductor layer during said step of self aligned implantation for making the implanted region in said semiconductor layer aligned with said opening. This method has the advantages discussed above, and it may for instance be used for the production of isolated gates semiconductor devices with an insulating layer still having an excellent quality after the high temperature anneal for acti¬ vating the impurity dopant implanted in the SiC- layer. According to another preferred embodiment of the in¬ vention said method comprises a step of implantation of a P-type impurity dopant, and said insulating layer is present during the activation annealing af¬ ter this implantation. It is very advantageous to be able to introduce acceptors as impurity dopants by the implantation technique, since these acceptors need a higher annealing temperature for being acti¬ vated than the donors, so that this case is particu¬ larly troublesome with known insulating materials, but the thermal stability of AIN allows these high temperatures . According to a further preferred embodiment of the invention said insulating layer is used as a mask for implantation for preventing the areas of said semi¬ conductor layer located therebehind being reached by the impurities implanted. The use of an insulating layer having AIN as major component as an implanta¬ tion mask is very advantageous, since AIN is a radiation hard material, i.e. it is only damaged on the surface due to a high resistance to implantation and the ions so implanted in the surface layer thereof will not diffuse through said mask to the in¬ terface with the semiconductor layer during the annealing step. Thus, high implantation energies are required for implantation in SiC and the use of AIN as an implantation mask makes it possible to design such a mask with a reasonable thickness, whereas other materials, such as Siθ2, as mask material have to be much thicker. A layer having AIN as major component can therefore be used as an implantation mask enabling structures to be defined in a non-mesa planar technology, for example implanted p-n diodes, field rings etc. The mask layer will remain intact as a means of device isolation (passivation) . According to a preferred development of the embodi¬ ment of the invention described above and including the application of a gate material layer, said gate is made of a refractory metal, and this metal is TiN. This refractory metal makes it possible to use the self aligned technology for producing isolated gate devices having a semiconductor layer of SiC, since it will not be damaged by the high annealing tempera¬ tures needed for activation of the impurities im¬ planted. Furthermore, the gate of TiN and said insulating layer, when it is made of AIN, may be grown in one single growth run facilitating the production of the semiconductor device. According to another preferred embodiment of the in- vention said insulating layer is applied on said semiconductor layer at a thickness allowing implanta¬ tion therethrough but adapted to prevent out-diffu- sion of the dopants and Si-evaporation from the SiC surface during said annealing step. Selecting such a thickness of the insulating layer will make it possible to allow implantation into the SiC-layer therebehind while at the same time taking advantage of the low diffusivity in AIN for preventing out-dif¬ fusion and Si-evaporation during the high temperature annealing step. The invention also comprises a use of a material hav¬ ing AIN as major component in a semiconductor device having a semiconductor layer of SiC, said device be¬ ing created by a method comprising ion implantation and annealing at high temperatures for activating the implant in the presence of said material, as well as a semiconductor device produced by carrying out a method comprising the characteristics according to any of the appended method claims . The advantages of this use and such a semiconductor device has been discussed above. Such a device will of course be most suitable for high power applications thanks to the physical characteristics of SiC and AIN. Further advantages and preferred features of the in- vention will appear from the following description and the other dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS With reference to the appended drawings, below follows a specific description of preferred embodi¬ ments of the invention cited as examples. In the drawings : Fig 1 - 4 illustrate schematically different steps of a method for producing a semiconductor power device in the form of an isolated gate device of SiC accord¬ ing to a first preferred embodiment of the invention, and Fig 5-6 illustrate schematically two of the steps of a method for producing a semiconductor power device in the form of a rectifier diode of SiC according to a second preferred embodiment of the invention. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS OF THE INVENTION Fig 1 - 4 illustrate a few important steps of a large number of steps of a method according to the inven- tion for producing an isolated gate device made of SiC for a high power application by using the implan¬ tation technique and in one step the self alignment technique. A thin insulating layer 1 of AIN has been epitaxially grown onto a low doped N-type semiconduc- tor layer 2 of SiC, and a mask 3 is applied onto an area of said insulating layer 1 for preventing that the areas of said semiconductor layer located there- behind are reached by the impurities implanted in an ion implantation step described below. The insulating layer 1 may have a thickness of about 500 A allowing implantation therethrough. The donor concentration in the low doped layer 2 will typically be about 10^5 cm ~ 3. The crystal is exposed to a bombardment of ions having a kinetic energy of several hundred keV or more, for instance 300 keV, for implanting impurities of P-type into said semiconductor layer 2. These high energies are needed as a consequence of the physical properties of SiC, and a kinetic energy of 300 keV may for instance result in a penetration depth of less than 1 μm in the SiC-layer. Said impurities may for instance be B or Al . The implantation process is indicated by the arrows 4. In this way a doped P-type layer 5 will be formed in the SiC crystal in the area not covered by said mask 3. After that said mask 3 is removed, for instance by Reactive Ion Etching (RIE) , and the crystal is heated to a temperature exceeding 1700°C for activating the acceptors implanted in said P-type layer 5. The insulating layer 1 of AIN is well capable of with¬ standing these high temperature activation anneal and will also prevent out-diffusion of the dopants and Si-evaporation from the SiC-surface during the annealing step. Fig 2 shows the crystal after said annealing step. After that a gate electrode material 6 is applied on a part of the insulating layer 1, and a further mask 7 is applied on another part thereof leaving an opening 8 therebetween for ion implanta¬ tion. Said gate electrode 6 is made of a refractory metal, for instance TiN. After that an implantation step (see arrows 9) is carried out for implantation cf a N-type impurity dopant in the SiC-layer behind said opening 8. In this way a highly doped, for instance 10^- cm " 3/ N-type layer 10 is obtained. This layer 10 is aligned with the gate electrode 6, which will remain intact in the semiconductor device, so that this implantation step uses the self alignment technology. After that said mask 7 is removed and the crystal is annealed for activating the donors im¬ planted in the highly doped N-type layer 10. The A1N- layer 1 will have the same function during this annealing step as during the annealing step described above. Following the annealing step a source area covering the implanted N + -layer and also partly the P-layer is etched away and a metal contact layer 11 forming the source is grown. In this way a semiconductor device having a gate 6 isolated by an isolating layer 1 having a high quality has been produced by using the self aligned technology. The device has a source 11 and a drain not shown connected to the N + substrate on which the low-doped N-type layer 2 is grown. The current through this device may be controlled by controlling the gate potential. Fig 5 and 6 illustrate some steps of another pre¬ ferred method according to the invention, in which AIN is used as a material for an implantation mask and left after said implantation for passivation pur¬ poses. A layer 12 of AIN is grown onto a low-doped N- type SiC crystal 13. In a region of said insulating layer 12 insulating layer material is removed by a suitable technique, so that there will be a thin layer portion 14 having a thickness allowing the penetration of ions therethrough during an implanta¬ tion step thereafter. Thus, the thickness of this layer portion 14 may be for instance 0,05 μm, whereas the thickness of the rest of the layer 12 may be for instance 1 μm, which will be enough for preventing implantation ions to reach the interface between said layer 12 and the SiC semiconductor layer 13. It may be mentioned that a layer of AIN having a thickness of 1,28 μm will be required to prevent boron having a kinetic energy of 1 MeV from penetrating to said in¬ terface, and boron is the P-type impurity that penetrates most deeply into a layer of AIN. Thus, a mask made of AIN or having AIN as major component may be made comparatively thin thanks to the radiation hardness of AIN. After that the crystal is bombarded by a P-type impurity (see arrows 15) , for instance Al or B, and these impurities will penetrate through the thin layer portion 14 but not through the layer 12 forming an implantation mask. Thus, a P-type doped region 16 is formed below or behind said layer portion 14. After that the crystal is annealed at a temperature above 1700°C for activating the acceptors in said region 16. During this anneal said thin layer portion 14 prevents out-diffusion of dopants from the region 16, and the layer 12 will not in any way be harmed by the high temperatures thanks to the physi¬ cal properties of AIN. After said activation anneal¬ ing said layer portion 14 is removed by for instance reactive ion etching, and an ohmic contact 17 is af¬ ter that applied in the opening so formed in the in- sulating layer 12. The insulating layer 12 is then left as a passivation layer of the rectifier diode so created. Accordingly, an insulating layer of AIN or of a material having AIN as major component makes it possible to use the ion implantation technique for p-roducing semiconductor devices of SiC when it is a requirement or a desire to have said insulating layer present during the high temperature anneal for activating the impurity dopant implanted. The invention is of course not in any way restricted to the preferred embodiments described above, but many possibilities to modifications thereof will be apparent to a man with ordinary skill in the art. As mentioned in the introduction the invention is ap¬ plicable to all types of semiconductor devices, preferably semiconductor devices adapted to operate under extreme conditions, such as high voltages and the generation of large amounts of heat, while taking advantage of the physical properties of SiC. The invention does not only cover methods for produc- ing SiC semiconductor devices according to the two embodiments described above, but every production method in which an implantation and after that an an- nealing takes place in the presence of an insulating layer is within the scope of the invention. The invention also comprises methods in which N-type impurity dopants, such as N and P, are implanted and a high temperature activating anneal is used thereaf¬ ter. All definitions concerning the materials of the dif- ferent device layers do of course also include inevi¬ table impurities as well as intentional doping when SiC is concerned. The definition layer is to be interpreted broadly and comprise all types of volume extensions and shapes.

Claims: Claims 1. A method for producing a semiconductor device hav¬ ing a semiconductor layer (2) of SiC, said method comprising at least the steps of applying an insulat¬ ing layer (1) on said semiconductor layer, implanta¬ tion of an impurity dopant into said semiconductor layer and annealing this layer at such a high tem¬ perature that the implanted impurities are activated, said insulating layer (1) being applied before and maintained on said semiconductor layer during said annealing step, characterized in that a material having AIN as major component is applied on said semiconductor layer (2) as said insulating layer (1) . 2.. A device according to claim 2, characterized in that the material is Al x B ( i__ x) N. 3. A device according to claim 2, characterized in that x is between 0.92 and 0.98, preferably around 0.96. 4. A method according to claim 1, characterized in that said material is AIN. 5. A method according to any of claims 1-4, characterized in that it comprises at least a step of self .aligned implantation, and that said insulating layer (1) is present during this step. 6. A method according to claim 4, characterized in that a gate material layer (6) for said semiconductor device is applied on said insulat- ing layer (1) before said step of self aligned implantation, said gate material layer leaving at least an opening (8) for the penetration of the implanted impurity dopant into said semiconductor layer (2) during said step of self aligned implanta¬ tion for making the implanted region (10) in said semiconductor layer (2) aligned with said opening. 7. A method according to claim 6, characterized in that it is used for producing iso¬ lated gate semiconductor devices. 8. A method according to any of claims 1-7, characterized in that it is used for producing a MIS- FET (Metal-Insulator-Semiconductor Field Effect Transistor) . 9. A method according to claim 8, characterized in that it comprises the following s.teps carried out in the order mentioned: implanting an impurity dopant of P-type into a first region (5) of a low doped N-type SiC-layer (2) where this is not covered by a mask (3) blocking penetra¬ tion of implanted ions, said SiC-layer being covered by a thin insulating layer (1) of a material having AIN as major component, annealing said SiC-layer (2) for activating said implanted impurities, applying a gate material layer (6) onto said insulating layer after removal of said mask while leaving an opening above a part of said P-type region, implanting an im¬ purity dopant of N-type into a self aligned region (10) of said P-type region for forming a N-type region surrounded by said P-type region and annealing the SiC-layer for activating the impurities implanted in said self aligned N-type region. 10. A method according to any of claims 1-9, characterized in that it comprises at least a step of annealing ir. the presence of said insulating layer (1) at a temperature above 1500°C. 11. A method according to claim 10, characterized in that said temperature is above 1700°C. 12. A method according to any of claims 1-11, characterized in that it comprises a step of implan¬ tation of a P-type impurity dopant, and that said in¬ sulating layer (1, 12, 14) is present during the ac- tivation annealing after this implantation. 13. A method according to any of claims 1-11, characterized in that it comprises a step of implan¬ tation of a N-type impurity dopant, and that said in- sulating layer (1, 12, 14) is present during the ac¬ tivation annealing after this implantation. 14. A method according to claim 1, characterized in that said insulating layer (12) is used as a mask for implantation for preventing that the areas of said semiconductor layer located there- behind are reached by the impurities implanted. 15. A method according to claim 1, characterized in that said insulating layer (12) is left on said semiconductor device as a passivation layer. 16. A method according to claim 6, characterized in that said gate (6) is made of a re¬ fractory metal. 17. A method according to claim 16, characterized in that said gate (6) is made of TiN. 18. A method according to claim 17 10 characterized in that said gate (6) of TiN and said insulating layer (1) being of AIN are grown in one single step. 19. A method according to any of claims 1-13 or 15- 18, characterized in that said insulating layer (1, 14) is applied on said semiconductor layer (2, 13) at a thickness allowing implantation therethrough but adapted to prevent out-diffusion of the dopants and Si-evaporation from the SiC surface during said annealing step. 20. A method according to any of the preceding claims, characterized in that it is used for producing high power devices. 21. A method according to claim 11, characterized in that said P-type impurity dopant is one of a) B and b) Al . 22. A use of a material having AIN as major component in a semiconductor device having a semiconductor layer of SiC, said device being created by a method comprising ion implantation and annealing at high temperatures for activating the implant in the presence of said material. 23. A semiconductor device produced by carrying out a method comprising the characteristics according to any of claims 1-19.

Inventors: HARRIS CHRISTOPHER, ROTTNER KURT, HARRIS, CHRISTOPHER, ROTTNER, KURT
Applicants: ABB RESEARCH LTD, HARRIS CHRISTOPHER, ROTTNER KURT, ABB RESEARCH LIMITED, HARRIS, CHRISTOPHER, ROTTNER, KURT
Application year: 1996
Main classification: H01L21
IPC codes: H01L21