CMOS PROGRAMMABLE RESISTOR-BASED TRANSCONDUCTOR

Abstract: An active termination resistor is provided within a feedback loop circuit thus advantageously increasing the stability of the feedback loop circuit. In particular, the active termination resistor traces the impedance of the feedback loop such that R(f) = 1/GM3(f). The active resistor may also be configured to track the value of the resistor to set the feedback transconductance over process and temperature variations to ensure stability of the feedback loop over these variations.

Description: ACTIVE RESISTOR FOR STABILITY COMPENSATION Background of the Invention The present invention relates to the use of active resistors in the control of the loop gain of an active circuit. It is known to provide a gain circuit using input transconductors in combination with an amplifier. A transconductor is a circuit which receives an input voltage and generates an output current. The magnitude of the output current of the transconductor is proportional to the input voltage received. The ratio by which the output current changes for a given ratio of input voltage change is known as the conversion gain, or transconductance (GM) , of the transconductor. A differential transconductor receives a differential voltage impressed between two input terminals (ignoring the common-mode voltage) and generates a differential current on two current output terminals. Fig. 1, labeled prior art, shows an example of a circuit which performs a gain or filter function. The circuit includes an input transconductor (GM1) which converts the voltage received at its input to a differential current at its outputs, an amplifier (A) , which amplifies the signal provided by the input transconductor, feedback resistors (RF1 and RF2) , feedback capacitors (CF1 and CF2) and a termination resistor (R) , which is provided at the input of the summation amplifier. Such a circuit may be used as a gain or filter stage in more complex linear circuitry. For stability, the magnitude of the loop gain of a circuit must be less than one before the phase shift around the loop exceeds 360°. In the case of the Fig. 1 circuit, if the output impedance of amplifier A is much less than the value of the resistors RF1, RF2, then the loop gain is equal to the open loop gain of amplifier A. Thus, if amplifier A is stable, the loop gain the circuit including feedback resistors RFl, RF2, feedback capacitors CFl, CF2 and input transconductor GM is stable. Summary of the Invention It has been discovered that providing an active termination resistor to a feedback loop circuit which includes a feedback transconductor advantageously increases the stability of the feedback loop circuit. In particular, stability is increased by causing resistance of the active termination resistor to track the transconductance of the feedback transconductor over process and temperature such that the resistance of the termination resistor is equal to or less than s the inverse of the transconductance of the feedback transconductor. I.e., R^ πn ≥ 1/GM^,,,,,,.. Such an active resistor advantageously provides a reduction in the area needed to stabilize a gain stage over the use of a passive resistor connected between o the input nodes of an amplifier. This invention is especially advantageous in situations where low frequency poles are required because the area required to implement a passive termination resistor in an integrated circuit could be prohibitive to the 5 implementation of such an integrated circuit. Brief Description of the Drawings Fig. 1, labeled prior art, shows a schematic block diagram of a typical feedback loop circuit. o Fig. 2 shows a schematic block diagram of a feedback loop circuit which includes an active termination resistor in accordance with the present invention. Fig. 3 shows a schematic block diagram of an 5 active resistor along with an active resistor bias generator in accordance with the present invention. Fig. 4 shows a schematic block diagram of an alternate active termination resistor in accordance with the present invention. Detailed Description The following sets forth a detailed description of the best contemplated mode for carrying out the invention. The description is intended to be illustrative of the invention and should not be taken to be limiting. Referring to Fig. 2, feedback loop circuit 20 includes input transconductor 21 (GM1) , amplifier 22 (A) , feedback transconductor 24 (GM2) , and active termination resistor circuit 26 coupled across the input terminals of amplifier 22. Active termination resistor circuit 26 includes active resistor 27 and termination resistor bias generator 28. Input transconductor 21 receives a differential input signal and provides a differential current to the inverting and non-inverting input terminals of amplifier 22. Amplifier 22 provides a differential output voltage signal as well as the input signal to feedback transconductor 24. Feedback transconductor 24 provides a differential feedback signal to the input terminals of amplifier 22 proportional to the voltage output of amplifier 22. The input terminals of amplifier 22, across which active termination resistor circuit 26 is coupled, functions as virtual grounds by virtue of the high gain of amplifier 22 and the feedback paths from feedback transconductor 24 to the input terminals of amplifier 22. With a virtual ground, the voltage difference at the input of amplifier 22, V x , is represented by the equation "-S where A is the open loop gain of amplifier 22 and V CΛ is the output voltage of amplifier 22. Termination resistor bias generator 28 generates voltages to control the resistance of active resistor 27 such that the resistance tracks resistance of the resistor which is used to establish the transconductance of feedback transconductor 24. The loop gain of feedback loop circuit 20 is equal to the open loop gain of amplifier 22 multiplied by the transconductance of feedback transconductor 24 multiplied by the resistance (R eff ) which is provided by the parallel combination of output resistance of transconductor 24 and the resistance of active termination circuit 26. More specifically, the loop gain of feedback loop circuit 20 is set forth by the equation LoopGain= A( ) • GMXJ) ■ R^ where, R tff l which represents the effective resistance of the feedback loop, is set forth by the equation R - R " m ' RQ and R„ equals the output resistance of feedback transconductor 24. In the case that the terminator is removed from the open loop gain circuit 20, R eff is simply equal to the output resistance of transconductor 24, which is very high, e.g., >100 Moh s. Thus, the loop gain of the circuit is very high and the circuit is nearly impossible to stabilize. By adding active termination resistor 26 to circuit 20, the effective resistance is essentially the resistance of active termination resistor 26. If the resistance of active termination resistor 26 is equal to the inverse of the transconductance of feedback transconductor 24, then the loop gain is equal to the gain of amplifier 22. In this condition, when the amplifier is stable, the open loop circuit 20 is stable. The stability of the feedback loop may be arbitrarily increased by lowering the resistance of active resistor 27. However, lowering the resistance of active resistor 27 below the inverse of the transconductance of transconductor 24 increases systematic offset and distortion within open loop gain circuit 20. Referring to Fig. 3, active termination resistor 27 includes P channel metal oxide semiconductor (PMOS) transistor 30 and N channel metal oxide semiconductor (NMOS) transistor 32, which are referred to as transistors P5 and N5, respectively. Transistors 30, 32 are biased to operate in their linear region by the TN and TP output signals of termination resistor bias generator 28. Termination resistor bias generator 28 includes amplifier 40, current mirror 42, current mirror circuit 44 as well as bias circuit 46. Termination resistor bias generator 28 also includes bias resistor 58, which is referred to as resistor Rl. Current mirrors 42 and 44 along with bias resistor 58 provide a current bias generator. Current mirror 42 includes PMOS transistors 50, 52, which are referred to as transistors PI and P2, respectively. Current mirror 44 includes NMOS transistors 54, 56, which are referred to as transistors Nl and N2, respectively. Bias circuit 46 includes transistors 60, 62, 64, 66, which are referred to as P3, N4 and P4, N3, respectively. Transistors PI and P2 are the same size and thus provide a 1:1 current mirror. The current, I ref , which is provided by the drains of transistors PI and P2, is determined by transistors Nl, N2 and resistor Rl. More specifically, the current I ref is determined by the difference in the gate length and width of transistors Nl and N2, the mobility and gate oxide thickness of transistors Nl and N2 and the resistance of resistor Rl. In the preferred embodiment, the width versus length (W/L) ratios of transistors PI, P2 and P3 are equal as are the W/L ratios of transistors Nl and N3. The W/L ratio of transistor N2 is greater than the W/L ratio of transistor Nl. Accordingly, the current I ref flows in all circuit legs as shown by the following equation. / - ^ nf RΫ where and Where μ d represents the mobility of the majority carriers, C ox is the capacitance per unit area of the gate of the referenced transistor, W dy is the gate width of the referenced transistor, L dy is the gate length of the referenced transistor and the subscript dy is a variable which represents the particular transistor, e.g., K N , is the equation for transistor Nl. Termination resistor circuit 26, also includes a common mode feedback circuit (not shown) which forces a common mode loop voltage to V com at the input terminals of summation amplifier 22. By virtue of the virtual ground between the input terminals of amplifier 22, the differential voltage on the input terminals of amplifier 22 is a very small value (V x = V 0 /A(f)). Accordingly, the transistors of termination resistor circuit 26 effectively have the voltage V com on both the drain and source terminals. In operation, transistor N5 is operating in its linear region of operation when terminals 68 and 69 are held to the common mode reference voltage V c . Accordingly, its drain to source resistance, R,,,, is = l - where the voltage TN is defined by the equation: substituting the derivation for the voltage TN in the equation for R ds yields Likewise, in operation, transistor P5 is operating in its linear region of operation when terminals 68 an d 69 are held to the common mode reference voltage V com. Accordingly, its drain to source resistance, R ds , is * = where the voltage TP is defined by the equation: M TP = V„ * + VT Pi + substituting the derivation for the voltage TP in t h e equation for R d5 yields Accordingly, the value R di is dependent directly upon the value of bias resistor Rl. For the N channel transistors, the mobility variations cancel and the remaining terms provide a scale constant dependent upon the geometry's (i.e., the W/L ratio) of transistors Nl, N2, N4, and N5. For the P channel transistors, the mobility variations substantially cancel and the remaining terms provide a scale constant dependent upon the geometry's of transistors PI, P2, P4 and P5. These geometry's are constant for a particular active resistor circuit. The final R,,. of active resistor circuit 26 is actually the effective resistance of the parallel R d5 's of P5 and N5. Two devices are provided to address power-up transients that might be present when a single N or P device is activated. The same type of passive resistor that is used to determine the GM of the feedback transconductor 24 is also used for Rl in the current bias generator to ensure that the effective R,,. which is provided by the parallel drain to source resistances of P5 and N5 is equal to 1/GM3. In practice, R Λs is set slightly lower, e.g., about 10% lower, to provide additional stability to compensate for the excess phase shift in feedback transconductor 24. Other Embodiments Other embodiments are within the following claims. For example, while two devices, P5 and N5, are shown in the preferred embodiment, only one device is necessary to form Rds. Alternately, other combinations of active resistors may be provided or parallel or in series to aid in programmability of the loop gain of the feedback loop circuit 20 and thus provide programmable stability. Also for example, referring to Fig. 4, an alternate active resistor circuit may be provided. Such an active resistor circuit would be preferable for use with a common mode feedback circuit 90. Common mode feedback circuit 90 ensures that the common mode voltage at the amplifier input terminals is equal to a reference common mode voltage Vco . More specifically, the common mode feedback circuit 90 supplies identical currents which are provided to balance the common mode output current of the transconductors. Amplifier 96 senses the common mode voltage by sensing the difference between the differential amplifier inputs terminals and compares it to the common mode reference voltage and provides a common gate voltage to transistors 98, 99 thereby supplying a common mode current such that the common mode voltage at the amplifier inputs is equal to the common mode reference voltage. The series combination of active resistors 100, 101 adds to provide the effective resistance Rds. I.e. , R^ + R dth = R„.. Also for example, while the gain circuit is shown using differential components, it is well known that these components may also be configured as single ended components.

Claims: CLAIMS What is claimed is: 1. A circuit comprising; s an amplifier, the amplifier including first and second amplifier input terminals and first and second amplifier output terminals, the first and second amplifier input terminals, the first and second amplifier output terminals being coupled to the first o and second amplifier input terminals to provide a virtual ground; a feedback transconductor, the feedback transconductor including first and second feedback transconductor input terminals and first and second s feedback transconductor output terminals, the first and second feedback transconductor input terminals being coupled to the first and second amplifier output terminals and the first and second feedback transconductor output terminals being coupled to the 0 first and second amplifier input terminals, the feedback transconductor input terminals having a high input impedance and the feedback transconductor output terminal having a high output impedance, the feedback transconductor having a feedback transconductance; 5 a resistor circuit having a resistor circuit resistance and including first and second resistor circuit terminals, the first and second resistor circuit terminals being coupled to the first and second amplifier input terminals so as to reduce the loop gain 30 of the circuit. 2. The circuit of claim 1 wherein; the resistor circuit resistance has a value at or below the inverse of the feedback transconductance 35 thereby reducing the loop gain so as to control the stability of the circuit. 3. The circuit of claim 1 wherein; the resistor circuit includes a passive resistor. 4. The circuit of claim 1 wherein; > the resistor circuit includes a first transistor having first and second current handling terminals coupled to the first and second input terminals of the amplifier, the first transistor being biased to operate in a linear region. 0 5. The circuit of claim 4 wherein; the first transistor is a PMOS transistor. 6. The circuit of claim 4 wherein; s the first transistor is an NMOS transistor. 7. The circuit of claim 4 wherein; the resistor circuit further includes a second transistor coupled to the virtual ground of the 0 amplifier, the second transistor being biased to operate in a linear region; the first transistor being a PMOS transistor and the second transistor being an NMOS transistor. 5 8. The circuit of claim 4 wherein; the active resistor includes a bias circuit, the bias circuit generating a bias current, the bias current being related to a resistance value. 0 9. The circuit of claim 8 wherein; the bias circuit includes a bias resistor, the bias resistor providing a bias resistor resistance, the bias current being dependent upon the square of the bias resistor resistance. 5 10. The circuit of claim 9 wherein; the bias circuit includes a second transistor having first and second current handling terminals and a control terminal, the second transistor first current handling terminal being biased with the bias current, the second transistor generating a bias voltage, the bias voltage biasing the first transistor. 11. The gain circuit of claim 10 wherein; the bias voltage is dependent linearly upon the absolute value of the bias resistor resistance and upon the bias transistor geometry and the first transistor geometry. 12. An active termination resistor circuit s comprising; first and second active termination resistor circuit terminals; an active termination resistor coupled between the first and second active termination resistor circuit o terminals, the active termination resistor providing a resistance based upon a bias voltage; and a termination resistor bias generator coupled to the active termination resistor, the termination resistor bias generator including a bias resistor 5 having a bias resistance, the termination resistor bias generator providing the bias voltage based upon the bias resistance of the bias resistor. 13. The active termination resistor circuit of 0 claim 12 wherein; the active termination resistor includes a transistor having a first current handling terminal coupled to the first active termination resistor circuit terminal, a second current handling terminal 5 coupled to the second active termination resistor circuit terminal and a control terminal coupled to the bias voltage. 14. The active termination resistor circuit of claim 12 wherein; the active termination resistor includes; a first transistor having a first transistor first current handling terminal coupled to the first active termination resistor circuit terminal, a first transistor second current handling terminal coupled to the second active termination resistor circuit terminal and a first transistor control terminal coupled to the bias voltage; a second transistor having a second s transistor first current handling terminal coupled to the first active termination resistor circuit terminal, a second transistor second current handling terminal coupled to the second active termination resistor circuit terminal and a second transistor control 0 terminal coupled to the bias voltage. 15. The active termination resistor circuit of claim 12 wherein; the active termination resistor includes; 5 a first transistor pair including a first transistor pair first transistor and a first transistor pair second transistor; the first transistor pair first transistor including a first transistor pair first transistor o first current handling terminal, a first transistor pair first transistor second current handling terminal and a first transistor pair first transistor control terminal, the first transistor pair first transistor first current handling terminal being coupled to the 5 first active termination resistor circuit terminal and the first transistor pair first transistor control terminal being coupled to the bias voltage; the first transistor pair second transistor including a first transistor pair second transistor first current handling terminal, a first transistor pair second transistor second current handling terminal and a first transistor pair second transistor control terminal, the first transistor pair second transistor first current handling terminal being coupled to the first active termination resistor circuit terminal and the first transistor pair second transistor control terminal being coupled to the bias voltage; and a second transistor pair including a second transistor pair first transistor and a second transistor pair second transistor; the second transistor pair first transistor including a second transistor pair first transistor first current handling terminal, a second transistor pair first transistor second current handling terminal and a second transistor pair first transistor control terminal, the second transistor pair first transistor first current handling terminal being coupled to the first transistor pair second current handling terminal, the second transistor pair first transistor second current handling terminal being coupled to the second active termination resistor circuit terminal and the second transistor pair first transistor control terminal being coupled to the bias voltage; the second transistor pair second transistor including second transistor pair second transistor first current handling terminal, a second transistor pair second transistor second current handling terminal and a second transistor pair second transistor control terminal, the second transistor first current handling terminal being coupled to the first transistor pair second transistor second current handling terminal, the second transistor pair second transistor second current handling terminal being coupled to the second active termination resistor circuit terminal and the second transistor pair second transistor control terminal coupled to the bias voltage. 16. The active termination resistor circuit of claim 12 wherein; the termination resistor bias generator includes; a current bias generator, the current bias generator including the bias resistor and providing a bias current; a bias circuit coupled to the current bias generator, the bias circuit providing the bias voltage; and; a bias circuit amplifier coupled to the bias circuit, the bias circuit amplifier providing a reference voltage to the bias circuit. 17. The active termination resistor circuit of claim 16 wherein; the current bias generator includes; a first current mirror coupled to a supply voltage, and; a second current mirror coupled to the first current mirror as well as to the bias resistor. 18. The active termination resistor circuit of claim 16 wherein; the bias circuit includes a first bias circuit transistor pair and a second bias circuit transistor pair, the first bias circuit transistor pair including a first bias circuit transistor pair input terminal, a first bias circuit transistor pair output terminal, a first transistor pair voltage output terminal and a first transistor pair control terminal, the first bias circuit transistor pair input terminal being coupled to the supply voltage, the first bias circuit transistor pair control terminal being coupled to the first current mirror, the first bias circuit transistor pair output terminal being coupled to the bias amplifier, and the first transistor pair voltage output terminal being coupled to the active resistor; the second bias circuit transistor pair including a second bias circuit transistor pair input terminal, a second bias circuit transistor pair output terminal, a second transistor pair voltage output terminal and a second transistor pair control terminal, the second bias circuit transistor pair input terminal being s coupled to the first transistor pair output terminal and the bias amplifier, the second bias circuit transistor pair control terminal being coupled to the second current mirror, the second bias circuit transistor pair output terminal being coupled ground, o and the second transistor pair voltage output terminal being coupled to the active resistor. 19. The active termination circuit of claim 12 wherein; 5 the active termination circuit is used within a circuit which includes an amplifier and a feedback transconductor, the amplifier providing an amplifier output to the feedback transconductor and the feedback transconductor providing a feedback signal to the input o of the amplifier, the active termination circuit being coupled at the input to the amplifier, the feedback transconductor having a feedback transconductance; and the active termination resistor resistance has a value at or below the inverse of the feedback 5 transconductance thereby reducing the loop gain so as to control the stability of the circuit.

Inventors: GORECKI JAMES L, GORECKI, JAMES, L.
Applicants: LATTICE SEMICONDUCTOR CORP, LATTICE SEMICONDUCTOR CORPORATION
Application year: 1996
Main classification: H03F1
IPC codes: G05F3, H03F1, H03F3, H03H11