Non-volatile memory device having optimized management of data transmission lines

Abstract: A non-volatile memory device (1) having optimized management of data transmission lines, having the particularity that it comprises at least one bidirectional internal bus (3) that runs from one end of the memory device to the other, one or more source structures (5', 5'') that lie externally and internally to the memory device (1), and timer means (8); the timer means (8) are adapted to time-control the independent and exclusive access of the external and internal source structures (5', 5''), within a same memory cycle, to the internal bus (3) for the transmission of data, controls, and functions, from one end of the memory (1) to the other over the internal bus (3).

Description: The present invention relates to a non-volatile memory device having optimized management of data transmission lines. As the complexity and size of non-volatile memories gradually increase, it is increasingly important to be able to rationalize the data exchange lines of the system. This requirement is due to the need to sort the streams of data, controls, and functions, to facilitate better inspectability of the memory, to implement analysis possibilities in order to improve reliability and finally to reduce the space occupation of the memory device. Transmission of the data acquired from the memory matrix for reading and sending to the output terminals occurs by means of dedicated lines; likewise, transmitting data that indicate the state of the memory, events in progress, and test data requires auxiliary lines that run from one end to the other of the memory device, depending on the placement of the external and internal sources from which data and information must be acquired. In this manner, in view of the ever-growing demand for information regarding the operation of the memory, which must thus be sent out, several additional lines are required; these lines are provided in addition to the data transmission lines of the memory, increasing the area that is physically occupied by the memory device and complicating its management. US-A-5 276 650 discloses a memory device having at least one bidirectional internal bus (94), one or more source structures (70,72), and timer means (120,122) adapted to time-control the access of said source structures to said internal bus. The aim of the present invention is therefore to provide a non-volatile memory device whose architecture allows to reduce the number of connecting lines for data transfer. Within the scope of this aim, an object of the present invention is to provide a non-volatile memory device that allows to perform bidirectional data transfer from the memory to the outside world and vice versa. Another object of the present invention is to provide a non-volatile memory device whose architecture allows to improve its number of external structures or points that can be directly inspected from outside in order to improve its monitoring. Another object of the present invention is to provide a non-volatile memory device that allows to standardize and synchronize the data streams. Another object of the present invention is to provide a non-volatile memory device whose architecture facilitate fault searching and analysis activities and expands their potential. Another object of the present invention is to provide a non-volatile memory device whose architecture allows to improve its performance as a consequence of a reduction in the loads caused by connecting lines. Another object of the present invention is to provide a non-volatile memory device that is highly reliable and relatively easy to manufacture at competitive costs. This aim, these objects, and others which will become apparent hereinafter are achieved by a non-volatile memory device having optimized management of data transmission lines, wherein it comprises at least one bidirectional internal bus that runs from one end of the memory device to the other, one or more source structures that lie externally and internally to said memory device, and timer means, said timer means being adapted to time-control the independent and exclusive access of said external and internal source structures, within a same memory cycle, to said internal bus for the transmission of data, controls, and functions, from one end of the memory to the other over said internal bus. This aim and the above mentioned objects are also achieved by a method for transmitting signals in a memory device provided with at least one bidirectional internal bus, with one or more external and internal sources that are adapted to access said internal bus, and with timer means, wherein it comprises the steps that consist in: detecting an address change signal of said memory; allowing the mutually exclusive access of each one of said external and internal source structures to said bidirectional internal bus during a step of the normal memory reading cycle in which the data of the memory are not yet preset for reading, said external and internal source structures transmitting data on said internal bus; and disabling the access of said external and internal source structures to said data bus to enable the reading of data of said memory within the same reading cycle of said memory. The characteristics and advantages of the invention will become apparent from the description of a preferred but not exclusive embodiment of the device according to the invention, illustrated only by way of non-limitative example in the accompanying drawings, wherein: figure 1 is a general block diagram of the architecture of the memory device according to the invention; figure 2 is a more detailed block diagram of the architecture of the memory device shown in figure 1; figure 3 is an even more detailed block diagram of the architecture of the memory device shown in figure 1; figure 4 is a diagram of the timings of the various signals that are present in the memory device according to the invention; figure 5 is a circuit diagram of a detail of the architecture of the memory device according to the invention, shown in figures 1 to 3 and in greater detail in figure 3; figure 6 is a circuit diagram of a detail of the architecture of the memory device according to the invention, shown in figures 1 to 3 and in greater detail in figure 3; figure 7 is a circuit diagram of a detail of the architecture of the memory device according to the invention, shown in figures 1 to 3 and in greater detail in figure 3; figure 8 is a circuit diagram of a detail of the architecture of the memory device according to the invention, shown in figures 1 to 3 and in greater detail in figure 3; figure 9 is a circuit diagram of a detail of the architecture of the memory device according to the invention, shown in figures 1 to 3 and in greater detail in figure 3; figure 10 is a circuit diagram of a detail of the architecture of the memory device according to the invention, shown in figures 1 to 3 and in greater detail in figure 3; figure 11 is a circuit diagram of a detail of the architecture of the memory device according to the invention, shown in figures 1 to 3 and in greater detail in figure 3; and figure 12 is a circuit diagram of a detail of the architecture of the memory device according to the invention, shown in figures 1 to 3 and in greater detail in figure 3. With reference to figure 1, the memory device according to the invention comprises a memory matrix 1, with which an internal bus 3, hereinafter termed data bus, is associated. The data bus 3 branches off, proximate to the memory matrix, into a bus that is designated by MAT-bus in the figure and connects the memory matrix to the sense amplifiers, generally designated by the reference numeral 2 in the figure. The data bus 3 allows connection between one end of the memory device and the other, i.e., between input/output (I/O) management means 4 and local signal sources 5. In figure 1, a single local source 5 is shown generically. The data bus 3 has characteristics that allow bidirectionality of data transmission between the input/output management means and the memory matrix 1. The local sources are interfaced with the data bus 3 by means of a local bus 6. A plurality of structures described hereinafter is interfaced with the data bus. Thus, the sense amplifiers 2, for transferring the data from the matrix 1 to the bus 3, communicate with the data bus by closing a switch designated by HZ in figure 1. Programming means 7, adapted to program the non-volatile memory matrix 1, are enabled/disabled by opening/closing a switch, designated in the figure by PG, for connection between the data bus 3 and the memory matrix 1 across the programming means 7. Furthermore, a connecting path between the data bus 3 and the memory matrix 1, used to perform direct memory access (DMA) tests, is provided by closing a switch designated by DMA. Finally, the connection between the local sources 5, with the corresponding local bus 6, and the data bus 3 is provided by closing a switch designated by LOC. Figure 2 is a more detailed view of the architecture of the memory device shown in figure 1. In particular, the figure shows timer means 8, which receive in input the ATD signal (Address Transition Detection) for detecting an address change in the memory, and a bus, referenced by CNT, that carries device control signals. The timer means are adapted to generate the signals that drive the switches HZ, PG, and LOC described above; these signals are referenced with the same designations, HZ, PG, and LOC, for the sake of convenience in description. The programming means generally designated by the reference numeral 7 in figure 1 are now split into their various components. The connecting path between the bus 3 and the programming means 7 is constituted by a branching of the bus 3 which, through a NAND logic gate 9, reaches at a switch 10 that enables connection to the matrix bus MAT-bus. In figure 2 (and in figure 3), the reference numeral 7 is replaced by the reference sign 7', which identifies adjustment means for programming. The NAND logic gate receives in input, in addition to the data bus 3 (and therefore signals that arrive from the input/output management means 4), the programming signal PG generated by the timer means 8 and an additional data bus, termed L/R, which transmits information concerning the portion of the memory matrix 1 that is affected by programming. Finally, the NAND gate 9 is connected to the ground. The adjustment means 7 receive in input the matrix bus MAT-bus and a reference signal, and are in turn connected to the ground at one end (by means of a switch 13) and to the matrix bus MAT-bus and, in output, at the other end, by means of a switch 10. In practice, the reference numeral 7 7 of figure 1 comprises the reference signs 7', 9, and 13. The sense amplifiers 2 are connected, as shown in figure 2, between the matrix bus MAT-bus (which is a branching of the data bus) and the data bus 3, for access to said bus, by virtue of the enabling/disabling means generally designated by HZ in figure 1 and shown in this successive figure as a circuit of the tristate type 11. The tristate circuit 11, which is particularly adapted for driving highly capacitive lines, receives in input the matrix bus MAT-bus and the signal HZ for enabling/disabling the read path between the sense amplifiers 2 and the data bus 3. Likewise, the switch shown in figure 1 and designated by LOC is shown in detail in figure 2 as means for enabling/disabling the access of the local source 5 to the data bus 3; said means are provided by means of a circuit 12 of the tristate type, which is particularly adapted to drive highly capacitive lines and receives in input the local bus 6 and the signal LOC for enabling/disabling the path between the local source 5 and the data bus 3. As already explained, the signal LOC is generated by the timer means 8. Figure 3 is a view of the same memory architecture of figures 1 and 2 described above, in the case in which there is a plurality of local sources 5 that require access to the data bus 3. For the sake of simplicity in illustration, only two local sources 5 have been shown. In this case, each local source 5 has access to the local bus 6 (which becomes a bus that is shared by a plurality of sources 5) by virtue of access enabling/disabling means, which are constituted by circuits 14 of the tristate type that interface each local source 5 with the local bus 6 for the transit of the data over the data bus 3, as shown earlier. In figure 3, the timer means 8 thus emit two signals, termed USR and CHK, which are meant for the sequential timing of the access to the bus 3 of the two local sources 5 respectively. In the continuation of the description, in order to distinguish between the two local sources they will be designated by 5' and 5". Therefore, the signal USR for enabling access to the data bus 3 for the local source 5' is fed into the tristate circuit 14' (related to the local source 5'), whereas the signal CHK for enabling access to the data bus 3 for the local source 5" is fed into the tristate circuit 14" (related to the local source 5"), and both signals USR and CHK also constitute inputs for additional enabling/disabling means that are advantageously constituted by a tristate circuit, shown in figure 9, whose output constitutes an input for the tristate circuit 12 for access to the data bus 3. The actual number of the tristate circuits 12 is equal to the number of data lines of the data bus 3. Figure 4 is a diagram of the timings of the various signals that are present in the memory device according to the invention. Said signals are now listed to clarify their meaning, postponing the explanation of figure 4 to the explanation of the operation of the memory device. Therefore, the signals are: ADD: memory address signal; ATD: address transition detection signal (the inverted ATD signal, ATDn, is shown in the figures); EQ: equalization signal; SEND: timing signal (the inverted SEND signal, SENDn, is shown in the figures) for sending data of the unit 5' in a "cyclic" manner and for simultaneously blocking the data of the unit 5", again in a cyclic manner; USR: signal for enabling/disabling the path from the local source 5' to the data bus 3; CHK: signal for enabling/disabling the path from the data source 5" to the data bus 3; LOC: signal for enabling/disabling the access of the local sources 5' and 5" to the data bus 3; PG: signal for enabling the programming circuits; DMA: signal for enabling/disabling the path for direct access to the memory matrix 1. These signals, which belong to the memory device, are complemented by signals that are characteristic of the data sources 5' and 5". Said signals can be grouped into special function signals, generally designated by the reference numeral 16; programming control signals, generally designated by the reference numeral 17; user indication signals 18; control indication signals 19; and DMA control signals 20. In particular, the following signals are provided: DC/MC-CODE: device code and manufacturer code signals; LOCAL-IN: signals of local input sources; PG-CNT: programming control signal; USR-CNT: control signal for the source 5', during memory device inspections; CHK-CNT: control signal for the source 5'' at the end of the signal SENDn; DMA: direct memory access signal; DATA-bus: signal for transmission of data on data bus 3; DI: signal for input of data from programming; ROC: redundancy activity signals (Redundancy Out Code); CONF: memory configuration signals; IST: instruction signals. Figures 5 to 12 are circuit diagrams that show in detail the circuits that provide the memory architecture shown in particular in figure 3 and generally in figures 1 and 2. The signals PG-CNT, USRn-CNT and CHK-CNT, passed through appropriate logic gates, shown in the figures that follow, produce the signals PG, LOC, HZ, USR, and CHK, which constitute the outputs of the timer means 8. These signals are stimulated in an exclusive manner. The bus CNT in input to the timer means carries the signals USRn-CNT, CHK-CNT, and PG-CNT. In particular, figure 5 shows a detail of the timer means 8. The reference numeral 8' designates the timer means, which differ from the timer means 8 of the preceding figures merely in that the block designated by the reference numeral 8 in figures 1 and 2 actually also comprises the circuits shown in figures 6, 7, 8, and 9 meant to generate the signals USR (and USRn) and CHK (and CHKn). Therefore, in practice, the timer means 8 are generally shown in figures 5 to 9, considered as a whole. In detail, figure 5 is a view of the circuit for generating the signals SENDn, EQ, and HZ. The signal HZ-CNT, together with the signal ATDn, is emitted by the timer means 8'. The signal ATDn is fed to the base of a first P-type transistor 21, whose drain terminal is connected to the supply voltage and whose source terminal is connected to the output terminal of a pass transistor 22, which is constituted by a P-type transistor and by an N-type transistor, whose input terminal receives the signal HZ-CNT. The signal ATDn is also sent in input to a first inverter 23, whose inverted output (ATD) is sent to the gate terminal of the P-type transistor of the pass transistor 22 and to the gate terminal of the N-type transistor of the pass transistor 22. The signal in output from the pass transistor 22 (i.e., HZ-CNT) is sent to a NOR logic gate 24 that has two inputs. The second input of the NOR gate 24 is constituted by the signal EQ (equalization, i.e., capture of the data item from the memory matrix 1 for reading) in output from delay means 25 that receive in input the signal SENDn. The delay means 25 are required to prevent simultaneous access to the data bus 3 by the local sources 5 i and by the sense amplifiers 2. The signal in output from the NOR logic gate 24 is inverted in a second inverter 26 to obtain the signal HZ. The output of the inverter 26 is connected to the ground by means of a capacitor 27. Figure 6 shows the generation of the signals USRn and USR starting from the SENDn and USRn-CNT signals emitted by the timer means 8'. In detail, the signals SENDn and USRn-CNT arriving from the timer means 8' are sent in input to a NAND logic gate 28, whose output is sent to an inverter 29 to obtain the signal USRn and to two cascade-connected inverters 30 and 31 to obtain the signal USR. The signal SENDn is cyclic and allows to send the data over the internal bus 3 during the inactive period of said bus. Figure 7 is instead a detail view of the generation of signals CHK and CHKn starting from the signals SENDn and CHK-CNT that arrive from the timer means 8'. In detail, the signals SENDn and CHK-CNT are sent in input to a NAND logic gate 32, whose output is constituted by the signals CHK and CHKn (after appropriate inverting through an inverter 33). Figure 8 shows the generation of the programming signal PG starting from the signals SENDn and PG-CNT, which again originate from the timer means 8'. In detail, the signals SENDn and PG-CNT constitute the inputs of a NAND logic gate 34 whose output, appropriately inverted by means of an inverter 35, is the signal PG. Figure 9 is a view of the generation of the signals LOCn and LOC starting from the signals USRn and CHK, generated respectively by the circuit of figure 6 and by the circuit of figure 7. The signals USRn and CHK constitute the inputs of a NAND logic gate 36, whose output, appropriately inverted by means of an inverter 37, is the signal LOCn and, inverted twice by means of the cascade-connected inverters 38 and 39, is the signal LOC. The circuits shown in figures 6 to 9 are therefore circuits for driving the circuits shown in the following figures, whose inputs are the signals generated by said circuits of figures 6 to 9. Figure 10 shows the tristates 14' and 14" that enable access to the further tristate 12 to finally gain access to the data bus 3. In detail, the tristates 14' and 14" have a similar structure, and the elements that compose the respective tristate circuits are therefore described and designated herein by the reference numerals only once to avoid redundancy in the description. With reference to the tristate circuit 14', the signal UF-IN shown in figure 10 in input to the gate terminals of P-type and N-type transistors, respectively 40 and 41, is a signal that originates from the local source 5' and is designated by the reference numeral 18 in figures 3 and 4. Likewise, with reference to the tristate circuit 14", the signal CF-IN shown in figure 10 in input to the gate terminals of transistors that are similar to the P-type and N-type transistors 40 and 41 is a signal that originates from the local source 5", and in figures 3 and 4 said signal is designated by the reference numeral 19. The signal CF-IN, before being fed into the gate terminals of said transistors, is first inverted by an inverter. The drain terminals of the transistor 40 and the source terminals of the transistor 41 are respectively connected to the supply voltage and to the ground. The tristate structure 14' (and therefore, likewise, the structure 14") also comprises two further transistors 42 and 43, respectively of the P type and of the N type. The drain terminal of the transistor 42 is connected to the source terminal of the transistor 40, and its source terminal is connected to the drain terminal of the transistor 43. The signals USR and USRn that originate from the circuits shown in figure 6 are fed to the gate terminals of the transistors 41 and 42 respectively. Likewise, the signals CHKn and CHK generated by the circuit shown in figure 7 are fed respectively to the gate terminals of the transistors of the tristate structure 14" that correspond to the transistors 41 and 42. The output signal of the two tristate structures 14' and 14", termed LOCAL, is fed to the tristate structure 12 for access to the data bus 3. In detail, the tristate structure 12 comprises two transistors 44 and 45, respectively of the P type and of the N type, whose gate terminals receive the LOCAL signal in input. The drain terminal of the transistor 44 is connected to the supply voltage, the source terminal of said transistor is connected to a pass transistor 46 formed by a P-type transistor and by an N-type transistor and to the gate terminal of a P-type transistor 47, whose drain terminal is connected to the supply voltage, whereas the source terminal is connected to the drain terminal of a transistor 48. The source terminal of the transistor 58 is connected to the ground and its gate terminal is connected to the drain terminal of the transistor 45. The drain terminal of the transistor 45 is also connected to the pass transistor 46. Signals LOC and LOCn, generated by the circuit shown in figure 9, are fed respectively to the gate terminals of transistors 49, of the P type, and 50, of the N type, whose drain terminals are respectively connected to the supply voltage and to the gate terminal of the transistor 48. The source terminal of the transistor 49 is connected to the gate terminal of the transistor 47, whereas the source terminal of the transistor 50 is connected to the ground. The signals LOC and LOCn are also fed to the gate terminals, respectively, of the N-type and P-type transistors that constitute the pass transistor 46. The signal in output from the tristate structure 12 is the signal for access to the data bus 3 on the part of the local sources 5 i (where i=1...n; in the case of figure 3, n=2) and is referenced as DATA-bus<x>. Figure 11 is a circuit diagram of the tristate structure 11 for access to the data bus 3 on the part of the sense amplifier 2. The number of tristate circuits shown in figure 11 is equal to the number of the sense amplifiers 2 of the memory matrix 1. The signal in input to the sense amplifier 2 (actually, as mentioned, a plurality of sense amplifiers) is a bus referenced by SA-OUT, i.e, the set of the output signals of the sense amplifiers 2. In practice, the output signal of each sense amplifier 2 is fed into the corresponding tristate circuit 11. The figures, for the sake of simplicity, show a single sense amplifier 11 instead of the plurality of said amplifiers and a bus SA-OUT for the plurality of signals in output from the sense amplifiers. In detail, as shown in the upper portion of figure 11, two signals are fed in input to each tristate circuit 11: the signal HZ generated by the circuit of figure 5, and the signal SA-OUT, which is the output of the corresponding sense amplifier. The signal HZ is fed into an inverter 51 to be fed to the gate terminals of a P-type transistor 52 and of an N-type transistor 53. The drain terminal of the transistor 52 is connected to the supply voltage, whereas its source terminal is connected to the gate terminal of a P-type transistor 54 and to a pass transistor 55. The source terminal of the transistor 53 is connected to the ground, whereas its drain terminal is connected to the gate terminal of an N-type transistor 56 and to a pass transistor 57. The drain terminal of the transistor 54 is connected to the supply voltage, whereas its source terminal is connected to the drain terminal of the transistor 56. The source terminal of the transistor 56 is connected to the ground. The signal SA-OUT is fed to the pass transistors 55 and 56, as shown in figure 11. Figure 12 shows the circuital execution of the switches 10 and 13, of the NAND logic gate 9, and of the DMA, shown in figures 2 and 3. In particular, the programming means 7 receive in input a reference voltage signal V ref , the signal DMA, and the bus MAT-bus<x>. The NAND logic gate 9 is implemented by means of four transistors 58, 59, 60, and 61, in which the transistor 58 is of the P type, whereas the other ones are of the N type. The transistors, connected as shown in the figure, receive in input the signal PG (which is fed to the gate terminals of the transistors 58 and 59), the signal L/R (which is fed to the gate terminal of the transistor 60), and the signal DATA-bus<x> (which is fed to the gate terminal of the transistor 61). DMA enabling is provided by means of a transistor 62 of the N type, whose gate terminal receives the signal DMA. The switch 13 is provided by a P-type transistor 63 that is connected as shown in the figure, whereas the switch 10 is implemented by two P-type transistors 64 and 65 that are connected as shown in the figure. With reference to the above figures, the operation of the memory device according to the invention is as follows. The architecture of the device according to the invention allows to provide a data transmission protocol, by virtue of the timer means 8, which in sync with each reading and programming cycle allows multiple use of the data bus 3 in a same reading cycle. During a first step of the reading cycle, when the data bus is not in use due to the unavailability of the data for reading, said data bus 3 is used to transmit redundancy signals ROC (Redundancy Output Code) or MC signals (device manufacturer code) and DC (Device Code) signals or signals related to contingent configurations or to instructions (CONF and IST). Therefore, all the lines that are required to supply data during the first step are grouped and organized to communicate with the internal bus 3 through the structures 5', which achieve their data transmission functions in a cyclic manner. The same units can also be monitored during the rest of the cycle as well, by acting on the control signal USRn-CNT=0. The interval dedicated to this first step is paced by the timing signal SEND, which is correlated to each pulse of the signal ATD (the respective inverted signals SENDn and ATDn are shown in figure 4) and is independent of any subsequent activity. In the second step, the data bus 3 constitutes the normal data transmission channel for the ordinary activities of the memory device (reading the data and programming the memory). Every time a data item that originates from a source that is external to the memory matrix 1 is requested, the timer means 8, more clearly defined in figures 5-8, which are constituted by a self-activation logic structure, allow to enable the path for connecting the external source to the data bus 3, in the case of the local sources 5 i after the transit of the data on the local bus 6. The signals that control the data stream over the data bus 3 are, as shown, exclusive and in sync with events that are paced by the timer means 8 and have the purpose of enabling access of the external sources to the data bus 3. In inactive conditions, the data bus 3 is assigned to the sense amplifiers 2 when the signal HZ is low. With reference to figure 4, when the signal EQ (equalization) goes from high to low, and therefore the signal SENDn has first passed from low to high (i.e., the step for sending the signals ROC, CONF, and IST during the inactivity step of the data bus 3 as regards reading the data from the memory matrix 1 has ended), the signal HZ goes from high to low, and during this period the data are read from the memory matrix 1 to the data bus 3. This situation can be observed in figure 11, with the input of the signals HZ and SA-OUT (output of the sense amplifiers 2) in the tristate circuit 11 that enables access of the tristate circuits 2 to the data bus 3. In this manner, the connecting path between MAT-BUS and the data bus 3 is completed. This situation occurs whenever HZ is low, simultaneously with the signal EQ, which becomes low. The correlation of the signal HZ with the signals SENDn, EQ, ATDn, and HZ-CNT (control signal) is shown in the circuit of figure 5. During this step, therefore, the signal SENDn is high, the signal PG is low (we are not in the step for programming the memory 1), the signal CHK, the signal LOC and the signal USR are low (the local sources are not communicating with the data bus 3), and therefore the local sources are in a high-impedance condition, i.e., in a condition in which access to the data bus 3 is denied. The states of the signals 16, 17, 18, 19, and 20 during this step can be read on the chart of figure 4. When the signal EQ goes from low to high, the signal HZ becomes high, the signal SENDn becomes low at a burst variation of ATDn, the signal USR becomes high, CHK remains low, LOC becomes high, and PG is always low. During this step, the connecting path between the sense amplifiers 2 and the data bus 3 is blocked. In the interval during which the signal HZ remains high, i.e., during which the data of the memory matrix 1 are not transmitted over the data bus 3, said data bus remains available for all external activities and can therefore be managed by the external sources and by the programming means 7 for programming the memory device. Therefore, in the interval during which USR is high (i.e., when SENDn or USRn-CNT are simultaneously or individually low, see figure 6), the source 5' accesses the data bus 3 after the data have passed along the local bus 6. The enabling of access to the local bus 6 is provided by the signal LOC, which is high in this step (see figure 9). The signal LOC is generated by the logic circuit of figure 9, which receives the signals USRn and CHK in input. Therefore, if either USRn or CHK is low, LOC is high. Whenever a local resource is stimulated, access to the data bus 3 is also allowed. The interval during which LOC is high corresponds to the interval during which the data bus is used by the internal and external sources, which are never stimulated during a programming step, i.e., when the signal PG is high. Therefore, if one considers the interval during which LOC is high and SENDn is low, and observing the groups of signals 16, 17, 18, 19, and 20 in figure 4, it is evident that several situations may occur in this interval. For example, if the signal DC/MC is high, i.e., it is necessary to read in output the signals DC and MC, said signals are sent in the interval during which the data of the memory 1 are not being read. Therefore the signals DC and MC are transmitted over the data bus 3 together with the data ROC, CON, and IST. Instead, in case of a high level of the programming signal PG-CNT that originates from the timer means 8' and from which the signal PG, which is high, originates by means of the circuit of figure 8, the programming step is enabled; during this step, the programming means 7 are under the control of the data bus 3, guided by the I/O means 4, which thus decide the "word" to be programmed in the memory 1. This programming step is represented by the group of signals 17 in figure 4. If instead it is the signal CHK-CNT that goes from low to high and therefore CHK also goes from low to high, again in the interval during which LOC is high, signals are transmitted over the data bus 3 by the local source 5" after passing through the local bus 6. Again, when it is the signal USRn-CNT that switches from high to low, the local source 5' gains access to the data bus 3 after the transit of the data on the local bus 6. In this step, too, the signals DC and MC are sill sent, but they are not requested during reading in output and therefore are not considered. Finally, when it is the DMA signal that goes from low to high, i.e., when direct access to the memory is requested for particular requirements related to checking the content of the individual cells of the memory, the data of the memory are transferred toward the output over the data bus. In this case, the signals USR and CHK are low to avoid overlaps in access to the data bus 3. In figure 4, with reference to the groups of signals 16, 17, 18, 19, and 20, the signal designated by LOCAL-IN indicates the signal that is transmitted over the local bus 6. In practice it has been observed that the memory device according to the invention fully achieves the intended aim, since it provides for an architecture that allows to implement a bidirectional data bus 3 that is used for all the transmission, programming, and testing functions of the memory. When the data of the memory matrix 1 are not yet ready for reading, the normal reading cycle of the memory is used for a series of operations related to the memory, by means of the access to said data bus on the part of a plurality of external and internal sources. The bidirectionality of the data bus 3 allows to communicate, even indirectly, with external sources that can be set to a high-impedance condition, so as to not access the data bus when another structure is in turn accessing the bus. Said external sources are then activated individually, within a same reading cycle of the memory, preventing any kind of data bus access conflict. Accordingly, one obtains a sorting of the data streams and of the controls between the various memory blocks, which is a consequence of the rationalization of the transmission lines of the memory device. Every exchange of data between the outside the memory and the inside or vice versa, memory monitoring, and testing activities are all performed by means of the single data bus 3, achieving the result of eliminating dedicated transmission lines that occupy space and complicate the architecture of the device. The device thus conceived is susceptible of numerous modifications and variations, all of which are within the scope of the inventive concept. Thus, for example, data transfer over the local bus 6 can be bidirectional, as occurs on the data bus 3. Furthermore, a plurality of tristate structures 14 i (where i=1...n) for enabling access of the local sources 5 i to the local bus 6 can communicate with the local bus 6. The above-mentioned architecture can also be adapted to the case in which the memory matrix 1 is divided into blocks and is not a single block as shown in figures 1 to 3. In this case, the signal L/R for selecting the memory block involved in a given event becomes crucially important. Finally, all the details may furthermore be replaced with other technically equivalent elements. In practice, the materials employed, so long as they are compatible with the specific use, as well as the dimensions, may be any according to the requirements and the state of the art. Where technical features mentioned in any claim are followed by reference signs, those reference signs have been included for the sole purpose of increasing the intelligibility of the claims and accordingly such reference signs do not have any limiting effect on the interpretation of each element identified by way of example by such reference signs.

Claims: Non-volatile memory device having optimized management of data transmission lines, wherein it comprises at least one bidirectional internal bus that runs from one end of the memory device to the other, one or more source structures that lie externally and internally to said memory device, and timer means, said timer means being adapted to time-control the independent and exclusive access of said external and internal source structures, within a same memory cycle, to said internal bus for the transmission. of data, controls, and functions, from one end of the memory to the other over said internal bus. Memory device according to claim 1, characterized in that it comprises one or more enabling/disabling means that are adapted to allow/deny the mutually exclusive access of said external and internal source structures to said internal bus, for the transmission of signals over said single bidirectional internal bus, within the same reading cycle of the memory device. Device according to claim 2, characterized in that it comprises at least one local bus that is adapted to interface said external source structures with said internal bus. Device according to claim 3, characterized in that one or more enabling/disabling means comprise enabling/disabling means that are adapted to allow the access of said one or more source structures to said local bus, said access being time-controlled by said timer means, independently and exclusively. Device according to claim 4, characterized in that the number of said means for enabling/disabling access to said local bus is equal to the number of said external source structures. Device according to claim 4, characterized in that it comprises enabling/disabling means that are adapted to interface said local bus with said data bus to enable the transfer of data, controls, and functions to said internal bus. Device according to claim 6, characterized in that said enabling/disabling means interposed between said local bus and said internal bus receive in input a driving signal that originates from said timer means and the signals to be transmitted, which originate from said local bus, said driving signal being adapted to set said means for enabling/disabling access to the internal bus to a low/high impedance condition respectively. Device according to claim 1, characterized in that said timer means receive in input control signals for said memory device, said control signals being time-controlled and synchronized so as to allow the mutually exclusive access of said internal and external source structures to said internal bus during a same memory reading cycle. Device according to claim 3, characterized in that said means for enabling/disabling the access of said external sources to said local bus receive in input a driving signal that is time-controlled by said timer means and the signals that originate from said external source structures. Device according to claim 1, characterized in that it furthermore has additional means for enabling/disabling access to the internal bus by the data of the memory, said additional enabling/disabling means being interposed between sense amplifiers of said memory and said internal bus. Device according to claim 10, characterized in that said additional means for enabling/disabling access to the internal bus on the part of the data of the memory receive in input a signal for disabling/enabling the memory data reading path and the memory data that arrive from the sense amplifiers. Device according to claim 1, characterized in that it comprises programming means that are connected between said internal bus and said memory. Device according to claim 1, characterized in that it comprises input/output means that interact with said internal bus. Device according to claim 2, characterized in that said enabling/disabling means are tristate circuits. Device according to claim 3, characterized in that said local bus is unidirectional. Device according to claim 3, characterized in that said local bus is bidirectional. Device according to claim 12, characterized in that said means for programming said memory comprise logic means, which receive in input a programming signal and data carried by the internal bus, and means for adjusting the programming of said memory, which receive in input said internal bus and a reference signal, the output of said adjustment means being sent to said internal bus in a manner that is time-controlled by said timer means. Device according to claim 17, characterized in that said logic means of said programming means receive in input a signal that indicates the portion of the memory that is to be programmed. Device according to claim 1, characterized in that it comprises means for direct access to the memory that are adapted to directly access said memory by accessing said internal bus. Device according to one or more of the preceding claims, characterized in that it comprises one or more of the described and/or illustrated characteristics. Method for transmitting signals in a memory device provided with at least one bidirectional internal bus, with one or more external and internal source structures that are adapted to access said internal bus, and with timer means, wherein it comprises the steps that consist in: detecting an address change signal of said memory; allowing the mutually exclusive access of each one of said external and internal source structures to said bidirectional internal bus during a step of the normal memory reading cycle in which the data of the memory are not yet preset for reading, said external and internal source structures transmitting data on said internal bus; and disabling the access of said external and internal source structures to said data bus to enable the reading of data of said memory within the same reading cycle of said memory. Method according to claim 21, characterized in that said step that consists in making each one of said sources access said internal bus in a mutually exclusive manner comprises the additional steps that consist in: time-controlling, by virtue of said timer means, the access of each one of said external and internal sources to a local bus; time-controlling, by virtue of said timer means, the access of said local bus to said internal bus. Method according to claim 21, characterized in that it comprises a step for programming said memory during the same normal reading cycle of said memory. Method according to claim 21, characterized in that it comprises, within the same normal reading cycle of said memory, a step for direct access to said memory. Method according to claim 21, characterized in that the transmission of signals that originate from said external and internal source structures occurs over said bidirectional internal bus within a normal cycle for reading said memory.

Inventors: BARCELLA ANTONIO, PASCUCCI LUIGI, BARCELLA, ANTONIO, PASCUCCI, LUIGI
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1996
Main classification: G11C7
IPC codes: G11C7