FEEDBACK AMPLIFIER WITH IMPROVED SPEED AND ACCURACY

Abstract: A feedback amplifier with improved speed and accuracy when the primary feedback around the amplifier configuration has been interrupted is provided. An additional feedback loop (Q2b) added to the input stage (IS) of the amplifier maintains the circuit response by preventing the interruption of the feedback and the saturation of the circuit components.

Description: Feedback amplifier with improved speed and accuracy. The present invention relates to feedback amplifiers. More particularly, it relates to a feedback amplifier having an input stage and an output stage driven by the input stage, the input stage comprising a first transistor having a control electrode for receiving a feedback signal, the output stage comprising an output transistor for driving an output terminal of the feedback amplifier. Such a feedback amplifier can be used, for example, in a peak detector circuit. In a basic peak detector circuit, as the input voltage increases, the feedback configuration of the circuit causes the circuit to go into a voltage follower mode. That is, the output voltage is equal to the input voltage. When the input voltage subsequently decreases, the feedback is interrupted, thereby causing the circuit elements to leave their normal operation mode. When the feedback is then restored, recovery of the circuit can take too long to allow for accurate tracking of the input signals. It is therefore an object of the present invention to provide a feedback amplifier with improved speed and accuracy. According to the invention there is provided a feedback amplifier characterized in that the input stage comprises a second transistor connected in parallel to the first transistor, the second transistor having a control electrode coupled to the output terminal. The second transistor provides an additional feedback loop added to the basic feedback configuration to enable faster and more accurate recovery after the primary feedback around the amplifier configuration has been interrupted. Other objects and features of the present invention will become apparent from the following detailed description considered in connection with the accompanying drawings which disclose an embodiment of the present invention. It should be understood, however, that the drawings are designed for the purpose of illustration only and not as a definition of the limits of the invention. In the drawing, wherein similar reference characters denote similar elements throughout the several views: FIG. 1 is a schematic circuit diagram of a peak detector of the prior art; FIG. 2 is a graphical representation of the transient response of the peak detector circuit of FIG. 1; FIG. 3 is a schematic circuit diagram of a peak detector according to the invention; and FIG. 4 is a graphical representation of the transient response of the peak detector circuit of FIG. 3. FIG. 1 shows a peak detector circuit of the prior art. The peak detector circuit comprises a diode D2, a capacitor C2 and a feedback amplifier. The feedback amplifier comprises an input stage IS followed by at least a second or output stage OS. The input stage IS comprises a PNP differential transistor pair Ql, Q2 having the common emitter node coupled to a positive supply voltage V cc via a current source II. The collectors of the differential pair transistors Ql, Q2 are coupled to ground via the input branch and the output branch of an NPN current mirror Q3, Q4 to form a single ended drive signal from the differential signal of the differential transistor pair Ql , Q2. The output stage OS comprises an NPN transistor Q5, the base of which is coupled to the output branch Q3 of the current mirror Q3, Q4 for receiving the drive signal from the input stage IS. The emitter of transistor Q5 is coupled to ground and its collector is coupled to an output terminal OT of the feedback amplifier. A Miller capacitor Cl between the collector and base of transistor Q5 provides stability to the feedback amplifier. A current source 12 connected between the positive supply voltage V cc and the collector of transistor Q5 provides bias current to J transistor Q5. The diode D2 and the capacitor C2 are series-connected between the output terminal OT and ground. The anode of diode D2 is connected to the output terminal OT. The output voltage V out across capacitor C2 is fed back to the base of transistor Q2. As the input voltage V in increases, the feedback of the voltage V out to the base of transistor Q2 forces the feedback amplifier into a voltage follower mode i.e., the output voltage V out is equal to the input voltage V in received at the base of transistor Ql. The voltage at output terminal OT also follows the output voltage V out , but is a diode voltage higher. If the input voltage V^ decreases, the diode D2 is cut off and the voltage V out on capacitor C2 remains constant and the feedback to the base of Q2 is interrupted, i.e. the voltage at the base of transistor Q5 no longer follows the voltage at the output terminal OT. Diode D2 is biased to only allow current to flow from current source 12 to capacitor C2 and not vice versa. When the input voltage V in decreases, the difference between the input voltage V m and the output voltage V out is negative, thereby forcing the collector voltage V C Q 5 of the output stage transistor Q5 to go negative and causing transistor Q5 to go into saturation. Therefore, when the input voltage V in subsequently increases beyond the voltage stored on capacitor C2, the collector voltage V CQ5 of transistor Q5 is brought back up. As a result of the saturation of transistor Q5, the charge built up on the base of transistor Q5 causes this response to be delayed. One well-known method of preventing saturation is to clamp the collector voltage of transistor Q5 with a Schottky diode Dl between the collector and base of transistor Q5. When the input voltage V in increases beyond the stored output voltage V out , the collector voltage of Q5 starts to rise immediately at a rate set by the current source II and the Miller capacitor Cl. As a result of this slewing effect, there still remains a delay before the output voltage V out follows the input voltage V in . FIG. 2 shows the transient response of the peak detector of FIG. 1. As shown, the peak of the input voltage V in has already passed when the output voltage V out is slewed back up. The implication is that for fast changing signals relative to the slew rate of the peak detector, this delay can cause accuracy errors. In addition, if the circuit consists of more than the two stages shown in FIG. 1, more than one Schottky diode may be needed to prevent saturation of other transistors. This is undesirable due to the increased size of the die that would be required to make the circuit. The circuit of FIG. 3 is similar to that of the prior art circuit of FIG. 1, except that the Schottky diode Dl has been removed and an additional PNP transistor Q2b has been added to the input stage IS to form an additional feedback loop from the output stage OS to the input stage IS. Transistor Q2b has its emitter and collector coupled to the emitter and collector of transistor Q2a, respectively, while the base of transistor Q2b is connected to the collector of transistor Q5. As described earlier, if the input voltage V in decreases below the value that is stored on output capacitor C2, the feedback is interrupted and diode D2 becomes reverse biased. As a result of the voltage decrease, the collector voltage V C Q 5 of transistor Q5 decreases, but now only to one diode voltage below the output voltage V out . At this point, and before any further decrease in the collector voltage V cQ5 of transistor Q5, the feedback is restored through the additional input transistor Q2b. As a result of this operation, the remaining circuit elements to the left of diode D2 remain properly biased and do not go into saturation. When the input voltage V in is subsequently increased beyond the voltage stored on capacitor C2, the circuit restores the feedback through input transistor Q2a. Therefore, the collector voltage V C Q 5 of Q5 now only has to slew over one diode voltage, and the response of the circuit is much faster. FIG. 4 shows the transient response of the circuit of FIG. 3 according to the invention. Since the feedback response is much faster, the output V out can now accurately track the input voltage V in . Under these circumstances, the collector voltage V CQ5 of transistor Q5 is not forced negative, and the response time is significantly increased. Although the additional feedback loop of the circuit shown in FIG. 3 consists of bipolar pnp transistors, the same approach can also be applied to circuits consisting of MOS transistors. In that case collector, emitter and base should be replaced by drain, source and gate. In addition, both p-type and n-type devices can be used in the primary and additional feedback loop. While one embodiment of the present invention has been shown and described, it is to be understood that many changes and modifications may be made thereinto without departing from the spirit and scope of the invention as defined in the appended claims. Instead of diode D2 and capacitor C2 other loads causing an interruption or an other disturbance in the primary feedback loop as described above can be used.

Claims: CLAIMS: 1. A feedback amplifier having an input stage (IS) and an output stage (OS) driven by the input stage (IS), the input stage (IS) comprising a first transistor (Q2a) having a con¬ trol electrode for receiving a feedback signal, the output stage (OS) comprising an output transistor (Q5) for driving an output terminal (OT) of the feedback amplifier, characterized in that the input stage (IS) comprises a second transistor (Q2b) connected in parallel to the first transistor (Q2a), the second transistor (Q2b) having a control electrode coupled to the output terminal (OT). 2. A feedback amplifier as claimed in claim 1 , wherein the input stage (IS) further comprises a third transistor (Ql) coupled to the first transistor (Q2a) to form a differential pair and means (Q3, Q4) for generating a drive signal for the output stage (OS) in response to a differential output signal of the differential pair (Ql , Q2a). 3. A feedback amplifier as claimed in claim 1 or 2, wherein the feedback amplifier further comprises a diode (D2) and a capacitor (C2), the diode (D2) being coupled between the output terminal (OT) and the capacitor (C2) to charge the capacitor (C2) for forming the feedback signal. 4. A feedback amplifier as claimed in claim 1 , 2 or 3, wherein the feedback amplifier comprises bipolar transistors. 5. A feedback amplifier as claimed in claim 1, 2 or 3, wherein the feedback amplifier comprises MOS transistors. 6. A feedback amplifier as claimed in claim 4, wherein the emitter and collector of the second transistor (Q2b) are connected to the emitter and collector, respectively, of the first transistor (Q2a), and the base of the second transistor (Q2b) is coupled to the collector of the output transistor (Q5).

Inventors: FONDERIE MAARTEN J, TOY EDMOND, FONDERIE, MAARTEN, J., TOY, EDMOND
Applicants: PHILIPS ELECTRONICS NV, PHILIPS NORDEN AB, PHILIPS ELECTRONICS N.V.
Application year: 1996
Main classification: H03F1
IPC codes: H03F1, H03F3