Programming and reading management architecture for memory devices, particularly for test purposes

Abstract: Programming and reading management architecture, particularly for test purposes, for memory devices of the non-volatile type, which has the particularity that it comprises: at least two memory half-matrices; a bidirectional internal bus (1) for the transmission of data to and from the memory half-matrices; a programming unit (30) for each one of the at least two memory half-matrices; and a data sensing unit (20). The programming units (30) are adapted to program the at least two memory half-matrices and the data sensing unit (20) and the programming units (20) communicate with the bidirectional internal bus (1) to reroute onto the bus (1) reading data and programming data of the at least two memory half-matrices.

Description: The present invention relates to a programming and reading management architecture, particularly for test purposes, for memory devices of the non-volatile type. In non-volatile memories it is particularly important to provide an architecture that allows to program the memory quickly and with preset programming voltages. In conventional architecture, the programming voltage of the various memory cells is never uniform due to the drops in voltage along the lines. The case thus occurs in which the memory cells that are closer to the programming means are programmed with an optimum voltage, whereas as one moves further away from the point where the programming voltage is generated, said voltage decreases due to the above mentioned voltage drops of the lines. Therefore, the more distant memory cells are programmed with decreasing voltage values that can differ even considerably from those of the first memory cells. In order to contain the non-uniformity of the programming voltage levels, it is necessary to program a small number of bits at a time, so that the voltage value differences are negligible. This approach is valid when byte programming is performed. It is not equally valid when, during testing, parallel programming is performed to reduce its time requirements. Abandoning or containing parallelism leads to the drawback of increasing the programming times to the detriment of the low cost of the finished memory device. It is in fact evident that the programming of large memory matrices is hindered by the difficulty in achieving uniform programming voltages except for a small number of memory cells at a time. This drawback will become increasingly important as memory construction technology improves, leading to ever larger sizes of said memories. These larger sizes are achieved by reducing the thicknesses and the size of the lines (this entails higher resistivity). Furthermore, in the case of the programming of multiple bits in parallel, using a redundancy system for output lines, if there are two defective cells in two different bit lines it is not possible to resort to the redundancy lines provided for replacement of the defective lines, since it is not possible to apply redundancy to two different lines simultaneously. This entails the important drawback of having to reject, during testing, a memory device that has this situation, or of having to take a much longer time by using only byte programming. As regards the direct memory access function, this function is usually provided by virtue of additional lines that allow to directly access the memory for inspection purposes. Said additional lines add to the normal lines provided for programming and reading the data, entailing the drawback of increasing the space occupation of the memory device and of reducing its reliability. US-A-5 022 009 discloses a programming and reading management architecture for memory devices of the non- volatile type, as defined in the preamble of claim 1. The aim of the present invention is therefore to provide an architecture that allows to advantageously manage programming, reading, and the various test activities, particularly for memory devices of the non-volatile type. Within the scope of this aim, an object of the present invention is to provide a programming management architecture for memory devices that allows to perform programming of the memory matrix with programming voltage control, so as to perform uniform programming for the various memory cells of the matrix. Another object of the present invention is to provide a programming management architecture for memory devices, particularly of the non-volatile type, that allows to make memory cell programming independent of the voltage drops along the programming line. Another object of the present invention is to provide an architecture for the programming and reading management, for test purposes, of memory devices that allows to acquire a reference signal for programming in a point that is free from voltage drops of any kind. Another object of the present invention is to provide a programming management architecture for memory devices, particularly of the non-volatile type, that allows to perform parallel programming and to maintain the possibility of redundancy of any defective lines. Another object of the present invention is to provide an architecture for the programming and reading management of memory devices, particularly of the non-volatile type, for test purposes that allows to perform direct memory accesses without requiring additional paths besides the normal reading paths. Another object of the present invention is to provide an architecture for the programming and reading management of memory devices, particularly of the non-volatile type, for test purposes that provides for symmetry and reversibility of the reading paths, so as to facilitate path balancing. Another object of the present invention is to provide an architecture for the programming and reading management of memory devices, particularly of the non-volatile type, for test purposes that allows to minimize the size of the memory device. Another object of the present invention is to provide an architecture for the programming and reading management of memory devices for test purposes that allows to preserve substantial independence of the data lines, so as to allow further uses thereof even in a time-shared mode. Another object of the present invention is to provide an architecture that is highly reliable and relatively easy to produce and at competitive costs. This aim, and these objects, are achieved by a programming and reading management architecture, particularly for test purposes, for memory devices of the non-volatile type, as defined in claim 1. The characteristics and advantages of the invention will become apparent from the description of a preferred but not exclusive embodiment of the architecture according to the invention, illustrated only by way of non-limitative example in the accompanying drawings, wherein: figure 1 is a block diagram of the programming and reading management architecture according to the invention; figure 2 is a more detailed block diagram of a portion of the architecture according to the invention, shown in figure 1; figure 3 is a view of a circuital detail of figure 2; figure 4 is a detailed circuit diagram of figure 3; figure 5 is a view of a circuital detail of figure 2; figure 6 is a detail view of the circuital detail shown in figure 5; and figure 7 is a view of a circuit for generating signals applied to the circuit of figure 6. With reference to the above figures, the architecture according to the invention entails a splitting of the memory matrix into at least two half-matrices (not shown), a left one and a right one; the two half-matrices are arranged so as to face each other. An internal bus, divided into a high bus 1 H and into a low bus 1 L , is provided for the bidirectional transmission of data and auxiliary information between the memory and the outside. In figure 1, the reference numeral 2 designates a programming terminal (which actually represents a number of programming terminals that is equal to the number of word bits of the memory matrix); the reference numeral 3 designates means for dividing the programming voltage, which receive in input both the programming voltage V PP and the programming enabling signal PG. The voltage dividing means 3 produce a reference voltage VPD-rif. With reference to the case of splitting into two memory half-matrices, the architecture according to the invention provides for data sensing means and duplicated programming and direct access (DMA) means. Figure 1 relates more particularly to the case in which each memory half-matrix is divided into a plurality of half-matrix subsections because a hierarchical decoding structure is used; particularly, it relates to the case in which each half-matrix is divided into four half-matrix subsections. The word size assumed for this exemplifying memory configuration is 16 bits. Therefore, for each half-matrix subsection there are data sensing means, advantageously constituted by a sense amplifier 4, and duplicated programming means 5 R and 5 L . The sense amplifier is conveniently of the reversible symmetrical type and it is therefore possible to swap the matrix branch with the reference branch if the left or right memory half-matrix is being read. Figure 2 is a detail view of the structures that are provided for each pair of opposite half-matrix subsections, i.e., one that belongs to the left half-matrix and one that belongs to the right half-matrix. In particular, figure 2 shows that for each half-matrix subsection there are data sensing means and duplicated programming means 5 R and 5 L . The programming means are provided in four pairs for every two opposite half-matrix subsections, since each pair is meant, respectively, for one bit of the left half-matrix subsection and for one bit of the right half-matrix subsection. Therefore, in summary, for a memory matrix with a 16-bit word length, divided into two half-matrices that are in turn divided into four half-matrix subsections each, there are sixteen sense amplifiers 4 and thirty-two programming means 5 (sixteen for the left half-matrix and sixteen for the right half-matrix). An additional sense amplifier is provided, for each half-matrix, for the redundancy lines. In figure 1, the reference numeral 10 generally designates the set of four sense amplifiers 4 and of eight programming means 5. The structures 10 are connected, by means of the lines YMS-L and YMS-R, respectively to the left half-matrix and to the right half-matrix. The connections 11 represent the bidirectional connections to the internal bus 1 L and 1 H . Each structure 10 receives in input the reference programming voltage signal VPD-rif and a bus that carries control signals CNT-bus. With reference again to figure 2, only the left portion of said figure, which comprises the sense amplifier 4 and the programming means 5 R and 5 L , is described since the right portion is exactly identical. The reference numeral 20 generally designates a data sensing unit and the reference numeral 30 generally designates a programming unit. The sense amplifier 4 receives in input the signals that arrive from the lines YMS-R and YMS-L, which carry the data of the right half-matrix and of the left half-matrix respectively. The lines YMS-R and YMS-L are bidirectional, since data exchange can occur from the memory matrix to the outside or, vice versa, the data can originate from outside and reach the memory matrix. The portions of said lines that reach the sense amplifier 4 are unidirectional toward the amplifier 4. The outputs of the sense amplifiers 4 are the signals SA-R and SA-L, depending on whether the control signal RD-L/R indicates reading of the right half-matrix or of the left half-matrix respectively. The output signals of the sense amplifier 4 thus selected are sent to enabling/disabling structures that are generally designated by the reference numeral 6. Said structures 6 comprise enabling/disabling means for the passage of the data of the left half-matrix or of the right half-matrix, designated by the reference numeral 7 in figures 5 and 6, and means 14 for enabling/disabling access of the data of the matrix to the internal bus 1, designated by DATA-BUS in figure 5. The output of the enabling/disabling structures 6 is sent, by means of the line 8, to the internal bus 1 H (DATA-BUS). The programming means 5 R and 5 L are connected to the internal bus 1 H by means of the line 8. This connection on the line 8, in case of programming, allows the flow of data from the outside of the memory to the memory itself. Likewise, the programming means 5 shown in the right portion of figure 1 are connected, by means of a similar line 8, to the internal bus, in this case the bus 1 L . The programming means 5 therefore receive in input the line 8 (i.e., the connection to the internal bus), the reference programming voltage VPD-rif, and a programming signal that indicates the half-matrix to be programmed. In the case of the programming means 5 R , the input programming signal is the signal PG-R for programming the right half-matrix 5 R ; for the programming means 5 L , the input signal is instead the signal PG-L. The outputs of the programming means 5 L and 5 R are sent respectively on the line YMS-L and on the line YMS-R for access to the memory half-matrices. Switching means 12, driven by a direct memory access signal, respectively DMA-R and DMA-L for direct access to the right and left half-matrix, are adapted to interrupt the connection between the programming means 5 R and 5 L and the lines YMS-R and YMS-L and to directly connect the left and right memory half-matrices to the internal bus 1 (DATA-BUS) by means of the line 8. Figure 3 shows the programming unit 30, separated from the architecture according to the invention shown in figure 2. Figure 4 is a detail view of the programming unit 30 shown in figure 3. For the sake of generality, the reference numerals are generalized, in these figures and in the ones that follow, by eliminating the suffixes L and H. In detail, the programming unit 30 comprises logic means 13 that receive in input the programming signal PG, the signal L/R that indicates whether the half-matrix to be programmed is the left half-matrix or the right one, and the line that arrives from the internal bus 1 for the flow of data from the outside world, by means of the bus, to the memory during programming. The output of the logic means 13 is sent to the programming terminal 2, which is connected to the line YMS- L/R that is adapted to connect the outside world to the left and right memory half-matrices respectively. Means 21 for adjusting the programming voltage receive in input the reference programming voltage VPD-rif produced by the voltage dividing means 3 and the programming voltage fedback by the programming terminal 2. The adjustment means 21 are advantageously provided, for example, by a differential amplifier, which receives in input, at its non-inverting terminal, the reference voltage VPD-rif and the output voltage of the programming terminal 2 at its inverting terminal. Switching means 12, advantageously provided by an N- channel transistor whose gate terminal receives the signal DMA-L/R, allow switching, in the presence of a direct memory access (DMA) signal, to the direct memory access function, enabling the direct connection between the internal bus 1 and the line YMS-L/R that leads to the memory half-matrices. Figure 5 shows the data sensing unit 20, separated from the architecture according to the invention shown in figure 2. Figure 6 is a detail view of the data sensing unit 20. This figure explicitly shows, in their circuital embodiment, the means 7 for enabling/disabling the flow of data of the left half-matrix or of the right half-matrix and the means 14 for enabling/disabling the access of said data to the internal bus 1. The enabling/disabling means 7 comprise a first structure and a second structure of the tristate type, designated by the reference numerals 15 and 16 respectively, that receive in input the signals SA-L and LEFT and the signals SA-R and RIGHT, respectively. The signals LEFT and RIGHT indicate the side of the memory matrix that is affected by the reading operation (the left side or the right side, respectively). The output SA-OUT of the enabling/disabling means 7 passes through the means 14 for enabling/disabling access to the internal bus 1, which are advantageously provided by a tristate structure 17 that receives in input the output signal SA-OUT of the enabling/disabling means 7 and receives, at the gate terminal of its P-type transistor, a signal HZ for enabling/disabling access to the internal bus 1. The gate terminal of the N-type transistor of the tristate structure 14 instead receives in input the inverted signal HZ. Figure 7 is a view of the circuit for generating the direct memory access signals, respectively for the right half-matrix, DMA-R, and for the left half-matrix, DMA-L. Said circuit comprises a first NOR gate 18, which receives in input the signal LEFT and the inverted direct memory access signal DMAn, and a second NOR gate 19, which receives in input the signal RIGHT and the signal DMAn. The outputs respectively of the NOR gates 18 and 19 are the signals DMA-R and DMA-L for direct access to the right half-matrix and to the left half-matrix respectively. With reference to the above figures, the operation of the architecture according to the invention is as follows. The sense amplifier 4 captures the data of the left half-matrix and of the right half-matrix of the memory device. As a consequence of the presence of a signal LEFT or RIGHT that is respectively high and low or vice versa, flow of the data of the left half-matrix or of the right half-matrix in output from the sense amplifier is enabled by virtue of the action of the enabling/disabling means 7 shown in figure 6. When the data have been enabled for flow in output from the sense amplifier 4, they are ready to access the internal bus 1 to be sent to the output terminals (not shown) of the memory device. In this case, the internal bus is used to transfer in output the data captured by the reading operation. This access to the internal bus is controlled by the enabling/disabling means 14 according to the enabling/disabling signal HZ. When the signal HZ is high, the enabling/disabling means are in a high-impedance condition and the data cannot be sent over the internal bus 1. It should be noted that the redundancy structure also has a configuration that is similar to the diagram of figure 2, i.e., a data sensing unit 20 and a duplicated programming unit 30. Vice versa, when the signal HZ is low, access to the internal bus 1 is allowed. The use of a sense amplifier of the reversible symmetrical type allows to balance the reading paths of the memory matrix and to mutually match the propagation times for reading the data on one branch or the other of the sense amplifier. As regards the programming step, which is timed by the high signal PG (PG-R and PG-L), each one of the two programming units 30 provided for the left half-matrix and for the right half-matrix is directly connected to the internal bus 1 for the programming of data present on the internal bus 1 in said memory half-matrices. In this case, the internal bus carries the data from the outside of the memory to the inside thereof. In the case of parallel programming, the signals for programming the left half-matrix PG-L and for programming the right half-matrix PG-R are both high to enable simultaneous programming, which occurs on both half-matrices. In this manner, one maintains column redundancy efficiency, since it is possible to apply redundancy simultaneously to both defective bit lines in the two memory half-matrices. In fact, if the bit line that is to be programmed is defective, column redundancy is performed for the defective line and for the corresponding line in the opposite half-plane simultaneously, allowing to always program simultaneously the redundancy lines provided in replacement of the defective line or lines. In this manner, the memory device is not rejected if two bits are simultaneously defective, since said two bits always belong to the same bit line, which is now split into two half-lines that belong to two opposite half-planes, the left one and the right one, but can be programmed simultaneously. It should be noted that the redundancy structure also provides for a configuration that is similar to the diagram of figure 2, i.e., a data sensing unit 20 and a duplicated programming unit 30. The programming unit 30 has local adjustment means 21 that are adapted to adjust, by feedback, the programming voltage with which the various memory cells of the half-matrices are to be programmed. The reference voltage VPD-rif is in fact sent in input to said adjustment means 21 together with the output voltage of the programming terminal 2 provided for the bit to be programmed. The reference voltage VPD-rif is generated proximate to the programming terminal 2, so that it is free from the voltage drops that are present on the programming line. The voltage in output from the adjustment means 21 and thus fed to the programming terminal 2 is adjusted constantly by utilizing the feedback, in said adjustment means, of the output voltage of the programming terminal 2. Therefore, the local adjustment means 21 make the programming voltage independent of the voltage drops along the lines, so as to ensure uniform programming of the various memory cells. Said means 21 allow to make the programming voltage level carried on the lines YMS-L/R independent of the number of cells being programmed, without using particular compensation techniques that are common in other approaches. Direct memory access from the outside of said memory is controlled by the switching means 12, which are enabled/disabled by the signal DMA-L/R. Direct memory access provides for two dedicated paths 8 that directly connect the internal bus 1 to the left and right memory half-matrix respectively. Generation of the signals DMA-L/R is controlled by the circuit of figure 7, in which the signal DMAn acts as a regulator. If the direct memory access function is activated (DMAn=0), then if LEFT=1 and RIGHT=0, i.e., if the involved half-matrix is the left one, then DMA-R=0 and DMA-L=1. If LEFT=0 and RIGHT=1, the opposite situation occurs. In practice it has been observed that the architecture according to the invention fully achieves the intended aim, since it allows to provide a much faster reading and programming path management than conventional architectures. The possibility of simultaneously programming memory half-matrices that belong to different half-planes considerably in fact speeds up the programming step and at the same time allows to avoid the need to reject, during testing, a memory device due to the presence of two defective bits on two different bit lines. This problem, which is frequent in conventional architecture, was due to the fact that the programming means that program a memory matrix do not allow to apply redundancy to two different lines simultaneously, whereas this is possible with the architecture according to the invention, since the memory matrix is divided into two half-matrices and the programming means simultaneously program even multiple bits on one half-line of a half-matrix and on the corresponding half-line in the opposite half-matrix. Therefore, this entails the possibility of applying redundancy to both half-lines and to avoid having to reject the memory device during testing or resorting to slower approaches, such as byte propagation. Programming with a programming voltage that is feedback-adjusted with a constant reference voltage VPD-rif allows to program all the memory cells with a uniform voltage, avoiding the problems of voltage drops along the lines that in conventional architecture caused the last cells, in terms of programming time order, to be programmed with voltage values that were distinctly lower than those of the first ones. Furthermore, the architecture according to the invention ensures alignment of the voltage VPD with the reference value, regardless of the number of memory cells being programmed. Furthermore, locating the voltage dividing means 3 proximate to the programming terminal in turn makes the reference voltage VPD-rif immune from any drops. The provision of a duplicated programming structure does not entail area consumptions, since the area already necessarily provided for the sense amplifiers, which is naturally necessary, is used fully for its placement. Finally, the use of symmetrical and reversible sense amplifiers facilitates balancing of the reading paths of the memory, with the possibility of providing uniform data propagation delays on both sides of the sense amplifiers and uniform data capture. The properties of the architecture according to the invention are also maintained for the redundancy portion of the memory device. The internal bus, which is the only path for data transmission in or out of the memory and from the outside of the device to the inside, provides a minimal and at the same time multipurpose transmission structure. In addition to having the function of sending the data outside the memory for reading and, vice versa, of sending the programming data to said memory, this bidirectional transmission medium also has the function of transmitting outside said memory additional information regarding the status of the memory, which can be required for example during testing. The architecture thus conceived is susceptible of numerous modifications and variations, all of which are within the scope of the inventive concept. Thus, for example, the splitting of the memory matrix into two half-matrices and the division of said half-matrices into four half-matrix subsections each are merely examples, since it is possible to perform different divisions without abandoning the inventive concept. Furthermore, the enabling/disabling means 14 can also be constituted by two pass transistors. Finally, all the details may be replaced with other technically equivalent elements. In practice, the materials employed, so long as they are compatible with the specific use, as well as the dimensions, may be any according to the requirements and the state of the art. Where technical features mentioned in any claim are followed by reference signs, those reference signs have been included for the sole purpose of increasing the intelligibility of the claims and accordingly such reference signs do not have any limiting effect on the interpretation of each element identified by way of example by such reference signs.

Claims: A programming and reading management architecture, particularly for test purposes, for memory devices of the non-volatile type, comprising: at least two memory half-matrices; a bidirectional internal bus (1) for the transmission of data to and from the memory half-matrices; a programming unit (30) for each one of said at least two memory half-matrices for applying a programming voltage to said internal bus (1); and a data sensing unit (20); said programming units being adapted to program said at least two memory half-matrices, said data sensing unit (20) and said programming units (30) communicating with said internal bus (1) to reroute onto said internal bus (1) reading data and programming data of said at least two memory half-matrices, characterized in that each one of said programming units (30) comprises means (3) for generating a reference programming voltage (VPD-rif), said reference programming voltage being generated proximate to a programming terminal (2), each one of said programming units (30) comprising programming voltage adjustment means (21) that receive said propramming voltage and said reference programming voltage to locally adjust the programming voltage so as to make it independent of the voltage drops along the internal bus (1) for programming the memory cells of said at least two memory half-matrices. The architecture according to claim 1, characterized in that said programming units (30) are adapted to program said at least two memory half-matrices in parallel. The architecture according to claim 1, characterized in that it comprises means (12) for direct access to said at least two half-matrices, said means being enabled by a signal (DMA-R, DMA-L) for selecting the half-matrix to be accessed and by a direct access control signal (DMA), said direct access means having a duplicated dedicated path for direct access to each one of said at least two memory half-matrices. The architecture according to claim 1, characterized in that said reference programming voltage generation means comprise a voltage divider (3) that is arranged proximate to said programming terminal (2). The architecture according to claim 1, characterized in that said programming voltage adjustment means (21) receive in input said reference programming voltage (VPD-rif) and said programming voltage generated by said programming terminal. The architecture according to claim 1, characterized in that each one of said programming units (30) is driven by a programming control signal (PG-R, PG-L) and by a signal that indicates which of said at least two memory half-matrices is to be programmed. The architecture according to claim 1, characterized in that each one of said programming units (30) is connected to said internal bus (1) and to one of said memory half-matrices. The architecture according to claim 1, characterized in that said data sensing unit (20) comprises: a sense amplifier (4); means (7) for enabling/disabling the flow of the data of said at least two half-matrices; and means (14) for enabling/disabling access to said internal bus by the data read from said at least two memory half-matrices. The architecture according to claim 8, characterized in that said means (7) for enabling/disabling the flow of data comprise tristate structures (15, 16) that are driven by signals for selecting said at least two half-matrices to enable/disable the flow of the data related to the selected half-matrix. The architecture according to claim 8, characterized in that said means (14) for enabling/disabling the access of the data of said half-matrices to the internal bus comprise a tristate structure (17) that is driven by a signal (Hz) for enabling/disabling access to said internal bus. The architecture according to claim 8, characterized in that said sense amplifier (4) is of the reversible symmetrical type. The architecture according to claim 3, characterized in that said paths for direct access to said memory half-matrices are enabled/disabled by signals that indicate direct access to one or the other of said memory half-matrices. The architecture according to claim 12, characterized in that said signals (DMA-L, DMA-R) that indicate direct access to one or the other of said memory half-matrices are produced by logic means (13) that receive in input a signal (L/R) for selecting one of said memory half-matrices and an inverted direct memory access signal. The architecture according to claim 2, characterized in that said programming units (30) adapted to program said at least two memory half-matrices in parallel are adapted to keep the column redundancy function active, said redundancy being performed simultaneously for both of said at least two memory half-matrices, simultaneously replacing the defective lines of said two half-matrices with redundancy lines. The architecture according to claim 1, characterized in that each one of said at least two memory half-matrices is divided into a plurality of half-matrix subsections for the use of hierarchical decoding means. The architecture according to claim 15, characterized in that each one of said at least two memory half-matrices is divided into four half-matrix subsections. The architecture according to claim 16, characterized in that it comprises, for each one of said half-matrix subsections, a data sensing unit (20) and two programming units (30). The architecture according to claim 1, characterized in that it comprises a redundancy line management structure for said at least two memory half-matrices, said structure comprising a data sensing unit (20) and two programming units (30), said data sensing unit and said programming units being identical to said data sensing unit and said programming units of normal word lines of said memory half-matrices. The architecture according to claim 18, characterized in that said data sensing unit (20) and said programming units (30) for said redundancy lines communicate with said internal bus (1) to reroute over said internal bus redundancy data of said at least two memory half-matrices.

Inventors: FONTANA MARCO, PASCUCCI LUIGI, FONTANA, MARCO, PASCUCCI, LUIGI
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1996
Main classification: G11C5
IPC codes: G11C5, G11C16