Compensation for input voltage variation in an electric motor drive

Abstract: The present invention employs digital circuitry to compensate for variations in DC link voltage transmitted to a switched reluctance machine. The digital voltage compensation system of the present invention periodically samples the DC link voltage and actual rotor speed, then supplies the samples in digital form to a microcontroller that derives a compensated speed signal to compensate for changes in DC link voltage.

Description: The present invention generally relates to an apparatus and method of compensating for DC link voltage variations in an electric motor system. More particularly, the present invention relates to digital circuitry and a method for operating a switched reluctance drive that periodically reads a digital value corresponding to a DC link voltage and adjusts a speed indication signal to compensate for changes in the DC link voltage. The adjusted speed signal is transmitted to a controller where it is used to adjust energisation timing of the switched reluctance drive. Electric motors turn electrical energy into mechanical energy to produce work. Electric motors work by applying a voltage across one or more windings in the motor thereby energising the windings to produce a resultant magnetic field. Mechanical forces of attraction caused by the magnetic field in turn cause a rotor in the electric motor to move. The efficiency of the electric motor depends in part on the timing and magnitude of each application of voltage to the motor. The magnitude of voltage applied is particularly important in the case of switched reluctance machines. Historically, the switched reluctance motor was thought to be incapable of competing effectively with other types of motors. Part of the problem was the difficulty in controlling the switched reluctance motor. More recently however, a better understanding of the motor design and application of electronically controlled switching has resulted in robust switched reluctance drives capable of high levels of performance over a wide range of sizes, powers and speeds. Note that the term 'motor' is used here, but it will be appreciated by those skilled in the art that the term covers the same machine in a generating mode unless a particular distinction is made. The general theory of the design and operation of switched reluctance motors is well known and is discussed, for example, in The Characteristics, Design and Applications of Switched Reluctance Motors and Drives , by Stephenson and Blake and presented at the PCIM '93 Conference and Exhibition at Nüremberg, Germany, June 21-24, 1993. The switched reluctance motor is generally constructed without windings or permanent magnets on the moving part of the motor (called the rotor). The stationary part of most switched reluctance motors (called the stator) includes coils of wire wound around stator poles that carry unidirectional current. In one type of switched reluctance motor, coils around opposing stator poles are connected in series or parallel to form one phase winding of a potentially multi-phase switched reluctance motor. Motoring torque is produced by applying a voltage across each of the phase windings in a predetermined sequence that is synchronized with the angular position of the rotor so that a magnetic force of attraction results between poles of the rotor and stator as they approach each other. Similarly, generating action is produced by positioning the pulse of voltage in the part of the cycle where the poles are moving away from each other. In typical operation, each time a phase winding of the switched reluctance motor is switched on (or energised), magnetic flux is produced by the phase winding, thereby turning the two opposing stator poles associated with the phase winding into electro-magnets of opposing polarities. The electro-magnetic field created by the energised phase winding causes a force of attraction on the rotor poles. The general construction and operation of controllers for switched reluctance motors is generally understood and is described herein for background purposes only. In order to maintain the speed and related torque developed by a switched reluctance motor, it is necessary to carefully control when and how much voltage is applied to the phase windings of the motor. Because the supply voltage can vary significantly, a control scheme that ignores changes in supply voltage may experience a significant reduction in ability to control the machine as demanded by the user. This is because the flux produced by the phase windings is directly related to the amount of voltage applied. Accordingly, a change in the supply voltage may result in more or less flux produced by the phase windings than would otherwise be desired. This undesirable change in the flux in the motor can result in the electro-magnets created by energisation of the phase windings being too strong or too weak resulting in degraded motor performance. Many switched reluctance motors are run from either battery supplies or, more commonly, from a DC voltage that is derived by rectifying or otherwise converting an AC supply voltage into a DC voltage. In the present application the DC voltage provided to the switched reluctance motor (from a battery, rectifier or otherwise) is referred to as the "DC link voltage". As those skilled in the art will recognize, the DC link voltage available to a switched reluctance motor system is often not constant. Changes in the voltage of the AC supply, changes in the electrical environment in which the motor system operates, and changes in the electrical components used to provide the DC link voltage often result in a DC link voltage that varies over time. These variations in the DC link voltage, if uncompensated, can diminish the performance of a switched reluctance drive. As discussed above, in switched reluctance drives when and how voltage is applied to the phase windings is very important. In most known switched reluctance drives, the relationship between the speed of the motor, the desired torque, and the time and amount of voltage that is applied to the phase windings is determined empirically through a process referred to as characterisation. In characterisation, the operating parameters of the motor are determined over a wide variety of operating conditions. These operating parameters are then stored in an analogue or digital circuit (called a control law table). During operation of the drive, the control system provides the control law table with signals representing the speed of the motor and the desired torque. Circuitry including the control law table in turn produces signals that control the energisation of the phase windings. The use of motor controllers with control law tables is generally understood and is not discussed in detail herein. For some motors, the characterisation is accomplished in a process that assumes that the DC link voltage available to the motor system is unchanging. Realizing that the DC link voltage will typically vary, characterisation is sometimes done assuming that the DC link voltage is at its lowest expected value. In other words, characterisation is done assuming the "worst case" DC link voltage. This type of characterisation is undesirable to the extent that it characterises the switched reluctance drive to run in a worst-case scenario (which may seldom occur) rather than at the desired optimum DC link value. Other motors are characterised at their optimum DC link voltage. For these motors, there must be some compensation for changes in the DC link value during operation or the drive will suffer diminished performance. Some known switched reluctance drives do not compensate for changes in DC link voltage. These systems necessarily suffer from the operating problems and loss of efficiency that results from such changes. Other switched reluctance drives use an analogue system to compensate for DC link voltage variations. In general, these systems compensate for the changes in the DC link voltage by adjusting the speed signal provided to the control law table so that the speed signal provided to the controller is not the actual speed of the motor but a modified speed signal that represents the actual speed signal modified by a signal representative of the DC link voltage. In typical analogue DC link compensation circuits, an analogue feedback signal that corresponds to the rotational speed of the motor is sampled at a fixed frequency using pulses having a duty cycle that corresponds to the DC link voltage. This sampling produces a modified analogue speed signal that is provided to the control circuit, which may include a control law table. For example, if the DC link value is at or near the desired DC link value, the speed feedback signal may be sampled using pulses with a duty cycle of approximately 90%. This will produce a modified speed signal of a first value. If the DC link value drops below the desired DC link voltage, the duty cycle of the sampling pulses may increase up to 100%, which correspondingly increases the modified analogue speed signal provided to the controller. Conversely, if the DC link voltage increases, the duty cycle of the sampling pulses will decrease, reducing the value of the modified analogue speed signal provided to the controller. The controller, which may include a control law table, receives the modified signals and produces the signals that control the energisation of the motor windings in a manner that compensates for the variations in the DC link voltage. These analogue DC link compensation systems typically suffer from several disadvantages. In particular, these analogue systems suffer from the poor accuracy and performance limitations inherent in all analogue systems. Moreover, these analogue systems require components that are costly and can only operate within a limited operating range. For example, the use of the analogue sampling technique discussed above is limited to the extent that the sampling pulses cannot have a duty cycle of greater than 100%. Still further, as digital controllers are integrated into motor control systems, the requirement of an analogue DC link compensator results in the need for additional, costly circuitry. Given the disadvantages of the known analogue systems, it is desirable to have a DC link voltage compensation system that is accurate, covers a considerable range of DC link voltages, and is relatively inexpensive. The present invention is defined in the accompanying independent claims 1 and 7. Preferably features of the invention are recited in the claims respectively dependent thereon. The present invention generally relates to an apparatus and method of compensating for DC link voltage variations in an electric drive system. More particularly, the present invention relates to a digital system for accurately and efficiently implementing DC link compensation in a manner that overcomes many of the disadvantages associated with known analogue DC link compensation systems. In one embodiment of the present invention, digital circuitry is used to periodically read digital signals representing the DC link voltage and actual rotor speed. The digital circuitry then uses a novel approach to adjust the digital representation of the rotor speed to compensate for changes in the DC link voltage. The compensated speed signal is then transmitted to a controller, which may include a control law table, where it is used to adjust coil energisation timing of the switched reluctance drive. In accordance with a preferred embodiment of the present invention, the foregoing disadvantages of known switched reluctance drive controllers are overcome by utilizing a microcontroller to digitally process signals representing DC link voltage to achieve compensation for DC link voltage variations. Other aspects and advantages of the invention will become apparent upon reading the following detailed description of exemplary embodiments of the invention and upon reference to the accompanying drawings, in which: Figure 1 is a block diagram of a DC link voltage compensation system according to one embodiment of the present invention; Figure 2 is a flow chart illustrating a method of implementing a DC link voltage compensation system according to one embodiment of the present invention; Figure 3 is a graph illustrating one possible relationship between the DC link voltage and a compensation factor that may be implemented through the use of the present invention; and Figure 4 is a table used to determine an acceptable relationship between the digital representation of the average DC link voltage and a compensation factor. Figure 1 illustrates a representative block diagram of a digital DC link voltage compensation system 10 for a switched reluctance motor (partially represented by a rotor 12 ). The voltage compensation system 10 further includes a rotor position sensor 14 (RPT), which is influenced by a member attached to rotate with the rotor, for creating a rotor position sensor output signal 16 representative of the position of rotor 12 . It will be appreciated by those skilled in the art that rotor position information can be derived by several alternative means, including a rotor position transducer (RPT) or by estimating the information from motor current, voltage and/or inductance. The sensor 14 is shown in block form in Figure 1 for illustrative purposes. By monitoring the changes in the rotor position over a given time period it is possible to determine the speed of the motor. In Figure 1 , a speed measurement block 18 performs the function of receiving the rotor sensor output signal 16 and providing an actual speed signal 20 that corresponds to the actual rotational speed of the rotor 12 . Construction of the speed measurement block 18 will be straightforward to one skilled in the art and depends on the particular RPT selected. The actual speed signal 20 is provided to a digital DC link voltage compensator block 22 . In addition to sensing the rotational speed of the rotor, the circuit of the present invention also senses the DC link voltage 24 . In the embodiment of Figure 1 , an analogue to digital converter (ADC) 26 samples the DC link voltage 24 and converts it into a digital output 28 that represents the voltage magnitude of the DC link voltage. The ADC 26 transmits its output 28 to the digital DC link voltage compensator block 22 . In one embodiment the ADC output 28 comprises 8 (eight) data bits, allowing for 2 8 (= 256) different voltage levels to be represented. The digital DC link voltage compensator block 22 receives the actual speed signal 20 and the ADC voltage output 28 and generates a digital compensated speed signal 30 which is passed to a motor controller 32 associated with the switched reluctance motor. In one embodiment, the digital compensated speed signal 30 is adjusted inversely to changes in DC link voltage 24 . For example, a rise in DC link voltage 24 will produce a smaller valued, compensated speed signal 30 , while a fall in DC link voltage 24 will produce a larger valued, compensated speed signal 30 . The digital compensated speed signal 30 from the digital DC link voltage compensator 22 is then applied to the motor controller 32 that in one embodiment includes a control law table. Control of the motor is accomplished using the compensated speed signal. It will be appreciated by those skilled in the art of motor control that the actual speed signal will be used for other aspects of control of the motor (not discussed here) in conventional fashion. The digital DC link voltage compensator 22 may be implemented in a number of different ways. For example, discrete digital components, or an application specific digital integrated circuit may be used to implement the DC link voltage compensator. In one embodiment of the present invention a digital microcontroller, such as a microcontroller from Motorola's MC68HC11 family of microcontrollers, may be used to implement the DC link voltage compensation method of the present invention. In that embodiment the same microcontroller may be used as the motor controller 32 . This embodiment has the advantage of performing DC link voltage compensation without the need for significant additional circuitry over that already required to implement the motor controller 32 . Turning now to Figure 2 , there is shown a flow chart illustrating a preferred method of implementing the digital DC link voltage compensator 22 within the DC link voltage compensation system 10 . In particular, Figure 2 illustrates a method in accordance with the present invention by which the digital DC link voltage compensator 22 may convert the actual speed signal 20 into the compensated speed signal 30 . At the beginning of the process, the digital DC link voltage compensator must first determine the actual DC link voltage. This is accomplished by reading the digital value provided by the ADC 26 that corresponds to the actual DC link voltage. To avoid having transient changes in the DC link voltage 24 affect the motor operation, the DC link voltage 24 is averaged over a given period of time. In the embodiment of the present invention illustrated in Figure 2 this reading and averaging is accomplished as follows: At step 34 the digital DC link voltage compensator 22 reads an eight bit digital output of the ADC 26 . At step 36 the digital value corresponding to the DC link voltage is normalised to values corresponding to decimal values between 123 and 210. The normalisation range corresponds to a range of DC link voltages that the digital DC link voltage compensator 22 can compensate for and still allow the control system of the drive to accurately control speed and torque. To accomplish the averaging of the DC link voltage over time, the process of reading the digital signal from the ADC 26 is repeated 256 times. The 256 readings are then added together and divided by 256 to get an average DC link voltage. In the present invention this adding and dividing is accomplished through the use of a binary storage register called link_sum. Each normalised DC link voltage reading is added to link_sum, a binary variable representing a running total, in step 38 . In next step 40 , a counter tracks whether 256 readings have been added to link_sum, if not, then the process repeats and another set of DC link voltage readings is taken. However, if exactly 256 readings have been added to link_sum, then 127 is added to link_sum in step 42 . Adding 127 to link_sum effectively allows link_sum to be rounded in step 42 , instead of merely truncating it. The counter is then reset to zero in anticipation of another round of voltage sampling 42 . In step 44 link_sum is shifted to the right 8 (eight) spaces, effectively dividing link_sum by 2 8 (= 256), thereby averaging link_sum to derive an average DC link voltage. The advantage to shifting link_sum to the right eight spaces as opposed to dividing by 256 is that the same result is achieved in far less time. Division is much more time consuming that mere shifting of numbers. Saving time is particularly important in real time systems where the present invention finds particular application. Once the average DC link voltage has been determined, the digital DC link compensator 22 of the present invention then determines the compensation factor to adjust the actual motor speed signal 20 to compensate for any variations in the DC link voltage. Because the present invention uses digital circuitry, the compensation factor may be selected according to any arbitrary relationship between actual DC link voltage and the compensation factor. In one embodiment of the present invention, the relationship between the actual DC link value and the compensation factor is set such that the compensation factor increases with decreasing actual DC link voltage, and decreases with increasing actual DC link voltage. Line A of Figure 3 illustrates one desirable relationship between DC link voltage (represented on the horizontal axis in terms of normalised ADC values) and the compensation factor (represented on the vertical axis). In Figure 3, the relationship between the DC link values and the compensation factor is as follows: the compensation factor is equal to the optimum DC link voltage divided by the actual DC link voltage. For example, in one embodiment of the present invention the optimum DC link voltage may be 1350 V DC , which translates into a normalised ADC value of 172 (based on a 2000 volt scale divided into 256 digital representations). If the actual DC link voltage is 1350 V DC (with an ADC of 172) then the compensation factor should be 1.0 since the actual speed signal does not need to be modified since there is no DC link voltage variation. Using the same example, if the actual DC link voltage is 1550 (with an ADC value of 198) the compensation factor should be (1350/1550) or approximately 0.87. Two examples are illustrated with respect to line A of Figure 3 ; when the actual DC link voltage is 1056 volts (with an ADC value of 135) the compensation factor should be approximately 1.28. When the actual DC link voltage is 1550 volts (with an ADC value of 198) the compensation factor should be approximately 0.87. It should be noted that the relationship between DC link voltages and the compensation factors represented by line A of Figure 3 is but one of many possible relationships that may be used to implement the present invention. The actual derivation of the compensation factor given the normalised ADC value representing the actual DC link voltage may be accomplished in a variety of ways. For example, a simple look-up table may be used, or the compensation factor may be calculated in some other manner. In the embodiment represented by Figure 2 , the compensation factor is calculated. Line A of Figure 3 represents a constant-slope approximation to a non-linear optimal compensation factor. As those skilled in the art will recognize, it is often difficult to exactly describe complex mathematical relationships, and as such, more simple approximations are often used as good, practical substitutes that may be implemented in digital systems. Accordingly, the embodiment represented by Figure 2 does not implement a precise non-linear optimal relationship between compensation factor and voltage variance, but implements a linear approximation related to the relationship represented by line A as described below. First it was realized that the relationship represented by Line A can be expressed as Y = MX + C where Y represents the compensation factor, M represents the slope of line A , X represents a digital value corresponding to the actual DC link voltage, and C represents an offset. To determine the characteristics of line A , the slope of line A was calculated. In the example of Figure 3 this slope M came out to be approximately - 0.00646. Because the fractional number 0.00646 was inconvenient to represent digitally, it was multiplied by a large multiplying factor (in this example 2 13 or 8192) to produce a whole decimal integer that could be used in a digital system. In this example the initial slope was approximately - 53. Because the right hand side of the equation was multiplied by 2 13 the left hand side must also be multiplied by the same number so that the calculated compensation factor Y when the actual DC link value equalled the desired DC link value (or when the normalised ADC value was 172) would now be 2 13 or 8192 rather than 1. Using those numbers the value C was calculated to be -17308. It was then noted that, while selecting the offset C at -17308 produces the desired compensation factor when the actual DC link voltage is equal to the optimum DC link voltage, it also produced offset errors at DC link voltages that were either greatly above or greatly below the optimum DC link voltage. This would have resulted in the compensation factor being slightly different from the desired compensation factor illustrated by line A . Accordingly, it was decided to select other slopes and compare the relative offset errors at the highest and lowest expected DC link values for the different slopes. A tradeoff between percentage error and overcompensation at the high end was then made. Figure 4 illustrates one example of these calculations for slopes of -53, -54, -55, -56 and -57. The chart in Figure 4 illustrates absolute value of the slope M, the calculated offset C, and absolute value of the percent error from the desired compensation factor represented by line A for the highest and lowest expected DC link voltages. The slope of -55 was selected in the present example, because it represents the preferable tradeoff between percentage error and overcompensation at high voltage. The lowest expected DC link voltage was used to determine the slope because it is believed that it is better to have too much DC link compensation at high actual DC link voltages than not enough at low actual DC link voltages. When a slope of -55 is used, the calculated offset factor C comes out to be 17,652. The selection of the slope -55 was made for the specific example described herein. Depending on the construction of the motor, the desired operating points and the goals of the system designer, other suitable slopes can easily be selected. Referring back to Figure 2, which illustrates an embodiment using a slope of - 55, the average DC link voltage that was derived in step 44 (which corresponds to X in the equation provided above) is multiplied by slope value 55 (fifty-five) in step 46 . The negative nature of the slope is understood and is not used in the example of Figure 2. Multiplying the average link voltage by 55 in step 46 enables determination of a corresponding DC link voltage variation. In order to complete the equation Y = MX + C it is necessary to subtract the value obtained by multiplying the average DC link voltage by 55 from 17,652 in step 48 , to produce Y the compensation factor. Having calculated the compensation factor, the digital DC link voltage compensator of the present invention then needs to adjust the measured motor speed 20 to reflect the compensation factor. This is accomplished, generally, by multiplying the actual motor speed 20 by the compensation factor to produce a compensated speed signal 30 . That is applied to the controller 32 as discussed above. In the embodiment of Figure 2 scaling, normalisation and multiplication factors are used to convert the actual speed signal 20 into the compensated speed signal 30 . These scaling factors, normalisation factors, and multipliers are used to optimize the implementation of the present method in a digital system and to compensate for the scaling and offset factors used to calculate the compensation factor from the actual DC link voltage. Those skilled in the art will recognize that these factors and multipliers may be changed and altered without deviating from the present invention. In the embodiment of Figure 2 , the actual speed signal 20 is received from the speed measurement block 18 and read by the digital DC link voltage compensator block 22 in step 50 . Knowing the actual speed provides a baseline which is altered according to DC link voltage variations. Once the actual speed signal is read in step 50 , it is normalised in step 52 . Here normalisation requires limiting of values greater than 2 15 -1 = 32767 to be equal to 32,767. This step ensures that the maximum speed signal used to provide a compensated speed signal is never greater than 32,767. In step 54 , the normalised actual speed in digital form, is multiplied by the digital compensation factor calculated in step 48 to produce a digital output which represents a compensated speed signal 30 . The digital compensated speed signal 30 may then be provided to the motor controller 32 to control the motor operation as discussed above. In the embodiment of Figure 2 the digital compensation speed signal is first scaled and then limited before it is provided to the motor controller. In Figure 2 the scaling occurs in step 58 where the compensated speed signal is divided by a divisor equal to 2 13 (8,192) * 2 7 (128) = 2 20 (1,048,576), to produce a scaled compensated speed in step 56 . The 2 13 (8,192) component of the divisor offsets multiplication of the slope by the same number above. The 2 7 (128) component helps to scale the uncompensated speed down to an 8 (eight) bit range. Adjusting the scaled compensated speed to an 8 bit range is completed by truncating values above eight bits in step 58 . Thus, in the embodiment of Figure 2 , step 58 results in the production of an 8 bit scaled compensated speed signal 30 which is transmitted to the switched reluctance motor controller 32 . The compensated speed signal 30 functions to provide to the switched reluctance motor controller 32 a way to make adjustments in pulse magnitude, duration and timing based on variations in DC link voltage. The compensated speed signal 30 works within a range of acceptable DC link voltages 24 as normalised and truncated in one embodiment of the present invention described above. There has been described herein a DC link voltage compensation system and method which adjusts a speed indication signal in response to a variation in DC link voltage. The program listing attached as Appendix A is a representative listing of a software routine that may be used to construct a DC link voltage compensation system in accordance with the present invention. A preferred embodiment of the present invention provides a digital DC link voltage compensation system which adjusts a rotor speed signal in response to a variation in DC link voltage. The digital voltage compensation system provides for improved accuracy and better control of rotor speed and torque in a cost-effective manner. While the invention is susceptible to various modifications and alternative forms, a number of specific embodiments have been shown by way of example in the drawings and have been described in detail. It should be understood, however, that this is not intended to limit the invention to the particular forms disclosed. On the contrary, the intention is to cover all modifications, equivalents and alternatives falling within the scope of the invention as defined by the appended claims.

Claims: A method for compensating for deviations of actual DC link voltage from a predetermined DC link voltage applied to an electric machine drive, which includes an electric machine having a rotor and a controller for controlling the machine in response to a speed signal, the method comprising the steps of: periodically sampling the actual DC link voltage and converting the sampled DC link voltage into a digital link voltage representation; periodically sampling the actual rotor speed and converting the sampled rotor speed to a digital speed representation; modifying the digital speed representation according to the digital link voltage representation to produce a compensated speed signal; and transmitting the compensated speed signal to the electric machine controller and using the compensated speed signal in control of the machine. A method as claimed in claim 1 in which the digital speed representation is multiplied by a compensation factor, generated from the digital link voltage representation, to produce the compensated speed signal. A method as claimed in claim 2, in which the compensation factor corresponds to the predetermined DC link voltage divided by the actual DC link voltage. A method as claimed in any of claims 1 to 3 in which each digital link voltage representation is an average of a plurality of samples. A method as claimed in any of claims 1 to 4 including limiting the digital dc link voltage representation to be within a predetermined range. A method as claimed in any of claims 1 to 5 including limiting the digital speed representation to be within a predetermined range. A compensation system for compensating for a deviation of an actual DC link voltage from a predetermined DC link voltage in an electric drive which includes an electric machine having a rotor (12), the system comprising: means (26) for sampling the actual DC link voltage periodically and converting the sampled DC link voltage into a digital link voltage representation; means (18) for sampling an actual rotor speed periodically and converting the sampled rotor speed into a digital speed representation; means (22) for modifying the digital speed representation according to the digital link voltage representation to produce a compensated speed signal, and means (32) for controlling the machine in accordance with the compensated speed signal. A system as claimed in claim 7 in which the means for sampling the actual DC link voltage are operable to produce, as the digital link voltage representation, an average of a plurality of sampled DC link voltages. A system as claimed in claim 7 or 8 in which the means for modifying the digital speed representation comprise means for limiting the digital link voltage representation to be within a predetermined range. A system as claimed in claim 9 in which the means for modifying the digital speed representation further comprise means for limiting the digital speed representation to be within a predetermined range. A system as claimed in claim 7, including: means for limiting the sampled DC link voltage to be within a predetermined range; means for accumulating a plurality of voltage samples; and means for averaging the voltage samples. A system as claimed in claim 8 in which the means for generating the compensated rotor speed signal further comprise: digital means for limiting the voltage sampled by making all voltage samples below a lower level equal to the lower level and all voltage samples above an upper level equal to the upper level; digital means for averaging and rounding a plurality of the voltage samples; means for multiplying the averaged and rounded voltage samples to produce a compensation factor; means for detecting the actual rotor speed; digital means for limiting the digital speed representation for values above a predetermined threshold; digital means for multiplying the digital speed representation by a compensation factor to produce an interim rotor speed signal; means for dividing the interim rotor speed signal by a predetermined divisor to produce a scaled interim rotor speed signal; and means for limiting the scaled interim rotor speed signals which are greater than a predetermined amount to produce the compensated speed signal. A system as claimed in claim 12 in which the means for generating the compensated speed signal include a microprocessor.

Inventors: BROWN GEOFFREY THOMAS, SUGDEN DAVID MARK, WEBSTER PAUL DONALD, BROWN, GEOFFREY THOMAS, SUGDEN, DAVID MARK, WEBSTER, PAUL DONALD
Applicants: SWITCHED RELUCTANCE DRIVES LTD, SWITCHED RELUCTANCE DRIVES LIMITED
Application year: 1996
Main classification: H02P7
IPC codes: H02P25, H02P7, G05F1