Data reading path management architecture for a memory device, particularly for non-volatile memories

Abstract: A data reading path management architecture for a memory device, particularly of the non-volatile type, comprising a memory matrix and data sensing means (2) that are adapted to receive in input the data of the memory matrix for reading, which has the particularity that the memory matrix is divided into at least two half-matrices (1 L , 1 R ); each one of the two half-matrices has a reference line (ROW-RIF) that is adapted to constitute a reference for reading the other half-matrix; the data sensing means (2) receive in input the data from one half-matrix (1 L , 1 R ) and the reference from the other half-matrix (1 L , 1 R ); the data sensing means (2) are adapted to transmit, according to a control timing, the data on an internal bus (DATA-BUS) for their transmission in output.

Description: The present invention relates to a data reading path management architecture for a memory device, particularly of the non-volatile type. In a non-volatile memory, it is important to be able to provide architectures that allow to perform data extraction as quickly as possible and in the reductive embodiment. One of the solutions that is adopted most frequently is to associate a reference bit line with each bit of the word, so as to provide each selection line with a cell whose conductivity characteristics are fully similar to those of a generic virgin matrix cell and at the same time repeat the capacitive load of a corresponding bit line. A drawback of this solution is the fact that it is not possible to repeat, in a simple way, the load of the entire selection path, such as for example the column multiplexer. Furthermore, the two selected cells (the matrix cell and the reference cell) are at a different distance from the same word line, with a consequent possible difference in signal level. This drawback is lessened by using static sense amplifiers, in which one waits for the steady-state condition to be reached before proceeding with the reading operation. The use of these sense amplifiers, however, entails a waste of time for reading, since it is unable to dynamically lock the timing of the reading operation to the actual conductivity of a memory cell, i.e., to the signal level that is present therein. On the other hand, the use of dynamic sense amplifiers is heavily penalized by the above mentioned drawback and by the additional inequality of the capacitive-resistive load of the lines. Furthermore, the architectures of conventional memory devices comprise, for redundancy management, redundancy line groups whose reference is constituted by the same reference columns used for the normal lines of the memory matrix. In this manner, the redundancy bit lines, too, are compared with the corresponding reference lines, but if a bit is defective on a reference line, then the memory device is defective and must be rejected because it is impossible to change the reference, due to the presence of reference columns, one for each word bit of the memory. US-A-5 022 009 discloses a data reading path management architecture for a memory device, as claimed in the preamble of claim 1. The aim of the present invention is therefore to provide a data reading path management architecture for a memory device, particularly of the non-volatile type, that allows to balance the read paths of the memory matrix side and of the reference side and the selection paths. Within the scope of this aim, an object of the present invention is to provide a data reading path management architecture for a memory device, particularly of the non- volatile type, that allows to reduce the number of reference lines. Another object of the present invention is to provide a data reading path management architecture for a memory device, particularly of the non-volatile type, that allows to detect the event of full propagation of a generic word line and at the same time to assign a corresponding reference cell to each bit line. Another object of the present invention is to provide a data reading path management architecture for a memory device, particularly of the non-volatile type, that allows to achieve synchronous propagation of the signals on the lines and therefore both on the reference cells and on the matrix cells. Another object of the present invention is to provide a data reading path management architecture for a memory device, particularly of the non-volatile type, that allows to enable/disable data transfer from the memory on a bus structure. Another object of the present invention is to provide a data reading path management architecture for a memory device, particularly of the non-volatile type, that allows to provide redundancy even for any defective bits of the reference lines. Another object of the present invention is to provide a data reading path management architecture for a memory device, particularly of the non-volatile type, that allows to produce paths for reproducing the normal propagation delays and paths within a memory matrix, for optimum balancing of the structure. Another object of the present invention is to provide an architecture that is highly reliable and relatively easy to manufacture at competitive costs. This aim and these objects that will become apparent hereinafter are achieved by a data reading path management architecture for a memory device, particularly of the non-volatile type, as defined in claim 1. This aim and these objects and others are furthermore achieved by a method for reading a memory device, particularly of the non-volatile type, that comprises at least two memory half-matrices, as defined in claim 22. Further characteristics and advantages of the invention will become apparent from the description of a preferred but not exclusive embodiment of the architecture according to the invention, illustrated only by way of non-limitative example in the accompanying drawings, wherein: figure 1 is a block diagram of the data reading path management architecture according to the invention; figure 2 is a diagram of a portion of a memory matrix executed by means of the architecture according to the invention; figure 3 is a circuit diagram of a first embodiment of the connection of a sense amplifier to the internal bus in accordance with the architecture according to the invention; figure 4 is a diagram of a first embodiment of a circuit for producing read signals of a left half-matrix or of a right half-matrix of the memory device; figure 5 is a diagram of a second embodiment of the circuit shown in figure 4; figure 6 is a circuit diagram of a second embodiment of the circuit shown in figure 3; figure 7 is a circuit diagram of a circuit for generating a signal for enabling/disabling access to the internal bus for the transmission of the data that arrive from the memory matrix; and figure 8 is a chart of the timings of the signals that are present in the architecture of the memory device according to the invention. With reference to the above figures, and particularly to figure 1, the reference numerals 1 L and 1 R designate respectively the left half-matrix and the right half-matrix of a memory device, particularly of the non-volatile type. The reference numeral 2 designates data sensing means, advantageously provided by a sense amplifier that is adapted to capture the data from the memory. Actually, the reference numeral 2 designates a plurality of sense amplifiers, whose number is equal to the number of bits of the words of the memory matrix. If one has a memory matrix that has, for example, 16-bit words, there are 16 sense amplifiers and a sense amplifier for redundancy, if provided. It should be noted that the memory matrix can be divided into any number of half-matrices, not necessarily two. Each memory half-matrix 1 (i.e., both 1 L and 1 R ) is divided into four subsections, since a matrix line selection approach employing a hierarchical decoder (not shown) is used. For the sake of convenience in description, reference will be made hereinafter to a single sense amplifier; this remark also applies to all the structures that are connected thereto. Each memory half-matrix 1 is connected by means of a bus that is adapted to connect the selected bit line of the memory matrix. Said bus is designated by L-YMS for the left half-matrix and by R-YMS for the right half-matrix. A bus, designated by SA-CNT, arrives in input to the sense amplifier 2 and carries several signals for controlling the memory device. In particular, the signals are as follows: A-LEFT: address that indicates reading of the left half-matrix 1 L ; A-RIGHT: address that indicates reading of the right half-matrix 1 R ; PCn: inverted signal related to the precharging of the nodes involved in the reading operation; EQ: equalization signal; HZ: signal for enabling/disabling access to the internal bus by the sense amplifier 2 for transmission of the data of the memory on said internal bus; RATIO: signal that indicates the mirroring ratio used in a reference system (not shown) that is adapted to check the status (programmed or virgin) of a memory cell; CAS-dis: signal for enabling/disabling biasing structures (not shown) used in said reference system. The sense amplifier 2 has two outputs for transmitting on the internal bus (not shown) the data of left half-matrix 1 L and of the right half-matrix 1 R . Said outputs are designated by SA-L and SA-R respectively. The outputs of the sense amplifier 2 are enabled or disabled for subsequent transfer to enabling/disabling means 3, which are adapted to enable/disable the passage of the data of the left half-matrix 1 L or of the right half-matrix 1 R . Advantageously, the means 3 are provided by means of tristate structures. The enabling/disabling of the outputs of the sense amplifier 2 is provided by logic means 13 that receive as inputs the outputs SA-L and SA-R of the sense amplifier 2 and the signals A-LEFT and A-RIGHT for indicating reading of the left half-matrix 1 L or of the right half-matrix 1 R . After passing through the enabling/disabling means 3, the outputs of the sense amplifier are introduced in means 4 for enabling/disabling access to the internal bus (not shown) for the transfer of the data captured from the memory matrix (by means of the sense amplifier 2) to the internal bus. Advantageously, the means for enabling/disabling access of the data to the internal bus are also provided by means of tristate structures. With reference again to the memory matrix divided into the two half-matrices 1 L and 1 R , for each one of said half-matrices it is possible to identify a first portion 5 and a second portion 6 (5 L , 5 R ; 6 L , 6 R ). The first portion, 5 L , 5 R , comprises means for selecting the bit lines of the matrix, which are advantageously provided by a multiplexer constituted by two selection buses YM and YN. In this first portion there is also a column, designated by OTP, which represents a one-time programmable column that is useful during the checking of the integrity of the memory device for devices which, despite being writable and erasable, are however inserted in plastic cases that do not have the necessary hole for the passage of UVA rays for memory erasing. The second portion 6 L , 6 R of each memory half-matrix contains the word lines of the matrix, designated by ROW-MAT, the matrix redundancy lines ROW-RED, a propagation line ROW-PROP adapted to reproduce the propagations of the signals from one cell to the next of the memory device, a reference line (only one for each half-matrix) ROW-RIF, and a line OTP whose function is similar to the column OTP described earlier. Figure 2 is an example of a configuration of one of the word bits of a memory matrix. The reference numeral 7 designates said bit. The elements designated by 13 are floating-gate transistors constituting the memory cells for the matrix lines ROW-MAT, for the redundancy lines ROW-RED, for the propagation reproduction line ROW-PROP, for the reference line ROW-RIF, and for the line OTP. The reference numerals 50 designate the bit lines. It can be seen that the propagation line ROW-PROP is disconnected from the bit lines 50, whereas all the other lines (ROW-OTP, ROW-RIF, ROW-MAT, and ROW-RED) are connected to said bit lines. Figure 3 is a view of the sense amplifier 2, which receives in input the lines L-YMS and R-YMS that are adapted to send in input to the sense amplifier the data of the bit line selected respectively in the left half-matrix 1 L and in the right half-matrix 1 R . The outputs SA-L and SA-R of the sense amplifier 2 are sent in input to the means 3 for enabling/disabling the transit of the data of the left half-matrix 1 L or of the right half-matrix 1 R . Advantageously, said means 3 comprise a first tristate structure 8 L and a second tristate structure 8 R . Said tristate structures 8 L and 8 R receive in input, respectively, the line SA-L and the signal LEFT, and the line SA-R and the signal RIGHT. The signal in output from the tristate structures 8 L and 8 R , designated by SA-OUT, is sent in input to the means 4 for enabling/disabling access to the internal bus, designated by DATA-BUS. Said means 4 advantageously comprise a tristate structure 10 that receives in input the signal SA-OUT and the signal HZ for enabling/disabling the transmission of data on the internal bus DATA-BUS. The tristate structure 10 receives in input, at the gate terminal of the N-channel transistor, the signal HZ, which is inverted by means of an inverter 9, whereas the same signal HZ is sent, without being inverted, in input to the gate terminal of the P-channel transistor of the tristate structure 10. Figure 4 shows in detail the logic means 13 for generating the signals LEFT and RIGHT. Said logic means 13 comprise a first NOR gate 11 L receiving in output the signal A-LEFT and the equalization signal EQ, and a second NOR gate 11 R receiving in input the signal A-RIGHT and the equalization signal EQ. The output of the NOR gate 11 L is the signal RIGHT, whereas the output of the logic gate 11 R is the signal LEFT. Figure 5 is a view of a second embodiment of the logic means 13, in which said logic means comprise a first NAND gate 14 R , which receives in input the signal A-RIGHT and the signal PCn (inverted precharging signal); a second NAND gate 14 L , which receives in input the signal A-LEFT and the signal PCn; and the two NOR gates 11 L and 11 R that have already been described. The outputs of the two NAND gates 15 L and 15 R are respectively combined with a precharging signal PC-L and with a precharging signal PC-R (respectively the left side precharging signal and the right side precharging signal of the sense amplifier 2). The NOR gate 11 R receives in input the output signal of the NAND gate 14 R and the equalization signal EQ. The NOR gate 11 L receives in input the output signal of the NAND gate 14 L and the equalization signal. The outputs of the NOR gates 11 R and 11 L are the signals RIGHT and LEFT respectively. Figure 6 shows a second embodiment of the circuit of figure 3, in which the means 4 for enabling/disabling access to the internal bus DATA-BUS are provided by means of a particular tristate structure that is adapted for driving high capacitive loads. Said particular tristate structure comprises a first pair of pass transistors and a second pair of pass transistors, designated by 15 and 16, which are constituted by a P-type transistor and by an N-type transistor respectively. Furthermore, the means 4 comprise two P-type transistors 17 and 18 and two N-type transistors 19 and 20, in addition to an inverter 21. In detail, in the transistor 17 the source terminal is connected to the supply voltage and the drain terminal is connected to the gate terminal of the transistor 18, which is in turn connected to the two pass transistors 15. The signal HZ is sent to the gate terminal of the transistor 17. The drain terminal of the transistor 20 is connected to the drain terminal of the transistor 18 and its source terminal is connected to the ground. The gate terminal of the transistor 20 is connected to the pair of pass transistors 16. The signal HZ is sent in input to the gate terminals of the N-type transistors of the pairs of pass transistors 15 and 16, whereas the inverted signal HZ is sent in input to the gate terminals of the P-type transistors of the pairs of pass transistors 15 and 16. In the transistor 19, the gate terminal is connected to the output of the inverter 21, the source terminal is connected to the ground, and the drain terminal is connected to the gate terminal of the transistor 20. The signal SA-OUT, in output from the data transit enabling/disabling means 3, is sent in input to the pairs of pass transistors 15 and 16. The tristate structures 8 L and 8 R are furthermore shown in detail in figure 6. In particular, the tristate structure 8 L comprises a pair of transistors 22 L and 23 L of the N-channel type and a pair of transistors 24 L and 25 L of the P-channel type. In the transistor 22 L , the source terminal is connected to the ground, the drain terminal is connected to the source terminal of the transistor 23 L , and the gate terminal receives the signal SA-L. In the transistor 23 L , the gate terminal receives the signal LEFT and the drain terminal is connected to the drain terminal of the transistor 24 L . In the transistor 24 L , the gate terminal receives the signal RIGHT and the source terminal is connected to the drain terminal of the transistor 25 L . In the transistor 25 L , the source terminal is connected to the supply voltage and the gate terminal receives the signal SA-L. The enabling/disabling means 8 R have a structure that is identical to the means 8 L , except for the fact that the transistor 23 R (which matches the transistor 23 L ) receives the signal RIGHT in input at its gate terminal and the transistor 24 R (which matches the transistor 24 L ) receives the signal LEFT in input at its gate terminal. Figure 7 shows in detail a possible circuit for generating the signal HZ for enabling the transmission of data on the internal bus DATA-BUS. Said circuit comprises means 26 for controlling the generation of the signal HZ and a pair of pass transistors that receives in input, at the gate terminal of its N-type transistor, an inverted address transition detection signal ATDn, which is also sent to the gate terminal of a P-channel transistor 28. In the transistor 28, the source terminal is connected to the supply voltage and the drain terminal is connected to the output of the pair of pass transistors 27. The signal ATDn, inverted in an inverter 29, is also sent in input to the gate terminal of the N-type transistor of the pair of pass transistors 27. The output of the pair of pass transistors 27 is sent, together with the signal EQ, through a NOR gate 30, whose output is inverted in an inverter 31 to produce the signal HZ. The chart of figure 8 will be explained in relation to the explanation of the operation of the architecture according to the invention. With reference to the above figures, the operation of the architecture according to the invention is as follows. Instead of the conventional reference columns, whose number matches the number of bits of the word of the memory matrix, the architecture according to the invention uses a single reference line ROW-RIF for each half-matrix, with a consequent reduction in the number of reference lines. In a memory device with words of, for example, 16 bits, conventional architectures in fact provide 16 reference columns, one for each word bit. For the redundancy lines, like the word lines, the reference line is located in the opposite half-plane, and like the word bit, it has its own dedicated sense amplifier, with the same management circuits. The memory matrix, which is divided into two half-matrices, is activated so that the selection of a generic word line of the matrix in one of the two sections associates, in the opposite section, the corresponding reference cell to check the status of the cell involved in the reading operation. Said reference cell is located at the bit line to which the selected memory cell belongs, in the same position with respect to the ground line. Simultaneously, a number of cells equal to the word bits is activated by said reference line ROW-RIF. This organization allows to fully balance the two reading paths that are compared, i.e., the path in the left half-matrix 1 L and the path in the right half-matrix 1 R , including the selection paths and their ohmic parameters, capacitive loads, and signal propagations. These paths are interchangeable. Furthermore, while in the case in which there is a defective memory cell on one of the reference bit lines it is necessary to reject the device since it is impossible to apply redundancy to the reference columns, in the case of the architecture according to the invention this does not occur because redundancy includes the two half-matrix lines and the corresponding reference cells. The redundancy mechanism in fact entails not only the replacement of the defective line but also the replacement of the corresponding reference cell on the reference line ROW-RIF. Therefore, the architecture according to the invention for the memory device allows to avoid rejection of the device due to defective reference bits. The selected reference line ROW-RIF is activated at the end of the pulse of ATD. The propagation lines ROW-PROP, synchronously with the activation of the reference lines ROW-RIF and on their same half-plane (i.e., if the reference line is taken in the left half-plane, the propagation line is also taken in the left half-plane, and vice versa), allow to monitor the propagation of a generic word line of the matrix, because they faithfully reproduce its capacitive loads, its ohmic paths, and the associated delays, so as to assuredly produce the appropriate timings for data reading by the sense amplifier 2. The architecture according to the invention furthermore allows to: select the side which, at that moment, is considered the matrix side, the other side acting as reference; perform synchronization with fundamental timing signals, such as ATD, PC, EQ, and HZ; provide synchronization with transfer of the read data; buffer the data transmission lines. With reference now to figure 1 and more particularly to figures 3-8, the sense amplifier 2 receives in input the signals that arrive from the selection of the bit lines in either of the half-matrices 1 L and 1 R . These signals, designated by L-YMS and R-YMS, are buffered in the sense amplifier to be released with appropriate timings. In particular, the release of the data of the sense amplifier is controlled by the signals LEFT and RIGHT, which indicate the side of the matrix that is involved in the reading operation. The signals LEFT and RIGHT are generated, for example, according to a first embodiment, by the circuit of figure 4, in which if the equalization signal is high (EQ=1), then LEFT and RIGHT are low and no reading occurs since the equalization step has not ended yet. In other words, the nodes of the storage structure of the sense amplifier are still perfectly balanced, and this prevents detection of any difference in value, however small, on the two matrix and reference branches that are connected to the sense amplifier 2. When EQ=0, then: if A-LEFT=1, A-RIGHT=0 → LEFT=1 and RIGHT=0 In these conditions, the tristate structure 8 L of figure 3 is at high impedance, whereas the tristate structure 8 R is at low impedance. In this case, therefore, the data that arrive from the right half-matrix 1 R are allowed to pass. The signal that passes is therefore SA-R and the signal SA-OUT indeed reflects said signal. Also when EQ=0, if: A-LEFT=0, A-RIGHT=1 → RIGHT=1 and LEFT=0, then the signal SA-L passes. At this point, when HZ=0, the transit of the data arriving from the memory matrix over the internal bus DATA-BUS is enabled. When instead HZ=1 the tristate structure 10 is at high impedance thus preventing access to the internal bus DATA-BUS. In this manner, if data reading is not enabled yet, the internal bus DATA-BUS, being disengaged from the sense amplifier 2, remains in an independent condition and can be used for auxiliary purposes, other than the transmission of the reading data of the memory matrix. The signal HZ is generated by the circuit shown in figure 7. This generation is correlated to the presence of the signal ATDn. Indeed, if ATDn is low, the transistor 28 is on, the pair of pass transistors 27 is off, and a high level, equal to the supply voltage, together with the signal EQ, is provided in input to the NOR gate 30. At this point, if the signal EQ is also high, then the output of the NOR gate 30 is low and the signal HZ is therefore high (HZ=1). In this condition, the tristate structure 10 is in a high-impedance condition and access to the internal bus DATA-BUS is denied. Vice versa, if ATDn is high and EQ is low, then HZ=0 and access of the data, represented by SA-OUT, to the internal bus DATA-BUS is permitted. It can be seen, also from the timing chart of figure 8, that access to the internal bus DATA-BUS is enabled only at the end of the equalization step (EQ=0). The generation of the signals LEFT and RIGHT is shown in figures 4 and 5. Figure 4 illustrates a first possible circuit for producing said signals, which selects a matrix side to be read when the equalization signal EQ is zero. If EQ=1, then LEFT and RIGHT are zero, since the data are not yet ready for reading. The circuit of figure 5 instead illustrates the case in which two precharging control points (precharging signals PC-L and PC-R), one for each side of the sense amplifier, are produced. If a single precharging control point is used, then it is sufficient to have a single inverter to invert the precharging signal PC. In the case of two precharging control signals, two NAND gates 14 R and 14 L combined with PCn are necessary. The following cases occur: if PCn=0 → PC-L = PC-R = 1 if PCn=1, A-RIGHT=1, A-LEFT=0 → PC-R=0, PC-L=1; PCn=1, A-RIGHT=0, A-LEFT=1 → PC-R=1, PC-L=0. The timings of these signals are clearly shown in figure 8. In particular, it can be noted that the transmission of the data on the DATA-BUS is timed by the signal HZ=0 and by the signal EQ=0. Let us now consider the case in which a data item is to be read in the left half-matrix 1 L . When the signal EQ becomes high (at a pulse of ATD), and the left side precharging signal PC-L is high, then the signal RIGHT-REF becomes high, i.e., the reference is taken in the right side of the matrix (right half-matrix 1 R ), since a data item must be read in the left half-matrix 1 L . During this step, the signal LEFT becomes low, since the data are not yet ready for reading (they will be when EQ=0). The signal RIGHT is low. Since RIGHT-REF is high, the signal LEFT-REF is low, the signal RIGHT-PROP becomes high, and the signal LEFT-PROP is low. The signal RIGHT-PROP indicates the propagation in the right side of the matrix to match the paths of the left side affected by the reading operation. The signal for precharging the left side PC-L becomes zero before the signal EQ also becomes zero. Then, when the signal EQ and the signal HZ become zero, transmission of the data on the DATA-BUS occurs. The above described steps are generally designated by the reference "a". The reference "b" indicates a similar succession of timings, but for reading the right side of the matrix (half-matrix 1 R ). In practice it has been observed that the architecture according to the invention fully achieves the intended aim, since it allows to provide a memory device in which the capacitive loads of each bit line are perfectly balanced with respect to the corresponding reference line. Furthermore, the number of reference lines is considerably reduced (in the case of a memory with 16-bit words, from sixteen to two). The introduction of lines for reproducing the propagation of a generic word line of the matrix (one propagation line per half-matrix) allows, synchronously with the activation of the reference lines and on the same plane as said reference lines, to control the propagation of a generic word line so as to determine when full propagation occurs on a given word line, in order to produce with certainty the timings for correct data reading. The possibility of applying redundancy to the defective reference bits allows the memory device to be still usable, differently from what occurs with memory devices with conventional architecture that use reference columns instead of the two reference lines according to the invention. The provision of buffering structures allows to transfer the data in an orderly fashion and synchronously with the events, from the memory on an internal bus. The architecture thus conceived is susceptible of numerous modifications and variations, all of which are within the scope of the inventive concept. Thus, for example, the tristate structure 10 can be replaced with a pair of pass transistors. Furthermore, the memory matrix can be divided into an even number, higher than two, of half-matrices without modifying the essential concepts of the invention. Finally, all the details may be replaced with other technically equivalent elements. In practice, the materials employed, so long as they are compatible with the specific use, as well as the dimensions, may be any according to the requirements and the state of the art. Where technical features mentioned in any claim are followed by reference signs, those reference signs have been included for the sole purpose of increasing the intelligibility of the claims and accordingly such reference signs do not have any limiting effect on the interpretation of each element identified by way of example by such reference signs.

Claims: A data reading path management architecture for a memory device, particularly of the non-volatile type, comprising a memory matrix and data sensing means (2) that are adapted to receive in input the data of said memory matrix for reading, said memory matrix being divided into at least two half-matrices (1 l , 1 r ), each one of said two half-matrices having a reference line (ROW-RIF) that is adapted to constitute a reference for reading the other half-matrix, said data sensing means (2) receiving in input the data from one half-matrix and the reference from the other half-matrix, said data sensing means being adapted to transmit, according to a control timing (3,4), the data to an interne bus (DATA-bus) for their transmission in output, characterized in that said sensing means (2) comprises an output branch (SA-L, SA-R) for each of said half-matrices, and that said architecture further comprises logic means (13) for selectively connecting an output branch of said sensing means to said internal bus (DATA-BUS). The architecture according to claim 1, characterized in that said at least two half-matrices comprise a left half-matrix (1 L ) and a right half-matrix (1 R ), said two half-matrices being interchangeable and the reference line being taken in the half-matrix that is opposite to the one in which data reading is performed. The architecture according to claim 1, characterized in that it also comprises, for each one of said at least two half-matrices (1 l , 1 r ), a propagation line (ROW-PROP) that is adapted to reproduce the propagation of a generic word line of said at least two half-matrices, said propagation line being adapted to detect the start timing of a certain reading of said memory matrix. The architecture according to claim 3, characterized in that said propagation line (ROW-PROP) is disconnected from the bit lines of each one of said at least two memory half-matrices (1 L , 1 R ). The architecture according to claim 1, characterized in that said data sensing means (2) comprise sense amplifiers. The architecture according to claim 1, characterized in that it comprises logic means (13) for selecting the outputs of said sense amplifiers, said logic means being adapted to select one of said at least two half-matrices (1 L , 1 R ) for reading on the part of said sensing means. The architecture according to claim 1, characterized in that it comprises means (4) for enabling/disabling the transit of said data of said of at least two memory half- matrices in output to said data sensing means (2). The architecture according to claim 1, characterized in that it comprises means for generating a signal (HZ) for enabling/disabling access to said internal bus on the part of the data of said at least two memory half-matrices. The architecture according to claim 1, characterized in that each one of said at least two memory half-matrices comprises redundancy lines. The architecture according to claim 3, characterized in that for said redundancy lines of each one of said at least two memory half-matrices there are data sensing means, a reference line, and a propagation reproduction line, said data sensing means, said propagation reproduction line (ROW-PROP), and said reference line being identical to the similar structures for the generic word lines of said memory half-matrices. The architecture according to claim 10, characterized in that said data sensing means (2) of said redundancy lines are adapted to transmit the data of the redundancy lines on said internal bus (DATA-BUS) for their transmission in output. The architecture according to claim 1, characterized in that each one of said at least two memory half-matrices comprises a line and a column of the one-time programmable type. The architecture according to claim 1, characterized in that each one of said at least two memory half-matrices (1 L , 1 R ) comprises means (YM, YN) for selecting bit lines (50). The architecture according to claim 1, characterized in that said at least two half-matrices (1 L , 1 R ) are divided into a plurality of half-matrix subsections that are driven by hierarchical decoding means. The architecture according to claim 1, characterized in that said data sensing means (2) are driven by control signals. The architecture according to claim 6, characterized in that said logic means (13) for selecting the outputs of said data sensing means (2) are driven by precharging control signals, one for each side of said sensing means. The architecture according to claim 7, characterized in that said means (4) for enabling/disabling the transit of the data of said at least two half-matrices in output to said data sensing means comprise tristate structures. The architecture according to claim 1, characterized in that said means (3) for enabling/disabling access to said internal bus on the part of the data of said at least two memory half-matrices (1 L 1 R ) comprise a tristate structure (8 L , 8 R ) that is driven by a signal for enabling/disabling access to said internal bus. The architecture according to claim 1, characterized in that said means (3) for enabling/disabling access to said internal bus (DATA-BUS) on the part of the data of said at least two memory half-matrices comprise a pair of pass transistors driven by a signal for enabling/disabling access to said internal bus. The architecture according to claim 8, characterized in that said means for generating said signal (HZ) for enabling/disabling access to the internal bus by the data of said at least two memory half-matrices are driven by a read address transition signal (ATD) and by an equalization signal (EQ). The architecture according to claim 1, characterized in that the number of said data sensing means (2) is equal to the number of word bits of the word lines of said at least two memory half-matrices (1 L, 1 R ). A method for reading a memory device, particularly of the non-volatile type, having at least two memory half-matrices (1 L , 1 R ), comprising the steps of: providing data sensing means having an output branch for each of said memory half-matrices; as a consequence of a pulsed read address transition signal (ATD), precharging the two output branches of data sensing means (2) to their operating level and equalizing said two output branches, thereby holding the data output from said memory in said data sensing means; producing a signal (HZ) for disabling access to an internal bus (DATA-BUS) for the transmission of the data held in said sensing means; releasing the equalization of said two output branches of the data sensing means (2) to allow output of the data held in said sensing means; and enabling the access of said data to said internal bus (DATA-BUS), through the interposition of means for enabling/disabling access to said bus, adapted to uncouple said data sensing means from said internal bus when data reading is not enabled yet. for the transmission of said data for output. The method according to claim 22, characterized in that said step of precharging the branches of data sensing means (2) and in equalizing said branches includes the precharging of one of said branches of the data sensing means (2) that corresponds to the memory half-matrix that is opposite to the one involved in the reading operation. The method according to claim 22, characterized in that said precharging and equalization step comprises the additional step of activating a reference line in the memory half-matrix (1 L , 1 R ) that is opposite to the one involved in the reading operation. The method according to claim 22, characterized in that said precharging and equalization step comprises the additional step of activating a propagation line (ROW-PROP) in the memory half-matrix (1 L , 1 R ) that is opposite to the one involved in the reading operation, said propagation line being adapted to match the propagation of a normal word line of said memory device, so as to give a certain indication of the end of the propagation of the signals in order to perform correct data reading.

Inventors: PASCUCCI LUIGI, PASCUCCI, LUIGI
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1996
Main classification: G11C5
IPC codes: G11C16, G11C5