Control circuit of an output buffer, particularly for a non-volatile memory device

Abstract: The invention relates to a control circuit (1) for an output buffer, of the type which comprises a first input terminal (I1) receiving a first enable signal (OEn) and a second input terminal (I2) receiving a second enable signal (CEn), as well as first (O1) and second (O2) output terminals to generate first (OE_L) and second (OE_H) partial enable signals to transfer discrete sets of data bits, the first (I1) and second (I2) input terminals being coupled to the first (O1) and second (O2) output terminals through a multiplexer (2), the control circuit (1) comprising a synchronization circuit (7) for linking the partial enable signals (OE_L,OE_H) operatively to a synchronization signal (SYNC) of the pulse type being synchronous with the loading of the output buffer, the synchronization circuit (7) being connected between an output terminal (O3) of said multiplexer (2) and the first (O1) and second (O2) output terminals of the control circuit (1).

Description: Field of the Invention This invention relates to a control circuit of an output buffer. More particularly, the invention relates to a control circuit of an output buffer, of the type which comprises a first input terminal receiving a first enable signal and a second input terminal receiving a second enable signal, as well as first and second output terminals to generate first and second partial enable signals to transfer discrete sets of data bits, said first and second input terminals being coupled to said first and second output terminals through a multiplexer. The invention is particularly, but not exclusively, concerned with a control circuit of an output buffer for a non-volatile memory device, and the description to follow will make reference to such an application for convenience of illustration only. Prior Art As is well known, non-volatile memory devices include two basic control terminals which receive a first enable signal, conventionally designated CE, and a second enable signal, designated OE. In particular, the first signal CE enables the memory device operation, while the second signal OE enables its communication to internal or external circuitry. The enable signals, CE and OE, are utilized, for example, to control output lines of memory devices through output buffers which are in a "tristate" condition, that is a high impedance condition, regulated by the signal OE. In particular, the enable signals CE and OE are applied to such output buffers by specially provided control circuits. As the enable signal OE assumes a low logic level, or 0 level, the control circuit drives the output buffer to the high impedance condition, thereby enabling the communication of external logics to internal circuitry of the memory device. Likewise, as the enable signal OE assumes a high logic level, or 1 level, the control circuit enables the output buffer to transmit to the outside of the memory device data stored in the inside. The signal CE sets an operation interval of the memory device, for example to read data which is transferred to the output lines only during the checking of programmed data for correctness, in the course of a programming phase. Thus, the signal CE functions as a signal enabling the checking of programmed data. Shown schematically in Figure 1 is a control circuit 1' of an output buffer according to the prior art. The control circuit 1' includes first I1' and second I2' input terminals, as well as first O1' and second 02' output terminals. In particular, the first input terminal I1' receives the first enable signal OE', actually its negation OEn', and the second input terminal I2' receives the second enable signal CE', actually its negation CEn'. The first input terminal I1' is further coupled to a first input terminal I3' of a multiplexer 2' through a first logic gate 3'. Likewise, the second input terminal I2' is coupled to a second input terminal I4' of the multiplexer 2', through a second logic gate 4'. The multiplexer 2' has a further input terminal I5' receiving a control signal PG'. The multiplexer 2' also has an output terminal O3' which is coupled to both the first O1' and the second O2' output terminals of the control circuit 1', through respective logic circuits. In particular, first 5' and second 6' logic circuits are provided. The multiplexer 2' will choose between the first OE' and the second CE' enable signal according to the condition of operation of the memory device, that is, it will output the first enable signal OE' while reading of the memory device, the second enable signal CE' being only output during the memory device programming phase to enable the checking during the programming phase. The first logic circuit 5' comprises substantially first IN1' and second IN2' logic inverters connected in series with each other between the output terminal O3' of the multiplexer 2' and the first output terminal O1' of the control circuit 1'. The second logic circuit 6' similarly comprises a first logic gate PL1' with two inputs and of a third logic inverter IN3', connected in series with each other between the output terminal O3' of the multiplexer 2' and the second output terminal O2' of the control circuit 1'. In addition, said first logic gate PL1' receives a control signal WORD' at an input terminal I6'. The first O1' and second 02' output terminals of the control circuit 1 supply first OE_L' and second OE_H' partial enable signals which are advantageously utilized to control the transfer of discrete sets of bits. However, the enabling of the read data transfer to the output, as provided by either enable signals OE' and CE', has a response time which is shorter than the propagation time required to complete the reading, from the time the memory is activated, which results in a first random switching of the output stages followed by a second reading, now a consistent one with the memory contents. Thus, it would be desirable to have, at a first reading event, the activation of the output buffers delayed, such that the switchings of the output signals cannot perturbate the real data read-out process with unreliable switchings. In fact, the sensitiveness to this undesired phenomenon is the higher the more parallel is the data. Hence the need to have a synchronized enabling for the first read cycle as to avoid penalties in terms of time. Once the first read cycle is synchronized, no further checking is necessary while the enable signal OE' is at the 0 level. The underlying technical problem of the present invention is to provide a control circuit of an output buffer, in particular for a non-volatile memory device, which has such structural and functional features as to allow the delaying of just the first switching of the memory device output lines at the end of a true reading interval, thereby overcoming the drawbacks with which prior art devices are beset. Summary of the Invention The idea of solution on which the present invention is based is to make the enabling of the output buffers to transmit read data dependent on a "first reading event", regardless of the generation of an enable signal. On the grounds of this idea of solution, the technical problem is solved by a control circuit for an output buffer as indicated above and defined by the characterizing portion of Claim 1. The features and advantages of the control circuit according to the invention will be apparent from the following description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings. Brief Description of the Drawings In the drawings: Figure 1 shows schematically a control circuit for an output buffer, according to the prior art; Figure 2 shows schematically a control circuit for an output buffer, according to the invention; Figure 3 shows schematically an improved embodiment of a control circuit of an output buffer, according to the invention; Figure 4 shows in greater detail the structure of the control circuit according to the embodiment of Figure 3; Figure 5 shows waveforms on a common time base which illustrate the behavior of signals present in the circuit of Figure 4 over time. Detailed Description Referring to the drawing figures, generally and schematically shown at 1 is a control circuit for an output buffer, according to this invention. The control circuit 1 includes first I1 and second I2 input terminals, and first O1 and second O2 output terminals. In particular, the first input terminal I1 receives a first enable signal OE, actually its negation OEn, and the second input terminal I2 receives the second enable signal CE, actually its negation CEn. The circuit parts denoted by 2, 3 and 4 fully correspond to the circuit parts 2', 3' and 4' previously described with reference to Figure 1 and the prior art control circuit 1'. In particular, the multiplexer 2 has a first input terminal I3 receiving the first enable signal OE through a first logic gate 3, a second input terminal I4 receiving the second enable signal CE through a second logic gate 4, and a further input terminal I5 receiving a control signal PG. The multiplexer 2 also has an output terminal O3 coupled to the first O1 and second O2 output terminals of the control circuit 1 through respective first 5 and second 6 logic circuits and a synchronization circuit 7. In the example shown in Figure 2, the first logic circuit 5 comprises a first logic gate PL1 with two inputs, and a first logic inverter IN1, connected in series with each other between the output terminal O3 of the multiplexer 2 and the first output terminal O1 of the control circuit 1. Likewise, the second logic circuit 6 comprises a second logic gate PL2 with three inputs, and a second logic inverter IN2, connected in series with each other between the output terminal O3 of the multiplexer 2 and the second output terminal O2 of the control circuit 1. In addition, said second logic gate PL2 receives a control signal WORD at another input terminal I6. The first PL1 and second PL2 logic gates have respective first I7 and second I8 input terminals in common. The second terminals I8 also receive the first enable signal OE. In the embodiment shown in Figure 2, the logic gates PL1 and PL2 are of the NAND type. In addition, the first O1 and second O2 output terminals of the control circuit 1 according to the invention supply first OE_L and second OE_H partial enable signals which are used to control the transfer of discrete sets of bits. Advantageously according to the invention, the control circuit 1 also includes the synchronization circuit 7, connected to the output terminal O3 of the multiplexer 2 through a logic inverter IN3 and to the first common input terminal I7 of the logic circuits 5 and 6. More particularly, the synchronization circuit 7 has a first input terminal I9 which is connected to the logic inverter IN3 and receives a disable signal DIS. The synchronization circuit 7 also has a second input terminal I10 receiving a synchronization signal SYNC. The circuit 7 has, moreover, an output terminal O4 for supplying a synchronized enable signal SYNC_OE of the pulse type. In the embodiment shown in Figure 2, the synchronization circuit 7 simply comprises a flip-flop of the SET-RESET type. The operation of the control circuit 1 according to the invention will now be described. The synchronization circuit 7 allows the partial enable signals OE_L and OE_H to be generated only on completion of a reading event. The synchronization signal SYNC indicates the simultaneous loading of data into the output buffers. In fact, the synchronized enable signal SYNC_OE goes to a high logic level, or 1 level, only upon the synchronization signal SYNC going to a 1 level, indicating the loading of data into the output buffers, thereby delaying the switching of the memory device outputs on completion of the reading, even when the enable signal OE has already been produced. It should be noted that the enable signal OE drives, to a low logic level or 0 level, the synchronization signal DIS, with no effects on propagation. On the other hand, as the enable signal OE goes to a 1 level, the synchronization signal DIS goes to a 0 level, thereby disabling the generation of the partial enable signals OE_L and OE_H and functioning, therefore, as a reset signal for the flip-flop 7. However, disturbation tied to possible bouncing of the enable signal OE requires to be filtered out, which disturbation would cause disabling of the partial enable signals OE_L and OE_H and a stepped signal pattern. In the presence of the synchronization signal SYNC, the pattern sought for the output signal OUT is that shown in Figure 5. Also, the disable pulse DIS should only be produced with the system disabled. Actually, the switching of the output lines may cause undesired pulses to appear in the pattern of the enable signals OE/CE which cause, in turn, incorrect pulses in the disable signal DIS. These incorrect pulses are shown by dash lines in Figure 5. In the presence of such incorrect pulses of the disable signal DIS, the synchronized enable signal SYNC_OE goes to ground erroneously, causing the whole system to become disabled, through the partial enable signals OE_L and OE_H which are blocking the output buffers. To obviate this drawback, in this invention, a delay circuit has been purposely provided for the disable signal DIS. This delay circuit is incorporated to a modified embodiment of the inventive control circuit shown schematically in Figure 3. In particular, generally shown at 10 is a control circuit with an asymmetrical delay circuit 8 connected between the multiplexer 2 and the synchronization circuit 7. The delay circuit 8, shown in detail in Figure 4, is connected between a first supply voltage reference Vdd and a second voltage reference, in particular a signal ground GND, and connected to the output terminal O3 of the multiplexer 2 and to the input terminal I9 of the synchronization circuit 7. In addition, the delay circuit 8 has a control terminal I11 receiving a reference signal PCH_Icost and an output terminal 05 supplying a controlled disable signal DIS1 through the delay circuit 8. For proper operation of the control circuit 10 according to this modification, the delay circuit 8 should include an asymmetrical delay network, having a significant delay from a first edge of the enable signal OE and immediate natural propagation at a second edge of that signal. More particularly, the delay circuit 8 comprises a charge control transistor P1 having a source terminal connected, through a first enable transistor P2, to the supply voltage reference Vdd, and a drain terminal connected to the ground GND through a parallel of a second enable transistor N1 and a delay capacitor C1. The charge control transistor P1 also has a gate terminal connected to the control terminal I11, while the enable transistors P2 and N1 have their gate terminals connected to the output terminal O3 of the multiplexer 2. The reference signal PCH_Icost cannot control, independently from the power supply, the conductivity of P1 such that the charging of the capacitor C1 can take place in a constant manner independently from the power supply. In particular, the charge control transistor P1 and the first enable transistor P2 are P-channel MOS transistors, whereas the second enable transistor N1 is an N-channel MOS transistor. The delay capacitor C1 is also connected to the input of a logic inverter IN4 which has its output connected to one input of a logic gate PL3, in particular a gate of the NOR type, having another input connected to the output terminal O3 of the multiplexer 2, and supplying the controlled disable signal DIS1 at its output terminal O5. In this way, as the enable signal OE goes to a 1 level, the controlled disable signal DIS1 immediately goes to the 1 level, thereby allowing the enable signal OE to be propagated. On the other hand, as the enable signal OE goes to a 0 level, the controlled disable signal DIS1 goes to a 0 level only after the delay capacitor C1 is discharged. In fact, in the presence of a first edge, in particular a raising edge of the enable signal OE, the controlled disable signal DIS1 immediately (or rather, after a trivial delay due to the switching of the logical elements included in the delay circuit 8) goes to a low logic level, or 0 level. Likewise, in the presence of a second edge, in particular a falling edge of the enable signal OE, the controlled disable signal DIS1 retains its 0 level until a charge current Icost, passing through the delay capacitor C1, brings the input of the logic inverter IN4 to a 1 level, and hence, the input of the logic gate PL3 to a 0 level, thus causing the output terminal O5 of the delay circuit 8 to go to a 1 level, and resetting the flip-flop 7. The switching of the controlled disable signal DIS1 at the falling edge of the enable signal OE occurs with a delay Δt which allows the data reading cycle of the memory device to be completed. Advantageously according to the invention, this delay is proportional to the charge current Icost of the delay capacitor C1 and is, therefore, independent from the supply voltage Vdd. The control circuit 10 with delay circuit 8 according to the invention is of special advantage at high voltage levels, when the presence of high levels of noise disallows the use of known delay circuits for which the delay is proportional to the supply voltage. Accordingly, to obtain a sufficiently delayed propagation to allow the use of such known delay circuits, at high levels of the supply voltage, it would be necessary to increase the basic delays provided thereby; however, this would entail unacceptable delays at lower voltage levels. The operation of the delay circuit 8 incorporated to the control circuit 10 of this invention involves the use of a constant current generator capable of delivering a regulating signal PCH_Icost substantially constant with respect to the supply voltage Vdd. To summarize, the control circuit 10 with delay circuit 8 according to this invention has immediate reaction features to the occurrence of a first reading cycle, and exhibits a delayed action from the disabling operation, thereby providing a filter action in the respect of pulses of noisy origin. In addition, by using a circuit with a delay which unvaries with respect to the supply voltage Vdd, the natural synchronized configuration in the various first read cycles, otherwise too slow for establishing at low voltages, can be promptly restored. In this way, the structures of the output buffers of memory devices operating at high voltages and equipped with this control circuit with delay can be safely increased in size to provide faster switchings, and accordingly, increased speed for the devices in their entirety. Finally, the control circuit 1 and 10 of this invention can be used to synchronize the second enable signal CE, supplying it at the second common input terminal I8 of the logic circuits 5 and 6.

Claims: A control circuit (1) for an output buffer, of the type which comprises a first input terminal (I1) receiving a first enable signal (OEn) and a second input terminal (I2) receiving a second enable signal (CEn), as well as first (O1) and second (O2) output terminals to generate first (OE_L) and second (OE_H) partial enable signals to transfer discrete sets of data bits, said first (I1) and second (I2) input terminals being coupled to said first (O1) and second (O2) output terminals through a multiplexer (2), characterized in that it comprises a synchronization circuit (7) for linking the partial enable signals (OE_L,OE_H) operatively to a synchronization signal (SYNC) of the pulse type being synchronous with the loading of the output buffer, said synchronization circuit (7) being connected between an output terminal (03) of said multiplexer (2) and the first (O1) and second (O2) output terminals of the control circuit (1). A control circuit (1) according to Claim 1, characterized in that the synchronization circuit (7) has a first input terminal (I10) receiving the synchronization signal (SYNC) and a second input terminal (I9), connected to the output terminal (O3) of the multiplexer (2), receiving a disable signal (DIS). A control circuit (10) according to Claim 2, characterized in that it comprises a delay circuit (8) connected between a first (Vdd) and a second (GND) voltage reference, and connected to the output terminal (03) of the multiplexer (2) and to the second input terminal (I9) of the synchronization circuit (7), said delay circuit (8) having a control terminal (I11) receiving a reference signal (PCH_Icost) and an output terminal (O5) supplying the disable signal (DIS1). A control circuit (10) according to Claim 3, characterized in that the delay circuit (8) comprises an asymmetrical delay network having a significant delay from a first edge of an enable signal (OE/CE) and immediate natural propagation at a second edge of said signal. A control circuit (1) according to Claim 2, characterized in that the synchronization circuit (7) has an output terminal (O4) supplying a synchronized enable signal (SYNC_OE) to respective first common input terminals (I7) of first (5) and second (6) logic circuits being in turn connected to the first (O1) and the second (O2) output terminal of the control circuit (1). A control circuit (1) according to Claim 5, characterized in that the first (5) and second (6) logic circuits have further second common input terminals (I8) connected to an enable signal (OE/CE). A control circuit (10) according to Claim 4, characterized in that the asymmetrical delay network (8), being connected between a first (Vdd) and a second (GND) voltage reference and having an input terminal (I11) receiving a regulating signal (PCH_Icost), comprises at least a charge control transistor (P1) and a delay capacitor (C1) connected in series with each other between the first (Vdd) and second (GND) voltage references, said charge control transistor (P1) having a control terminal connected to the input terminal (I11), the asymmetrical delay network (8) having an output terminal (O5) supplying a controlled disable signal (DIS1) synchronized to a first edge of the enable signal (OE/CN). A control circuit (10) according to Claim 7, characterized in that the controlled disable signal (DIS1) switches from the first edge of the enable signal (OE/CN) with a delay (Δt) which is proportional to a charge or discharge time of the delay capacitor (C1) and substantially independent from the first voltage reference (Vdd), said signal also switching with no or trivial delay from a second edge of the enable signal (OE/CN). A control circuit (1) according to Claim 1, characterized in that said synchronization circuit (7) comprises essentially a flip-flop of the SET-RESET type. A control circuit (10) according to Claim 7, characterized in that the delay capacitor (C1) is connected to the output terminal (O5) by way of a series of first (IN4) and second (PL3) logic gates, said second logic gate (PL3) having an input terminal connected to the output terminal (03) of the multiplexer (2). A control circuit (10) according to Claim 7, characterized in that it comprises first (P2) and second (N1) enable transistors, connected between the charge control transistor (P1) and the first (Vdd) and second (GND) voltage references, respectively, having a control terminal connected to the input terminal (I11) of the asymmetrical delay network (8). A control circuit (1) according to Claim 5, characterized in that the first (5) and second (6) logic circuits respectively comprise first (PL1,PL2) and second (IN1,IN2) logic gates connected in series with each other between the common input terminals (I7,I8) and the first (O1) and second (O2) output terminals of the control circuit (1). A control circuit (1) according to Claim 12, characterized in that said first logic gate (PL2) of the logic circuit (6) receives a control signal (WORD) at an input terminal (I6). A control circuit (1) according to Claim 1, characterized in that it comprises a logic gate (IN3) connected between the output terminal (O3) of the multiplexer (2) and the first (O1) and second (O2) output terminals of the control circuit (1). A method for a synchronous loading of data into an output buffer comprising a control circuit (1) receiving first (OEn) and second (CEn) enable signals and generating first (OE_L) and second (OE_H) partial enable signals to transfer data in discrete sets of bits, characterized in that it provides for the use of a synchronization signal (SYNC) of the pulse type which is synchronous with the output buffer loading and generated by a synchronization circuit (7) to control the partial enable signals (OE_L,OE_H). A synchronous data loading method according to Claim 15, characterized in that it provides a delay circuit (8), connected to said synchronization circuit (7), comprising an asymmetrical delay network which features an immediate reaction to the occurrence of a first data reading cycle and a delayed action with respect to a synchronization circuit (7) disabling operation, thereby producing a filtering action in the respect of pulses of noisy origin.

Inventors: PASCUCCI LUIGI, PASCUCCI, LUIGI
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1996
Main classification: G11C7
IPC codes: G11C7