METHOD AND APPARATUS FOR DE-INTERLACING VIDEO FIELDS TO PROGRESSIVE SCAN VIDEO FRAMES

Abstract: A method and apparatus are provided for converting interlaced video fields of arbitrary size to progressive scan format video frames of arbitrary size. The method and apparatus of the invention provide consistent conversion quality even while output video dimensions are scaled in real-time. According to a first aspect of the invention the space between output lines is calculated with respect to the input fields. According to a second aspect, the output line spacing information is used to calculate the final line positions in a progressive scan output frame.

Description: METHOD AND APPARATUS FOR DE-INTERLACING VIDEO FIELDS TO PROGRESSIVE SCAN VIDEO FRAMES BACKGROUND OF THE INVENTION Field of the Invention This invention relates in general to video signal de- interlacing and interpolation. More particularly, the invention relates to a method and apparatus for properly interpolating and spatially positioning video lines from an arbitrarily sized video field to create an arbitrarily resized progressive scan frame. Description of the Prior Art Current state-of-the-art de-interlacing involves converting an interlaced scanned video signal into a progressive scan (sometimes referred to as sequentially scanned) video signal with exactly double or quadruple the number of output lines. The output size restriction makes it very difficult and expensive to de-interlace video fields for use in an application that requires an arbitrarily sized output progressive scan video window. The original video signal is composed of interlaced scanned odd and even fields . These fields are mapped into progressive scan frames through a process of spatial interpolation and positioning that produces exactly double or quadruple the number of input lines per field. De-interlacing has many applications including slow motion playback, computer video-in-a-window displays and large screen projection television systems to name but a few. All of these applications require the high quality and performance provided by the generation of progressive scan frames using a de-interlacing process. Producing high quality de-interlaced video signals is difficult. An object in one video field may be in a different spatial position in the next field which makes it very difficult to properly combined the fields into a single progressive scan frame. In such an application, advanced and expensive methods of temporal and vertical interpolation are required to give satisfactory results. One common prior art method of interpolation uses motion detector circuitry to identify areas of a video field which change over time. These changing areas are interpolated differently from static regions to ensure a high quality image. The complexity and expense of motion detector circuitry and advanced interpolation circuitry restricts the flexibility and affordability of such prior art de- interlacing systems. These systems have been highly optimized to produce either double or quadruple the number of input lines per field, as discussed above. Examples of well known prior art de-interlacing systems are described in the following publications and patents: Publications Watkinson, John, "The Art of DIGITAL VIDEO - 2nd Edition", Focal Press 1994, pp. 180-185. U.S. Patent Documents 5,291,280 3/1994 Faroudja; Yves C. 5,070,403 12/1994 Wilkinson, Basingstoke Summary of the Invention A general aspect of an object of the present invention is to provide a method and apparatus for creating arbitrarily sized output progressive scan frames of video from arbitrarily sized input interlaced video fields in a manner which overcomes the limitations and drawbacks of the prior art . The method and apparatus of the present invention de- interlaces video by properly interpolating and spatially positioning each input field line at the correct output progressive scan line position based on the relative size of the input and output video frames. The process of the invention is broken down into two steps. The first step involves calculating the space between output progressive scan lines and then using this information to determine the correct spatial position of these lines. Once the position of the output lines is calculated, an image resizing engine is used to map the input lines to the appropriate output spatial position and store these lines in an external frame buffer. This two-step process continuously calculates output line positions to provide proper de-interlacing for dynamically resized video signals. Brief Description of Drawings Figure 1 is a schematic representation of a plurality of target lines derived from a plurality of source lines in magnification mode, wherein the number of lines in the input fields is increased to map to the number of the lines in the output frames; Figure 2 is a schematic representation of a plurality of target lines derived from a plurality of source lines in bypass mode, wherein the number of lines in the input fields is equal to the number of lines in the output frames; Figure 3 is a schematic representation of target lines derived from a plurality of source lines in reduction mode, wherein the number of lines in the input fields is decreased to map to the number of lines in the output frames; Figures 4 and 5 are schematic representations showing details of even field resizing and odd field resizing, respectively, for the de-interlacing system of the preferred embodiment; Figure 6 is a block diagram showing the functional components of a first aspect of the de-interlacing system according to the preferred embodiment for calculating a Target Increment (Tarlnc) value; Figure 7 is a block diagram showing the functional components of a second aspect of the de-interlacing system that uses the Tarlnc value to generate a correct Target Line Spacing; Figure 8 is a flow chart showing operation of the de- interlacing system shown in Figures 6 and 7; and Figure 9 is a memory map diagram showing the placement of the output lines in an external output frame store, according to the preferred embodiment . Detailed Description of the Preferred Embodiment As discussed above, video de-interlacing is achieved in accordance with the present invention by continuously calculating the spatial position of the output lines and then mapping interlaced input fields to progressive scan output frames. Figures 1, 2 and 3 each show two input fields (not to scale) which are referred to as the Even Input Field (lines YO, Y2, Y4, Y6) and the Odd Input Field (lines Yl, Y3, Y5, Y7) , and two output frames referred to as the Even Output Frame and the Odd Output Frame. All even input fields are mapped to even output frames and the odd input fields are mapped to the odd output frames. The variables in each of these figures is explained in Table A, below: TABLE A Variable Name Description A Space between input interlaced video lines W Space between lines in the even or odd input fields B Space between lines in the even or odd output frames S The number of lines in each input field T The number of lines in each output frame According to the present invention, the following relationship is implemented for determining the space between output lines with respect to the interlaced input lines: Tarlnc -= B = (2*S-1) / (2* (T-1) ) (1-1) The actual spatial position of the output lines depends on whether the input field is even or odd. An even input field has lines positioned in the even line spaces and an odd input field has lines positioned in the odd line spaces. The following relationship is implemented for determining the spatial position of the output lines: P^P-^+Tarlnc, j=l..T-l (1-2) where P -i0 =0 for Even Input Fields P -=0 =-0.5 for Odd Input Fields Magnification Mode Figure 1 shows a single input interlaced video frame containing a total of 8 lines numbered 0 to 7. In actual fact, standard interlaced video frames contain even and odd fields each having 240 active lines, for a total of 480 lines per frame. A reduced number of lines are depicted for ease of illustration. The even lines YO, Y2, Y4 and Yβ are stored in the even field and the odd lines Yl, Y3, Y5 and Y7 are stored in the odd field. Each de-interlaced output frame contains a total of 8 lines numbered 0 through 7. To map each input field (4 lines) to each output frame (8 lines) requires a magnification of 2 times. It is important to note that only the first line of the even field (Y0) maps to the first line of the even output frame (F0) and the last line of the odd field (Y7) maps to the last line of the odd output frame (F7) . The remaining input lines are mapped to a fractional position with respect to the output frames. The method and apparatus of the present invention correctly calculates the output line position depending on the user specified resize factor, as shown in greater detail with reference to Figures 4 and 5. Since all of the even and odd field lines are equally spaced (e.g. A=l; S=4 and T=8 in the example of Figures 4 and 5) by mapping the input even field to the output even frame, then A* (2*S-1)=B* (T-1) (2-1) , and , by positioning the input odd field lines between the input even field lines, then A=1/2*W (2-2) . Substituting (2-2) into (2-1) and solving for B: B=( (2*S-l)*W)/(2* (T-1) ) (2-3) =0.5W The variable B is now equal to the space between output lines with respect to the interlaced input lines. According to the next step in the method of the present invention, the proper spatial location of each output line is determined using 1-2, resulting in the spatial locations set forth in Tables B and C, for the even output frame (Figure 4) and the odd output frame (Figure 5) , respectively. Table B Output Line Number Spatial Location (1-2) FO D =o=0 Fl P 3-ll =0.5W F2 P. =2 =1.0W F3 P D . 3 =1.5W F4 Pj=4=2.0W F5 P.- 5 =2.5W F6 P D . 6 =3.0W F7 P-_ 7 =3.5W Table C Output Line Number Spatial Location (1-2) FO P-. 0 =-0.5W Fl P =0W F2 P-_ 2 =0 . 5W F3 P D . 3 =1 . 0W F4 P-_ 4 =1 . 5W F5 P-. 5 =2 . OW F6 P 3 . 6 =2 . 5 F7 P-. 7 =3 . OW The methodology discussed above with respect to magnification mode, can be used for both bypass and reduction modes. Bypass Mode Since all of the even and odd field lines are equally spaced (e.g. A=l; S=4 and T=4 from Figure 2) , by mapping the input even field to the output even frame, then A* (2*S-1)=B* (T-1) (2-1), and by positioning the input odd field lines between the input even field lines, then A=1/2*W (2-2) substituting (2-2) into (2-1) and solving for B: B=( (2*S-1)*W/ (2* (T-1) ) =7/6W According to the next step in the method of the present invention, the proper spatial location of each output line is determined using 1-2, resulting in the spatial locations set forth in Tables D and E for the even output frame and the odd output frame, respectively. Table D Output Line Number Spatial Location (1-2) FO P.- o =0 Fl P.. 0 =1.166(7/6)W F2 P-. 2 =:2.33 (14/6)W F3 P j , 3 =3.5(2l/6)W Table E Output Line Number Spatial Location (1-2) FO P 3 . 0 =-0.5W Fl P 3=1 =0.667 (7/6-0.5)W F2 P 3=2 =1.833 (14/6-0.5)W F3 P j . 3 =3.0(21/6-0.5)W Reduction Mode Since all of the even and odd field lines are equally spaced (e.g. A=l; S=4 and T=3 from Figure 3) , by mapping the input even field to the output even frame, then A*(2*S-1)=B* (T-1) (2-1), and by positioning the input odd field lines between the input even field lines, then A=1/2*W (2-2) Substituting 2-2 into (2-1) and solving for B B=( (2*S-l)*W)/(2*(t-l) ) (2-3) = 7/4W According to the next step in the method of the present invention, the proper spatial location of each output line is determined using 1-2, resulting in the spatial locations set forth in Tables F and G for the even output frame and the add output frame, respectively. Table F Output Line Number Spatial Location (1-2) F0 P , _ o =0 Fl P 3 . 1 =1.75(7/4)W F2 P j->2 =3.5(14/4)W Table G Output Line Number Spatial Location (Equation 1-2) FO P j= o=~0.5 Fl P j=1 =l.25(7/4-0.5)W F2 P 3=2 =3.0(14/4-0.5)W Figure 6 depicts a hardware embodiment for executing the process set forth in 1-1. The number of source field lines (S) is multiplied by 2 using a first multiplier 61, and then 1 is subtracted from the product using a first subtractor 63. The value 1 is subtracted from the number of target frame lines using a second subtractor 65, and the sum is multiplied by 2 using a second multiplier 67. The output of subtractor 63 is divided by the output of multiplier 67 using a divider 69, to produce the Output Target Increment (Tarlnc) value. Figure 7 depicts a hardware embodiment for executing the process set forth in 1-2. An accumulator is formed by the combination of register 71 and adder 73 with multiplexer 75 controlling the initial value. As the data from an even field is loaded into image resizing engine 77, the MuxSelect signal ensures that the value 0 is multiplexed into register 71 to initialize the accumulator to zero. As each new input line is loaded into the image resizing engine 77, the value of Tarlnc is accumulated to produce the target line spacing value required for an even output frame. When data from an odd field is loaded into the image resizing engine 77, the MuxSelect signal ensures that the value -0.5 is multiplexed into register 71 to initialize the accumulator. This ensures that all target line spacing values produced for an output frame are properly positioned. The Clk signal is used to synchronize all data movement in accordance with standard digital system design. Figure 8 depicts a flow chart illustrating the control system for the hardware embodiment of Figures 6 and 7. After the system is initialized (step 80) , a Tarlnc value is calculated (step 82) , as discussed in greater detail above. If the apparatus is processing an even field (step 803) , the MuxSelect signal loads a 0 value into register 71 (step 804) and then loads the Target Line Spacing to the Image Resizing Engine 77 (step 806) . If more lines must be processed (i.e. a NO decision at step 808) , Adder 73 adds Tarlnc and Target Line Spacing from register 71 (step 810) . MuxSelect now selects input A of multiplexer 75 (step 812) and the new Target Line Spacing is fed to the Image Resizing Engine (step 808) . The odd field is processed the same way with respect to steps 803 and 814- 822, except that an initial starting value of -0.5 is loaded in register 71 (step 814) . After both the event and odd fields have been processed, (step 824) , then the system waits to process the next pair of input video fields relative to the next calculated Target-Line spacing. Output frame lines must be stored at different locations in an external frame buffer. Figure 8 shows storage of video lines from the output even frame starting at the top of the frame buffer. Lines from the output odd frame are stored in such a way that the last line is at the bottom of the frame buffer. These different storage requirements greatly simplify the top and bottom boundary conditions encountered while spatially positioning the output. All of the hardware components depicted in Figures 6 and 7, and the frame buffer whose operation is discussed in Figure 9, are of well known design. The image r esizing engine is preferably as set forth in U.S. patent application 125,530 filed September 22, 1993, the contents of which are incorporated herein by reference. According to an alternative embodiment of the present invention, the steps of calculating the output target increment and output line spacing as set forth in the hardware embodiment of Figures 6 and 7, with reference to Figure 8, may be implemented by a computer implementing appropriate software such as set forth in Appendix A to the present disclosure. Other embodiments and variations of the invention are possible. For example, rather than having an integer number of lines per field or per frame, the apparatus of the present invention will operate equally well where a fractional number of lines are provided per field or per frame. All such embodiments are believed to be within sphere and scope as set forth in the claims appended hereto.

Claims: WE CLAIM 1. A video de-interlacing system for mapping a pair of input video fields each having a predetermined number of lines per field to a single output video frame having a predetermined number of lines per frame, comprising: a) a target increment calculator for receiving said predetermined number of lines per field and said predetermined number of lines per frame and in response generating a target increment value representing space between respective lines of said output video frame relative to lines of said input video fields; b) a target spacing calculator for receiving said target increment value and for successive ones of said lines of said pair of input video fields generating respective target line spacing values; and c) an image resizing engine for receiving successive ones of said lines of said pair of input video fields and respective target line spacing values and in response generating successive lines of said output video frame . 2. The system of claim 1, wherein said target increment calculator further comprises: d) a first multiplier for multiplying said number of lines per field by two and in response generating a first product value; e) a first subtractor for subtracting one from said first product value and in response generating a first difference value; f) a second subtractor for subtracting one from said number of lines per frame and in response generating a second difference value; g) a second multiplier for multiplying said second difference value by two and in response generating a second product value; and h) a divider for dividing said first difference value by said second product value and in response generating said target increment value. 3. The system of claim 1, wherein said target spacing calculator further comprises an accumulator for receiving said target increment value and generating said respective target line spacing values as a running accumulated sum of said target increment value. 4. The system of claim 3, wherein said accumulator further comprises an adder, a multiplexer and a storage register, a first input of said adder being provided for receiving said target increment value, an output of said adder being applied to a first input of said multiplexer, a second input of said multiplexer being provided for receiving a first accumulator initialization value for even ones of said pair of input video fields, a third input of said multiplexer being provided for receiving a second accumulator initialization value for odd ones of said pair of input video fields, an output of said multiplexer being connected to an input of said storage register, and an output of said storage register being connected to a second input of said adder.

Inventors: GOEL JAMES, GREGGAIN LANCE, GOEL, JAMES, GREGGAIN, LANCE
Applicants: GENESIS MICROCHIP INC, GENESIS MICROCHIP INC.
Application year: 1996
Main classification: H04N5
IPC codes: H04N5