Method of manufacturing an inverted thin film transistor

Abstract: An amorphous silicon thin film transistor (a-Si TFT) or other a-Si device is produced by depositing and lithographically patterning a layer of doped semiconductor material (40) such as microcrystalline or polycrystalline silicon to produce a conductive lead (62). The semiconductor material is deposited over an insulating region (28) and over an exposed part of an amorphous silicon layer (26). The insulating region has an edge (32) that is over and approximately aligned with an edge (30) of a gate region (22). The doped semiconductor layer therefore forms a junction (42) to the amorphous silicon layer at the edge of the insulating region, approximately aligned with the edge of the gate region. Self-aligned lithographic patterning is performed in such a way that the conductive lead (62) overlaps the insulating region by a distance (Δ) that is no more than a maximum overlap distance (D MAX ).

Description: The present invention relates to fabrication of circuitry on a substrate. Kanicki, J., Hasan, E., Griffith, J., Takamori, T., and Tsang, J.C., "Properties of High Conductivity Phosphorous Doped Hydrogenated Microcrystalline Silicon and Application in Thin Film Transistor Technology," Mat. Res. Soc . Symp. Proc. , Vol. 149, 1989, pp. 239-246, disclose techniques for phosphorous (P) doping of microcrystalline silicon. Kanicki et al. disclose use of a heavily (n+) P-doped layer in a hydrogenated amorphous silicon (a-Si:H) thin film transistor (TFT) as a contact interlayer between a source/drain metal and a-Si:H layer. Kanicki et al. also disclose application of such a layer to a TFT structure, mentioning a gate to source-drain overlap of about 5µm. Lustig, N., and Kanicki, J., "Gate dielectric and contact effects in hydrogenated amorphous silicon-silicon nitride thin-film transistors," J. Appl. Phys., Vol. 65, May 1989, pp. 3951-3957, disclose improvement in TFT mobility upon replacement of phosphorous doped ( n + ) hydrogenated amorphous silicon ( a -Si:H) by n + hydrogenated microcrystalline silicon (µ c -Si:H) in source-drain contact fabrication. Lustig et al. disclose an experiment that included a thin n + µ c -Si:H layer between source-drain metal and intrinsic a -Si:H, to insure ohmic contacts. The n + µ c - Si:H was deposited from a PH 3 /SiH 4 mixture in H 2 yielding an approximately 0.1-Ω cm material. The devices had a width of 50 µm, a channel length of 20 or 40 µm, and a gate to source-drain overlap of approximately 5 µm, and that the TFTs are suitable for addressing flat panel LCD displays. Average field-effect mobility increased with n + µ c -Si:H. The invention addresses problems in fabricating circuitry on a substrate. Performance of an amorphous silicon (a-Si) device such as a thin film transistor (TFT) depends heavily on the relative lateral positions of the edges of the device's gated region and the boundaries or junctions between the device's doped channel leads and the undoped region that includes the device's channel. If the source-side boundary or junction is outside the edge of the gated region, contact resistance is poor; in the limit, the gate cannot control the state of the channel as required for proper device operation. On the other hand, if a device's gated region extends beyond the boundary or junction at either side of the channel and overlaps one or both doped channel leads, unnecessary excess geometric capacitance occurs; if the extent of overlap is not precisely controlled, capacitance will vary, producing intra-device variations between different devices formed on the same substrate. Precise alignment of the edges of the gated region and the boundaries or junctions with the channel leads, referred to herein as "gate/lead alignment," would avoid these problems and would also make it possible to fabricate devices with shorter channel lengths, thus improving device performance. But precise gate/lead alignment is difficult to achieve. Some conventional techniques attempt to achieve precise gate/lead alignment by depositing an a-Si layer and a phosphorous layer over a metal gate region and by then performing backside laser crystallization. But the laser crystallization step is technically difficult and, since laser operations are not otherwise necessary for a-Si TFT production, use of a laser may require inefficient modifications in processes and equipment. Another conventional technique attempts to achieve precise gate/lead alignment by depositing an a-Si layer over the gate region, by performing a backside exposure to produce a patterned dielectric layer that forms an insulating region self-aligned with the gated region, and by then implanting phosphorous ions. The insulating region prevents the phosphorous ions from entering the channel, but the phosphorous ions enter adjacent areas, forming heavily doped channel leads. Again, since implantation of phosphorous ions is not otherwise necessary for a-Si TFT production, use of phosphorous ion implantation may require inefficient modifications. Further, ion implantation can damage a TFT, and the resulting channel leads do not make good electrical contact with other layers as well as a doped deposited layer would. Also, a TFT produced in this manner is likely to have lower mobility. The invention is based on the discovery of an improved technique that solves the problem of precise gate/lead alignment. The technique achieves precise gate/lead alignment by depositing a doped semiconductor layer using plasma enhanced chemical vapor deposition (PECVD) to produce a self-aligned junction at an edge of a self-aligned insulating region. The technique then patterns the doped semiconductor layer using self-aligned lithography to produce a conductive lead that has a self-aligned edge overlapping the insulating region by a distance that is no more than a maximum overlap distance. The maximum overlap distance can, for example, be no more than 1.0 µm or can be 0.5 µm, permitting very small a-Si TFTs. The technique can be implemented as an improvement on conventional techniques. The conventional techniques form an a-Si TFT that includes a gate region with first and second edges, an undoped a-Si layer over and extending beyond the edges of the gate region, and an insulating region over the a-Si layer but with edges approximately aligned with the gate region's edges. The improvement includes depositing a PECVD layer of doped semiconductor material, such as microcrystalline silicon (µxtal-Si) or polycrystalline silicon (poly-Si), over the insulating region and over parts of the a-Si layer outside the edges of the insulating region; this produces junctions at the edges of the insulating region and approximately aligned with the edges of the gate region. The improvement then patterns the doped semiconductor layer using self-aligned lithography in such a way that each of the channel leads has a self-aligned edge approximately aligned with one of the gate region's edges and each self-aligned edge overlaps the insulating region by a distance that is no more than the maximum overlap distance. The doped semiconductor layer can be patterned with a self-aligned lithographic backside exposure in which the gate region prevents photoexposure of parts of a photoresist layer that are over it. Parts of the photoresist layer that are not photoexposed can then be removed to expose parts of the doped semiconductor layer. The exposed parts of the doped semiconductor layer can then be removed. A number of operations can be timed to control overlap, including backside exposure, application of developer, baking, and application of etchant. The technique can also be implemented by producing a gate region in a patterned conductive layer and by then patterning subsequent layers using two self-aligned lithographic backside exposures. The first backside exposure, with positive resist, can be used to pattern an insulating layer to produce an insulating region with an edge approximately aligned with an edge of the gate region. The second backside exposure, with negative resist, is then used to pattern a PECVD layer of doped µxtal-Si as described above to produce a conductive lead extending from a junction approximately aligned with the edge of the gate region. The conductive lead has a self-aligned edge that overlaps the insulating region by a distance that is no more than the maximum overlap distance. A conductive metal electrode can be on the conductive lead, electrically connected to the junction through the conductive lead. The technique therefore produces a junction that is fully self-aligned with the edge of the gate region and that is electrically connected to a conductive lead. The result is an inverted staggered device, because the gate is below the channel and on the opposite side of the a-Si layer from the channel leads. The technique can be used to produce array circuitry in which each cell includes an a-Si TFT. The array circuitry could be used, for example, in producing a light valve array for an AMLCD. The technique described above is advantageous because it can be used to produce a fully self-aligned a-Si TFT with minimal geometric capacitance between the gate and the channel leads and without reduced mobility. The technique is highly compatible with conventional techniques for producing a-Si TFTs, and does not require lasers, phosphorous implantation, or other complicated additional process steps or additional equipment. JP-A-02 295 132 discloses a method of forming an amorphous silicon thin film transistor which corresponds to the pre-characterising portion of claim 1. In one aspect of the invention there is provided a method as defined in claim 1. Further aspects of the invention are defined in the dependent claims 2-8. The invention will now be described by examples with reference to the accompanying drawings, in which: Fig. 1 is a flow diagram showing schematic cross sections of stages in which a doped semiconductor layer is deposited to produce a junction at a self-aligned edge of an insulating region and is then patterned using self-aligned lithography to produce a conductive lead extending from the junction and overlapping the insulating region by a distance that is no more than a maximum overlap distance; Fig. 2 is a flow chart showing acts in producing a junction and a conductive lead as in Fig. 1; Fig. 3 is a schematic cross section showing how a backside exposure can be timed to control the distance by which a conductive lead as in Fig. 1 overlaps an insulating region; Fig. 4 is a schematic cross section showing how application of developer can be timed to control the distance by which a conductive lead as in Fig. 1 overlaps an insulating region; Fig. 5 is a schematic cross section showing how baking can be timed to control the distance by which a conductive lead as in Fig. 1 overlaps an insulating region; Fig. 6 is a schematic cross section showing how application of etchant can be timed to control the distance by which a conductive lead as in Fig. 1 overlaps an insulating region; Fig. 7 is a flow chart showing acts in producing an active matrix array on an insulating substrate in one implementation of the general acts in Fig. 2; Fig. 8 is a schematic flow diagram with cross sections showing several stages in performing the acts in Fig. 7; Fig. 9 is a schematic diagram showing an array product produced by the acts in Fig. 7 and showing layout of some layers in a cell in the array; Fig. 10 is a microscopic photograph showing a structure produced by implementing the general acts in Fig. 2; Fig. 11 is a graph showing current-voltage characteristics of a structure like that in Fig. 10. To perform "chemical vapor deposition" is to cause a material to be deposited on a physical structure by use of reactant gases and an energy source to produce a gas-phase chemical reaction. The energy source could be thermal, optical, or plasma in nature; "plasma enhanced chemical vapor deposition" or "PECVD" uses a plasma energy source. A "PECVD layer" is a layer produced by PECVD. To perform "lithography" or to "lithographically pattern" is to use a radiation source to transfer a mask pattern to a layer of radiation-sensitive material and then to develop the radiation-sensitive material to obtain a positive or negative copy of the mask pattern. The radiation-sensitive material is referred to as "resist" or "photoresist." The process of transfering a mask pattern to a resist layer is referred to herein as "exposure," and parts of a resist layer that receive radiation during exposure are referred to herein as "photoexposed." A fluid used to develop a resist is referred to as a "developer." A "positive resist" is a resist for which a developer can remove photoexposed parts much more quickly than parts that are not photoexposed. A "negative resist" is a resist for which a developer can remove parts that are not photoexposed much more quickly than photoexposed parts. If it is to be used for etching, a pattern of resist that results from development may be referred to as a "pattern of mask material" or simply a "mask." In lithography, "backside exposure" is exposure of a resist layer in a structure on a substrate, where radiation reaches the resist layer through the substrate. A part of a layer between the resist layer and the substrate can provide a mask pattern if it prevents radiation from reaching the resist layer in areas over it. The terms "gate region," "gated region," and "channel" have related meanings: A "gate region," sometimes called a "gate," is a part of a layer that controls conductivity of a "gated region" that is part of another layer, typically defined by the projection of the gate region onto the other layer; conversely, a "gated region" is a part of a layer with conductivity that changes depending on the gate region; a "channel" is formed when current flows through a gated region. A channel is "highly conductive" or "ON" when the channel is in a state in which current can flow freely through it. A channel is "OFF" when the channel is in a state in which very little current can flow through it. A "channel lead" is a lead that electrically connects to a channel. A channel may, for example, extend between two channel leads. A "charge carrier" is a real or fictitious particle that can transport charge to produce a current; electrons and holes are examples of charge carriers. A "charge carrier source" is an ion, atom, molecule, or other feature that can provide a charge carrier. A "charge carrier destination" is an ion, atom, molecule, or other feature that can neutralize or stop movement of a charge carrier. In an integrated circuit, an "n-channel" is a channel for which the majority of charge carrier sources provide charge carriers of negative sign such as electrons; a "p-channel" is a channel for which the majority of charge carrier sources provide charge carriers of positive sign such as holes. A "dopant particle" or "dopant" is an ion, atom, molecule, or other particle that can be added to a channel or other part of an integrated circuit during fabrication and that serves as a charge carrier source when the integrated circuit is in use. An "n-type dopant" provides charge carriers of negative sign and a "p-type dopant" provides charge carriers of positive sign. A layer or part of a layer is "doped" if it contains dopant and "undoped" if it does not. A "transition" or "junction" occurs where a doped channel lead meets an undoped layer of material that includes a gated region. The channel lead "extends away from" the transition or junction. A "transistor" is a component that has a channel or a series of channels that extends between two channel leads, and that also has a third lead--referred to as a "gate lead" or simply "gate"--such that the channel or series of channels can be switched between ON and OFF by signals that change potential difference between the gate and one of the channel leads, referred to as the "source." The channel lead that is not the source is referred to as the "drain." Other components may have leads called gates, sources, and drains by analogy to transistors. A part of a first layer "overlaps" a part of a second layer if the part of the first layer is over and extends beyond an edge of the part of the second layer, but has an edge inside the edge of the part of the second layer. The "overlap distance" or "distance" by which the first layer overlaps the second layer is the maximum distance from the edge of the second layer inward to the edge of the first layer. A "maximum overlap distance" is an overlap distance that cannot be exceeded. For example, it may not be possible to reliably fabricate a device or a device may not function properly if a maximum overlap distance is exceeded. An operation "controls" an overlap distance if the operation is one of a set of one or more operations that determine the size of the overlap distance. Edges of two layers or parts of layers in a structure formed on a substrate are "approximately aligned" if their projections onto the surface of the substrate at which the structure is formed are approximately the same. Edges of two layers or parts of layers are "self-aligned" if they are approximately aligned because one was produced by a lithographic process in which the other served as a mask. Accordingly, "self-aligned lithography" or "self-aligned lithographic patterning" is lithography that obtains approximate alignment between edges of two layers or parts of layers by using one layer as a mask in a process that patterns the other. In self-aligned lithography, "self-aligned backside exposure" is backside exposure in which part of a blocking layer between the resist layer and the substrate prevents radiation from reaching the resist layer so that the resulting exposure pattern in the resist layer can then be used to lithographically pattern a layer between the blocking layer and the resist layer. A "thin film transistor" or "TFT" is a transistor that is part of a thin-film structure. An "amorphous silicon thin film transistor" or "a-Si TFT" is a TFT with a gated region that is part of a layer of amorphous silicon, so that the TFT's channel is formed in amorphous silicon. Figs 1-6 show general features of the invention. In each of cross sections 10, 12, and 14 in Fig. 1, circuitry being formed at a surface of substrate 20 includes gate region 22, first insulating layer 24, undoped a-Si layer 26, and insulating region 28. Layers 24 and 26 extend over edge 30 of gate region 22, but edge 32 of insulating region 28 is approximately aligned with edge 30 of gate region 22, as would be the case for a self-aligned insulating region. Cross section 10 in Fig. 1 also shows doped semiconductor layer 40. Prior to PECVD deposition of doped semiconductor layer 40, undoped a-Si layer 26 has an exposed part outside edge 32 of insulating region 28. Doped semiconductor layer 40 lies over insulating region 28 and over the exposed part of a-Si layer 26. PECVD deposition of doped semiconductor layer 40 therefore produces junction 42 at edge 32 of insulating region 28. Junction 42 is approximately aligned with edge 30 of gate region 22, as suggested by the dashed line in cross section 12. Cross section 12 shows self-aligned lithographic patterning of doped semiconductor layer 40. Part 52 of resist layer 50 remains after other parts are removed, such as through exposure, development, and baking. Edge 54 illustratively indicates extent of exposure, edge 56 indicates the distance by which resist layer 50 overlaps insulating region 28 after development, and edge 58 indicates overlap after baking. Self-aligned edge 60, approximately aligned with edge 30 of gate region 22, indicates the distance by which doped semiconductor layer 40 overlaps insulating region 28 after other parts of doped semiconductor layer 40 are removed, such as through etching. Cross section 14 shows the structure after lithographic patterning. Conductive lead 62 is formed in doped semiconductor layer 40, with overlap 64 extending beyond edge 32 of insulating region 28 after completion of lithographic patterning, such as by removal of photoresist layer 50. As shown in Fig. 1, the distance Δ by which the self-aligned edge of conductive lead 62 overlaps insulating region 28 at any point along edge 32 is less than D MAX , a maximum value appropriate to the structure being produced. In general, D MAX can be kept sufficiently small to prevent shorting across insulating region 28 and to keep capacitance between conductive lead 62 and gate region 22 below the maximum capacitance allowable for proper operation of the structure. For example, for a-Si TFTs with channel lengths of approximately 5 µm, it may be necessary to have D MAX ≤1.0 µm to minimize capacitance and maintain performance of the device; even lower values of D MAX may help to avoid problems due to small variations in capacitance. The general acts in Fig. 2 begin in box 80 with a structure that includes a gate region, an insulating layer and an undoped a-Si layer over the gate region, and an insulating region over the gate region in a layer over the a-Si layer. The insulating region has an edge approximately aligned with the gate region's edge, like edge 32 of insulating region 28 in Fig. 1, approximately aligned with edge 30 of gate region 22. As a result, the a-Si layer has an exposed part outside the edge of the insulating region, like layer 26 in Fig. 1. The act in box 82 deposits a doped PECVD layer of semiconductor material, such as layer 40 in Fig. 1, over the insulating region and over exposed parts of the a-Si layer. The act in box 82 produces a junction, such as junction 42, between the doped semiconductor layer and the a-Si layer at the edge of the insulating region. Because the edge of the insulating region is approximately aligned with the edge of the gate region, the junction is also approximately aligned with the edge of the gate region. The act in box 84 then patterns the doped semiconductor layer using self-aligned lithography to produce a conductive lead extending from the junction, like lead 62 in Fig. 1. The act in box 84 is performed in such a way that the conductive lead has a self-aligned edge approximately aligned with the edge of the gate region but overlapping the insulating region by a distance that is no more than a maximum overlap distance, D MAX . Figs. 3-6 illustrate ways in which overlap distance can be controlled in the act in box 84. Each shows an enlarged detail of the region around overlap 64, with parts of layers having the same reference numerals as in cross section 12 in Fig. 1. In Fig. 3, resist layer 50 is a layer of photoresist, and backside exposure is performed to photoexpose parts of resist layer 50 that are not over gated region 22. Gated region 22 initially prevents photoexposure of resist layer 50 in areas over it, but scattering of light gradually exposes more and more of resist layer 50 near edge 32 of insulating region 28. Therefore, backside exposure of resist layer 50 can be timed to control overlap. At time t 0 , the boundary between photoexposed part 100 and non-photoexposed part 102 is approximately aligned with edge 32, because the backside exposure has full effect where it is not blocked by gate region 22. As the duration of backside exposure increases to t 1 and t 2 , however, photoexposed part 100 extends further and further past edge 32 of insulating region 28 due to light scattering. Eventually, photoexposed part 100 could extend so far that the extent of overlap after subsequent processes would exceed D MAX , but a duration of backside exposure below that limit can produce an appropriate overlap distance by preventing removal of doped semiconductor layer 40 above edge 32. In Fig. 4, resist layer 50 is being developed, removing non-photoexposed part 102 and leaving photoexposed part 100. The developer quickly removes non-photoexposed part 102, but also removes photoexposed part 100 at a slower rate. Therefore, development of resist layer 50 can be timed to control overlap. At time t 0 , photoexposed part 100 extends to edge 104, the boundary between photoexposed part 100 and non-photoexposed part 102, but all of non-photoexposed part 102 has been removed. As the duration of development increases to t 1 and t 2 , however, the developer reduces the size of photoexposed part 100. Eventually, photoexposed part 100 could be reduced so much that there would be no overlap after subsequent processes, but a duration of development below that limit can produce an appropriate overlap distance. In Fig. 5, resist layer 50 is being baked, which slowly shrinks remaining part 110. Therefore, baking of resist layer 50 can be timed to control overlap. At time t 0 , remaining part 110 extends to edge 112, its extent after development. As the duration of baking increases to t 1 and t 2 , however, the size of remaining part 110 shrinks. An appropriate duration of baking can produce an appropriate overlap distance. In Fig. 6, a slight overlap is produced by timing application of etchant to remove exposed parts of doped semiconductor layer 40. An anisotropic etchant can be used that quickly etches downward through parts of semiconductor layer 40 that are not covered by baked part 114 of resist layer 50, but that also etches to the side at a slower rate. Therefore, application of etchant can be timed to control overlap. At time t 0 , overlap 64 extends to edge 120, approximately aligned with edge 122 of baked part 114. As the duration of etchant application increases to t 1 and t 2 , however, the etchant reduces the size of overlap 64. Eventually, overlap 64 could be removed, but a duration of etchant application below that limit can produce an appropriate overlap distance. The techniques illustrated in Figs. 3-6 could be used separately or together to control overlap distance. The general features described above could be implemented in numerous ways to produce an amorphous silicon device with a fully self-aligned junction and a conductive lead that overlaps the insulating region by a distance not exceeding the maximum overlap distance. The implementation described below produces an active matrix array on an insulating substrate. Figs. 7 and 8 illustrate a fabrication technique that implements the general features described above. The act in box 150 in Fig. 7 begins by producing a bottom metal pattern that forms a scan line for each row of cells in an active matrix array and, for each cell, a gate lead that includes a gate region. The act in box 150 can be implemented by depositing metal using a physical vapor deposition process such as sputtering. The metal can be MoCr, TiW, Al, Al with a TiW capping layer, or another appropriate scan line metal, deposited to a thickness of 40-200nm. 100nm of MoCr, for example, is an appropriate metal. The metal can then be lithographically patterned. In current implementations, typically distances between gate region edges are approximately 10 µm, with distances of 5 µm and less being attainable in the near future. The act in box 152 then produces a bottom nitride layer, an amorphous silicon layer, and a top nitride layer. The act in box 152 has been implemented with plasma chemical vaper deposition (CVD) using a trilayer deposition or etch stop process that deposited three layers in sequence without breaking vacuum. The bottom nitride layer can be silicon nitride deposited at 300-380° C to obtain a thickness of 300nm. The amorphous silicon layer can be deposited at 230-300° C with 5-12% hydrogen, with a thickness of 30-50nm. The top nitride layer can be silicon nitride deposited at 200-250° C to obtain a thickness of 100-150nm. The act in box 154 then lithographically patterns the top nitride with self- aligned backside exposure and top masked exposure of a positive photoresist. The backside exposure defines the self-aligned edges of an insulating region at which junctions will be formed, and the top masked exposure defines the other two edges of the insulating region. The act in box 154 can use a wet etch with a 10:1 buffered oxide etch such as 10 parts ammonium fluoride per part of HF for approximately 2.5 minutes or until the oxide is removed, as indicated by water sheeting off so that the surface is not wet when removed from the etchant, to obtain a self-aligned insulating region over the gate region. The act in box 154 can also include cleaning with a solution of 200 parts water per part of HF to remove native oxide; here again, the etch can continue until the oxide is removed as indicated by water sheeting off. The acts in boxes 160 and 162 then produce a pattern of doped µxtal-Si, providing self-aligned channel leads that overlap the self-aligned insulating region by no more than a maximum overlap distance of 1.0 µm. The act in box 160 deposits a layer of doped µxtal-Si to produce self-aligned junctions at the edges of the insulating region. Deposition of µxtal-Si can be implemented by first performing plasma CVD with SiH 4 , PH 3 , and H 2 at a high deposition power to deposit a heavily n+ doped µxtal-Si layer at 200-250° C with 5-15% hydrogen to a thickness 50-100nm. The µxtal-Si layer should be thin enough to let light through, yet thick enough to be sufficiently conductive to function as a channel lead. The proportions of gases should be chosen to obtain an appropriate grain size and an appropriate level of dopant. The µxtal-Si layer can be doped, for example, with 0.5-2% phosphorous. The act in box 160 could alternatively deposit poly-Si, which has adequate conductivity, or another highly conductive semiconductor material. A heavily n+ doped a-Si layer, however, would not be sufficiently conductive at this scale to carry current between the a-Si channel and subsequently formed metal electrodes without introducing a large series resistance--the metal is patterned to have an edge separated from the self-aligned edge of the insulating region by a sufficient alignment tolerance to avoid errors in which the metal overlaps the insulating region and causes additional capacitance. The act in box 162 lithographically patterns the µxtal-Si layer by self-aligned backside exposure and top masked exposure of a conventional negative photoresist that behaves like a positive resist in process to avoid use of problematic developers such as phenol and xylene. The backside exposure defines the self-aligned edges of channel leads that will overlap the insulating region, and the top masked exposure defines the other edges of the channel leads. The act in box 162 can etch to remove the µxtal-Si layer over the insulating region, which acts as an etch stop, and to remove both the µxtal-Si layer and the a-Si layer elsewhere. During backside exposure, application of developer, baking, and application of etchant, the operator can observe the structure through a microscope and time each operation to obtain an overlap distance that does not exceed the maximum overlap distance. Appropriate times will depend on such factors as intensity of backside illumination, concentrations of developer and etchant, and temperature of baking. With standard illumination, for example, 60 sec of backside exposure can produce an overlap distance as large as 1 µm; in general, the overlap distance is proportional to the length of backside exposure. An etch technique can be chosen that obtains the desired overlap distance. Reactive ion etching produces a vertical profile because it is highly anisotropic, rapidly etching downward and only slowly etching sideways, while chemical and barrel etching are isotropic and produce more undercut. Therefore, reactive ion etching can be more easily timed to control overlap. The act in box 162 can also include another lithographic process that cuts vias through the bottom nitride layer in appropriate locations to allow electrical connections with the bottom metal pattern. For uniform overlap distances, all the lithographic processes performed in box 162 must be performed uniformly over the array. The act in box 164 produces a top metal pattern, including electrodes that are over the channel leads formed in box 162, for electrically connecting the junctions to other components such as a cell's circuitry and a data line. To prevent top metal from overlapping the insulating region, the electrodes are pulled back from the edge of the insulating region by at least 2 µm. The top metal can be the same as the bottom metal in box 150, and can have a thickness of 40-200nm. The manner in which the array can be used to produce an active matrix LCD and further details of the technique in Fig. 7 can be understood from the description of Fig. 4 of US-A-5 491 347. For example, as suggested by the dashed line from box 162 to box 164, additional acts could be performed after box 162 and before box 164. The act in box 164 can also be followed by conventional acts including passivation and so forth. Fig. 8 shows stages in the implementation of Fig. 7. Cross section 180 in Fig. 8 shows the first backside exposure, in box 154. As in the other stages, a structure is formed on a surface of substrate 182, with gate region 184 formed in box 150 and layers 186, 188, and 190 formed in box 152. Prior to the first backside exposure, the act in box 154 deposits positive photoresist layer 192. Part 194 of layer 192 is not photoexposed, but parts 196 and 198 are photoexposed. Cross section 200 shows the second backside exposure, in box 162. The act in box 154 develops photoresist layer 192, removes part 194, and then etches away exposed parts of SiN layer 190, producing insulating region 202 with self-aligned edges. The act in box 160 then deposits doped µxtal-Si layer 204, producing self-aligned junctions at the edges of insulating region 202. Prior to the second backside exposure, the act in box 162 deposits negative photoresist layer 210. Part 212 of layer 210 is not photoexposed, but parts 214 and 216 are photoexposed. Cross section 220 shows the structure after the act in box 164. The act in box 162 develops photoresist layer 210, removes part 212 and then etches away exposed parts of µxtal-Si layer 204, producing channel lead 222 with overlap 224 and channel lead 226 with overlap 228. The lithographic patterning is performed in such a way that overlaps 224 and 228 do not exceed a maximum overlap distance. The act in box 164 then produces electrodes 230 and 232, parts of the top metal layer that are electrically connected to the self-aligned junctions through channel leads 222 and 226. Fig. 9 shows array product 250, which could be produced with the techniques described above in relation to Figs. 7 and 8. Array product 250 includes substrate 252 with array region 254 in which scan lines extend left to right and data lines extend top to bottom, so that each scan line crosses each data line. Fig. 9 also shows a layout of the top and bottom metal layers in the area where a representative scan line 260 crosses a representative data line 262. The bottom metal layer includes scan line 260 and also gate region 270. Gate region 270 can have an appropriate width for the device being fabricated--its width determines the length of the channel of the a-Si TFT formed over it. The top metal layer includes data line 262 and also channel electrodes 272 and 274. Data line 262 can have the same width as scan line 260, but channel electrodes 272 and 274 can have a width larger or greater than the width of the channel of the a-Si TFT, which must be sufficient to meet the current requirement of the device being fabricated. In addition, the spacing from channel electrode 272 to the edge of gate region 270 and the spacing from channel electrode 274 to the edge of gate region 270 can each be 2 µm to avoid errors in which channel electrodes 272 and 274 extend over the insulating region, increasing capacitance. These dimensions are merely illustrative, of course; in practice, the TFT will be dimensioned to provide the necessary current for proper device operation. As can be understood from Fig. 9, the a-Si TFT connects data line 262 to a cell's circuitry (not shown) under control of gate line 260. When the a-Si TFT is ON due to a signal on gate line 260, the channel of the a-Si TFT provides an electrical connection between channel electrodes 272 and 274. Channel electrode 272 in turn is electrically connected to data line 262, and channel electrode 274 is electrically connected to the cell's circuitry. An example of cell circuitry that could be used in an active matrix liquid crystal display (AMLCD) is described in relation to Fig. 3 of US-A-5 491 347. An implementation of the general features described above has been built and tested. The microscopic photograph in Fig. 10 shows device 300 successfully produced by implementing the general acts in Fig. 2, using a fabrication process similar to that described above in relation to Figs. 7 and 8. Line 302 is a long, narrow line formed in a bottom metal layer and covered by layers 304, an undoped a-Si layer covered by a PECVD layer of doped µxtal-Si. The pattern of doped µxtal-Si is formed using backside exposure to obtain self- aligned edges that overlap the self-aligned edges of insulating region 306. The area in which layers 304 cover line 302 defines a gate region of line 302 and a gated region of the undoped a-Si layer, each with dimensions approximately 98 µm X 5 µm. Over the gated region of the undoped a-Si layer is insulating region 306, formed in a layer of SiN using backside exposure to obtain self-aligned edges. As can be seen from Fig. 10, the PECVD layer of doped µxtal-Si overlaps insulating region 306 by distances that are generally less than 0.5 µm and that are less than 1.0 µm along the entire length of insulating region 306. The overlap distances were obtained by microscopically examining the device during etching, judging visually when an appropriate overlap distance had been obtained. This suggests that more precise fabrication techniques will allow smaller values for D MAX , such as 0.5 µm. The overlap shown in Fig. 10 is sufficient to provide a tolerance that prevents etching of the undoped a-Si layer for devices in an array, yet is small enough to avoid shorts across insulating region 306 and to minimize capacitance. If there were no overlap, extremely slight alignment errors across an array of devices would lead to defects due to etching of undoped a-Si at a junction. Channel electrodes 310 and 312 are formed in a top metal layer to permit electrical connections so that device 300 can be tested. A similar device has measured mobility of 0.59 cm 2 /V-sec. The device's current-voltage performance is shown in Fig. 12, which shows that the device exhibited low OFF current and high ON current at a drain-source voltage of 20V. The above implementation uses particular materials in a thin-film structure, but other materials could be used. For example, different metals could be used in the bottom and top metal layers, or other conductive materials could be used rather than metal, such as a thick layer of heavily doped silicon provided it is thick enough to prevent photoexposure of resist. Different insulating materials could be used. The channel leads could be formed from a different doped semiconductor material, provided it is sufficiently conductive. The above implementation uses particular processes to produce a thin-film structure, but other processes could be used. In some cases, for example, acts could be performed with different materials which full within the definition of claim 1. Various resists, developers, and etchants could be used. The above implementation uses a layout for a cell in an array, but other layouts could be used. The implementation described above provides circuitry with specific geometric and electric characteristics, but the invention could be implemented with different geometries and with different circuitry. The implementation described above includes layers of specified thicknesses, produced from specified materials by specified processes, but other thicknesses could be produced, and other materials and processes could be used, such as thinner semiconductor and insulating layers to improve TFT performance or to increase storage capacitance. The invention could be applied in many ways, including not only production of active matrix arrays but also production of other structures in which very small a-Si TFTs are beneficial. The invention can be applied in active matrix arrays of many different kinds, including display arrays, light valve arrays, and sensor arrays.

Claims: A method of forming an amorphous silicon thin film transistor at a surface of a substrate (20, 182, 252), the amorphous silicon thin film transistor including: a gate region (22, 184, 270) that has first and second edges (30); an undoped amorphous silicon layer (26, 188) over the gate region (22, 184, 270), the undoped amorphous silicon layer (26, 188) extending beyond the first and second edges (30) of the gate region (22, 184, 270); and an insulating region (28, 202) over the undoped amorphous silicon layer (26, 188), the insulating region (28, 202) having first and second edges (32) approximately aligned with the first and second edges (30) of the gate region (22, 184, 270) so that the undoped amorphous silicon layer (26, 188) has exposed parts outside the first and second edges (32) of the insulating region (28, 202); the method comprising the steps of: a) depositing doped semiconductor layer (40, 204) by PECVD over the insulating region (28, 202) and over the exposed parts of the undoped amorphous silicon layer (26, 188), thereby producing first and second junctions (42) between the doped semiconductor layer (40, 204) and the exposed parts of the undoped amorphous silicon layer (26, 188) at the first and second edges (32) of the insulating region (28, 202), respectively, the first and second junctions (42) being approximately aligned with the first and second edges (30) of the gate region (22, 184, 270), respectively; b) depositing a photoresist layer (50, 210) over the doped semiconductor layer (40, 204); c) photoexposing the photoresist layer (50,210) for forming an opening in the photoresist layer over the gate region (22,184,270); d) removing the parts (102, 212) of the photoresist layer (50, 210) to form the opening which expose parts of the doped semiconductor layer (40, 204); e) removing the parts of the doped semiconductor layer (40, 204) which are exposed in step d); to produce a patterned doped semiconductor layer (40, 204) which form first and second channel leads (62, 222, 226) which first and second channel leads (62, 222, 226) that extend from the first and second junctions (42), respectively, the first and second channel leads having first and second aligned edges (64), respectively, approximately aligned with the first and second edges (30) of the gate region (22, 184, 270), respectively, each of the first and second aligned edges (64) overlapping the insulating region (28, 202) by a distance (Δ) that is no more than a maximum overlap distance (D MAX ); characterized in that the photoresist layer is deposited directly on the doped semiconductor layer the step c) is realised by a backside exposure to photoexpose the photoresist layer (50, 210) and the gate region (22, 184, 270) prevents photoexposure of parts (102, 212) of the photoresist layer (50, 210) which are over the gate region (22, 184, 270); first and second metal leads (230,232) are formed on the first and second channel lead, respectively after step e). The method of claim 1, wherein the backside exposure comprises timing the backside exposure to control a distance by which second parts (100) of the photoresist layer (50, 210) which are photoexposed overlap the insulating region (28, 202). The method of claim 1, wherein the step d) comprises applying of a developer, which applying of the developer comprises timing application of the developer to control a distance by which the second parts (100) of the photoresist layer (50, 210) which are not removed overlap the insulating region (28, 202). The method of claim 3, wherein the step d) further comprises baking the second parts (100) of the photoresist layer (50, 210), which baking comprises timing the baking to control a distance by which baked parts (110) of the photoresist layer (50, 210) overlap the insulating region (28, 202). The method of claim 1, wherein the step a) comprises applying of an etchant which removes the parts of the doped semiconductor layer (40, 204) which are exposed, which applying of an etchant comprises timing the application of the etchant to control a distance by which parts of the doped semiconductor layer (40, 204) which are not removed by the etchant overlap the insulating region (28, 202). The method of any of the preceding claims, in which the maximum overlap distance (D MAX ) is no more that 1.0 µm. The method of any of the preceding claims, in which the maximum overlap distance (D MAX ) is 0.5 µm. A method of forming a circuitry at a surface of a substrate, the method comprising: forming an array of electrically connected thin film transistors according to the method as defined in any of claims 1-7, wherein the doped semiconductor layer is formed as a microcrystalline silicon layer.

Inventors: HACK MICHAEL G, LUJAN RENE A, HACK, MICHAEL G., LUJAN, RENE A., Lujan, René A.
Applicants: XEROX CORP, XEROX CORPORATION
Application year: 1996
Main classification: H01L21
IPC codes: H01L29, H01L21