Method and corresponding circuit for generating a syncronization ATD signal

Abstract: The invention relates to a method and a circuit for generating a pulse synchronization signal (ATD) in order to control the reading phase of memorycells in semiconductor integrated, electronic memory devices. The pulse signal (ATD) is generated upon sensing a change in logic state on at least one of a plurality of address input terminals (PAD) of the memory cells to also generate an equalization signal (EQLZ) for a sense amplifier. The logic state of said pulse signal (ATD) is re-acknowledged by a fed-back response having a predetermined delay and being generated upon reception of a corresponding signal to said equalization signal (EQLZ). To this aim, a re-acknowledge circuit portion (15) is provided which is input a corresponding signal to the equalization signal (EQLZ) and feedback connected to the output node (12) to drive the discharging of the node (12) with a predetermined delay from the reception of the input signal.

Description: Field of the Invention This invention relates to a method and to a circuit for generating an ATD pulse synchronization signal in order to control the reading phase of memory cells in semiconductor integrated, electronic memory devices. As is well known, reading the contents of cells in a semiconductor integrated electronic memory device is possible by means of a predetermined sequence of operations referred to in the art as the reading cycle. A reading cycle begins with the memory address of data to be read being presented to the input terminals of the memory circuit. An input stage detects a change in the status of the addresses present on such terminals to thereby initiate a reading operation. Row and column decoder circuits select the memory word that has been addressed. The states of the cells contained in this memory word are sensed by a read amplifier, commonly referred to as the sense amplifier. The data sensed by the sense amplifier is then output through an output buffer stage. Background Art Each of the above reading cycle phases must have a predetermined duration and compatible with the memory access times set up by the memory circuit specifications. All of the various phases of a reading cycle are clocked by synchronization pulses derived from a single main pulse referred to as the ATD (Address Transition Detection) pulse. The ATD pulse is generated within the memory circuit each time that a switching of address is sensed on the input terminals. In general, the generation of the ATD pulse is entrusted to a NOR structure whose output is normally at a high logic level. On the occurrence of a change in logic level, even at just one of the input terminals, the NOR structure will switch its output to allow a terminal, from which the ATD pulse is delivered, to be discharged to ground. The accompanying Figure 1 depicts schematically circuitry for generating the ATD signal, in accordance with the state of the art. Figure 1 shows circuitry which comprises an input buffer stage 2 associated with each address input terminal or PAD. The input terminals are designated PAD<0>,...,PAD<9>. Each of the stages 2 has at least one buffered output 3, that is an output delivering a signal buff-inp which is essentially a delayed replica of the signal present on the corresponding PAD. The structure shown in Figure 1 is referred to as a concentrated NOR because all the outputs 3 of the stages 2 are connected to a single ATD pulse generating circuit 4. This NOR always has at least one of its inputs at a high logic level, such that its output can be low all the time in the stationary condition. Therefore, the ATD signal will be normally high and the ATD pulse will originate from a downward transition of the ATD signal. As previously mentioned, the ATD pulse would only be generated on the occurrence of a transition in the logic state of the input terminals. The accompanying Figure 2 depicts schematically the structure of a circuit 4 for generating the ATD signal, according to the state of the art. This circuit 4 comprises P-channel MOS transistors, designated M2, M4 and M7, which are highly resistive and, therefore, hardly conductive. The transistor M7 is always 'on' and holds the output node 8 of the circuit 4 at a high logic level, in co-operation with a stabilizing capacitor C1. The transistors M2 and M4 are the pull-up elements for respective CMOS inverters formed of corresponding pull-down NMOS transistors M3 and M5. The structure which results from the coupling of the inverters M2, M3 and M4, M5 is that of a latching register 11 which has outputs, Q and #Q, the Q output being normally at a high logic level. The latch 11 is input signals buff-inp from one of said input terminals, as stabilized by the capacitors C2 and C3. These signals are allowed to pass to the latch 11 by respective NMOS transistors M1 and M6 being highly conductive. On the occurrence of an input transition, the first output, Q, of the latching inverter 11 is at once brought to a low logic level. The other output, #Q, will take a little more time to change its state because the pull-up transistors M2 and M4 are highly resistive. Thus, there will be a time when both these outputs are at a low logic level. With the Q and #Q outputs connected directly to respective inputs of a logic gate 13 of the NOR type, the output of the gate 13 will be driven to a high logic value, thereby allowing an NMOS transistor M8, connected to the output node 8 of the circuit 4, to be turned on. This transistor M8 enables discharging of the current through the transistor M7, which transistor is held permanently 'on', to ground and consequent changing of the node 8 to a low logic value effective to produce the ATD pulse. The structure just described is duplicated in the circuit 4 at each of the input terminals; only the transistor M7 of the output node 8 and its capacitor C1 are shared by the entire circuit 4, and correspond respectively to the resistor R and the capacitor C shown in Figure 1. While being in many ways advantageous and substantially achieving its objective, the generator circuit previously described has certain drawbacks, as specified herein below. A stable duration for the ATD pulse cannot always be ensured on the occurrence of spurious switching pulses (noise) at the address input terminals. This has an adverse effect on the memory access times because the circuit will also generate an ATD pulse in the presence of noise, but this short-duration pulse does not allow a correct reading of data from the memory. A second known solution, depicted schematically in Figure 3, provides for the association, with each input PAD, of an input buffer stage 5 which also incorporates a portion of the foregoing ATD pulse generating circuit. According to this prior solution, referred to in the art as the distributed NOR, each stage 5 is provided with a control output 6 whereat a signal atd-line is developed. All the outputs 6 of the buffer stages 5 are connected to a single line 7, ATD-LINE, which is normally implemented as a metallization line running up to the output node 8, the node 8 being connected to the supply Vcc through the resistor R and to the ground GND through the capacitor C. A pulse ATD-PULSE is obtained from the node 8 by an inverter 9, as in the example of Figure 1. When a logic level transition occurs on the corresponding input PAD, an output 6 is able to bias the line ATD-LINE 7 to ground. Being comparatively long, the line 7 has a resistance and intrinsic capacitance of relatively high value. Accordingly, if the switching affects all of the addresses in parallel, the line 7 will be discharged quite rapidly; otherwise, if the switching only affects the farthest PAD from the output node 8, the line 7 will be discharged at a slower rate. This prior structure shows, therefore, to be dependent on the number of the switched addresses. In fact, where the switching involves those address terminals which are physically the farthest, the circuit undergoes a delay due to the length of the metallization paths. This reflects on the stability of the ATD pulse duration in an adverse manner. In practice, a different duration is obtained for the equalization period according to which terminal is being switched, and this worsen the memory access time during the reading phase. The underlying technical problem of the instant invention is to provide a method and a circuit for generating an ATD signal, which have such respective functional and structural features as to obviate the drawbacks that are besetting the solutions offered by the prior art. US-A-5418479 discloses the generation of an address transition pulse of a safe length by use of feedback. Summary of the Invention The solution idea on which the instant invention stands is one of providing for a re-acknowledgment of the logic state of said ATD pulse signal by means of a fed-back response having a predetermined time duration and being generated upon reception of a signal which corresponds to an equalization signal EQLZ derived from the ATD signal for a sense amplifier. Based on this solution idea, the technical problem is solved by a method as indicated above and defined in the characterizing portion of Claim 1. The technical problem is also solved by a circuit for generating an ATD pulse synchronization signal to control the reading phase of memory cells of semiconductor integrated electronic memory devices, being of the type which is linked operatively to the occurrence of a change in logic state on at least one of a plurality of address input terminals of said memory cells, and comprising a structure of the NOR type placed between said address terminals and an output node whence an equalization signal is obtained for a sense amplifier. The circuit is characterized in that it comprises a re-acknowledge circuit portion which is input a signal corresponding to said equalization signal and is feedback connected to said output node to drive the discharging of the node with a predetermined delay from the reception of the input signal. The features and advantages of the method and circuit according to the invention will be apparent from the following detailed description of an embodiment thereof, given by way of non-limitative example with reference to the accompanying drawings. Brief Description of the Drawings Figure 1 shows schematically a prior art circuit for generating an ATD pulse signal. Figure 2 is a schematic detail view of the circuit shown in Figure 1. Figure 3 shows schematically a second circuit proposal from the prior art for generating an ATD signal. Figure 4 shows schematically the generator circuit of this invention. Figures 5A and 5B show, on respective voltage (V) vs, time (ns) graphs, plots of the ATD and equalization EQLZ signals present in the generator circuit of Figure 4. Detailed Description Referring to the drawing figures, and in particular to the example in Figure 4, generally and schematically shown at 1 is a generator circuit according to the invention for generating an ATD (Address Transition Detection) signal for use during a memory cell reading cycle. Memory cells mean here a plurality of memory elements incorporated into a conventional electronic device integrated on a semiconductor and implemented with a matrix of cells organized in rows and columns. Associated with the matrix are corresponding row and column decoder circuit portions, and sense amplifiers. The memory cells may be any types; however, for the purpose of this invention, they are preferably of the FLASH EPROM non-volatile type adapted to be programmed and erased electrically. To fully appreciate the aspects of this invention, it should be recalled that the phase of reading such memory cells comprises a cycle of operations which are clocked by synchronization pulses derived from a single main pulse designated ATD. That circuit portion which is to read the contents of the memory cells and convert the read analog data to digital data is called the sense amplifier or read amplifier. This amplifier is usually of the differential type and has a pair of inputs which are respectively connected the one to a cell of the memory matrix and the other to a reference cell. The reading is made possible by an unbalance in the loads of the matrix leg Matside and the reference leg Rifside. The prior art teaching is of carrying out an equalization phase for the potential present on said two legs connected to the amplifier inputs, before each reading phase that involves an unbalance of the two legs. The equalization is allowed by a suitable circuit, not shown because conventional, being driven by an equalization signal EQLZ. For the purpose of this invention, the single fact of relevance is that the equalization signal EQLZ is derived from the ATD signal through a set of logic gates, as explained hereinafter. The generator circuit 1 comprises P-channel MOS transistors which are connected in parallel with one another, and denoted by MP1, MP2 and MP3. These transistors are connected between a positive voltage supply reference Vcc and an ATD output node 12. These transistors have their respective control terminals connected together and in common with the control terminal of an N-channel MOS transistor MN1 placed between the node 12 and a second voltage reference, such as a ground GND. All of the above control terminals are connected to the line ATD-LINE on which a signal enabling the generation of the ATD pulse is presented. A P-channel MOS transistor MP4 connects the node 12 to the first supply reference, and a capacitor C connects the node 12 to the ground GND. The ATD pulse synchronization signal is obtained from the node 12. The node 12 is connected to the input of a logic gate 16 of the OR type with two inputs. The second input of the gate 16 receives a standby signal STBY which is the equivalent of a low logic value. In essence, it is as if this second input of the gate 16 were held at ground potential. The gate 16 has an output connected to an input of a logic gate 17 of the NAND type with two inputs. The other input of the second logic gate 17 is applied a signal FORCEATDN which corresponds to a high logic value. In essence, it is as if the second input of the gate 17 were held at the same potential as the supply Vcc. The logic gate 17 has an output connected to the input of an inverter 18. The output of the inverter 18 is connected to the input of another inverter 19 and branches off toward a re-acknowledge circuit portion 15, described herein below. The inverter 19 output delivers the equalization signal EQLZ for the sense amplifier. In this invention, the output from the inverter 18 is advantageously the input of the re-acknowledge circuit portion 15 which comprises a monostable delay line 20 and a logic gate 21 of the NOR type with two inputs. The input signal to the portion 15, as provided by the output from the inverter 18, is applied to one of the logic NOR gate 21 inputs. The other input of the logic gate 21 receives the same signal through the delay line 20 comprised of a series of three inverters. A capacitor Cc is placed, toward ground, between the output of the first inverter and the input of the second inverter. The logic NOR gate 21 has an output connected directly to the control terminal of an N-channel MOS transistor denoted by MNX and serving a pull-down function. This transistor MNX has its source terminal connected to ground, GND, and its drain terminal connected to the ATD output node 12 at the first input of the logic OR gate 16. Advantageously, the transistor MNX has been selected with large dimensions so that it can dischagre the node 12 to ground fairly rapidly. Illustratively, the transistor MNX can bias the node 12 to ground within an equivalent time to those to be obtained normally in the presence of a concurrent switching of all of the n address input terminals or PADs. Briefly stated, the structure of the circuit portion 15 is input a signal corresponding to the equalization signal EQLZ, and is feedback connected to said AT output node 12 to drive the discharging of the node 12 with a predetermined delay from reception of the input signal. The main phases of the method according to the invention will now be reviewed in detail, from an initial state where at least one switching of the logic state of one of the address input terminals or PADs has occurred. The transistors MP1, MP2 and MP3 are highly resistive, and hence, hardly conductive. The transistor MP4 is always 'on' and holds the output node 12 of the circuit 1 at a high logic level, in co-operation with the stabilizing capacitor C. The signal ATD-LINE is active on the transistor MN1 as the result of a change in level occurring on any of the address inputs when this transistor is turned on and the resistive PMOS transistors are turned off. This allows the generation of an ATD pulse which has a falling edge toward a low logic level as shown in Figure 5A. At this point, the ATD output node 12 is low, and therefore, so is also the input of the logic gate 16, which will output a low value for the input of the NAND gate 17. The gate 17 output goes high, and therefore, the output of the inverter 18 is low. The equalization pulse EQLZ is generated at the output of the inverter 19 with a rising edge toward the high logic level, as shown in Figure 5B. The input of the re-acknowledge circuit portion 15 is low, because derived downstream from the inverter 18. Consequently, the output of the logic NOR gate 21 will go to a high logic level with a predetermined time delay set by the delay line 20. This allows the discharge transistor MNX to be turned on, thereby holding the ATD output node 12 low. As highlighted by the comparative plots of Figures 5A and 5B, even in the event of the ATD pulse presenting a spurious level transition due to the appearance of noise, for example, the equalization pulse would be unaffected by this phenomenon, and would retain a sufficient duration to correctly complete a reading phase. All this because the circuit portion 15 substantially allows the ATD pulse to be re-acknowledged even when this pulse is generated by a spurious input switching. The method and circuit of this invention do solve the technical problem and afford a number of advantages, such as: a stable pulse duration, and hence, uniform memory access times; substantial unaffection by spurious pulses due to noise, which no longer interfere with the completion of a correct data reading from the memory; independence of the number of the address input terminals which are switched.

Claims: A method for generating a pulse synchronization signal (ATD) in order to control the reading phase of memory cells in semiconductor integrated electronic memory devices, being of the type wherein said pulse signal (ATD) is generated upon sensing a change in the logic state on at least one of a plurality of address input terminals (PAD) of said memory cells to also generate an equalization signal (EQLZ) for a sense amplifier, characterized by that the logic state of said pulse signal (ATD) is re-acknowledged by means of a fed-back response having a predetermined time duration and being generated upon reception of a signal corresponding to said equalization signal (EQLZ). A semiconductor integrated electronic memory device comprising: an array of memory cells, row and column decoder circuits, a sense amplifier and a circuit (1) for generating a pulse synchronization signal (ATD) to control the reading phase of said memory cells of said memory device, being of the type which is linked operatively to the occurrence of a change in logic state on at least one of a plurality of address input terminals (PAD) of said memory cells, and comprising a structure of the NOR type placed between said address terminals and an output node (12) whence an equalization signal (EQLZ) is obtained for said sense amplifier, characterized in that it comprises a re-acknowledge circuit portion (15) which is input a signal corresponding to said equalization signal (EQLZ) and is feedback connected to said output node (12) to drive the discharging of said node (12) with a predetermined delay from the reception of the input signal. A memory device according to Claim 2, characterized in that said re-acknowledge circuit portion (15) comprises a logic gate (21) with two inputs, and a delay line (20), a first input of the logic gate (21) receiving directly the signal applied to the re-acknowledge portion (15) input, and the second input thereof receiving the same signal through said delay line (20). A memory device according to Claim 3, characterized in that said delay line (20) comprises a set of inverters. A memory device according to Claim 3, characterized in that said re-acknowledge circuit portion (15) further comprises a discharge transistor (MNX) connected between said output node (12) and a voltage reference (GND) at a low logic level, said transistor having a control terminal connected to the output of said logic gate (21). A memory device according to Claim 5, characterized in that said transistor (MNX) is of the NMOS type having a source terminal connected to ground. A memory device according to Claim 2, characterized in that the signal applied to the input of said re-acknowledge circuit portion (15) is the negated equalization signal (EQLZ). A memory device according to Claim 2, characterized in that said discharging is enabled with a delay from the rising edge of the equalization signal (EQLZ).

Inventors: BETTINI LUIGI, DEFENDI MARCO, VILLA CORRADO, BETTINI, LUIGI, DEFENDI, MARCO, VILLA, CORRADO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1996
Main classification: G11C8
IPC codes: G11C8, G11C11