Video decoder system

Abstract: A timing signal generator (12A) of an MPEG video decoder is responsive to a picture type signal (PT) for selectively generating one of a timing signal (K) for decoding I and P pictures and a timing signal (KB) for decoding a B picture within a predetermined period of time, permitting an increased speed for the B picture decoding.

Description: The present invention generally relates to a system for decoding an encoded video signal, and particularly, to a video decoder system for decoding a sequence of motion picture data, as it is encoded in accordance with an MPEG standard. Description of the Related Art For a standardization of an inter-frame prediction coding of video signals such as for a TV, some drafts had been prepared by the Moving Picture Expert Group and examined by the IS0/IEC, JTC1/SC2/WG8. Among them, that one which provides for a decoder system has been provided for as an MPEG1 standard (hereafter simply "MPEG") in the Recommendation ISO/IEC-11172-2 (1993). see Fig. 6 to 8 and Tables 1 to 4. An MPEG video decoder system is adapted to decode a code sequence comprising a sequence header (hereafter "SH") and a substantially independent group of pictures (hereafter "GOP"), as it is a sequence layer formatted to the MPEG by an MPEG video encoder system. Under the sequence layer, the MPEG provides for a GOP layer consisting of three types of pictures: an intra-frame coded picture (hereafter sometimes "I picture") assuring an independency of the GOP, an inter-frame forward-directionally predictive picture (hereafter sometimes "P picture") of which prediction needs a past I or P picture to be refererred to. and a bidirectionally predictive picture (hereafter sometimes "B picture") of which a prediction needs a past I or P picture and a future P picture to be referred to. In this respect, the MPEG video decoder system is necessarily adapted to decode any and all of the three types of pictures. A typical conventional video decoder system for decoding a GOP. i.e. an MPEG-formatted bitstream, has a decoding rate of one picture per one frame, whereas for the B picture to be scanned, the system employs a pair of scan memories either for writing data therein and the other for reading data therefrom, in an alternating manner. This is due to an inherent difference between an order of pictures to be processed and an order of reproduced pictures to be equivalent to that of original pictures. For example, letting N (number of pictures in a GOP to be processed) = 15, M (period for an occurrence of I or P picture in the GOP) = 3 and Ii, Pi or Bi be an I, P or B picture located at an arbitrary i-th position in a sequence of reproduced pictures (hereafter sometimes "outputs" or {0} ), such that: "B0-B1-I2-B3-B4-P5-B6-B7-P8-B9-B10-P11-B12-B13-P14". the GOP has a picture sequence such that : " I2 -B0-B1- P5 -B3-B4- P8 -B6-B7- P11 -B9-B10- P14 -B12-B13". In other words, assuming Ij, Pj or Bj be an I, P or B picture at an arbitrary j-th order to occur as a picture in a picture sequence of a GOP such that : "I0-B1-B2-P3-B4-B5-P6-B7-B8-P9-B10-B11-P12-B13-B14", a reproduced picture sequence {O} has corresponding pictures rearranged such that : "B1-B2- I0 -B4-B5- P3 -B7-B8- P6 -B10-B11- P9 -B13-B14- P12 ". It will be seen that letting k = [j/3], where [x] means a largest integer not exceeding x, it so follows that : GOP = {P(3k),B(3k+1),B(3k+2); k = 0 to 4 } and {0} = {B(3k+1),B(3k+2),P(3k); k = 0 to 4 }, providing that P0 = 10. Fig. 1 is a block diagram of a conventional video decoder system of such a type. The conventional system includes a demultiplexing decoder 1 for Huffman-decoding a sequence of input picture data DI, as they are MPEG-formatted, an inverse quantizer 2 for inverse-quantizing a set of Huffman-decoded data, and an inverse discrete cosine transform (hereafter "IDCT") section 3 for performing an IDCT of inverse-quantized data to provide a set of inverse-transformed data IT as ac-component data for P and B pictures or dc-component data for an I picture. Assuming a suffix "a" representing an ac-component (i. e. a pixel data difference between an original picture and a prediction picture) and a suffix "d" representing a dc-component (i.e. a pixel data of prediction picture), the data set IT has a picture sequence, e.g. : IT = {Pa(3k),Ba(3k+1),Ba(3k+2); k = 0 to 4}, providing that Pa(3k) = Ia(3k) = Id for k = and an ideal relationship between a coding and a decoding. The conventional system further includes an adder 4 for adding the inverse-transformed data IT to a set of type-dependent prediction data DR as dc-component data for the P and B pictures or zero-value data for the I picture, to provide a set of reproduced pixel data PI and PP on the I and P pictures to be alternatively stored in a pair of frame memories 8 and 9, and a set of reproduced pixel data PB on the B picture to be alternatively stored in a pair of scan memories 10 and 11. The data set DR should have a corresponding picture sequence to the data set IT, e.g. : DR = {Pd(3k),Bd(3k+1),Bd(3k+2); k = 0 to 4}, providing that Pd(3k) = Id(3k) = 0 for k = 0. Therefore, the adder 4 is provided with a prediction signal select switch Sw1 responsive to a select signal MT supplied as a macroblock level picture-type identifier from the decoder 1, for a selection among an inter-framer forward MC (motion compensation) prediction signal M1 from an MC unit 6 of a half-pel (i.e. half pixel) accuracy, an inter-frame backward MC prediction signal M2 from another MC unit 7 of a half-pel accuracy, an inter-frame bidirectional MC prediction signal MPI as a mean value from an average calculator 5. and an intra-frame prediction signal. The MC units 6 and 7 are responsive to a decoded motion vector signal MV supplied from the decoder 1, for executing half-pel MC's of I and/or P pictures P(3k) and P(3k+3) in a previous frame, as they are read from the frame memories 8 and 9, respectively. The system of Fig. 1 further includes a picture select switch Sw2 responsive to a select signal PT supplied as a picture sequence identifier from the decoder 1, for a selection among I and/or P pictures F1/0 and F2/0 and a B picture OB in a current frame, as they are each scanned. single or double, to be read from a corresponding one of the frame and scan memories 8 to 10, to be output as {0} . and a timing generator 12 for generating a timing signal K for a decoding control. Fig. 2 shows a time chart of various signals in the system of Fig. 1. assuming that M = 4. Letting Ip. Pq and Br be a p-th I picture, a q-th P picture and an r-th B picture in a GOP, it is now assumed that the input code sequence DI formatted to the MPEG has a picture sequence such that: "[1-P1-B1-B2-B3-P2-···". In accordance with the control by the timing signal K. there are MC-prediction decoded I. P and B pictures (i.e. PI, PP and PB), of which the I and P pictures (e.g. I1, P1, P2, ···) are written by a sequential line scan (hereafter "block scan") at a rate of 30 fields (30 frames) per second, alternately into the frame memories 8 and 9, wherefrom they are read by a two-to-one line jump scan (hereafter "raster scan") at a rate of 60 fields (30 frames) per second. alternately providing data F1, F2 corresponding to reference pictures for MC and data O (e.g. OI1). 0 (e.g. OP1) corresponding to reproduced pictures to be output. The B pictures (e.g. B1, B2, B3, ···) are alternately written to the scan memories 10 and 11, wherefrom they are alternately read as data OB (e.g. OB1, OB2, OB3) to be output. The MC-prediction decoding in MPEG (coding: 30 fields/s) is executed at a rate of one picture per frame. Therefore, as shown in Fig. 2, in application to an NTSC National Television Standards Comittee system (display: 60 fields/s), there occur overlaps (eg. TL1, TL2) between neighboring periods (e.g. Tb1, Tb2, Tb3) for processing data of B pictures (e.g. B1, B2, B3) to be each written to a scan memories 10, 11 and raster-scanned to be twice read therefrom to output. Namely, an end portion (e.g. TL1) of a current write/read process (e.g. Tb1) overlaps a head portion (e.g. TL1) of a subsequent write/read process (e.g. Tb2), which means that, if a single scan memory is provided, either process (Tb1 or Tb2) has to be put in a waiting state, or alternately the subsequent process (Tb2) has to be delayed to eliminate an overlap, and a next one (Tb3) thereto as well. To avoid such an undesirable delay accumulation, the conventional system employs the two scan memories 10 and 11 so that write/read operations can be made in an alternating manner, i.e. on one memory 10 for B1 picture, on the other memory 11 for B2 picture and on the memory 10 for B3 picture, outputting a picture sequence such that: "0I1-0I1-0B1-0B1-0B2-0B2-0B3-OB3-0P1-0P1-0P2-···". Necessary storage capacity for frame and scan memories (= 4 frames) is calculatable such that: 352 (dots) × 288 (lines) × 8 (bits) × 1.5 (Y+Cb+Cr) × 4 (frames) = 4,866,048 (bits). Like this, the conventional system needing two scan memories for B pictures tends to have a relatively large storage capacity, resulting in an enlarged expensive system. The present invention has been achieved with such points in mind. The article "A Video Decoder for H.261 Video Teleconferencing and MPEG Stored Interactive Video Applications" published in Digest of Technical Papers - ISSCC 1993, San Francisco, U.S.A., dated February 24 - 26, 1983, pages 34 to 35, authored by Brinthaupt D., et al deals with the construction of a video decoder comprising a symbol processor, a memory controller, a signal processor, a color converter, a lookup table, a pixel FIFO, a host/serial interface, a compressed data FIFO, and a variable length decoder performing Huffman decoding. It therefore is an object of the present invention to provide a video decoder system having a reduced storage capacity. Present invention is defined in the independent claim 1. The preferred embodiment is described in the dependent claim 2. To achieve the object, a genus of the present invention provides a video decoder system comprising a decoder means for Huffman-decoding a set of Huffman-coded picture data, an inverse quantization means for inverse-quantizing the Huffman-decoded data, an inverse discrete cosine transformation means for inverse-discrete-cosine-transforming the inverse-quantized data to provide a set of first data, an adder means responsive to a first selection signal from the decoder means, for adding a selected one of prediction data sets to the set of first data to provide a corresponding one of first, second and third picture data sets representing pictures of first, second and third types, respectively, first and second frame memories accessible for alternatively writing therein data of the first and second picture data sets in frames by a predetermined block scan and reading therefrom the same in a predetermined raster scan order, a third frame memory accessible for writing therein data of the third picture data set in frames by the predetermined block scan and reading therefrom the same in the predetermined raster scan order, and a timing signal generation means for generating a timing signal for a timing control of the video decoder system, wherein the timing signal generation means includes a timing signal select means responsive to a picture type signal indicating an arbitrary one of the first, second and third types for selectively generating one of a first said timing signal for decoding the first and second picture data sets and a second said timing signal for decoding the third picture data set within a predetermined period of time. Therefore, according to the genus of the invention, a video decoder system is permitted to have a single scan memory for effectively processing a third picture data set within a predetermined period of time, without a conventional need of delay. According to a species of the genus of the invention, the predetermined block scan comprises a sequential line scan. the predetermined raster scan comprises a two-to-one line jump scan, and the predetermined period comprises at least a half of a scan period of one of the frames minus a period for one line of the predetermined block scan. The objects, features and advantages of the present invention will become more apparent from consideration of the following detailed description, in conjunction with the accompanying drawings, in which: Fig. 1 is a block diagram of a conventional video decoder system; Fig. 2 is a time chart of various signals in the system of Fig. 1; Fig. 3 is a block diagram of a video decoder system according to an embodiment of the invention; Figs. 4 and 5 are time charts of various signals in the system of Fig. 3, respectively: Fig. 6 is an illustration of a layered structure of MPEG data: Fig. 7 is an illustration of a sequence of three types of pictures in a GOP of the MPEG data of Fig. 6: and Fig. 8 is a diagram describing directions of inter-frame MC predictions. There will be detailed below preferred embodiments of the present invention, with reference to the accompanying drawings. Like members are designated by like reference characters. Fig. 3 is a block diagram of a video decoder system according to an embodiment of the invention. The video decoder system of Fig. 3 comprises a decoder 1, an inverse quantizer 2, an IDCT section 3, an adder 4, an average calculator 5. a pair of MC units 6 and 7, a pair of frame memories 8 and 9, a single scan memory 10, and a pair of select switches Sw1 and Sw2, like the system of Fig. 1. The system of Fig. 3 further comprises a timing signal generator 12A including a timing selector 121 which is responsive to a picture type signal PT supplied from the decoder 1. representing an I, P or B picture type. for selectively generating one of a timing signal K for decoding I and P pictures in a similar manner to the system of Fig. 1 and a timing signal KB for decoding B pictures at a higher speed than the signal K. Fig. 4 and 5 show time charts of various signals in the system of Fig. 3, assuming that M = 4. Again letting Ip, Pq and Br be a p-th I picture, a q-th P picture and an r-th B picture in a GOP, it is assumed that an input code sequence DI formatted to the MPEG has a picture sequence such that: "f1-P1-B1-B2-B3-P2-···". Like the system of Fig. 1, in accordance with the control by the timing signal K, there are MC-prediction decoded I, P and B pictures (i.e. PI, PP and PB), of which the I and P pictures (e.g. I1, P1, P2, ···) are written by a block scan at a rate of 30 fields (30 frames) per second, alternately into the frame memories 8 and 9, wherefrom they are read by a raster scan at a rate of 60 fields (30 frames) per second, alternately providing data F1, F2 corresponding to reference pictures for MC and data 0 (e.g. OI1). 0 (e.g. OP1) corresponding to reproduced pictures to be output. The B pictures (e.g. B1, B2, B3, ···) are each written to the scan memory 10, wehrefrom it is read as data OB (e.g. OB1, OB2, OB3) to be output. When the picture type signal PT supplied from the decoder 1 is changed, indicating a B picture, the timing selector 121 responds thereto to generate the timing signal KB in place of the timing signal K, driving the system to execute a series of associated decoding steps of the B picture at a high speed, securing a necessary period (e.g. Tb1, Tb2, Tb3) for writing data of the B picture to the scan memory 10 and reading therefrom the same, to avoid an occurrence of an overlap time TL between neighboring periods (eg. Tb1-Tb2, Tb2-Tb3) for processing B pictures. Such effects may be achieved via an unshown CPU responsible for the timing signal KB. or directly the signal KB that may act on each associated section or unit. More specifically, as shown in Fig. 5, a B1 picture is written to the scan memory 10 in a timing designated by the timing signal K defining a normal decoding process time TD1. In a rear half of the writing time TD1, a raster scan starts reading data OB1 of the written B1 picture, for the first time. In concurrence therewith, the timing selector 121 of the timing signal generator 12A responding to the picture type signal PT, as it has been changed to be indicative of the B picture, switches the timing signal from K to KB, whereby a B2 picture is MC-prediction decoded at a high speed. As a result, upon completion of a second reading of the data OB1. a writing of the decoded B2 picture starts. To effectively avoid an overlap between neighboring B picture write/read process periods Tb1 and Tb2, letting BL be a fraction of a block scan that corresponds to one block line (i.e. one block line period), a writing of a B2 picture is required to start at least one BL before a first scan for reading data OB2 of the written B2 picture and end one BL before an end of the first reading of the B2 picture. In this respect, a blanking period BT, i.e. a data output interruption period between the second output of the data OB1 and the first output of the data OB2, is apparently longer than the one block line period BL, meeting a write start condition to the scan memory 10. Therefore, to avoid an overlap between neighboring B picture write/read process periods, a writing period TD2 of B2 picture as well as that TD3 of B3 picture may preferably be set to a half of one-frame period FT minus the one block line period BL, i.e. (1/2)FT - BL, whereto the timing signal KB is designed, permitting a high speed decoding process, so that the scan memory 10 mere one in number can serve for a complete write/read operation of B picture. Necessary storage capacity for frame and scan memories (= 3 frames) is calculatable such that: 352 (dots) × 288 (lines) × 8 (bits) × 1.5 (Y+Cb+Cr) × 3 (frames) = 3,649,536 (bits), so that a single 4M RAM affords a competent use. According to the embodiment of Fig. 3, therefore, a possible capacity reduction to a one-frame storage permits an effective reduction in a total memory capacity, resulting in a size-reduced inexpensive system. Incidentally, the MPEG is an internationally known standard. However, for a quick reference. Figs. 6 to 8 are appendixed hereto. Fig. 6 is an illustration of a layered structure of MPEG data, of which characteristics are listed in Tables I to 4 below. Fig. 7 is an illustration of a sequence of three types of pictures in a GOP of the MPEG data of Fig. 6. Fig. 8 is a diagram describing directions of inter-frame MC predictions.

Claims: A video decoder system comprising: a decoder means (1) for Huffman-decoding a set of Huffman-coded picture data; an inverse quantization means (2) for inverse-quantizing the Huffman-decoded data; an inverse discrete cosine transformation means (3) for inverse-discrete-cosine-transforming the inverse-quantized data to provide a set of first data (IT); an adder means (4) responsive to a first selection signal from the decoder means, for adding a selected one of prediction data sets (DR) to the set of first data (IT) to provide a corresponding one of first, second and third picture data sets (PI, PP, PB) representing pictures of first, second and third types (I , P, B) respectively, indicating intra-frames (I), forward- and bi-directionally predictive inter-frames (P, B), first and second frame memories (8, 9) accessible for alternatively writing therein data of the first and second picture data sets in frames by a predetermined block scan and reading therefrom the same in a predetermined raster scan order; wherein said video decoder system is characterized by comprising : only one third frame memory (10) accessible for writing therein data of the third picture data set in frames by the predetermined block scan and reading therefrom the same in the predetermined raster scan order; and a timing signal generation means (12A) for generating a timing signal for a timing control of the video decoder system, wherein: the timing signal generation means (12A) includes a timing signal select means (121) responsive to a picture type signal (PT) indicating an arbitrary one of the first, second and third types for selectively generating one of a first said timing signal (K) for decoding the first and second picture data sets (PI, PP) and a second said timing signal (KB) for decoding the third picture data set (PB) within a predetermined period (TD2) of time at a high speed, wherein said predetermined period (TD2) for a picture subsequent to a first picture (B1) of the third picture data set (PB) is such that an overlap between neighboring write/read process periods (Tb) for the pictures of the third data picture set (PB) is avoided. A video decoder system according to claim 1. wherein: the predetermined block scan comprises a sequential line scan: the predetermined raster scan comprises a two-to-one line jump scan; and the predetermined period (TD2) comprises at least a half of a scan period (FT) of one of the frames minus a period (BL) for one line of the predetermined block scan.

Inventors: KINOUCHI SHIGENORI, SAWADA AKIRA, KINOUCHI, SHIGENORI, SAWADA, AKIRA
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1996
Main classification: G06T9
IPC codes: H04N7, H04N5, G06T9