Loss-gain circuit and electronic device having such a circuit

Abstract: A loss-gain circuit for use in compensating variations in output frequency between different oscillators manufactured, for example, in a single batch of quartz oscillators. The circuit comprises an oscillator (1) for outputting a reference signal; a frequency divider (2) for frequency dividing the reference signal; loss gain means (4) for controlling within a first set range (A) the frequency divider (2) so as to correct deviation of the oscillator output from a desired standard; shift means (5) for changing the first set range (A) to a second set range (e.g. B) if the said deviation does not lie within the first set range (A).

Description: The present invention relates to a loss-gain circuit for example for performing fine adjustment of time precision and to an electronic device such as an electronic watch that achieves a high accuracy of time precision by using the said loss-gain circuit. Conventionally, there has been adopted a method for performing a logical loss-gain operation in accordance with one cycle of a frequency division clock using a circuit such as shown in Fig. 6, in order to compensate deviation of oscillation frequencies caused due to the uneven quality of quartz oscillators used as the master oscillator of an oscillation circuit. The logical loss-gain operation will now be briefly described with reference to Fig. 6 and Fig. 7 that is a timing chart. A reference clock (a) output from a quartz oscillator 601 is input to a frequency division circuit constituted by T flip-flops (which will be referred to as TFFs hereinafter) 602 to 608 to be sequentially frequency-divided. When the logical loss-gain operation is not performed, the clock (a) is subjected to precise 1/2 frequency division as shown by a section extending from a timing A to another timing B as shown in Fig. 7. Outputs from OR gates 609 to 612, which receive a logical loss-gain control signal VCWX and logical loss-gain data signals VCWD1 to VCWD4, are connected to set inputs SX of the TFFs 603 to 606. Outputs of an OR gate 613 to which VCWD5 and VCWX are input is connected with reset inputs RX of the TFFs 607 and 608. The logical loss-gain operation is usually performed at 10-second intervals and, at this time, a pulse signal VCWX at "L" level is generated in synchronism with a first transition of a Q output of the TFF 607 at the timing B shown in Fig. 7. A pulse width of the signal VCWX is half of a cycle of a reference clock. When predetermined any of the TFFs 603 to 608 are forcibly preset by the "L" level pulse signal VCWX, a predetermined quantity of the logical loss-gain operation is carried out. For example, if loss-gain data VCDW1 to VCWD5 are at "L", "H", "H", "H" and "H" levels, respectively, output signals c, d, e, f and g of the OR gates 609 to 612 are output in synchronism with the signal VCWX at "L", "H", "H", "H" and "H" levels, respectively. The "L" level pulse signal is applied to the set input SX of the TFF 603, the Q output of the TFF 603 is forcibly turned to "H" level (timing B). Since a frequency division clock b of the TFF 602 is continuously input to the TFF 603, a Q output signal of the TFF 603 displays its last transition at a timing C shown in Fig. 7, and the regular 1/2 frequency division is thereafter carried out. With this operation, one section for the Q output from the TFF 603 at "L" level, i.e., a time corresponding to one cycle of the frequency division clock of the TFF 602 is omitted. As viewed from the timing at which the first transition of the Q output signal from the TFF 606 is demonstrated, the signal should have shown its first transition at a timing E in Fig. 7, but it actually displays its first transition at a timing D in Fig. 7. Therefore, the loss-gain operation was consequently carried out for a time corresponding to one cycle of the Q output from the TFF 602 in the advance direction. There has been known that the logical loss-gain operation in delay or advance direction is carried out by adequately operating the state of the frequency division circuit at a predetermined timing in accordance with the above-described method. In the prior art loss-gain method, since the loss-gain range or loss-gain resolution is determined by a number of signal lines prepared as the logical loss-gain data input means, a large amount of quartz oscillators whose oscillation frequencies deviate beyond the loss-gain range of the logical loss-gain circuit are generated when unevenness in quality of quartz oscillators made during manufacturing process is large. For example, when a quartz oscillator of 32kHz is used, frequency-dividing stages for outputting 8kHz, 4kHz, 2kHz, 1kHz and 512Hz are controlled by five logical loss-gain data signals to perform the logical loss-gain operation, the loss-gain range corresponds to ±8.4375sec/day (±97.665PPM). The quartz oscillator having the oscillation frequency deviation beyond this range can not be, therefore, compensated by the above-mentioned logical loss-gain circuit, and the yield of the quartz oscillator is disadvantageously decreased. When enlarging the loss-gain range by the prior art logical loss-gain method, it is possible to adopt a method by which a number of logical loss-gain data signals are increased, but the number of input terminals of an IC must be correspondingly increased and the space of the IC is thereby greatly enlarged, leading to increased cost. Further, with the prior art logical loss-gain method enlarging the loss-gain range without increasing the number of loss-gain signals reduces the loss-gain resolution and it is relatively more difficult to make adjustments to obtain a predetermined rate. US 4413350 discloses a clock rate generator which may be programmed to provide an output frequency that is any fraction of the input frequency. A range select switch is set so as to cause a counter to be selectively reset within one of three count ranges. The output frequency, which is any fraction of the input frequency, is controlled by bit patterns stored in a programmable memory. US 4378167 discloses a time correction circuit for an electronic timepiece. A high frequency reference signal is fed to a divider network, where it is serially divided by a serial chain of divider stages. Correction data is periodically applied to selected divider stages to provide coarse or fine adjustment to the output frequency depending upon the number of divider stages which are corrected and their location in the serial chain. US 4101838 discloses a clock pulse generator circuit having a frequency divider including a number of division stages for frequency dividing the output of a pulse generator. The circuit includes pulse adders and pulse subtractors for respectively adding and subtracting pulses at selected division stages in order to adjust the clock pulse frequency. US 4254494 describes a system for correcting the accuracy of a reference signal in an electronic timepiece. A reference frequency from an oscillator is frequency divided and any deviation of the reference signal frequency from a standard signal frequency is corrected by periodically applying a low frequency signal. In one aspect the present invention enables the implementation of a logical loss-gain circuit having a large adjustment range without increasing the number of terminals of an IC so that a quartz oscillator having a large oscillation frequency deviation can be used successfully. According to a first aspect of the present invention there is provided a loss-gain circuit comprising: an oscillator for outputting a reference signal; a frequency divider for frequency dividing the reference signal; loss gain means for controlling within a first set range the frequency divider so as to correct deviation of the oscillator output from a desired standard; shift means for changing the first set range to a second set range if the said deviation does not lie within the first set range. According to another aspect of the present invention there is provided an electronic device having a loss-gain circuit, according to the first aspect of the invention, wherein the frequency divider divides the reference signal to generate a time signal and further comprising, a display driving means for generating a display signal based on the time signal, and display means for receiving the display signal so as to display time information. Embodiments of the present invention will now be described by way of example only and with reference to the accompanying drawings, in which:- Fig. 1 is a function block circuit diagram showing an example of a basic configuration according to the present invention; Fig. 2 is a circuit diagram showing an embodiment of a logical loss-gain circuit according to the present invention; Fig. 3 is a view showing loss-gain modes and loss-gain ranges of the embodiment of the logical loss-gain circuit according to the present invention; Figs. 4 are timing charts for the logical loss-gain operation of the embodiment of the logical loss-gain circuit according to the present invention; Fig. 5 is a view showing an example of the oscillation frequency distribution of the quartz crystal and the logical loss-gain range; Fig. 6 is a circuit diagram showing a prior art logical loss-gain circuit; and Fig. 7 is a timing chart for the logical loss-gain operation of a prior art logical loss-gain circuit. An embodiment of the present invention will now be described with reference to Fig. 1. An oscillating means 1 having an oscillator of such as a quartz crystal as a master oscillation outputs a reference clock, and a frequency dividing means 2 sequentially subjects the reference clock to 1/2 frequency division. A logic loss-gain data setting means 3 sets logic loss-gain data for compensating a deviation of the oscillation frequency of the oscillator by a logic circuit. A logic loss-gain means 4 operates a state of the frequency dividing means 2 based on the thus-set logic loss-gain data at predetermined periods and controls in such a manner that a cycle of a frequency division output signal of the frequency dividing means 2 coincides with a predetermined cycle. A logic loss-gain shift means 5 shifts an operating logic loss-gain range of the loss-gain means in accordance with an oscillation frequency characteristic when the cycle of the frequency division output signal requires adjustment from outside the initial operating loss-gain range. With this logic loss-gain shift means 5, a quartz oscillator group having a large deviation of oscillation frequencies, that was hard to adjust and had a deteriorated yield, can now be adjusted by logic loss-gain. Determining the frequency division output signal of the frequency dividing means 2 as a time reference signal, a display driving means 6 generates a display drive output signal for driving hands or a display means 7 including an optical display unit such as a liquid crystal display unit or a light-emitting diode, based on the time reference signal. With such an arrangement, it is possible to obtain an electronic device such as an electronic watch that can precisely adjust time information such as time or lapsed time by a means like a logical circuit. Referring to Fig. 2, a quartz oscillating circuit 293 outputs a reference clock signal. In this embodiment, a frequency of the reference clock is 32kHz. A frequency dividing circuit 298 is constituted by 10 stages of TFFs 201 to 210. In order to synthesise a control signal for operating a display drive circuit or the like, a few stages of TFFs are actually connected to a rear side of the TFF 210, but they are omitted herein. A logical loss-gain circuit 299 receives signals of VCWD1 to VCWD5 output from a logical loss-gain data holding circuit 294 and VCWX that is a control signal synthesised from an output signal of the frequency dividing circuit 298, and outputs logical loss-gain operation signals S8KX, S4KX, S2KX and S1KX for presetting the TFFs 202 to 210 in the frequency dividing circuit 298 and logical loss-gain shift signals S512X, S256X, S 128X and R64X in synchronism with VCWX when one or more of signals VCWD1 to VCWD5 are at "L" level. A mask option switch 297 is constituted by input signals VCWH, VCWL, VCWPZ and VCWPZX and logical loss-gain shift signals S512X, S256X, S128X and R64X. Each signal line of the logical loss-gain shift signals S512X, S256X, S128X and R64X is connectable to each signal line of input signals VCWH, VCWL, VCWPZ and VCWPZX in the IC manufacturing process. Fig. 3 shows modes of the loss-gain range that can be selected by the connection method for the mask option switch 297. A loss-gain amount is shown with 8.4375 sec/day as a unit. In case of a mode A, the loss-gain range corresponds to units of ±1 (±8.4375 sec/day) and is equal to the loss-gain range described in connection with the prior art configuration. Further, it is possible to arbitrarily set the loss-gain range from a mode K of -6 through -4 units to a mode F of +4 through +6 units in accordance with dispersion in frequencies of quartz oscillators by adequately selecting the mask option switch 297. For example, when the signal lines of the logical loss-gain shift signals S512X, S256X, S128X and R64X are all connected to a signal line of VCWPZ as indicated by solid circles in the mask option switch 297, the loss-gain range corresponds to the mode A in Fig. 3. Furthermore, when the signal lines of the logical loss-gain shift signals S512X, S256X, S128X and R64X are connected to the signal lines of the input signals VCWPZX, VCWH, VCWL and VCWH, respectively, as indicated by hollow circles in the mask option switch 297, the loss-gain range corresponds to the mode F in Fig. 3. Fig. 4 is a timing chart for the logical loss-gain operation in the present embodiment, wherein Fig. 4(a) shows the case where the loss-gain range corresponds to the mode A and the logical loss-gain data signals VCWD1, VCWD2, VCWD3 and VCWD4 are at "H", "H", "L" and "L" levels, respectively. In regard of the logical loss-gain data signals, values set from a non-illustrated external terminal or the like are held by the logical loss-gain data holding circuit 294 shown in Fig. 2. As to the signal VCWX, a pulse at "L" level is input at a timing A synchronised with a first transition of Q64 at 10-second periods. A logical circuit block 295 is constituted by OR gates 211,212, 213 and 214 and outputs data of the signals VCWD1, VCWD2, VCWD3 and VCWD4 as logical loss-gain operation signals S8KX, S4KX, S2KX and S1KX, respectively, in synchronism with the signal VCWX. The logical circuit block 296 is made up of OR gates 215 and 216 and a NAND gate 217, and outputs data of the signal VCWD5 as VCWPZ and an inverted value of data of the signal VCWD5 as VCWPZX in synchronism with the signal VCWX. The VCWL outputs the "L" level in synchronism with the signal VCWX, and the VCWH is constantly at "H" level. The logical loss-gain shift signals S512X, S256X, S128X and R64X are dependant on the signals VCWH, VCWL, VCWPZ and VCWPZX in accordance with the connection state of the mask option switch 297. When the logical loss-gain operation signals S8KX, S4KX, S2KX and S1KX and the logical loss-gain shift signals S512X, S256X and S128X output pulse signals at "L" level, the TFFs 202, 203, 204, 205, 206, 207 and 208 are preset, while when the R64X outputs a pulse signal at "L" level, the TFFs 209 and 210 are reset to perform the logical loss-gain operation. For example, in case of the mode A where the logical loss-gain data signals VCWD1, VCWD2, VCWD3, VCWD4 and VCWD5 are at "H", "H", "L", "L" and "H" levels, respectively, and the mask option switch is set in such a manner that the logical loss-gain shift signals S512X, S256X, S128X and R64X are all connected with the VCWPZ, the logical loss-gain operation is performed in accordance with a timing chart illustrated in Fig. 4(a). That is, the TFFs 204 and 205 are set by the pulse signal VCWX of "L" level that is output in synchronism with a first transition (timing A) of Q64 in Fig. 4(a), and the Q2K and Q1K enter "H" level. The regular frequency division operation is thereafter continued and Q64 shows its last transition at the timing B. Moreover, in case of the mode F where the logical loss-gain shift signals S512X, S256X, S128X and R64X are connected to VCWPZX, VCWH, VCWL and VCWH, respectively, the logical loss-gain operation is carried out in accordance with the timing chart of Fig. 4(b). In other words, TFFs 206 and 208 are set simultaneously with TFFs 204 and 205 by the pulse signal VCWX of "L" level that is output in synchronism with a first transition (timing C) of Q64 in Fig. 4(b), and Q512 and Q128, as well as Q2K and Q1K, are turned to "H" level. The regular frequency division operation is thereafter continued and Q64 displays its last transition at the timing D. In this case, the last transition obtained at the timing D is ahead of that at the timing B by five cycles, and this difference corresponds to a shift amount of the loss-gain ranges of the mode A and the mode F. Fig. 5 is a view showing a distribution of the oscillation frequencies of the quartz oscillator group obtained during a regular manufacturing process. In accordance with the distribution of the oscillation frequencies, when a quartz oscillator having a oscillation frequency being out of the logical loss-gain range in one of the illustrated logical loss-gain modes is adjusted in another logical loss-gain mode, use of such a quartz oscillator that can not be used in the prior art configuration is enabled. As a result, availability of the quartz oscillator can be improved and reduction in the overall cost can be realised. The present invention as described in the foregoing has the following advantages. Since the logical loss-gain range can be shifted by the logical loss-gain shift means in accordance with the oscillation frequencies of the quartz oscillators, the present invention can compensate for nearly all of the quartz oscillators even when using a quartz oscillator group having a large deviation of the oscillation frequencies caused by uneven quality generated during the manufacturing process, thereby reducing the overall cost. In addition, when the logical loss-gain shift means is incorporated into an IC, the mask option switch can shift the logical loss-gain range without increasing the number of terminals of the IC, thereby conserving space and saving cost.

Claims: A loss-gain circuit comprising: an oscillator (1) for outputting a reference signal; a frequency divider (2) for frequency dividing the reference signal; loss gain means (4) for controlling within a first set range (A) the frequency divider (2) so as to correct deviation of the oscillator output from a desired standard; characterised by shift means (5) for changing the first set range (A) to a second set range (e.g. B) if the said deviation does not lie within the first set range (A). A loss-gain circuit as claimed in claim 1, wherein the shift means (5) is capable of changing the first set range (A) to any of a plurality of second set ranges (B to K). A loss-gain circuit as claimed in claim 1 or claim 2, wherein the first set range (A) and the second set range (e.g. B) or ranges are of equal span. A loss-gain circuit as claimed in any preceding claim, wherein the first set range (A) and the second set range (e.g. B) or ranges have overlapping spans. A loss-gain circuit as claimed in any preceding claim, further comprising data storage means (3) storing data used for operation of the loss-gain means (4) and storing data used for operation of the shift means (5). An electronic device having a loss-gain circuit as claimed in any preceding claim, characterised in that the frequency divider (2) divides the reference signal to generate a time signal and further comprising, a display driving means (6) for generating a display signal based on the time signal, and display means (7) for receiving the display signal so as to display time information. A logical loss-gain circuit comprising: an oscillating means (293) for outputting a reference clock; a frequency dividing means (298) for receiving and sequentially frequency-dividing the reference clock; a logical loss-gain data setting means (294) for setting predetermined logical loss-gain data (VCWD1 to VCWD5); a logical loss-gain means (299) for operating a state of the frequency dividing means (298) at predetermined periods based on the logical loss-gain data (VCWD1 to VCWD5) set in the logical loss-gain data setting means (294); characterised by a logical loss-gain shift means (295) for arbitrarily shifting a loss-gain range of the logical loss-gain means (299).

Inventors: KATO KAZUO, KATO, KAZUO
Applicants: SEIKO INSTR INC, SEIKO INSTRUMENTS INC.
Application year: 1996
Main classification: G04G3
IPC codes: G04G3, H03K23, H03L7