A CIRCUIT PROVIDED WITH FACILITIES FOR IDDQ-TESTING OF A BIAS GENERATOR

Abstract: A bias generator is tested in an IDDQ-scheme by applying each respective one of the bias voltages to a respective PFET that is individually gated by a respective NFET. This permits measuring the quiescent currents. Any deviation in the bias voltages is translated into a deviation of the quiescent current.

Description: A circuit provided with facilities for I DDQ -testing of a bias generator FIELD OF THE INVENTION The invention relates to a large scale integrated electronic circuit comprising analog circuit elements and multiple nodes interconnected to said circuitry for on said nodes receiving various mutually independent biasing voltages. BACKGROUND ART A bias generator is an integral and well known building block of many large scale integrated electronic circuits. Generally, a bias generator is designed to provide one or more stable, time-invariant voltages for controlling electronic circuits like amplifiers, comparators and oscillators. A typical example of such a circuit is a parallel or so-called flash A/D converter. In a parallel A/D converter an analog input signal is applied to a plurality of comparators. Each comparator also receives an input reference voltage that is different from the one received by another comparator. The bias generator maintains the operating points of these comparators stable to ensure an optimal performance in terms of gain, resolving time, operational frequency, metastability, dynamic range and other parameters that are relevant to the operation of the converter. OBJECT OF THE INVENTION Conventional tests conducted on circuits such as the flash A/D converter are unable to detect various malfunctions in the bias generators, such as manufacturing process defects and parametric process variations. Detection of these malfunctions would require unconventional, tedious and long test procedures. It is therefore, inter alia, an object of the invention to provide a design-for-testability facility with respect to the bias generator. SUMMARY OF THE INVENTION To this end, the invention provides an electronic circuit as specified in the preamble, characterized in that the electronic circuit contains internal test circuitry for testing a plurality of said biasing voltages, in that for various ones of said nodes voltage-to-current converter means have been provided for converting the respectively associated biasing voltage into a quiescent current signal, conditionally to an enabling signal on an associated switch, and in that various such voltage-to-current converter means are arranged for feeding amalgamating circuitry, for therein producing, conditionally to one or more correct biasing voltages on the associated node or nodes, a predetermined quiescent current. The bias signal of a defect-free bias generator gives rise to a quiescent current in a current path with a magnitude that is known in advance, such as through computation. The current path allows measuring the actual magnitude of the quiescent current. If the presence of a defect in the bias generator influences the bias signal value, this defect is represented by a quiescent cuπent whose magnitude deviates from the theoretical magnitude. Testing through measuring a quiescent cuπent, also refeπed to as I DDQ -testing, is becoming an increasingly important test tool. The testing of the bias generator according to the invention fits in nicely with I DDQ strategies. The amalgamating feature can be used to dimin¬ ish the number of required parts, and therefore, the amount of circuit area. Advantageously, said switch is privy to said voltage-to-cuπent converter, for allowing said cuπent to be measured in an amalgamating time divisional multiplex organization with respect to various ones of said voltage-to-current converters. The sharing of the elements that actually measure the various cuπents diminishes the circuit area that is required for the testing. Advantageously, said switch is instantaneously shared among a plurality of said voltage-to-current converter means for amalgamating various said cuπents through addition thereof. This further diminishes the necessary circuit area. The invention is in particular, but not exclusively, relevant to A/D converters. Further advantageous aspects of the invention are recited in dependent Claims. BRIEF DESCRIPTION OF THE DRAWING The invention is explained below in further detail and by way of example with reference to the accompanying drawing, wherein: Figure 1 is a diagram of a first electronic circuit with a bias generator and a plurality of cuπent paths; and Figure 2 is a diagram of a second electronic circuit with a bias generator and current paths. Throughout the drawing like reference symbols indicate similar or corresponding features. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS Figure 1 is a diagram of an electronic circuit 100 that may include an A/D converter. The circuit comprises a first supply node 102 for connection to a first supply voltage (V dd ), a second supply node 104 for connection to a second supply voltage (V„), a bias generator 106 and a plurality of cuπent paths 108, 110, 112 and 114. Bias generator 106 is operative to provide four bias signals, namely, stpl (3.2 Volts), stp2 (3.2 Volts), stp3 (3.4 Volts) and V b s (2.3 Volts), wherein the values between parentheses indicate ideal values. In this example, stpl and stp2 have the same value, e.g, because they are generated separately so as not to overload generator 106. Each respective one of cuπent paths 108-114 comprises a series arrangement of a unique one of PFETs 116, 118, 120 and 122, and a respective one of NFETs 124, 126, 128 and 130. Each respective one of the bias signals controls a respective one of PFETs 116-122. In this way, each of PFETs 116-122 functions as a voltage-to-current converter or as a voltage controlled current source. Each respective one of NFETs 124-130 receives a respective one of enable signals bl, b2, b3 and b4. Each of NFETs 124-130 functions as a switch. This scheme permits measurement of a quiescent current I through each path individually through amalgamating in a time division multiplex organization. Altematively, the amalgamating is by adding the various cuπents that run in parallel through multiple paths. To this end, for example, bonding pads 132 and 134 are provided that are normally disconnected in operational use of circuit 100. During testing, a current measuring device 136 is connected between pads 132 and 134 to perform the quiescent cuπent test. In this way, the voltages on nodes 146,148, 150, 152 can be checked versus their intended values. These voltages can be used in a flash A/D converter contained in circuit block 80 that has only been indicated in a symbolic manner. For brevity, further and altemative features of this block, that may contain amplifiers, comparators, oscillators, D/A converters and various other elements, have been suppressed for clarity. Also the sequencing of control electrodes bl..b4 has not been shown, inasmuch as such would be clear to implement by a skilled art person. As is clear, a complementary embodiment is feasible wherein NFETs are used as voltage-to-current converters and PFETs as switches. A hybrid embodiment is possible as well, wherein some of the voltage-to-cuπent converters are PFETs and others are NFETs, and wherein some of the switches are PFETs and others NFETs. Altematively, transistors of the same conductivity type can be used as both switch and voltage-to-cuπent converter. Whichever configuration is chosen, may depends on the magnitude of the individual bias signals. Figure 2 is a diagram of an electronic circuit 200 largely similar to circuit 100, but now with a single switch 202 in series with a parallel arrangement of voltage-to-cuπent converters 116-122. An enable signal "b" controls switch 202. This configuration enables measuring the aggregate cuπent I through the parallel arrangement. Here, the amalgamating is necessarily through adding of the various cuπents. It should be clear that an intermediate arrangement between Figures 1 and 2 would be feasible.

Claims: CLAIMS: 1. A large scale integrated electronic circuit comprising analog circuit elements and multiple nodes interconnected to said circuitry for on said nodes receiving various mutually independent biasing voltages, characterized in that the electronic circuit contains intemal test circuitry for testing a plurality of said biasing voltages, in that for various ones of said nodes voltage-to- current converter means have been provided for converting the respectively associated biasing voltage into a quiescent cuπent signal, conditionally to an enabling signal on an associated switch, and in that various such voltage-to-current converter means are arranged for feeding amalgamating circuitry, for therein producing, conditionally to one or more correct biasing voltages on the associated node or nodes, a predetermined quiescent current. 2. A circuit as claimed in Claim 1 , wherein said switch is privy to said voltage-to- current converter, for allowing said cuπent to be measured in an amalgamating time divisional multiplex organization with respect to various ones of said voltage-to-cuπent converters. 3. A circuit as claimed in Claim 1, wherein said switch is instantaneously shared among a plurality of said voltage-to-cuπent converter means for amalgamating various said currents through addition thereof. 4. A circuit as claimed in Claims 1, 2 or 3, wherein said voltage to cuπent converter means comprise a transistor that is controlled by an associated biasing voltage, and which transistor is arranged in series with said associated switch. 5. A circuit as claimed in any of Claims 1 to 4, and furthermore comprising D/A and/or A/D conversion circuitry, that is directly interconnected to one or more of said nodes for testing.

Inventors: ATZEMA BOTJO, SACHDEV MANOJ, ATZEMA, BOTJO, SACHDEV, MANOJ
Applicants: PHILIPS ELECTRONICS NV, PHILIPS NORDEN AB, PHILIPS ELECTRONICS N.V.
Application year: 1996
Main classification: G01R31
IPC codes: G01R31, G05F3, H01L21, H01L27, H03M1