Method and circuit for controlling the charge of a bootstrap capacitor in a switching step-down regulator

Abstract: The invention concerns a method of controlling the charging of a bootstrap capacitance (C BOOT ) incorporated into a switching regulator (2) of a power transistor (M1). The method consists of carrying out, at each switching cycle, a comparison between the voltage value (V CBOOT ) at the bootstrap capacitance (C BOOT ) and a predetermined threshold voltage (Vs), to change the mode of operation of the regulator following said comparison. More particularly, the control on the transistor (M1) is taken off the regulator (2) when the voltage (V CBOOT ) at the bootstrap capacitance (C BOOT ) is lower than the threshold voltage (Vs), while the transistor (M1) is forced into the "on" state through a full cycle. In this way, the minimum current (I MIN ) to operate the regulator (2) can be minimised.

Description: Field of the Invention This invention relates to a method of controlling the charging of a bootstrap capacitance which is incorporated into a switching regulator of a power transistor connected to an electric load. In particular, the invention relates to a method of controlling the operation of step-down switching regulators which use a bootstrap capacitance for charging an NMOS switch whenever a small current is output by the regulator. The invention also concerns a circuit for controlling the charging of a bootstrap capacitance and implementing the method. As is well known, many applications in the electric industry require that the value of a current through an electric load be regulated. The most commonly adopted solution, for regulating a lower output voltage than the input voltage, is to use a switching regulator of the step-down type. In this case, the current through the electric load is regulated by means of a power transistor which is controlled from a driver circuit. The state of the art favours the use of MOS transistors as the power switches, in preference to bipolar transistors. The provision of a MOS transistor affords improved efficiency for the regulator as a whole; it also involves, however, added circuit complexity in that a second power supply, higher than that to be applied to the drain terminal, must be provided for charging the gate terminal of the MOS transistor. Background Art Several prior solutions are available for producing the aforementioned second power supply, of which the most commonly adopted one provides for the use of a bootstrap capacitance which can be re-charged during the conduction phase of a recirculation diode. Other, and more complex, solutions, such as the provision of a step-up circuit for producing the power supply sought, involve an increased number of outward connections for the integrated circuit, It has also been proposed of using an internal charge pump, but this solution cannot provide the amount of charge required for fast changeovers of the MOS switch. In the respect of the first-mentioned solution, the use of a bootstrap capacitance restricts the operational conditions for the switching regulator. In fact, where the voltage value to be regulated exceeds the difference between the voltage value to which the bootstrap capacitance is charged and the turn-on threshold of the MOS switch, the regulating system can only operate properly if the load output current is larger than a minimum current I MIN . To illustrate this conception, a review of the operation of a switching regulator of the step-down type may be helpful. The bootstrap capacitance is powered from a voltage generator V REG having a diode in series therewith, as shown in the accompanying Figure 1. A MOS transistor M1 operates as a switch to regulate the current being supplied to an electric load LOAD. For the purpose, the switch M1 has a first conduction terminal connected to a supply voltage reference Vcc, and a second conduction terminal OUT connected to the load LOAD through an inductance L. A diode D1 is connected between the terminal OUT and one end of the load LOAD taken to a ground GND. A capacitor C1 is provided in parallel with the load LOAD. The gate terminal of the switch M1 is connected to the output of a driver circuit DRIVER. With the switch M1 in the off state, the current to the inductance L flows through the diode D1, presently conducting, so that the voltage at the node OUT will turn negative and be equal to -V D1 . Under this condition, the voltage generator V REG is able to deliver a current for charging the bootstrap capacitance C BOOT . The maximum voltage V CBOOT at that capacitance is given by: V CBOOTMAX = V REG - V D2 - (-V D1 ) ≈ V REG With D1 conducting, V REG will deliver a current until V CBOOT becomes less than.V CBOOTMAX In operation at a small load current, there is a time period T1 when the current IL at the inductance L becomes zero, as shown in Figure 2C. In this case, at the end of the discharge transient, the voltage V OUT at the node OUT becomes equal to Vload, as shown in Figure 2B. In this situation, the bootstrap capacitance can only be charged during the time when the recirculation diode D1 is conducting, as shown in Figure 3D. If the average current demanded by the load is a very small one, the pulses SWITCH for turning on the switch M1 are quite narrow and have a very large period, as shown in Figure 3A, because a small current will suffice to regulate the output voltage Vload. At the end of the turn-on pulse, following a short time period of conduction of the diode D1 when the bootstrap capacitance C BOOT is being charged by the generator V REG , the inductance current IL drops to zero, and the voltage V OUT at the node OUT becomes equal to Vload. Under this condition, the static consumption Idriver of the driver stage results in the bootstrap capacitance being gradually discharged. This discharge continues until the voltage V CBOOT across the capacitance equals the difference between V REG - V D2 and Vload, as shown in Figure 3D. Under these conditions, in order for the switch M1 to change over at the next turn-on pulse, the voltage at the bootstrap capacitance should be higher than the turn-on threshold V TH of the NMOS transistor M1, i.e.: V REG - V D2 - Vload > V TH Given that V MAX = V REG - V D2 - V TH , if the voltage to be regulated is higher than V MAX , then the switching regulator will only operate properly at larger currents than a minimum value I MIN which is proportional to the consumption of the driver circuit. With currents below a value I MIN , the output voltage Vload will equal V MAX . In actual constructions of step-down switching regulators, the critical current for proper operation of the circuit is much larger than the theoretical value of I MIN , because the considerations made above takes no account of the lessthan-ideal nature of the voltage generator V REG . In fact, no real generator would be able to deliver its maximum current at once, especially when constructed for a small drop, as is usual in most instances. By way of example, Figure 4 shows the current I(V REG ) to be delivered by the generator V REG upon the diode D1 being turned on. In a condition of minimum load, the switch M1 would be held "on" for a very short time, and the amount of charge fed to the bootstrap capacitance from V REG would be less than optimum, as shown in figure 5. The triangular areas in Figure 5 represent the amounts of charge. A European application 89119160.3 for a reference voltage generating device for a switching circuit that includes a capacitive bootstrap circuit was deposited in the name of the applicant. That device ensures a correct driving voltage for a bootstrap circuit which allows an output stage to generate and supply a high-amplitude voltage signal at the output. While similar in some respects to the background of this invention, that device does not directly address the underlying technical problem of this invention. The underlying technical problem of this invention is to provide a method for optimising the charging of a bootstrap capacitance during operation of a switching circuit of the step-down type, which method can obviate the drawbacks with which prior switching regulators have been beset. Summary of the Invention The solution idea on which this invention stands is that of so modifying the drive signal being applied to the transistor switch as to have the latter turned on at less frequent intervals, but held in the "on" state for a longer time. In this way, the charge of the bootstrap capacitance can be optimised, enabling the generator V REG to deliver its maximum current and, consequently, lowering the minimum value of the load current I MIN . In addition, the overall efficiency of the system can be improved because the gate terminal of the switch is charged less frequently. Based on this solution idea, the technical problem is solved by a method as previously indicated and defined in the characterising portions of Claim 1 and following. The technical problem is also solved by a switching regulator as previously indicated and defined in the characterising portion of Claim 5. The features and advantages of the method and circuit according to the invention will be apparent from the following description of embodiments thereof, given by way of example with reference to the accompanying drawings. Brief Description of the Drawings Figure 1 is a diagrammatic view of a switching regulator according to the prior art. Figures 2A, 2B and 2C show respective graphs, plotted on the same time base, of voltage and current signals which are present in the regulator of Figure 1 during operation at a small load current. Figures 3A, 3B, 3C, 3D and 3E show respective graphs, on the same time base, of voltage and current signals which are present in the regulator of Figure 1 in another condition of its operation. Figures 4A and 4B show respective graphs, on the same time base, of more voltage and current signals appearing in the regulator of Figure 1. Figures 5A and 5B show respective graphs, on the same time base, of the voltage and current signals in Figure 4 under a different condition of operation of the regulator of Figure 1. Figure 6 is a flow chart illustrating the regulating method of this invention. Figures 7A and 7B show respective graphs, plotted on the same time base, of voltage and current signals which are present in a regulator controlled by the method of this invention. Figure 8 is a diagrammatic view of a control circuit for implementing the method of this invention. Detailed Description Referring to the drawing figures, in particular to the example shown in Figure 6, generally designated 1 is a flow chart illustrating the control method of this invention. The inventive method uses a comparator to compare, at each switching cycle, the voltage at this bootstrap capacitance with a predetermined threshold voltage Vs. When the voltage at one input of the comparator is higher than the threshold Vs, the regulator is allowed to operate as normal; otherwise, control of the transistor switch is taken off the regulator and the switch is forced into the "on" state for a full cycle. In essence, the switching regulator is operated in two distinct modes. When the voltage at the bootstrap capacitance is below the threshold Vs of the comparator, the regulating loop is no longer in control, and the switch will be forced into the "on" state for a full cycle. Throughout the following cycle, the switch will be held in the "off" state to allow for the bootstrap capacitance charging. The novel features of the present method are highlighted by Figure 6. Shown at 3 is a flow chart block which represents the normal operation of the switching regulator 2, acting as a regulating loop to switch over the transistor M1 of Figure 1. A subsequent check, indicated schematically by a block 4, on the value of the voltage V CBOOT at the bootstrap capacitance provides a verification of whether this voltage is below the threshold voltage Vs of a comparator 10, whose construction will be described hereinafter. In the negative, control is at once restored to the regulating loop. In the affirmative, the switch M1 is forced "on" for the duration of a full cycle, as indicated by a block 9. When the regulating loop 3 is disabled, the output voltage V load of the regulator 2 must be further checked. This additional check, indicated schematically by a block 7, is carried out by means of a comparator, not shown because conventional, which will force the switch into the "off" state upon a predetermined overvoltage threshold being overtaken. By so controlling the operation of the regulator 2, the minimum operating current I MIN can be minimised. In fact, this current I MIN is the same as the current that would be made available by an ideal voltage generator V REG , in that the amount of the charge supplied by the generator V REG is of the type indicated in Figure 7 by a shaded area. The construction of a control circuit 10 for implementing the inventive method will presently be described with reference in particular to the example shown in Figure 8. The circuit 10 comprises a comparator 9 and a network 19 of logic gates, and certain storage elements, such as flipflops of the D type. The comparator 9 has an inverting input which is held at a voltage threshold Vs, and a non-inverting input whereat a voltage equal to V CBOOT - V OUT is presented. The comparator 9 has an output 8 on which a signal Cboot_ok is produced which corresponds to a voltage value detected on the bootstrap capacitance. This signal will be active when its logic value is low. The output 8 is coincident with a first input of a first logic gate 11 of the NAND type, having two inputs and an output connected to one input of a second two-input logic gate 12 of the NAND type. The output of this second gate 12 is connected to an input D of a storage element 20 having a natural output Q which is feedback connected to one input of a third logic gate 13 of the NAND type. The negated output QN of the storage element 20 is connected to the second input of the first logic gate 11. The output of the third gate 13 is connected to the second input of the second gate 12, as well as to an input I0 of a multiplexer 25 via a first inverter 26. Fourth and fifth logic gates, both of the two-input NAND type and denoted by 14 and 15, respectively, receive on respective inputs, the one the signal from the natural output Q of the element 20 and the other the signal from the negated output QN of the element 20. The output of the fourth gate 14 is connected to one input of a sixth two-input NAND gate 16 whose output is connected to an input D of a second storage element 21. The second storage element 21 also has a natural output Q and a negated output QN. The negated output QN is connected to the second input of the third logic gate 13 and the second input of the fifth logic gate 15. The natural output Q of the second element 21 is connected, on the other hand, to the second input of the fourth logic gate 14. Finally, it should be noted that the negated output of the first storage element 20 is connected, via a second inverter 27, to the second input of the sixth logic gate 16. The multiplexer 25 has a control input 18 connected to the output of the fifth gate 15 via a third inverter 28. Another input 11 of the multiplexer 25 receives directly a control signal SWITCH from the regulator 2. The multiplexer 25 has an output OUT connected to one input of a seventh logic gate 17 of the two-input AND type. The other input of the gate 17 receives an overvoltage control signal OVERVOLTAGE. The output of the logic gate 17 corresponds to the control output of the control circuit 10. A signal SWITCH2 is produced on this output and applied to the gate terminal of the power transistor M1 whenever the transistor M1 is to be forced into the "on" state following a comparison of the bootstrap capacitance voltage with the threshold voltage Vs. For completeness of description, the presence should be considered of an applied signal CLEAR, and of respective reset inputs CP on both storage elements 20 and 21. CLEAR is a supply control signal required for proper start-up of the switch. Furthermore, a signal CLOCK is applied to respective inputs CD of the storage elements 20 and 21 to regulate their operational clocking. CLOCK is a signal which sets the operational frequency of the step-down switching regulator 2. With this signal CLOCK at a high level, the switch M1 is sure to be in the "off" state. OVERVOLTAGE is the signal for controlling overvoltages at the regulator output. The signal SWITCH2 controls the switch M1 to the "on" state. When the capacitance voltage is correct, this signal is coincident with the signal SWITCH as set by the regulating loop of the regulator 2; otherwise, SWITCH2 will force the switch M1 into the "on" state through one cycle, and the "off" state through the next, when no overvoltage is presented at the load.

Claims: A method of controlling the charging of a bootstrap capacitance (C BOOT ) incorporated into a switching regulator (2) of a power transistor (M1) connected to an electric load, characterised in that a comparison is carried out, at each switching cycle, between the voltage value (V CBOOT ) at said bootstrap capacitance (C BOOT ) and a predetermined threshold voltage (Vs), to change the mode of operation of the regulator according to the outcome of said comparison. A method according to Claim 1 characterised in that to change the mode of operation means to take the control on said transistor (M1) off the regulator (2) when the voltage (V CBOOT ) at the bootstrap capacitance (CBOOT) is lower than said threshold voltage (Vs). A method according to Claim 2, characterised in that, with the voltage (V CBOOT ) at the bootstrap capacitance (C BOOT ) below said threshold voltage (Vs), the transistor (M1) is forced into the "on" state through a full cycle. A method according to Claim 2, characterised in that, with the regulator (2) disabled, an additional check is carried out on the output voltage (V load ) of the regulator (2). A circuit (10) for controlling the charging of a bootstrap capacitance incorporated into a switching regulator (2) of a power transistor (M1) connected to an electric load, characterised in that it comprises a comparator (9) for comparing the voltage value (V CBOOT ) at said bootstrap capacitance (C BOOT ) with a predetermined threshold voltage (Vs) and taking the control on said transistor (M1) off the regulator (2) when the voltage (V CBOOT ) at the bootstrap capacitance (C BOOT ) is lower than said threshold voltage (Vs). A circuit according to Claim 5, characterised in that it further comprises a network (19) consisting of some logic gates, storage elements (20,21), and at least one multiplexer (25).

Inventors: BORGHI MARIA ROSA, MAGAZZU ANTONIO, BORGHI, MARIA ROSA, MAGAZZU', ANTONIO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1996
Main classification: G05F1
IPC codes: G05F1