STACKABLE MODULES AND MULTIMODULAR ASSEMBLIES

Abstract: Stacked multimodular circuit assemblies (10, 12, 14) are provided which comprise stacked, sealable, modules containing electronic circuitry (50), each module having a plurality of electrically conductive, embedded through-vias (52, 53) between the upper and lower major surfaces thereof. The through-vias are contained within the module matrix outside of the circuit-containing cavity or "tub" (55) of the module and within the outer edges of the module body. Electronic circuitry contained in the module cavity is electrically connected to the through-vias by signal traces or vias passing out of the cavity and into contact with the through-vias, and adjacent modules are electrically interconnected by sealable, multichannel connector array (90) between adjacent modules having electrically conductive channels (92) coupling opposing through-vias of the adjacent modules. The connector arrays can also serve to seal the assembly when the entire assemblage of modules is copressed and to connect the stacked modular assembly to exterior circuitry such as a printed circuit board or other devices. Methods are also provided for assembling and electrically interconnecting electronic components within such stacked multimodular assemblies by attaching components of an electronic circuit to at least two stackable modules of the type described within the cavity thereof, interconnecting the circuit components with the described through-vias, and stacking and interconnecting the stackable modules with the described multichannel connector arrays interposed between each adjacent module pair.

Description: STACKABLE MODULES AND MULTIMODULAR ASSEMBLIES BACKGROUND Field of the Invention This invention relates to the field of electronics packaging and, in particular, to modules for housing electronic components and interconnecting multiple electronic components in multimodular stacked assemblies and to stacked, multimodular assemblies containing interconnected electronic components. Description of Related Art The need for greater capacity, more complex, yet coherent and rapid data processing has always exceeded the ability of available technology to meet that need. Nevertheless, advances are constantly being made through the design of faster and more complex processors and essential complementary memories, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), and the like. More complex circuits take advantage of multiple parallel processors and ancillary circuitry. Having the available processors, memories, and other essential components, it is not difficult to conceive of integrated systems capable of performing most desired functions. However, ever increasing processor operating speeds and concomitant limitations on signal travel distance, circuit density limitations imposed by thermal requirements, and other factors quickly introduce realities which eliminate many conceivable circuits from consideration. This is true even when cost is no object and is even more the case when market realities limit acceptable costs of circuit manufacture, testing, reworking, etc. Accordingly, a considerable amount of effort is devoted to circuit designs and layouts which make feasible integrated, heterogeneous circuits that are otherwise only conceivable. Often the most compelling imperative in circuit design and structure is to limit signal travel distance (duration) between processors, memories, and other ancillary components so that processor operating speed (frequency) need not be limited and reliable data processing and management can be achieved. And often circuit performance is most restricted by the system's ability to accommodate microprocessor frequency which eliminates many circuit design options due to excessive signal travel distance. In fact, processor operating speeds are often reduced or stepped down in view of unavoidable signal travel distance requirements imposed by the system design. For instance, some of the previously known circuit designs discussed hereinafter involve the use of multiple high speed processors and numerous essential memory ICs. Often, any arrangement of such circuit components in two dimensions is impossible due to the signal travel distances required between the processor and other components. The principal reason for these limitations is known as signal reflection/distortion. Typical digital signals are step functions having extremely fast rise and fall times, and signal duration and rise and fall times decrease markedly as operating frequencies increase. If signal travel distance is relatively long with respect to signal periodic rise and fall time, the signals are reflected in- line and can be distorted by such reflectance to the point that extra or "ghost" signal pulses appear. Obviously, such signal distortion results in system failure, and these problems are exacerbated as microprocessor operating frequencies increase. Signal reflectance/distortion can be reduced with adequate impedance in the output circuit to "terminate" the signal. This impedance, referred to as "termination impedance," is typically on the order of about 22 to about 33 ohms. It can be readily seen that, while introduction of such impedance might solve the problem of signal distortion, it is unacceptable in many circumstances. The power required to drive the output signals against such impedance is often excessively high, unduly increasing circuit heat load and multiplying several fold the capacity of chip output transistors. Signal distortion associated with line reflectance, capacitance, inductance, etc., can also be reduced by reducing signal travel distance and/or frequency. Several circuit structures have been used for reducing signal travel distance, e.g., multichip modules (MCMs) and IC chip stacks with one or more access planes (both discussed hereinafter), and signal frequency is often attenuated before exiting higher frequency microprocessors which are internally "clock doubled." Currently, high speed processors may operate at 120 to 130 megahertz with exi signals stepped down to 66 MHz or less, primarily to avoid signal reflection/distortion and thus limiting system speed. Reducing signal distance poses yet other problems. Conventional multi- chip modules and PC boards are laid out in two dimensions, and these designs are adequate for simpler circuits but become inadequate for more complex multi- component systems. Figure 1 is an illustration of one such two-dimensional microprocessor/memory array available from Intel, Inc., Portland, Oregon, known as iWARP. The array contains three packaged microprocessors 20 mounted on PC board 22 which also carries multiple memory units 24. Memory units 24 are interconnected with the microprocessors by conductors on PC board 22. The area occupied by this two-dimensional array is about five times the area of the microprocessor chips, and it can be seen that the signal distance to and from the furthermost memory units becomes significant, especially as microprocessor operating frequencies increase. A similar, contemporary microprocessor/memory array known as n25 available from nCUBE, Beaverton, Oregon, is illustrated in Figure 2. In this array, the microprocessor package 26 containing microprocessor chip 28 is mounted on PC board 30 which also carries a plurality of memory units 32. As in the iWARP array, the memory units and microprocessor are connected by conductors on PC board 30 and provide memory function required by the microprocessor. As illustrated, the area occupied by the nCUBE array, i.e., the array "footprint," is three to four times the area of the microprocessor chip resulting in significant signal travel distances between microprocessor and memory units. Numerous specific architectures are available. The module of memory IC chips may be the type referred to as a "sliced bread" stack, in which the memory chips extend in planes perpendicular to the microprocessor on which they are mounted. Or the module of memory IC chips may be the type referred to as a "pancake" stack, in which the memory chips extend in planes parallel to the microprocessor on which they are mounted. Either the "sliced bread" memory stack or the "pancake" memory stack may be electrically 4 connected to the integrated microprocessor chip by use of wire bond connections, or by flip-chip connections. The flip-chip connections are functionally preferable, because they minimize the distances traveled by the electronic signals. The wire bond connections may be easier to manufacture, at least in some structures. In some instances a lead-carrying intermediate layer may be mounted between the microprocessor chip and its memory stack. Some microprocessor chips contain internal memory interface circuitry; others will need to have such interface circuitry provided by a separate IC chip which can be included in the same stack as the memory chips. The integrated microprocessor/memory stack permits the simplified manufacture of massively-parallel electronic systems, in which many microprocessor/memory stacks are mounted in proximity to one another on a single substrate. A unique, hybrid combination of two and three dimensional IC chip arrays designed to reduce component spacing is illustrated in PCT International Publication No. WO 94/13121, June 9, 1994, application No. PCT/US93/ 11601 , by John C. Carson. The hybrid combination is illustrated, in part, in Figures 3 and 4 and combines the memory chips serving each microprocessor within the microprocessor "footprint" by the chip and interconnect arrangement illustrated. Figure 5 shows one version of the memory stack/microprocessor combination, which is particularly easy to manufacture, using readily available components. A stack 21 of glued together silicon IC memory chips 23 is separately constructed, using techniques explained in the common assignee patents identified above. On the access plane face of the memory stack, which is the invisible lower side in Figure 5, a substantial number of solder bumps are formed, individually mounted on terminals and/ or buses formed on the access plane face. A separate substrate layer 27a is formed having electrical traces 27 extending from terminals 47, located near the edges of substrate 27a, to terminals on substrate located under the access plane face of the stack 21, each terminal on the substrate being matched to an opposite terminal on the access plane of the stack. The stack and substrate are connected together by flip-chip bonding, or, if desired, by a new solder bonding technique explained in copending common assignee application Serial No. 955,461, filed October 2, 1992. The substrate 27a, whose area is only slightly larger than that of memory stack 21, may be formed of silicon material covered by insulating material, or of a ceramic dielectric material, such as aluminum nitride. Aluminum nitride is a preferred ceramic, because it is an effective heat conductor, and because it has a thermal coefficient of expansion close to that of silicon. The substrate memory stack assembly is then glued to a microprocessor chip 49. Using memory interface terminals 29 (corresponding to some of the terminals in Figure 2) , which have been pre-foπned on the microprocessor to provide electrical access to the microprocessor's internal IC circuitry, the terminals 47 on substrate 27a are wire bonded (connected by wires 59) to the appropriate teπninals 29 on the microprocessor. The total number of terminals on the microprocessor chip 49 may, as previously stated, be as high as 200, of which about one-third may be connected to the memory stack 21 via substrate 27a. The other terminals 29a on the microprocessor chip are connected to external portions of the system by wire bonds 59a. Figure 6, which is taken from common assignee Application S/N 884,719, shows one of many T-connects formed on the access plane of the memory chip stack. An electrical lead 31 extending from the IC circuitry in a chip 63 reaches the surface of the access plane 65, where it is joined to metallization 67, which may be a terminal pad or a bus, or a combination of pad and bus. The T-connect (lead 31 and terminal 67) provides an effective and reliable electrical contact. A passivation layer 69 lies between the access plane surface of the chips 63 and the metallization 67. This is necessary to avoid short-circuiting by the silicon semiconductor material of the chips. A layer 17 of adhesive material secures together the adjacent chips 63. Insulating material (not visible in the figure) is provided on each flat surface of each chip 63. The earlier common assignee patents referenced above deal with (a) the preparation of the chips for stacking, (b) the forming of the chips into a stack having adhesive material retaining the chips in the stack, and (c) the preparation of the access plane of the stack for metallization to create electrical communication with exterior circuitry. If desired, a stack of chips may have more than one access plane connected to exterior circuitry. Figure 7 shows a "pancake" stack 19 containing several active IC chip layers 93, plus an inactive top layer 95, whose purpose is to provide easily accessible terminals 97 which are used to connect the memory stack 90 to its microprocessor chip. As described in common assignee Application No. 07/884,660, the top layer 95 is preferably formed of a dielectric (ceramic) material, such as aluminum nitride. The memory stack 19 has an access plane 99 on which buses 119 and individual terminals 103 have been formed, providing T-connects with the leads on chips 93 which extend to the access plane. As in the case of the "sliced bread" stack which is shown in Figure 5, the buses 119 shown in Figure 7 extend across the entire stack of IC chips; and each terminal 103 is part of a T-connect on a single IC chip. The common assignee application identified in the preceding paragraph describes in detail the electrical connections from buses 119 and terminals 103 to the appropriate teπninals 97 on the top of stack 19. Metallic traces formed on the underside of layer 95 extend from T-connects at the access plane to the holes formed in layer 95. Metal extending through each hole connects to one of the exterior terminals 97. Figure 8 shows the "pancake" stack 19 mounted on top of a microprocessor chip 113. The stack 19 is glued to the microprocessor 113, with a layer of insulating material between them. Along the edge of the microprocessor chip are a large number of teπninals. Terminals 115 are memory-interface terminals, which are connected to the respective memory stack terminals 97 by wire bonds 109. Terminals 117 are connected by wire bonds 113 to exterior circuitry. This structure, like the structure in Figure 5, is the simplest to manufacture, based on available components. However, the benefits of faster signal communication can be obtained by eliminating the wire bond connections between the memory stack and the microprocessor chip. This design represents a significant improvement in microprocessor/memory array component density over the iWARP and nCUBE systems. In Carson, the necessary memory chips are first integrated into a compressed stack having an access plane on one side bonded at "T-connects" or by other connections to the microprocessor, so that the memory stack fits within the microprocessor "footprint." In an alternative embodiment, the memory chip stack is bonded to an interface layer which, in turn, is bonded to and within the "footprint" of the microprocessor. The microprocessor/memory stacks can further be arranged in a two-dimensional array for massive parallel processing as discussed by Carson. As a consequence of this arrangement, Carson reduces microprocessor-memory spacing and, therefore, the signal travel distance and time. These and other advantages of three-dimensional chip stacking, wherein chips are bonded directly to each other, and methods of manufacturing such assemblies, are further elaborated, for instance, by Clark, U.S. 4,403,238, Carson, et al, 4,525,921, 4,551,629 and 4,646, 128, and Belanger, et al, 4,617, 160. Such chip stacks provide very high circuit densities with conventional IC chips. However, the techniques employed to achieve those results impose some limitations on the flexibility of those assemblies in other respects. For instance, such chip assemblies cannot be easily repaired, and cannot be repaired practically in the field. Furthermore, the geometry of such three-dimensional chip assemblies often places some significant limitations on the diversity of chips that can be incorporated in one unit. ICs come in a variety of sizes with the exterior dimensions depending, primarily, on circuit complexity and layout and the manufacturer's desire to reduce substrate size and cost. For this reason it would be complicated, at best, to incorporate all of the ICs required for a heterogeneous circuit into a single cube. Another problem with densely packed cube structures, such as those described by Carson and others, supra, are limitations on heat transfer which may not be acceptable under some circumstances. Obviously, the circuit density of the densely packed cube devices concentrates thermal load and must be accommodated by adequate cooling. Yet another alternative for using the third dimension to reduce overall circuit area is described by Palmer and Newton in their article "3-D Packaging Using Low-Temperature Cofired Ceramic (LTCC)," Int'l. Journal of Microcircuits and Bectronic Packaging, V. 16, No. 4, 4th Quarter, 1993, pp. 279-83. These authors describe a multimodular/stacked memory device in which a plurality of chip carriers, or tubs, each containing one or two memory ICs, are stacked and interconnected with external electrical interconnects, e.g. solder or conductive epoxy. Signals to and from the internal memory units are communicated to the module's exterior edge, in part, by interior metallization between layers of cofired ceramic. The external and internal circuitry is connected, in part, through a series of what the authors call "blind castellations" within the matrix of each module. Those blind constellations are vertical vias within the module matrix electrically connected to the interior and exterior of the module body by interlaminar metallization. SUMMARY We have found that the two- and three-dimensional IC circuit layouts known in the art suffer one or more disadvantages which limit system performance with complex, multi-component, high speed circuits presently available. The necessity of reducing signal travel distance and time between circuit components has been discussed somewhat above, and further limitations are placed on currently available circuit layouts, particularly in some situations, by space requirements, ease of component testing, in-field testing and repairability, and heat load, particularly in dense, three-dimensional integrated packages. These and other deficiencies of prior art devices can be ameliorated with the stackable modules and multimodular assemblies of this invention. These multimodular assemblies comprise stacked, resealable, electronic circuit modules having a plurality of electrically conductive embedded through-vias between the upper and lower major surfaces of each module. Those through-vias are embedded within the module matrix outside of the circuit-containing cavity or tub of the module and within the outer edges of the module body. The stacked modules are electrically interconnected by interposing between adjacent modules a resealable, multichannel connector array having electrically conductive channels coupling opposing through-vias in the adjacent modules. The connector arrays also serve to seal the assembly when the entire assemblage is compressed together by retaining pins or other device. These assemblies provide several advantages over presently available circuit designs. They enable the reliable construction of high-density, complex, high speed circuits with all ancillary supporting circuitry without limiting chip selection, ease of component testing, hermeticity, or in-field repairability. While the reduced "footprint" of these assemblies and their reduced overall volume result in higher power densities and, therefore, higher specific heat loads, the interconnecting through-vias provide heat transfer throughout the assembly adequate to dissipate the increased heat load even with complex circuits, and they thus make possible assemblies which would not otherwise be feasible due to thermal load. The assembled systems comprise a plurality of heterogeneous (multi- component) hermetic, separately testable modules which can be independently tested and replaced on site thereby preventing costly down time and factory reworking. The through-via design affords the option of providing vias in excess of the number required for the original circuit design to allow for heat dissipation and circuit redesign and expansion; i.e. additional modules. It also reduces internal wiring density due to its flexible Z-axis configuration. This simplicity, in turn, reduces substrate wiring complexity and enables the use of simpler, high- yield laminated module designs by reducing the number of signal trace layers (between module lamina) required due to the staggered and multiple row placement of vertical vias around the periphery of the component cavities. BRIEF DESCRIPTION OF THE DRAWINGS These and other advantages, variations and modifications of this invention will be apparent from the following description and drawings, of which: Figure 1 is an isometric view of the commercially available two- dimensional, board mounted iWARP microprocessor system with support memory; Figure 2 is an isometric view of a commercially available nCUBE microprocessor system mounted in two dimensions on a single PC board; Figure 3 is a side sectional view of a five- module, multimodular assembly in accordance with this invention containing processor, memory, and programmable ROM circuit modules; Figure 4 is a top planar view of the processor module of Figure 3 showing the processor and address and data buffer chips, wire bonding and other module features; Figure 5 is an isometric drawing showing a "sliced bread" memory chip stack mounted on a substrate, which in turn is mounted on a microprocessor; Figure 6 is a cross-section through a T-connect which joins a lead line from the interior of the memory stack of IC chips shown in Figure 5 to a terminal on the access plane surface of the memory stack; Figure 7 is an isometric drawing showing a 'pancake" stack similar to the one disclosed in common assignee Application Serial No. 07/884,660; Figure 8 shows the "pancake" stack of Figure 7 mounted on a microprocessor, with terminals on the top of the stack wire-bonded to the memory-interface terminals on the microprocessor; Figure 9 is a side sectional view of the processor module of Figure 4; Figure 10 is a top planar view of one of the two static RAM (SRAM) modules of the assembly of Figure 3 showing two mounted SRAM chips, capacitors and other module components; Figure 11 is a side sectional view of the SRAM module of Figure 6; Figure 12 is a top planar of one of the two program-containing modules of the assembly of Figure 3 illustrating the mounted electrically erasable programmable ROM chips and one mounted data buffer chip; Figure 13 is a side sectional view of the programmable module of Figure 8; Figure 14 is a top partial view of a hypothetical module in accordance with this invention illustrating circuit to module wire bonding, interlaminar signal trace layout, and trace-to-through-via orientation; Figure 15 is a side sectional view of the hypothetical assembly illustrated in Figure 10; Figure 16 is a transparent isometric view of a button-type intermodular connector useful in accordance with this invention; Figures 17(a), (b) and (c) are schematic illustrations of connector variations useful in the intermodular connectors of Fig. 12; Figures 18(a) and (b) are top and sectional views, respectively, of a conductive epoxy button connector useful as an intermodular connector in accordance with this invention; and Figures 19(a) and (b) are transparent partial isometric views of two types of compressible multi-wire intermodular connectors useful in this invention. DETAILED DESCRIPTION Referring now to the remaining drawings, Fig. 3 is a side-sectional view of a multimodular device in accordance with this invention schematically illustrating five stacked modules 10, 12, and 14 including two electrically erasable, programmable, ROM (EEPROM) modules, 10 and 11, 2 SRAM modules, 12 and 13, and processor module 14. The details of individual modules are illustrated and discussed in more detail with regard to Fig. 4-9 and are illustrated in Fig. 3 only to show the manner in which the modules can be assembled into a unitary structure. The five modules illustrated in Fig. 3 are electrically interconnected via resealable, multichannel connectors 18, and a similar connector 18 connects the through-vias in lowermost module 14 to circuit board 17 from which signals are distributed beyond housing 15 via circuitry not shown. The five modules are aligned relative to each other and to circuit board 17 by any suitable positioning device, such as guide pin 40, and the entire assembly is supported on base 16 within housing 15 retained on the base by suitable tie-downs, such as bolts 19. The assembly is rendered more shock-resistant by spacer 42 which can comprise any resilient, preferably dielectric material. Headspace 41 is provided to accommodate compressed entrapped gas during assembly. Also illustrated schematically in Fig. 3 are the various module components (discussed in more detail hereinafter), the multiple layers of refractory 43 from which the modules are assembled in one preferred embodiment, hermetic sealing lids 44 on 6/23396 12 each module, and wire bonds 45 electrically connecting the components with conductive signal traces on the module lamina. As discussed in more detail hereinafter, the module signal traces just mentioned and not illustrated in Fig. 3 are described in more detail with reference to Fig. 4-11 , along with the interconnections between those traces and the embedded through-vias. Fig. 4 is a top planer view of a suitable processor module 14 with processor chip 50 and address and data buffer chips 51 fixedly mounted to the base 55, all of which are electrically interconnected to metal traces on module laminae (not illustrated) via wire bonds 45 and outer bond pads 54. Outer bond pads 54 are electrically connected to through-vias 53 (see Fig. 5) which have contact pads 52 at either end thereof at the upper and lower surfaces of module 14. The processor module 14 illustrated in Figs. 4 and 5 suitably has a width (W) and depth (D) of about 1.4 inches, and these dimensions apply to all modules within the assembly illustrated, in part, in Fig. 3, supra. Each module is also provided with four rows of embedded through-vias 53 bordering each side of the module tub (i.e. , the central area of the module housing the processor and buffer chips) four rows deep, and each row comprising 25 vias to provide a total of 400 matching through-vias. As illustrated in Fig. 4, the through-vias 53 have diameters within the module matrix of approximately 0.01 inch and terminate at larger contact pads 52 having diameters, for instance, of about 0.035 inch and are spaced on centers of about 0.035 inch. After assembly and wiring of the module components, the module tub 57 is evacuated in inert atmosphere (e.g. nitrogen) and hermetically sealed lid 44 which is bonded by metallization or adhesive 58. As illustrated in Fig. 5, processor module 14 comprises 16 total refractory layers, having five layers of lamina below the base 55 of the interior tub and has an over all height of nominally 0.09 inch. These dimensions, and the diameters and spacing of through-vias 53, become significant in view of the necessity of maintaining the integrity of all signal leads from a module, such as processor module 14, which as illustrated in Figs. 4 and 5, has 396 active wire bonds 45 and bond pads 54. It, therefore, has 396 active internal traces or vias between or within the module lamina (not illustrated in Fig. 4) communicating between the several components of the processor module and through-vias 53. The SRAM modules 12, one of which is illustrated in top planer perspective in Fig. 6, have the same height and width as processor module 14 and the same number and spacing of through-vias 53 and contact pads 52. The interior or tub of the module, the perimeter of which is defined generally by hermetic seal bond ring 58, is also generally the same as that illustrated for the processor module 14. However, the SRAM, module contains two SRAM chip stacks 60 wire- bonded to outer bond pads at two levels as better illustrated in Fig. 7, which is a side-sectional view taken along Section 7-7 of Fig. 6. Each of the chip stacks is a "sliced bread" or "pancake", as illustrated in Figures 3-8. Module 12 is also provided with four capacitors 61 ancillary to the SRAM units. Due to the height and bond pad configuration on the two SRAM units 60, module 12 has an overall height of about 0.13 inch. The last two modules of the assembly, EEPROM modules 10, are illustrated in Fig. 8 in top planer view and in Fig. 9 and in off-set sectional view taken along section 9-9 of Fig. 8. Each of these modules comprises 2 EEPROM chips 70 which can be AT28C010 chips available from ATMEL, and data buffer (temporary data storage) chip 71. Each of modules 10 has the same exterior dimensions as processor module 14 and the same number and spacing of internal vias 53 and via bond pads 52. The bodies of modules 10, 12, and 14 can be manufactured of any suitable dielectric material capable of providing the necessary placement and integrity of through-vias 53, contact pads 52, and the necessary electrical connections, such as wire bond pads 54 and signal traces or vias communicating between pads 54 and through-vias 52. The signal traces are illustrated in Figs. 10 and 11 and are discussed hereinafter. One manner in which the buried signal traces connecting the I/O leads of electronic components contained within the module to the through-vias is illustrated in Figs. 10 and 11, of which Fig. 10 is a top planer view of a segment of a module similar to those illustrated in Figs. 3-9 and Fig. 11 is a side-sectional view of the segment illustrated in Fig. 10 taken along section line 11-11 of Fig. 10. The module body 80 contains a hypothetical electronic component 83 having I/O pins 84 mounted to the floor of the internal well in the module by suitable adhesive 89, such as epoxy or solder well known in the art. The module well is bordered by 5 rows of through-vias 81 embedded within the module layers 87 and extending continuously vertically through the module body as illustrated in Fig. 11. The vias terminate in contact pads 82 at either end of each via. I/O pins 84 of device 83 are interconnected by wire bonds 85 with outer bond pads 86 on the buried traces 88. Each of traces 88 is, in turn, connected to one or more of the vertical vias 81 as illustrated, in part, in the side sectional view of Fig. 11. Fig. 11 illustrates, in part, the four lowermost traces illustrated in Fig. 10 showing that they originate at bond pads 86 at four different levels in the module cross-section thereby enabling them to extend, uninterrupted and without interference, into the interior of module body 80 along the dielectric layer planes 87. Any variations of the signal wiring arrangement illustrated in Figs. 10 and 11 suitable for communicating signals from device 83 to through-vias 81 can be employed within the concepts of this invention. For instance, device 83, often an IC chip, can be flip-chip bonded to signal leads running from the floor of the module tub to the traces 88 embedded between layers 87 of the module body 80. Also, lateral internal vias can be employed to communicate signals from bond pads 86 to the vertical through-vias 81. Such lateral embedded vias can be formed along the same patterns as those illustrated for the signal traces illustrated in Figs. 10 and 11 with the exception that such vias would occupy a channel through a portion or all of the height of an appropriate layer 87 of the module body. The module assemblies comprise at least two modules up to the number of modules required to house the desired circuitry in a unitary structure, with the limiting factor on module number generally being thermal conductivity and heat load. Typically, most assemblies can be effectively integrated within two to about ten modules assembled as illustrated in Figs. 3 and 4 with most circuits requiring at least about three of such modules. Module dimensions are also widely variable, and the modules can be of any size required to house the circuits involved, and they are preferably as small as possible to achieve that function. Typically, the depth (D) and width (W) of the modules as illustrated in planer view of Fig. 3 are about 5 inches or less, preferably about 3 inches or less in the maximum of those dimensions. Module height is determined by the number of layers of lamina in the module which, in turn, is largely a function of design convenience (for housing electronic components) and the number and configuration of signal power, ground, and shielding traces or other leads, from contained circuitry to the through-vias. A greater number of signal leads, as well as a greater number of through-vias, can be effectively managed in one unitary structure with more layers in the module to provide a greater number of interlaminer layers through which to run signal leads or lateral signal vias. Thus, these modules will comprise at least two, generally at least three, and typically at three to about thirty layers of lamina determined primarily by the height of contained electronic components and the number of signal leads and through-vias in the module. The number of signal connections per module will depend, of course, upon the components contained in that module and usually is at least about 10, often at least 20, and generally about 50 to as high at 1000 or more leads per module. Most typical modules will involved about 50 to about 400 signal leads interconnected either internally within the same module or with the through-vias. The number of signal leads and their orientation, in turn, determines the number and layout of signal traces, lateral vias, or other type of interconnections between module components and/or the through-vias. The number of through-vias must be adequate to accommodate the number of signals transmitted between modules internal of the assembly and exiting the assembly as well as to provide adequate component testing capability and heat transfer. As in the case of the other components of the modules, the number of through-vias can vary considerably in view of demands imposed by the circuits involved. Ordinarily, however, each module in the assembly will have at least about 20, typically at least 50, and most often 50 to as many as 1000 through-vias per module, and each module in an assembly typically will contain the same number and layout of through-vias. However, different numbers of vias can be used in different modules in the same assembly, for instance, to provide interconnections between two or more modules within an assembly having an overall greater number of total modules. Vertical via spacing and size are related to accommodate signal and heat carrying capacity and to reduce overall module dimensions as much as possible. In this regard, through-via spacings as low as 0.02 inch on centers can be readily achieved with vias having diameters as small as 0.008 inch and contact pads at either end of the vias of 0.012 inch. Through-vias of this type provide a number of advantages including heat transfer as discussed above, and for this reason, a number of through-vias in excess of that required simply for signal carrying capability can be provided to facilitate heat transfer and to provide flexibility for reworking module assemblies, for rerouting leads as required to accommodate modified modules, and for test pads for in-lab or in-field testing. The modules or "tubs" can be fabricated from any suitable dielectric, preferably high temperature resistant dielectrics including plastics and ceramics, by procedures well known in the art, such as those discussed for cofired laminated ceramics and laminated plastics in "Electronic Packaging and Interconnection Handbook", McGraw-Hill, 1991 , Sections 6.2.3 and 6.2.4, pages 6.30 et seq. and by Palmer and Newton in "3-D Packaging Using Low-Temperature Cofired Ceramics (LTCC)", International Journal of Microcircuits and Electronic Packaging, vol. 16, no. 4, fourth quarter 1993 pages 279-284, the disclosures of which are incorporated herein by reference in their entireties. High temperature cofired ceramic and pressed ceramic technologies, as well as other technologies used for producing multilaminar modules of the type illustrated in the drawings and discussed herein, can also be employed. Suitable ceramics or, more broadly, refractory inorganic oxides, include the many temperature resistant, dielectric inorganics known in the art such as alumina, beryllia, aluminum nitride, silicon carbide, silica, etc. Illustrative plastics include high temperature epoxies, polyimides, triazines, temperature resistant phenolic resins, etc. Typical ceramic composites having signal traces and through-vias as illustrated herein can be prepared by forming a dispersion or slurry of ceramic powder, casting the slurry into thin sheets, and drying to form sheets of "green" tape ready for size cutting, hole punching (e.g., for the vertical vias described herein), and cutting out areas to be the center cavities of the modules. At this stage, signal traces can also be screened onto the surface for connections between wire bond pads and the through-vias, intramodule connections, or otherwise, using, for instance, a tungsten powder slurry; and the via holes can be filled with metal. The tungsten slurry used for signal trace screening can also be employed for this purpose or molybdenum-manganese alloys can be substituted for tungsten in the vias and/or traces. Multiple sheets cut to form one module tub are then press- laminated together in a confining fixture and fired, e.g., at 1 ,600 C°, in a non- oxidizing atmosphere to form the module body containing embedded signal traces and through-vias. Lead attachment and metallization plating can then be accomplished by procedures well known in the art such as plating the exposed tungsten traces with nickel in preparation for led brazing or with Kovar, specialized iron-nickel-cobalt alloys, or Alloy-42 for gold-copper eutectic alloy braising. These procedures are conventional in the art and do not constitute an aspect of this invention. Accordingly, any methods and materials suitable for forming conductive signal traces, through-vias, wire bonding pads, etc. can be employed. The signal trace and bond pad layouts for component-to-component and component-via interconnects can be designed manually, although the procedure can become time consuming with complex three dimensional, multimodular assemblies. More expeditious design and signal trace layout can be accomplished with available MCM CAD tools such as Cadence Allegro, available from Cadence Design Systems, Inc., San Jose, California, and MCM Station available from Mentor Graphics, Inc., Wilsonville, Oregon. Similar procedures can be employed to manufacture module bodies using laminated plastic technologies by preparing and cutting thin sheets of suitable plastic, such as those noted above, to form interior cavities and through-vias. Signal traces and wire bond pads can be formed by copper, nickel, and/or gold plating. Also at this stage the holes for vertical vias can be filled with conductive metals such as gold, silver, copper, or aluminum by pressing the metal in paste form through a screen mask using a squeegee. There are a number of reputable suppliers for multi-laminar modules using technologies compatible with the module designs of this invention having the through vertical vias described. Illustrative are Kyocera, San Diego, California; Micro Electronic Packaging, Inc., San Diego, California; and Coors Electronic Packaging, Inc., Chattanooga, Tennessee. After the modules are formed, the electronic components are mounted and wire bonded as described, in part, above, typically with gold or aluminum wire, the module contents are encapsulated in a polymeric coating and sealed hermetically with a metal or ceramic lid, and the module is sealed as described above. After environmental and functional testing, the modules then can be assembled as illustrated, in part, in Figure 3 and described above, using a resealable, multichannel connector array, several types of which are presently available from manufacturers in the component packaging industry. The connector array matrix is usually a non-adherent, resealable plastic, such as the high temperature epoxies, polyimides, triazines, and phenolics referred to above. These connector arrays can be custom designed to provide one or more connector contacts for each through-via in the modules so that adequate interconnection of vias in adjacent modules is ensured, provided there is accurate placement of modules and connector arrays. The connector arrays are preferably compressible and also preferably have compressible electrical contact (connector) areas to better ensure adequate via-to-via contact for all through-vias. Suitable arrays usually have contact spacings of about 0.01 to about 0.1 inch on centers, corresponding to the usual center-to-center placement of through-vias. Suitable connector arrays are, for instance, the "CIN::APSE" and "Fuzz Button" connectors available from Cinch Connectors, Elk Grove Village, Illinois, examples of which are illustrated in Figures 12 and 13; the embedded, silver-filled epoxy dots illustrated in Figure 14 and available from Merix Corporation, Needham Heights, MA; the embedded wire-filled silicone rubber dots illustrated in Figure 15 available from Fujipoly Inc., Cranford, New Jersey; and the "Matrix MOE" elastomeric connectors available from Elastomeric Technologies, Inc., Hatboro, Pennsylvania, Figure 12 illustrates a section of a "Fuzz Button" connector array showing a transparent isometric of a dielectric layer 90 having a grid of apertures 92 into which are fitted compressible, conductive "Fuzz Buttons" 91, each of which preferably protrudes beyond the surface of substrate 90 a minor amount, e.g., about 0.003 to about 0.01 inch per side sufficient to ensure contact with the through-via contact pads. Substrate 90 can comprise any suitable insulating material, generally a plastic such as the epoxies and temperature resistant polyimides and triazines referred to above. The insulating layer 90 is preferably as thin as possible to ensure adequate sealing of the modules and adequate strength of the multi-channel contact array and can be obtained in substrate thicknesses as low as 0.032 inch. The buttons are randomly wound cylinders of gold-plated, resilient, conductive wire retained in hourglass-shaped apertures 92. Figures 13(A), (B), and (C) illustrate variations of the button contacts illustrated in Figure 12 which are also available from Cinch Connectors, Inc., with Figure 13(A) showing an expanded view of the button contact 91 of Figure 12 in dielectric substrate 90. Figure 13(B) illustrates a similar contact comprising non- conductive cylinder 100 containing conductive pin 101 on either end of which are mounted compressible randomly wound conductive wire contacts 102, such as the button contacts 91 of Figures 12 and 13(A). Figure 13(C) illustrates yet another variation of these contacts showing a dielectric substrate 105 containing conductive metal pin 106 opposed by compressible, randomly wound conductive wire button or cylinder 107. Figures 14(A) and (B) illustrate, respectively, a top planar view and a side sectional view of conductive, silver-filled epoxy dots 110 about 0.02 inch in diameter on 100 mil spacing embedded in dielectric epoxy substrate 111. This type of connector array can be obtained with dielectric thicknesses as small as 0.002 inch or less and dot heights of 0.004 inch available from Merix Corporation, supra. These arrays of epoxy dots can be deposited directly on one or both surfaces of the modules with the location of the dots corresponding to the location of through via contact points at the module surface. Figures 15(A) and (B) are transparent isometric illustrations of Fujipoly Inc.'s W Series "L" and "S" pattern conductors, respectively, which are yet another alternative for use as the multichannel contact arrays. Both conductor arrays comprise a dielectric silicon rubber sheet 120 containing either single bundles of embedded, gold plated wires ("L" pattern) 121 in Figure 15(A) or multiple bundles of gold plated metal wires 122 for the "S" pattern illustrated in Figure 115(B). In both instances, the conductive portion 121 and 122 of the substrate 120 contains about 300 to about 2,000 fine metal wires per square centimeter of conductive area. These arrays and others available from Fujipoly can be obtained with wire bundle spacing customized to correspond to the spacing of through-via contact pads on modules formed in accordance with this invention to provide useful, resealable multichannel contact arrays. Numerous variations and modifications of the foregoing concepts of this invention will be apparent to one of ordinary skill in the art in view of the foregoing disclosure and drawings, and it is intended that such variations be encompassed within the appended claims.

Claims: CLAIMS: 1. A stacked, resealable, multimodular, electronic circuit assembly comprising: (1) at least two stacked modules, each module comprising a dielectric substrate having upper and lower planar surfaces and at least one cavity in at least one of said surfaces said cavity having lesser width and breadth than said one surface, thereby forming a dielectric substrate matrix surround said cavity; (2) at least one electronic component comprising a three- dimensional stack of IC chips positioned within at least one cavity of each of the said modules and having I/O contacts; (3) a closure plate overlying said cavity, enclosing same and bonded to said one surface with a sealable adhesive to provide a hermetic seal of said cavity; (4) a plurality of electrically conductive through-vias between said upper and lower planar surfaces of each of said modules outside of said cavity and within said matrix each of said through-vias having exposed electric contact points where it penetrates said upper and lower planar surfaces; (5) said I/O contacts of said electronic components in each of said modules being electrically connected with through-vias in each respective module; and (6) a planar, multichannel connector array between each opposing pair of said modules having separate electrically conductive channels electrically coupling opposing through-vias in said adjacent modules and for sealing said modules when pressed together. 2. The assembly defined in Claim 1, wherein said modules comprise multiple, laminated, dielectric lamina oriented in planes generally perpendicular to the major axis of said through-vias. 3. The assembly defined in Claim 1, wherein said multichannel connector array comprises a dielectric plastic or elastomeric layer comprising said electrically conductive channels in an array on centers of about 0.2 inch or less. 4. The assembly defined in Claim 3, wherein each of said channels comprises an aperture through said layer containing a compressible electrically conductive wire bundle. 5. The assembly defined in Claim 4, wherein said compressible wire bundle comprises a randomly wound wire strand. 6. The assembly defined in Claim 2, wherein said layers of dielectric lamina comprise a refractory inorganic oxide, nitride, carbide, or combination thereof. 7. The assembly defined in Claim 2, wherein said I/O contacts are connected to said through-vias by electrically conductive paths along the interfaces between adjacent layers. 8. The assembly defined in Claim 7, comprising at least two rows of said through-vias bordering at least one side of said cavities in said modules, and the number of interfaces between said layers in at least one of said modules is at least equal to the number of said rows of said through-vias. 9. The assembly defined in Claim 7, comprising at least four rows of said through-vias bordering to at least one side of the cavities in said modules and at least about five layers of lamina in at least one of said modules forming interfaces available for forming conductive paths between said I/O contacts and said through- vias. 10. The multimodular assembly defined in Claim 7, comprising at least three of said stacked modules, at least about 50 of said through-vias, and at least about 50 I/O contacts on said components connected to said vias. 11. The multimodular assembly defined in Claim 2, wherein said I/O contacts are interconnected with said through-vias in a pattern such that each of said components can be tested by determining electrical signals in said through- vias. 12. The stacked, multimodular assembly defined in Claim 2, further comprising a number of said through-vias in excess of that required for connection with said I/O contacts on said components such that said assembly comprises unconnected through-vias. 13. The multimodular assembly defined in Claim 12, comprising at least one memory IC chip. 14. An expandable memory, stacked, multimodular assembly comprising the assembly defined in Claim 12 having memory and processor logic circuitry. 15. The multimodular assembly defined in Claim 8, wherein said electronic components within said assembly, combined, have at least about 50 of said I/O contacts electrically connected to said through-vias, and each of said modules has at least about 50 of said through-vias electrically connected with corresponding opposing vias on adjacent modules. 16. The assembly defined in Claim 15, wherein said through-vias have contact pads at either end thereof having a diameter greater than the maximum diameter of the through-via, said through-vias are arranged in a grid pattern on centers of about 0.2 inch or less, and each of said through-vias has a diameter within the module matrix of about 0.05 inch or less. 17. A stackable module for containing and interconnecting electronic components comprising a dielectric substrate having upper and lower planar surfaces and at least one cavity on at least one of said surfaces for containing one or more three-dimensional IC chip stacks, said substrate comprising multiple, laminated layers of said dielectric, at least 50 electrically conductive through-vias between said upper and lower planar surfaces of said module outside of said cavity and within the matrix of said module, each of said through-vias having exposed electric contacts at either end where it penetrates said upper and lower surfaces of said planar substrate and electrically conductive signal paths interconnecting said through-vias and the interior of said cavity and being located between said layers of said module for communicating electronic signals to and from electronic components within said cavity, and a closure plate covering said cavity and sealed thereabout to hermetically contain said cavity. 18. The stackable module defined in Claim 17, comprising at least three of said laminated layers and having said electrically conductive pathways between at least two of said layers interconnecting said through-vias and said cavity. 19. The stackable module defined in Claim 17, comprising at least about 100 of said through-vias in a grid pattern bordering said cavity and being spaced on centers of about 0.2 inch or less and having maximum diameters within the matrix of said module of about 0.05 inch or less. 20. A multimodular assembly comprising at least two stacked modules defined in Claim 19, each containing at least one electronic component and at least one of said modules containing said three-dimensional stack of IC chips, the I/O contacts of said electronic components being interconnected with said through-vias via said inter laminar electronic signal paths, each of said modules being electrically interconnected with at least one adjacent module through a sealable, multichannel connector array having separate electrically conductive channels electrically coupling each pair of opposing, matching through-vias in said adjacent modules and for sealing said modules. 21. A stacked, sealable, multimodular, electronic circuit assembly comprising at least three stacked modules, each module comprising multiple laminated dielectric lamina layers forming a dielectric substrate having upper and lower planar surfaces and at least one cavity in at least one surface of each of said modules for containing at least one electronic component; a. said laminated dielectric lamina being oriented in planes generally parallel to said upper and lower planar surfaces; b. at least one three-dimensional chip stack of electronic components positioned within at least one cavity on each of said modules and having I/O contacts; c. at least about 50 electrically conductive through-vias between said upper and lower planar surfaces of each of said modules through the matrix thereof outside of said cavity and within the outer surface of each module, each of said through-vias having exposed electrical contact points where it penetrates said upper and lower planar surfaces of said module, and the position of said contact points on each surface of said module corresponding to the position of corresponding through-via contact points on adjacent modules, whereby said contact points can be electrically interconnected as described hereinafter; d. said I/O contacts of said electronic components being electrically connected to said through-vias by electrically conductive paths along the interfaces between adjacent layers of said dielectric lamina; and e. a sealable, multichannel connector array between each opposing pair of said modules having separate electrically conductive channels electrically coupling opposing, matching through-vias in said adjacent modules and for sealing said modules when pressed together, thereby hermetically sealing each of said cavities. 22. The stacked multimodular assembly defined in Claim 21 , wherein each of said modules comprises at least about 200 of said through-vias; the electronic components in said assembly comprise at least about 100 I/O contacts electrically connected to said through-vias, said refractory is selected from the group consisting of refractory inorganic oxides, and wherein said multichannel connector array comprises a dielectric plastic or elastomeric layer comprising said electrically conductive channels in an array on centers of about 0.2 inch or less. 23. The multimodular assembly defined in claim 22, wherein each of said channels in said connector array comprises an aperture through said layer containing a compressible, electrically conductive wire bundle. 24. The stacked, multimodular assembly defined in Claim 21, wherein said through-vias constitute continuous thermal conductive paths through said assembly. 25. A method for assembling and electrically interconnecting electronic components which comprises positioning at least one three-dimensional IC chip array in said cavities of each of at least 2 of said modules defined in claim 17, closing and hermetically sealing each of said cavities with a closure plate to form hermetically sealed modules, and electrically connecting the I/O contacts of each said IC chip array to said conductive through-vias, stacking said modules and electrically interconnecting said through-vias therein by interposing between each adjacent pair of modules a multichannel connector array comprising a compressible, dielectric layer having electrically conductive channels corresponding to and interconnecting each opposing pair of through-vias in adjacent modules when pressed together; said through-vias and electrically conductive channels in said connector array being spaced on centers of about 0.2 inch or less.

Inventors: CARSON JOHN C, DECARO ROBERT E, HSU YING, CARSON, JOHN, C., DECARO, ROBERT, E., HSU, YING
Applicants: IRVINE SENSORS CORP, IRVINE SENSORS CORPORATION
Application year: 1996
Main classification: H05K7
IPC codes: H01L23, H01L25, H05K7