Method of aligning layers in a semiconductor device

Abstract: This invention relates to method for forming a semiconductor device on a semiconductor wafer comprising the following steps: forming a plurality of device layers each including a reference mark applied thereon; forming a composite reference mark including one or more features from each of the reference marks applied on the layers which are to be aligned; comparing the reference mark with the features of the marks applied on the or each layer to be aligned in order to identify when the alignment is attained; and forming a next device layer aligned with two or more of said plurality of device layers.

Description: This invention, relates to improvements in or relating to semiconductor processing methods, in particular to a method for aligning a multi-layer device. Semiconductor devices are typically made by building up a number of layers of conductor, semiconductor and insulator material using processing methods, such as photolithography. Typically each of the layers must be aligned with another layer to make up the semiconductor device. The requirement to align the layers is very important, since if the layers are mis-aligned the device is unlikely to work. In current systems, the alignment occurs between one layer and the next one. A mark is applied during the processing stages of the first layer which is used to align the next layer. Should alignment of subsequent layers be required, it would be necessary to apply a new reference mark and then to align the subsequent layer with it. In addition, in the manufacture of most semiconductor devices, there are usually a large number of devices on any single wafer. Since all the devices on any wafer are identical, a mask for a given layer of the device is programmed for a single device and, therefore, the mask is exposed over the whole of the wafer by using a stepper machine. The stepper machine allows the mask for a single device to be reproduced over the whole surface of the wafer. The stepper device exposes the photoresist at the location of the first device and then 'steps' on to the next device and exposes it. This treatment is extended to the whole surface of the wafer. The stepper device can detect when it is in the correct position to expose the next device, by identifying a stepper or reference mark. The stepper mark is a mark which is exposed in the masking step preceding to the one which is currently being carried out. The present system makes it very difficult to align one layer with more than one other layer, especially when the layers are not adjacent. In fact, in the latter case, the failure rate of a process is typically fairly high and/or the processing steps are complicated and laborious. In addition, similar problems are encountered when the stepper device steps from one device to the next one. The combination of the operations for aligning the layers and stepping from one device to the next in the production of a typical semiconductor device is thus fraught with problems, especially when there are more than two layers which need to be aligned with one another. JP-A-07 249 558, corresponding to the later-published US-A-5 532 091, discloses a positioning method for aligning a mask pattern with a substrate to be exposed, particularly applicable when additional patterns are exposed in superimposed fashion on a shot area where plural-layer patterns have already been formed on the substrate to be exposed, said alignment between the predetermined exposure area and the mask pattern being performed on the basis of alignment reference coordinate values. One object of the present invention is to provide a method to overcome at least some of the disadvantages of the prior art. According to the present invention, there is provided a method of forming a semiconductor device on a semiconductor wafer comprising: forming a first device layer including a first reference mark on said semiconductor wafer; forming a second device layer including a second reference mark on said semiconductor wafer, said first and second reference marks being arranged to form a composite mark including- one or more features from said first reference mark and one or more features from said second reference mark; forming a third device layer aligned with said first and second device layers by identifying said composite mark and comparing and aligning it with a composite reference mark. This method has the advantage that it is possible to align each layer in a semiconductor device with the underlying layers. The reference marks used are of hybrid type and as such each layer requiring alignment includes at least a part of the hybrid reference mark. Advantageously the method further comprises the steps recited in claim 2. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will now be further described, by way of example, with reference to the accompanying drawings, wherein: Figure 1 is a diagram showing the layers making up a semiconductor device: Figures 2a to 2d are diagrams showing the process for making a semiconductor device for illustrating the present invention; Figure 3 is a diagram illustrating one of the steps of an embodiment of the present invention; Figure 4 is a diagram showing a second step of an embodiment of the present invention; Figure 5 is a diagram showing a third step of the process of the present invention; Figure 6 is a diagram illustrating the stepping reference marks made on various layers of the device, for operation of the stepper machine; Figure 7 is a diagram illustrating the alignment marks on the various layers; and Figure 8 is a diagram showing all the reference marks produced during the manufacturing process of the device. Referring now to the drawings, Figure 1 illustrates an alignment tree for a memory device being made up of a number of layers. In the Figure, the layers are each represented by a number of letters: MR2 represents a connection layer; VIA represents a via formed in the next layer; MR1 represents connection layer; CT represents a contact layer; BL represents a bit line layer; BLCT represents a bit line contact; GATE represents a gate layer; F/P represents a field plate layer; TRCH represents a trench layer for capacitors; and MOAT represents an active area or moat layer. In addition, Figure 1 also shows a number of dotted lines, these lines represent the layers which are intended to be aligned with one another. For example, it can be seen that the contact layer (CT) needs to be aligned with both the gate and the moat layers and the bit line contact (BLCT) layer should be aligned with the gate and the field plate (F/P) layers. In different types of devices it is possible that different layers will need to be aligned, as it will be apparent to those skilled in the art. The general process steps of Figure 2a-2c show the trench (TRCH), field plate (F/P) and gate (GATE) positions in three levels, 1, 2 and 3. In addition, the relative positions of each of these elements are shown superimposed upon one another in Figure 2d. It is essential that the levels (or layers) be positioned such that the layers be aligned as it is shown in Figure 2d. In Figure 3, it can be seen that, when the trench layer is made, two reference marks are applied to this layer. One mark is the stepper mark (30) and the other one is the alignment mark (32). The stepper mark includes a number of strokes having a predetermined separation from one another and positioned at known orientations with respect to one another. The alignment mark is a square having a known location and size. The two reference marks can be applied at any suitable location on the layer. Typically they are located near the edges of the layer so that they do not cover any one of the component parts of the device. The marks are not limited to be as they are shown but they may be of other shapes and orientations, as long as they are known for a given layer. Referring to Figure 4, the field plate treatment process is shown. In a similar manner to the trench treatment process above, two reference marks are applied during the production of the field plate layer. The first one is a stepper reference mark (40) and the second one is an alignment reference mark (42). The stepper mark includes a number of strokes which are positioned in different positions with respect to the trench stepper reference mark (30), but which can be combined with the reference mark (30) to allow the alignment of a third layer with both the trench and the field plate layers. The reference marks of more than one layer are combined to make a composite or hybrid stepper mark. Therefore, it is possible that two sets of stepper marks be applied to each layer. One set for alignment with single layers and another set for alignment with multiple layers where a composite or hybrid reference mark is used. In the manufacturing process for each of the layers, a stepper machine (not shown) is used, which is capable of identifying the reference marks on the or each layer below the one which is currently being applied. By identifying the reference mark or marks, it is possible to accurately position the current layer with respect to one or more other layers. When one layer is aligned with one other layer, the stepper reference mark is identified by the stepper machine and compared with a stored reference mark to ensure that the layer is correctly and accurately aligned. In the case of an alignment operation with more than one layer, there is a composite reference mark which contains features of the stepper reference marks for each layer. The alignment is effected by ensuring that the composite reference mark is aligned with the features on all relevant underlying layers. Referring to Figure 5, the gate layer process is illustrated. Once again a stepper reference mark (50) and an alignment reference mark (52) are applied. The mark identifiable by the stepper treatment machine is a composite mark containing features extracted from the stepper marks of both the trench and the field plate layers. Referring to Figure 6, the stepper reference marks and the printed marks are shown for each process step. It can be seen that when step three is carried out, that is the process step involving the gate layer, the stepper reference mark is a composite mark made up of features of the marks on each of the trench and field plate layers. By using this technique for aligning a given layer with a composite stepper mark obtained from the reference marks of a number of different layers, it is possible to improve the method for manufacturing a circuit. As previously mentioned, each layer may additionally include an alignment mark, which may be used in the same way as the stepper marks and can assist in the alignment of different layers with each other. Typically the alignment marks are used in conjunction with an overlay machine (not shown) to ensure correct alignment of the layers. Figure 7 illustrates the alignment marks for each of the trench, field plate and gate layers and the combination mark produced when all the layer are accurately overlaid. In Figure 8 the full set of reference marks are shown for the stepping and alignment or overlaying processes. In addition, the final locations of the trench layer (80), the field plate layer (82) and the gate layer (84) can be seen. In the illustrated example, the stepper reference marks are shown as a number of stripes having different positions and lengths. It will be understood that different types of marks could be used other than those shown. The main requirement is that the stepper machine can use the appropriate reference marks to enable recognition of the alignment and stepper marks as applied. It will be appreciated that a different mark will typically be used on each different layer and that composite or hybrid marks will be produced in dependence on the marks of the individual layer. Where there is the need that more than two layers be aligned, the stepper machine will include means for identifying the composite mark to allow alignment with all those layers to which the alignment is required. The composite or hybrid mark could include features extracted from any number of underlying layers depending on which layers must be aligned.

Claims: A method of forming a semiconductor device on a semiconductor wafer comprising: forming a first device layer (1; 80) including a first reference mark (30) on said semiconductor wafer; forming a second device layer (2; 82) including a second reference mark (40) on said semiconductor wafer, said first and second reference mark being arranged to form a composite mark including one or more features from said first reference mark (30) and one or more features from said second reference mark (40); forming a third device layer (3; 84) aligned with said first and second device layers by identifying said composite mark and comparing and aligning it with a composite reference mark. The method according to claim 1, further comprising: storing the composite reference mark in a memory; identifying the composite mark including features of said first and second reference marks applied respectively on the first (1; 80) and second (2; 82) device layers by using a viewing means and comparing and aligning the identified composite mark with the stored composite reference mark; adjusting the position of a processing machine in dependence on said step of identifying, comparing and aligning, such that the next processing step may be performed in the position required for alignment of the third layer with said first and second layers of the semiconductor device.

Inventors: AUZINO LUIGI, CANGIANO AGOSTINO, AUZINO, LUIGI, CANGIANO, AGOSTINO
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS ITALIA SPA, TEXAS INSTRUMENTS INCORPORATED, TEXAS INSTRUMENTS ITALIA S.P.A.
Application year: 1996
Main classification: H01L21
IPC codes: H01L21, G03F9