Static ram with reduced power consumption

Abstract: The invention relates to a memory comprising a matrix of memory cells (12); a plurality of gates (16) for transmitting respective selection outputs (S) of a row decoder (20) to respective rows (RS) of the matrix; a dummy bit line (DBL) having an equivalent load as bit lines (BL, BL') associated to columns of the matrix and which is discharged by a dummy memory cell (22') when any row is selected; and control means (18, MP1) for precharging the bit lines (BL, BL') and the dummy bit line (DBL) when no row is selected, and enabling said gates (16) for transmission of the selection outputs (S) of the row decoder in response to a clock signal (CK). Each gate (16) has an input coupled to the dummy bit line (DBL) such that the gate is disabled as soon as the dummy bit line has discharged to a switching threshold (Vt) of the gate.

Description: The present invention relates to a memory, such as a Static Random Access Memory (SRAM). The invention aims more specifically at reducing the power consumption of a memory during its access cycles. Figure 1 illustrates a conventional architecture of a static RAM, of the type disclosed, for example, in US patent N° 5,471,428. The memory comprises a matrix 10 of memory cells 12. Each row of memory cells is selectable for reading or writing by a row selection line RS. Each memory cell of a column is connected between two complementary bit lines BL and BL'. Each bit line is coupled to a high supply voltage Vdd through a precharge MOS transistor MP1 of P-channel type. The two complementary bit lines BL and BL' of each column are connected to a sense amplifier 14. Each row selection line RS is driven by an AND gate 16 having a first input which receives a common enable signal EN from a control circuit 18. A second input of each AND gate 16 receives a respective selection output S from a row decoder 20. The enable signal EN is also provided to the gates of precharge transistors MP1. The purpose of control circuit 18 and gates 16 is to synchronize the read and write cycles with a clock signal CK received by control circuit 18. The memory further includes a dummy column comprising a dummy bit line DBL to which is connected, in each row, a dummy memory cell 22. The dummy bit line DBL is connected to voltage Vdd, like the other bit lines, through a precharge transistor MP1 and to the input of a circuit equivalent to a sense amplifier 14, for example an inverter 24. The inverter 24 provides a reset signal RST to control circuit 18. Each dummy memory cell is selectable by the row selection line RS of the corresponding row and permanently stores a state which will discharge the dummy bit line DBL when the dummy cell is selected. The function of the dummy column is to notify, with reset signal RST, that an access operation of a row has been completed, i.e. that the values provided by the sense amplifiers 14 are stable. For this purpose, the dummy column should react to a row selection in the same manner as a "normal" column of matrix 10. In particular, it is essential that the dummy bit line DBL and the normal bit lines have equivalent loads. In a static RAM, each memory cell 12 comprises a pair of head-to-tail inverters 26 coupled, at each side, to one of the bit lines BL and BL' through a respective pass transistor MN. Transistors MN are N-channel MOS transistors and their gates are driven by a row selection line RS. Each dummy cell 22 comprises, in this example, a pass transistor MN1 connected to dummy bit line DBL and controlled by a row selection line RS. Inside each dummy cell 22, the pass transistor MN1 is coupled to a low supply voltage Vss through an N-channel MOS transistor MN2. Transistor MN2 has its gate connected to voltage Vdd and is therefore always on. The shown dummy column is a simplified alternative. In a more accurate alternative, the dummy column is similar to the normal columns, except that the inverters of the dummy cells are connected such that the dummy cells are always at the same state. The inverter 24 is then replaced by a complete sense amplifier. Figure 2 shows a time diagram illustrating an access cycle of the static RAM of figure 1. The shown waveforms and the delays between transitions are not to scale. Initially, one selection output S of row decoder 20 is active. The corresponding row selection line RS is not asserted immediately. A rising edge of clock signal CK causes the assertion of enable signal EN, which in turn causes the assertion of row selection line RS and turns off the precharge transistors MP1. Dummy bit line DBL starts discharging through transistors MN1 and MN2 of the selected dummy cell 22. In each of the normal columns, either bit line BL or bit line BL' is discharged under the same conditions by the memory cell 12 of the selected row. When the level of the dummy bit line DBL reaches the threshold Vt of inverter 24, reset signal RST is asserted, causing the fall of enable signal EN, which in turn disables the row selection line RS. The dummy bit line DBL, and therewith the normal bit lines BL and BL', continue discharging as long as the row selection line RS remains asserted. When enable signal EN falls, precharge transistors MP1 are switched on. The precharge transistors MP1 actually start charging the bit lines up to voltage Vdd when the row selection line RS is disabled. The assertion of the reset signal RST indicates the completion of the access cycle. The reset signal RST falls when the level of dummy bit line DBL rises above the threshold Vt of inverter 24. Like in any circuit, there is a need for reducing the power consumption in a memory without reducing its performance. A known solution for reducing the power consumption is shown in figure 1, i.e. signal EN also enables the sense amplifiers 14 so that they become active and consume power only during a short necessary period of the access cycles. As an alternative, sense amplifiers 14 can be enabled by reset signal RST. An object of the present invention is to further reduce the power consumption. The invention is based on the study of an access cycle, such as illustrated in figure 2. It appears that the bit lines continue discharging unnecessarily after reaching the threshold Vt. This unnecessary discharge happens in one bit line of each column and must be compensated by the precharge phase at the end of each access cycle. This causes an unnecessary power consumption which increases with the number of columns. The unnecessary discharge is caused by the delay between the time when the threshold Vt is reached and the subsequent disabling of the row selection line RS. A main contribution to this delay is the time needed for the enable signal EN to fall after the assertion of the reset signal RST. Indeed, the capacitance of the conductors carrying the enable signal EN is particularly large because the enable signal EN is provided to a great number of elements of the memory. Moreover, when the enable signal EN falls, the precharge transistors MP1 are turned on while a row is still selected and tends to discharge the bit lines (when signal EN falls, row selection line RS remains asserted for a short period). This causes additional power consumption. A more specific object of the invention is to reduce the power consumption during an access cycle by limiting the unnecessary discharge of the bit lines. The invention achieves this object by disabling each gate driving a row selection line as soon as the dummy bit line has discharged to a switching threshold of the gate. The invention more specifically provides a memory comprising a matrix of memory cells; a plurality of gates for transmitting respective selection outputs of a row decoder to respective rows of the matrix; a dummy bit line having an equivalent load as bit lines associated to columns of the matrix and which is discharged by a dummy memory cell when any row is selected; and control means for precharging the bit lines and the dummy bit line when no row is selected, and enabling said gates for transmission of the selection outputs of the row decoder in response to a clock signal. Each gate has an input coupled to the dummy bit line such that the gate is disabled as soon as the dummy bit line has discharged to a switching threshold of the gate. According to an embodiment of the invention, the dummy bit line is associated to a dummy column comprising, in each row, a dummy pass transistor which connects the corresponding gate to the dummy bit line at least while the row is selected, and the control means have an enable output for enabling the gates and selecting the dummy memory cell. According to an embodiment of the invention, each gate has three inputs connected, respectively, to the corresponding dummy pass transistor, the corresponding row selection output of the row decoder, and the enable output of the control means. According to an embodiment of the invention, the memory comprises means for precharging the connection between each dummy pass transistor and the corresponding gate when the corresponding row selection output or said enable output is inactive. According to an embodiment of the invention, each dummy pass transistor is directly controlled by the corresponding row selection output of the row decoder, and the corresponding gate has two inputs connected, respectively, to the dummy pass transistor and to the enable output of the control means. According to an embodiment of the invention, the memory comprises means for discharging the connection between each dummy pass transistor and the corresponding gate when the corresponding row selection output is inactive. According to an embodiment of the invention, each dummy pass transistor is directly controlled by the corresponding row selection output of the row decoder, and the corresponding gate has three inputs connected, respectively, to the dummy pass transistor, to the row selection output, and to the enable output of the control means. According to an embodiment of the invention, the memory comprises means for precharging the connection between each dummy pass transistor and the corresponding gate when the corresponding row selection output is inactive. According to an embodiment of the invention, the memory comprises other dummy cells for loading each column of the matrix. The foregoing and other objects, features, aspects and advantages of the invention will become apparent from the following detailed description of embodiments, given by way of illustration and not of limitation with reference to the accompanying drawings, among which: figures 1 and 2, previously described, are intended to illustrate the state of the art and the related problems; figure 3 schematically illustrates a first embodiment of a static RAM architecture according to the invention; figure 4 shows a time diagram illustrating the operation of the static RAM of figure 3; figure 5 shows a second embodiment of a static RAM architecture according to the invention; and figure 6 shows a third embodiment of a static RAM architecture according to the invention. In all figures, same elements are designated with same reference characters. In a memory architecture according to the invention, for example a static RAM, local reset circuitry is provided for each gate 16, adapted to disable the corresponding row selection line RS as soon as possible after the dummy bit line has discharged to the required threshold. This could be achieved by connecting a third input of each gate 16 directly to the dummy bit line DBL. Then, the gate 16 would be disabled when the dummy bit line DBL has discharged to the switching level of the gate, which corresponds substantially to the threshold of inverter 24. As a consequence, the row selection line is disabled without waiting for the rise of reset signal RST and the subsequent fall of enable signal EN. However, by connecting inputs of gates 16 directly to dummy bit line DBL, the load characteristics of this dummy bit line DBL are modified, whereby the necessary matching is lost between the dummy bit line DBL and the normal bit lines BL and BL'. Figure 3 shows a first embodiment of the invention which avoids this drawback. The gates 16 have three inputs, two of which are connected like the two inputs of gates 16 in figure 1. The third input of each gate 16 is connected to a local reset line LRST. The dummy cells 22 of figure 1 are replaced with dummy cells 23 which load the dummy bit line DBL in the same manner, but additionally allow to couple the local reset lines LRST to the dummy line DBL without modifying the load of this dummy line. Each dummy cell 23 comprises a dummy pass transistor MN1' which couples a corresponding local reset line LRST to dummy line DBL. The gate of this pass transistor MN1' is connected to the corresponding row selection line RS. With this arrangement, the dummy cells 23 do not discharge the dummy bit line DBL. Therefore, an additional discharge dummy cell 22' is provided. This additional dummy cell 22' comprises transistors MN1 and MN2 connected as in the dummy cells 22 of figure 1. The gate of transistor MN1 is controlled by the enable signal EN through a three input AND gate 16' serving only to introduce the same delay as the AND gates 16. One input of gate 16' receives the enable signal EN, and the two other inputs are connected to voltage Vdd. In order to maintain the matching between dummy line DBL and the normal bit lines BL and BL', dummy pass transistors MN are connected as capacitors between each bit line BL and BL' and voltage Vss and constitute a dummy cell 27 for each column. To more accurately match the output of gate 16' with the row selection lines RS, the output of gate 16' may be connected (not shown) to the gates of transistors MN of the dummy cells 27. To ensure, if necessary, that the local reset lines LRST do not float when the dummy pass transistors MN1' are off, each line LRST may additionally be coupled to voltage Vdd through two parallel P-channel MOS transistors MP2 and MP3. The gate of transistor MP2 is controlled by the enable signal EN and the gate of transistor MP3 is controlled by the corresponding selection output S of row decoder 20. Transistors MP2 and MP3 will maintain the local reset lines LRST at a precharged state when the corresponding dummy pass transistors MN1' are off. Figure 4 shows a time diagram illustrating an access cycle of the memory of figure 3. The enable signal EN rises shortly after a rising edge of clock signal CK. As the enable signal EN rises, the precharge transistors MP1 are turned off. Shortly afterwards, one row selection line RS is asserted and the output of gate 16' rises at the same time, selecting the additional dummy cell 22'. As a consequence, the dummy bit line DBL and the normal bit lines start discharging. The local reset line LRST corresponding to the selected row follows the evolution of the dummy bit line DBL, since the corresponding pass transistor MN1' is turned on by the row selection line RS. The row selection line RS is disabled soon after the level of the local reset line LRST, following the evolution of the dummy bit line DBL, reaches the switching threshold Vt of gate 16. Then, the row is no longer selected and the bit lines BL and BL' stop discharging, like line LRST. Line LRST and the bit lines BL and BL' will stay at the level reached until the precharge transistors MP1 are turned on. Substantially as soon as the row selection line RS is disabled, the global reset signal RST rises, since the threshold of inverter 24 is substantially equal to the threshold of gates 16. The rise of signal RST causes the fall of enable signal EN, thus the precharge to voltage Vdd of lines LRST, DBL, BL and BL'. Signal RST is disabled as soon as the level of the dummy bit line DBL rises to threshold Vt. Since the additional dummy cell 22' remains selected between the disabling of row selection line RS and the fall of enable signal EN, the dummy bit line DBL continues discharging during this period. However, this does not represent a significant power consumption, since this discharge only affects the single dummy bit line DBL and not the plurality of normal bit lines. In a memory according to the invention, the discharge of the bit lines is thus stopped when the switching threshold of the gates 16 is reached, whereby the energy for precharging the bit lines back to their initial value is practically reduced to the minimum possible value. Moreover, since the enable signal EN falls after the disabling of row selection line RS, the precharge transistors MP1 are not turned on while the cells of the selected row are discharging the bit lines. This further reduces the power consumption. Figure 5 shows a second embodiment of a static memory architecture according to the invention. This embodiment differs from the embodiment of figure 3 in that the gates of the pass transistors MN1' of the dummy cells 23 are directly connected to the selection outputs S of row decoder 20, and in that each gate 16 only has two inputs, one connected to the local reset line LRST and the other to the enable signal EN. The gate 16' controlling the pass transistor of the additional dummy cell 22' also has two inputs, for ensuring a closer match with gates 16. Moreover, each local reset line LRST is coupled to the low supply voltage Vss through an N-channel MOS transistor MN3 and the transistors MP2 and MP3 of figure 3 are omitted. The gate of transistor MN3 is controlled by the logical complement of the corresponding selection output S. Usually, the selection outputs S are provided by inverters 28 of the row decoder 20. Therefore, transistors MN3 may be controlled by the inputs of inverters 28, as shown. The purpose of each transistor MN3 is to pull the local reset line LRST low when the corresponding selection signal S is inactive, so that the gate 16 cannot be inadvertently enabled when the common enable signal EN is asserted. This embodiment operates as illustrated in figure 4. What cannot be seen in figure 4 is that the local reset line LRST of a row to be selected will be connected to the dummy bit line DBL before the row is effectively selected by the corresponding row selection line RS. An advantage of this embodiment is that the gates 16, having only two inputs, are faster than three input gates. Moreover, this embodiment uses less components. Figure 6 shows a third embodiment of a static RAM architecture according to the invention. This embodiment differs from that of figure 3 in that the pass transistors MN1' of dummy cells 23 are directly controlled by the selection outputs S of row decoder 20. Transistor MP2 of figure 3 is unnecessary and transistor MP3 has the same function as transistor MP3 of figure 3. This embodiment operates like the embodiment of figure 5. The invention has been described in relation with static RAMs. It however applies to any memory where a dummy bit line is discharged to detect the completion of an access of the memory. Many alternatives and modifications of the present invention will appear to those skilled in the art. For example, each of the described transistors may be replaced by a transistor of opposite type, controlled by a complementary signal. The local reset lines LRST may be directly connected to the dummy bit line DBL if the resulting modification of the characteristics of the dummy bit line is controllable and can be compensated by modifying the normal bit lines. Of course, this solution would increase the capacitance of the lines, and thus reduce the speed of operation of the memory.

Claims: A memory comprising: a matrix of memory cells (12); a plurality of gates (16) for transmitting respective selection outputs (S) of a row decoder (20) to respective rows (RS) of the matrix; a dummy bit line (DBL) having an equivalent load as bit lines (BL, BL') associated to columns of the matrix and which is discharged by a dummy memory cell (22') when any row is selected; and control means (18, MP1) for precharging the bit lines (BL, BL') and the dummy bit line (DBL) when no row is selected, and enabling said gates (16) for transmission of the selection outputs (S) of the row decoder in response to a clock signal (CK); characterized in that each gate (16) has an input coupled to the dummy bit line (DBL) such that the gate is disabled as soon as the dummy bit line has discharged to a switching threshold (Vt) of the gate, and in that the dummy bit line (DBL) is associated to a dummy column comprising, in each row, a dummy pass transistor (MN1') which connects the corresponding gate (16) to the dummy bit line at least while the row is selected. The memory according to claim 1, characterized in that the control means (18) have an enable output (EN) for enabling the gates and selecting the dummy memory cell (22'). The memory according to claim 2, characterized in that each gate (16) has three inputs connected, respectively, to the corresponding dummy pass transistor (MN1'), the corresponding row selection output (S) of the row decoder, and the enable output (EN) of the control means. The memory according to claim 3, characterized in that it comprises means (MP2, MP3) for precharging the connection (LRST) between each dummy pass transistor (MN1) and the corresponding gate (16) when the corresponding row selection output (S) or said enable output (EN) is inactive. The memory according to claim 2, characterized in that each dummy pass transistor (MN1) is directly controlled by the corresponding row selection output (S) of the row decoder, and in that the corresponding gate (16) has two inputs connected, respectively, to the dummy pass transistor and to the enable output (EN) of the control means. The memory according to claim 5, characterized in that it comprises means (MN3) for discharging the connection (LRST) between each dummy pass transistor (MN1) and the corresponding gate (16) when the corresponding row selection output (S) is inactive. The memory according to claim 2, characterized in that each dummy pass transistor (MN1) is directly controlled by the corresponding row selection output (S) of the row decoder, and in that the corresponding gate (16) has three inputs connected, respectively, to the dummy pass transistor (MN1), to the row selection output (S), and to the enable output (EN) of the control means (18). The memory according to claim 7, characterized in that it comprises means (MP3) for precharging the connection (LRST) between each dummy pass transistor (MN1) and the corresponding gate (16) when the corresponding row selection output (S) is inactive. The memory according to claim 2, characterized in that it comprises other dummy cells (27) for loading each column of the matrix. A method for accessing a memory including a matrix of memory cells (12) and gates (16) for transmitting selection signals (S) to respective rows of the matrix in response to a common enable signal, the method comprising the steps of: precharging normal bit lines (BL, BL') associated to columns of the matrix and a dummy bit line (DBL) having an equivalent load as the normal bit lines; asserting said common enable signal in response to a clock signal (CK); discharging the dummy bit line (DBL); disabling said common enable signal in response to a reset signal generated when the dummy line has discharged to a predetermined level (Vt) ; characterized in that it comprises the step of disabling each gate as soon as the dummy bit line has discharged to a switching threshold (Vt) of the gate, the dummy bit line (DBL) being associated to a dummy column comprising, in each row, a dummy pass transistor (MN1') which connects the corresponding gate (16) to the dummy bit line at least while the row is selected.

Inventors: RIMONDI DANITO, TORRELLI COSIMO, RIMONDI, DANITO, TORRELLI, COSIMO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1996
Main classification: G11C8
IPC codes: G11C8, G11C11