A DELAYED UPDATE REGISTER FOR AN ARRAY

Abstract: An update unit for an array in an integrated circuit is provided. The update unit delays the update of the array until a clock cycle in which the functional input to the array is idle. The input port normally used by the functional input is then used to perform the update. During clock cycles between receiving the update and storing the update into the array, the update unit compares the current functional input address to the update address. If the current functional input address matches the update address, then the update value is provided as the output of the array. Otherwise, the information stored in the indexed storage location is provided. In this manner, the update appears to have been performed in the clock cycle that the update value was received, as in a dual-ported array. A particular embodiment of the update unit is a branch prediction array update unit. This unit is described in detail.

Description: TITLE: A DELAYED UPDATE REGISTER FOR AN ARRAY BACKGROUND OF THE INVENTION 1 Field of the Invention This invention relates to update mechanisms for storage arrays on an integrated circuit and more particularly to an update mechanism for a branch prediction array embodied on a superscalar microprocessor 2 Description of the Relevant Art Integrated circuits are groups of transistors employed on a single monolithic substrate The groups of transistors embody various functions for a system (for example a computer system) One particular example of an integrated circuit is a superscalar microprocessor which embodies multiple instruction processing pipelines Integrated circuits typically have a clock input associated with them which defines a "clock cycle" A clock cycle is an interval of time in which the functions embodied on the integrated circuit complete a portion of their tasks (a "subfunction") At the end of a clock cvcle. the results are moved to the next function or subfunction which operates on the value Integrated circuits may employ arrays for storing information useful to the embodied functions For example data and instruction caches are arrays that are commonK employed within superscalar microprocessors As used herein, the term "array" means a plurality of storage locations configured into a structure from which the values stored in one or more of the plurality of storage locations may be selected for manipulation Arrays are configured with one or more input ports which allow functions to access information stored in the array Each input port may be associated with an output port A particular input port may allow read access write access, or read/write access to storage locations within the array and is referred to as a read port, a write port, or a read/write port respectively A read access is an access in which the value in the selected storage location is transferred to the associated output port and the storage location is left unchanged A write access is an access in which the value in the selected storage location is changed to a value provided with the input port A port which allows read/write access allows either a read or a write access to occur Ports which allow write accesses typically are associated with a write data input port The write data input port conveys the data to be stored at the address provided on the write port "Indexes" are often used to select a storage location within an array An index is a value which indicates which of the plurality of storage locations of an array that a particular access intends to manipulate The act of selecting one of a plurality of storage locations according to an index is called "indexing" In one particular example a set associative cache has an index which identifies which group of sets to access and a "way value" which selects one of the sets within the selected group for manipulation In many cases, more than one access to an array in a given clock cycle may be desirable for the functions an integrated circuit embodies An array which allows two accesses per clock cycle is referred to as "dual-ported" bach port may allow a read access, a write access, or a read/write access Unfortunately, dual-ported arrays are much larger than single ported arrays, often occupying more than double the silicon area of a single ported array which stores the same amount of information One particularly useful dual-ported array is an array in which one port allows a read access while a second (write) port updates a storage location with new information Arrays that are configured in this way do not block a read access with an update, which simplifies array control logic and may improve performance An example of an array configured with a read port and a write port for updates is a branch prediction array associated with a branch prediction unit of a superscalar microprocessor The branch prediction array stores information related to past branch predictions A fetch address is used to index into the branch prediction array, and the information read from the arra\ is used to create a branch prediction associated with the instructions residing at the fetch address When a branch instruction is mispredicted, then the correct address is fetched and new prediction information is calculated The new prediction information should be stored into the branch prediction array in a storage location indexed by the address of the mispredicted branch instruction Then, the next time the branch instruction is fetched, a correct prediction may be made The new prediction information is available to update the branch prediction array in the clock cycle following the cycle in which the correct address is fetched However the clock cycle that the update is available is also a clock cycle in which a fetch address is presented to the branch prediction unit Therefore, a read port for the fetch address and a write port for the update would be useful for the branch prediction array, but the silicon area cost for the dual-ported array is relatively large A mechanism which achieves the effects of a dual-ported array with a read port and a write port without the associated silicon area penalty is desired SUMMARY OF THE INVENTION The problems outlined above are in large part solved by an integrated circuit employing an update unit for an array according to the present invention The update unit delays the update of the array until a clock cycle in which the functional input to the array is idle The input port normally used by the functional input is then used to perform the update During clock cycles between receiving the update and storing the update into the array, the update unit compares the current functional input address to the update address If the current functional input address matches the update address, then the update value is provided as the output of the array Otherwise, the information stored in the indexed storage location is provided In this manner, the update appears to have been performed in the clock cycle that the update value was received, as in the dual-ported array However, the second port has been advantageously removed A large amount of silicon area may be saved A particular embodiment of the update unit is a branch prediction array update unit This embodiment collects the update prediction information for each misprediction or external fetch When a fetch address is presented for branch prediction, the fetch address is compared to the update address stored in the update unit If the addresses match, then the update prediction information is forwarded as the output of the array If the addresses do not match, then the information stored in the indexed storage location is forwarded as the output of the array When the next external fetch begins or mispiediction is detected, the update is written into the branch prediction array This embodiment allows a microprocessor to update branch prediction information speculatively This functionality is desirable because modern microprocessors allow out-of-order execution of instructions, including branch instructions Out-of-order instructions are generally executed speculatively, meaning that the instruction execution is not known to be needed by the sequential execution of the program An instruction may be executed speculatively, for example, if it is on the path that is the target of a predicted branch instruction which has not yet executed An instruction becomes non-speculative when each instruction previous to it is guaranteed to execute, and therefore that instruction is guaranteed to execute If updates were written directly into the array, then speculatively updating the branch prediction information would skew the information with incorrect data Correct prediction rates might suffer However, by placing the update information in the update unit a speculative update may occur If the next branch misprediction is for a branch instruction that is prior to the branch instruction associated with the current update information the current update information is discarded instead of being written into the branch prediction array Performance may be increased by advantageously updating branch prediction information speculatively but being able to discard the information if the branch is not to be executed Broadly speaking, the present invention contemplates an update unit for providing a delayed update to an array on an integrated circuit, comprising an update storage device an input selection device, an output selection device, and a functional array input bus The update storage device stores update information for the array and is coupled to a write input port of the array The input selection device selects an input to the array The update storage device is coupled to the input selection device, which is coupled to an input port of the array Also coupled to the input selection device is the functional array input bus which conveys a non-update input value to the array Coupled to the output port of the array and the update storage device, the output selection device is configured to select between the output port of the array and the update storage device to convey a value as the output of the array The present invention further contemplates a method for delayed update of an array on an integrated circuit The method comprises storing update information in a storage device and updating the array during a clock cycle in which a functional input to the array is idle The present invention still further contemplates an update unit for a branch prediction array comprising four components The first component is a register for storing branch prediction update information which is coupled to an input multiplexor as a first input An address bus for conveying a current fetch address to the branch prediction array is the second component, and address bus is coupled to the input multiplexor as a second input Third is the input multiplexor for selectively coupling the address bus and the register to an input to the array The fourth component is an output multiplexor coupled to an output port of the array and to the register The output multiplexor is configured to select between the output port of the array and the register to convey a value as the output of the array BRIEF DESCRIPTION OF THE DRAWINGS Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which Figure 1 is a block diagram of a superscalar microprocessor embodying the present invention in a branch prediction unit Figure 2 is a diagram of an instruction cache and the branch prediction unit of Figure 1 depicting one embodiment of the present invention Figure 3 is a timing diagram showing one set of events occurring with respect to the embodiment shown in Figure 2 illustrating the delayed update mechanism for the branch prediction array for two consecutive mispredicted branches Figure 4 is a timing diagram showing another set of events occurring with respect to the embodiment shown in Figure 2 illustrating the delayed update mechanism for a mispredicted branch followed by an instruction cache miss While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail . should be understood, however, that the drawings and detailed description thereto are not intended to lim the invention to the particular form disclosed, but on the contrary the intention is to cover all modification equivalents and alternatives falling within the spirit and scope of the present invention as defined by the appended claims DETAILED DESCRIPTION OF THE INVENTION Turning now to Figure 1 , a block diagram of a superscalar microprocessor 200 including a branch prediction unit 220 in accordance with the present invention is shown As illustrated in the embodiment of Figure 1 , superscalar microprocessor 200 includes a prefetch/predecode unit 202 and a branch prediction unit 220 coupled to an instruction cache 204 Instruction alignment unit 206 is coupled between instruction cache 204 and a plurality of decode units 208A-208F (referred to collectively as decode units 208) Each decode unit 208A-208F is coupled to respective reservation station units 210A-210F (referred to collectively as reservation stations 210), and each reservation station 210A-210F is coupled to a respective functional unit 212A-212F (referred to collectively as functional units 212) Decode units 208, reservation stations 210, and functional units 212 are further coupled to a reorder buffer 216, a register file 218 and a load/store unit 222 A data cache 224 is finally shown coupled to load/store unit 222, and an MROM unit 209 is shown coupled to instruction alignment unit 206 Generally speaking, instruction cache 204 is a high speed cache memory provided to temporarily store instructions prior to their dispatch to decode units 208 In one embodiment, instruction cache 204 is configured to cache up to 32 kilobytes of instruction code organized in lines of 16 bytes each (where each byte consists of 8 bits) During operation, instruction code is provided to instruction cache 204 by prefetching code from a main memory (not shown) through prefetch/predecode unit 202 It is noted that instruction cache 204 could be implemented in a set-associative, a fully-associative, or a direct-mapped configuration Prefetch/predecode unit 202 is provided to prefetch instruction code from the main memory for storage within instruction cache 204 In one embodiment, prefetch/predecode unit 202 is configured to burst 64-bιt wide code from the main memory into instruction cache 204 It is understood that a variety of specific code prefetching techniques and algorithms may be employed by prefetch/predecode unit 202 As prefetch/predecode unit 202 fetches instructions from the main memory, it generates three predecode bits associated with each byte of instruction code a start bit, an end bit, and a "functional" bit The predecode bits form tags indicative of the boundaries of each instruction The predecode tags may also convey additional information such as whether a given instruction can be decoded directly by decode units 208 or whether the instruction must be executed by invoking a microcode procedure controlled by MROM unit 209, as will be described in greater detail below Table 1 indicates one encoding of the predecode tags As indicated within the table, if a given byte is the first byte of an instruction, the start bit for that byte is set If the byte is the last byte of an instruction, the end bit for that byte is set If a particular instruction cannot be directly decoded by the decode units 208, the functional bit associated with the first byte of the instruction is set On the other hand, if the instruction can be directly decoded by the decode units 208, the functional bit associated with the first byte of the instruction is cleared The functional bit for the second byte of a particular instruction is cleared if the opcode is the first byte, and is set if the opcode is the second byte It is noted that in situations where the opcode is the second byte, the first byte is a prefix byte The functional bit values for instruction byte numbers 3-8 indicate whether the byte is a MODRM or an SIB byte, or whether the byte contains displacement or immediate data Table 1 Encoding of Start, End and Functional Bits Instr Start End Functional Byte Bit Bit Bit Number Value Value Value Meanine 1 1 X 0 Fast decode 1 1 X 1 MROM instr 2 0 X 0 Opcode is first byte 2 0 X 1 Opcode is this byte, first byte is prefix 3-8 0 X 0 Mod R/M or SIB byte 3-8 0 X 1 Displacement or immediate data, the second functional bit set in bytes 3-8 indicates immediate data 1 -8 X 0 λ Not last byte of instruction 1 -8 X 1 X Last byte of instruction As stated previously, in one embodiment certain instructions w ithin the x86 instruction set may be directly decoded by decode unit 208 These instructions are referred to as "fast path" instructions The remaining instructions of the x86 instruction set are referred to as "MROM instructions" MROM instructions are executed by invoking MROM unit 209 More specifically when an MROM instruction is encountered, MROM unit 209 parses and serializes the instruction into a subset of defined fast path instructions to effectuate a desired operation A listing of exemplary x86 instructions categorized as fast path instructions as well as a description of the manner of handling both fast path and MROM instructions will be provided further below Instruction alignment unit 206 is provided to channel variable byte length instructions from instruction cache 204 to fixed issue positions formed by decode units 208A-208F Instruction alignment unit 206 independently and in parallel selects instructions from thiee groups of instruction bytes provided by instruction cache 204 and arranges these bytes into three groups of preliminary issue positions Each group of issue positions is associated with one of the three groups of instruction bytes The preliminary issue positions are then merged together to form the final issue positions each of which is coupled to one of decode units 208 Before proceeding with a detailed description of the branch prediction array update mechanism within branch prediction unit 220, general aspects regarding other subsystems employed within the exemplary superscalar microprocessor 200 of Figure I will be described For the embodiment of Figure each of the decode units 208 includes decoding circuitry for decoding the predetermined fast path instructions referred to above In addition, each decode unit 208A-208F routes displacement and immediate data to a corresponding reservation station unit 210A-210F Output signals from the decode units 208 include bit-encoded execution instructions for the functional units 212 as well as operand address information, immediate data and/or displacement data The superscalar microprocessor of Figure 1 supports out of order execution, and thus employs reorder buffer 216 to keep track of the original program sequence for register read and write operations, to implement register renaming, to allow for speculative instruction execution and branch misprediction recovery, and to facilitate precise exceptions As will be appreciated by those of skill in the art, a temporary storage location within reorder buffer 216 is reserved upon decode of an instruction that involves the update of a register to thereby store speculative register states Reorder buffer 216 may be implemented in a first-m- first-out configuration wherein speculative results move to the "bottom" of the buffer as they are validated and written to the register file, thus making room for new entries at the "top" of the buffer Other specific configurations of reorder buffer 216 are also possible, as will be described further below If a branch prediction is incorrect, the results of speculativelv-executed instructions along the mispredicted path can be invalidated in the buffer before thev are written to register file 218 The bit-encoded execution instructions and immediate data provided at the outputs of decode units 208A-208F are routed directly to respective reservation station units 21 OA-21 OF In one embodiment, each reservation station unit 210A-210F is capable of holding instruction information (l e , bit encoded execution bits as well as operand values, operand tags and/or immediate data) for up to three pending instructions awaiting issue to the corresponding functional unit It is noted that for the embodiment of Figure 1 , each decode unit 208A-208F is associated with a dedicated reservation station unit 210A-210r, and that each reservation station unit 210A-210F is similarly associated with a dedicated functional unit 212A-212F Accordingly, six dedicated "issue positions" are formed by decode units 208 reservation station units 210 and functional units 212 Instructions aligned and dispatched to issue position 0 through decode unit 208A are passed to reservation station unit 210A and subsequently to functional unit 212A for execution Similarly, instructions aligned and dispatched to decode unit 208B are passed to reservation station unit 210B and into functional unit 212B, and so on Upon decode of a particular instruction, if a required operand is a register location, register address information is routed to reorder buffer 216 and register file 218 simultaneously Those of skill in the art will appreciate that the x86 register file includes eight 32 bit real registers (l e typically referred to as EAX, EBX, ECX, EDX, EBP, ESI, EDI and ESP) Reorder buffer 216 contains temporary storage locations for results which change the contents of these registers to thereby allow out of order execution A temporary storage location of reorder buffer 216 is reserved for each instruction which, upon decode, is determined to modify the contents of one of the real registers Therefoie, at various points during execution of a particular program reorder buffer 216 may have one or more locations which contain the speculatively executed contents of a given register If following decode of a given instruction it is determined that reorder buffer 216 has a previous location or locations assigned to a register used as an operand in the given instruction, the reorder buffer 216 forwards to the corresponding reservation station either 1) the value in the most recently assigned location, or 2) a tag for the most recently assigned location if the value has not yet been produced by the functional unit that will eventually execute the previous instruction If the reorder buffer has a location reserved for a given register, the operand value (or tag) is provided from reorder buffer 216 rather than from register file 218 If there is no location reserved for a required register in reorder buffer 216, the value is taken directly from register file 218 If the operand corresponds to a memory location, the operand value is provided to the reservation station unit through load/store unit 222 Details regarding suitable reorder buffer implementations may be found within the publication "Superscalar Microprocessor Design" by Mike Johnson, Prentice-Hall, Englewood Cliffs, New Jersey, 1991 , and within the co-pending, commonly assigned patent application entitled "High Performance Superscalar Microprocessor", Serial No 08/146,382, filed October 29, 1993 by Witt, et al I hese documents are incorporated herein by reference in their entirety Reservation station units 210A-210F are provided to temporarily store instruction information to be speculatively executed by the corresponding functional units 212A-212F As stated previously, each reservation station unit 210A-210F may store instruction information for up to three pending instructions Each of the six reservation stations 210A-210F contain locations to store bit-encoded execution instructions to be speculatively executed by the corresponding functional unit and the values of operands If a particular operand is not available, a tag for that operand is provided from reorder buffer 216 and is stored within the corresponding reservation station until the result has been generated (1 e , by completion of the execution of a previous instruction) It is noted that when an instruction is executed by one of the functional units 212A- 212F, the result of that instruction is passed directly to any reservation station units 210 A-21 OF that are waiting for that result at the same time the result is passed to update reorder buffer 216 (this technique is commonly referred to as "result forwarding") Instructions are issued to functional units for execution after the values of any required operand(s) are made available That is, if an operand associated with a pending instruction within one of the reservation station units 210A-210r has been tagged with a location of a previous result value within reorder buffer 216 which corresponds to an instruction which modifies the required operand, the instruction is not issued to the corresponding functional unit 212 until the operand result for the previous instruction has been obtained Accordingly, the order in which instructions are executed may not be the same as the order of the original program instruction sequence Reorder buffer 216 ensures that data coherency is maintained in situations where read-aftcr-wπte dependencies occur In one embodiment, each of the functional units 212 is configured to perform integer arithmetic operations of addition and subtraction, as well as shifts, rotates, logical operations, and branch operations It is noted that a floating point unit (not shown) may also be employed to accommodate floating point operations Each of the functional units 212 also provides information regarding the execution of conditional branch instructions to the branch prediction unit 220 If a branch prediction was incorrect, branch prediction unit 220 flushes instructions subsequent to the mispredicted branch that have entered the instruction processing pipeline, and causes prefetch/predecode unit 202 to fetch the required instructions from instruction cache 204 or main memory It is noted that in such situations, results of instructions in the original program sequence which occur after the mispredicted branch instruction are discarded, including those which were speculatively executed and temporarily stored in load/store unit 222 and reorder buffer 216 Exemplary configurations of suitable branch prediction mechanisms are well known Results produced by functional units 212 are sent to the reorder buffer 216 if a register value is being updated, and to the load/store unit 222 if the contents of a memory location is changed If the result is to be stored in a register, the reorder buffer 216 stores the result in the location reserved for the value of the register when the instruction was decoded As stated previously, results are also broadcast to reservation station units 210A-210F where pending instructions may be waiting for the results of previous instruction executions to obtain the required operand values Generally speaking, load/store unit 222 provides an interface between functional units 212A-212F and data cache 224 In one embodiment load/store unit 222 is configured with a load/store buffer with eight storage locations for data and address information for pending loads or stores Decode units 208 arbitrate fot access to the load/store unit 222 When the buffer is full, a decode unit must wait until the load/store unit 222 has room for the pending load or store request information The load/store unit 222 also performs dependency checking for load instructions against pending store instructions to ensure that data coherency is maintained Data cache 224 is a high speed cache memory provided to temporarily store data being transferred between load/store unit 222 and the main memory subsystem In one embodiment, data cache 224 has a capacity of storing up to eight kilobytes of data It is understood that data cache 224 may be implemented in a variety of specific memory configurations, including a set associative configuration Turning now to Figure 2, a diagram of instruction cache 204 and branch prediction unit 220 is shown Instruction cache 204 includes a branch holding register 250, a current fetch PC register 251, and an instruction cache storage array 252 Current fetch PC register 251 contains the current fetch address and indexes into instruction storage array 252 to fetch instructions Both fetch PC register 251 and branch holding register 250 are coupled to a comparator 253 and an input multiplexor 254 within branch prediction unit 220 Input multiplexor 254 is coupled to a read/write input port of a branch prediction array 255 Coupled to a write data port of branch prediction array 255 is branch update data register 256 Both the output of branch prediction array 255 and branch update data register 256 are coupled to an output multiplexor 257 which receives its select line from comparator 253 Output multiplexor 257 is coupled to a branch prediction logic block 258, which manipulates the data transferred by output multiplexor 257 and produces a branch prediction which is conveyed to instruction cache 204 on a branch prediction bus 259 Therefore, the output of multiplexor 257 is considered to be the output of branch prediction array 255 Instruction cache 204 stores the address conveyed on branch prediction bus 259 in the current fetch PC register unless a branch misprediction or exception is indicated by reorder buffer 216 Generally speaking, branch holding register 250, branch update data register 256, input multiplexor 254 and output multiplexor 257 provide a mechanism by which a delayed update of branch prediction array 255 may be made The address of the branch instruction which was mispredicted is stored in branch holding register 250, and the associated branch prediction data is stored in branch update data register 256 Input multiplexor 254 is an input selection device for branch prediction array 255, and is used to select the current fetch PC address for branch prediction processing or the branch holding register to provide the update to branch prediction array 255 Therefore, the current fetch PC address is selected for reading only and the branch holding register is selecting for writing only In this way, branch prediction array 255 may be single ported while still effectively providing the simultaneous read and update function of the dual-ported array Instead of performing the update immediately, the update is delayed until a cycle in which the current fetch PC register is invalid However, the update information is made visible via comparator 253 and output multiplexor 257 Comparator 253 compares the addresses stored in current fetch PC register 251 and branch holding register 250 Output multiplexor 257 is an output selection device which selects the output of branch prediction array 255 if comparator 253 indicates not equal and selects the branch update data register if comparator 253 indicates equal Therefore, if the branch instruction whose correct prediction information is held in branch update data register 256 is refetched before the update is written to branch prediction array 255. the correct prediction information will be processed As mentioned above, branch holding register 250 stores the address of the last mispredicted branch instruction until an opportunity to update branch prediction array 255 occurs Branch update data register 256 stores the branch prediction data associated with the address stored in branch holding register 250 Together, branch update data register 256 and branch holding register 250 form an update storage device that allows a branch prediction update to be stored until a convenient clock cycle in which to perform the update to branch prediction array 255 In one embodiment, an update occurs the clock cycle following another mispredicted branch detection by reorder buffer 216 and the clock cycle when an external instruction fetch is started in response to an instruction cache miss Instruction cache 204 detects such clock cycles and causes an update select line 260 to convey a signal to input multiplexor 254 indicating that branch holding register 250 should be selected to access branch prediction array 255 In clock cycles in which the above mentioned events are not detected, the current fetch PC is selected to access branch prediction array 255 such that branch predictions are provided for each instruction fetch The clock cycle following a branch misprediction detection by reorder buffer 216 is a clock cycle in which the current fetch PC is invalid because the corrected address provided by reorder buffer 216 (or one of functional units 212) is a logical address The logical address is converted to a linear address before accessing instruction cache 204 As will be appreciated by those skilled in the art, branch instruction execution in the x86 architecture produces a logical (or virtual) address 1 he logical address is translated first to a linear address and then to a physical address as detailed in the publication "Programming the 80386" by John H Crawford, et al, Sybex, Inc San Francisco, California, 1987 1 his publication is incorporated herein by reference in its entirety In an embodiment of microprocessor 200, instruction cache 204 stores instructions based on their linear address Therefore, the update update occurs during a clock cycle in which current fetch PC register 251 cannot access branch prediction array 255, and so the update is performed with no performance penalty Similarly, when an external fetch is started, the current fetch PC contains an address that need not access the branch prediction array The instructions associated with the current fetch PC address will not be available until they are returned from external memory, typically at least several clock cycles The branch prediction information will be determined from the instructions fetched, and so branch prediction array 255 need not be accessed 1 herefore, the update occurs during a clock cycle in which current fetch PC register 251 does not need access to branch prediction array 255 Branch holding register 250 and branch update data register 256 are also used to hold predecoded branch prediction information produced by prefetch/predecode unit 202 when instructions are being fetched into instruction cache 204 from main memory The update to branch prediction array 255 when an external fetch is started allows prefetch/predecode unit 202 access to branch holding register 250 and branch update data register 256 In one embodiment, branch update data register 256 stores the successor index, branch counters, the byte position within the cache line of the branch instruction, and a way value associated with the branch address in branch holding register 250 The successor index includes the index bits for instruction cache 204 of the branch prediction for the branch instruction The branch counters are counters associated with the branch prediction mechanisms employed by microprocessor 200 Any suitable branch prediction mechanism may be employed, and various branch prediction mechanisms are well-known The way value recorded is the way of instruction cache 204 in which the corrected fetch address is stored Branch prediction array 255 is in one embodiment, a linear array of storage locations which store the information stored in branch update data register 256 In one embodiment two fields of data in the form stored in branch update data register 256 are stored and branch prediction array 255 is configured with 2048 entries Branch prediction logic block 258 chooses one of the two fields from an indexed storage location according to the branch prediction mechanism implemented by microprocessor 200 When updating branch prediction array 255, one of the two fields stored in a the storage location indexed by the branch instruction address is replaced by the update information If the update is due to a misprediction with respect to an address stored within branch prediction array 255, then the mispredicted address is updated with the corrected prediction information If the branch was not detected at prediction time or was predicted not taken, then the field that predicts a non-taken branch is replaced by the new information A bit for each field is sent along with the predicted branch instruction and returned by leorder buffer 216 along with the misprediction indication and corrected fetch address The bit indicates when set that the corresponding field predicts a taken branch The bit indicates when cleared that the corresponding field predicts a non-taken branch This information is used to select a non-taken branch for replacement with the new information If both addresses stored in a particular entry are predicted taken, then a pseudo-random selection policy is used for the replacement In one embodiment, the pseudo-random policy is to select an entry to replace based on the least significant bit of the corrected fetch address If the bit is set, the second entry is replaced If the bit is clear, the first entry is replaced It is noted that the branch holding register and branch update data may be used to allow out of ordei update of branch prediction information without disturbing the contents of the branch prediction array If a branch instruction is executed speculatively and mispredicted, it may be written into the branch prediction register and the branch update data register On the next misprediction, the new misprediction is checked to see if it is prior to the speculatively stored misprediction If the new misprediction is prior to the speculative misprediction, the branch holding register and branch update data register are invalidated and not written into the branch prediction array Instead, the new misprediction data overwrites the previously stored misprediction data If the new misprediction is not prior to the speculative misprediction, the speculative misprediction data is correct and the new misprediction information is not written into the branch holding register at this time Speculative misprediction results are held in the branch holding register until they are indicated to be non-speculative by reorder buffer 216 Then they may be written into the branch prediction array at the next misprediction or external fetch It is further noted that the information stored in branch update data register 256 may vary from embodiment to embodiment, as may the information stored in branch prediction array 255 and the size of branch prediction array 255 It is also noted that, although the input selection device is represented by input multiplexor 254, the input selection device may vary from embodiment to embodiment Specifically, multiple multiplexor devices may form the input selection device Similarly, the output selection device may vary from embodiment to embodiment Turning now to Figure 3, a timing diagram illustrates the clock cycles during which branch prediction array 255, branch holding register 250, and branch update data register 256 are updated for the case of two consecutive mispredicted branches In ICLK 1 , branch holding register 250 contains an address A as shown in block 300 and branch update data register 256 contains the update data associated with address A Address A is a misprediction or external fetch address detected in a clock cycle prior to 1CLK 1 In ICLK 1 , reorder buffer 216 indicates that a misprediction has been detected, as shown in block 301 The corrected fetch address associated with the mispredicted branch instruction is conveyed to instruction cache 204 In ICLK2, a signal on update select line 260 indicates that the branch history register should be selected by input multiplexor 254 While the instruction cache translates the logical corrected address to a linear address (as indicated by block 302 in Figure 3), address A and its associated branch prediction information are written into branch prediction array 255 (as indicated by block 303 where "BPA" is an abbreviation for branch prediction arraj ) In 1CL 3, the corrected address has been translated to a linear address and accesses instruction cache 204 and branch prediction array 255, as indicated by block 305 The way value of instruction cache 204 storing the instructions associated with the corrected address is stored in branch update data register 256 In ICLK4 and subsequent clock cycles, branch holding register 250 and branch update data register 256 contain the corrected fetch address and associated branch prediction data, respectively (as indicated by block 306) Later, in ICLKN, another branch misprediction is detected as indicated by block 307 In ICLKN+ 1 , similar to ICLK2, the new address ("Corrected Addr2") is translated to a linear address and the corrected address currently stored in branch holding register 250 ("Corrected Addr") is written into the branch prediction array (as indicated by blocks 308 and 209, respectively) Turning now to Figure 4, a second timing diagram depicts a misprediction followed by an external fetch to further illustrate operation of the branch holding register Similar to Figure 4, branch holding register 250 contains an address A as shown in block 400, and branch update data register 256 contains the update data associated with address A In ICLK1 , reorder buffer 216 indicates that a misprediction has been detected, as shown in block 401 In ICLK2, a signal on update select line 260 indicates that the branch history register should be selected by input multiplexor 254 While instruction cache 204 translates the logical corrected address to a linear address (as indicated by block 402 in Figure 4), address A and its associated branch prediction information are written into branch prediction array 255 (as indicated by block 403) In ICLK3, the corrected address has been translated to a linear address and accesses instruction cache 204 and branch prediction array 255, as indicate by block 405 The way value of instruction cache 204 storing the instructions associated with the corrected address is stored in branch update data register 256 In ICLK4 and subsequent clock cycles, branch holding register 250 and branch update data register 256 contain the corrected fetch address and associated branch prediction data, respectively (as indicated by block 406) Later, in ICLKN, instruction cache 204 detects an instruction cache miss (as indicated by block 407) In ICLKN+ 1 , an external fetch begins (as indicated by block 408) and the corrected fetch address from the previous misprediction is written into branch prediction array 255 (as indicated by block 409) In a later clock cycle (not shown) the external fetch data arrives and predecoding is performed When a branch instruction is predecoded, the predecoded information and branch address are stored in branch update data register 256 and branch holding register 250, respectively, until the next misprediction is detected or until the next external fetch begins As can be seen from the above timing diagrams, external fetches and bianch mispredictions may occur in any order Each time one of the two events occurs, the data associated with the previous event is written into the branch prediction array The data associated with the new event is written into the branch holding register and branch update data register It is noted that aspects regarding instruction cache 204 are described within the co-pending, commonly assigned patent application entitled "Linearly Addressable Microprocessor Cache", Serial No 08/146,381 , filed October 29, 1993 by Witt The disclosure of this patent application is incorporated herein by reference in its entirety In accordance with the above disclosure an update mechanism for a branch prediction array is described which allows updates to be delayed, eliminating a dual-port array in favor of a single port array for the branch prediction array A large amount of silicon area may therefore be saved, at little cost in complexity of operation of the array It is noted that, although this embodiment describes the delayed update mechanism in terms of a branch prediction array, many other applications of this mechanism exist It is further specifically contemplated that this mechanism may be adapted to any dual-ported array included on an integrated circuit in which one of the ports is used for updating the array. Numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated. It is intended that the following claims be inteφreted to embrace all such variations and modifications.

Claims: WHAT IS CLAIMED IS: 1. An update unit for providing a delayed update to a branch prediction array on a superscalar microprocessor, comprising: an update storage device for storing branch prediction update information for said branch prediction array wherein said update storage device is coupled to a write input data port of said branch prediction array, and wherein said update information includes an update address; an input selection device for selecting an input to said branch prediction array wherein said input selection device is coupled to an input port of said branch prediction array and has said update storage device coupled as a first input; a functional array input bus for conveying an instruction fetch address to said array wherein said functional array input bus is coupled to said input selection device as a second input; and an output selection device coupled to an output port of said branch prediction array and further coupled to said update storage device wherein said output selection device is configured to select between said output port of said branch prediction array and said update storage device to convey a value as an output of said branch prediction array. 2. The update unit as recited in claim 1 wherein said update storage device comprises a register. 3. The update unit as recited in claim I wherein said input selection device comprises a multiplexor and a multiplexor select signal line. 4. The update unit as recited in claim 3 wherein said multiplexor select signal line is configured to convey a signal which selects said branch prediction update information stored in said update storage device during a clock cycle in which said functional array input bus is idle. 5. The update unit as recited in claim 3 wherein said multiplexor select signal line is configured to convey a signal which selects said fetch address conveyed on said functional array input bus during a clock cycle in which said functional array input bus is not idle. 6. The update unit as recited in claim 1 wherein said output selection device comprises a multiplexor and a multiplexor select signal line. 7. The update unit as recited in claim 6 wherein said multiplexor select signal line is configured to convey a signal which selects said value conveyed on said array output port during a clock cycle in which said functional array input bus is selected by said input selection device and said fetch address conveyed on said functional array input bus indexes a storage location within said branch prediction array different from a second storage location indexed by said update address. 8. The update unit as recited in claim 6 wherein said multiplexor select signal line is configured to convey a signal which selects said branch prediction update information stored in said update storage device during a clock cycle in which said functional array input bus is selected by said input selection device and said fetch address conveyed on said functional array input bus indexes a storage location within said array, and wherein said update address indexes said storage location. 9. The update unit as recited in claim 1 further comprising a comparator circuit wherein said comparator circuit is configured to compare said update address to said fetch address. 10. The update unit as recited in claim 9 wherein said comparator circuit is coupled to said output selection device, and wherein said comparator circuit is configured to cause said output selection device to select an output value. 1 1. The update unit as recited in claim 10 wherein said comparator circuit is further configured to cause said output selection device to select said value conveyed on said output port of said array during a clock cycle in which said comparator circuit detects that said update address is not equal to said fetch address. 12. The update unit as recited in claim 10 wherein said comparator circuit is further configured to cause said output selection device to select said update information during a clock cycle in which said comparator circuit detects that said update address is equal to said fetch address. 13. A method for delayed update of a branch prediction array on a superscalar microprocessor, comprising: storing branch prediction update information in a storage device wherein said branch prediction update information includes an update address; and updating said branch prediction array during a clock cycle in which a functional input to said branch prediction array is idle. 14. The method as recited in claim 13 further comprising determining that said functional input is going to be idle during said clock cycle. 15. The method as recited in claim 13 further comprising comparing a value conveyed on said functional input to said update address. 16. The method as recited in claim 15 further comprising forwarding said branch prediction update information as an output of said branch prediction array during a second clock cycle in which said comparing step indicates equality 17 The method as recited in claim 15 further comprising forwarding information stored within a storage location which is indexed by said value as an output of said branch prediction array during a second clock cycle in which said comparing step indicates inequality 18 The method as recited in claim 13 wherein said branch prediction update information is speculative and wherein said updating step occurs after said branch prediction update information becomes non-speculative 19 A superscalar microprocessor comprising a branch prediction unit including a branch prediction array and a branch prediction array update unit which includes a register for storing branch prediction update information wherein said register is coupled to a write input data port of said branch prediction array and is further coupled to an input multiplexor as a first input, and wherein said update information includes an update address, an address bus for conveying a current fetch address to said branch prediction array wherein said address bus is coupled to said input multiplexor as a second input, said input multiplexor for selectively coupling said address bus and said register to an input to said array wherein said input multiplexor is coupled to an input port of said array, and an output multiplexor coupled to an output port of said array and further coupled to said register wherein said output multiplexor is configured to select between said output port of said array and said register to convey a value as an output of said array 20 The superscalar microprocessor as recited in claim 19 wherein said input multiplexor is further configured with a multiplexor select signal line 21 The superscalar microprocessor as recited in claim 20 wherein said multiplexor select signal line is configured to convey a signal which selects said update information stored in said register during a clock cycle in which said address bus is idle 22 The superscalar microprocessor as recited in claim 0 wherein said multiplexor select signal line is configured to convey a signal which selects said current fetch address conveyed on said address bus during a clock cycle in which said address bus is not idle 23 The superscalar microprocessor as recited in claim 19 wherein said output multiplexor is further configured with a multiplexor select signal line 24 The superscalar microprocessor as recited in claim 23 wherein said multiplexor select signal line is configured to convey a signal which selects said value conveyed on said array output port during a clock cycle in which said address bus is selected by said input multiplexor and said current fetch address conveyed on said address bus indexes a storage location within said array different from a second storage location indexed by said update address 25 The superscalar microprocessor as recited in claim 23 wherein said multiplexor select signal line is configured to convey a signal which selects said update information stored in said register during a clock cycle in which said address bus is selected by said input multiplexor and said current fetch address conveyed on said address bus indexes a storage location within said array and wherein said update address indexes said storage location 26 The superscalar microprocessor as recited in claim 1 further comprising a comparator circuit wherein said comparator circuit is configured to compare said update address to said current fetch address 27 The superscalar microprocessor as recited in claim 26 wherein said comparator circuit is coupled to said output multiplexor, and wherein said comparator circuit is configured to cause said output multiplexor to select an output value 28 The superscalar microprocessor as recited in claim 27 wherein said comparator circuit is further configured to cause said output multiplexor to select said value conveyed on said output port of said array during a clock cycle in which said comparator circuit detects that said update address is not equal to said current fetch address 29 The superscalar microprocessor as recited in claim 27 wherein said comparator circuit is further configured to cause said output multiplexor to select said update information during a clock cycle in which said comparator circuit detects that said update address is equal to said current fetch address 30 The superscalar microprocessor as recited in claim 19 further comprising an instruction cache coupled to said branch prediction unit for storing previously fetched instructions, and a prefetch/predecode unit coupled to said instruction cache for fetching instruction bytes from a main memory into said instruction cache and for predecoding said instructions 31 The superscalar microprocessor as recited in claim 30 wherein said instruction cache is further configured to receive a branch prediction address from said branch prediction unit and to fetch instructions from said branch prediction address 32 The superscalar microprocessor as recited in claim 31 wherein said instruction cache is further configured to provide a current fetch address to said branch prediction unit on said address bus 33 The superscalar microprocessor as recited in claim 30 wherein said prefetch/predecode unit is further configured to provide branch predecode information to said branch prediction unit during clock cycles in which instruction bytes are being fetched from said main memory 34 The superscalar microprocessor as recited in claim 30 wherein said instruction cache is further configured to provide said prefetch/predecode unit with instruction fetch addresses which miss said instruction cache 35 The superscalar microprocessor as recited in claim 30 further comprising an instruction alignment unit coupled to said instruction cache for aligning instructions received from said instruction cache to a plurality of decode units 36 The superscalar microprocessor as recited in claim 35 wherein said instruction cache is further configured to provide instructions from a branch prediction address to said instruction alignment unit 37 The superscalar microprocessor as recited in claim 35 further comprising said plurality of decode units coupled to said instruction alignment unit for decoding instructions provided by said instruction alignment unit, an MROM unit coupled to said instruction alignment unit for executing MROM-type instructions a plurality of reservation station units wherein each one of said reservation station units is coupled to a respective one of said plurality of decode units and wherein said reservation station units are configured to store decoded instructions until said decoded instructions are provided with operands and a functional unit is available to execute said decoded instructions, a plurality of functional units configured to execute instructions wherein each one of said plurality of functional units is coupled to a respective one of said reservation station units, a reorder buffer for retiring instructions in program order and providing operands to instructions coupled to said plurality of decode units, said plurality of reservation station units, and said plurality of functional units, and a register file coupled to said reorder buffer and to said plurality of reservation station units and said plurality of decode unit wherein said register file is configured to store architected registers. 38. The superscalar microprocessor as recited in claim 37 further comprising: a load/store unit coupled to said plurality of functional units and said plurality of decode units wherein said load/store unit is configured to execute load and store instructions; and a data cache coupled to said load/store unit and to said main memory for storing previously accessed data. 39. An update unit for providing a delayed update to a branch prediction array on a superscalar microprocessor, comprising: an update storage device; an input selection device; and an output selection device.

Inventors: TRAN THANG M, WITT DAVID B, TRAN, THANG, M., WITT, DAVID, B.
Applicants: ADVANCED MICRO DEVICES INC, ADVANCED MICRO DEVICES, INC.
Application year: 1996
Main classification: G06F9
IPC codes: G06F9