Variable gain mixer having improved linearity and lower switching noise

Abstract: A mixer section is combined with a post-mixer linearizer to counteract the nonlinear transconductance characteristics of the RF input section of the mixer thereby increasing the overall linear response of the mixer. The post-mixer linearizer has a response that is increasingly non-linear outside the non-linear operating range of the RF input section. This non-linear response compensates for the decreasingly non-linear response of the RF input section. Current mirrors in the post-mixer linearizer increase the rail-to-rail headroom of the mixer while maintaining high gain. An input driver is coupled to the mixer that provides quick switching transitions in the mixer to reduce noise effects. The mixer also includes a gain control circuit that provides linear-in-decibel gain control.

Description: This invention relates generally to analog receiver circuits and more particularly to a radio frequency variable gain mixer. An example of a classic active mixer is shown in FIG. 1. The mixer 10 is comprised of a mixer core 13, which includes transistors Q1-Q4, and an RF input section 15. The mixer 10 is commonly known as the "Gilbert Mixer" after the inventor of the present application. In fact, a prior art search at the time of the invention thereof produced a reference, U.S. Patent No. 3,241,078 issued to Jones, which showed essentially the same circuit, although it was described as a "synchronous detector," and did not seem to envision its utility in mixer applications. The operation of the mixer 10 is as follows. In the absence of any voltage difference between the base of Q5 and Q6, the collector currents of these two transistors are essentially equal. Thus, a voltage applied to the LO port 12 results in no change of output current. Should a small DC offset voltage be present at the RF port (e.g., due to a mismatch in the emitter areas of Q5 and Q6), this will only result to a small feed through of the LO signal V LO to the IF port 16, which will be blocked by a first IF filter (not shown). Conversely, if an RF signal V RF is applied to the RF port 14, but no voltage difference is applied to the LO port 12, the output currents will again be balanced. A small offset voltage (due now to emitter mismatch in Q1-Q4) may cause some RF signal feed through to the IF port; as before, this will be rejected by the IF filter. Thus it is only then when a signal supplied to both the LO port 12 and the RF port 14 that a signal appears at the IF port 16. FIG. 2 is a graph showing the relationship between the RF input voltage (V RF ) and output voltage (V IF ) for the mixer 10, where the LO signal V LO is held at a DC value. As is known in the art, the relationship between V RF and V IF can be described by the hyperbolic tangent (tanh) function. As can be seen in FIG. 2, there is essentially a linear relationship between the input and output signals for a certain small operating range, generally between points 22 and 23. This is due to the linear transconductance (g m ) of the RF input section over that operating range. The g m of transistors Q5 and Q6, however, becomes increasingly nonlinear outside this small operating range causing the slope of the response to decline past points 22 and 23. The nonlinear operating characteristics of g m effectively compresses the input signal, inducing unwanted inter-modulation products in the mixer output signal. Emitter degeneration resistors in the emitters of Q5 and Q6 can be used to improve the linearity but this degrades the noise performance of the mixer. Another problem with the mixer shown in FIG. 1 is the switching noise generated by the core transistors (e.g., Q1-Q4) as they switch between their "on" and "off' states. This switching noise compromises the spectral integrity of the mixer output. Referring to FIG. 3, an upper graph 26 shows a local oscillator (V LO ) signal fed into the differential pair shown in FIG. 2. A lower graph 27 shows noise bursts 28 created by the amplifier during transition periods when the V LO signal changes between high and low states. To reduce noise bursts 28, the mixer core transistors need to be turned on more quickly to supply more charge to their base terminals. However, more current is then required to remove the charge from the base of Q1, which makes this approach difficult to implement for high frequency applications. Accordingly, needs remain for a low noise mixer circuit with improved linearity. According to a first aspect of the present invention there is provided a mixer circuit, comprising: a mixer core including two inputs and an output for multiplying a first signal at the first input with a second signal at the second input, the mixer core having a linear transconductance within a given operating range and a nonlinear transconductance outside the given operating range; characterized in that said mixer further comprises: a post-mixer linearizer circuit having an input coupled to the output of the mixer core and an output, the post-mixer linearizer circuit including means for counteracting the nonlinear transconductance characteristics of the mixer core; wherein the means for counteracting the nonlinear transconductance characteristics of the mixer core has a substantially linear transconductance within the operating range of the mixer core and a non-linear response outside of said range which compensates for the non-linear response of the mixer core. According to a second aspect of the present invention there is provided a method for processing signals with a mixer, comprising: combining a first signal and second signal together with the mixer, the mixer having a linear response within a given operating range and a nonlinear response outside the given operating range; characterized in that said method further comprises: counteracting the nonlinear characteristics outside the mixer linear operating range in a post-mixer linearizer which has a linear response within said mixer linear operating range, and a non-linear response outside of said operating range which compensates for the non-linear response of the mixer. The foregoing and other objects, features and advantages of the invention will become more readily apparent from the following detailed description of a preferred embodiment of the invention which proceeds with reference to the accompanying drawings. FIG. 1 is a prior art mixer circuit. FIG. 2 is a graph showing the operating characteristics of a prior art mixer circuit. FIG. 3 is a sketch showing the switching noise created during transitions of the mixer of FIG. 1. FIG. 4 is a block diagram of a mixer circuit according to the invention. FIG. 5 is a detailed circuit diagram of an input driver for the mixer circuit shown in FIG. 4. FIG. 6 is a detailed circuit diagram of a mixer section for the mixer circuit shown in FIG. 4. FIG. 7 is a detailed circuit diagram of a post-mixer linearizer for the mixer circuit shown in FIG. 4. FIG. 8 is a graph showing the operating characteristics of the post-mixer linearizer shown in FIG. 7. FIG. 9 is a graph showing the increased linear operating range for the mixer circuit shown in FIG. 4. FIG. 10 is a circuit diagram of a prior art current mirror. FIG. 4 is a block diagram of a practicl variable gain mixer circuit 20 having increased linear response and increased noise suppression according to the invention. The mixer circuit 20 includes a local oscillator input driver 32, a mixer section 34, and a post-mixer linearizer 36, the latter two being connected in series. The input driver 32 improves the noise performance of the mixer 34. The mixer section 34 in addition to embodying transconductance stage, includes a linear-in-dB gain control circuit that varies the gain of the mixer exponentially in response to linear changes in a gain control current (I G ) applied to terminal 54. Finally, the post-mixer linearizer 36 compensates for the non-linear response of the mixer as described below. The LO input driver 32 receives a single-sided input signal LOIP at terminal 38 and produces a well-balanced differential output signal V LO , which is provided to the mixer section 34. The input threshold driver is balanced about a mid-point reference voltage VMID supplied at terminal 42. A bias current IBLO is received at terminal 40 for energizing the LO driver 32. The mixer section 34 receives a differential radio frequency (RF) input signal (RFLO and RFHI) at terminals 46 and 48. A reference current IPMX is supplied at terminal 52 and a gain control current MXGN, which sets the gain of the mixer, is supplied to terminal 54. The mixer section 34 generates a differential intermediate frequency V IF signal across terminals MH and ML, which is fed into the post-mixer linearizer 36. The post-mixer linearizer 36 receives an enable signal IBDR at terminal 56 and produces an intermediate frequency (IF) output signal MO at terminal 58. Supply voltages VP and CM provided to terminals 44 and 50, respectively, are fed into each block. In the preferred embodiment, the mixer circuit 20 is implemented in complementary bipolar technology. However, other technologies such as CMOS can be used with appropriate modification as will be apparent to those skilled in the art based on the following description. Input Driver Referring now to FIG. 5, a detailed circuit diagram of the input driver 32 is shown. To reduce noise created during switching transitions and to increase signal gain, LO input driver 32 is used to drive the mixer section 34. The mixer section is shown in detail in FIG. 6, described further below. The input driver 32 raises the voltage level of the single-sided input voltage LOIP at terminal 38 to a level required by the mixer section. The LO input signal LOIP is a single-sided voltage of typically ±50 millivolts (mV) (-16dBm) at 229 megahertz (MHz). The LO signal to the mixer core 34 (FIG. 6), on the other hand, is at about ±250 mV and in well-balanced differential form. The input driver 32 provides enough high-frequency gain so that the input driver 32 behaves like a limiter, generating an essentially square-wave drive signal to the mixer core 42. This results in maximum conversion efficiency and minimum noise. Resistor R200 is coupled between VMID and LOIP and provides an internal bias return path for the LOIP input signal. Resistor R207 and capacitor C201 are coupled in parallel to node 42. R207 co-balances the bias offset created by R200 and capacitor C201 shunts R207 at high frequencies. Transistors Q207 and Q208 are coupled together as a first differential pair and are typically biased to 100 micro amps (µA), which is proportional-to-absolute-temperature (PTAT) in the preferred embodiment. The biased first differential pair forms a first amplifier stage. The first amplifier stage includes load resistors R209-212 and a diode-connected transistor Q209 coupled in series therewith. The first amplifier stage is biased by a current mirror comprised of transistors Q201 and Q202. The first amplifier stage has an unloaded voltage gain of 9.75, which is lowered to 8.65 by the input resistance of a second differential pair Q210-211 at nominal NPN betas (β). The second amplifier stage is biased by current source transistor Q212 to about 100µA (PTAT) by two 2KΩ load resistors R213 and R214 coupled to the collectors of Q210 and Q211, respectively. The second amplifier stage supplies a loaded low frequency gain of approximately 30.3. The right-hand half of the input driver 32 comprises a first Class-AB emitter-follower (Q219/Q220) and a second Class-AB emitter-follower (Q221/Q222). Transistors Q219 and Q220 comprise a first complementary transistor pair (first output stage) coupled between the collector of Q210 and terminal 60. Transistors Q221 and Q222 comprise a second complementary transistor pair (second output stage) coupled between the collector of Q211 and terminal 62. Two bias stages are interposed between the amplifier stages and the two output stages. The first bias stage includes emitter follower circuit Q213/Q214, which controls the first output stage and the second bias stages includes emitter follower circuit Q216/Q217, which controls the second output stage. The output stages are biased to moderate currents, but the transistors Q219-222 carry high peak currents of about 400µA at a typical LO frequency of 229MHz due to the base-current loading of the mixer's core (FIG. 6). The loaded low frequency voltage gain from terminal 38 to the output terminals 60 and 62 is approximately 29.3. The LO input driver 32 is energized by a 50µA (PTAT) input current IBLO at terminal 40. Current IBLO drives conventional current mirror transistor Q224, whose current is mirrored by Q203, Q212, Q215, and Q218. The current mirror transistor Q224 is aided by an emitter-follower Q223, which operates at 79µA that establishes an r e in Q223 of approximately 330Ω thus providing decoupling on the common bias node at the emitter of Q223. Capacitor C202 ensures that the beta-loop around Q223 and Q224 is stable, and also maintains a low impedance at high frequency. In operation, the output stages Q219/Q220 and Q221/Q222 and associated bias stages supply and draw charge quickly to and from the core transistors in the mixer section 34. For example, when the base of transistor Q221 goes positive, Q216 couples this voltage. The current through diode Q217 to the base of transistor Q222 and a charge is supplied to terminal 62. However, when the base of Q221 goes negative, Q216 couples this negative voltage step to Q222, turning it on. Transistor Q222 then quickly pulls the output terminal 62 negative and the charge at the input terminal of the mixer core is removed. Thus, the input driver 32 provides a large charge for quick turn on and off of the mixer core. In this way, noise created during mixer core on-off transitions is reduced. Mixer Section FIG. 6 is a detailed circuit diagram of the mixer section 34 previously shown in FIG. 4. The mixer section includes a mixer core comprised of transistors Q237-Q240 arranged as a conventional doubly-balanced switching modulator, as shown in FIG. 1. Instead of the prior art RF input stage, the mixer section 34 includes a so-called "multi-tanh doublet," which operates as a conventional transconductance (g m ) stage but which exhibits improved linearity. The use of the doublet, however, is not essential to the operation of the invention. Nor are the particular emitter area ratios described here necessary. Accordingly, for purposes of the following discussion the multi-tanh doublet can be considered a g m stage, having improved but not perfect linearity. Typically, an RF input signal is applied in single-sided form (RFHI, RFLO) to one of the input terminals 46 or 48, usually by a blocking capacitor (not shown). DC bias paths for the RFLO and RFHI inputs are provided by R233 and R234, whose common node is biased by Q230 and Q231. This arrangement ensures that all parts of the mixer core operate correctly at the minimum supply of 2.7V and temperature of -25 degrees Centigrade. The input impedance seen from RFHI to RFLO varies slightly with the gain-control voltage MXGN at terminal 54. This is due to the variation in bias current in Q245 and Q246 and thus, in the "multi-tanh doublet" formed by differential pairs Q241/244 and Q242/243. For nominal parameters and operating conditions, the resistive part of the impedance varies almost linearly from 2.7kΩ at I G =0 (maximum gain, hence maximum bias current) to 5.5kΩ at I G =75µA. The effective input capacitance of the mixer itself, excluding pad and pin parasitics, varies from 1.5 pF at V G =0 to 1.15 pF at I G =75µA. Adding a further 1.25 pF for parasitic capacitances, the total input capacitance will vary from between 2.4pF and 2.75pF. The input impedance Z IN at 240MHz varies essentially linearly from 238Ω at the practical maximum gain to 272Ω at the practical minimum gain. HF loading at each side of the differential output at nodes MH and ML is provided by the capacitors C253 and C254. The post-mixer linearizer 36 (FIG. 4) has a moderately high impedance. Thus, the capacitors C253 and C254 form a low-pass corner with a 3dB frequency close to 100MHz. The low-pass corner attenuates the sum frequency component of the output signal, typically of 240MHZ+229.3MHz = 469.3MHz, while the intermediate frequency (IF) present between terminals 74 and 76 is passed with little attenuation. Mixer Gain Control Circuit The mixer section 34 also includes a gain control circuit 70, which controls the gain of the mixer. The gain control circuit provides "linear-in-decibel" gain control since a linear increase in a gain control current produces a corresponding exponential increase in the gain of the mixer, hence "linear-in-decibel." This is accomplished by varying a bias current supplied to the mixer core 72 Before considering how this is accomplished, the "basic" biasing for the RF input stage in mixer core 72 is discussed first. A mixer bias current IPMX of approximately 109µA is applied at terminal 52 and flows in Q235 with the aid of emitter-follower Q236. Transistor Q236 is biased to about 180µA, when I G =0, which flows through R232. For a gain-control current I G applied to terminal 54 equal to zero and for very large beta values, transistors Q245 & Q246 operate at a multiple of the input current at node IPMX. The input current ratio is defined by the emitter-area ratios between Q245,Q246 and Q235, which in the preferred embodiment is 7. Thus, the nominal collector current of Q245 and Q246 is 7*109µA or approximately 763µA. There is some small current at the base of Q235 (about 2µA) even when the I G is zero. Thus, the peak current at Q245 and Q246 is higher due to the voltage drop across R231. For finite NPN betas, the current in Q245 and Q246 is raised by the voltage drop across both R231 and R230. For the general case where I G is non-zero at terminal 54, the current I G causes a reduction of ΔV BE =I G *R231 between the V BE of Q235 and that of Q245, Q246. The currents of transistors Q245 and Q246 are, therefore, reduced by the ratio exp (ΔV BE /V T ), where V T is the thermal voltage kT/q. Thus, a linear increase in I G causes an exponential reduction in the transconductance g m at the input stage of the mixer core 72, i.e., a logarithmic gain reduction is produced. The scaling is chosen such that a 1µA (PTAT) change in I G causes ?V BE of 1mV (PTAT) and consequently a change of exp(1/26), or about 0.333dB in the mixer's gain. Thus, the 75µA (PTAT) full-scale change in I G (2µA to 77µA) results in a gain change of 75*0.333dB, or 25dB. It will be apparent to those skilled in the art that the gain control circuit can be made responsive to a voltage rather than a current with the addition of an appropriate current-to-voltage converter (not shown). The 75µA (PTAT) current variation at node MXGN is absorbed by Q236. The variation in the emitter current of Q236 is actually slightly less because the V BE of Q245 and Q246, and hence the current in R232, reduces with I G . A nominal beta of 110 results in a base-current variation of about 0.7µA in Q236. The variation in the base current in Q236 varies the primary current supplied to the collector of Q235 causing a small gain nonlinearity. The change in primary current to Q235 is especially problematic for very low betas. For example, at one-third the nominal beta a base current change of 2µA would represent a roughly 2%, or 0.17dB, nonlinearity. Transistors Q232-Q234 corrects for variations in the collector current in Q235. Transistor Q234 has a base current closely replicating that of Q236. Current mirror Q232,Q233 is coupled between the base of Q234 and the input terminal 52 and offsets changes in the base current in Q236. Thus, the overall change in primary current in the collector current of Q235 over the full range of I G and betas (β) is very small. A large capacitor (not shown) is coupled to terminal 55 to hold the impedance at the bases of the current-source transistors Q245/246 to as low a value as possible minimizing HF modulation noise. Capacitor C251 is coupled across Q235 to ensure that the 'beta-loop' around Q235/236 is stable. Capacitor C251 also serves to maintain a low HF impedance at terminal 52. Application of the linear-in-dB gain control circuit is not limited to mixer applications but can be used in any amplifier that employs a transconductance stage whose gain is linear to the bias current supplied thereto. Post-Mixer Linearizer FIG. 7 is a detailed circuit diagram of the post-mixer linearizer 36 shown in FIG. 4. The purpose of the post-mixer linearizer, as the name implies, is to correct or compensate for the non-linear response of the RF input section of the mixer. This would be particularly important where the RF input section is a single transconductance stage instead of the multi-tanh doublet as shown and described above. Even with the multi-tanh doublet, however, some non-linearity remains. The post-mixer linearizer compensates for this remaining non-linearity. The IF output signals MH and ML at terminals 74 and 76 from the mixer section 72 (FIG. 6) are at a fairly low level, at a moderately high impedance, differential in form and close to the positive supply voltage. The post-mixer linearizer 36 also provides a large amount of post-mixer gain to drive a doubly-terminated 330Ω filter (not shown). The output at terminal 58 is a current; with the additional of a load impedance, the post-mixer linearizer 36 centers the IF output (V OUT ) to the mid-point of the supply voltage and provides further pre-filtering of frequency sum components at the mixer core output. Simple resistive loads R235 and R236 are coupled at the mixer core output at terminals 74 and 76 allowing introduction of a low-pass pole of known and fixed frequency. Using the largest possible values for, load resistors R235 and R236 result in low noise by providing the maximum possible voltage gain in the first stage of a high gain amplifier system. In one embodiment, R235 and R236 are each approximately 458.5 ohms. Resistive loads R235 and R238 alone would result in a proportional to absolute temperature (PTAT) voltage swing of 328 mVP, which would be acceptable if the loads could be taken directly to the reference voltage VP. However, the DC voltage level of the IF signal at the input of the post-mixer linearizer 36 must be about a V BE below the bias voltage VP, to satisfy certain bias constraints in the mixer core 32. If a 328mV variation is superimposed on a V BE drop, the collectors in the mixer core fall by a maximum of about 1V below VP. The transistors in the mixer core 72 would then saturate. The saturation problem is avoided by using a common-mode bias circuit which overcomes the disadvantages of other active loading schemes. The MH and ML inputs of the post-mixer linearizer are coupled to emitter followers Q256/Q258 and Q257/Q259. The emitter followers are biased to 65µA (PTAT) by Q251 and Q252. The voltages at the emitters of diodes Q258 and Q259 are sensed by the PNP emitter followers Q254 and Q255, and averaged in R230 and R239, in conjunction with C257. The resulting common mode voltage is applied to the base of Q249 which servos the voltage at the bottom of load resistors R235 and R236 at terminals 74 and 76. Thus, the voltages MH and ML vary only slightly with the mixer core bias currents. The voltage variation is still 240mV over the full gain and temperature range. This is approximately 100mV less variation and, and more importantly, the PTAT variation in the bias voltage in the mixer core 72 is eliminated and "replaced" by complementary to absolute temperature variations (CTAT). Overall, the improvement over temperature compared to simple resistive loading is significant. Transconductance Correction A main feature of the post-mixer linearizer 36 is that it is really a g m stage that provides a current output with near rail-to-rail voltage compliance. In the preferred embodiment, this g m is nominally 16.3 mS. Thus, when used with a 165Ω load, the voltage gain from the differential port (MH, ML) to the final mixer output (V OUT ) at terminal 58 is close to 2.7 times or 8.6dB. Transistors Q266 and Q267 are biased into conduction by the combined V BE 's of Q256 and Q258, while Q262 and Q263 are biased into conduction by the combined V BE 's of Q257 and Q259. When the voltage across MH and ML (V IF ) is zero, the voltage at the base of Q256 and Q257 are the same. The emitters for both Q256 and Q257 are also at the same voltage potential. Thus, the current down the R240 branch and the R241 branch are both equal and approximately 73.2 µA (PTAT). This current is larger than the bias currents in the emitter-follower branches Q256 and Q257 because of the emitter areas in Q263 and Q267 are a multiple of those in Q256 and Q257 (e.g., 2:1). However, the current is not doubled because of the inclusion of the emitter resistors R240 and R241. A cross-over connection between the emitter followers Q256 and Q257 and the R240 and R241 output branches provide an output response that counteracts nonlinear characteristics of the g m in the mixer core 42. The differential voltage between MH and ML is transferred via the emitter-followers Q256 through Q259 to the bases of Q266 and Q267 in the R241 branch and the bases of Q262 and Q263 in the R240 branch, respectively. If MH goes high relative to ML, the current in the R241 branch increases while current in the R240 branch decreases. The opposite occurs when MH goes low relative to ML. Thus, the fully-differential output of the mixer core 72 is converted to two separate currents. The separate currents each have a local transconductance g m controlled by the bias currents which are directly traceable to physically large 1kΩ resistors in a PTAT bias generator (not shown). The g m is also controlled by the values of R240 and R241 (∼152.8 Ω), which are made physically large to ensure good control. The emitter resistance r e of the output branches (i.e., R240 branch and R241 branch) at 73.2µA (PTAT) are each 353Ω. Thus, the net g m in each output branch is 1/(353.1Ω + 152.8Ω + 353.1Ω), or 1.164mS. The R241 branch drives PNP current-mirror 80 and the R240 branch drives NPN current-mirror 82. The PNP current mirror comprises essentially Q265 and Q269, and is aided by complementary emitter followers Q268 and Q270. The NPN current mirror 82 comprises essentially Q264 and Q273 and is aided by Q271 and Q272. The current mirrors each provide a current gain of 7 by virtue of the emitter area ratios (i.e., 14:2). Each current mirror is biased into Class-AB and, therefore, both mirrors contribute to the output at moderate signal amplitudes. Thus, the effective current gain is 14. This raises the overall g m from the IF input (V IF ) at 74, 76 to the output (V OUT ) at 58 to 14*1.164mS=16.3mS. FIG. 10 is a circuit diagram of a prior art current mirror 88. A single emitter-follower Q133 is coupled to the base of Q122 to provide additional gain which would not be available with smaller values of beta. While Q133 increases gain it also increases the voltage drop across the current mirror input. Specifically, Q133 creates a voltage drop of two V BE above the supply or ground. This two-V BE voltage drop makes the application of this prior art current mirror undesirable for low voltage environments. For low voltage applications, it is desirable to design a current mirror having as little a voltage drop as possible while also having the benefit of the extra gain provided by Q33. The current mirrors 80 and 82 satisfy these two objectives. Referring again to current mirror 82 in FIG. 7, a PNP transistor Q271 is included to bring the offset voltage down to one V BE . An additional drive current I EF is generated by an auxiliary current mirror formed by transistors Q260 and Q261. This supply current drives Q271 and Q272 and provides extra current gain to the current mirror 82. R243 provides an additional voltage drop of (I EF *R243), which causes the base-to-emitter voltage of Q264 to drop below V BE . The input voltage of current mirror 82 is then equal to V BE -(I EF * R243). A capacitor C256 is coupled between the bases of Q271 and Q272 and operates as a diode at high frequencies thereby eliminating phase error. R243 also sets a predictable time constant for capacitor C256. A similar but complementary design is used in current mirror 80. A current supply transistor Q253 provides the additional drive current to current mirror 80, as did Q261 in current mirror 82. Thus, the current mirrors 80 and 82 provide high current gain in the sense that a large area ratio is established between, for example, Q264 and Q273 without high sensitivity to beta tolerances. Second, the current mirror has a very low input voltage of approximately 100 millivolts. Thus, the incorporation of Q271 in combination with R243 in current mirror 82 and Q268 in current mirror 80 increase the available headroom for the current mirrors while maintaining high open-loop current gain. The transconductance of the post-mixer linearizer 36 is deliberately rendered nonlinear to compensate for nonlinearity in the g m of the mixer core. For example, assume that the RF input g m is simply that of a bipolar differential pair, having a hyperbolic tangent transfer curve. This results in a compressive nonlinearity as previously shown in FIG. 2. The incremental g m is progressively reduced as the instantaneous value of the input signal at the RF port increases. The g m of the post-mixer linearizer 36 is designed to "increase" as the differential voltage between V IF increases, resulting in an expanding nonlinearity. Resistors R240 and R241 scale the nonlinear effects in the post-mixer linearizer to optimize the nonlinear compensation. Without R240 and R241, the compensation would be too severe. The g m compensation of the post-mixer linearizer 36 operates in the following manner. When the base of Q256 goes positive, due to a relative increase in the IF signal at 74, Q266 turns on. The base of PNP transistor Q267, however, is coupled to diode Q259 and, therefore, goes negative. Thus, the current in the collector of Q266 goes up, and the current in the collector of Q263 goes down. Alternately, if the differential voltage V IF is higher at node ML relative to MH, the current in Q267 goes down and the current in Q263 goes up. Thus, the collector current in Q263 increases and the collector current in Q266 decreases. When combined, the signals from the R240 and R241 branches generate two different halves of the output signal V OUT at 58. The operating response of the post-mixer linearizer 36 is shown in FIG. 8. It can be seen that the post-mixer linearizer has a substantially linear g m but begins to progressively increase at larger values of V IF . Thus, the gm response of the mixer core 72 and the post-mixer linearizer 36 actually work with each other to achieve a wider liner operating range. FIG. 9 is a graph showing the increased overall linear g m of the mixer circuit shown in FIG. 4. This wider linear response prevents the mixer core from producing cross-modulation products prior to filtering. Having described and illustrated the principles of the invention in a preferred embodiment thereof, it should be apparent that the invention can be modified in arrangement and detail without departing from such principles. I claim all modifications and variation coming within the scope of the following claims.

Claims: A mixer circuit, comprising: a mixer core (72) including two inputs and an output for multiplying a first signal at the first input with a second signal at the second input, the mixer core having a linear transconductance within a given operating range and a nonlinear transconductance outside the given operating range; characterized in that said mixer further comprises: a post-mixer linearizer circuit (36) having an input coupled to the output of the mixer core and an output (58), the post-mixer linearizer circuit including means for counteracting the nonlinear transconductance characteristics of the mixer core; wherein the means for counteracting the nonlinear transconductance characteristics of the mixer core has a substantially linear transconductance within the operating range of the mixer core and a non-linear response outside of said range which compensates for the non-linear response of the mixer core. A mixer circuit according to claim 1 wherein the mixer core (72) includes a differential pair of transistors forming a first and second output node. A mixer circuit according to claim 2 wherein the post-mixer linearizer circuit (36) includes a first output branch coupled to the first output node and a second output branch coupled to the second output node. A mixer circuit according to claim 3 wherein the first output branch comprises an NPN transistor coupled at a base terminal to the first output node of the mixer core and a PNP transistor coupled in series to the NPN transistor and further operably coupled at a base terminal to the second output node of the mixer core (72). A mixer circuit according to claim 4 wherein the second output branch comprises an NPN transistor coupled at a base terminal to the second output node of the mixer core and a PNP transistor coupled in series to the NPN transistor and further operably coupled at a base terminal to the first output node of the mixer core (72). A mixer circuit according to claim 3 wherein the post-mixer linearizer (36) further includes a first and second control branch each cross-coupled to both the first and second output branches. A mixer circuit according to claim 6 wherein the first and second control branches each comprise an emitter follower circuit. A mixer circuit according to claim 3 wherein the post-mixer linearizer circuit (36) includes a first current mirror (80) coupled to the first output branch and a second current mirror (82) coupled to the second output branch. A mixer circuit according to claim 8 wherein both the first (80) and second (82) current mirrors each include an input transistor coupled to the associated output branch, an output transistor coupled between the input transistor and the output of the post-mixer linearizer, a drive transistor coupled to the output transistor for supplying drive current, and a offset transistor coupled between the drive transistor and the input transistor for reducing voltage offset in the current mirror. A mixer circuit according to claim 9 including a resistor and capacitor circuit coupled between the drive transistor and the offset transistor for further reducing the voltage offset in the current mirror. A mixer circuit according to claim 1 including an input driver (32) coupled to the input of the mixer core (72) for reducing noise generated by the mixer when switching between an on arid off state. A mixer circuit according to claim 1 including a gain control circuit (70) having an input for receiving a gain control signal and an output coupled to the mixer core (72), the gain control circuit varying a given mixer core gain value linearly in decibel according to linear changes in the gain control signal. A method for processing signals with a mixer, comprising: combining a first signal and second signal together with the mixer, the mixer having a linear response within a given operating range and a nonlinear response outside the given operating range; characterized in that said method further comprises: counteracting the nonlinear characteristics outside the mixer linear operating range in a post-mixer linearizer (36) which has a linear response within said mixer linear operating range and a non-linear response outside of said operating range which compensates for the non-linear response of the mixer. A method according to claims 13 including varying a given gain value in the mixer linearly in decibel according to linear changes in a gain control signal. A method according to claim 13 including forcing a charge into the mixer thereby switching the mixer from a first to a second state and correspondingly discharging the mixer thereby switching the mixer back to the first state. A method according to claim 13 wherein the mixer generates an intermediate output signal and including the steps of generating a first and second intermediate signal that combine to form a mixer output signal, the first and second intermediate signals having transconductance characteristics that are complementary with the nonlinear response of the mixer. A method according to claim 16 including the following steps: coupling a current mirror (80, 82) to the first and second intermediate output signals for generating a single combined output current, each current mirror having a given offset voltage and current gain, and increasing the current gain for each current mirror while at the same time reducing the given offset voltage.

Inventors: GILBERT BARRIE, GILBERT, BARRIE
Applicants: ANALOG DEVICES INC, ANALOG DEVICES, INCORPORATED
Application year: 1996
Main classification: H03G3
IPC codes: H03D7, H03G1