Bipolar transistor and method of manufacturing the same

Abstract: A semiconductor device having an epitaxial layer (3) of one conductivity type formed on a semiconductor substrate (1) of the other conductivity type, a base region of the other conductivity type formed on the epitaxial layer to extend from a surface of the epitaxial layer to a predetermined depth, the base region including an intrinsic base region (8) and an external base region (7), an emitter region (12) of the one conductivity type formed in the intrinsic base region (8), and a pedestal collector region of the one conductivity type formed in a portion of the epitaxial layer which is immediately under the base region to correspond thereto, wherein the pedestal collector region comprises a plurality of layers of pedestal collector regions (102,103,104) which have an impurity concentration that changes in a direction of depth of the substrate and which are sequentially arranged in the direction of depth of the substrate.

Description: BACKGROUND OF THE INVENTION 1. FIELD OF THE INVENTION The present invention relates to a semiconductor device and, more particularly, to a semiconductor device which includes a bipolar transistor, is capable of suppressing the Kirk effect and is also capable of a high-speed operation, and a method of manufacturing the same. 2. DESCRIPTION OF THE PRIOR ART In order to obtain a high-speed switching performance in a bipolar transistor, the maximum oscillating frequency (to be abbreviated as fmax hereinafter) as one of performance indices must be increased. This fmax is given by the following equation: fmax = (fT/8π·Rb·C BC ) 1/2 where fT is the cut-off frequency, Rb is the base resistance, and C BC is the base-collector capacitance. It is apparent from the above equation that, in order to increase fmax, the cut-off frequency fT must be increased, the base-collector capacitance C BC must be decreased, and the base resistance Rb must be decreased. In recent years, in order to improve fmax to thereby improve the performance of the bipolar transistor, it has become more and more important to further increase the cut-off frequency and to decrease the base-collector junction capacitance or at least to minimize any increases in this capacitance. Conventionally, in order to increase the cut-off frequency fT, scaling in the vertical direction, in particular in the direction of thickness of the base layer, has been performed. In order to decrease the base-collector capacitance and the base resistance, scaling in the planar direction has been performed by using a self alignment type bipolar transistor structure as shown in Fig. 1. Referring to Fig. 1, for example, reference numeral 111 denotes a p-type silicon substrate; 112, an n-type buried collector layer; 113, an n-type epitaxial layer; 114, 119, and 120, insulating films, e.g., silicon oxide films; 116, a base contact polycrystalline silicon layer; 117, a p-type external base diffusion layer; 118, a p-type intrinsic base; 115, a collector contact diffusion layer; 121, an emitter polycrystalline silicon layer; and 122, an n-type emitter diffusion layer, respectively. As is generally known well, during a high-current injection operation the effective base width of a bipolar transistor increases in accordance with an increase in injection current. This is the so-called Kirk effect which is a major factor that degrades the high-speed operating performance. It is, therefore, important to decrease this Kirk effect. Conventionally, many methods of forming a pedestal collector region have been proposed in order to suppress the Kirk effect. For example, as shown in Fig. 2A, an n-type impurity is ion-implanted at a high concentration through an emitter-base forming opening portion 200 formed between a base contact electrode 216 and an insulating film 219, thus forming a pedestal collector region 201. However, with this technique for suppressing the Kirk effect by forming a region doped with an impurity at a relatively high concentration immediately under the base-collector junction, since the base-collector junction capacitance increases, the transistor operation speed in the low-current injection decreases inversely. Also, the resistance of a region extending from the internal base to the external base, i.e., a so-called link base region, increases. These problems largely degrade the high-frequency characteristics of the transistor, as described above. In order to solve these problems, as shown in Fig. 2B, there has been proposed a technique for forming a side wall 220 made of an insulating film on the side wall of an opening portion 200, and ion-implanting an n-type impurity at a high concentration through the opening portion 200, so that an n-type pedestal collector region 201 is selectively formed under an intrinsic base 218 immediately beneath the emitter region. As shown in Fig. 2C, Japanese Unexamined Patent Publication No. 5-259175 proposes a technique for forming a conductive layer 221 forming part of the emitter electrode in the emitter forming opening portion, and ion-implanting an n-type impurity at a high concentration to form a pedestal collector region 201. In this technique, the area of the pedestal collector region can be further decreased by self alignment, so that the base-collector parasitic capacitance can be decreased. However, in each of the semiconductor devices shown in Figs. 2B and 2C, although the base-collector parasitic capacitance can be decreased, the Kirk effect cannot be suppressed completely. This is due to the following reason. When the collector current increases, this collector current causes a so-called emitter clouding phenomenon (refer to reference symbol E in Fig. 2D) and mainly flows around the emitter diffusion layer. This emitter clouding phenomenon is described in, e.g., OHTA Kuni-ichi, "Introduction to VLSI", Ohm Sha, pp. 30 to 31. If the pedestal collector region is formed immediately under an emitter diffusion layer 222 or on only a region narrower than the emitter diffusion layer 222, as described above, the Kirk effect occurs at the end portion of the emitter diffusion layer 222, as shown in Fig. 2D. Then, when a high-current injection operation is started, the cut-off frequency immediately decreases despite the presence of the pedestal collector region 201. IBM Technical Disclosure Bulletin, Vol. 26 No. 2, July 1983, page 492 discloses a deep and large collector region having a dopant concentration of about 10 16 cm -3 and superficial collector region located below the intrinsic base region having a dopant concentration of about 10 17 cm -3 whereby the Kirk effect is supressed and the base-collector capacitance is reduced. However, also for this semiconductor device the above mentioned problems still exist. It is therefore an object of the invention to provide a semiconductor device which includes a bipolar transistor, and is capable of greatly improving the operation speed in a low-current injection region to a high-current injection while supressing the Kirk effect, thus, realizing a decrease in base resistance and base-collector junction capacitance, and a method of manufacturing the same. This object is solved by claims 1 and 5. Advantageous features are mentioned in the subclaims. According to the present invention having the respective aspects described above, the pedestal collector region formed immediately underneath the base region of the bipolar transistor is constituted by a plurality of layers of pedestal collector regions which have an impurity concentration that changes in a direction of depth of the substrate and which are sequentially arranged in the direction of depth of the substrate. Consequently, suppression of an increase in base resistance and base-collector junction capacitance can be realized simultaneously while suppressing the Kirk effect, so that the operation speed of the bipolar transistor can be greatly improved in the low-current injection region to the high-current injection region. The above and many other advantages, features and additional objects of the present invention will become manifest to those versed in the art upon making reference to the following detailed description and accompanying drawings in which preferred embodiments incorporating the principles of the present invention are shown by way of illustrative example. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a longitudinal sectional view showing a conventional semiconductor device having a self alignment type bipolar transistor structure; Figs. 2A to 2C are longitudinal sectional views respectively showing different conventional semiconductor devices in each of which a pedestal collector region is formed in an epitaxial layer; Fig. 2D is a view for explaining the drawbacks of the semiconductor devices shown in Figs. 2B and 2C; Fig. 3 is a longitudinal sectional view showing the first embodiment of the present invention; Figs. 4A to 4C are graphs showing the impurity concentration distribution in a pedestal collector region respectively taken along lines A - A, B - B, and C - C in Fig. 3; Figs. 5A to 5D are longitudinal sectional views showing a manufacturing method according to the first embodiment in the order of steps; Fig. 6 is a graph showing the effect of suppressing the Kirk effect in the first embodiment in comparison with that in the conventional example; Fig. 7 is a longitudinal sectional view showing a modification of the first embodiment; Fig. 8 is a longitudinal sectional view showing the second embodiment of the present invention; Figs. 9A to 9F are longitudinal sectional views showing a manufacturing method according to the second embodiment in the order of steps; Figs. 10A and 10B are graphs showing the impurity concentration distribution of a pedestal collector region respectively taken along lines XA - XA and XB - XB in Fig. 8; Figs. 11A and 11B are graphs showing the impurity concentration distribution of a conventional example employed as a comparative example; and Fig. 12 is a longitudinal sectional view showing a modification of the second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Several preferred embodiments of the present invention will be described with reference to the accompanying drawings. Fig. 3 is a sectional view showing the first embodiment of the present invention. Referring to Fig. 3, an n-type buried layer 2 and an n-type epitaxial layer 3 are sequentially formed on a p-type semiconductor substrate 1. An isolation oxide film 4 is selectively formed on the surface portion of the n-type epitaxial layer 3. An n-type collector contact diffusion layer 5 is formed in a predetermined region of the n-type epitaxial layer 3 to reach the n-type buried layer 2. An p-type intrinsic base region 8 is formed on a predetermined portion of the n-type epitaxial layer 3, and an emitter region 12 is formed in the p-type intrinsic base region 8. A p-type external base region 7 is formed on the surface portion of the n-type epitaxial layer 3 on the two sides of the p-type intrinsic base region 8. A base contact electrode 6 of p-type polycrystalline silicon for connection with the p-type intrinsic base region 8 is formed on the p-type external base region 7. An insulating interlayer film 9 consisting of a nitride film and a side wall insulating film 10 are formed to cover the base contact electrode 6, and an emitter electrode 11 for connection with an emitter region 12 is formed on the side wall insulating film 10. First, second, and third n-type pedestal collector regions 102, 103, and 104 are sequentially formed in the n-type epitaxial layer 3 immediately below the emitter region 12 such that their impurity concentration changes and their regions increase from the surface of the n-type epitaxial layer 3 toward the inner portion of the substrate. Figs. 4A to 4C show the impurity concentration distribution of the pedestal collector regions 102, 103, and 104 in the direction of depth, in which Fig. 4A shows the impurity concentration distribution of a portion taken along the line A - A of Fig. 3, Fig. 4B shows the impurity concentration distribution of a portion taken along the line B - B of Fig. 3, and Fig. 4C shows the impurity concentration distribution of a portion taken along the line C - C of Fig. 3. In this manner, the impurity concentration changes in the pedestal collector regions 102, 103, and 104 in the direction of depth and among the respective pedestal collector regions. In Figs. 4A to 4C, the impurity concentration in the ordinate is shown by logarithm. A manufacturing method according to the first embodiment of the present invention described above will be described with reference to Figs. 5A to 5D. As shown in Fig. 5A, an n-type buried layer 2 and an n-type epitaxial layer 3 are sequentially formed on the entire surface of a p-type semiconductor substrate 1. Subsequently, an isolation oxide film 4 having a thickness of 300 nm to 600 nm is selectively formed on the resultant structure in accordance with the ordinary method. By employing ion implantation, a collector contact diffusion layer 5 is formed to reach the n-type buried layer 2. Phosphorus is ion-implanted at a depth of about 0.5 to 0.6 µm (a projected range Rp of ion implantation) in a transistor formation region with an energy of 500 to 600 keV. and at 1 x 10 12 to 1 x 10 13 cm -2 , so that a first pedestal collector region 104 is selectively formed. Subsequently, as shown in Fig. 5B, an oxide film 13 on the active base region is removed in accordance with known photoetching, and a p-type polycrystalline silicon film 6 containing boron and having a thickness of 100 nm to 300 nm is formed. Boron is doped in the polycrystalline silicon film 6 in accordance with, e.g., ion implantation with an energy of 5 to 10 keV and at 5 x 10 15 to 1 x 10 16 cm -2 . Boron may be doped while forming the polycrystalline silicon layer. A nitride film 9 is formed to have a thickness of 100 nm to 200 nm in accordance with the known LPCVD method. The resultant structure is patterned to a predetermined shape to form a base contact electrode 6 and an emitter opening portion 100. Boron is ion-implanted in a region corresponding to the active base region with an energy of 10 keV and at 3 x 10 13 cm -2 to form a p-type intrinsic base region 8. Subsequently, phosphorus is ion-implanted with an energy of 300 to 400 keV and at 1 x 10 12 to 1 x 10 13 cm -2 through the emitter opening portion 100, thus forming a second pedestal collector region 103 having a thickness of about 0.4 to 0.5 µm (a projected range Rp of ion implantation) in the transistor formation region. As shown in Fig. 5C, a side wall insulating film 10 having a thickness of 100 nm to 300 nm is formed on the side surface of the base contact electrode 6. This formation is performed in accordance with, e.g., a known etching-back technique after a nitride film is formed. Phosphorus is ion-implanted with an energy of 200 to 250 keV and at 1 x 10 12 to 1 x 10 13 cm -2 through an emitter opening portion 100a, so that a third pedestal collector region 102 is formed at a depth of about 0.25 to 0.35 µm (a projected range Rp of ion implantation) in the transistor formation region. As shown in Fig. 5D, a polycrystalline silicon layer containing an n-type impurity, e.g., arsenic, and having a thickness of 200 nm to 300 nm is formed, and the resultant structure is selectively etched to form an emitter contact electrode 11. The resultant structure is annealed in a nitrogen atmosphere of 900 to 950°C for 10 minutes, so that arsenic contained in the emitter contact electrode 11 diffuses into the p-type intrinsic base region 8, thus forming an n-type emitter region 12. At this time, boron contained in the p-type polycrystalline silicon film 6 diffuses into the epitaxial layer 3 simultaneously to form a p-type external base region 7. Thereafter, although not shown, an insulating interlayer film, an electrode, and the like are formed in accordance with an ordinary method, thus completing a bipolar transistor. In the bipolar transistor shown in Fig. 3 which is manufactured in this manner, the impurity concentrations and areas of the first, second, and third pedestal collector regions 102, 103, and 104 immediately under the emitter region 12 increase toward the inner portion of the substrate (as the depth is increased). Therefore, as shown in Fig. 6, the Kirk effect can be suppressed than in the conventional case without increasing the base-collector parasitic capacitance, and the cut-off frequency is not degraded even in a high-current injection region. Fig. 7 is a longitudinal sectional view showing a modification of the first embodiment. In this modification, when selectively forming a first pedestal collector region 104a, a phosphorus ion implantation region is formed to be connected to a collector contact diffusion layer 5. At this time, a portion of the first pedestal collector region 104a where phosphorus ions are doped through an isolation oxide film 4 becomes shallower than the remaining portion. When the first pedestal collector region 104a is connected to the collector contact diffusion layer 5, the collector resistance can be decreased than in the first embodiment. The second embodiment of the present invention will be described. Fig. 8 is a sectional view of the second embodiment. The second embodiment is different from the first embodiment in the following respects. The surface of a substrate 1 is exposed and the implantation angle is set to 0°, to cause a channeling phenomenon. A p-type low-concentration region 25 is formed immediately under an external base region 17 and an intrinsic base region 18 more deeply with less concentration gradient than with ordinary 7° ion implantation, to be in contact with an external base region 17 and an intrinsic base region 18. With this technique, the base-collector junction capacitance can be decreased, and an increase in base resistance of the base region can be prevented. A manufacturing method according to the second embodiment will be described. As shown in Fig. 9A, an isolation oxide film 14 having a thickness of 300 nm to 600 nm is selectively formed on a p-type semiconductor substrate 11 in accordance with the ordinary method. Subsequently, phosphorus is selectively ion-implanted with an energy of 1 to 1.5 MeV and at 1 x 10 13 to 1 x 10 14 cm -2 by using a photoresist (not shown) as a mask, so that an N-well 24 serving as a collector layer is formed at a depth of about 1 to 2 µm (a projected range Rp of ion implantation) in a region at least including a transistor formation region. At this time, a portion of the N-well 24 where the phosphorus ions are doped through the isolation oxide film 14 having a thickness of 300 to 600 nm becomes shallower than the remaining portion. Reference numeral 23 denotes an oxide film corresponding to the transistor formation region. As shown in Fig. 9B, an n-type impurity, e.g., phosphorus, is doped into the substrate 11 in accordance with ion implantation, and the resultant structure is annealed in an inert gas, thus forming an n-type collector contact diffusion layer 15. Phosphorus is selectively ion-implanted with an energy of 500 to 600 keV and at 1 x 10 12 to 1 x 10 13 cm -2 by using a photoresist (not shown) as a mask, so that a first pedestal collector region 204 is formed at a depth of about 0.5 to 0.6 µm (projected range Rp of ion implantation) in the transistor formation region. The second embodiment is different from the first embodiment in that the phosphorus implantation region is formed widely to extend to a portion below the isolation oxide film 14, as shown in Fig. 9B. With this structure, a sufficiently high dielectric breakdown voltage (the punch-through breakdown voltage between the external base region 17 formed in the subsequent step and the substrate 11) can be obtained. As shown in Fig. 9C, boron is ion-implanted in the transistor formation region with an energy of 10 to 50 keV and at 5 x 10 11 to 1 x 10 13 cm -2 to form a p-type low-concentration region 25. In this ion implantation, it is preferable that the oxide film on the transistor formation region 23 be removed in accordance with known photoetching, and thereafter boron be ion-implanted with an energy of 10 to 50 keV and at 5 x 10 11 to 1 x 10 13 cm -2 with an ion implanting angle of 0° (to be perpendicular to the substrate surface), not 7° which is an ordinary angle. This is because of the following reason. Since the surface of the silicon (100) substrate 11 is exposed and the implantation angle is set to 0°, a channeling phenomenon is caused. Then, the p-type low-concentration region 25 is formed more deeply with less concentration gradient than in ordinary 7-degree ion implantation, so that a p-type low-concentration region 25 uniform in the direction of depth can be formed. As shown in Fig. 9D, the oxide film 23 on the transistor formation region is removed, and a p-type polycrystalline silicon film 16 containing boron and having a thickness of 100 nm to 300 nm is formed on the entire surface of the substrate 11 including a region where the surface of the substrate is exposed. For example, boron is doped in the polycrystalline silicon film 16 in accordance with ion implantation with an energy of 5 to 10 keV and at 5 x 10 15 to 1 x 10 16 cm -2 . Boron may be doped during formation of the polycrystalline silicon film 16. Subsequently, a nitride film 19 having a thickness of 100 nm to 200 nm is formed by using the known LPCVD method. The resultant structure is patterned into a predetermined shape to form a base contact electrode 16, and an emitter opening portion 300 is formed in the base contact electrode 16. Subsequently, boron is ion-implanted in the active base region with an energy of 10 keV and at 5 x 10 12 cm -2 to form the p-type intrinsic base region 8. Phosphorus is ion-implanted with an energy of 300 to 400 keV and at 1 x 10 12 to 1 x 10 13 nm -2 through the emitter opening portion 300 to form a second pedestal collector region 203 at a depth of about 0.4 to 0.5 µm (a projected range Rp of ion implantation) in the transistor formation region. As shown in Fig. 9E, a side wall insulating film, e.g., a nitride film 20, having a thickness of about 100 nm to 300 nm is formed on the side surface of the base contact electrode 16 in accordance with a known technique. Phosphorus is ion-implanted with an energy of 200 to 250 keV and at 1 x 10 12 to 1 x 10 13 nm -2 through an emitter opening portion 300a, so that a third pedestal collector region 202 is formed at a depth of about 0.25 to 0.35 µm (a projected range Rp of ion implantation) in the transistor formation region. As shown in Fig. 9F, a polycrystalline silicon layer containing an n-type impurity, e.g., arsenic, and having a thickness of 200 nm to 300 nm is formed to form an emitter contact electrode 21. The resultant structure is thermally treated in a nitrogen atmosphere of 900 to 950°C for 10 minutes, so that arsenic contained in the emitter contact electrode 21 diffuses into the p-type intrinsic base region 18, thus forming an emitter region 22. At this time, boron contained in the p-type polycrystalline silicon film 16 diffuses into the low-concentration region 25 simultaneously to form an external base region 17. Thereafter, although not shown, an insulating interlayer film, an electrode, and the like are formed in accordance with a known method, thus completing a bipolar transistor. Figs. 10A and 10B show the impurity concentration distribution in the direction of depth of the pedestal collector according to the second embodiment shown in Fig. 8 respectively along the lines XA - XA and XB - XB therein. In Figs. 10A and 10B, the impurity concentration in the ordinate is shown by logarithm. In contrast to these impurity concentration distributions, Japanese Unexamined Patent Publication No. 4-51526 employed as a comparative example describes a technique for lowering the concentration of the n-type impurity in a region extending from the surface of a collector layer to a depth of 0.5 µm to 1 x 10 16 /cm 3 (a technique for not inverting this region to a p-type region), as shown in Figs. 11B, by performing compensation ion implantation of a p-type impurity, e.g., boron, to an n-type collector layer by using an isolation oxide film as a mask. Figs. 11A and 11B show the impurity concentration distributions of a section of the intrinsic base region and of a section of the external base region of this comparative example. However, it is difficult to form such a compensated low-concentration region having a concentration of 1 x 10 16 /cm 3 or less by compensating ion implantation in the interface of the external base diffusion layer and the collector at high precision. Meanwhile, with the method of forming a p-type low-concentration region having an impurity concentration distribution as in the second embodiment shown in Figs. 10A and 10B, such a low-concentration region can be realized comparatively easily, although the depletion layer extends less than with the method of compensating the impurity. According to the second embodiment, when the p-type low-concentration region 25 is formed by ion implantation at an angle of 0°, the parasitic capacitance can be further decreased than in the first embodiment by 5 to 10%. Also, since the p-type region of the link base region located between the external base region 17 and the intrinsic base region 18 is not compensated for by the n-type impurity which is doped in order to form the pedestal collector region, the base resistance does not increase unlike in the conventional ease but can be decreased by about 5 to 10%. Fig. 12 is a longitudinal sectional view showing a modification of the second embodiment. In the second embodiment, the deep N-well 24 is formed at a depth of about 1 to 2 µm (a projected range Rp of ion implantation) in a region including a transistor formation region by phosphorus ion implantation under conditions of, e.g., 1 to 1.5 MeV and 1 x 10 13 to 1 x 10 14 cm -2 . This implantation amount is preferably set to 1 x 10 14 cm -2 or less. If the ion implantation amount is suppressed to this value or less, the collector resistance of the bipolar transistor undesirably increases. In order to solve this drawback, in the modification shown in Fig. 12, when selectively forming a first pedestal collector region 204a, a phosphorus ion implantation region is formed to be connected to an n-type collector contact diffusion layer 15. For example, this first pedestal collector region 204a is formed at a depth of about 0.4 to 0.5 µm (a projected range Rp of ion implantation) in the transistor formation region with a phosphorus ion implantation energy of 300 to 400 keV and at 1 x 10 12 to 1 x 10 14 cm -2 . At this time, a portion of the first pedestal collector region 204a where phosphorus is doped through an isolation oxide film 14 having a thickness of 300 to 600 nm becomes shallower than the remaining portion. In this manner, when the first pedestal collector region 204a is connected to the collector contact diffusion layer 15, the collector resistance can be decreased by about 5 to 30% when compared to the second embodiment. It is to be understood that the present invention is not limited to the embodiments described above, but the conductivity type, the impurity to be ion-implanted, and the like can be designed arbitrarily while achieving the same effect as in the above embodiments.

Claims: A semiconductor device comprising an epitaxial layer (3) of one conductivity type formed on a semiconductor substrate (1) of the other conductivity type, a base region (8) of the other conductivity type formed on the epitaxial layer to extend from a surface of the epitaxial layer to a predetermined depth, the base region including an intrinsic base region (8) and an external base region (7), an emitter region (12) of the one conductivity type formed in the intrinsic base region, and a pedestal collector region of the one conductivity type formed in a portion of the epitaxial layer (3) which is immediately under the base region (8) to correspond thereto, wherein the pedestal collector region comprises a first pedestal collector region (104) formed at a deepest portion in the epitaxial layer, having a highest impurity concentration, and extending for a comparatively wide range in lateral direction, a second pedestal collector region (103) formed at a position in the epitaxial layer which is shallower than the first pedestal collector region, having an impurity concentration lower than that of the first pedestal collector region, and extending for a range smaller than that of the first pedestal collector region, and a third pedestal collector region (102) formed at a position in the epitaxial layer which is shallower than the second pedestal collector region, having an impurity concentration lower than that of the second pedestal collector region, and extending for a range smaller than that of the second pedestal collector region. A semiconductor device according to claim 1, further comprising a region (25) of the other conductivity type which is formed on a portion of the epitaxial layer immediately under the base region (17) to correspond thereto so as to be in contact with the base region and which has an impurity concentration lower than that of the base region. A semiconductor device according to claim 1, further comprising a collector buried layer (24) formed under the epitaxial layer and a collector contact diffusion layer (15) formed in the epitaxial layer to be in contact with the collector buried layer, wherein the first pedestal collector region (104a) is in contact with the collector contact diffusion layer with part of a periphery thereof. A semiconductor device according to claim 2, further comprising a collector buried layer formed under the epitaxial layer and a collector contact diffusion layer formed in the epitaxial layer to be in contact with the collector buried layer, wherein the first pedestal collector region is in contact with the collector contact diffusion layer with part of a periphery thereof. A method of manufacturing a semiconductor device, comprising the steps of forming an epitaxial layer (3) of one conductivity type on a semiconductor substrate (1) of the other conductivity type, doping an impurity of the one conductivity type to a prospective transistor formation region from a surface of the epitaxial layer to have a first depth and for a predetermined height, thus forming a first pedestal collector region (104), forming a polycristalline silicon film (6) of the one conductivity type on the substrate, using part of the polycristalline silicon film as a base contact electrode and forming an emitter opening portion in part of the base contact electrode, doping an impurity of the other conductivity type to the substrate through the emitter opening portion, thus forming an intrinsic base region (8), doping an impurity of the one conductivity type from the surface of the epitaxial layer through the emitter opening portion to have a second depth shallower than the first depth and for a predetermined height, thus forming a second pedestal collector region (103), forming a side wall comprising an insulating film (10) at least on an inner surface of the emitter opening portion, doping an impurity of the one conductivity type from the surface of the epitaxial layer through the emitter opening portion to have a third depth shallower than the second depth and for a predetermined height, thus forming a third pedestal collector region (102), and doping an impurity of the one conductivity type to the intrinsic base region, thus forming an emitter region (12), wherein the impurity concentrations and the lateral extension of the first, second and third pedestal collector regions (102, 103, 104, 202, 203, 204) increase towards the substrate. A method according to claim 5, further comprising, after the step of forming the first pedestal collector region and before the step of forming the base region, the step of removing the insulating film from the surface of the epitaxial layer, and the step of doping an impurity of the other conductivity type in accordance with ion implantation at an implantation angle of 0°, thus forming a low-concentration layer of the other conductivity type in the vicinity of the surface of the epitaxial layer.

Inventors: YAMAZAKI TORU, YAMAZAKI, TORU, Yamazaki, Toru, c/o NEC Corp.
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1996
Main classification: H01L29
IPC codes: H01L21, H01L29