DRAM capacitor electrode process

Abstract: A storage node 64 of a capacitor having increased charge storage capacity and a method for forming thereof. A doped polysilicon region 68 is formed. A thin layer of hemispherical grain polysilicon 70 is deposited over the doped polysilicon region 68. The doped polysilicon region 68 and the thin layer of hemispherical grain polysilicon 70 are etched using an etch chemistry that etches the doped polysilicon region 68 faster than the thin layer of hemispherical grain polysilicon 70 to increase the surface area of an upper surface 66 of the storage node 64.

Description: FIELD OF THE INVENTION This invention generally relates to semiconductor processing and more specifically to storage capacitors for dynamic memories. BACKGROUND OF THE INVENTION The acquisition of sufficient charge-storage capacity in a small area is one of the most challenging design problems of Ultra Large Scale Integration (ULSI) Dynamic Random Access Memory (DRAM) technology. As the pus for higher density DRAMs increases, the charge-storage device of each memory cell must physically fit into a smaller area. A moderate degree of success has been achieved through the use of cell structure innovations that increase the effective storage-node area beyond the amount allocated within each memory cell. Several methods use hemispherical grain (HSG) polysilicon (i.e. rugged poly) to increase the charge storage capacity. HSG polysilicon, as deposited, enhances the surface area bya factor of 1.6-2.2. In one method, a thin layer of HSG polysilicon is deposited to produce a pseudo archipelago pattern (grain size and separation will not strictly be constant over the area of interest) with dimensions that are far smaller than those presently producible with current practical lithography tools. (Archipelago patterns with features less than 500Å are possible with electron-beam lithography, but low throughput makes this process unattractive). The HSG polysilicon 10 is deposited on a thin CVD (chemical-vapor deposition) oxide layer 12 that rests on top of a thick doped polysilicon layer 14, as shown in Figure 1a. The doped polysilicon layer 14 extends through oxide layer 18 to semiconductor body 20. An oxide etch, followed by a polysilicon etch produces a micro-villus pattern 16 as shown in Figure 1b. One such method of manufacture is disclosed in U.S.-A-5,350,707 filed 13 November 1992 by Jaehong Ko et al, and entitled "Method for making a capacitor having an electrode surface with a plurality of trenches formed therein". This document teaches the etching of trenches into a conductive layer of the capacitor structure by anistropic etching in order that the surface area of the storage node is increased. Similarly, a casellated pattern formed in a conductive layer of a storage node capacitor by a process comprising etching between hemispherical grains of polysilicon is diclosed in German Patent DE-A-43-21-638A1, filed 30 June 1993 by Samsung Electronics Co. Ltd., and entitled "Semiconductor Storage Element with a Capacitor, and a Process for its Manufacture". A major problem with this approach is that area enhancement is due totally to the ability to form micro-villi of high aspect ratio. The ability to strictly control the HSG polysilicon graion distribution threatens the reliability of such a structure. Thus, there is a need for surface area enhancement of charge storage nodes that is easily manufacturable, repeatable, and reliable. SUMMARY OF THE INVENTION According to claim 1 of the invention, a method of forming a storage node of a capacitor having increased storage node capacity is disclosed herein. A doped polysilicon storage node is formed at the surface of a semiconductor body. A thin layer of HSG polysilicon is then formed over the structure. The doped and HSG polysilicon are then etched using an etch chemistry that selectively etches the doped polysilicon faster than the HSG polysilicon. An etch ratio of at least 3:1 is preferred. The etch is anisotropic and does not remove the HSG polysilicon from the sidewalls of the storage node. As a result, U-shaped grooves are formed in the upper surface of the doped polysilicon storage node which increases the surface area of the storage node, and thus increases the charge storage capacity. Claim 2 of the invention is for a method of forming a memory cell comprising a capacitor with a storage node as defined in claim 1. An advantage of the invention is providing a capacitor having increased storage capacity. A further advantage of the invention is providing a charge storage node having increased surface area. A further advantage of the invention is providing a charge storage node having increased surface area that is highly reproducible, reliable and easily fabricated. These and other advantages of the invention will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS In the drawings: FIGs. 1a-b are cross-sectional views of a prior art charge storage node; FIGs. 2a-b are perspective and layout views, respectively, of a DRAM cell according to the invention; FIG. 3 is a cross-sectional view of a charge storage node according to the invention; FIGs. 4a-h are cross-sectional views of a charge storage node according to the invention at various stages of fabrication; FIG. 5a is a perspective view of a charge storage node prior to HSG etchback; FIG. 5b is a graph of storage node height versus area enhancement factor; FIG. 5c is a perspective view of a charge storage node after HSG etchback; FIG. 6 is a graph of area enhancement factor and etch depth versus etch duration; and FIG. 7 is a graph of I-V characteristics comparing before and after etch leakage currents. Corresponding numerals and symbols in the different figures refer to corresponding parts unless otherwise indicated. DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS The invention will be described in conjunction with a charge storage node for a DRAM memory cell. However, it will be apparent to those skilled in the art that the invention is applicable to many technologies desiring increased storage capacity in a small area. One embodiment of a DRAM cell using a charge storage node according to the invention is shown in Figures 2a-b. DRAM cell 50 is a capacitor over bitline (COB) type cell. Active area 52 is formed in substrate 54. Wordline 56 extends over active area 52 to form the gate of a transistor. Contact 58 connects bitline 60 to active area 52 on one side of wordline 56. A local interconnect 62 is used to connect charge storage node 64 to active area 52 on the other side of wordline 56. With the exception of charge storage node 64, DRAM cell 50 is a conventional DRAM cell and operates in a conventional manner. Charge storage node 64 has increased surface area on the upper surface 66, as shown in detail in Figure 3. Charge storage node 64 includes a doped polysilicon region 68 and a thin layer of HSG polysilicon 70 on the sidewalls of the doped polysilicon region 68. HSG polysilicon layer 70 increases the surface area on the sidewalls of charge storage node 64 by a factor on the order of 1.6 to 2.5. None of the originally deposited HSG polysilicon is located on the upper surface 66 of charge storage node 64. The upper surface 66 of charge storage node 64 has U-shaped grooves 72 which have a depth on the order of 0.1 - 0.3 microns. The U-shaped grooves 72 of upper surface 66 increase the surface area by a factor on the order of 3 or greater depending on the depth and average spacing of the U-shaped grooves 72. The storage capacity of a capacitor is directly related to the effective surface area of the nodes or electrodes of the capacitor. Thus, increasing the surface area of charge storage node 64 increases the storage capacity of a capacitor formed with charge storage node 64 as the bottom electrode. This is extremely important for very dense devices, such as DRAMs, where the area allocated for charge storage capacity is very small. In addition, upper surface 66 avoids the problems of reliability, repeatability, and difficulty in manufacturing associated with high aspect ratio structures used in prior art techniques. Figure 4a shows a semiconductor body 82 having a dielectric layer 84 formed thereon. Dielectric layer 84 has been patterned and etched to remove the portions where a charge storage node 64 is to be formed. As is the case for COB cells, semiconductor body 82 may have active areas, bitlines, wordlines, and other structures (not shown) located therein. Typically, semiconductor body 82 will not yet include metal interconnect lines. The formation of a charge storage node 64 into the structure of Figure 4a according to the invention will now be described. A layer of polysilicon is deposited over the surface of the structure to a depth above dielectric layer 84 of 0.3-0.6 microns. Preferably, the polysilicon is insitu-doped (ISD) with phosphorous. However, the polysilicon may alternatively be doped after deposition and/or doped with alternative dopants. The doped polysilicon layer is then patterned and etched to form the doped polysilicon region 68 of charge storage node 64, as shown in Figure 4b. The width and length of doped polysilicon region 68 will vary by design, but may typically be in the range of 0.3 to 1 micron each. Next, a thin layer of HSG polysilicon 70 is deposited over the structure as shown in Figure 4c. The HSG layer 70 should be thin enough to bring about surface area enhancement for the corresponding charge storage node 64 dimensions. For high density DRAM applications, surface area enhancement occurs when the grain size of the HSG polysilicon 70 is much less than the dimensions of the charge storage node 64. For thin HSG layers, the grain size and film thickness are usually on the same order of magnitude. A grain size and film thickness on the order of 500Å is appropriate for 256 Mb DRAM applications having approximately a 0.25 µm 2 storage node cross-sectional area. Typically, HSG polysilicon layer 70 is deposited via silane (SiH 4 ) deposition at the amorphous silicon/polysilicon transition temperature. However, other deposition techniques may alternatively be used. HSG polysilicon layer 70 is preferably undoped to maximize etch selectivity between the HSG polysilicon layer 70 and doped polysilicon region 68. Figure 4d shows an amplified view of the upper surface of charge storage node 64 after HSG polysilicon 70 deposition. The average separation between HSG grains 86 is the key to optimization of surface area enhancement. It is not favorable to have adjacent grains 86 in contact with one another. As will be explained further below, an average grain separation of 100-300Å (10Å = 1 nm) is desirable. Next, a charge storage node etch is performed to enhance the surface area of the upper surface 66. The etch chemistry needs to be selective to doped polysilicon region 68 over undoped HSG polysilicon layer 70, such as a halogen based gas chemistry. An etch selectivity ratio of 3:1 or greater is desired. For example, an anisotropic etch using a HBr/Cl 2 etch-gas chemistry may be used. Etch process selectivity allows HSG polysilicon layer 70 to serve as an etch mask so that the degree of roughness of the original charge storage node surface (with HSG) may be amplified accordingly. Referring to Figure 4e, the doped polysilicon region 68 etches faster than the HSG polysilicon layer 70 causing grooves to be formed in the surface of the doped polysilicon region 68. The etch continues until all of the HSG polysilicon layer 70 is removed from the upper surface, as shown in Figure 4f. This creates U-shaped grooves 72 in the upper surface having a depth on the order of 0.1-0.3. microns. As shown in Figure 4g, because the etch is anisotropic, the HSG polysilicon layer 70 remains on the sidewalls of charge storage node 64. However, all of the HSG polysilicon layer 70 between charge storage nodes 64 is removed from the surface of dielectric layer 84 during the charge storage node etch. This is necessary to electrically isolate the charge storage nodes 64 from each other. After the charge storage node etch, a dielectric layer is deposited, followed by the deposition of a polysilicon layer as shown in Figure 4h. The dielectric layer may comprise an oxide-nitride-oxide tri-layer. In order to take advantage of the surface area enhancement, there must be enough room in the grooves 72 to accommodate both capacitor dielectric 88 and top capacitor electrode 90. Accordingly, the average HSG grain 86 separation before the charge storage node etch needs to be on the order of 150Å or larger. Figure 5a is a depiction of charge storage node 64 with dimensions approaching those needed for 256 Mb DRAM applications after deposition of thin HSG polysilicon layer 70 but prior to the etchback. A top and A sw are the area enhancement factors for the charge storage node 64's top surface and sidewalls, respectively. Before etchback, A top and A sw are identical. The total area enhancement factor, A eff , is determined according to the following formula: A eff = A top ( w*L ) + A sw *2*H(w + L) (w*L) + (2H(w + L)) Assuming that A top = A sw = 2.25, w = 0.3 µm, L = 0.8µm, and H = 0.6µm, A eff according to the above equation equals 2.25. After etchback, A top increases, while A sw remains the same. As A top increases, the height of the charge storage node 64 can be decreased while obtaining the same total effective area. Figure 5b is a graph showing the relationship between the area enhancement factor of the top surface, A top , and the height (H) which yields a constant value of total surface area. For example, if the area enhancement factor, A top , increased to 4.2 (as a result of an etchback), the height (H) of charge storage node 64 could be reduced to 0.5 µm while obtaining the same total effective area as a 0.6 µm - storage node. This is shown in Figure 5c. It should be noted that if a reduced height is not required, the final (post etchback) height could remain at 0.6 µm and the total effective area enhancement factor, A eff , would increase to 2.55. Figure 6 is a graph of how the area enhancement factor (AEF) varies as a function of etch time using a HBr/Cl 2 etch-gas chemistry. Planar MIS-type capacitors were used to obtain this data. The AEF first decreases slightly before it begin to increase. This decrease can be traced to two causes. First, the etch begins with a brief (15 sec.) breakthrough stage which occurs in CF 4 . This segment of the etch is more selective to the undoped HSG polysilicon layer. Therefore, surface roughness is lost during this portion of the etch and the actual starting point of the HBr/Cl 2 etch begins with an AEF closer to 2.0. Second, because the initial grain separation in this experiment was on the order or 100 Å, the valleys formed in the doped polysilicon portion are initially too narrow to accommodate both the capacitor dielectric layer and the top polysilicon electrode. As the main etch proceeds, the valleys become large enough to accommodate both the capacitor dielectric and top polysilicon electrode. Figure 6 shows that after an etch duration of 40 seconds, an AEF of approximately 2.9 and an etch depth of approximately 940 Å are obtained in this example. Figure 6 also shows that the AEF for a smooth polysilicon capacitor does not vary significantly with etch duration. Figure 7 is a plot of leakage current versus gate voltage for etched and unetched HSG polysilicon capacitors. As can be seen in Figure 7, the charge storage node etch has negligible effect on the leakage characteristics of the storage capacitor.

Claims: A method for forming a storage node electrode (64) of a capacitor comprising: forming a doped polysilicon region (68) over a semiconductor body (82); depositing a thin undoped layer of hemispherical grain polysilicon (70) over said doped polysilicon region (68) ; etching said doped polysilicon region (68) and said thin undoped layer of hemispherical grain polysilicon (70); and characterised in that said step of etching said doped polysilicon region (68) and said thin undoped layer of hemispherical grain polysilicon (70) is performed with an etch chemistry that etches said doped polysilicon faster than said undoped polysilicon to increase the upper surface area (66) of said storage node electrode (64). A method of forming a memory cell (50) comprising: forming an active area (52) in a semiconductor body (82); forming a polysilicon gate (56) extending over said active area (52); forming a bitline (60) over and insulated from said polysilicon gate (56), said bitline (60) arranged to be electrically coupled to said active area (52) on a first side of said polysilicon gate (56); and forming a storage node electrode (64) arranged to be electrically coupled to said active area (52) on a second side of said polysilicon gate (56), said step of forming said storage node electrode (64) comprising the steps of: forming a doped polysilicon region (68) over said bitline (60); depositing a thin undoped layer of hemispehrical grain polysilicon (70) over said doped polysilicon region (68); etching said doped polysilicon region (68) and said thin undoped layer of hemispherical grain polysilicon (70); forming a capacitor dielectric (88) over said storage node electrode (64); forming a capacitor electrode (90) over said capacitor dielectric (88) such that said storage node electrode (64), said capacitor dielectric (88), and said capacitor electrode (90) form a capacitor; and characterised in that said step of etching said doped polysilicon region (68) and said thin undoped layer of hemispherical grain polysilicon (70) is performed with an etch chemistry that etches said doped polysilicon faster than said undoped polysilicon to increase the upper surface area (66) of said storage node electrode (64). The method as claimed in claim 1 or claim 2, wherein said etching step comprises: etching said doped polysilicon region (68) and said thin undoped layer of hemispherical grain polysilicon (70) with a halogen etch chemistry. The method as claimed in claim 1 or claim 2, wherein said etching step comprises: etching said doped polysilicon region (68) and said thin undoped layer of hemispherical grain polysilicon (70) with a HBr/C12 etch chemistry. The method as claimed in any preceding claim further comprising: performing said etching step until all of said thin undoped layer of hemispherical grain polysilicon (70) is removed from said upper surface of said storage node electrode (64). The method as claimed in any preceding claim, wherein said step of forming said doped polysilicon region (68) comprises: in-situ doping of said doped polysilicon region (68). The method as claimed in any preceding claim further comprising: doping said doped polysilicon region (68) with phosphorous. The method as claimed in any preceding claim further comprising: performing said etching step such that U-shaped grooves (72) are formed in said upper surface (66) of said doped polysilicon region (68). The method as claimed in claim 8, wherein said etching step comprises: forming U-shaped grooves (72) having a depth of 0.1-0.3 microns. The method as claimed in any preceding claim further comprising: depositing said thin undoped layer of hemispherical grain polysilicon (70) such that the dimensions of the grains of hemispherical polysilicon are substantially less than the dimensions of the storage node electrode (64). The method as claimed in any preceding claim further comprising: depositing said thin undoped layer of hemispherical grain polysilicon (70) to a thickness of the order of 50 nm (500Å). The method as claimed in any preceding claim further comprising: performing said etching step such that a selectivity of at least 3:1 between doped polysilicon and hemispherical grain polysilicon is achieved. The method as claimed in any preceding claim, wherein said step of depositing a thin undoped layer of hemispherical grain polysilicon (70) comprises: depositing a thin undoped layer of hemispherical grain polysilicon (70) on sidewalls and an upper surface of said polysilicon region (68). The method as claimed in any preceding claim, wherein the step of depositing a thin undoped layer of hemispherical grain polysilicon (70) comprises: depositing a thin undoped layer of hemispherical grain polysilicin (70) having an average grain separation of the order of 10-30 nm (100-300Å).

Inventors: CRENSHAW DARIUS L, MCKEE JEFFREY, WISE RICK L, CRENSHAW, DARIUS L., MCKEE, JEFFREY, WISE, RICK L.
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1996
Main classification: H01L21
IPC codes: H01L21, H01L27