GENERAL PURPOSE, PROGRAMMABLE MEDIA PROCESSOR

Abstract: A general purpose, programmable media processor (12) for processing and transmitting a media data streams. The media processor (12) incorporates an execution unit (100) that maintains substantially peak data throughout of media data streams. The execution unit (100) includes a dynamically partionable multi-precision arithmetic unit (102), programmable switch (104) and programmable extended mathematical element (106). A high bandwidth external interface (124) supplies media data streams at substantially peak rates to a general purpose register file (110) and the execution unit. A memory management unit, and instruction and data cache/buffers (118, 120). The general purpose, programmable media processor (12) is disposed in a network fabric consisting of fiber optic cable, coaxial cable and twisted pair wires to transmit, process and receive single or unified media data streams.

Description: S GENERAL PURPOSE, PROGRAMMABLE MEDIA PROCESSOR 10 Field of the Invention This invention relates to the field of communications processing, and more particularly, to a method and apparatus for real-time processing of 15 multi-media digital communications. Background of the Invention Optical fiber and discs have made the transmission and storage of digital information both cheaper and easier than older analog technologies. An 20 improved system for digital processing of media data streams is necessary in order to realize the full potential of these advanced media. For the past century, telephone service delivered over copper twisted pair has been the lingua franca of communications. Over the next century, broadband services delivered over optical fiber and coax will more completely fulfill the human need for sensory information by supplying voice, video, and data at rates of about 1 ,000 times greater than narrow band telephony. Current general-purpose microprocessors and digital signal processors ("DSPs") can handle digital voice, data, and images at narrow band rates, but they are way too slow for processing media data at broadband rates. This shortfall in digital processing of broadband media is currently being addressed through the design of many different kinds of application- specific integrated circuits ("ASICs " ). For example, a prototypical broadband device such as a cable modem modulates and demodulates digital data at rates up to 45 Mbits/sec within a single 6 MHZ cable channel (as compared to rates of 28.8 Kbits/sec within a 6 KHz channel for telephone modems) and transcodes it onto a 10/100baseT connection to a personal computer ("PC") or workstation. Current cable modems thus receive data from a coaxial cable connection through a chain of specialized ASIC devices in order to accomplish Quadrature Amplitude Modification ("QAM") demodulation. Reed-Solomon error correction, packet filtering, Data Encryption Standard ("DES") decryption, and Ethernet protocol handling. The cable modems also transmit data to the coaxial cable link through a second chain of devices to achieve DES encryption, Reed-Solomon block encoding, and Quaternary Phase Shift Keying ("QPSK") modulation. In these environments, a general-purpose processor is usually required as well in order to perform initialization, statistics collection, diagnostics, and network management functions. The ASIC approach to media processing has three fundamental flaws: cost, complexity, and rigidity. The combined silicon area of all the specialized ASIC devices required in the cable modem, for example, results in a component cost incompatible with the per subscriber price target for a cable service. The cable plant itself is a very hostile service environment, with noise ingress, reflections, nonlinear amplifiers, and other channel impairments, especially when viewed in the upstream direction. Telephony modems have developed an elaborate hierarchy of algorithms implemented in DSP software, with automatic reduction of data rates from 28.8Kbits/sec to 19.6Kbits/sec, 14.4Kb its/ sec, or much lower rates as needed to accommodate noise, echoes, and other impairments in the copper plant. To implement similar algorithms on an ASIC-based broadband modem is far more complex to achieve in software. These problems of cost, complexity, and rigidity are compounded further in more complete broadband devices such as digital set-top boxes, multimedia PCs, or video conferencing equipment, all of which go beyond the basic radio frequency ("RF " ) modem functions to include a broad range of audio and video compression and decoding algorithms, along with remote control and graphical user interfaces. Software for these devices must control what amounts to a heterogeneous multi-processor, where each specialized processor has a different, and usually eccentric or primitive, programming environment. Even if these programming environments are mastered, the degree of programmability is limited. For example, Motion Picture Expert Group-I ("MPEG-I") chips manufactured by AT&T Corporation will not implement advances such as fractal- and wavelet-based compression algorithms, but these chips are not readily software upgradeable to the MPEG-II standard. A broadband network operator who leases an MPEG ASIC-based product is therefore at risk of having to continuously upgrade his system by purchasing significant amounts of new hardware just to track the evolution of MPEG standards. The high cost of ASIC-based media processing results from inefficiencies in both memory and logic. A typical ASIC consists of a multiplicity of specialized logic blocks, each with a small memory dedicated to holding the data which comprises the working set for that block. The silicon area of these multiple small memories is further increased by the overhead of multiple decoders. sense amplifiers, write drivers, etc. required for each logic block. The logic blocks are also constrained to operate at frequencies determined by the internal symbol rates of broadband algorithms in order to avoid additional buffer memories. These frequencies typically differ from the optimum speed-area operating point of a given semiconductor technology. Interconnect and synchronization of the many logic and memory blocks are also major sources of overhead in the ASIC approach. The disadvantages of the prior ASIC approach can be over come by a single unified media processor. The cost advantages of such a unified processor can be achieved by gathering all the many ASIC functions of a broadband media product into a single integrated circuit. Cost reduction is further increased by reducing the total memory area of such a circuit by replacing the multiplicity of small ASIC memories with a single memory hierarchy large enough to accommodate the sum total of all the working sets, and wide enough to supply the aggregate bandwidth needs of all the logic blocks. Additionally, the logic block interconnect circuitry to this memory hierarchy may be streamlined by providing a generally programmable switching fabric. Many of the logic blocks themselves can also replaced with a single multi-precision arithmetic unit, which can be internally partitioned under software control to perform addition, multiplication, division, and other integer and floating point arithmetic operations on symbol streams of varying widths, while sustaining the full data throughput of the memory hierarchy. The residue of logic blocks that perform operations that are neither arithmetic or permutation group oriented can be replaced with an extended math unit that supports additional arithmetic operations such as finite field, ring, and table lookup, while also sustaining the full data throughput of the memory hierarchy. The above multi-precision arithmetic, permutation switch, and extended math operations can then be organized as machine instructions that transfer their operands to and from a single wide multi-ported register file. These instructions can be further supplemented with load/store instructions that transfer register data to and from a data buffer/cache static random access memory ("SRAM") and main memory dynamic random access memories ("DRAMs"), and with branch instructions that control the flow of instructions executed from an instruction buffer/cache SRAM. Extensions to the load/store instructions can be made for synchronization, and to branch instructions for protected gateways, so that multiple threads of execution for audio, video, radio, encryption, networking, etc. can efficiently and securely share memory and logic resources of a unified machine operating near the optimum speed-area point of the target semiconductor process. The data path for such a unified media processor can interface to a high speed input/output ("I/O") subsystem that moves media streams across ultra-high bandwidth interfaces to external storage and I/O. Such a device would incorporate all of the processing capabilities of the specialized multi-ASIC combination into a single, unified processing device. The unified processor would be agile and capable of reprogramming through the transmission of new programs over the communication medium. This programmable, general purpose device is thus less costly than the specialized processor combination, easier to operate and reprogram and can be installed or applied in many differing devices and situations. The device may also be scalable to communications applications that support vast numbers of users through massively parallel distributed computing. It is therefore an object of this invention to process media data streams by executing operations at very high bandwidth rates. It is also an object of this invention to unify the audio, video, radio, graphics, encryption, authentication, and networking protocols into a single instruction stream. It is also an object of this invention to achieve high bandwidth rates in a unified processor that is easy to program and more flexible than a heterogeneous combination of special purpose processors. It is a further object of the invention to support high level mathematical processing in a unified media processor, including finite group, fmite field, finite ring and table look-up operations, all at high bandwidth rates. It is yet a further object of the invention to provide a unified media processor that can be replicated into a multi-processor system to support a vast array of users. It is yet another object of this invention to allow for massively parallel systems within the switching fabric to support very large numbers of subscribers and services. It is also an object of the invention to provide a general purpose programmable processor that could be employed at all points in a network. It is a further object of this invention to sustain very high bandwidth rates to arbitrarily large memory and input/output systems. Summary of the Invention In view of the above, there is provided a system for media processing that maintains substantially peak data throughput in the execution and transmission of multiple media data streams. The system includes in one aspect a general purpose, programmable media processor, and in another aspect includes a method for receiving, processing and transmitting media data streams. The general purpose, programmable media processor of the invention further includes an execution unit, high bandwidth external interface, and can be employed in a parallel multi-processor system. According to the apparatus of the invention, an execution unit is provided that maintains substantially peak data throughput in the unified execution of multiple media data streams. The execution unit includes a data path, and a multi-precision arithmetic unit coupled to the data path and capable of dynamic partitioning based on the elemental width of data received from the data path. The execution unit also includes a switch coupled to the data path that is programmable to manipulate data received from the data path and provide data streams to the data path. An extended mathematical element is also provided, which is coupled to the data path and programmable to implement additional mathematical operations at substantially peak data throughput. In a preferred embodiment of the execution unit, at least one register file is coupled to the data path. According to another aspect of the invention, a general purpose programmable media processor is provided having an instruction path and a data path to digitally process a plurality of media data streams. The media processor includes a high bandwidth external interface operable to receive a plurality of data of various sizes from an external source and communicate the received data over the data path at a rate that maintains substantially peak operation of the media processor. At least one register file is included, which is configurable to receive and store data from the data path and to communicate the stored data to the data path. A multi-precision execution unit is coupled to the data path and is dynamically configurable to partition data received from the data path jo account for the elemental symbol size of the plurality of media streams, and is programmable to operate on the data to generate a unified symbol output to the data path. According to the preferred embodiment of the media processor, means are included for moving data between registers and memory by performing load and store operations, and for coordinating the sharing of data among a plurality of tasks by performing synchronization operations based upon instructions and data received by the execution unit. Means are also provided for securely controlling the sequence of execution by performing branch and gateway operations based upon instructions and data received by the execution unit. A memory management unit operable to retrieve data and instructions for timely and secure communication over the data path and instruction path respectively is also preferably included in the media processor. The preferred embodiment also includes a combined instruction cache and buffer that is dynamically allocated between cache space and buffer space to ensure real-time execution of multiple media instruction streams, and a combined data cache and buffer that is dynamically allocated between cache space and buffer space to ensure real-time response for multiple media data streams. In another aspect of the invention, a high bandwidth processor interface for receiving and transmitting a media stream is provided having a data path operable to transmit media information at sustained peak rates. The high bandwidth processor interface includes a plurality of memory controllers coupled in series to communicate stored media information to and from the data path, and a plurality of memory elements coupled in parallel to each of the plurality of memory controllers for storing and retrieving the media information. In the preferred embodiment of the high bandwidth processor interface, the plurality of memory controllers each comprise a paired link disposed between each memory controller, where the paired links each transmit and receive plural bits of data and have differential data inputs and outputs and a differential clock signal. Yet another aspect of the invention includes a system for unified media processing having a plurality of general purpose media processors, where each media processor is operable at substantially peak data rates and has a dynamically partitioned execution unit and a high bandwidth interface for communicating to memory and input/output elements to supply data to the media processor at substantially peak rates. A bi-directional communication fabric is provided, to which the plurality of media processors are coupled, to transmit and receive at least one media stream comprising presentation, transmission, and storage media information. The bi-directional communication fabric preferably comprises a fiber optic network, and a subset of the plurality of media processors comprise network servers. According to yet another aspect of the invention, a parallel multi¬ media processor system is provided having a data path and a high bandwidth external interface coupled to the data path and operable to receive a plurality of data of various sizes from an external source and communicate the received data at a rate that maintains substantially peak operation of the parallel multi-processor system. A plurality of register files, each having at least one register coupled to the data path and operable to store data, are also included. At least one multi- precision execution unit is coupled to the data path and is dynamically configurable to partition data received from the data path to account for the elemental symbol size of the plurality of media streams, and is programmable to operate in parallel on data stored in the plurality of register files to generate a unified symbol output for each register file. According to the method of the invention, unified streams of media data are processed by receiving a stream of unified media data including presentation, transmission and storage information. The unified stream of media data is dynamically partitioned into component fields of at least one bit based on the elemental symbol size of data received. The unified stream of media data is then processed at substantially peak operation. In one aspect of the invention, the unified stream of media data is processed by storing the stream of unified media data in a general register file. Multi-precision arithmetic operations can then be performed on the stored stream of unified media data based on programmed instructions, where the multi-precision arithmetic operations include Boolean, integer and floating point mathematical operations. The component fields of unified media data can then be manipulated based on programmed instructions that implement copying, shifting and re-sizing operations. Multi-precision mathematical operations can also be performed on the stored stream of unified media data based on programmed instructions, where the mathematical operations including finite group, finite field, finite ring and table look-up operations. Instruction and data pre-fetching are included to fill instruction and data pipelines, and memory management operations can be performed to retrieve instructions and data from external memory. The instructions and data are preferably stored in instruction and data cache/buffers, in which buffer storage in the instruction and data cache/buffers is dynamically allocated to ensure real-time execution. Other aspects of the invention include a method for achieving high bandwidth communications between a general purpose media processor and external devices by providing a high bandwidth interface disposed between the media processor and the external devices, in which the high bandwidth interface comprises at least one uni-directional channel pair having an input port and an output port. A plurality of media data streams, comprising component fields of various sizes, are transmitted and received between the media processor and the external devices at a rate that sustains substantially peak data throughput at the media processor. A method for processing streams of media data is also included that provides a bi-directional communications fabric for transmitting and receiving at least one stream of media data, where the at least one stream of media data comprises presentation, transmission and storage information. At least one programmable media processor is provided within the communications network for receiving, processing and transmitting the at least one stream of unified media data over the bi-directional communications fabric. The general purpose, programmable media processor of the invention combines in a single device all of the necessary hardware included in the specialized processor combinations to process and communicate digital media data streams in real-time. The general purpose, programmable media processor is therefore cheaper and more flexible than the prior approach to media processing. The general purpose, programmable media processor is thus more susceptible to incorporation within a massively parallel processing network of general purpose media processors that enhance the ability to provide real-time multi-media communications to the masses. These features are accomplished by deploying server media processors and client media processors throughout the network. Such a network provides a seamless, global media super-computer which allows programmers and network owners to virtualize resources. Rather than restrictively accessing only the memory space and processing time of a local resource, the system allows access to resources throughout the network. In small access points such as wireless devices, where very little memory and processing logic is available due to limited battery life, the system is able to draw upon the resources of a homogeneous multi-computer system. The invention also allows network owners the facility to track standards and to deploy new services by broadcasting software across the network rather than by instituting costly hardware upgrades across the whole network. Broadcasting software across the network can be performed at the end of an advertisement or other program that is broadcasted nationally. Thus, services can be advertised and then transmitted to new subscribers at the end of the advertisement. These and other features and advantages of the invention will be apparent upon consideration of the following detailed description of the presently preferred embodiments of the invention, taken in conjunction with the appended drawings. Brief Description of the Drawings FIG. 1 is a block diagram of a broad band media computer employing the general purpose, programmable media processor of the invention; FIG. 2 is a block diagram of a global media processor employing multiple general purpose media processors according to the invention: FIG. 3 is an illustration of the digital bandwidth spectrum for telecommunications, media and computing communications; FIG. 4 is the digital bandwidth spectrum shown in FIG. 3 taking into account the bandwidth overhead associated with compressed video techniques: FIG. 5 is a block diagram of the current specialized processor solution for mass media communication, where FIG. 5(a) shows the current distributed system, and FIG. 5(b) shows a possible integrated approach; FIG. 6 is a block diagram of two presently preferred general purpose media processors, where FIG. 6(a) shows a distributed system and FIG. 6(b) shows an integrated media processor; FIG. 7 is a block diagram of the presently preferred structure of a general purpose, programmable media processor according to the invention; FIG. 8 is a drawing consisting of visual illustrations of the various group operations provided on the media processor, where FIG. 8(a) illustrates the group expand operation, FIG. 8(b) illustrates the group compress or extract operation, FIG. 8(c) illustrates the group deal and shuffle operations, FIG. 8(d) illustrates the group swizzle operation and FIG. 8(e) illustrates the various group permute operations; FIG. 9 shows the preferred instruction and data sizes for the general purpose, programmable media processor, where FIG. 9(a) is an illustration of the various instruction formats available on the general purpose, programmable media processor, FIG. 9(b) illustrates the various floating-point data sizes available on the general purpose media processor, and FIG. 9(c) illustrates the various fixed- point data sizes available on the general purpose media processor; FIG. 10 is an illustration of a presently preferred memory management unit included in the general purpose processor shown in FIG. 7, where FIG. 10(a) is a translation block diagram and FIG. 10(b) illustrates the functional blocks of the transaction lookaside buffer; FIG. 11 is an illustration of a super-string pipeline technique; FIG. 12 is an illustration of the presently preferred super-spring pipeline technique; FIG. 13 is a block diagram of a single memory channel for communication to the general purpose media processor shown in FIG. 7; FIG. 14 is an illustration of the presently preferred connection of standard memory devices to the preferred memory interface; FIG. 15 is a block diagram of the input/output controller for use with the memory channel shown in FIG. 13; FIG. 16 is a block diagram showing multiple memory channels connected to the general purpose media processor shown in FIG. 7, where FIG. 16(a) shows a two-channel implementation and FIG. 16(b) illustrates a twelve- channel embodiment; FIG. 17 illustrates the presently preferred packet communications protocol for use over the memory channel shown in FIG. 13; FIG. 18 shows a multi-processor configuration employing the general purpose media processor shown in FIG. 7, where FIG. 18(a) shows a linear processor configuration, FIG. 18(b) shows a processor ring configuration, and FIG. 18(c) shows a two-dimensional processor configuration; and FIG. 19 shows a presently preferred multi-chip implementation of the general purpose, programmable media processor of the invention. Detailed Description of the Presently Preferred Embodiments Referring to the drawings, where like-reference numerals refer to like elements throughout, a broad band microcomputer 10 is provided in FIG. 1. The broad band microcomputer 10 consists essentially of a general purpose media processor 12. As will be described in more detail below, the general purpose media processor 12 receives, processes and transmits media data streams in a bi¬ directional manner from upstream network components to downstream devices. In general, media data streams received from upstream network components can comprise any combination of audio, video, radio, graphics, encryption, authentication, and networking information. As those skilled in the art will appreciate, however, the general purpose media processor 12 is in no way limited to receiving, processing and transmitting only these types of media information. The general purpose media processor 12 of the invention is capable of processing any form of digital media information without departing from the spirit and essential scope of the invention. Svstem Configuration In the preferred embodiment of the invention shown in FIG. 1. media data streams are communicated to the media processor 12 from several sources. Ideally, unified media data streams are received and transmitted by the general purpose media processor 12 over a fiber optic cable network 14. As will be described in more detail below, although a fiber optic cable network is preferred, the presently existing communications network in the United States consists of a combination of fiber optic cable, coaxial cable and other transmission media. Consequently, the general purpose media processor 12 can also receive and transmit media data streams over coaxial cable 14 and traditional twisted pair wire connections 16. The specific communications protocol employed over the twisted pair 16. whether POTS. ISDN or ADSL, is not essential: all protocols are supported by the broad band microcomputer 10. The details of these protocols are generally known to those skilled in the art and no further discussion is therefore needed or provided herein. Another form of upstream network communication is through a satellite link 18. The satellite link 18 is typically connected to a satellite receiver 20. The satellite receiver 20 comprises an antenna, usually in the form of a satellite dish, and amplification circuitry. The details of such satellite communications are also generally known in the art, and further detail is therefore not provided or included herein. As described above, the general purpose media processor 12 communicates in a bi-directional manner to receive, process and transmit media data streams to and from downstream devices. As shown in FIG. 1 , downstream communication preferably takes place in at least two forms. First, media data streams can be communicated over a bi-directional local network 22. Various types of local networks 22 are generally known in the art and many different forms exist. The general purpose media processor 12 is capable of communicating over any of these local networks 22 and the particular type of network selected is implementation specific. The local network 22 is preferably employed to communicate between the unified processor 12. and audio/visual devices 24 or other digital devices 26. Presently preferred examples of audio/visual devices 24 include digital cable television, video-on-demand devices, electronic yellow pages services. integrated message systems, video telephones, video games and electronic program guides. As those skilled in the art will appreciate, other forms of audio/video devices are contemplated within the spirit and scope of the invention. Presently preferred embodiments of other digital devices 26 for communication with the general purpose media processor 12 include personal computers, television sets. work stations, digital video camera recorders, and compact disc read-only memories. As those skilled in the art will also appreciate, further digital devices 26 are contemplated for communication to the general purpose media processor 12 without departing from the spirit and scope of the invention. Second, the general purpose media processor preferably also communicates with downstream devices over a wireless network 28. In the presently preferred embodiment of the invention, wireless devices for communication over the wireless network 28 can comprise either remote communication devices 30 or remote computing devices 32. Presently preferred embodiments of the remote communications devices 30 include cordless telephones and personal communicators. Presently preferred embodiments of the remote computing devices 32 include remote controls and telecommunicating devices. As those skilled in the art will appreciate, other forms of remote communication devices 30 and remote computing devices 32 are capable of communication with the general purpose media processor 12 without departing from the spirit and scope of the invention. An agile digital radio (not shown) that incorporates a general purpose media processor 12 may be used to communicate with these wireless devices. Network Configuration Referring now to FIG. 2. the general purpose media processor 12 is preferably disposed throughout a digital communications network 38. In order to enable communication among large and small businesses, residential customers and mobile users, the network 38 can consist of a combination of many individual sub¬ networks comprised of three main forms of interconnection. The trunk and main branches of the network 38 preferably employ fiber optic cable 40 as the preferred means of interconnection. Fiber optic cable 40 is used to connect between general purpose media processors 12 disposed as network servers 46 or large business installations 48 that are capable of coupling directly to the fiber optic link 40. For communications to small business and residential customers that may be incapable of directly coupling to the fiber optic cable 40, a general purpose media processor 12 can be used as an interface to other forms of network interconnection. As shown in FIG. 2, alternate forms of interconnection consist of coaxial cable lines 42 and twisted pair wiring 44. Coaxial cable lines are currently in place throughout the U.S. and is typically employed to provide cable television services to residential homes. According to the preferred embodiment of the invention, general purpose media processors 12 can be installed at these residential locations 52. In contrast to the specialized processor approach, the general purpose media processor 12 provides enough bandwidth to allow for bi-directional communications to and from these residential locations 52. Network servers 46 controlled by general purpose media processors 12 are also employed throughout the network 38. For example, the network servers 46 can be used to interface between the fiber optic network 40 and twisted pair wiring 44. Twisted pair wiring 44 is still employed for small businesses 50 and residential locations 52 that do not or cannot currently subscribe to coaxial cable or fiber optic network services. General purpose media processors 12 are also disposed at these small business locations 50 and non-cable residential locations 52. General purpose media processors 12 are also installed in wireless or mobile locations 52, which are coupled to the network 38 through agile digital radios (not shown). As shown in FIG. 2, network databases or other peripherals 56 can also coupled to general purpose media processors 12 in the network 38. The general purpose media processor 12 is operable at significantly high bandwidths in order to receive, process and transmit unified media data streams. Referring to FIG. 3, the respective frequencies for various types of media data streams are set forth against a bandwidth spectrum 60. The bandwidth spectrum 60 includes three component spectrums, all along the same range of frequencies, which represent the various frequency rates of digital media communications. Current computing bandwidth capabilities are also displayed. The telecommunications spectrum 62 shows the various frequency bands used for telecommunications transmission. For example, teletype terminals and modems operate in a range between approximately 64 bits/second to 16 kilobits/second. The ISDN telecommunication protocol operates at 64 kilobits/second. At the upper end of the telecommunications spectrum 62, Tl and T3 trunks operate at one megabit per second and 32 megabits per second, respectively. The SONET frequency range extends from approximately 128 megabits per second up to approximately 32 gigabits per second. Accordingly, in order to carry such broad band communications, the general purpose media processor 12 is capable of transferring information at rates into the gigabits per second range or higher. A spectrum of typical media data streams is presented in the media spectrum 64 shown in FIG. 3. Voice and music transmissions are centered at frequencies of approximately 64 kilobits per second and one megabit per second, respectively. At the upper end of the media spectrum 64, video transmission takes place in a range from 128 megabits per second for high density television up to over 256 gigabits per second for movie applications. When using common video compression techniques, however, the video transmission spectrum can be shifted down to between 32 kilobits per second to 128 megabits per second as a result of the data compression. As described below, the processing required to achieve the data compression results in an increase in bandwidth requirements. Current computing bandwidths are shown in the computing spectrum 66 of FIG. 3. Serial communications presently take place in a range between two kilobits per second up to 512 kilobits per second. The Ethernet network protocol operates at approximately 8 megabits per second. Current dynamic random access memory and other digital input/output peripherals operate between 32 megabits per second and 512 megabits per second. Presently available microprocessors are capable of operation in the low gigabits per second range. For example, the '386 Pentium microprocessor manufactured by Intel Corporation of Santa Clara. California operates in the lower half of that range, and the Alpha microprocessor manufactured by Digital Equipment Corporation approaches the 16 gigabits per second range. When video compression is employed, as expressed above, the associated processing overhead reduces the effective bandwidth of the particular processor. As a result, in order to handle compressed video, these processors must operate in the terahertz frequency range. The bandwidth spectrum 60 shown in FIG. 4 represents the effect of handling media data streams including compressed video. The computing spectrum 66 is skewed down to properly align the computing bandwidth requirements with the telecommunications spectrum 62 and the media spectrum 64. Accordingly, current processor technology is not sufficient to handle the transmission and processing associated with complex streams of multi-media data. The current specialized processor approach to media processing is illustrated in the block diagram shown in FIG. 5. As shown in FIG. 5. special purpose processors are coupled to a back plane 70, which is capable of transmitting instructions and data at the upper kilobits to lower gigabits per second range. In a typical configuration, an audio processor 76, video processor 78. graphics processor 80 and network processor 82 are all coupled to the back plane 70. Each of the audio, video, graphics and network processors 76-82 typically employ their own private or dedicated memories 84, which are only accessible to the specific processor and not accessible over the back plane 70. As described above, however, unless video data streams are constantly being processed, for example, the video processor 78 will sit idle for periods of time. The computing power of the dedicated video processor 78 is thus only available to handle video data streams and is not available to handle other media data streams that are directed to other dedicated processors. This, of course, is an inefficient use of the video processor 78 particularly in view of the overall processing capability of this multi -processor system. The general purpose media processor 12, in contrast, handles a data stream of audio, video, graphics and network information all at the same time with the same processor. In order to handle the ever changing combination of data types, the general purpose media processor 12 is dynamically partitionable to allocate the appropriate amount of processing for each combination of media in a unified media data stream. A block diagram of two preferred general purpose media processor system configurations is shown in FIG. 6. Referring to FIG. 6(a), a general purpose media processor 12 is coupled to a high-speed back plane 90. The presently preferred back plane 90 is capable of operation at 30 gigabits per second. As those skilled in the art will appreciate, back planes 90 that are capable of operation at 400 gigabits per second or greater bandwidth are envisioned within the spirit and scope of the invention. Multiple memory devices 92 are also coupled to the back plane 90, which are accessible by the general purpose media processor 12. Input/ output devices 94 are coupled to the back plane 90 through a dual-ported memory 92. The configuration of the input/ output devices 94 on one end of the dual-ported memory 92 allows the sharing of these memory devices 92 throughout a network 38 of general purpose media processors 12. Alternatively, FIG. 6(b) shows a presently preferred integrated general purpose media processor 12. The integrated processor includes on-board memory and I/O 86. The on-board memory is preferably of sufficient size to optimize throughput, and can comprise a cache and/or buffer memory or the like. The integrated media processor 12 also connects to external memory 88, which is preferably larger than the on-board memory 86 and forms the system main memory. Execution Unit One presently preferred embodiment of an integrated general purpose media processor 12 is shown in FIG. 7. The core of the integrated general purpose media processor 12 comprises an execution unit 100. Three main elements or subsections are included in the execution unit 100. A multiple precision arithmetic/ logic unit (".ALU") 102 performs all logical and simple arithmetic operations on incoming media data streams. Such operations consist of calculate and control operations such as Boolean functions, as well as addition, subtraction, multiplication and division. These operations are performed on single or unified media data streams transmitted to and from the multiple precision ALU 102 over a data bus or data path 108. Preferably the data path 108 is 128 bits wide, although those skilled in the art will appreciate that the data path 108 can take on any width or size without departing from the spirit and scope of the invention. The wider the data path 108 the more unified media data can be processed in parallel by the general purpose media processor 12. Coupled to the multi-precision ALU 102 via the data path 108, and also an element of the execution unit 100, is a programmable switch 104. The programmable switch 104 performs data handling operations on single or unified media data streams transmitted over the data path 108. Examples of such data handling operations include deals, shuffles, shifts, expands, compresses, swizzles, permutes and reverses, although other data handling operations are contemplated. These operations can be performed on single bits or bit fields consisting of two or more bits up to the entire width of the data path 108. Thus, single bits or bit fields of various sizes can be manipulated through programmable operation of the switch 104. Examples of the presently preferred data manipulation operations performed by the general puipose media processor 12 are shown in FIG. 8. A group expand operation is visually illustrated in FIG. 8(a). According to the group expand operation, a sequential field of bits 270 can be divided into constituent sub-fields 272a-272d for insertion into a larger field array 274. The reverse of the group expand operation is a group compress or extract operation. A visual illustration of the group compress or extract operation is shown in FIG. 8(b). As shown, separate sub- fields 272a-272d from a larger bit field 274 can be combined to form a contiguous or sequential field of bits 270. Referring to FIGS. 8(c)-8(e), group deal, shuffle, swizzle and permute operations performed by the programmable switch 104 are also illustrated. The operations performed by these instructions are readily understood from a review of the drawings. The group manipulation operations illustrated in FIGS. 8(a)-8(e) comprise the presently contemplated data manipulation operations for the general puφose media processor 12. As those skilled in the art will appreciate, either a subset of these operations or additional data manipulation operations can be incoφorated in other alternate embodiments of the general puφose media processor 12 without departing from the spirit and scope of the invention. Refening again to FIG. 7, higher level mathematical operations than those performed by the multi-precision ALU 102 are performed in the general puφose media processor 12 through an extended math element 106. The extended math element 106 is coupled to the data path 108 and also comprises part of the execution unit 100. The extended math element 106 performs the complex arithmetic operations necessary for video data compression and similarly intensive mathematical operations. One presently preferred example of an extended math operation comprises a Galois field operation. Other examples of extended mathematical functions performed by the extended math element 106 include CRC generation and checking, Reed-Solomon code generation and checking, and spread-spectrum encoding and decoding. As those skilled in the art appreciate. additional mathematical operations are possible and contemplated. According to the preferred embodiment of the integrated general puφose media processor 12, a register file 110 is provided in addition to the execution unit 100 to process media data. The register file 110 stores and transmits data streams to and from the execution unit 100 via the data path 108. Rather than employing a complex set of specific or dedicated registers, the general puφose media processor 12 preferably includes 64 general puφose registers in the register file 110 along with one program counter (not shown). The 64 general puφose registers contained in the register file 110 are all available to the user/programmer, and comprise a portion of the user state of the general puφose media processor 12. The general puφose registers are preferably capable of storing any form of data. Each register within the register file 110 is coupled to the data path 108 and is accessible to the execution unit 100 in the same manner. Thus, the user can employ a general puφose register according to the specific needs of a particular program or unique application. As those skilled in the art will appreciate, the register file 110 can also comprise a plurality of register files 110 configured in parallel in order to support parallel multi-threaded processing. Instruction Set and User Programming Control or manipulation of data processed by the general puφose media processor 12 is achieved by selected instructions programmed by the user. Those skilled in the art will appreciate that a great number of programs are possible through various sequences of instructions. Particular programs can be developed for each unique implementation of the general puφose media processor 12. A detailed discussion of such specific programs is therefore beyond the scope of this description. One presently preferred instruction set for the general puφose media processor 12 is included in the Microfiche Appendix, the contents of which are hereby incoφorated herein by reference. A list of the presently preferred major operation codes for the general puφose media processor 12 appears below in Table I. 97/07450 MAJOR OPERATION CODES major operation code field values TABLE I As shown in Table I, the major operation codes are grouped according to the function performed by the operations. The operations are thus arranged and listed above according to the presently preferred operation code number for each instruction. As many as 255 separate operations are contemplated for the preferred embodiment of the general puφose media processor 12. As shown in Table I, however, not all of the operation codes are presently implemented. As those skilled in the art will appreciate, alternate schemes for organizing the operation codes, as well as additional operation codes for the general puφose media processor 12, are possible. The instructions provided in the instruction set for the general puφose media processor 12 control the transfer, processing and manipulation of data streams between the register file 110 and the execution unit 100. The presently preferred width of the instruction path 112 is 32-bits wide, organized as four eight-bit bytes ("quadlets"). Those skilled in the an will appreciate, however, that the instruction path 112 can take on any width without departing from the spirit and scope of the invention. Preferably, each instruction within the instruction set is stored or organized in memory on four-byte boundaries. The presently preferred format for instructions is shown in FIG. 9(a). As shown in FIG. 9(a), each of the presently preferred instruction formats for the general puφose media processor 12 includes a field 280 for the major operation code number shown in Table I. Based on the type of operation performed, the remaining bits can provide additional operands according to the type of addressing employed with the operation. For example, the remainder of the 32-bit instruction field can comprise an immediate operand ("imm"), or operands stored in any of the general registers ("ra," "rb," "re," and "rd"). In addition, minor operation codes 282 can also be included among the operands of certain 32-bit instruction formats. The presently preferred embodiment of the general puφose media processor 12 includes a limited instruction set similar to those seen in Reduced Instruction Set Computer ("RISC") systems. The preferred instruction set for the general puφose media processor 12 shown in Table I includes operations which implement load, store, synchronize, branch and gateway functions. These five groups of operations can be visually represented as two general classes of related operations. The branch and gateway operations perform related functions on media data streams and are thus visually represented as block 114 in FIG. 7. Similarly, the load, store and synchronize operations are grouped together in block 116 and perform similar operations on the media data streams. (Blocks 114 and 116 only represent the above classification of these operations and their function in the processing of media data streams, and do not indicate any specific underlying electronic connections.) A more detailed discussion of these operations, and the functionality of the general puφose media processor 12, appears in the Microfiche Appendix. The four-byte structure of instructions for the general puφose media processor 12 is preferably independent of the byte ordering used for any data structures. Nevertheless, the gateway instructions are specifically defined as 16- byte structures containing a code address used to securely invoke a procedure at a higher privilege level. Gateways are preferably marked by protection information specified in the translation lookaside buffer 148 in the memory management unit 122. Gateways are thus preferably aligned on 16-byte boundaries in the external memory. In addition to the general puφose registers and program counter, a privilege level register is provided within the register file 110 that contains the privilege level of the currently executing instruction. The instruction set preferably includes load and store instructions that move data between memory and the register file 110, branch instructions to compare the content of registers and transfer control, and arithmetic operations to perform computations on the contents of registers. Swap instructions provide multi-thread and multi-processor synchronization. These operations are preferably indivisible and include such instructions as add-and-swap, compare-and-swap. and multiplex-and-swap instructions. The fixed-point compare-and-branch instructions within the instruction set shown in Table I provide the necessary arithmetic tests for equality and inequality of signed and unsigned fixed-point values. The branch through gateway instruction provides a secure means to access code at a higher privileged level in a form similar to a high level language procedure call generally known in the art. The general purpose media processor 12 also preferably supports floating-point compare-and-branch instructions. The arithmetic operations, which are supported in hardware, include floating-point addition, subtraction, multiplication, division and square root. The general puφose media processor 12 preferably supports other floating-point operations defined by the ANSI-IEEE floating-point standard through the use of software libraries. A floating point value can preferably be 16. 32, 64 or 128-bits wide. Examples of the presenting preferred floating-point data sizes are illustrated in FIG. 9(b). The general puφose media processor 12 preferably supports virtual memory addressing and virtual machine operation through a memory management unit 122. Referring to FIG. 10(a), one presently preferred embodiment of the memory management unit 122 is shown. The memory management unit 122 preferably translates global virtual addresses into physical addresses by software programmable routines augmented by a hardware translation lookaside buffer ("TLB") 148. A facility for local virtual address translation 164 is also preferably provided. As those skilled in the art will appreciate, the memory management unit 122 includes a data cache 166 and a tag cache 168 that store data and tags associated with memory sections for each entry in the TLB 148. A block diagram of one preferred embodiment of the TLB 148 is shown in FIG. 10(b). The TLB 148 receives a virtual address 230 as its input. For each entry in the TLB 148, the virtual address 230 is logically AND-ed with a mask 232. The ouφut of each respective AND gate 234 is compared via a comparator 236 with each entry in the TLB 148. If a match is detected, an ouφut from the comparator 236 is used to gate data 240 through a transceiver 238. As those skilled in the art will appreciate, a match indicates the entry of the corresponding physical address within the contents of the TLB 148 and no external memory or I/O access is required. The data 240 for the data cache 166 (FIG. 10(a)) is then combined with the remaining lower bits of the virtual address 230 through an exclusive-OR gate 242. The resultant combination is the physical address 244 ouφut from the TLB 148. If a match is not detected between the logical address and the contents of the tag cache 168, the memory management unit 122 an external memory or I/O access is necessary to retrieve the relevant portion of memory and update the contents of the TLB 148 accordingly. Using generally known memory management techniques, the memory management unit 122 ensures that instructions (and data) are properly retrieved from external memory (or other sources) over an external input/ouφut bus 126 (see FIG. 7). As described in more detail below, a high bandwidth interface 124 is coupled to the external input/ouφut bus 126 to communicate instructions (and media data streams) to the general puφose media processor 12. The presently preferred physical address width for the general puφose media processor 12 is eight bytes (64-bits). In addition, the memory management unit 122 preferably provides match bits (not shown) that allow large memory regions to be assigned a single TLB entry allowing for fine grain memory management of large memory sections. The memory management unit 122 also preferably includes a priority bit (not shown) that allows for preferential queuing of memory areas according to respective levels of priority. Other memory management operations generally known in the an are also performed by the memory management unit 122. Referring again to FIG. 7, instructions received by the general puφose media processor 12 are stored in a combined instruction buffer/cache 118. The instruction buffer/cache 118 is dynamically subdivided to store the largest sequence of instructions capable of execution by the execution unit 100 without the necessity of accessing external memory. In a preferred embodiment of the invention, instruction buffer space is allocated to the smallest and most frequently executed blocks of media instructions. The instruction buffer thus helps maintain the high bandwidth capacity of the general puφose media processor 12 by sustaining the number of instructions executed per second at or near peak operation. That portion of the instruction buffer/cache 118 not used as a buffer is, therefore, available to be used as cache memory. The instruction buffer/cache 118 is coupled to the instruction path 112 and is preferably 32 kilobytes in size. A data buffer/ cache 120 is also provided to store data transmitted and received to and from the execution unit 100 and register file 110. The data buffer/cache 120 is also dynamically subdivided in a manner similar to that of the instruction buffer/cache 118. The buffer portion of the data buffer/cache 120 is optimized to store a set size of unified media data capable of execution without the necessity of accessing external memory. In a preferred embodiment of the invention, data buffer space is allocated to the smallest and most frequently accessed working sets of media data. Like the instruction buffer, the data buffer thus maintains peak bandwidth of the general puφose media processor 12. The data buffer/cache 120 is coupled to the data path 108 and is preferably also 32 kilobytes in size. The preferred embodiment of the general puφose media processor 12 includes a pipelined instruction pre-fetch structure. Although pipelined operation is supported, the general puφose media processor 12 also allows for non-pipelined operations to execute without any operational penalty. One preferred pipeline structure for the general puφose media processor 12 comprises a "super-string" pipeline shown in FIG. 11. A super-string pipeline is designed to fetch and execute several instructions in each clock cycle. The instructions available for the general puφose media processor 12 can be broken down into five basic steps of operation. These steps include a register-to- register address calculation, a memory load, a register-to-register data calculation, a memory store and a branch operation. According to the super-string pipeline organization of the general puφose media processor 12, one instruction from each of these five types may be issued in each clock cycle. The presently preferred ordering of these operations are as listed above where each of the five steps are assigned letters "A," "L," "E," "S" and "B" (see FIG. 11). According to the super- string pipelining technique, each of the instructions are serially dependent, as shown in FIG. 11 , and the general puφose media processor 12 has the ability to issue a string of dependent instructions in a single clock cycle. These instructions shown in FIG. 11 can take from two to five cycles of latency to execute, and a branch prediction mechanism is preferably used to keep up the pipeline filled (described below). Instructions can be encoded in unit categories such as address, load, store/sync, fixed, float and branch to allow for easy decoding. A similar scheme is employed to pre-fetch data for the general puφose media processor 12. As those skilled in the art will appreciate, the super-string pipeline can be implemented in a multi-threaded environment. In such an implementation, the number of threads is preferably relatively prime with respect to functional unit rates so that functional units can be scheduled in a non-interfering fashion between each thread. In another more preferred embodiment, a "super-spring" pipelining scheme is employed with the general puφose media processor 12. The super- spring pipeline technique breaks the super-string pipeline shown in FIG. 11 into two sections that are coupled via a memory buffer (not shown). A visual representation of the super-φring pipeline technique is shown in FIG. 12. The front of the pipeline 204. in which address calculation (A), memory load (L). and branch (B) operations are handled, is decoupled from the back of the pipeline 206, in which data calculation (E) and memory store (S) operations are handled. The decoupling is accomplished through the memory buffer (not shown), which is preferably organized in a first-in-first-out ("FIFO") fast/dense structure. (The memory buffer is functionally represented as a spring in FIG. 12.) As indicated in Table I above, the general puφose media processor 12 does not include delayed branch instructions, and so relies upon branch or fetch prediction techniques to keep the pipeline full in program flows around unconditional and conditional branch instructions. Many such techniques are generally known in the art. Examples of some presently preferred techniques include the use of group compare and set, and multiplex operations to eliminate unpredictable branches; the use of short forward branches, which cause pipeline neutralization; and where branch and link predicts the return address in a one or more entry stack. In addition, the specialized gateway instructions included in the general puφose media processor 12 allow for branches to and from protected virtual memory space. The gateway instructions, therefore, allow an efficient means to transfer between various levels of privilege. As described above, two basic forms of media data are processed by the general puφose media processor 12, as shown in FIG. 7. These data streams generally comprise Nyquist sampled I/O 128, and standard memory and I/O 130. As shown in FIG. 7, audio 132, video 134, radio 136, network 138, tape 140 and disc 142 data streams comprise some examples of digitally sampled I/O 128. As those skilled in the art will appreciate, other forms of digitally sampled I/O are contemplated for processing by the general puφose media processor 12 without departing from the spirit and scope of the invention. Standard memory and I/O 130 comprises data received and transmitted to and from general digital peripheral devices used in the design of most computer systems. As shown in FIG. 7. some examples of such devices include dynamic random access memory ("DRAM") 146, or any data received over the PCI bus 144 generally known in the an. Other forms of standard memory and I O sources are also contemplated. The various fixed-point data sizes preferred for the general puφose media processor 12 are illustrated in FIG. 9(c). External Interface As mentioned above, the general puφose media processor 12 includes a high bandwidth interface 124 to communicate with external memory and input/ouφut sources. As pan of the high bandwidth interface 124, the general puφose media processor 12 integrates several fast communication channels 156 (FIG. 13) to communicate externally. These fast communication channels 156 preferably couple to external caches 150, which serve as a buffer to memory interfaces 152 coupled to standard memory 154. The caches 150 preferably comprise synchronous static random access memory ("SRAM"), each of which are sixty-four kilobytes in size; and the standard memories 154 comprise DRAM's. The memory interfaces 152 transmit data between the caches 150 and the standard memories 154. The standard memories 154 together form the main external memory for the general puφose media processor 12. The cache 150, memory interface 152, standard memory 154 and input/ouφut channel 156 therefore make up a single external memory unit 158 for the general puφose media processor 12. According to the presently preferred embodiment of the invention, the memory interface protocol embeds read and write operations to a single memory space into packets containing command, address, data and acknowledgment information. The packets preferably include check codes that will detect single-bit transmission errors and some multiple-bit errors. As many as eight operations may be in progress at a time in each external memory unit 158. As shown in FIG. 13, up to four external memory units 158 may be cascaded together to expand the memory available to the general puφose media processor 12, and to improve the bandwidth of the external memory. Through such cascaded memory units 158, the memory interface 152 provides for the direct connection of multiple banks of standard memory 154 to maintain operation of the general puφose media processor 12 at sustained peak bandwidths. According to one embodiment shown in FIG. 13, up to four standard memory devices 154 can be coupled to each memory interface 152. Each standard memory 154 thus includes as many as four banks of DRAM, each of which is preferably sixteen bits wide. The standard memories 154 are connected in parallel to the memory interface 152 forming a 72-bit wide data bus 160, where 64 bits are preferably provided for data transfer and eight bits are provided for error correction. In addition to the data bus 160, an address/control bus 162 is coupled between the memory interface 152 and each standard memory 154. The address/control bus 162 preferably comprises at least twelve address lines (4 kilobits x 16 memory size) and four control lines as shown in FIG. 13. An alternate manner for coupling the DRAM's to the memory interface 152 is illustrated in FIG. 14. As shown in FIG. 14, two banks of four DRAM single in¬ line memory modules are coupled in parallel to the memory interface 152. The memory interface 152 also supports interleaving to enhance bandwidth, and page mode accesses to improve latency for localized addressing. Using standard DRAM components, the external memory units 158 achieve bandwidths of approximately two gigabits/second with the standard memories 154. When four such external memory units 158 are coupled via the communication channel 156, therefore, the total bandwidth of the external main memory system increases to one gigabyte/ second. As discussed further below, in implementations with two or eight communication channels 156, the aggregate bandwidth increases to two and eight gigabytes/second, respectively. A more detailed depiction of the communication channel 156 circuitry appears in FIG. 15. According to the preferred embodiment of the invention, each communication channel 156 comprises two unidirectional, byte- wide, differential, packet-oriented data channels 156a, 156b (see FIG. 13). As explained above, where memory units 158 are cascaded together in series, the ouφut of one memory unit 158 is connected to the input of another memory unit 158. The two unidirectional channels are thus connected through the memory units 158 forming a loop structure and make up a single bi-directional memory interface channel. Referring to FIG. 15. each communication channel 156 is preferably eight bits wide, and each bit is transmitted differentially. For example, ouφut transceiver 170 for bit D^, transmits both D 0 and /D 0 signals over the communication channel 156. Additional transceivers are similarly provided for the remaining bits in the channel 156. (The transceiver 176 for bit D 7ouI and associated differential lines 178. 180 are shown in FIG. 15.) A CLK 0Ut transceiver 182 is also provided to generate differential clock ouφuts 184, 186 over the channel 156. To complete the link between memory units 158, input transceivers 188-192 are provided in each memory unit 158 for each of the differential bits and clock signals transmitted over the commumcation channel 156. These input signals 172, 174, 178, 180, 184, 186 are preferably transmitted through input buffers 194-198 to other parts of the memory unit 158 (described above). Each memory unit 158 also includes a skew calibrator 200 and phase locked loop ("PLL") 202. The skew calibrator 200 is used to control skew in signals ouφut to the commumcation channel 156. Preferably, digital skew fields are employed, which include set numbers of delay stages to be inserted in the ouφut path of the communication channel 156. Setting these fields, and the corresponding analog skew fields, permits a fine level of control over the relative skew between ouφut channel signals. The PLL 202 recovers the clock signal on either side of the communication channel 156 and is thus provided to remove clock jiner. The clock signals 184, 186 preferably comprise a single phase, constant rate clock signal. The clock signals 184, 186 thus contain alternating zero and one values transmitted with the same timing as the data signals 172, 174, 178, 180. The clock signal frequency is, therefore, one-half the byte data rate. The communication channel 156 preferably operates at constant frequency and contains no auxiliary control, handshaking or flow control information. Each external memory unit 158 preferably defines two functional regions: a memory region, implemented by the c'ache 150 backed by standard memory 154 (see FIG. 13), and a configuration region, implemented by registers (not shown). Both regions are accessed by separate interfaces; the communication channel 156 is used to access the memory region, and a serial interface (described below) is used to access the configuration region. In the memory region, the caches 150 are preferably write-back (write-in) single-set (direct-map) caches for data originally contained in standard memory 154. All accesses to memory space should maintain consistency between the contents of the cache 150 and the contents of the standard memory 154. The configuration region registers provide the mechanism to detect and adjust skew in the communication channel 156. Software is preferably employed to adaptively adjust the skew in the channel 156 through digital skew fields, as explained above. The serial interface thus is used to configure the external memory units 158, set diagnostic modes and read diagnostic information, and to enable the use of a high-speed tester (not shown). One presently preferred embodiment of the invention employs two byte-wide packet communication channels 156 (FIG. 16(a)). In order to further increase the bandwidth of the general puφose media processor 12, up to sixteen byte-wide packet communication channels 156 can be employed. Referring to FIG. 16(b), twelve communication channels, comprising eight memory channels 210, a ninth channel for parallel processing 212 (described below), and three input ouφut ("I/O") channels 214, are shown. Each of the commumcation channels 210-214 preferably employs the cascade configuration of four channel interface devices 216. (Each channel interface device 216 coupled to the memory channels 210 corresponds to the external memory unit 158 shown in FIG. 13.) Through each of the twelve communication channels shown in FIG. 16(b), the general puφose media processor 12 can request or issue read or write transactions. When not interleaved, the twelve channels provide a single contiguous memory space for each channel interface device 216. Alternatively, memory accesses may be interleaved in order to provide for continuous access to the external memory system at the maximum bandwidth for the DRAM memories. In an interleaved configuration, at any point in time some memory devices will be engaged in row pre-charge, while others may be driving or receiving data, or receiving row or column addresses. The memory interface 152 (FIG. 13) thus preferably maps between a contiguous address space and each of the separate address spaces made available within each external memory unit 158. For maximum performance, therefore, the memory interface is interleaved so that references to adjacent addresses are handled by different memory devices. Moreover, in the preferred embodiment, additional memory operations may be requested before the corresponding DRAM bank is available. In ah interleaved approach, these operations are placed in a queue until they can be processed. According to the preferred embodiment, memory writes have lower priority than memory reads, unless an attempt is made to read an address that is queued for a write operation. As those skilled in the art will appreciate, the depth of the memory write queue is dictated by the specific implementation. Although up to four external memory units 158 are preferably cascaded to form effectively larger memories, some amount of latency may be introduced by the cascade. Packets of data transmitted over the communication channel 156 are uniquely addressed to a particular channel interface device 216. A packet received at a particular device, which specifies another module address, is automatically passed to the correct channel interface device 216. Unless the module address matches a particular device 216, that packet simply passes from the input to the ouφut of the interface device 216. This mechanism divides the serial interconnection of interface devices 216 into strings, which function as a single larger memory or peripheral, but with possibly longer response latency. In addition to the memory channels 210, the general puφose media processor 12 provides several communication channels 214 for communication with external input/ouφut devices. Referring to FIG. 16(b), three input/ouφut channels 214 having SRAM buffered memory (see FIG. 13) provide an interface to external standard I/O devices (not shown). Like the eight memory channels 210, the three I/O channels 214 are byte-wide input/ouφut channels intended to operate at rates of at least one gigahertz. The three I/O channels 214 also operate as a packet communication link to synchronous SRAM memory 208 within the channel interface device 216. A controller 226 within the channel interface device 216 completes the interface to the I/O devices. The three I/O channels 214 preferably function in like manner to the memory channels 210 described above. The interface protocol for the three I/O channels 214 divides read and write operations to a single memory space into packets containing command, address, data and acknowledgment information. The packets also include a check code that will detect single-bit transmission errors and some multiple-bit errors. According to the preferred embodiment of the invention, as many as eight operations may progress in each interface device 216 at a time. As shown in FIG. 16(b), up to four channel interface devices 216 can be cascaded together to expand the bandwidth in the three I/O channels 214. A bit-serial interface (not shown) is also provided to each of the channel interface devices 216 to allow access to configuration, diagnostic and tester information at standard TTL signal levels at a more moderate data rate. (A more detailed description of the serial interface is provided below). Like the memory channels 210. each I/O channel 214 includes nine signals - one clock signal and eight data signals. Differential voltage levels are preferably employed for each signal. Each channel interface device 216 is preferably terminated in a nominal 50 ohm impedance to ground. This impedance applies for both inputs and ouφuts to the communication channel 156. A programmable termination impedance is preferred. Interface Communication According to one presently preferred embodiment of the invention, the channel interface devices 216 can operate as either master devices or slave devices. A master device is capable of generating a request on the communication channel 156 and receiving responses from the communication channel 156. Slave devices are capable of receiving requests and generating responses, over the communication channel 156. A master device is preferably capable of generating a constant frequency clock signal and accepting signals at the same clock frequency over the communication channel 156. A slave device, therefore, should operate at the same clock rate as the communication channel 156, and generate no more than a specified amount of variation in ouφut clock phase relative to input clock phase. The master device, however, can accept an arbitrary input clock phase and tolerates a specified amount of variation in clock phase over operating conditions. Packets of information sent over the communication channel 156 preferably contain control commands, such as read or write operations, along with addresses and associated data. Other commands are provided to indicate error conditions and responses to the above commands. When the commumcation channel 156 is idle, such as during initialization and between transmitted packets, an idle packet, consisting of an all-zero byte and an all- one byte is transmitted through the communication channel 156. Each non-idle packet consists of two bytes or a multiple of two bytes, and begins with a byte having a value other than all zeros. All packets transmitted over the communication channel 156 also begin during a clock period in which the clock signal is zero, and all packets preferably end during a clock period in which the clock signal is one. A depiction of the preferred packet protocol format for transmission over the communication channel 156 appears in FIG. 17. The general form of each packet is an array of bytes preferably without a specific byte ordering. The first byte contains a module address 250 ("ma") in the high order two bits; a packet identifier, usually a command 252 ("com"), in the next three bit positions; and a link identification number 254 ("lid") in the last three bit positions. The inteφretation of the remaining bytes of a packet depend upon the contents of the packet identifier. The length of each packet is preferably implied by the command specified in the initial byte of the packet. A check byte is provided and computed as odd bit-wise parity with a leftward circular rotation after accumulating each byte. This technique provides detection of all single-bit and some multiple-bit errors, but no correction is provided. The modular address 250 field of each packet is preferably a two-bit field and allows for as many as four slave devices to be operated from a single communication channel 156. Module address values can be assigned in one of two fashions: either dynamically assigned through a configuration register (not shown), or assigned via static/geometric configuration pins. Dynamic assignment through a configuration register is the presently preferred method for assigning module address values. The link identification number 254 field is preferably 3-bits wide and provides the opportunity for master devices to initiate as many as eight independent operations at any one time to each slave device. Each outstanding operation requires a distinct link identification number, but no ordering of operations should be implied by the value of the link identification field. Thus. there is preferably no requirement for link identification values 254 to be sequentially assigned either in requests or responses. The receipt of packets over the communication channel 156 that do not conform to the channel protocol preferably generates an error condition. As those skilled in the art will appreciate, the level or degrees to which a specific implementation detects errors is defined by the user. In one presently preferred embodiment of the invention, all errors are detected, and the following protocol is employed for handling errors. For each error detected, the chaimel interface device 216 causes a response explicitly indicating the error condition. Channel interface devices 216 reporting an invalid packet will then suppress the receipt of additional packets until the error is cleared. The transmitted packet is otherwise ignored. However, even though the erroneous packet is ignored, the channel interface devices 216 preferably continue to process valid packets that have already been received and generate responses thereto. An identification of the presently preferred commands 252 to be used over the communication channel 156 are listed in FIG. 17. In the master/slave preferred embodiment, the channel interface devices 216 forward packets that are intended for other devices connected to the communication channel 156. as described above. In slave devices, forwarding is performed based on the module address 250 field of the packet. Packets which contain a module address 250 other than that of the current device are forwarded on to the next device. All non-idle packets are thus forwarded including error packets. In master devices, forwarding is performed based on the link identifier number 254 of the packet. Packets that contain link identifier numbers 254 not generated by the specific channel interface device 216 are forwarded. In order to reduce transmission latency, a packet buffer may be provided. As those skilled in the art appreciate, the suitable size for the packet buffer depends on the amount of latency tolerable in a particular implementation. A variety of master/slave ring configurations are possible using the high bandwidth interface 124 of the invention. Five ring configurations are currently preferred: single-master, dual-master, multiple-master, single-slave and multiple-master/multiple-slave. The simplest ring configuration contains a single non- forwarding master device and a single non-forwarding slave device. No forwarding is required for either device in this configuration as packets are sent directly to the recipient. A single-master ring, however, may contain a cascade of up to four slave devices (see FIGS. 13, 16). In the single-master ring configuration, each slave device is configured to a distinct module address, and each slave device forwards packets that contain module address fields unequal to their own. As discussed above, a single-master ring provides a larger memory or I/O capacity than a master-slave pair, but also introduces a potentially longer response latency. In the single -master ring, each slave device may have as many as eight transactions outstanding at any time, as described above. The remaining combinations share many of the above basic attributes. In a dual-master pair, each master device may initiate read and write operations addressed to the other, and each may have up to eight such transactions outstanding. No forwarding is required for either device because packets are sent directly to the recipient. A multiple-master ring may contain multiple master devices and a single slave device. In this configuration, the slave device need not forward packets as all input packets are designated for the single slave device. A multiple-master ring may contain multiple master devices and as many as four slave devices. Each slave device may have up to eight transactions outstanding, and each master device may use some of those transactions. In a preferred embodiment, a master also has the capability to detect a time-out condition or when a response to a request packet is not received. Further aspects of inter- processor communications and configurations are discussed below in connection with FIG. 18. Serial Bus In one preferred embodiment of the invention, the general puφose media processor 12 includes a serial bus (not shown). The serial bus is designed to provide bootstrap resources, configuration, and diagnostic support to the general puφose media processor 12. The serial bus preferably employs two signals, both at TTL levels, for direct commumcation among many devices. In the preferred embodiment, the first signal is a continuously running clock, and the second signal is an open-collector bi-directional data signal. Four additional signals provide geographic addresses for each device coupled to the serial bus. A gateway protocol, and optional configurable addressing, each provide a means to extend the serial bus to other buses and devices. Although the serial bus is designed for implementation in a system having a general puφose media processor 12. as those skilled in the art will appreciate, the serial bus is applicable to other systems as well. Because the serial bus is preferably used for the initial bootstrap program load of the general purpose media processor 12, the bootstrap ROM is coupled to the serial bus. As a result, the serial bus needs to be operational for the first instruction fetch. The serial bus protocol is therefore devised so that no transactions are required for initial bus configuration or bus address assignment. According to the preferred embodiment, the clock signal comprises a continuously running clock signal at a minimum of 20 megahertz. The amount of skew, if any, in the clock signal between any two serial bus devices should be limited to be less than the skew on the data signal. Preferably, the serial data signal is a non-inverted open collector bi-directional data signal. TTL levels are preferred for communication on the serial bus, and several termination networks may be employed for the serial data signal. A simple preferred termination network employs a resistive pull-up of 220 ohms to 3.3 volts above V„. An alternate embodiment employs a more complex termination network such as a termination network including diodes or the "Forced Perfect Termination" network proposed for the SCSI-2 standard, which may be advantageous for larger configurations. The geographic addressing employed in the serial bus is provided to insure that each device is addressable with a number that is unique among all devices on the bus and which also preferably reflects the physical location of the device. Thus, the address of each device remains the same each time the system is operated. In one preferred embodiment, the geographic address is composed of four bits, thus allowing for up to 16 devices. In order to extend the geographic addressing to more than 16 devices, additional signals may be employed such as a buffered copy of the clock signal or an inverted copy of the clock signal (or both). The serial bus preferably incoφorates both a bit level and packet protocol. The bit level protocol allows any device to transmit one bit of information on the bus, which is received by all devices on the bus at the same time. Each transmitted bit begins at the rising edge of the clock signal and ends at the next rising edge. The transmitted bit value is sampled at the next rising edge of the clock signal. According to one preferred embodiment where the serial data signal is an open collector signal, the transmission of a zero bit value on the bus is achieved by driving the serial data signal to a logical low value. In this embodiment, the transmission of a one bit value is achieved by releasing the serial data signal to obtain a logical high value. If more than one device attempts to transmit a value on the same clock, the resulting value is a zero if any device transmits a zero value, and one if all devices transmit a one value. This provides a "wired-AND" collision mechanism, as those skilled in the art will appreciate. If two or more devices transmit the same value on the same clock cycle, however, no device can detect the occurrence of a collision. In such cases, the transaction, which may occur frequently in some implementations, preferably proceeds as described below. The packet protocol employed with the serial bus uses the bit level protocol to transmit information in units of eight bits or multiples of eight bits. Each packet transmission preferably begins with a start bit in which the serial data signal has a zero (driven) value. After transmitting the eight data bits, a parity bit is transmitted. The transmission continues with additional data. A single one (released) bit is transmitted immediately following the least significant bit of each byte signaling the end of the byte. On the cycle following the transmission of the parity bit, any device may demand a delay of two cycles to process the data received. The two cycle delay is initiated by driving the serial data signal (to a zero value) and releasing the serial data signal on the next cycle. Before releasing the serial data signal, however, it is preferable to insure that the signal is not being driven by any other device. Further delays are available by repeating this pattern. In order to avoid collisions, a device is not permitted to start a transmission over the serial bus unless there are no currently executing transactions. To resolve collisions that may occur if two devices begin transmission on the same cycle, each transmitting device should preferably monitor the bus during the transmission of one (released) bits. If any of the bits of the byte are received as zero when transmitting a one, the device has lost arbitration and must cease transmission of any additional bits of the current byte or transaction. According to the preferred embodiment of the invention, a serial bus transaction consists of the transmission of a series of packets. The transaction begins with a transmission by the transaction initiator, which specifies the target network, device, length, type and payload of the transaction request. The transaction terminates with a packet having a type field in a specified range. As a result, all devices connected to the serial bus should monitor the serial data signal to determine when transactions begin and end. A serial bus network may have multiple simultaneous transactions occurring, however, so long as the target and initiator network addresses are all disjoint. Parallel Processing In one preferred embodiment of the invention, two or more general puφose media processors 12 can be linked together to achieve a multiple processor system. According to this embodiment, general puφose media processors 12 are linked together using their high bandwidth interface channels 124, either directly or through external switching components (not shown). The dual-master pair configuration described above can thus be extended for use in multiple-master ring configurations. Preferably, internal daemons provide for the generation of memory references to remote processors, accesses to local physical memory space, and the transport of remote references to other remote processors. In a multi-processor environment, all general puφose media processors 12 run off of a common clock frequency, as required by the communication channels 156 that connect between processors. Referring to FIG. 18, each general puφose media processor 12 preferably includes at least a pair of inter-processor links 218 (see also FIG. 16(b)). In one configuration, both pairs of inter-processor links 218 can be connected between the two processors 12 to further enhance bandwidth. As shown in FIG. 18(a) several processors 12 may be interconnected in a linear network employing the transponder daemons in each processor. In an alternate embodiment shown in FIG. 18(b), the inter-processor links 218 may be used to join the general puφose media processors 12 in a ring configuration. Alternatively still, general puφose media processors 12 may be interconnected into a two-dimensional network of processors of arbitrary size, as shown in FIG. 18(c). Sixteen processors are connected in FIG. 18(c) by connecting four ring networks. In yet another alternate embodiment, by connecting the inter-processor links 218 to external switching devices (not shown), multi-processors with a large number of processors can be constructed with an arbitrary interconnection topology. The requester, responder and transponder daemons preferably handle all inter-processor operations. When one general puφose media processor 12 attempts a load or store to a physical address of a remote processor, the requester daemon autonomously attempts to satisfy the remote memory reference by communicating with the external device. The external device may comprise another processor 12 or a switching device (not shown) that eventually reaches another processor 12. Preferably, two requester daemons are provided each processor 12. which act concurrently on two different byte channels and/or module addresses. The responder daemon accepts writes from a specified channel and module address, which enables an external device to generate transaction requests in local memory or to generate processor events. The responder daemon also generates link level writes to the same external device that communicated responses for the received transaction request. Two such responder daemons are preferably provided; each of which operate concurrently to two different byte channels and/or module addresses. The transponder daemon accepts writes from a specified channel and module address, which enable an external device to cause a requester daemon to generate a request on another channel and module address. Preferably, two such transponder daemons are provided, each of which act concurrently (back-to-back) between two different byte channel and/or module addresses. As those skilled in the art will appreciate, the requester, responder and transponder daemons must act cooperatively to avoid deadlock that may arise due to an imbalance of requests in the system. Deadlocks prevent responses from being routed to their destinations, which may defeat the benefits of a multi-processor distributed system. According to one presently preferred embodiment of the invention, the general puφose media processor 12 can be implemented as one or more integrated circuit chips. Referring to FIG. 19, the presently preferred embodiment of the general puφose media processor 12 consists of a four-chip set. In the four- chip set, a general puφose media processor 12 is manufactured as a stand alone integrated circuit. The stand alone integrated circuit includes a memory management unit 122, instruction and data cache/buffers 118. 120, and an execution unit 100. A plurality of signal input/ouφut pads 260 are provided around the circumference of the integrated circuit to communicate signals to and from the general puφose media processor 12 in a manner generally known in the art. The second and third chips of the four-chip set comprise in an external memory element 158 and a channel interface device 216. The external memory element 158 includes an interface to the communication channel 156. a cache 150 and a memory interface 152. The channel interface device 216 also includes an interface to the communication channel 156, as well as buffer memory 262, and input/ouφut interfaces 264. Both the external memory element 158 and the channel interface device 216 include a plurality of input/ouφut signal pads 260 to communicate signals to and from these devices in a generally known manner. The fourth integrated circuit chip comprises a switch 226, which allows for installation of the general puφose media processor 12 in the heterogeneous network 38. In addition to the plurality of input/ouφut pads 260, the switch 226 includes an interface to the communication channel 156. The switch 226 also preferably includes a buffer 262, a router 266, and a switch interface 268. As those skilled in the art will appreciate, many implementations for the general puφose media processor 12 are possible in addition to the four-chip implementation described above. Rather than an integrated approach, the general puφose media processor can be implemented in a discrete manner. Alternatively, the general puφose media processor 12 can be implemented in a single integrated circuit, or in an implementation with fewer than four integrated circuit chips. Other combinations and permutations of these implementations are contemplated. There has been described a system for processing streams of media data at substantially peak rates to allow for real time communication over a large heterogeneous network. The system includes a media processor at its core that is capable of processing such media data streams. The heterogeneous network consists of, for example, the fiber optic/coaxial cable/twisted wire network in place throughout the U.S. To provide for such communication of media data, a media processor according to the invention is disposed at various locations throughout the heterogeneous network. The media processor would thus function both in a server capacity and at an end user site within the network. Examples of such end user sites include televisions, set-top converter boxes, facsimile machines, wireless and cellular telephones, as well as large and small business and industrial applications. To achieve such high rates of data throughput, the media processor includes an execution unit, high bandwidth interface, memory management unit, and pipelined instruction and data paths. The high bandwidth interface includes a mechanism for transmitting media data streams to and from the media processor at rates at or above the gigahertz frequency range. The media data stream can consist of transmission, presentation and storage type data transmitted alone or in a unified manner. Examples of such data types include audio, video, radio, network and digital communications. According to the invention, the media processor is dynamically partitionable to process any combination or permutation of these data types in any size. A programmable, general puφose media processor system presents significant advantages over current multimedia communications. Rather than rigid, costly and inefficient specialized processors, the media processor provides a general purpose instruction set to ease programmability in a single device that is capable of performing all of the operations of the specialized processor combination. Providing a uniform instruction set for all media related operations eliminates the need for a programmer to learn several different instruction sets, each for a different specialized processor. The complexity of programming the specialized processors to work together and communicate with one another is also greatly reduced. The unified instruction set is also more efficient. Highly specialized general calculation instructions that are tailored to general or special types of calculations rather than enhancing communication are eliminated. Moreover, the media processor system can be easily reprogrammed simply by transmitting or downloading new software over the network. In the specialized processor approach, new programming usually requires the delivery and installation of new hardware. Reprogramming the media processor can be done electronically, which of course is quicker and less costly than the replacement of hardware. It is to be understood that a wide range of changes and modifications to the embodiments described above will be apparent to those skilled in the art and are contemplated. It is therefore intended that the foregoing detailed description be regarded as illustrative rather than limiting, and that it be understood that it is the following claims, including all equivalents, that are intended to define the spirit and scope of this invention. Set forth on the following pages (46-406) is a more detailed discussion of the operations, and the functionality of the general puφose media processor 12. Introduction MicroUnity ' s Terpsichore System Architecture describes general-purpose processor, memory, and interface subsystems, organized to operate at enormouslv higher bandwidth rates than traditional computers. Terpsichore ' s Euterpe processor performs integer, floating point, and signal processing operations at data rates up to 512 bits (i.e., up to four 128-bit operand groups) per instruction. The instruction set design carries the concept oi streamlining beyond Reduced Instruction Ser Computer (RISC) architectures, since it targets implementations that issue several instructions per machine cycle. The Terpsichore memory subsystem provides 64-bit virtual and physical addressing for UNIX, λlach, and other advanced OS environments. Caches supply the high data and instruction issue rates of the processor, and support coherency primitives for scalable multiprocessors. The memory subsystem includes mechanisms for sustaining high data rates not only in block transfer modes, but also in non-unit stride and scatter/gather access patterns. Hermes channels provide 64-bit transfers between subsystem components with gigabyte-per-second bandwidth. Terpsichore's Cerberus serial bus provides a flexible, robust and inexpensive mechanism to handle system initialization, configuration, availability, and error recovery. Mnemosyne memory interface devices provide for the integration of large numbers of industry-standard memory components into Terpsichore systems. Persephone devices enable Terpsichore systems to utilize industrv-standard PCI interface cards. Terpsichore's Calliope interface subsystem is tightly integrated with the processor and memory, to supply both the bandwidth and real-time response needs of video. audio, network, and mass storage interfaces. Integration provides for the sharing of memory bandwidth among these devices and the processor, without distributed or dedicated buffer memories in each interface adapter. Terpsichore's Euterpe processor incorporates Icarus interprocessor interfaces for assembly of small-scale, coherently-cached, shared-memory multiprocessors, without additional circuitry. Icarus interfaces may also be used to connect Terpsichore processors to a high-performance switching fabric for large-scale multiprocessors, or to adapters to standard interprocessor interfaces, such as Scalable Coherent Interface (IEEE standard 1596-1992). The goal of the Terpsichore architecture is to integrate these processor, memory, and interface capabilities with optimal simplicity and generality. From the software perspective, the entire machine state consists of a program counter, a single bank of 64 general-purpose 64-bit registers, and a linear byte-addressed shared memory space with mapped interface registers. All interrupts and exceptions are precise, and occur with low overhead. This document is intended for Terpsichore software and hardware developers alike, and defines the interface at which their designs must meet. Terpsichore pursues the most efficient tradeoffs between hardware and software complexity by mak i ng all processor, memory, and interface resources direc t lv access i ble to high-level language programs. ' aLς -" Die co Conformanoe To ensure that Terpsichore s y stems are able to freelv interchange data, user-level programs, svstem-level programs and interlace devices, the Terpsichore system architecture reaches above the processor lev el architecture Mandatory and Optional Areas A computer system conforms to the requirements of the Terpsichore Svstem Architecture if and onlv if it implements all the specifications described in this document and other specifications included by reference Conformance to the specification is mandatory in all areas including the instruction set. memorv management svstem, interface devices and external interfaces, and bootstrap ROM functional requirements, except where explicit options are stated Optional areas include Number of processor threads Size of first-level cache memories Existence of a second-lev el cache Size of second-level cache memory Size of system-level memorv Existence of certain optional interface device interfaces Conformance to the specification is also optional regarding the physical implementation of internal interfaces, specifically that of the Cerberus serial bus architecture, the Hermes high-bandwidth channel architecture, and the Icarus interprocessor interconnection architecture An implementation may replace, modify or eliminate these interfaces, prov ided that the software-level functionalitv is unchanged Upward-compatible Modifications From time to time, MicroUnity mav modify the architecture in an upward- compatible manner, such as by the addition of new instructions definition of reserved bits in system state, or addition of new standard interfaces Such modifications will be added as options so that designs which conform to this version of the architecture will conform to future, modified versions Additional devices and interfaces, not covered by this standard mav be added in specified regions of the physical memory space, provided that svstem reset places these devices and interfaces in an inactive state that does not interfere with the operation of software that runs in anv conformant system The software interface requirements of any such additional devices and interfaces must be made as widely available as this architecture specification Promotion of Optional Features It is most strongly recommended that such optional instructions, state or interfaces be implemented in all contorrning designs Such implementations enhance the value of the features in particular and the architecture as a whole by broadening the set of implementations ov er which software mav depend upon the presence of these features Implementations which fail to implement these features mav encounter unacceptable levels of overhead when attempting to emulate the features bv exception handlers or use of virtual memorv This is a particular concern when involved in code which has real-time performance constraints In order that upward-compatible optional extensions of the original Terpsichore svstem architecture may be relied upon bv system and application software, MicroUnity mav upon occasion promote optional features to mandatory conformance for implementations designed or produced after a suitable delav upon such notification by publication of future version of the specification Unrestricted Physical Imolementatipn Nothing in this specification should be construed to limit the implementation choices of the conformant system beyond the specific requirements stated herein In particular, a computer system mav conform to the Terpsichore Svstem Architecture while employing any number of components, dissipate any amount of heat, require any special environmental faculties, or be of any physical size. Draft Version This document is a draft version of the architectural specification In this form, conformance to this document may not be claimed or implied. MicroUnitv may change this specification at any time, in any manner, until it has been declared final When this document has been declared final, the only changes will be to correct bugs, defects or deficiencies, and to add upward-compatible optional extensions Common Elements Notation The descriptive notation used in this document is summarized in the table below: descriptive notation Bit ordering The ordering of bits in this document is always little-endian, regardless of the ordering of bytes within larger data structures. Thus, the least-significant bit of a data structure is always labeled 0 (zero), and the most-significant bit is labeled as the data structure size (in bits) minus one. Memory Terpsichore memory is an array of 2 64 bytes, without a specified byte ordering, which is physically distributed among various Terpsichore components. Bvte A byte is a single element of the memory array, consisting of 8 bits: 7 0 | byte | 8 Bvte ordering Larger data structures are constructed from the concatenation of bytes in either little-endian or big-endian byte ordering. A memory access of a data structure of size s at address i is formed from memory bytes at addresses i through i+s-1. Unless otherwise specified, there is no specific requirement of alignment: it is not generally required that i be a multiple of s. Aligned accesses are preferred whenever possible, however, as they will often require one less processor or memory clock cycle than unaligned accesses. With little-endian byte ordering, the bytes are arranged as: With big-endian byte ordering, the bytes are arranged as: Terpsichore memory is byte-addressed, using either little-endian or big-endian byte ordering. For consistency with the bit ordering, and for compatibility with x86 processors, Terpsichore uses little-endian byte ordering when an ordering must be selected. Euterpe load and store instructions are available for both little- endian and big-endian byte ordering. The selection of byte ordering is dynamic, so that little-endian and big-endian processes, and even data structures within a process, can be intermixed on the processor. Memory read/load semantics Terpsichore memory, including memory-mapped registers, must conform to the following requirements regarding side-effects of read or load operations: A memory read must have no side-effects on the contents of the addressed memory nor on the contents of any other memory. Memory write/store semantics Terpsichore memory, including memory-mapped registers, must conform to the following requirements regarding side-effects of read or load operations: A memory write must have no side-effects on the contents of the addressed memory. A memory write may cause side-effects on the contents of memory not addressed by the write operation, however, a second memory write of the same value to the same address must have no side-effects on any memory; memorv write operations must be idempotent. Euterpe store instructions which are weakly ordered may have side-effects on the contents of memory not addressed by the store itself; subsequent load instructions which are also weakly ordered may or may not return values which reflect the side-effects. Data Euterpe provides eight-byte (64-bit) virtual and physical address sizes, and eight- byte (64-bit) and sixteen-byte (128-bit) data path sizes, and uses fixed-length four- byte (32-bit) instructions. Arithmetic is performed on two's-complement or unsigned binary and ANSI/IEEE standard 754-1985 conforming binary floating¬ point number representations. Fixed-point Data Bit A bit is a primitive data element: 0 ES3 1 Peck A peck is the catenation of two bits: Nibble A nibble is the catenation of four bits: 3 0 nibble Byte A byte is the catenation of eight bits, and is a single element of the memory array: 7 0 I byte | 8 Doublet A doublet is the catenation of 16 bits, and is the concatenation of two bytes: 1 5 0 [ doublet 16 Quadlet A quadlet is the catenation of 32 bits, and is the concatenation of four bytes: Octlet An octlet is the catenation of 64 bits, and is the concatenation of eight bytes: 31 0 [ octlet3i ..o 32 Hexlet A hexlet is the catenation of 128 bits, and is the concatenation of sixteen bvtes: 32 Address Terpsichore addresses are octlet quantities. Floating-point Data Terpsichore's floating-point formats are designed to satisfy ANSI/IEEE standard 754-1985: Binary Floating-point Arithmetic. Standard 754 leaves certain aspects to the discretion of the implementor: Terpsichore adds additional half-precision and quad-precision formats to standard 754's single-precision and double-precision formats. Terpsichore's double-precision satisfies standard 754's precision requirements for a single- extended format, and Terpsichore's quad-precision satisfies standard 754's precision requirements for a double-extended format. Quiet NaN values are denoted by any sign bit value, an exponent field of all one bits, and a non-zero significand with the most significant bit cleared. Quiet NaN values generated by default exception handling of standard operations have a zero sign bit, an exponent field of all one bits, and a significand field with the most significant bit cleared, the next-most significant bit set, and all other bits cleared. Signaling NaN values are denoted by any sign bit value, an exponent field of all one bits, and a non-zero significand with the most significant bit set. Half-orecision Floating -point Terpsichore half precision uses a format similar to standard 754's requirements, reduced to a 16-bit overall format. The format contains sufficient precision and exponent range to hold a 12 -bit signed integer. 1 5 1 4 1 0 9 0 sign exponent! significand 1 0 Singie-cecision Floating -point Terpsichore single precision satisfies standard 754's requirements for "single." 31 30 23 22 0 jsign exponent | significand | 8 23 Double-precision Floating-point Terpsichore double precision satisfies standard 754's requirements for "double." 63 62 52 51 32 1 1 1 20 31 I significand3i ..Q 32 Quad -precision Floating-point Terpsichore quad precision satisfies standard 754's requirements for "double extended," but has additional significand precision to use 128 bits. 32 Euterpe Prooessor MicroUnity's Euterpe processor provides the general-purpose, high-bandwidth computation capability of the Terpsichore system. Euterpe includes high- bandwidth data paths, register files, and a memory hierarchy. Euterpe's memory hierarchy includes on-chip instruction and data memories, instruction and data caches, a virtual memory facility, and interfaces to external devices. Euterpe's interfaces include flash ROM, synchronous DRAM, Cerberus serial bus, Hermes high-bandwidth channels, and simple keyboard and display. Architectural Framework The Euterpe architecture builds upon MicroUnity's Hermes high-bandwidth channel architecture and upon MicroUnity ' s Cerberus serial bus architecture, and complies with the requirements of Hermes and Cerberus. Euterpe uses parameters A and W as defined by Hermes. The Euterpe architecture defines a compatible framework for a family of implementations with a range of capabilities. The following implementation- defined parameters are used in the rest of the document in boldface. The value indicated is for MicroUnity's first Euterpe implementation. Interfaces and Block Diagram Instruction Instruction Mnemonics Instruction mnemonics are usually written with periods (.) separating elements of the mnemonic to make them easier to understand. Terpsichore assemblers and other code tools treat these periods as optional; the mnemonics are designed to be parsed uniquely either with or without the periods. Instruction ^ Structure A Terpsichore instruction is specifically defined as a four-byte structure with the little-endian ordering shown below. It is different from the quadlet defined above because the placement of instructions into memory must be independent of the byte ordering used for data structures. Instructions must be aligned on four-byte boundaries: in the diagram below, i must be a multiple of 4. 31 24 23 1 6 1 5 8 7 j byte i+3 | byte i+2 j byte i+1 | bytel Gateway A Terpsichore gateway is specifically defined as a 16-byte structure with the little- endian ordering shown below. A gateway contains a code address and a data address used to invoke a procedure at a higher privilege level securely. Gateways are marked by protection information specified in the TLB. Gateways must be aligned on 16-byte boundaries, that is, in the diagram below, i must be a multiple of 16. 127 120 1 19 1 12 1 1 1 104 103 96 The gateway contains two data items within its structure, a code address and a data address: 127 64 | data address \ 64 63 I code address 64 User state The user state consists of hardware data structures that are accessible to all conventional compiled code. The Terpsichore user state is designed to be as regular as possible, and consists only of the general registers, the program counter, and virtual memory. There are no specialized registers for condition codes, operating modes, rounding modes, integer multiply/divide, or floating-point values. Gene r al Registers Terpsichore user state includes 64 general registers. All are identical; there is no dedicated zero-valued register, and there are no dedicated floating-point registers Definition def v d(rn. size) case size of 64 val i- REG[rn] 128 if ΓΠQ then raise Reservedlnstruction endif val <- REG[rn+1 ] II REG[rn] endcase enddef def size, val) 128 if ΓΠQ then raise Reservedlnstruction endif REG[rn+1] <- vali27 64 REG[rn] *- val 63 0 endcase enddef Program Counter The program counter contains the address of the currently executing instruction. This register is implicitly manipulated by branch instructions, and read by branch instructions that save a return address in a general register. 63 2 10 | ProgramCounter |0| 62 2 Privilege Level The privilege level register contains the privilege level of the currently executing instruction. This register is implicitly manipulated by branch gateway and branch down instructions, and read by branch gateway instructions that save a return address in a general register. 1 0 2 Program Counter and Privilege Level The program counter and privilege level may be packed into a single octlet. This combined data structure is saved by the Branch Gateway instruction and restored by the Branch Down instruction. 63 2 10 | ProgramCounter |pi| 62 2 System state The system state consists of the facilities not normally used by conventional compiled code. These facilities provide mechanisms to execute such code in a fully virtual environment. All system state is memory mapped, so that it can be manipulated by compiled code. Fixed-point Terpsichore provides load and store instructions to move data between memory and the registers, branch instructions to compare the contents of registers and t o transfer control from one code address to another, and arithmetic operations to perform computation on the contents of registers, returning the result to registers. Load and Store The load and store instructions move data between memory and the registers. When loading data from memory into a register, values are zero-extended or sign- extended to fill the register. When storing data from a register into memory, values are truncated on the left to fit the specified memory region. Load and store instructions that specify a memory region of more than one bv t e may use either little-endian or big-endian bvte ordering: the size and ordering are explicitly specified in the instruction. Regions larger than one byte may be either aligned to addresses that are an even multiple of the size of the region, or of unspecified alignment: alignment checking is also explicitly specified in the instruction. The load and store instructions are used for fixed-point data as well as floating¬ point and digital signal processing data; Terpsichore has a single bank of registers for all data types. Swap instructions provide multithread and multiprocessor synchronization, using indivisable operations: add-and-swap, compare-and-swap, and multiplex-and- swap. A store-multiplex operation provides the ability to indivisably write to a portion of an octlet. These instructions always operate on aligned octlet data, using either little-endian or big-endian byte ordering. Branch Conditionally The fixed-point compare-and-branch instructions provide all arithmetic tests for equality and inequality of signed and unsigned fixed-point values. Tests are performed either between two operands contained in general registers, or on the bitwise and of two operands. Depending on the result of the compare, either a branch is taken, or not taken. A taken branch causes an immediate transfer of the program counter to the target of the branch, specified by a 12-bit signed offset from the location of the branch instruction. A non-taken branch causes no transfer; execution continues with the following instruction. Branch Unconditionally Other branch instructions provide for unconditional transfer of control to addresses too distant to be reached by a 12 -bit offset, and to transfer to a target while placing the location following the branch into a register. The branch through gateway instruction provides a secure means to access code at a higher privilege level, in a form similar to a normal procedure call. Arithmetic Operations The fixed-point arithmetic operations include add, subtract, multiply, divide, shifts, and set on compare, all using octlet-sized operands. Multiply and divide operations produce hexlet results; all other operations produce octlet results. When specified, add, subtract, and shift operations may cause a fixed-point arithmetic exception to occur on resulting conditions such as signed overflow, or signed or unsigned equality or inequality to zero. Addressino Operations A subset of the arithmetic operations are available as addressing operations. These addressing operations may be performed at a point in the Euterpe processor pipeline so that they may be completed prior to or in conjunction with the execution of load and store operations in a "superspring" pipeline in which other arithmetic operations are deferred until the completion of load and store operations. Floating-point Terpsichore provides all the facilities mandated and recommended by ANSI/IEEE standard 754-1985: Binary Floating-point Arithmetic, with the use of supporting software. Branch Conditionally The floating-point compare-and-branch instructions provide all the comparison types required and suggested by the IEEE floating-point standard. These floating¬ point comparisons augment the usual types of numeric value comparisons with special handling for NaN (not-a-number) values. A NaN compares as "unordered" with respect to any other value, even that of an identical NaN. Terpsichore floating-point compare-and-branch instructions do not generate an exception on comparisons involving quiet or signaling NaNs; if such exceptions are desired, they can be obtained by combining the use of a floating-point compare and set instruction, with either a floating-point compare-and-branch instruction on the floating-point operands or a fixed-point compare-and-branch on the set result. Because the less and greater relations are anti-commutative, one of each relation that differs from another only by the replacement of an L with a G in the code can be removed by reversing the order of the operands and using the other code. Thus, a UL relation can be used in place of a UG relation by swapping the operands to the compare-and-branch or compare-and-set instruction. The E and NE relations can be used to determine the unordered condition of a single operand by comparing the operand with itself. The following floating-point compare-and-branch relations are provided: compare-and-branch relations Compare -and -set The floating-point compare-and-set instructions provide all the comparison types supported as compare-and-branch instructions. Terpsichore floating-point compare-and-set instructions may optionally generate an exception on comparisons involving quiet or signaling NaNs. The following floating-point compare-and-branch relations are provided: compare-and- ranc re at ons Arithmetic Operations The operations supported in hardware are floating-point add, subtract, multiply, divide, and square root. Other operations required by the ANSI/IEEE floating¬ point standard are provided by software libraries. The operations explicitly specify the precision of the operation, and round the result to the specified precision at the conclusion of each operation. A single instruction provides a floating-point multiply with the result fed into a floating-point add. The result is computed as if the multiply is performed to infinite precision, added as if in infinite precision, then rounded. This operation is a particularly good match to the needs of vector linear algebra routines. Rounding Rounding is specified within the instructions explicitly, to avoid maintaining explicit state for a rounding mode. Exceptions All the mandated floating-point exception conditions cause a trap when they occur; maintenance of sticky and other status bits may be performed using software routines. Because the floating-point inexact exception may be very frequent, this exception only occurs when specified in the instruction explicitly. Arithmetic operations may also specify that all exceptions are to be handled by default, generating special results instead of traps. Digital Sional Processing The Terpsichore processor provides a set of operations that maintain the fullest possible use of 64- and 128-bit data paths when operating on lower-precision fixed-point or floating-point vector values. These operations are useful for several application areas, including digital signal processing, image processing, and synthetic graphics. The basic goal of these operations is to accelerate the performance of algorithms that exhibit the following characteristics: Low-precision arithmetic The operands and intermediate results are fixed-point values represented in no greater than 64 bit precision. For floating-point arithmetic, operands and intermediate results are of 16, 32, or 64 bit precision. The use of fixed-point arithmetic permits various forms of operation reordering that are not permitted in floating-point arithmetic. Specifically, commutativity and associativity, and distribution identities can be used to reorder operations. Compilers can evaluate operations to determine what intermediate precision is required to get the specified arithmetic result. Terpsichore supports several levels of precision, as well as operations to convert between these different levels. These precision levels are always powers of two, and are explicitly specified in the operation code. Sequential access to data The algorithms are or can be expressed as operations on sequentially ordered items in memory. Scatter-gather memory access or sparse-matrix techniques are not required. Where an index variable is used with a multiplier, such multipliers must be powers of two. When the index is of the form: nx+k, the value of n must be a power of two, and the values referenced should have k include the majority of values in the range 0..n-l. A negative multiplier may also be used. Vecto zable operations The operations performed on these sequentially ordered items are identical and independent. Conditional operations are either rewritten to use boolean variables or masking, or the compiler is permitted to convert the code into such a form. Data-handling Operations The characteristics of these algorithms include sequential access to data, which permit the use of the normal load and store operations to reference the data. Octlet and hexlet loads and stores reference several sequential items of data, the number depending on the operand precision. The discussion of these operations is independent of byte ordering, though the ordering of bit fields within octlets and hexlets must be consistent with the ordering used for bytes. Specifically, if big-endian byte ordering is used for the loads and stores, the figures below should assume that index values increase from left to right, and for little-endian byte ordering, the index values increase from right to left. For this reason, the figures indicate different index values with different shades, rather than numbering. When an index of the nx+k form is used in array operands, where n is a power of 2, data memory sequentially loaded contains elements useful for separate operands. The "deal" instruction divides a hexlet of data up into two octlets, with alternate bit fields of the source hexlet grouped together into the two results. For example, a G.DEALJ6 operation rearranges the source hexlet into two octlets as follows: 1 *An example of the use of a deal can be found in rhe appendix: Digital Signal Processing Applications: Decimation of Monochrome Image or Decimation of Color Image In the deal operation, the source hexlet is specified by two octlet registers, and the two result octlets are specified as a hexlet register pair. (This sounds backwards, and it really is, but it works in practice, because the result is usually used in operations that accept octlet operands. Ideally, the source hexlet should be a register pair, and the result should be two octlet registers.) The example above directly applies to the case where n is 2. When n is larger, a series of DEAL operations can be used to further subdivide the sequential stream. For example, when n is 4, we need to deal out 4 sets of doublet operands, as shown in the figure below: 2 This 4-way deal is performed by dealing out 2 sets of quadlet operands, and then dealing each of them out into 2 sets of doublet operands. 2 An example of the use of a four-way deal can be found in the appendix: Digital Signal Processing Applications: Conversion of Color to Monochrome There are three rows of arrows shown above. The first row is the result of two G. DEAL.32 operations, each independently dealing 2 sets of pairs of doublets. The result of these two operations is the second row of boxes. The last row is the result of two independent G.DEALJ6 operations, each dealing 2 sets of doublets into register pairs. The middle row of arrows shows the implicit action performed by specifying two non-adjacent registers for the hexlet sources of the G.DEALJ6 operations. When an array result of computation is accessed with an index of the form nx+k, for n a power of 2, the reverse of the "deal" operation needs to be performed on vectors of results to interleave them for storage in sequential order. The "shuffle" operation interleaves the bit fields of two octlets of results into a single hexlet. For example a G.SHUFFLEJ6 operation combines two octlets of doublet fields into a hexlet as follows: For larger values of n, a series of shuffle operations can be used to combine additional sets of fields, similarly to the mechanism used for the deal operations. For example, when n is 4, we need to shuffle up 4 sets of doublet operands, as shown in the figure below: 3 This 4-way shuffle is performed by shuffling up 2 sets of doublet operands, and then shuffling each of them up as 2 sets of quadlet operands. 3 An example of the use of a four-way shuffle can be found in the appendix: Digital Signal Processing Applications: Conversion of Monochrome to Color There are three rows of arrows shown above. The first row is the result of two G.SHUFFLEJ6 operations, each independently shuffling 2 sets of pairs of doublets. The result of these two operations is the second row of boxes. The last row is the result of two independent G. SHUFFLE.32 operations, each shuffling 2 sets of quadlets into register pairs. The middle row of arrows shows the implicit action performed by specifying two non-adjacent registers for the two octlet sources of the G.SHUFFLE.32 operations. W^hen the index of a source array operand or a destination array result is negated, or in other words, if of the form nx+k where n is negative, the elements of the array must be arranged in reverse order. The "swap" operation reverses the order of the bit fields in a hexlet. For example, a G.SWAPJ6 operation reverses the doublets within a hexlet: Variations of the deal and shuffle operations are also useful for converting from one precision to another. This may be required if one operand is represented in a different precision than another operand or the result, or if computation must be performed with intermediate precision greater than that of the operands, such as when using an integer multiply. When converting from a higher precision to a lower precision, specifically when halving the precision of a hexlet of bit fields, half of the data must be discarded, and the bit fields packed together. The "compress" operation is a variant of the "deal" operation, in which the operand is a hexlet, and the result is an octlet. An arbitrary half-sized sub-field of each bit field can be selected to appear in the result. For example, a selection of bits 19..4 of each quadlet in a hexlet is performed by the G.COMPRESS.16,4 operation: When converting from lower-precision to higher-precision, specifically when doubling the precision of an octlet of bit fields, one of several techniques can be used, either multiply, expand, or shuffle. Each has certain useful properties. In the discussion below, m is the precision of the source operand. The multiply operation, described in detail below, automatically doubles the precision of the result, so multiplication by a constant vector will simultaneously double the precision of the operand and multiply by a constant that can be represented in m bits. An operand can be doubled in precision and shifted left with the "expand" operation, which is essentially the reverse of the "compress" operation. For example the G.EXP AND.16,4 expands from 16 bits to 32, and shifts 4 bits left: The "shuffle" operation can double the precision of an operand and multiply it by 1 (unsigned only), 2 m or 2 m +l , by specifying the sources of the shuffle operation to be a zeroed register and the source operand, the source operand and zero, or both to be the source operand. When multiplying by 2m, a constant can be freely added to the source operand by specifying the constant as the right operand to the shuffle. Arithmetic Operations The characteristics of the algorithms that affect the arithmetic operations most directly are low-precision arithmetic, and vectorizable operations. The fixed-point arithmetic operations provided are most of the functions provided in the standard integer unit, except for those that check conditions. These functions include add, subtract, bitwise boolean operations, shift, set on condition, and multiply, in forms that take packed sets of bit fields of a specified size as operands. The floating-point arithmetic operations provided are as complete as the scalar floating-point arithmetic set. The result is generally a packed set of bit fields of the same size as the operands, except that the fixed-point multiply function intrinsically doubles the precision of the bit field. Conditional operations are provided only in the sense that the set on condition operations can be used to construct bit masks that can select between alternate vector expressions, using the bitwise boolean operations. All instructions operate over the entire octlet or hexlet operands, and produce a hexlet result. The sizes of the bit fields supported are always powers of two. Galois Field Operations Terpsichore provides a general software solution to the most common operations required for Galois Field arithmetic. The instruction provided is a polynomial divide, with the polynomial specified as one register operand. The result of a specified number of division steps, expressed as a register pair, is the result of the instruction. This instruction can be used to perform CRC generation and checking, Reed-Solomon code generation and checking, and spread-spectrum encoding and decoding. Software Conventions The following section describes software conventions which are to be employed at sofware module boundaries, in order to permit the combination of separately compiled code and to provide standard interfaces between application, library and system software. Register usage and procedure call conventions may be modified, simplified or optimized when a single compilation encloses procedures within a compilation unit so that the procedures have no external interfaces. For example, internal procedures may permit a greater number of register-passed parameters, or have registers allocated to avoid the need to save registers at procedure boundaries, or may use a single stack or data pointer allocation to suffice for more than one level of procedure call. Register Usaoe All Terpsichore registers are identical and general-purpose; there is no dedicated zero-valued register, and no dedicated floating-point registers. However, some procedure-call-oriented instructions imply usage of registers zero (0) and one (1) in a manner consistent with the conventions described below. By software convention, the non-specific general registers are used in more specific ways. register usage At a procedure call boundary, registers are saved either by the caller or callee procedure, which provides a mechanism for leaf procedures to avoid needing to save registers. Optimizers may choose to allocate variables into caller or callee saved registers depending on how their lifetimes overlap with procedure calls. The dp register points to a small (4 kilobyte) array of pointers, literals, and statically-allocated variables, which is used locally to the procedure. The uses of the dp register are similar to the Mips use of the gp register, except that each procedure may have a different value, which expands the space addressable by small offsets from this pointer. This is an important distinction, as the offset field of Terpsichore load and store instructions are only 12 bits. The compiler may use additional registers and/or indirect pointers to address larger regions. This mechanism also permits code to be shared, with each static instance of the dp region assigned to a different address in memory. In conjunction with position- independent or pc-relative branches, this allows library code to be dynamically relocated and shared between processes. Procedure Calling Conventions Procedure parameters are normally allocated in registers, starting from register 2 up to register 9. These registers hold up to 8 parameters, which may each be of any size from one byte to eight bytes, including single-precision and double- precision floating-point parameters. Quad-precision floating-point parameters require an aligned pair of registers. The C varargs.h or stdarg.h conventions may require saving registers into memory (this is not necessarily so, but some semi- portable semi-conventions such as _doprnt would break otherwise). Procedure return values are also allocated in registers, starting from register 2 up to register 9. There are several data structures maintained in registers for the procedure calling conventions: link, sp, dp, fp. The link register contains the address to which the callee should return to at the conclusion of the procedure. The sp register is used to form addresses to save parameter and other registers, maintain local variables, i.e., data that is allocated as a LIFO stack. For procedures that require a stack, normally a single allocation is performed, which allocates space for input parameters, local variables, saved registers, and output parameters all at once. The sp register is always 16-byte aligned. The dp register is used to address pointers, literals and static variables for the procedure. The newpc register is loaded with the entry point of the procedure, and the ne dp register is loaded with the value of the dp register required for the procedure. This mechanism provides for dynamic linking, by initially filling in the link and dp fields in the data structure to point to the dynamic linker. The linker can use the current contents of the link and/or dp registers to determine the identity of the caller and callee, to find the location to fill in the pointers and resume execution. The fp register is used to address the stack frame when the stack size varies during execution of a procedure, such as when using the GNU alloca function When the stack size can be determined at compile time, the sp register is used to address the stack frame and the fp register may be used for other general purposes as a callee-saved register. Typical static-linked, intra-module calling sequence: caller or callee (non-leaf): L.64 lιnk.off(sp) callee (le Typical dynamic-linked, inter-module calling sequence: caller or callee (non-leaf): (sρ) (dρ) (sp) callee (le The load instruction is required in the caller following the procedure call to restore the dp register. A second load instruction also restores the link register, which may be located at any point between the last procedure call and the branch instruction which returns from the procedure. Svstem and Privileged Library Calls It is an objective to make calls to system facilities and privileged libraries as similar as possible to normal procedure calls as described above. Rather than invoke system calls as an exception, which involves significant latency and complication, we prefer to use a modified procedure call in which the process privilege level is quietly raised to the required level. In to provide this mechanism safely, interaction with the virtual memory system is required. Such a routine must not be entered from anywhere other than its legitimate entry point, otherwise the sudden access to a higher privilege level might be taken advantage of. The branch-gateway instruction ensures both that the procedure is invoked at a proper entry point, and that the data pointer is properly set. To ensure this, the branch-through-gateway instruction retrieves a "gateway" directly from the protected virtual memory space. The gateway contains the virtual address of the entry point of the procedure and the virtual address to be loaded into the data pointer. A gateway can only exist in regions of the virtual address space designated to contain them, to ensure that a gateway cannot be forged. Similarly, a return from a system or privileged routine involves a reduction of privilege. This need not be carefully controlled by architectural facilities, so a procedure may freely branch to a less-privileged code address. However, in certain, though perhaps rare, cases, it would be useful to have highly privileged code call less-privileged routines. As an example, a user may request that errors in a privileged routine be reported by invoking a user-supplied error-logging routine. In such a case, a return from a procedure actually requires an increase in privilege, which must be carefully controlled. Again, a branch-through-gateway instruction can be used, this time in the instruction following the call, to raise the privilege again in a controlled fashion. In such a case, special care must be taken to ensure that the less-privileged routine is not permitted to gain unauthorized access by corruption of the stack or saved registers, such as by saving all registers and setting up a new stack frame that may be manipulated by the less-privileged routine. Typical dynamic-linked, inter-gateway calling sequence: caller: S 128 nkdp, off(sp) B GATE lιnkdp.off(dp) L 128 hnkdp. off(sp) callee (non-leaf): S.64 sp.off(dp) L.64 sρ.off(dp) SJ28 link.dp.off(sp) ... (using dp) LJ 28 link.dp.off(sp) L.64 sρ.off(dp) B.DOWN link callee (leaf ) : ... (using dp) B.DOWN link The callee, if it uses a stack for local variable allocation, cannot necessarily trust the value of the sp passed to it, except as a region to receive parameters held in memory. Pipeline Organization Euterpe performs all instructions as if executed one-by-one, in-order, with precise exceptions always available. Consequently, code which ignores the subsequent discussion of Euterpe pipeline implementations will still perform correctly. However, the highest performance of the Euterpe processor is achieved only by matching the ordering of instructions to the characteristics of the pipeline. In the following discussion, the general characteristics of all Euterpe implementations preceeds discussion of specific choices for specific implementations. Classical Pipeline Structures Pipelining in general refers to hardware structures that overlap various stages of execution of a series of instructions so that the time required to perform the series of instructions is less than the sum of the times required to perform each of the instructions separately. Additionally, pipelines carry to connotation of a collection of hardware structures which have a simple ordering and where each structure performs a specialized function. The diagram below shows the timing of what has become a canonical pipeline structure for a simple RISC processor, with time on the horizontal axis increasing to the right, and successive instructions on the vertical axis going downward. The stages I, R, E, M, and W refer to units which perform instruction fetch, register file fetch, execution, data memory fetch, and register file write. The stages are aligned so that the result of the execution of an instruction may be used as the source of the execution of an immediately following instruction, as seen by the fact that the end of an E stage (bold in line 1 ) lines up with the beginning of the E stage (bold in line 2) immediately below. Also, it can be seen that the result of a load operation executing in stages E and M (bold in line 3) is not available in the immediately following instruction (line 4), but may be used two cycles later (line 5); this is the cause of the load delay slot seen on some RISC processors. In the diagrams below, we simplify the diagrams somewhat by eliminating the pipe stages for instruction fetch, register file fetch, and register file write, which can be understood to preceed and follow the portions of the pipelines diagrammed. The diagram above is shown again in this new format, showing that the canonical pipeline has very little overlap of the actual execution of instructions. A superscalar pipeline is one capable of simulatenously issuing two or more instructions which are independent, in that they can be executed in either order and separately, producing the same result as if they were executed serially. The diagarm below shows a two-way superscalara processor, where one instruction may be a register-to-register operation (using atage E) and the other may be a register-to-register operation (using atage A) or a memory load or store (using stages A and M). A superpipelined pipeline is one capable is issuing simple instructions frequently enough that the result of a simple instruction must be independent of the immediately following one or more instructions. The diagram below shows a two- cycle superpipelined implementation: In the diagrams below, pipeline stages are labelled with the type of instruction which may be performed by that stage. The posititon of the stage further identifies the function of that stage, as for example a load operation may require several L stages to complete the instruction. Superstring Pipeline Euterpe architecture provides for implementations designed to fetch and execute several instructions in each clock cycle. For a particular ordering or instruction types, one instruction of each type may be issued in a single clock cycle. The ordering required is A, L, E, S, B; in other words, a register-to-register address calculation, a memory load, a register-to-register data calculation, a memory store, and a branch. Because of the organization of the pipeline, each of these instructions may be serially dependent. Instructions of type E include the fixed- point execute-phase instructions as well as floating-point and digital signal processing instructions. We call this form of pipeline organization "superstring," 4 because of the ability to issue a string of dependent instructions in a single clock cycle, as distinguished from superscalar or superpipelined organizations, which can only issue sets of independent instructions. ^Readers with a background in theoretical physics may have seen this term in an other, unrelated, context. These instructions take from one to four cycles of latency to execute, and a branch prediction mechanism is used to keep the pipeline filled. The diagram below shows a box for the interval between issue of each instruction and the completion. Bold letters mark the critical latency paths of the instructions, that is, the periods between the required availability of the source registers and the earliest availability of the result registers. The A-L critical latency path is a special case, in which the result of the A instruction may be used as the base register of the L instruction without penalty. E instructions may require additional cycles of latency for certain operations, such as fixed-point multiply and divide, floating-point and digital signal processing operations. Superspring Pipeline Euterpe architecture provides an additional refinement to the organization defined above, in which the time permitted by the pipeline to service load operations may be flexibly extended. Thus, the front of the pipeline, in which A, L and B type instructions are handled, is decoupled from the back of the pipeline, in which E, and S type instructions are handled. This decoupling occurs at the point at which the data cache and its backing memory are referenced; similarly, a FIFO that is filled by the instruction fetch unit decouples instruction cache references from the front of the pipeline shown above. The depth of the FIFO structures is implementation-dependent, i.e. not fixed by the architecture. The diagram below indicates why we call this pipeline organization feature "su jppeerrsspprninngg,," aann eexxtteennssiioonn oofr oouurr ssuuppeerrssttrriinngg oorrggaanniizzaattiioonn.. With the super-spring organization, the latency of load instructions can be extended, so execute instructions are deferred until the results of the load are available. Nevertheless, the execution unit still processes instructions in normal order, and provides precise exceptions. Superthread Pipeline A difficulty of superpipelining is that dependent operations must be separated by the latency of the pipeline, and for highly pipelined machines, the latency of simple operations can be quite significant. The Eutepe "superthread" pipeline provides for very highly pipelined implementations by alternating execution of two or more independent threads. In this context, a thread is the state required to maintain an independent execution; the architectural state required is that of the register file contents, program counter, privilege level, local TLB, and when required, exception status. The latter state, exception status, may be minimized by ensuring that only one thread may handle an exception at one time. In order to ensure that all threads make reasonable forward progress, several of the machine resources must be scheduled fairly. An example of a resource that is critical that it be fairly shared is the data memory/cache subsystem. In MicroUnity's first Euterpe implementation, Euterpe is able to perform a load operation only on every second cycle, and a store operation only on every fourth cycle. Euterpe schedules these fixed timing resources fairly by using a round-robin schedule of a number of threads which is relatively prime to the resource reuse rates. For Euterpe's first implementation, five simulateous threads of execution ensure that resources which may be used every two or four cycles are fairly shared by allowing the instructions which use those resources to be issued only on every second or fourth issue slot for that thread. In the diagram below, the thread number which issues an instruction is indicated on each clock cycle, and below it, a list of which functional units may be used by that instruction. The diagram repeats every 20 cycles, so cycle 20 is similar to cycle 0, cycle 21 is similar to cycle 1, etc. This schedule ensures that no resource conflict occur between threads for these resources. Thread 0 may issue an E,L,S or B on cycle 0, but on its next opportunity, cycle 5. may only issue E or B, and on cycle 10 may issue E, L or B, and on cycle 15, may issue E or B. When seen from the perspective of an individual thread, the resource use diagram looks similar to that of the collection. Thus an individual thread may use the load unit every two instructions, and the store unit every four instructions. A Euterpe Superthread pipeline, with 5 simulatenous threads of execution, permits simple operations, such as register-to-register add (E.ADD), to take 5 cycles to complete, allowing for an extremely deeply pipelined implementation. Branch/fetch Prediction Euterpe does not have delayed branch instructions, and so relies upon branch or fetch prediction to keep the pipeline full around unconditional and conditional branch instructions. In the simplest form of branch prediction, as in Euterpe ' s first implementation, a taken conditional backward (toward a lower address ) branch predicts that a future execution of the same branch will be taken. More elaborate prediction may cache the source and target addresses of multiple branches, both conditional and unconditional, and both forward and reverse. The hardware prediction mechanism is tuned for optimizing conditional branches that close loops or express frequent alternatives, and will generally require substantially more cycles when executing conditional branches whose outcome is not predominately taken or not-taken. For such cases of unpredictable conditional results, the use of code which avoids conditional branches in favor of the use of set on compare and multiplex instructions may result in greater performance. Where the above technique may not be applicable, a Euterpe pipeline may ensure that conditional branches which have a small positive offset be handled as if the branch is always predicted to be not taken, with the recovery of a misprediction causing cancellation of the instructions which have already been issued but not completed which would be skipped over by the taken conditional branch. This "conditional-skip" optimization is performed by the Euterpe implementation and requires no specific architectural feature to access or implement. A Euterpe pipeline may also perform "branch-return" optimization, in which a branch-and-link instruction saves a branch target address which is used to predict the target of the next branch-register instruction. This optimization may be implemented with a depth of one ( only one return address kept), or as a stack of finite depth, where a branch and link pushes onto the stack, and a branch-register pops from the stack. This optimization can eliminate the misprediction cost of simple procedure calls, as the calling branch is susceptible to hardware prediction, and the returning branch is predictable by the branch-return optimization. Like the conditional-skip optimization described above, this feature is performed by the Euterpe implementation and requires no specific architectural feature to access or implement. Additional Load and Execute Resources Studies of the dynamic distribution of Euterpe instructions on various benchmark suites indicate that the most frequently-issued instruction classes are load instructions and execute instructions. In a high-performance Euterpe implementation, it is advantageous to consider execution pipelines in which the ability to target the machine resources toward issuing load and execute instructions is increased. One of the means to increase the ability to issue execute-class instructions is to provide the means to issue two execute instructions in a single-issue string. The execution unit actually requires several distinct resources, so by partitioning these resources, the issue capability can be increased without increasing the number of functional units, other than the increased register file read and write ports. The partitioning favored for the initial implementation places all instructions that involve shifting and shuffling in one execution unit, and all instructions that involve multiplication, including fixed-point and floating-point multiply and add in another unit. Resources used for implementing add, subtract, and bitwise logical operations may be duplicated, being modest in size compared to the shift and multiply units, or shared between the two units, as the operations have low- enough latency that two operations might be pipelined within a single issue cycle. These instructions must generally be independent, except perhaps that two simple add, subtract, or bitwise logical may be performed dependently, if the resources for executing simple instructions are shared between the execution units. One of the means to increase the ability to issue load-class instructions is to provide the means to issue two load instructions in a single-issue string. This would generally increase the resources required of the data fetch unit and the data cache, but a compensating solution is to steal the resources for the store instruction to execute the second load instruction. Thus, a single-issue string can then contain either two load instructions, or one load instruction and one store instruction, which uses the same register read ports and address computation resources as the basic 5 -instruction string. This capability also may be employed to provide support for unaligned load and store instructions, where a single-issue string may contain as an alternative a single unaligned load or store instruction which uses the resources of the two load-class units in concert to accomplish the unaligned memory operation. Result Forwarding When temporally adjacent instructions are executed by seperate resources, the results of the first instruction must generally be forwarded directly to the resource used to execute the second instruction, where the result replaces a value which may have been fetched from a register file. Such forwarding paths use significant resources. A Terpsichore implementation must generally provide forwarding resources so that dependencies from earlier instructions within a string are immediately forwarded to later instructions, except between a first and second execution instruction as described above. In addition, when forwarding results from the execution units back to the data fetch unit, additional delay may be incurred. Instruction Set All instructions are 32 bits in size, and use the high order 8 bits to specify a major operation code. 31 24 23 C major other 8 24 For the major operation field values A.MINOR, L.MINOR, E.MINOR, F.16, F.32, F.64, F.128, GF.16, GF.32, GF.64, G.l, G.2, G.4, G.8, G.16, G.32, G.64, S.MINOR and B.MINOR, the lowest-order six bits in the instruction specify a minor operation code: 31 24 23 6 5 0 [ major other | minor | 8 18 'Blank table entries cause the Reserved Instruction exception to occur. minor operation code ieiα values for E. MINOR minor operation code field values for F.size minor operation code field values for GF.size minor operation code field values for .size minor operaton code ie vaues or . m nor operat on code ield values for B.MINOR For the major operation field values F.16, F.32, F.64, F.128. with minor operation field values F.UNARY.N, F.UNARY.T, F.UNARY.F, F.UNARY.C, F.UNARY, and F. UNARY. X, and for major operation field values GF.16, GF.32, GF.64, with minor operation field values GF.UNARY.N, GF.UNARY.T, GF.UNARY.F, GF.UNARY.C, GF.UNARY, and GF.UNARY.X, another six bits in the instruction specify a unary operation code: 3 1 24 23 1 8 1 7 12 1 1 6 5 | major | other other | unary \ minor | The unary field is filled with a value from one of the following tables: unary operation code field values for F.UNARY.size.r unary operation code field values for . NA . s ze. r The general forms of the instructions coded by a major operation code are one of the following: 31 24 23 0 The general forms of the instructions coded by major and minor operation codes are one of the following: 31 24 23 1 8 1 7 1 2 1 1 6 5 major 8 I ra rb | re j minor { 31 24 23 18 1 7 12 1 1 6 5 major ra rb | simm | minor \ 8 The general form of the instructions coded by major, minor, and unary operation codes is the following: Definition def Thread as forever do mst <- Load emory(ProgramCounter,32,L) ProgramCounter <- ProgramCounter + 4 lnstructιon(ιnst) endforever enddef def lnstructιon(ιnst) as major <- ιns 3i ..24 ra <- ιnst23 18 simm «- rb «<— insti 7 12 re <- insti l 6 minor <- rd <— msts o case major of ERES EternallyReserved E MINOR case minor of EADD EADDO E ADD UO EAND E ANDN E NAND E NOR EOR EORN ESUB E SUB 0 E SUB UO E XNOR E XOR ESHL ESHLO E SHL UO E SHR E USHR E ROTL E ROTR EMUL EUMUL E DIV E UDIV ELMS E ULMS E ASUM ESETE ESETNE E SET L E SET GE E SET UL E SET UGE ESUBE ESUBNE E SUB L E SUB GE E SUB UL E SUB UGE Execute(mιnor ra rb re) E SHL I E SHL I 0 E SHL I UO E SHR I E USHR I E ROTR I ExecuteShortlmmedιate(mιnor ra simm re) others raise Reservedlπstruction pπd ssp EADDI EADD I SO E AND I E OR I E NAND I E NOR I E XOR I E SET I E E SET I NE E SET I L ES ET I GE E SET I UL E SET I UGE ESUB IE ESUB INE E SUB I L E SUB I GE E SUB I UL E SUB I UGE Executelmmedιate(ma]θr ra re inst- 1 o) EMUX ExecuteTernary(major ra rb re rd) E COPY I ExecuteCopylmmedιate(majcr ra ιnst-170) FMULADD16 FMULADD32 FMULADD64 FMULADD128 FMULSUB16 FMULSUB32 FMULSUB64 FMULSUB128 FloatιngPoιntTernary(major ra rb re rd) F16 F32 F64 F 128 case minor of F ADD N, FSUB N F MUL N F DIV N FADDT FSUBT F MUL T F DIV T FADDF FSUBF F MUL F F DIV F FADDC FSUBC FMULC F DIV C FADD FSUB FMUL FDIV F ADD X, F SUB X, F MUL X F DIV X FSETE FSETNE F SET UE FSET UE F SET NUGE F SET UGE. F SET UL F SET NUL F SET E X, FSETNE X FSETUEX F SET NUE X FSETLX, FSETNLX F SET NGE X F SET GE X FloatιngPoιnt(mιnor op major size minor round ra, rb re) F UNARY N F UNARY T F UNARY F F UNARY C F UNARY, F UNARY X case unary of FABS FNEG F SQR FHALF F SINGLE F DOUBLE F QUAD, FINT F FLOAT FloatιngPoιntUnary(unary op major size minor round ra re) others raise Reservedlnstruction endcase others raise Reservedlnstruction GMULADD1 GMULADD2 GMULADD4 GMULADD8 GMULADD16 GMULADD32 GUMULADD2. GUMULADD4, GUMULADD8, GUMULADD16 GUMUL4DD32 GMUX, GMUXGATHER, GSCATTERMUX G EXTRACT 128 GroupTernary(major,sιze ra rb re rd) G EXTRACT I. G EXTRACT I 64 GroupExtractlmmedιate(major ra rb re minor) G 1. G 2 G 4, G 8 G 16 G 32 case minor of G SHL G SHR G USHR G ADD G SUB G MUL, G UMUL G AND G OR, G XOR. G ANDN G NAND G NOR. G XNOR, G ORN G SET E G SET NE G SET L G SET GE G SET UL. G SET UGE. G COPY G SWAP G DEAL G SHUFFLE G COMPRESS, G EXPAND. G GATHER, G SCATTER Group(mιnor major ra rb re) G COMPRESS I G EXPAND I G SHL I G SHR I G U SHR I GroupShortlmmedιate(mιnor major ra simm, re) G EXTRACT I GroupExtractlmmedιa:e(major,ra rb re. minor) others raise Reservedlnstruction endcase GFMULADD16, GFMULADD32 GFMULΛDD64 GFMULSUB16. GFMULSUB32 GFMULSUB64 GroupFloatιngPoιntTernary(majcr ra rb re rd) GF 16. GF 32, GF 64, GF 128 case minor of GF ADD N, GF SUB N, GF MUL N, GF DIV N GF ADD T, GF SUB T, GF UL T GF DIV T GF ADD F, GF SUB F GF MUL F GF DIV F GF ADD C. GF SUB C GF MUL C. GF DIV C, GF ADD, GF SUB, GF MUL GF DIV GF ADD X, GF SUB X, GF MUL X GF DIV X, GF SET E, GF SET NE GF SET UE, GF SET NUE. GF SET NUGE GF SET UGE GF SET UL, GF SET NUL GF SET E X, GF SET NE X GF SET UE X GF SET NUE . GF SET L X, GF SET NL X GF SET NGE X. GF SET GE X GroupFloatιngPoιnt(mmor op major size minor round ra. rb re) GF UNARY N, GF UNARY T GF UNARY F, GF UNARY C GF UNARY, GF UNARY X case unary of GF ABS, GF NEG GF SQR, GF HALF GF SINGLE, GF DOUBLE, GF QUAD, GF INT, GF FLOAT GroupFloatιngPoιntUnary(unary op, major size, minor round, ra, re) others raise Reservedlnstruction endcase others raise Reservedlnstruction endcase L M INOR case minor of L16L LU16L L32L LU32L L64L L128L L8 LU8, L16LA LU 16LA. L32LA LU32LA. L64LA, L128LA, L16B. LU16B, L32B LU32B L64B, L128B L16BA LU16BA L32BA LU32BA. L64BA L128BA Load(mιnor ra rb re) others raise Reservedlnstruction βπdcssθ L16U. LU16LI. L32LI. LU32LI. L64U. L128LI. L8I. LU8I, L16LAI, LU16LAI. L32LAI, LU32LAI. L64LAI, L128LAI, L16BI LU16BI. L32BI. LU32BI L64BI, L128BI, L16BAI, LU 16BAI, L32BAI. LU32BAI, L64BAI, L128BAI Loadlmmedιate(major,ra rb inst-π rj) S MINOR case minor of S16L. S32L S64L. S123L S8, S16LA, S32LA, S64LA S128LA, SAAS64LA, SCAS64LA SMAS64LA. SM64LA, S16B, S32B, S64B. S128B, S16BA, S32BA. S64BA. S128BA. SAAS64BA. SCAS64BA SMAS64BA, SM64BA Store(mιnor,ra.rb re) others raise Reservedlnstruction endcase S16LI. S32LI. S64LI. S128LI. S3I S16LAI S32LAI. S64LAI S128LAI SAAS64LAI, SCAS64LAI SMAS64LAI. SM64LAI S16BI, S32BI. S64BI, S128BI S16BAI, S32BAI. S64BAI, S128BAI SAAS64BAI, SCAS64BAI, SMAS64BAI, SM64BAI Storelmmedιate(major.ra.rb.ιnstι 1 o) B MINOR case minor of B. B DOWN Branch(mιnor.ra) B.LINK BranchAndLιnk(mιnor.ra.rb) B GATE BranchGateway(mιnor,ra,rb,rc) others raise Reservedlnstruction endcase BLINKI, Bl Branchlmmedιate(major,ιnst23 rj) BFE16, BFNUE16. BFNUGE16. BFNUL16, BFE32, BFNUE32, BFNUGE32. BFNUL32, BFE64, BFNUE64, BFNUGE64, BFNUL64, BFE128. BFNUE128, BFNUGE128. BFNUL128, BE, BNE, BL, BGE, BUL BUGE, BANDE, BANDNE BranchCondιtιonal(major,ιnstι 1 .0) BGATEI BranchGatewaylmmedιate(ra rb.insti i 0) others raise Reservedlnstruction endcase enddef Eternally Reserved This operation generates a reserved instruction exception. Operation code I E.RES Eternally reserved Format E.RES imm Descr i ption The reserved instruction exception is raised. Software may depend upon this major operation code raising the reserved instruction exception in all Terpsichore processors. The choice of operation code intentionally ensures that a branch to a zeroed memory area will raise an exception. Definition def EternallyReserved as raise Reservedlnstruction enddef Exceptions Reserved Instruction Branch This operation branches to a location specified by a register, optionally reducing the current privilege level. Operation codes Format op ra 31 24 23 18 17 12 11 6 5 I B.MINOR I ra f op Description Execution branches to the address specified by the contents of register ra. If specified, the current privilege level is reduced to the level specified by the low order two bits of the contents of register ra. Access disallowed exception occurs if the contents of register ra is not aligned on a quadlet boundary, unless the operation specifies the use of the low-order two bits of the contents of register ra as a privilege level. Definition def Branch(op.ra) as a <- RegRead(ra, 64) if op = B.DOWN then if PπvilegeLevel > a-| ..o then PrivilegeLevel «- aι ..o endif else if (a and 3) ≠ 0 then raise AccessDisallowedByVirtualAddress endif endif ProgramCounter <- a63..2 " 0 2 enddef Exceptions Access disallowed bv virtual address Branch and Link This operation branches to a location specified by a register, saving the value of the program counter into a register. Operation codes B.LINK Branch and link Format op rb.ra 31 24 23 18 17 12 11 6 5 0 j B.MINOR I ra I rb j 0 | op | 8 6 6 6 6 Description The address of the instruction following this one is placed into register rb. Execution branches to the address specified by the contents of register ra. Access disallowed exception occurs if the contents of register ra is not aligned on a quadlet boundary. Definition def BranchAndLink(op.ra.rb) as a «r- RegRead(ra, 64) if (a and 3) ≠ 0 then raise AccessDisallowedByVirtualAddress endif RegWrιte(rb, 64. ProgramCounter + 4) ProgramCounter <- ag3..2 II 0 2 enddef Exceptions Access disallowed by virtual address Branch Conditionally These operations compare two operands, and depending on the result of that comparison, conditionally branches to a nearby code location. Operation codes β.E suffices for both signed and unsigned comparison for equality. " B.G.Z is encoded as B.U.L with both instruction fields ra and rb equal. 8 B.GE.Z is encoded as B.GE with both instruction fields ra and rb equal. 9 BJ.Z is encoded as B.L with both instruction fields ra and rb equal. 10 B.LE.Z is encoded as B.U.GE with both instructionf fields ra and rb equal. 1 J B.NE suffices for both signed and unsigned comparison for inequality. Format op rb.ra, target 31 24 23 18 r 12 1 1 op ra rb offset 1 2 Description The contents of registers or register pairs specified by ra and rb are compared, as specified by the op field. If the result of the comparison is true, execution branches to the address specified by the offset field. Otherwise, execution continues at the next sequential instruction. exception occurs when the size specified by the op field is Definition def BranchCondιtιonal(op,ra.rb offset) as case op of BFE16. BFNUE16, BFNUGE16. BFNUL16. BFE32. BFNUE32. BFNUGE32,. BFNUL32, BFE64, BFNUE64, BFNUGE64, BFNUL64, BFE128, BFNUE128, BFNUGE128 BFNUL128 type <- F BE, BNE type <- NONE BL, BGE type «- (ra = rb) ? Z NONE BUL, BUGE type <r- (ra = rb) ? ∑ j BANDE, BANDNE type <- AND endcase case op of B U L compare «- (ra = rb) 7 G L B U GE 12 B U E implemented as B E 13 B U NE implemented as B NE compare <- (ra = rb) 9 LE GE BGE compare «•- GE B L compare <- L B AND NE, B NE compare <- NE BANDE BE BFE 16 B F E 32 BFE64, BFE128 compare <- E B F NUE 16, B F NUE 32 B F NUE 64. B F NUE 128 compare <- NUE B F NUGE 16, B F NUGE 32, B F NUGE 64, B F NUGE 128 compare <- NUGE BFNUL 16, BFNUL32 B F NUL 64 BF NUL 128 compare <- NUL endcase case op of BFE16, BFNUE16 BFNUGE16 BFNUL16 BFE32 BFNUE32 BFNUGE32. BFNUL32 BFE64 BFNUE64 BFNUGE64, BFNUL64 BFE128 BFNUE128 BFNUGE128 BFNUL128 BE BNE BL BGE BUL, BUGE BANDE. BANDNE size <- undefined endcase case type of NONE a <- RegRead(ra, 64) b <- RegRead(rb, 64) l«-b r <- a U E: c < — I = r NE, NUE: c <- I ≠ r L, NUGE: c *- I < r NUL, GE: c <- I > r G: c «— I > r LE: c «— I < r endcase endif if c then PC «_ PC + (offset-- 1 50 II offset II 0 2 ) endif enddef Exceptions Reserved Instruction Branch Gateway Immediate This operation provides a secure means to call a procedure, including those at a higher privilege level. Operation codes I B.GATE.I Branch gateway immediate Format B. GATE. I ra.imm Description A virtual address is computed from the sum of the contents of register ra and the sign-extended value of the 12-bit immediate field. The contents of 16 bytes of memory using the little-endian byte order is fetched. A branch and link occurs to the low-order octlet of the memory data, and the successor to the current program counter, catenated with the current execution privilege is placed in register 0. The privilege level is set to the contents of the low-order two bits of the memory data. Register 1 is loaded with the high-order octlet of the memory data. An access disallowed exception occurs if the new privilege level is greater than the privilege level required to write the memory data, or if the old privilege level is lower than the privilege required to access the memory data as a gateway. An access disallowed exception occurs if the target virtual address is a higher privilege than the current level and gateway access is not set for the gateway virtual address, or if the access is not aligned on a 16-byte boundary. A reserved instruction exception occurs if the rb field is non-zero. Definition def BranchGatewaylmmedιate(ra.rb.ιmm) as a <- RegRead(ra, 64) VirtAddr <- a + dmm '■ -mm) if VιrtAddr3. _ ≠ 0 then raise AccessDisallowedByVirtualAddress endif if rb ≠ 0 then raise Reservedlnstruction endif b «- LoadMemory(VιrtAddr.128,L) bx <- bi27 64 H ProgramCountere3 2 + 1 H PπvilegeLevel ProgramCounter <- b63 2 '■ ° 2 PrivilegeLevel <- b-| ..o RegWrite(rb, 128, bx) enddef Exceptions Reserved Instruction Access disallowed by virtual address Access disallowed by tag Access disallowed by global TLB Access disallowed by local TLB Access detail required by tag Access detail required by local TLB Access detail required by global TLB Cache coherence intervention required by tag Cache coherence intervention required by local TLB Cache coherence intervention required by global TLB Local TLB miss Global TLB miss Branch Gateway This operation provides a secure means to call a procedure, including those at a higher privilege level. Operation codes | B. GATE Branch gateway Format B.GATE ra,rb 8 6 6 12 Descnotion A virtual address is computed from the sum of the contents of register ra and register rb. The contents of 16 bytes of memory using the little-endian byte order is fetched. A branch and link occurs to the low-order octlet of the memory data, and the successor to the current program counter, catenated with the current execution privilege is placed in register 0. The privilege level is set to the contents of the low-order two bits of the memory data. Register 1 is loaded with the high- order octlet of the memory data. An access disallowed exception occurs if the new privilege level is greater than the privilege level required to write the memory data, or if the old privilege level is lower than the privilege required to access the memory data as a gateway. An access disallowed exception occurs if the target virtual address is a higher privilege than the current level and gateway access is not set for the gateway virtual address, or if the access is not aligned on a 16-byte boundary. A reserved instruction exception occurs if the rb field is non-zero. Definition def BranchGateway(ra,rb,rc) as a «- RegRead(ra, 64) b <- RegRead(rb, 64) VirtAddr <- a +b if VιrtAddr 3 0 ≠ 0 then raise AccessDisallowedByVirtualAddress endif if re ≠ 0 then raise Reservedlnstruction endif c *- LoadMemory(VιrtAddrJ 28 L) ex <-c-i 27 6 I' ProgramCounterδ3 2+1 N PπvilegeLevel ProgramCounter «- C53 2 " 0 2 PrivilegeLevel <- cι ..o RegWrite(rc, 128, ex) enddef Exceptions Reserved Instruction Access disallowed by virtual address Access disallowed by tag Access disallowed by global TLB Access disallowed by local TLB Access detail required by tag Access detail required by local TLB Access detail required by global TLB Cache coherence intervention required by tag Cache coherence intervention required by local TLB Cache coherence intervention required by global TLB Local TLB miss Global TLB miss Branch Immediate This operation branches to a location that is specified as an offset from the program counter, optionally saving the value of the program counter into register 0. Format op target 31 24 23 op offset 8 24 Description If requested, the address of the instruction following this one is placed into register 0. Execution branches to the address specified by the offset field. Definition def Branchlmmedιate(op. offset) as if (op = B.LINK.I) then RegWrιte(0, 64, ProgramCounter + 4) endif ProgramCounter <- ProgramCounter + (offset ϋ " offset II 0 2 ) enddef Exceptions none Execute These operations perform calculations with two general register values, placing the result in a general register. Oρe r a pn codes Format op rc=ra,rb 31 24 23 IS 17 12 11 6 5 Description The contents of registers ra and rb are fetched and the specified operation is performed on these operands. The result is placed into register re. Definition def Execute(op.ra.rb,rc) as a «- RegRead(ra.64) b <- RegRead(rb, 64) case op of EROTL c «- a (6 3_ b5 o) o II a 63 (s-i-b : - 3 ) E ROTR c *~ a (b 5 0-1) 0 " a 63 b 5 o ESHL c*- a (63 _ b5o) 0 IIO & 50 ESHLO 'f a6363- 5 . 0 ≠a s3 0+1 thβn raise FixedPointArithmetic endif c^ (63 _ b5o) 0 IIO b 5- E SHL UO lf a 6364-b 5 . 0 ≠ ° then raise FixedPointArithmetic endif c^ a (63 _ b5o) 0 IIO b 50 ESHR c^ a b 5-0 |ia 63 b5 _ o EUSHR 1^5.0 1 a 63 b 5 o EADD c *- a + b E.ADD.O t «- (a 6 3 II a) + (b 6 3 II b) raise FixedPointArithmetic endif c*-t63 0 EADDUO t«-(0 1 lla) + (0 1 lib) if t6 ≠ 0 then raise FixedPointArithmetic endif c *- t630 E AND c <- a and b E OR c «- a or b E XOR c <- a xor b E ANDN c <- a and not b E NAND c <- not (a and b) E NOR c <- not (a or b) E XNOR c <r- not (a xor b) E ORN c «- a or not b E LMS if (a=0) then c «- -1 else for ι «— 0 to 63 if aβ3 ι = (ag3~' II not a 63 ) then c *- ι endif endfor endif E ULMS if (a=0) then c <- -1 else for ι «— 0 to 63 ιf a 6 3 ι = (0 63 -' II 1 ) then c <- i endif endfor endif E ASUM t «- a & b u «- (t63 ι&0x5555555555555555) + (t&0x5555555555555555) v «- (U63 2&0x3333333333333333) + (u&0x3333333333333333) w «- (v 6 3 4&0x707070707070707) + (v&0x0707070707070707) x ♦- ( 63 8&0xf000f000f000f) + (w&OxOOOfOOOfOOOfOOOf) C ♦ - X52 48 + x 36 32 + *20 16 + x 4 0 E SELECT 8 for i <- 0 to 7 ] «- b3*, + 2 3*ι C8'ι+7 8 * ι «- a8 * |+7 8 * j endfor endcase RegWrιte(rc, 64 c) enddef Exceptions Fixed-point arithmetic Execute Copy Immediate This operation produces one immediate value, placing the result in a general register. Operation codes I E.COPY.I Execute copy immediate Format E.COPY.I ra=imm Description A 64-bit immediate value is sign-extended from the 18-bit imm field. The result is placed into register ra. Definition def ExecuteCopylmmedιate(op.ra.ιmm) as RegWrιte(ra, 64, ι) enddef Exceptions none Execute Field Immediate These operations perform calculations with one or two general register values and two immediate values, placing the result in a general register. Operation codes Format op rb=ra,ιshιft,ιsιze 31 24 23 18 17 12 11 6 5 0 I op j ra I rb I ishift | isizea | 8 6 6 6 6 Description The contents of register ra, and if specified, the contents of register rb is fetched, and 6-bit immediate values are taken from the 6-bit ishift and isizea fields. The specified operation is performed on these operands. The result is placed into register rb. Definition def ExecuteFιeldlmmedιate(op,ra rb ishift isizea) as a <- RegRead(ra 64) isize «- ιsιzea+1 if (ιshιft+ιsιze>64) raise Reservedlnstruction endif case op of E DEPI b <- a 6 s ^ 2 1 β Sh,ft H a ιsιze -ι o H 0 ιshlft E UDEPI b <_ o-34-ιsιz β -ιs h ιft || aι S|Ze .ι 0 » 0 ,shl,t E MDEPI m <- RegRead(rb 64) b *- m63 ιsιze+ιshιft H Sιsιze-1 0 H 0 E WTHI ll a!SlZ3 - shlft - 1 ιshlft izβ+ishifM ishift endcase RegWrite(rb, 64, b) enddef Exceptions Reserved instruction Execute Immediate These operations perform calculations with one general register value and one immediate value, placing the result in a general register. Operation codes Format op rb=ra,imm 3 1 24 23 1 8 1 7 1 2 1 1 op ra rb imm 12 Description The contents of register ra is fetched, and a 64-bit immediate value is sign- extended from the 12 -bit imm field. The specified operation is performed on these operands. The result is placed into register re. Definition def Executelmmedιate(op,ra,rb.ιmm) as a <- RegRead(ra, 64) case op of E AND I b <- a and ι E OR I b «- a or i E NAND I b <- a nand i E NOR.I b <- a nor i E XOR I b <- a xor i E.ADD.I: b •»- a + i E.ADD.I.SO: t «- (a63 II a) + 063 " ') i f t64 ≠ t63 then raise FixedPointArithmetic endif b <- 163..0 endcase RegWπte(rb, 64, b) enddef Exceptions Fixed-point arithmetic Execute Immediate Reversed These operations perform calculations with one general register value and one immediate value, placing the result in a general register. Operation codes Format op rb=imm,ra Descπotion The contents of register ra is fetched, and a 64-bit immediate value is sign- extended from the 12 -bit imm field. The specified operation is performed on these operands. The result is placed into register re. Definition def .ra.rb,ιmm) as a <- RegRead(ra, 64) case op of E.SUB. I: b «- i - a E.SUB. I.SO: t «- ("63 I' i) - (a63 II a) if t64 -≠ t63 then raise FixedPointArithmetic endif b <- tβ3. o E.SET.I.E: b <r- (i = a) 64 E.SET.I.NE: b <r- (i ≠ a) 64 E.SET.I.L: b «- (■ < a) 64 E.SET.I.GE: b «- (i > a) 64 E.SET.I.UL: b «- ((0 II i) < (0 II a)) 64 E.SET LUGE- b «- ((0 II i) > (0 II a)) 64 E.SUB. I.E. b <- i - a if i ≠ a then raise FixedPointArithmetic endif E.SUB. I. NE. b «- i - a if i = a then raise FixedPointArithmetic endif E.SUB. I. L: b <— i - a if i > a then raise FixedPointArithmetic endif E.SUB. I.GE: b <- i - a if i < athen raise FixedPointArithmetic endif E.SUB. I. UL: b <- i - a if (0 II i) > (0 II a) then raise FixedPointArithmetic endif E.SUB. I. UGE: b «- i - a if (0 II i) < (0 II a) then raise FixedPointArithmetic endif endcase RegWrιte(rb, 64, b) enddef Exceptions Fixed-point arithmetic Execute Inolace These operations perform calculations with three general register values, placing the result in the third general register. Operation codes I E.MSHR Execute merge shift right Format E.MSHR rc=ra,rb,rc 31 24 23 1 8 17 1 2 1 1 6 5 0 j E.MINOR | ra j rb | re I op I 8 6 6 6 6 Descnpfon The contents of registers ra, rb, and re are fetched. The specified operation is performed on these operands. The result is placed into register re. Definition def ExecuteTernarylnplace(op.ra.rb,rc) as a <- RegRead(ra. 64) b <- RegRead(rb. 64) c <- RegRead(rc, 64) case op of E.MSHR ύ * ~ c 63 64-b 5 0 ll a 63 b 5 0 endcase RegWrιte(rc, 64, d) enddef Exceptions none Execute Reversed These operations perform calculations with two general register values, placing the result in a general register. Operation codes Format op rc=rb,ra 31 24 23 18 17 12 11 6 5 1 E.MINOR ra rb re op 8 6 6 6 6 Description The contents of registers ra and rb are fetched and the specified operation is performed on these operands. The result is placed into register re. De ιnιtιon def ExecuteReversed(op.ra.rb.rc) as a <- RegRead(ra, 64) b *- RegRead(rb. 64) case op of E.SUB: c <- b - a E.SUB.O: 1 «- (b 6 3 II b) - 063 II a) if t64 ≠ t63 then raise FixedPointArithmetic endif c «- t63 .0 E.SUB. UO- t <- (0 1 ll b) - (0 1 II a) raise FixedPointArithmetic endif c <- t63 .0 E.SUB. E: c <- b - a if b ≠ a then raise FixedPointArithmetic endif E.SUB. NE c <- b - a if b = a then raise FixedPointArithmetic endif E.SUB.L: c «- b - a if b > a then raise FixedPointArithmetic endif E.SUB.GE. c «- b - a if b < a then raise FixedPointArithmetic endif E.SUB UL. c «- b - a if (0 II b) > (0 II a) then raise FixedPointArithmetic endif E.SUB. UGE. c «- b - a if (0 II b) < (0 II a) then raise FixedPointArithmetic endif E.SET.E. c «- (b = a) 64 E.SET.NE: c <- (b ≠ a) 64 E.SET.L: c <- (b < a) 64 E.SET.GE. c <- (b > a) 64 E.SET.UL c «- ((0 II b) < (0 II a)) 64 E.SET UGE c «- ((0 II b) > (0 II a)) 64 endcase RegWrite(rc, 64, c) enddef Exceptions Fixed-point arithmetic Execute Short Immediate These operations perform calculations with one general register value and one immediate value, placing the result in a general register. Operation codes Format op rb=ra,sιmm 31 24 23 18 1 12 11 6 5 I E.MINOR I ra T rb simm op Descnptipn The contents of register ra is fetched, and a 6-bit immediate value is taken from the 6-bit simm field. The specified operation is performed on these operands. The result is placed into register rb. Definition def ExecuteShortlmmedιate(op ra rb.simm) as a <- RegRead(ra, 64) case op of E SHUFFLE I 0 b <- a 1 35 for x <- 0 to 7, for y <- 0 to x-1 , for z «- 1 to x-y if simm = ((x"x'x-3 * x * x-4 * x)/6-(z"z-z)/2+x * z+y+1) then for ι «— 0 to 63 bi <- a<ι 7 x ii ι y+z _* y ii ι x _* y+2 n ι y _. o ) end endif endfor, endfor, endfor 36 255 raise Reservedlnstruction endcase E ROTR I E.SHL.I: b «- a 63 . sιmm o II 0 sι m E.SHL.I.0: raise FixedPointArithmetic endif b «- a 63-sιmm o II 0 Sim E.SHL.I. UO: if 363. 64-sιmm ≠ 0 then raise FixedPointArithmetic endif b <- a 63 . sιmm o II O sιmm E.SHR.I. endcase RegWπte(rb. 64. b) enddef Exceptions Fixed-point arithmetic Execute Short Immediate Inclace These operations perform calculations with one general register value and one immediate value, placing the result in a general register. Operation codes I E.MSHR. I Execute merge shift right immediate Format op rb=ra,simm 31 24 23 18 17 12 11 6 5 0 I E.MINOR I ra j rb I simm | op | 8 6 6 6 6 Description The contents of registers ra and rb are fetched, and a 6-bit immediate value is taken from the 6-bit simm field. The specified operation is performed on these operands. The result is placed into register rb. Definition def ExecuteShortlmmediatelnplace(op.ra.rb.simm) as a <- RegRead(ra, 64) b <- RegRead(rb. 64) case op of E.MSHR. I: C <- b63..63-simm H a63..sιmrr. endcase RegWrite(rb, 64, c) enddef Exceptions Fixed-point arithmetic Execute Swizzle Immediate These operations perform calculations with a general register value and twc immediate values, placing the result in a general register. Operation codes I E.SWIZZLE.I Execute swizzle immediate 18 17 12 11 6 5 0 op I ra I rb I icopy | iswap | Description The contents of register ra is fetched, and 6-bit immediate values are taken from the 6-bit icopy and iswap fields. The specified operation is performed on these operands. The result is placed into register rb. Definition def GroupSwizzle!mmediate(op,ra.rb, icopy. iswap) as a <r- RegRead(ra. 64) for i <- 0 to 63 bi <— a(i & icopy) Λ iswap endfor RegWrιte(rb, 63, b) enddef Exceptions Reserved instruction Execute Ternary These operations perform calculations with three general register values, placing the result in a fourth general register. Qperatipn codes Format op rd=ra,rb,rc Descriptipn The contents of registers ra, rb, and re are fetched. The specified operation is performed on these operands. The result is placed into register rd. Definition RegWrite(rd, 64, d) enddef Exceptions none Floating-point These operations perform floating-point arithmetic on two floating-point operands. Ooe atιon codes Format F.op. prec. round rc=ra,rb Descrotipn The contents of registers is register pairs specified by ra and rb are combined using the specified floating-point operation. The operation is rounded using the specified rounding option or using round-to-nearest if not specified. The result is placed in the register or register pair specified by re. If a rounding option is specified, the operation raises a floating-point exception if a floating-point invalid operation, divide by zero, overflow, or underflow occurs, or when specified, if the result is inexact. If a rounding option is not specified, floating-point exceptions are not raised, and are handled according to the default rules of IEEE 754. If F128 precision is specified, ra, rb and re refer to an aligned pair of registers, and a reserved instruction exception occurs if the low-order bit of these operands is set. De f inition def FloatιngPomt(op,prec round, ra.rb. re) as a «- F(prec RegRead(ra, (prec≤64) ? £4 prec)) b *- F(prec. RegRead(rb, (prec 64) 7 64 prec)) if round≠NONE then if ιsSιgnallιngNaN(a) I ιsSιgnallιngNaN(b) raise FloatingPointException endif case op of F DIV if b=0 then raise FloatingPointAπthmetic endif others endcase endif case op of F ADD c <- a+b F MUL c <- a"b F DIV c *r- a/b endcase case round of X N T F C NONE endcase RegWrιte(rc, (prec<64) 64 prec, PackF(prec.c)) enddef Exceptions Reserved instruction Floating-point arithmetic Floating-point Reversed These operations perform floating-point arithmetic on two floating-point operands. Oceraz'cn codes 127 microunity Format F.op. prec. round rc=rb,ra 31 24 23 1 8 1 7 1 2 1 1 6 5 | F.prec ra rb re | op.round | 8 Description The contents of registers or register pairs specified by ra and rb are combined using the specified floating-point operation. The operation is rounded using the specified rounding option or using round-to-nearest if not specified. The result is placed in the register or register pair specified by re. If a rounding option is specified, the operation raises a floating-point exception it a floating-point invalid operation, divide by zero, overflow, or underflow occurs, or when specified, if the result is inexact. If a rounding option is not specified. floating-point exceptions are not raised, and are handled according to the deiau.: rules of IEEE 754. If F128 precision is specified, ra, rb and re refer to an ahgned pair of registers, and a reserved instruction exception occurs if the low-order bit of these operands is set. Definition def FloatιngPoιntReversed(op. prec. round. ra.rb. re) as a *- F(prec, RegRead(ra, (prec<64) ? 64 prec)) b <- F(prec, RegRead(rb, (prec<64) ? 64 prec)) if round≠NONE then if ιsSιgnallιngNaN(a) I ιsSιgnallιngNaN(b) raise FloatingPointException endif case op of F SET.L, F SET GE. F SET.NL F SET NGE. if ιsNaN(a) I ιsNaN(b) then raise FloatingPoiniΛπthmetic endif others endcase endif case op of F SUB c <- b-a F SET NUGE F SET L c <- b l? ≥a F SET NUL, F SET GE c «- b^o F SET UGE. F SET NL c «- b ? ≥a F SET UL. F SET NGE c <- b 7 <a F SET UE c «- b ? =a F SET NUE c <- b"=a F SET E c *- b=a F SET NE c *- b≠a endcase case op of F SUB destprec <- prec F SET NUGE F SET NUL. F SET UGE F SET UL F SET L F SET GE. F SET E F SET NE, F SET UE, F SET NUE destprec <- INT endcase case round of X N T F C NONE endcase case destprec of 16, 32, 64, 128 RegWrιte(rc, (destprec<64) 64 destprec, PackF(destprec.c)) INT RegWrιte(rc, 64, c) endcase enddef Exceptions Reserved instruction Floating-point arithmetic Floating-point Ternary These operations perform floating-point arithmetic on three floating-point operands.. Operation codes Format F operation. type rd=ra.rb ? rc Description The contents of registers or register pairs specified by ra and rb are multiplied together and added to or subtracted from the contents of the register or register pair specified by re. The result is rounded to the nearest representable floating¬ point value in a single floating-point operation. The result is placed in the register or register pair specified by rd. Floating-point exceptions are not raised, and are handled according to the default rules of IEEE 754. These instructions cannot select a directed rounding mode or trap on inexact. If F128 precision is specified, ra, rb, re and rd refer to an aligned pair of registers, and a reserved instruction exception occurs if the low-order bit of these operands is set. Definition def FloatιngPoιntTernary(op.ra,rb rc.rd) as case op of FMULADD16 FMULSUB 16 prec *- 16 FMULADD32. FMULSUB32 prec «- 32 FMULADD64, FMULSUB64: prec <- 64 FMULADD128, FMULSUB 128: prec <r- 128 endcase a <- F(prec. RegRead(ra, (prec<64) ? 64 . prec)) b <- F(prec. RegRead(rb, (prec<64) ? 64 : prec)) c <- F(prec, RegRead(rc. (prec<64) ? 64 : prec)) case op of FMULADD16, FMULADD32. FMULADD64, FMULADD128. d <- a * b+c FMULSUB16, FMULSUB32. FMULSUB64. FMULSUB 128. d <- a * b-c endcase RegWπte(rd, (prec<64) . 64 : prec. PackF(prec.d)) enddef Exceptions Reserved instruction Floating-point arithmetic Floating-point Unary These operations perform floating-poin: arithmetic on one floating-point operand Oce r a:cn codes Format F.op. prec. round rc=ra 3 1 24 23 1 8 1 7 1 2 1 1 6 5 Descnction The contents of the register or register pair specified by ra is used as the operand of the specified floating-point operation. The operation is rounded using the specified rounding option or using round-to-nearest if not specified. The result is placed in the register or register pair specified by re. If a rounding option is specified, the operation raises a floating-point exception if a floating-point invalid operation, divide by zero, overflow, or underflow occurs, or when specified, if the result is inexact. If a rounding option is not specified, floating-point exceptions are not raised, and are handled according to the default rules of IEEE 754. If F128 precision is specified, ra or rb or both refer to an aligned pair of registers, and a reserved instruction exception occurs if the low-order bit of these operands is set. Definition def FloatιngPoιntUnary(op, prec, round. ra.rb re) as if op = F FLOAT then a «- RegRead(ra, 64) else a «- F(prec. RegRead(ra, (prec<64) ? 64 prec)) endif case op of F ABS c *- -a else c «- a endif F NEG. c <- -a F SQR. c <- Va F FLOAT. F.SINK, F INFLATE, F DEFLATE c <- a endcase case op of F ABS. F NEG F.SQR, F FLOAT destprec <- prec F SINK destprec «- INT F INFLATE destprec <- prec + prec F.DEFLATE: destprec <- prec / 2 endcase case round of X: N T F C: NONE: endcase case destprec of 16, 32, 64, 128: RegWrιte(rc, (destprec<64) ■ 64 : destprec, PackF(destprec.c)) INT: RegWrite(rc. 64, c) endcase enddef Exceptions Reserved instruction Floating-point arithmetic Group These instructions take two operands perform a group of operations on partitions of bits m the operands, and catenate the results together Ocerarcn codes 1_ *G AND does not require a size specihcation and is encoded as G AND 1 15 G ANDN does not require a size specihcation, and is encoded as G ANDN 1 G ANDN is used as the encoding for G SET L 1, and reversing the operands, for G SET UL 1 16 G GATHER 128 is encoded as G GATHER 1 17 G MUL 1 is used as the encoding for G UMUL 1 ^G NAND does not require a size specification, and is encoded as G NAND. l ^ 9 G NOR does not require a size specification, and is encoded as G.NOR.l 20 G.OR does not require a size specification, and is encoded as G.OR. l. 2 1 G ORN does not require a size specification, and is encoded as G.ORN.l. G ORN is used as the encodinε for G.SET.UGE 1 , and bv reversing the operands, for G.SET GE 1 22 G SCATTER.128 is encoded as G SCATTER.1 2 -*G.XNOR does not require a size specification, and is encoded as G.XNOR.l. G.XNOR is used as the encoding for G.SET.EJ. 2 G.XOR does not require a size specification, and is encoded as G.XOR.l. G.XOR is used as the encoding for G.ADD.l, G.SUB 1 and G SET.NEJ. Format 31 24 23 18 1 7 12 1 1 6 5 G.size ra rb re op Description Two values are taken from the contents of registers or register pairs specified by ra and rb. The specified operation is performed, and the result is placed in the register or register pair specified by re. A reserved instruction exception occurs if rcrj is set, and for certain operations, if Definition def Group(op.sιze,ra,rb,rc) case op of G MUL, G U MUL, G DIV, G U DIV a *- RegRead(ra, 64) b <- RegRead(rb, 64) G ADD. G SUB, G SET L. G SET UL. G SET E, G SET NE, G SET GE, G SET UGE G AND, G OR, G XOR. G ANDN, G NAND G NOR, G XNOR, G ORN, G GATHER G SCATTER a <- RegRead(ra, 128) b <- RegRead(rb 128) G COMPRESS G ROTL G ROTR. G SHL G SHR, G U SHR. G POLY a «- RegRead(ra, 128) b <- RegRead(rb, 64) G EXPAND G U EXPAND a «- RegRead(ra. 64) b «- RegRead(rb.64) endcase case op of GADD for i <- 0 to 128-sιze by size c ι+sιze-1 ι *~ ai+size- * , + bι+sιze-1 ι endfor G MUL for i «- 0 to 64-sιze by size C2 * (ι+sιz β )-ι 2 * ι ÷-(a 3 ,z5-ι sl2e II a s ,ze-ι +l ,) * (b s ,ze-ι sιze II b sl2 β- . .) endfor G U MUL for i <— 0 to 64-sιze by size C2 * (ι + 3ize)-ι 2 * ι <-(0 sz II a 3ιze-1+l ,) * (0 sιze II b s ,ze- ι ,) endfor GDIV if (b = 0) or ( (a = (1 UO 63 )) and (b = 1 64 ) ) then c <- undefined else q •*- a/b r <- a - q"b c «- 63 0 'I 630 endif G U DIV c «- undefined else q «- (0 II a) / (0 II b) r «- a - q"b c <- r 63 o H q630 endif GAND c «- a and b GOR c <- a or b GXOR c <- a xor b GANDN c <- a and not b GNAND c «- not (a and b) GNOR c <- not (a or b) GXNOR c -j— not (a xor b) GORN c *- a or not b GPOLY P[ι] ^ (P[ι-1]0 7 (0 64 II b) 0 12 8) xor (p[ι-1] 0 II p[ι-1]ι 2 7 1) endfor c «- pfsize] G GATHER for k <- 0 to 128-sιze by size for i <— k to k+sιze-1 by 1 if a, then I + 1 endif endfor j <- k+sιze-1 for ι <- k+sιze-1 to k by -1 if -a, then C) «- b, j ■ * — J - 1 endif endfor endfor G SCATTER for k <- 0 to 128-sιze by size J«-k for ι «— k to k+sιze-1 by 1 if a, then c,<-b, J «-J + 1 endif endfor ] <- k+sιze-1 for i «■- k+sιze-1 to k by -1 if -a, then c, «-b, endif endfor endfor G COMPRESS for i «- 0 to 64-sιze by size Cι+sιze-1 ι * • — aι-H+sιze-*-'o&(sιze-i)) ι+ι+(b&(sιze-i)) endfor G EXPAND for i <- 0 to 64-sιze by size Cι+ι+sιze+sιze- ι 1 I+I t «—- -l))ι M ι a + sιze-1 i M M 0b&(sιze i) endfor G U EXPAND for i <— 0 to 64-sιze by size r Cι+ι+sιze+sιze- .1, i+i t <—- 0 ι-.S'23 — (b&( size —1)) 1 " 1 aι + sιze-11 I "I n 0b&(sιze-') endfor G ROTL for i - 0 to 128-sιze by size c ι+sιze-1 ι *— a ι+sιze-1-(b&(sιze-1)) ι " a ι+sιze-1 ι+sιze-1-(b&(sιze-l)) endfor G ROTR for i «— 0 to 128-sιze by size Cι+sιze-1 i *- l+ (b&(sιze-i))-ι ι H a, +S ιze-l ι+(b&(sιze-J) endfor GSHL for i <- 0 to 128-sιze by size Cι+sιze-1 ι *- a, + sιze-ι-(b&(sιz6-l)) ι » 0 & ( s,ze P endfor GSHR for i •<— 0 to 128-sιze by size Cι+sιze-1 ι *- aι+sιze-1 ( sιze-i )n a l+s , ze -1 ι + (b&(sιze-l )) endfor G U SHR for i <r- 0 to 128-sιze by size c. +S ιzβ-ι ι ^ 0 b ^ sιzs - 1 )ll a l +sι29- ι ,+(b&(sιzβ-i)) endfor endcase case op of G ADD, G MUL. G UMUL, G DIV G UDIV G AND, G OR, G XOR, G ANDN, G NAND, G NOR G XNOR. G ORN, G EXPAND G U EXPAND G SHL. G SHR, G U SHR, G GATHER. G SCATTER, G POLY RegWrιte(rc, 128. c) G COMPRESS RegWπte(rc 64, c) endcase enddef Exceptions Reserved Instruction Group Extract Immediate These operations perform calculations with two general register pair values and a small immediate field, placing the result in a third general register pair. Operation codes Format G.EXTRACT.I.size rc=ra,rb, shift Description The contents of registers pairs specified by ra, and rb are fetched. The specified operation is performed on these operands. The result is placed into the register pair specified by re. Definition def GroupExtractlmmedιate(op,ra.rb.rc.ιshιfta) as a «- RegRead(ra, 128) b <- RegRead(rb, 128) ab <- a II b opimm <- op2 o H ishifta case opimm of 0 2 raise Reservedlnstruction 3 5 6 1 1 12..2 24 .4 48 9 96 1 192 . 384.. endcase shift *- opιmrτi6 o & (sιze+sιze-1) if shift > size then sex <- (opimm & (size+size)) ≠ 0 if sex then for i <— 0 to 128-sιze by size c ι+sιz9-ι i <— a. l-r,.l -^' .-j ι£ "-; — " -ji^- _ *~ . I II | + ι_ 3 ι 2e+S | Z g.ι i + i + shift endfor else for ι <- 0 to 128-sιze by size Cι + 5ize-ι i <- 0 s |T "; " z =ll ab| +iJ . 3l2e+S | 2e- ι i + i + shift endfor endif else for i <— 0 to 128-sιze by size c ι+sιze-ι ι *~ a )+ ι+shιfr-rs z5-ι i+i-rs ift endfor endif RegWrιte(rc, 128, c) enddef Exceptions Reserved instruction Group Field Immediate These operations perform calculations with one or two general register values and two immediate values, placing the result in a general register. Ooer aτicn codes Format op. size rb=ra, ishift, isize 31 24 23 18 17 12 11 6 5 0 I op I ra I rb I ishifta | isizea | 8 6 6 6 6 Description The contents of register ra, and if specified, the contents of register rb is fetched, and 6-bit immediate values are taken from the 6-bit ishifta and isizea fields. The specified operation is performed on these operands. The result is placed into register rb. Definition case op of G DEPI for i <- 0 to 128-sιze by size , -Size -isize — ishift „ n mshift bι+sιzβ-1 i *- a j+ιs , zβ _ι " a '+ιsιze-ι ι II 0 l5πιπ endfor G UDEPI for i <- 0 to 128-sιze by size h u ι+ «s.ιz ,e Λ - ι1 i * *— ^ u312 - 3 - 1 - 5126 - 1 - 5 -^' 1 I "I a d ι-ri rsιze „- ι1 ι I "I n u 'S ift endfor G MDEPI m <- RegRead(rb, 128) for i «- 0 to 128-sιze by size bι+sιze-1 ι *- rnι+sιze- i+isizs+isriift " a n-ιsιze-l ι " m ι+ιshιft-l ι endfor G WTHI for i «- 0 to 128-sιze by size - _ „sιze -ιsιze π _ bι+sιze-1 ι «- a i+ιsιze +ιshlft _ 1 » aι-ιsιze+ιs ιft-1 ι+ιshιft endfor G UWTHI for i <- 0 to 128-sιze by size bι + sιze-1 i <- 0 sιze'ιsιze II a l _ lS!ze . HSh |f t- -| l + ,s ιτt endfor endcase RegWrιte(rb, 128, b) enddef Exceptions Reserved instruction Group Inolace These operations perform calculations with three general register values, placing the result in the third general register. Operation codes G.MSHR.2 Group merge shift right pecks G.MSHR 4 Group merge shift right nibbles G.MSHR.8 Group merge shift right bytes G.MSHR.16 G UrloluUμp m I I IedrgjeC shl 1i 1f 1t L r πigv-jhi iti d uouuuublieetiss G.MSHR.32 Group merge shift right quadlets G.MSHR.64 G uiruouupμ m i πec-ri gLjec s ohi πifiti r I iIgLJhI ItI o Uc/tilieotisa G. MSHR 128 Group merge shift right hexlets Format G MSHR.size rc=ra,rb,rc Description The contents of register pairs specified by ra and re and register rb are fetched. The specified operation is performed on these operands. The result is placed into the register pair specified by re. A reserved instruction exception occurs if rarj or rco is set. Definition def GroupTernarylnplace(op,ra.rb,rc) as a <- RegRead(ra. 128) b «- RegRead(rb, 64) c <r- RegRead(rc, 128) case op of G MSHR for i <- 0 to 128-sιze by size dι+sιze-1 ι *~ c ι+sιze-1 ι+ι+sιzβ-l-(b&(sιze-1)) ■■ a n-sιze-1 ι+(b&(sιze-l)) endfor endcase RegWrιte(rc. 128. d) enddef Exceptions Reserved Instruction Group Reversed These operations take two values from a pair of registers, perform operations on groups of bits in the operands, and place the concatenated results i in a register. Operat i on codes Format 3 1 24 23 1 8 1 7 1 2 1 1 6 5 G.size ra rb re op Descπot'pn Two values are taken from the contents of registers ra and rb. The specified operation is performed, and the result is placed in register re. Definition def GroupReversed(op size.ra.rb.rc) a «- RegRead(ra 128) b <- RegRead(rb 128) case op of G SUB for i <- 0 to 128-sιze by size c ι ^-sιze-1 i *- b|+sιze-l ι * a n-sιze-l ι endfor G SET L for i <— 0 to 128-sιze by size Cι+sιze-1 ι * > ~ (bι+sιze-1 ι aι+sιze-1 ι) sιze endfor G SET.UL for i «— 0 to 128-sιze by size Cι+sιze-1 i <- (° H b+sιze-1 ι < 0 II a (+sιze -i ι) sιze endfor G SET E for i <- 0 to 128-sιze by size c ι+sιze-1 ι *— (bι+sιze-1 i = a ι+sιze-1 i) ' endfor G SET NE for i <— 0 to 128-sιze by size Cι+sιze-1 ι *- (bι+sιze-1 ι ≠ a ι+sιze-1 i) endfor G SET GE for i <— 0 to 128-sιze by size Cι+sιze-1 ι *— (bι+sιze-1 ι ≥ Sι + sιze-1 ι ) endfor G SET UGE for i <- 0 to 128-sιze by size Cι+sιze-1 i «- (0 II b, +S ιzδ-i ι ≥ 0 II a l+sιze-1 ,)sιze endfor endcase RegWπte(rc. 128. c) enddef Exceptions Reserved Instruction Group Short Immediate These operations take operands from a pair of registers, perform operations on groups of bits in the operands, and place the concatenated results in a register or pair of registers. Operation codes Format G. op. size rb=ra,simm DescnpTipn A 128-bit value is taken from the contents of the register pair specified by ra. The second operand is taken from simm. The specified operation is performed, and the result is placed in the register pair specified by rb. This instruction is undefined and causes a reserved instruction exception if the simm field is greater or equal to the size specified. Definition def GroupShortlmmedιate(op, size. ra.rb, simm) case op of G COMPRESS I, G.U COMPRESS I , 128) if simm≥size then raise Reservedlnstruction endif G ROTR I. G SHL I, G SHR I, G U SHR I. a *- RegRead(ra, 128) shift «- opo II simm if shift≥size then raise Reservedlnstruction endif G EXPAND I. G U EXPAND I a <- RegRead(ra. 64) shift <- opo II simm if shrft>sιze+sιze then raise Reservedlnstruction endif endcase case op of G COMPRESS I for i <- 0 to 64-sιze by size bι+sιze-1 ι <— ai+i+size-l -rSiTim ι+ι+sιmm endfor G EXPAND I for i <— 0 to 64-sιze by size h . _ size -shift ii II -.shift bι+ι+sιze- sιze-1 ι+ι *- a ] _. ιze _ 1 n a + sιze -1 1 " 0 endfor G U EXPAND I for ι <— 0 to 64-sιze by size h . <— n 3lZ6 -Shift | | I I —Shift Dι+ι+sιze+sιze-1 ι+ι *• — 0 " aμ + sιze -1 ι " 0 endfor G SHL I for i <— 0 to 128-sιze by size bι+sιze-1 ι «- aι+sιze-1 -shift ι H 0 shlft endfor G SHR I for i <— 0 to 128-sιze by size h < — Shift II Dι+sιze-1 ι *- a l→ , sιze _ 1 " a+sιze -1 j+shιft endfor G U SHR I for i «— 0 to 128-sιze by size bι+size-1 ι <- 0 ' " aι^sιze -1 i+shift endfor endcase case op of G EXPAND I, G U EXPAND I. G SHL I. G SHR. I, G U.SHR I RegWnte(rb, 128, b) G COMPRESS I RegWrιte(rb, 64, b) endcase enddef Exceptions Reserved Instruction Group Short Immediate Inolace These operations take operands from two register pairs, perform operations on groups of bits in the operands, and place the concatenated results in the second register pair. Operation codes Format 31 24 23 1 8 1 7 1 2 1 1 6 5 G.size ra rb | s imm | op | Description Two 128-bit values are taken from the contents of the register pairs specified by ra and rb. A third operand is taken from simm. The specified operation is performed, and the result is placed in the register pair specified by rb. This instruction is undefined and causes a reserved instruction exception if the simm field is greater or equal to the size specified. Definition def GroupShortlmmedιatelnplace(op, size, ra.rb, simm) a <- RegRead(ra, 128) b <- RegRead(rb, 128) shift <- opo II simm if shift≥size then raise Reservedlnstruction endif endcase case op of G MSHR I for i <- 0 to 128-sιze by size c ι+sιze-1 ι *- bι+sιze -1 ι+sιze -1-shιft " aι+sιze -1 j+shift endfor endcase RegWrιte(rb, 128, c) enddef Exceptions Reserved Instruction Group Shuffle Immediate These operations take operands from a pair of registers, perform operations on groups of bits in the operands, and place the concatenated results in a register or pair of registers. Operation codes Format op.a.b.c rc=ra,rb 31 24 23 18 1 7 12 1 1 6 5 op ra rb re s i mm Description A 128-bit value is taken from the contents of the register pair specified by ra. The second operand is taken from simm. The specified operation is performed, and the result is placed in the register pair specified by re. This instruction is undefined and causes a reserved instruction exception if the simm field is greater or equal to the size specified. Definition def GroupShufflelmmedιate(op.ra.rb.rc.sιmm) case op of G SHUFFLE.I: a <- RegRead(ra, 64) b <- RegRead(rb. 64) G.SHUFFLE.I.4MUX. a <- RegRead(ra, 128) b <- RegRead(rb, 128) endcase raise Reservedlnstruction endif case op of G.SHUFFLE.I: ab «- a II b 0 c <- ab 1..56 for x <r- 0 to 7, for y <- 0 to x-1 , for z <- 1 to x-y if simm = ((x * x * x-3 * x * x-4 * x)/6-(z * z-z)/2+x * z+y+1 ) then for i <r- 0 to 127 C| *~ ab (' 6 x " -y *z .ι y ii ι x . 1 y . z ii ι y _ιo) end endif endfor. endfor, endfor 57.255 raise Reservedlnstruction endcase G SHUFFLE I 4MUX 0 t «- a 1 .56 for x <- 0 to 7, for y «- 0 to x-1 , for z <- 1 to x-y if simm = ((x * x * x-3 * x * x-4 * x)/6-(z"z-z)/2+x * z+y+1) then for i <- 0 to 127 l| *~ ^'c x 8 'y+z-l y 'I 'x-l yz " 'y-10 ) end endif endfor. endfor. endfor 57 255 raise Reservedlnstruction endcase for ι <- 0 to 127 C, *- t( l6 2 || b (l&63)+64 ii b 463 ) endfor endcase RegWrιte(rc, 128. c) enddef Excepf/σns Reserved Instruction Group Swizzle Immediate These operations perform calculations with a general register or register pair value and two immediate values, placing the result in a general register pair. Operation codes Format op rb=ra, icopy, iswap 31 24 23 18 17 12 11 6 5 op j ra I rb I icopya \ iswapa | Description The contents of register ra, or if specified, the contents of the register pair specified by ra is fetched, and 6-bit immediate values are taken from the 6-bit icopya and iswapa fields. The specified operation is performed on these operands. The result is placed into the register pair specified by rb. Definition def GroupSwιzzle(op,ra.rb, icopya. iswapa) as case op of G SWIZZLE. I. a <- RegRead(ra, 128) icopy <- 0 II icopya iswap <- 0 II iswapa G.SWIZZLE.I.COPY: a «- 0 64 II RegRead(ra, 64) icopy <- 1 II icopya iswap *- 0 II iswapa G.SWIZZLE.I. SWAP: a <- RegRead(ra, 128) icopy <- 1 II icopya iswap <- 1 II iswapa endcase for i <- 0 to 127 bi <— a(j & icopy) Λ iswap endfor RegWrιte(rb, 128, b) enddef Exceptions Reserved instruction Group Ternary These operations perform calculations with three general register values, placing the result in a fourth general register. Format G.op size rd=ra,rb,rc 25 G MULADD 1 is used as the encoding for G.UMULADD.l Description The contents of registers or register pairs specified by ra, rb, and re are fetched. The specified operation is performed on these operands. The result is placed into the register pair specified by rd. Definition def GroupTernary(op.sιze.ra rb rc.rd) as case op of G MUX a <- RegRead(ra, 128) b <- RegRead(rb. 128) c <- RegRead(rc, 128) G EXTRACT, G 8MUX, G TRANSPOSE 8MUX a <- RegRead(ra. 128) b «- RegRead(rb 128) c <- RegRead(rc 64) G MULADD G U MULADD a *- RegRead(ra, 64) b «- RegRead(rb 64) c <- RegRead(rc 128) G SELECT a «- RegRead(ra, 64) b <- RegRead(rb. 64) c «- RegRead(rc 64) endcase case op of G MUX d *- (b and a) or (c andnot a) G 8MUX for i <- 0 to 127 d. «- a(ι 6 3 n c lά63 ιι b ( 4 s 3 S4 ιι b l&63 ) endfor G TRANSPOSE 8MUX for i *- 0 to 127 ll *~ ^'6 6 I' '2 0 II '5 3 ) endfor for i <- 0 to 127 d| * " ^'6 3 'I C.&63 » b(,4S3) + 64 » b 1& 63 ) endfor G. EXTRACT d «- (a II b)( C &i27)+127 (C&127) G MULADD for i <— 0 to 64-sιze by size d2 * (ι+sιze)-1 2 * ι *- C2 * (ι+sιze)-1 2 * ι + (a sιze -ι s,zs ll a sι2 e-ι +l ,) * (b s , 2e -ι s,ze II b SIZ β- . .) endfor G U MULADD for i <— 0 to 64-sιze by size d2 * (ι+sιze)-1 2 * ι *- C2 * (ι+sιze)-l 2 * ι + (OJ'Z-PI a sιze- ι +1 ^ " (O^ ll bs.ze- . .) endfor G SELECT Exceptions Reserved instruction Group Floating-point These operations take two values from registers, perform floating-point arithmetic on groups of bits in the operands, and place the concatenated results in a register. Operation codes Format GF. op. prec. round rc=ra,rb 31 24 23 1 8 17 12 1 1 6 5 | GF.prec ra rb | re | op.round | Description The contents of registers ra and rb are combined using the specified floaring-point operation. The result is placed in register re. The operation is rounded using the specified rounding option or using round-to-nearest if not specified. If a rounding option is specified, the operation raises a floating-point exception if a floating point invalid operation, divide by zero, overflow, or underflow occurs, or when specified, if the result is inexact. If a rounding option is not specified, floating-point exceptions are not raised, and are handled according to the default rules of IEEff 754. Definition def GroupFloatιngPoιnt(op.prec round. ra.rb. re) as a <- RegRead(ra. 128) b <- RegRead(rb, 128) for i «- 0 to 128-prec by prec aι <- F(prec aι +pre c-i ι) bi «- F(prec.b| +D rec-1 ι) if round≠NONE then if ιsSιgnallιngNaN(aι) I ιsSιgnallιngNaN(bι) raise FloatingPomtException endif case op of F DIV if bι=0 then raise FloatingPointAnthmetic endif others endcase endif case op of GF ADD GF MUL GF endcase case op of GF ADD GF MUL. GF DIV c ι+prec-l i *- PackF(prec ci) endcase endfor endcase case round of X N T F C NONE endcase raise Reservedlnstruction endif RegWrιte(rc, 128, c) endcase enddef Exceptions Reserved instruction Floating-point arithmetic Group Floating-point Reversed These operations take two values from registers, perform floating-point arithmetic on groups of bits in the operands, and place the concatenated results in a register. Ooerat'cn codes Format GF.op. prec. round rc=rb,ra 31 24 23 1 8 1 7 1 2 1 1 6 5 0 | GF.prec | ra | rb | re | op.round | Description The contents of registers ra and rb are combined using the specified floating-point operation. The result is placed in register re. The operation is rounded using the specified rounding option or using round-to-nearest if not specified. If a rounding option is specified, the operation raises a floating-point exception if a floating-point invalid operation, divide by zero, overflow, or underflow occurs, or when specified, if the result is inexact. If a rounding option is not specified, floating-point exceptions are not raised, and are handled according to the default rules of IEEE 754 Def ition def GroupFloatιngPoιntReversed(op prec round ra.rb.rc) as a «- RegRead(ra. 128) b <- RegRead(rb. 128) for ι «- 0 to 128-prec by prec ai <- F(prec , a l+P rec-1 ι) bi «- F(prec,b, + p r ec-ι ι) if round≠NONE then if ιsSιgπallιngNaN(aι) I ιsSιgnallιngNaN(bι) raise FloatingPointException endif case op of GF SET L GF SET GE GF SET NL, GF SET NGE if ιsNaN(aι) I ιsNaN(bι) then raise FloatingPointAnthmetic endif endcase endif case op of GF SUB GF S GF.S GF S GF S GF SET UE GF SET NUE GF SET E GF.SET.NE: ci «- bi≠ai endcase case op of GF.SUB: Ci+prec-ιJ «- PackF(prec. ci) GF.SET.NUGE. GF.SET.NUL. GF.SET.UGE, GF.SET.UL, GF.SET.L, GF.SET.GE. GF.SET.E, GF.SET.NE, GF.SET.UE. GF.SET.NUE: c i+prec-1..i *~ c ' endcase endfor endcase case round of X: N: T: F: C: NONE: endcase RegWrιte(rc, 128, c) endcase enddef Exceptions Reserved instruction Floating-point arithmetic Group Floating-point Ternary These operations perform floating-point arithmetic on three groups of floating¬ point operands contained in registers. Ooeratipn codes Format GF. operation. type rd=ra,rb,rc 31 24 23 1 8 1 7 1 2 1 1 6 5 op ra rb re rd Description The contents of registers ra and rb are taken to represent a group of floating-po.r.t operands and pairwise are multiplied together and added to or subtracted from the group of floating-point operands taken from the contents of register re. The results are concatenated and placed in register . The results are rounded to the nearest representable floating-point value in a single floating-point operation Floating-point exceptions are not raised, and are handled according to the detault rules of IEEE 754. These instructions cannot select a directed rounding mode or trap on inexact. Definition def GroupFloatιngPoιntTernary(op,prec,ra,rb,rc,rd) as a «- RegRead(ra, 128) b <- RegRead(rb. 128) c <- RegRead(rc, 128) for l •*— 0 to 128-prec by prec ai <- F(prec,aι +pre c-l i) bi <- F(prec,b, +pr ec-l ι) ci <r- F(prec,C| +P rec-l ,i) case op of GF. MULADD GF.MULSUB- endcase dι+prec-ι..ι «- PackF(prec, di) endfor RegWrιte(re, 128, d) enddef Exceptions Reserved instruction Floating-point arithmetic Group Floating-ooint Unary These operations take one value from a register , perform floating-point arithmetic on groups of bits in the operands, and place the concatenated results in a register . Operation codes Format GF. op. prec. round rc=ra 31 24 23 18 17 1 2 1 1 6 5 Description The contents of register ra is used as the operand of the specified floating-point operation. The result is placed in register re. The operation is rounded using the specified rounding option or using round-to-nearest if not specified. If a rounding option is specified, the operation raises a floating-point exception if a floating-point invalid operation, divide by zero, overflow, or underflow occurs, or when specified, if the result is inexact. If a rounding option is not specified, floating-point exceptions are not raised, and are handled according to the default rules of IEEE 754. Definition def GroupFloatingPoιntUnary(op, prec, round, ra.rb, re) as a <- RegRead(ra, 128) case op of GF.ABS, GF.NEG, GF.SQR: for i <— 0 to 128-prec by prec ai <- F(prec , a, +P rec-1. ι) case op of GF.ABS. else endif GF.NEG endcase c ι + prec-l i *- PackF(prec. ci. round) endfor GF.SINK for i «- 0 to 128-prec by prec ai «- F(prec.aι +P rec-1 i) c ι+prec-l i *~ a' endfor GF.FLOAT: for i «- 0 to 128-prec by prec Cι + ρrec-1. ι *- PackF(prec.aι. round) endfor GF INFLATE. for i «— 0 to 64-prec by prec ai «- F(prec a, +or9C .ι ,) c l+l +pre - +pre c-ι I + I «- PackF(prec+prec.aι, round) endfor GF.DEFLATE for i <— 0 to 128-prec by prec ai <- F(prec,a l+pre c-i ι) c i/2+ρrec/2-ι ..ι/2 *- PackF(prec/2.aι, round) endfor endcase RECfrc] *- c enddef Exceptions Reserved instruction Floating-point arithmetic Load These operations add the contents of two registers to produce a virtual address, load data from memory, sign- or zero-extending the data to fill the destination register OceraPon codes 26 L 8 need not distinguish between little-endian and big-endian ordering, nor between aligned and unaligned, as only a single byte is loaded 2 ~L 64 B need not distinguish between signed and unsigned, as the octlet tills the destination register 28 L 64 B A need not distinguish between signed and unsigned, as the octlet fills the destination register 29 L 64 L need not distinguish between signed and unsigned, as the octlet fills the destination register 30 L 64 L A need not distinguish between signed and unsigned, as the octlet fills the destination register •" ■ l ~L 128 B need not distinguish between signed and unsigned, as the hexlet fills the destination register pair 32 L 128 B A need not distinguish between signed and unsigned, as the hexlet fills the destination register pair 3 J L 128 L need not distinguish between signed and unsigned, as the hexlet fills the destination register pair •^L 128 L A need not distinguish between signed and unsigned as the hexlet fills the destination register pair J 'L U8 need not distinguish between little-endian and big-endian ordering, nor between aligned and unaligned, as onlv a single bvte is loaded Format op rc=ra,rb 31 24 23 18 17 12 11 6 5 I L.MINOR I ra T rb re op Descπotipn A virtual address is computed from the sum of the contents of register ra and register rb. The contents of memory using the specified byte order is treated as the size specified and zero-extended or sign-extended as specified, and placed into register rb. If alignment is specified, the computed virtual address must be aligned, that is, it must be an exact multiple of the size expressed in bytes. If the address is not aligned an "access disallowed by virtual address" exception occurs. Definition def Load(op ra.rb.rc) as case op of L16L L32L, L8 L16LA, L32LA, L16B, L32B, L16BA, L32BA, L64L, L64LA, L64B, L64BA signed <- true LU16L, LU32L LU8. LU16LA, LU32LA, LU16B LU32B, LU16BA, LU32BA LU64L. LU64LA, LU64B LU64BA signed <- false L128L L128LA, L128B. L128BA signed «- undefined endcase case op of L8, LU8 L16L LU16L, L16LA, LU16LA. L16B LU16B, L16BA, LU 16BA L32L. LU32L. L32LA, LU32LA, L32B. LU32B. L32BA, LU32BA L64L LU64L, L64LA, LU64LA L64B LU64B L64BA, LU64BA L128L, L128LA, L128B. L128BA endcase case op of L16L LU16L, L32L, LU32L, L64L LU64L, L128L L16LA, LU 16LA, L32LA, LU32LA. L64LA LU64LA. L128LA order <- L L16B LU16B L32B LU32B L6^B LU64B L128B, L16BA. LU16BA. L32BA. LU32BA L64BA. LU64BA. L128BA order <- B L8, LU8 order <- undefined endcase case op of L16L. LU16L. L32L, LU32L L64L LU64L, L128L, L16B LU16B. L32B, LU32B. L64B LU64B, L128B align <- false L16LA, LU16LA, L32LA, LU32LA. L64LA, LU64LA, L128LA, L16BA, LU16BA, L32BA, LU32BA L64BA, LU64BA, L128BA align <- true L8, LU8 align <- undefined endcase a <- RegRead(ra, 64) b <- RegRead(rb, 64) VirtAddr <- a + b if align then if (VirtAddr and ((sιze/8)-1)) ≠ 0 then raise AccessDisallowedByVirtualAddress endif endif m <- LoadMemory(VιrtAddr, size, order) mx «- (m S|Ze- -| and sιgned) 128 - s,ze II m case size of RegWrιte(rc, 64, mx63 o) 128 RegWrιte(rc, 128, mx) endcase enddef Exceptions Reserved instruction Access disallowed by virtual address Access disallowed by tag Access disallowed by global TLB Access disallowed by local TLB Access detail required by tag Access detail required by local TLB Access detail required by global TLB Cache coherence intervention required by tag Cache coherence intervention required by local TLB Cache coherence intervention required by global TLB Local TLB miss Global TLB miss Load Immediate These operations add the contents of a register to a sign-extended immediate value to produce a virtual address, load data from memory, sign- or zero-extending the data to fill the destination register. Ooeratipn codes ^L.8.1 need not distinguish between little-endian and big-endian ordering, nor between aligned and unaligned, as only a single byte is loaded. '" L.64. B.A.I need not distinguish between signed and unsigned, as the octlet fills the destination register. ^L.64. B.I need not distinguish between signed and unsigned, as the octlet fills the destination register. -* 9 L.64. L.A.I need not distinguish between signed and unsigned, as the octlet fills the destination register. 40 L.64J.I need not distinguish between signed and unsigned, as the octlet fills the destination register. 4 A 128. B.A.I need not distinguish between signed and unsigned, as the hexlet fills the destination register pair. 2 L.128.B.I need not distinguish between signed and unsigned, as the hexlet fills the destination register pair. A.128. L.A.I need not distinguish between signed and unsigned, as the hexlet fills the destination register pair. 4 L.128.L.I need not distinguish between signed and unsigned, as the hexlet fills the destination register pair. "■AU8.I need not distinguish between little-endian and big-endian ordering, nor between aligned and unaligned, as only a single byte is loaded. Format op rb=ra, offset 8 12 Description A virtual address is computed from the sum of the contents of register ra and the sign-extended value of the offset field. The contents of memory using the specified byte order is treated as the size specified and zero-extended or sign-extended as specified, and placed into register rb. If alignment is specified, the computed virtual address must be aligned, that is, it must be an exact multiple of the size expressed in bytes. If the address is not ahgned an "access disallowed by virtual address" exception occurs. Definition def Loadlmmedιate(op,ra,rb, offset) as case op of L16LI, L32LI, L8I, L16LAI, L32LAI, L16BI, L32BI, L16BAI, L32BAI- L64LI. L64LAI, L64BI, L64BAI' signed <- true LU16LI, LU32LI, LU8I. LU16LAI, LU32LAI, LU16BI, LU32BI, LU 16BAI, LU32BAI: LU64LI, LU64LAI, LU64BI, LU64BAI: signed <- false L128LI. L128LAI, L128BI, L128BAI: signed <- undefined endcase case op of L8I. LU8I L16LI, LU16LI. L16LAI, LU16LAI, L16BI. LU 16BI L16BAI, LU16BAI L32LI, LU32LI. L32LAI, LU32LAI, L32BI, LU32BI L32BAI, LU32BAI L64LI. LU64LI, L64LAI, LU64LAI, L64BI, LU64BI L64BAI. LU64BAI L128LI, L128LAI, L128BI, L128BAI endcase case op of L16LI. LU 16LI, L32LI. LU32LI. L64LI, LU64LI, L128LI, L16BI, LU16BI, L32BI LU32BI L64BI, LU64BI L128BI align <- false L16LAI, LU 16LAI, L32LAI, LU32LAI, L64LAI. LU64LAI, L128LAI, L16BAI, LU 16BAI, L32BAI. LU32BAI, L64BAI. LU64BAI L128BAI align <- true L8I LU8I align <- undefined endcase case op of L16LI, LU 16LI, L32LI, LU32LI L64LI. LU64LI, L128LI. L16LAI, LU 16LAI, L32LAI, LU32LAI, L64LAI, LU64LAI. L128LAI order <- L L16BI, LU 16BI, L32BI. LU32BI. L64BI, LU64BI, L128BI L16BAI, LU 16BAI, L32BAI, LU32BAI. L64BAI. LU64BAI, L128BAI order «-— B L8I. LU8I order <- undefined endcase a <r- RegRead(ra, 64) VirtAddr <- a + (offset- ) - | 52 II offset) if align then if (VirtAddr and ((sιze/8)-1 )) ≠ 0 then raise AccessDisallowedByVirtualAddress endif endif b <- LoadMemory(VιrtAddr. size. order) bx <- (b s ,ze-l and signed) 1 28-sιze n b RegWrιte(rb, 64, bx) enddef Exceptions Reserved instruction Access disallowed by virtual address Access disallowed by tag Access disallowed by global TLB Access disallowed by local TLB Access detail required by tag Access detail required by local TLB Access detail required by global TLB Cache coherence intervention required by tag Cache coherence intervention required by local TLB Cache coherence intervention required by global TLB Local TLB miss Global TLB miss Store These operations add the contents of two registers to produce a virtual address, and store the contents of a register into memory. Ooerat'on codes 4 ^S 8 need not specifv byte ordering, nor need it specifv alignment checking, as it stores a single bvte Format op ra.rb.rc Description A virtual address is computed from the sum of the contents of register ra and register rb. The contents of register re, treated as the size specified, is stored in memory using the specified byte order. If alignment is specified, the computed virtual address must be aligned, that is, it must be an exact multiple of the size expressed in bytes. If the address is not aligned an "access disallowed by virtual address" exception occurs. Definition def Store(op. ra.rb.rc) as case op of S8. S16L S16LA. S16B. S16BA, S32L. S32LA. S32B. S32BA, S64L S64LA. S64B, S64BA, S12SL S128LA, S128B. S128BA: function <— NONE SAAS64BA, SAAS64LA: function <- AAS SCAS64BA, SCAS64LA: function «- CAS SMAS64BA. SMAS64LA: function <- MAS SMUX64BA, SMUX64LA: function <- MUX endcase case op of S8: S16L, S16LA. S16B, S16BA. S32L. S32LA, S32B, S32BA: S64L S64LA, S64B, S64BA, SAAS64BA, SAAS64LA: SCAS64BA, SCAS64LA, SMAS64BA, SMAS64LA, SMUX64BA, SMUX64LA: S128L S128LA, S128B, S128BA. endcase case op of S8, S16L, S16LA. S16B, S16BA. S32L, S32LA. S32B, S32BA, S64L S64LA. S64B. S64BA. SAAS64BA, SAAS64LA rsize <- 64 SCAS64BA, SCAS64LA. SMAS64BA, SMAS64LA, SMUX64BA. SMUX64LA rsize <— 128 S128L S128LA. S128B. S128BA rsize <- 128 endcase case op of S8 align *- undefined S16L. S32L S64L. S128L, S16B. S32B. S64B. S128B align <- false S16LA, S32LA, S64LA, S128LA S16BA, S32BA. S64BA. S128BA SAAS64BA, SAAS64LA, SCAS64BA. SCAS64LA, SMAS64BA. SMAS64LA. SMUX64BA. SMUX64LA align •— true endcase case op of S8 order <- undefined S16L. S32L, S64L. S128L S16LA. S32LA, S64LA. S128LA SAAS64LA, SCAS64LA, SMAS64LA, SMUX64LAI order <- L S16B, S32B. S64B, S128B. S16BA, S32BA, S64BA, S128BA. SAAS64BA, SCAS64BA, SMAS64BA, SMUX64BAI order <- B endcase a <- RegRead(ra, 64) b <- RegRead(rb, 64) VirtAddr <- a + b if align then if (VirtAddr and ((sιze/8)-1 )) ≠ 0 then raise AccessDisallowedByVirtualAddress endif endif m <r- RegRead(rc, rsize) case function of NONE StoreMemory(VιrtAddr.sιze order, m S ι 2e- ι o) AAS c *- LoadMemory(VιrtAddr, size, order) StoreMemory(VιrtAddr,sιze,order,m63 o+c) RegWrιte(rc, 64, c) CAS c *- LoadMemory(VιrtAddr, size, order) if (c = rτi63 o) then StoreMemory(VιrtAddr, size. order, m-| 27 64) endif RegWrιte(rc, 64, c) MAS c <- LoadMemory(VιrtAddr, size, order) n <- ( i 27 64 & rri53 o) I (c & -rri63 o) StoreMemory(VιrtAddr, size. order, n) RegWrιte(rc. 64, c) MUX: c «- LoadMemory(VirtAddr. size. order) n «- (mi27..64 & m 63 .0) I (c & ~m 63 .. 0 ) StoreMemory(VιrtAddr. size. order, n) endcase enddef Exceptions Reserved instruction Access disallowed by virtual address Access disallowed by tag Access disallowed by global TLB Access disallowed by local TLB Access detail required by tag Access detail required by local TLB Access detail required by global TLB Cache coherence intervention required by tag Cache coherence intervention required by local TLB Cache coherence intervention required by global TLB Local TLB miss Global TLB miss Store Immediate These operations add the contents of a register to a sign-extended immediate value to produce a virtual address, and store the contents of a registerinto memory. Operation codes ~S 8 I need not specify byte ordering, nor need it specify alignment checking, as it stores a sinsle bvte. Format S. size, order, align. ra.rb, offset 8 6 6 12 Description A virtual address is computed from the sum of the contents of register ra and the sign-extended vale of the offset field. The contents of register rb, treated as the size specified, is stored in memory using the specified byte order. If alignment is specified, the computed virtual address must be aligned, that is, it must be an exact multiple of the size expressed in bytes. If the address is not aligned an "access disallowed by virtual address" exception occurs. Definition def Storelmmedιate(op. ra.rb. offset) as case op of S8I , S16LI, S16LAI. S16BI. S16BAI S32LI, S32LAI. S32BI, S32BAI. S64LI. S64LAI, S64BI, S64BAI. S128LI. S128LAI. S 128BI. S128BAI: function <- NONE SAAS64BAI, SAAS64LAI function •*- AAS SCAS64BAI, SCAS64LAI- function «- CAS SMAS64BAI, SMAS64LAI function <- MAS SMUX64BAI, SMUX64LAI- function <- MUX endcase case op of S8I . S16LI. S16LAI. S16BI, S16BAI. S32LI. S32LAI, S32BI, S32BAI S64LI, S64LAI, S64BI, S64BAI, SAAS64BAI, SAAS64LAI, SCAS64BAI, SCAS64LAI. SMAS64BAI, SMAS64LAI, SMUX64BAI, SMUX64LAI. S 128LI. S 128LAI, S128BI, S128BAI' endcase case op of S8I, S16LI. S16LAI. S16BI, S16BAI, S32LI, S32LAI, S32BI, S32BAI. S64LI. S64LAI. S64BI. S64BAI. SAAS64BAI, SAAS64LAI. rsize <- 64 SCAS64BAI, SCAS64LAI. SMAS64BAI. SMAS64LAI, SMUX64BAI, SMUX64LAI rsize <- 128 S128LI, S128LAI, S128BI, S128BAI rsize <- 128 endcase case op of S8I align <- undefined S16LI. S32LI. S64LI. S128LI. S16BI. S32BI, S64BI S 128BI align <- false S16LAI. S32LAI, S64LAI, S128LAI, S16BAI, S32BAI. S64BAI. S128BAI, SAAS64BAI. SAAS64LAI. SCAS64BAI. SCAS64LAI, SMAS64BAI, SMAS64LAI, SMUX64BAI. SMUX64LAI align <- true endcase case op of S8I order <- undefined S16LI, S32LI. S64LI. S128LI, S16LAI. S32LAI. S64LAI S128LAI. SAAS64LAI, SCAS64LAI. SMAS64LAI. SMUX64LAI order <- L S16BI, S32BI. S64BI. S128BI, S16BAI. S32BAI, S64BAI. S128BAI, SAAS64BAI, SCAS64BAI, SMAS64BAI. SMUX64BAI order <- B endcase a <- RegRead(ra, 64) VirtAddr <- a + (offset- j - j 50 II offset) if align then if (VirtAddr and ((sιze/8)-1 )) ≠ 0 then raise AccessDisallowedByVirtualAddress endif endif m «-— RegRead(rb, rsize) case function of NONE. StoreMemory(VιrtAddr, size, order, m S|Ze- t _ _) A AS. b <- LoadMemory(VιrtAddr, size, order) StoreMemory(VιrtAddr, size. order, 63 rj+b) RegWrιte(rb, 64, b) CAS b <- LoadMemory(VιrtAddr, size, order) StoreMemory(VιrtAddr, size, order, m 127 64) endif RegWrιte(rb, 64, b) MAS b <- LoadMemory(VιrtAddr, size. order) n <- (m-i27 64 & ^63 o) I (b &. -m63 o) StoreMemory(VιrtAddr size. order, n) RegWrιte(rb, 64, b) MUX b <- LoadMemory(VirtAddr. size. order) n <- (m * i27..64 & rri63..θ) ' (b & ~m63..θ) StoreMemory(VirtAddr. size. order, n) endcase enddef Exceptions Reserved instruction Access disallowed by virtual address Access disallowed by tag Access disallowed by global TLB Access disallowed by local TLB Access detail required by tag Access detail required by local TLB Access detail required by global TLB Cache coherence intervention required by tag Cache coherence intervention required by local TLB Cache coherence intervention required by global TLB Local TLB miss Global TLB miss Memory Management This section discusses the caches, the translation mechanisms, the memory interfaces, and how the multiprocessor interface is used to maintain cache coherence. The Terpsichore processor provides for both local and global virtual addressing, arbitrary page sizes, and coherent-cache multiprocessors. The memory management system is designed to provide the requirements for implementation of virtual machines as well as virtual memory. All facilities of the memory management system are themselves memory mapped, in order to provide for the manipulation of these facilities by high-level language, compiled code. The translation mechanism is designed to allow full byte-at-a-time control of access to the virtual address space, with the assistance of fast exception handlers. Privilege levels provide for the secure transition between insecure user code and secure system facilities. Instructions execute at a privilege, specified by a two-bit field in the access information. Zero is the least-privileged level, and three is the most-privileged level. The diagram below sketches the organization of the memory management system: Starting from a local virtual address, the memory management system performs three actions in parallel: the low-order bits of the virtual address are used to directlv access the data in the cache, a low-order bit field is used to access the cache tag, and the high-order bits of the virtual address are translated from a local address space to a global virtual address space. Following these three actions, operations vary depending upon the cache implementation. The cache tag may contain either a physical address and access control information (a physically-tagged cache), or may contain a global virtual address and global protection information (a virtually-tagged cache). For a physically-tagged cache, the global virtual address is translated to a physical address by the TLB, which generates global protection information. The cache tag is checked against the physical address, to determine a cache hit. In parallel, the local and global protection information is checked. For a virtually-tagged cache, the cache tag is checked against the global virtual address, to determine a cache hit, and the local and global protection information is checked. If the cache misses, the global virtual address is translated to a physical address by the TLB, which also generates the global protection information. Local and Global Virtual Addresses The 64-bit global virtual address space is global among all tasks. In a multitask environment, requirements for a task-local address space arise from operations such as the UNIX "fork" function, in which a task is duplicated into parent and child tasks, each now having a unique virtual address space. In addition, when switching tasks, access to one task's address space must be disabled and another task's access enabled. Terpsichore provides for portions of the address space to be made local to individual tasks, with a translation to the global virtual space specified by four 16- bit registers for each local virtual space. Terpsichore specifies four sets of virtual spaces, and therefore four sets of these four registers. The registers specify a mask selecting which of the high-order 16 address bits are checked to match a particular value, and if they match, a value with which to modify the virtual address. Terpsichore avoids setting a fixed page size or local address size; these can be set by software conventions. A local virtual address space is specified by the following:: local virtual address space specifiers These 16-bit registers are packed together into a 64-bit register as follows: Local Translation Lookaside Buffe r The LTLB contains a separate context of register sets for each thread. A context consists of one or more sets of mask match/xor/protect registers, one set for each simultaneously accessible local virtual address range. This set of registers is called the "Local TLB context," or LTLB ( Local Translation Lookaside Buffer) context. The effect of this mechanism is to provide the facilities normally attributed to segmentation. However, in this system there is no extension of the address range, instead, segments are local nicknames for portions of the global virtual address space. For instructions executing at the two least privileged levels (level 0 or level 1 ). a failure to match a LTLB entry causes an exception. This exception may be handled by loading an LTLB entry and continuing execution, thus providing access to an arbitrary number of local virtual address ranges. Instructions executing at the two most privileged levels (level 2 or level 3) may access any region in the local virtual address space, when a LTLB entry matches, and may acess regions in the global virtual address space when no LTLB entry matches. This mechanism permits privileged code to make judicious use of local virtual address ranges, which simplifies the manner in which privileged code may manipulate the contents of a local virtual address range on behalf of a less- privileged client. A minimum implementation of an LTLB context is a single set of mask/match/xor/protect registers per thread. A single-set LTLB context may be further simplified by reserving the implementation of the mask and match registers, setting them to a read-only zero value: 1 6 1 6 1 6 If the largest possible space is reserved for an address space identifier, the virtual address is partitioned as shown below. Any of the bits marked as "local" below may be used as "offset" as desired. 63 48 47 0 local i offset 1 6 48 Definition def GlobalVA.LocalProtect <- LocalVιrtualToGlobalVιrtualAddressTranslatιon(th, va.pl) as LocalTLBMatch *- NONE for i <- 0 to <<sets per thread>>-1 if (vae3 48 & -LocalTLB[th][ιj63 * _) = LocalTLB[th][i] 47 32 then LocalTLBMatch <- ι endif endfor if LocalTLBMatch = NONE then if pi < 2 then raise LocalTLBMiss endif GlooalVA «- va LocalProtect <- 0 else GlooalVA <- (vae3 48 Λ LocalTLB[th][LocalTLBMatch]3 1 16 ) II va47 0 LocalProtect *- LocalTLB[thJ[LocalTLBMatch]i5 .0 endif enddef Global Virtual Cache The innermost levels of the instruction and data caches are direct-mapped and indexed and matched entirely by the global virtual address. Consequently, each block of memory data is tagged with access control information and the high-order bits of the global virtual address. The current size of the virtual caches is 32 kilobytes; for architectural compatibility, a minimum size of 8 kilobytes and a maximum size of 1 megabyte is specified. The mapping of virtual addresses to physical may freely contain aliases, however, provided that either the associated regions of memory are maintained as coherent, or that the low order 20 bits of any virtual cache aliases are identical. (20 bits reflects the size of the maximum lλl byte virtual cache.) A virtual cache tag is contained in the buffer memory (described below). It is accessed in parallel with the virtual cache. The virtual tag must match, and the control information must permit the access, or a cache miss or exception occurs There is one tag for each cache block: a cache block consists of 64 bytes, so for a 32 kilobyte cache, there is 4 kilobytes of cache tag information for each cache. The protect field shown below is the concatenation of the access, state and control fields shown in the table below: 63 13 1 2 0 | global virtual tag \ protect | 51 13 Definition The following function reads the data, tag, and protection bits from either the instruction (c=0) or data (c=l) cache, given a local virtual address. def data.GlobalVA.GIobalProtect <- ReadCache(c.va,sιze) as data <- cacheDataArray[c][va-i 4 4] GlobalVA <- cacheTagArray[c][va-|4 6J63 16 ■■ va i5 0 GlobalProtect <- cacheTagArray[c][va-i4 el l 5 .0 enddef Translation and Protection Global virtual addresses are translated to physical addresses only upon misses in the virtual caches. The translation is performed by software-programmable routines, augmented by a hardware TLB, specifically, the global TLB. The global TLB labels a cache line with the physical and access information in the virtual cache tag. The global TLB contains a minimum of 64 entries and a maximum of 256 entries. A local TLB, global TLB or virtual cache entry contains the following information. The figures in parentheses are the actual size of the field contained, if only a sub- field is held in the entrv. information in local L , global LB, or virtual cache entry The bottom section of the table above indicates the contents of the 16-bit protection field: 1 1 1 15 1-1 13 12 11 13 8 7 6 5 4 3 2 1 1 1 1 pr cec:c nfcrmazO ι ' sfuct c~ cacne :ag 13 12 11 10 5 7 6 5 4 3 2 1 P r otect;o ■ ncrmarc < r vua 1 ca:a cacne lag 13 12 11 10 8 7 6 5 4 3 2 1 1 1 1 Protection ■ nfqrmapcn m p nvsca 1 ca:a cacne tag 5 4 3 2 jccjda jao cs 1 1 1 Memory Interface Dedicated hardware mechanisms are provided to fetch and store back data b.oc.-.s in the instruction and data caches, provided that a matching entry can be rour.d :r. the global TLB. When no entry is to be found in the global TLB, an exception handler is invoked either to generate the required information from the virtual address, or to place an entry in the global TLB to provide for automatic handling of this and other similarly addressed data blocks. The initial implementation of Terpsichore partitions the remainder of the local memory system, including a second-level joint physical cache and a DRAλl-based memory array, into a set of separate devices, called Mnemosyne. These devices are accessed via a high-bandwidth, byte-wide packet interface, called Hermes, which is largely transparent to the Terpsichore architecture. The Mnemosyne devices provide single-bit correction, double-bit detection ECC on all local memory accesses, and a check byte protects all packet interface transfers. The size of the secondarv cache and the DRAM memory array is implementation- dependent Cache Coherence The Terpsichore processor is intended for use in either a uniprocessor or multiprocessor environment At the high performance level intended for Terpsichore, mechanisms emploved other processor designs to maintain cache coherence, such as "snoopy cache ' buses, cannot be effec eh built, because the communication latency and bandwidth between processors would be excessive Several cache coherence mechanisms have been designed for high-performance processors that do not require that all memory transactions be broadcast among the processors in a svstem. one of which is the Scalable Coherent Interface, or SCI, as specified bv the IEEE Standard 1596-1992 The SCI cache coherence mechanism is extremely complex Many of the cache coherence operations take time proportional to the number of processors involved in the operation, and so lmphcitlv assume that the number ot processors sharing a particular data item will tend to be much less than the 64k processors that SCI can theoreticall y handle (SCI is now considering an even more complex mechanism that mav assure logarithmic growth in time complexity) Most importantly, no complete working prototype of this mechanism has been built, tested and benchmarked at the time of development of the Terpsichore architecture It is considered then, that the cache coherence mechanism should not be implemented in immutable, hardware state machines. A software implementation of a cache coherence protocol is proposed, which given the high intrinsic performance of the processor, is likely to reach nearly the performance level that can be achieved in dedicated hardware The greatest advantage, though, is that Terpsichore will be an excellent vehicle to test and improve the performance of experimental non-bus-oriented cache coherency operations Cache coherence information is available within the local TLB, global TLB and the cache tags, so that coherence operations may be performed at task-level, page- level, or cache-block-level as desired. This flexibility provides for a coherent view of memory in multiprocessing systems with varying degrees of coupling Physical Addresses Phvsical addresses are 64 bits in size, consisting of a 16 bit processor node number and a 48 bit address. 63 48 47 o node LocalAddress 1 6 48 Physical addresses in which the node number is zero reference the local processors local memorv space, providing access to local memorv cache tags, svstem and interface facilities Phvsical addresses in which the node number is nonzero reference other processors ' local memory spaces, using the Hydra interface for communication. The local memory environment or Terpsichore involves the use of up to tweh e Hermes byte-wide packet communications channels, bv which Terpsichore can request read or write transactions :o Mnemosyne. Calliope, and Hydra devices. In addition. Terpsichore can issue read or write transactions to the Cerberus serial bus interface, via which the Mnemosvne, Calliope. Hydra and other devices ' configuration and control registers car. be accessed The diagram illustrates shows one possible Terpsichore memory environment: Hermes channels 0..7 are always used to connect Terpsichore to Mnemosyne memory devices. Hermes channels S.J 1 may be used to connect Mnemosvne. Calliope, or Hydra devices. Terpsichore provides three different mappings of the local memory environment in the local physical address space. The non-interleaved space provides for the access of all Mnemosyne, Calliope, and Hydra device memory spaces such that each device appears as a single continuous space. The uniprocessor spaces provide for the interleaved access of one. two, or four sets of eight Mnemosyne devices on separate Hermes channels as a single continuous space. The multiprocessor spaces provide for the interleaved access of one, two, or four sets of nine Mnemosyne devices on separate Hermes channels as a single continuous space with the ninth channel used as α cache coherency directory. 63 48 4 40 39 0 node space Space ocalAddress 16 40 The value of the space field determines the interpretation of the 48-bit local address field as given by the following table: space fieiα interpretation Non-'nterieaved Hermes channel P..7 Soace The non-interleaved Hermes channel 0..7 space provides a single continuous memory space for each device in Hermes channels 0..7. Mnemosyne protocols are used. Only incoherent accesses are supported (no memory directory tags). The range of valid values and the interpretation of the fields is given by the following table: non-interleaveα space field interpretation ■ or - : n χ eπeaved Hermes cna^re 1 8 11 Soace The non-interleaved Hermes channel 8..11 space provides a single continuous memory space for each device in Hermes channels 8..11. Either Mnemosyne or Calliope/ Hydra protocols may be specified. Only incoherent accesses are supported (no memory directory tags). The range of valid values and the interpretation of the fields is given by the following table: non-interleaveα space tieid interpretation jniprccessor inzeπeavec Spaces The interleaved spaces described below interleave between 8 Hermes channels ( 0..7 ). supporting only incoherent accesses (no memory directory tags ). Mnemosyne protocols are used. 32 The interleaved spaces described below interleave between 4 Hermes channels ( 0..3 or 4..7 ) . supporting only incoherent accesses (no memory directory tags). Mnemosyne protocols are used. 47 40 39 337 3 6 5 4 3 2 0 32 2 2 The interleaved spaces described below interleave between 2 Hermes channels (0.J, 2..3, 4..5, or 6..7), supporting only incoherent accesses (no memory directory- tags). Mnemosyne protocols are used. 32 2 1 The range of valid values and the interpretation of the fields is given by the following table: interleaved space field interpretation The Hermes channel number is constructed by concatenating the d and c fields: 5 3 - ' ' -d 3 393a 3 [ ] or SΩ or [TR 3 1 2 2 2 The Hermes module number is constructed by concatenating the n and m fields: 3736 r 4 5 4 or μi or [m] 2 1 1 2 Multiprocessor Interleaved Scace The interleaved spaces described below interleave between 9 channels for a multiprocessor. The range of valid values and the interpretation of the fields is given by the following table: interleaved space field interpretation For the multiprocessor space the channel number field is modified by the low- order memory block address bits according to the following tables. In addition. access to a location in this space also accesses a memory tag, using the Hermes channel specified in the tables below. 9 channel translation table The memory tag entry is an octlet value for each 64-byte memory block The contents of the tag is interpreted by Terpsichore hardware to signify C" a zero value indicates that the memory block is not contained in the cache. 1 1 • a vaiue equal to the virtual address used to access the memory block indicates that the value is cached at that address, and (2) any other values indicates that the value may be cached in multiple or remote locations and requires software intervention for interpretation. Thus a read to a memory block accesses the tag, and if the value is zero, fills it with the virtual address via which the access occurred. When the memory block is returned to memory, the tag is accessed, and if the value is equal to the virtual address, the tag is reset to zero. In all other cases, an exception occurs, which is handled by software to implement the cache coherency mechanisms. We also need to have a space av ich access to the tag via software routines is straightforward - the ed space makes the tag available but not conveniently ,Oar a O, -c Q fl o The Cerberus serial bus space provides access to α memory space in which Bootstrap ROM code. Terpsichore. ne and Calliope configuration data, and other Cerberus peripherals are accessed The Cerberus serial bus is specified by the document " Cerberus Serial Bus Architecture " Terpsichore configuration data is accessable via Cerberus as a slave deuce as well as \ ιa this address space 1 6 1 6 The range of valid values and the interpretation of the fields is given bv the following table Cerberus space tieiα interpretation Co f roi ^eoιsτe r Adcresses This section is under construction Local TLB (4 octlets) Virtual cache tags (2k-128k x 2 caches) Virtual cache data (16k-1 M x 2 caches) Global TLB (4 octlets x 64-256 entπes=2k-8k bytes) Events and Threads Exceptions signal several kinds of events ' 1 ) events that are indicative of failure of the software or hardware, such as arithmetic overflow or paπtv error, (2) events that are hidden from the virtual process model, such as translation buffer misses. (3 ) events that infrequently occur, but may require corrective action, such as floating-point underflow. In addition, there are (4) external events that cause scheduling of a computational process such as completion of a disk transfer or clock events Each of these types of events require the interruption of the current flow of execution, handling of the exception or event, and in some cases, descheduling of the current task and rescheduling of another. The Terpsichore processor provides a mechanism that is based on the multi-threaded execution model of Mach. Mach divides the well-known UNIX process model into two parts, one called a task, which encompasses the virtual memorv space, file and resource state, and the other called a thread, which includes the program counter, stack space, and other register file state The sum of a Mach task and a Mach thread exactlv equals one UNIX process, and the Mach model allows a task to be associated with several threads. On one processor at any one moment in time, at least one task with one thread is running In the taxonomy of events described above, the cause of the event may either be synchronous to the currently running thread, generally types 1 , 2, and 3 , or asynchronous and associated with another task and thread that is not currently running, generally type 4. For synchronous events, Terpsichore will suspend the currently running thread in the current task, and continue execution with another thread that is dedicated to the handling of events. For asynchronous events, Terpsichore will continue execution with the dedicated event thread, while not necessarily suspending the currently running thread Terpsichore provides sufficient resources for the interleaved execution of at least one full thread, containing 64 general registers and a program counter, and at least one separate event thread, containing 16 general registers and a program counter When both threads are able to continue execution, priority is generally given to the event threads. All facilities of the exception, memory management, and interface systems are themselves memory mapped, in order to provide for the manipulation of these facilities by high-level language, compiled code. In particular, the thread resources of the full threads are memory-mapped so that the exception threads are able to read and write the general registers and program counter of the full threads Events are single-bit messages used to communicate the occurrence of exceptions between full threads and event threads and interface devices 63 event 64 The event register appears at several locations in memorv , with shghtlv different side effects on read and write operations onset side efrect on read siαe e * τect on write 0 none return event register normal write data into event contents reαister stall thread until contents or stall threaα until bitwise and of event register is non-zero then data and event register contents return event reαister contents is non-zero 16 return zero value (so reaα- one pits in αata set (to one) modify-wπte for byte/dcuc'et' corresponding event register guadlet store works) bits 24 return zero value (so reaα- one oits in σata clear (to zero) modify-wπte for byte/dcublet' corrεsoonding event register αuadlet store works) bits interface devices signal events b\ responding to non-blocking read requests generated by a write to a Terpsichore control register The response to these read requests is combined into the event register with an inclusive-or operation 63 0 [ event daemon address 64 A write to the event daemon address register causes Terpsichore to issue a read request to the corresponding physical address The device referenced bv this request mav respond at any future time with a value, which is mclusn e-or ' ed into th e event register The following notes list the resources needed to support the threads Events 0 full thread 0 suspended at instruction fetch because of exception 1 full thread 0 suspended at data fetch because or exception 2 full thread 0 suspended at execution because of exception 3 full thread 0 suspended at execution because of empty pipeline 4-15 same for full threads 1 -3 16-63 timer, calliope and hydra events Thread resources General registers at data fetch stage General registers at execution state Program counter, privilege level at data fetch stage Program counter, privilege level at execution stage Mask register events which permit the thread to run Mask register events which prevent tre thread to run 7 Control register suspend ifetch, dfetcn execute, thread priority Local TLB entries (full threads only) Exception information registers exception cause instruction which caused exception virtual address at which access attempted size of access attempted type of access (read, write, execute gateway) did exception occur at lower or higner addr if cross boundary 7 don t need - register contents (can get from mem map GR) Sort by stage Inst fetch stage program counter exception state cause TLB miss, coherence action required control register suspend (drain queue), reset(clear queue), proceed past detail Data fetch stage General registers program counter, privilege level control register suspend (drain queue), reset (clear queue) proceed past detail exception state cause(ιπcl access type, size, boundary, local TLB hit indication), inst can compute local va from GR, inst shift-and-add-load-shiftl-shiftr-add (7) computing global va is hard => need global va register can compute size from inst, 16-word table shift and add load (4 ) prefetched data, instruction queue clear queue drain queue Execute stage General registers program counter, privilege level control register suspend exception state cause(flt/fιx arithmetic), inst Exceptions Parameter passing There are no special registers to indicate details about the exception, such as the virtual address at which an access was attempted, or the operands of a floating¬ point operation that results in an exception. Instead, this information is available via memory-mapped registers. When a synchronous exception occurs in a full thread, the corresponding thread ' s state is frozen, and a general event is signalled. An event thread should handle the exeception. in whatever manner is required, and then may restart the full thread by writing to the full thread's control register. When a synchronous exception occurs in an event thread, an immediate transfer of control occurs to the machine check vector address, with information about the exception available in the machine check cause field of the status register. The transfer of control may overwrite state that may be necessary to recover from the exception; the intent is to provide a satisfactory post-mortem indication of the characteristics of the failure. Exceptions in detail This section is under construction. Terpsichore has changed from passing the parameters in registers to passing the parameters in memory-mapped registers, and the information in this section doesn ' t reflect the changes yet. This section describes in detail the conditions under which exception occurs, the parameters passed to the exception handler, and the handling of the result of the procedure. Access disallowed bv tag This exception occurs when a read ( load), write (store), execute, or gateway attempts to access a virtual address for which the matching virtual cache entry- does not permit this access. int AccessDisallowedByTag(int address, int size, int access) Desc'-cvcn The address at which the access was attempted is passed as address. The size of the access in bytes is passed as size. The type of access is passed as access, with 0 meaning read, 1 meaning write. 2 meaning execute, and 3 meaning gateway. The exception handler should determine accessibility, modify the virtual memory state if desired, and return if the access should be allowed. Upon return, execution is restarted and the access will be retried. Access detail reouired bv tac This exception occurs when a read (load), write (store), or execute attempts to access a virtual address for which the matching virtual cache entry would permit this access, but the detail bit is set. Prototype int AccessDetailRequiredByTag(int address, int size, int access) Descrip icn The address at which the access was attempted is passed as address. The size of the access in bytes is passed as size. The type of access is passed as access, with 0 meaning read. 1 meaning write, 2 meaning execute, and 3 meaning gateway. The exception handler should determine accessibility and return if the access should be allowed. Upon return, execution is restarted and the access will be retried. If the detail bit is set in the matching virtual cache entry, access will be permitted. Cache coherence action reαuired bv tag This exception occurs when a read (load, execute, or gateway), write (store), or replacement attempts to access a virtual address for which the coherence state of the matching virtual cache entry cannot permit this access. P r ctowce int CacheCoherence InterventionRequireddnt address, int size, int access) .e^ The address at which the access was attempted is passed as address The size of the access in bvtes is passed as size The type of access is passed as access, with 0 meaning read, 1 meaning write, 2 meaning replacement The exception handler should modify the cache status to make the cache line accessible Upon return, execution is restarted and the access will be retried Access ass'-cwed oy cicoa ~_5 This exception occurs when a read (load) , write (store), execute, or gateway attempts to access a virtual address for which the matching global TLB entry does not permit this access. int AccessDisallowedByGlobalTLBunt address, int size, int access) Zescnpfon The address at which the access was attempted is passed as address The size of the access in bytes is passed as size The type of access is passed as access with 0 meaning read, 1 meaning write. 2 meaning execute, and 3 meaning gateway The exception handler should determine accessibility, modify the virtual memory state if desired, and return if the access should be allowed. Upon return, execution is restarted and the access will be retried. If the detaii bit is set in the matching global TLB entry, access will be permitted Access detail required bv cooal L3 This exception occurs when a read (load), write (store), execute, or gatewax attempts to access a virtual address for which the matching global TLB er.tr. would permit this access, but the detail bit in the global TLB entry is set F'OtOV'/Oe int AccessDetailRequiredByGlobalTLBdnt address, int size, int access) Description The address at which the access was attempted is passed as address The size of the access in bytes is passed as size The type of access is passed as access, with 0 meaning read, 1 meaning write, 2 meaning execute, and 3 meaning gateway The exception handler should determine accessibility and return if the access should be allowed Upon return, execution is restarted and the access will be forced to be permitted If the access is not to be allowed, the handler should not return Cache coherence acrcn recwed bv global 7? R This exception occurs when a read ( load, execute, or gateway), write (store), or replacement attempts to access a virtual address for which the coherence state of the matching global TLB entry cannot permit this access. int CacheCoherence InterventionRequiredunt address, int size, int access) Descrp ic^ The address at which the access was attempted is passed as address. The size of the access in bytes is passed as size. The type of access is passed as access, with 0 meaning read, 1 meaning write, 2 meaning replacement. The exception handler should modify the virtual memory state to make the global TLB accessible. Upon return, execution is restarted and the access will be retried. This exception occurs when a read ( load), write (store), execute, or gateway- attempts to access a virtual address for which no global TLB entry matches. °rctoτyce void GlobalTLBMissdnt address, int size, int access) Descnpiion The address at which the global TLB miss occurred is passed as address. The size of the access in bytes is passed as size. The type of access is passed as access, with 0 meaning read. 1 meaning write. 2 meaning execute, and 3 meaning gateway. The exception handler should load a global TLB entry which defines the translation and protection for this address. Upon return, execution is restarted and the global TLB access will be attempted again. Access disallowed bv local TLB This exception occurs when a read (load), write (store), execute, or gateway- attempts to access a virtual address for which the matching local TLB entry does not permit this access. Prptcr>/oe int AccessDisallowedByLocalTLBdnt address, int size, int access) Description The address at which the access was attempted is passed as address. The size of the access in bytes is passed as s ze. The type of access is passed as access, with 0 meaning read, 1 meaning write. 2 meaning execute, and 3 meaning gatewav The exception handler should determine accessibility modify the virtual memory state if desired, and return if the access should be allowed Upon return, execution is restarted and the access will be retried Access cezaii reαwred cv cca ~ _Ξ This exception occurs when a read ι load), write (store 1 , execute, or gateway attempts to access a virtual address for w hich the matching local TLB entrv would permit this access, but the detail bit in the local TLB entrv is set int AccessDetailRequiredBvLocalTLBiint address, int size, int access) The address at which the access was attempted is passed as address The size ot the access in bytes is passed as size The tvpe of access is passed as access with 0 meaning read, 1 meaning write, 2 meaning execute, and 3 meaning gateway The exception handler should determine accessibility and return if the access should be allowed Upon return, execution is restarted and the access will be forced to be permitted If the access is not to be allowed, the handler should not return Cache coherence action recu ed bv local TLB This exception occurs when a read (load, execute, or gateway), write (store), or replacement attempts to access a virtual address for which the coherence state of the matching local TLB entry cannot permit this access P'-ptotvce int CacheCoherence InterventionRequireddnt address, int size, int access) Descrpi'on The address at which the access was attempted is passed as address The size of the access in bytes is passed as size. The type of access is passed as access, with 0 meaning read, 1 meaning write, 2 meaning replacement The exception handler should modify the virtual memorv state to make the local TLB accessible Upon return, execution is restarted and the access will be retried Local TLB miss This exception occurs when a read (load) , write (store), execute, or gatewa y attempts to access a virtual address for which no local TLB entrv matches Prototype void LocalTLBMissdnt address, int size, int access) -esccton The address at which the local TLB miss occurred is passed as address The size of the access in bytes is passed as s ze The type of access is passed as access, with 0 meaning read, 1 meaning write, 2 meaning execute, and 3 meaning gateway The exception handler should load a local TLB entry which defines the translation and protection for this address Upon return, execution is restarted and the local TLB access will be attempted again Fcaimg-ppint art^mez>c ■ ^"OtoTvce quad FloatingPointArithmeticdnt inst, quad ra, quad rb, quad re) The contents of the instruction which was the cause of the exception is passed as inst, and the contents of registers ra rb and re are passed as rα rb and re The exception handler should attempt to perform the function specified in the instruction and service any exceptional conditions that occur The result of the function is placed into register re or rd upon return. Fixed -cpini arithmetic P ototvoe int FixedPointArithmeticdnt inst, int ra, int rb) Descnct'cn The contents of the instruction which was the cause of the exception is passed as inst. and the contents of registers ra and rb are passed as rα and rb The exception handler should attempt to perform the function specified in the instruction and service any exceptional conditions that occur The result of the function is piaced into register rb or re. Reserved Instruction P rototype int Reservedlnstructiondnt inst, int ra, int rb) Descr ct'on The contents of the instruction which was the cause of the exception is passed as inst, and the contents of registers ra and rb are passed as rα and rb The result of the function is placed into register rd Access Disailowec bv T al access This exception occurs when a load, store branch, or gateway refers to an aligned memory operand with an improperh aligned address int AccessDisallowedByVirtualAddressdnt mst int address) Descorcn The contents of the instruction which was the cause of the exception is passed as inst. and the address at which the access was attempted is passed as address Clock Each Euterpe processor includes a clock that maintains processor-clock-cvcle accuracy The value of the clock cycle register is incremented on every cycle regardless of the number of instructions executed on that cycle The clock cycle register is 64-bιts long For testing purposes the clock cycle register is both readable and writable, though in normal operation it should be written only at system initialization time, there is no mechanism provided for adjusting the value in the clock cycle counter without the possibility of losing cycles 63 0 [ clock cycle 64 Clock Event An event is asserted when the value in the clock cycle register is equal to the value in the clock match register, which sets the specified clock event bit in the event register For testing purposes the clock match register is both readable and writable, though in normal operation it is normally written to 64 Waτchdoo Timer A Machine Check is asserted when the \ aiue in the clock cycle register is equal to the value m the watchdog timer registe: The watchdog timer register is both readable and writable, though in normal operation it is usually and penodicallv w ritten with a sufficiently large value that the register does not equal the value in the clock cycle register before the next time it is written 63 0 I watchdog timer j 54 Tally Counter Each Euterpe processor includes two counters that can tally processor-related events or operations The value ot the tally counter registers are incremented on each processor clock cycle in which specined events or operations occur The tally counter registers do not signal Euterpe ev ents It is required that a sufficient number of bits be implemented so that the tallv counter registers overflow no more frequently than once per second 32 bits is sufficient for a 4 GHz clock The remaining unimplemented bits must be zero whenever read, and ignored on write For testing purposes each of the tallv counter registers are both readable and writable, though in normal operation each should be written only at system initialization time, there is no mechanism provided for adjusting the value in the event counter registers without the possibility of losing counts 63 0 tally counter 0 64 63 tally counter 1 64 The tallv counter control register selects one event for each of the event counters to tally 63 32 31 1 6 15 0 0 [tally control Oftally control 1 32 1 6 1 6 The valid values for the tally control fields are given by the following table: tally control field interpretation Control Register Addresses This section is under construction. Software and hardware designers should not infer anything about the value oi the addresses from the ordering or entries in the tentative table below: Reset and Error Recovery Certain external and internal ev ents cause the Euterpe processor to invoke reset or error recover y operations These operations consist ot a full or partial reset ot critical machine state, including initialization of the event thread to begin fetching instructions from the start vector address Software mav determine the nature of the reset or error bv reading the value ot the Cerberus control register, m which finding the reset bit set ( 1 ) indicates that a reset has occurred, finding the clear bit set ( 1 ) and the reset bit cleared (0) indicates that a logic clear has occurred, and finding both the reset and clear bits cleared (0) indicates that a machine check has occurred When either a reset or machine check has been indicated, the contents ot the Cerberus status register contains more detailed information on the cause Reset A reset mav be caused by a Cerberus reset, α write of the Cerberus control register which sets the reset bit or mternαllv detected errors including meltdow n detection, and double machine check A reset causes the Euterpe processor to set the configuration to minimum power and low clock speed, note the cause ot the reset in the Cerberus status register, stabilize the phase locked loops, set the local TLB to translate all local virtual addresses to equal physical addresses and initialize a single event thread to begin execution at the start vector address Other system state is left undefined bv reset and must be explicitly initialized by- software, this explicitly includes the main thread state, global TLB state, superspring state, Hermes channel interfaces, Mnemosyne memory and Cerberus interface devices The code at the start vector address is responsible for initializing these remaining svstem facilities, and reading further bootstrap code from a series ot standard interface devices to be specified D owe r -on Reset A reset occurs upon initial power-on The cause of the reset is noted bv initializing the Cerberus status register and other registers to the reset values noted below Ce r berus-orounded Reset A reset occurs upon observing that the Cerberus SD data signal has been at a logic low level for at least 33 cvcles of the Cerberus SC clock signal The cause of the reset is noted bv initializing the Cerberus status register and other registers to the reset values noted below Cerbe r us Cont r ol Register & ese~ A reset occurs upon writing a one to the reset bit of the Cerberus control register The cause of the reset is noted bv initializing the Cerberus status register and other registers to the reset values noted below 'Verdown Deτeoτed Resez A reset occurs if the temperature is above the threshold set by the meltdown margin field of the Cerberus configuration register. The cause of the reset is noted by setting the meltdown detected bit of the Cerberus status register Dcub'e lyiacrire Check Reset A reset occurs if a second machine check occurs that prevents recovery from the first machine check. Specifically, the occurrence of an exception in event thread, watchdog timer error, or Cerberus transaction error while any machine check cause bit is still set in the Cerberus status register results in a double machine check reset. The cause of the reset is noted by setting the double machine check bit of the Cerberus status register. Clear Writing a one to the clear bit of the Cerberus control register invokes a logic clear A logic clear causes the Euterpe processor to set the configuration to the power and swing levels written in deferred state to the Cerberus power and swing registers, configuration register and Hermes channel configuration registers, stabilize the phase locked loops, set the local TLB to translate all local virtual addresses to equal physical addresses, and initialize a single event thread to begin execution at the start vector address. The cause of the clear is noted by leaving the clear bit of the Cerberus control register set to a one ( 1) at the end of the logic clear. Machine Check Detected hardware errors, such as communications errors in one of the Hermes channels or the Cerberus bus, a watchdog timeout error, or internal cache parity errors, invoke a machine check. A machine check will set the local TLB to translate all local virtual addresses to equal physical addresses, note the cause of the exception in the Cerberus status register, and transfer control of the event thread to the start vector address. This action is similar to that of a reset, but differs in that the configuration settings, main thread state, and Cerberus and i nemosyne state are preserved. Recovery from machine checks depends on the severity of the error and the potential loss of information as a direct cause of the error. The start vector address is designed to reach instruction memory accessed via Cerberus, so that operation of machine check diagnostic and recovery code need not depend on proper operation or contents of any Hermes channel device. The program counter and register file state of the event thread prior to the machine check is lost (except for the portion of the program counter saved in the Cerberus status register), so diagnostic and recovery code must not assume that the register file state is indicative of the prior operating state of the event thread. The state of the main thread is frozen similarly to that of a main thread exception. Machine check diagnostic code determines the cause of the machine check from the processor ' s Cerberus status register, and as required, the Cerberus status and other registers of devices connected to the B teChαnnels. Any outstanding memory transactions may be recovered by a combination of software to re-issue outstanding writes, and by aborting and restarting the main thread execution pipeline to purge outstanding reads Because Cerberus operates much more slowly than the peak speed of the Euterpe processor under normal operation, machine check diagnostic and recovery code will generally consume enough time that real-time interface performance targets may have been missed. Consequently, the machine check recovery software may- need to repair further damage, such as interface buffer underruns and overruns as may have occurred during the intervening time. This final recovery code, which re-mitiαhzes the state of the interface system and recovers a functional event thread state, may return to using the complete machine resources, as the condition which caused the machine check will have been resolved. The following table lists the causes of machine check errors. Parity or uncorrectable error in Euterce cacne Parity or uncorrectable error in Mnemosvne cacne Parity or uncorrectable error in Callicoe memory Parity or uncorrectable error in system-level memory Communications error in Hermes cnaπnels Communications error in Cerberus bus Event Thread exception Watchdog timer machine cneck errors Panτv cr Uncorrectable Ξ rr o r , Cacne When a parity or uncorrectable error occurs in a Euterpe or Mnemosyne cache, such an error is generally non-recoverable. These errors are non-recoverable because the data in such caches may reside anywhere in memory, and because the data in such caches may be the only up-to-date copy of that memory contents Consequently, the entire contents of the memory store is lost, and the severity of the error is high enough to consider such a condition to be a system failure. The machine check provides an opportunity to report such an error before shutting down a system for repairs. There are specific means by which a system may recover from such an error without failure, such as by restarting from a system-level checkpoint, from which a consistent memorv state can be recovered. Parr/ or Urccmectaoie — r,r c r ^ Me ory When a parity of uncorrectable error occurs in Mnemosyne or Calliope memory, such an error may be partially recoverable. The contents of the affected area of memory is lost, and consequently the tasks associated with that memory must generall y be aborted, or resumed from a task-level checkpoint. If the contents of the affected memory can be recovered from mass storage, a complete recovery is possible. If the affected memory is that of a critical part of the operating system, such a condition is considered a system failure, unless recovery can be accomplished from a system-level checkpoint. A communications error in Hermes channels, such as a check byte error, command error, or timeout error, is generally fully recoverable. Bits corresponding to the affected Hermes channel are set in the processor ' s Cerberus status register. Recovery software should determine which devices are affected, by querying the Cerberus status register of each device on the affected Hermes channels. Read and write transactions may have been underway at the time of a machine check. Because the machine check freezes the Hermes channel(s), these transactions will not be completed. Recovery software must search through the memory interface buffers for uncompleted write operations and re-issue them as stores, then must reset the memory interface buffer to a known state. Communications Error m Cemerus Bus A communications error in the Cerberus bus, such as a Cerberus transaction error is generally fully recoverable. A Cerberus transaction error (due to timeout; may result from normal system self-configuration operations to determine the existence of optional devices in the system. Watchdog Timeout Error A watchdog timeout error indicates a general software or hardware failure. Such an error is generally treated as non-recoverable and fatal. Event Thread Exception When an event thread suffers an exception, the cause of the exception and a portion of the virtual address at which the exception occurred are noted in the Cerberus status register. Because under normal circumstances, the event thread should be designed not to encounter exceptions, such exceptions are treated as non-recoverable, fatal errors. Start Vector Address The start vector address is used to initialize the event thread with a program counter upon a reset, clear or machine check. These causes of such initialization can be differentiated by the contents of the Cerberus status register. The start vector address is a virtual address which, when "translated " by the local TLB to a physical address, is designed to access node number zero on the local Cerberus network, which will ordinarity contain an interface to the bootstrap ROM code. The Cerberus/Bootstrap ROM space is chosen to minimize the number of internal Terpsichore resources and Terpsichore interfaces that must be operated to begin execution or recover from a machine check. Bootstrap Code Bootstrap code requirements are a necessary part of the Terpsichore System Architecture, but remains to be specified in a later version of this document. The basic requirements of Terpsichore bootstrap code include power-on initialization of Euterpe, Calliope, and Mnemosyne devices, using Cerberus control registers; handling of machine checks, selection of an interface from which further bootstrap code is obtained. Interfaces should be scanned in a priority- based ordering which gives highest priority to removable/replaceable read-only storage devices, then removable/replaceable read-write devices, then network interfaces, then non-removable storage devices. Cerberus Registers Cerberus registers are internal read/only and read/write registers which provide an implementation-independent mechanism to query and control the configuration of devices in a Terpsichore system. By the use of these registers, a user of a Terpsichore system may tailor the use of the facilities in a general- purpose implementation for maximum performance and utility. Conversely, a supplier of a Terpsichore system component may modify facilities in the device without compromising compatibility with earlier implementations. These registers are accessed via the Cerberus serial bus. As a device component of a Terpsichore system, each Euterpe processor contains a set of Cerberus-accessable configuration registers. Additional sets of configuration registers are present for each additional device in a Euterpe sys.em, including Mnemosyne Memory devices, and Calliope interface devices. Read/only registers supply information about the Terpsichore system implementation in a standard, implementation-independent fashion. Terpsichore software may take advantage of this information, either to verify that a compatible implementation of Mnemosyne is installed, or to tailor the use of the part to conform to the characteristics of the implementation. The read/only registers occupy addresses 0..5. An attempt to write these registers may cause a normal or an error response. Read/write registers select operating modes and select power and voltage levels for gates and signals. The read/write registers occupy addresses 6..9 and 25..43. Reserved registers in the range 10..24 and 44..63 must appear to be read/only registers with a zero value. An attempt to write these registers may cause a normal or an error response. Reserved registers in the range 64..2 16 -1 may be implemented either as read/only registers with a zero value, or as addresses which cause an error response if reads or writes are attempted. The format of the registers is described in the table below. The octlet is the Cerberus address of the register; bits indicate the posifion of the field in a register. The value indicated is the hard-wired value in the register for a read/only register, and is the_ value to which the register is initialized upon a reset for a read/write register. If a reset does not initialize the field to a value, or if initialization is not required by this specification, a * is placed in or appended to the value field. The range is the set of legal values to which a read/write register may be set. The interpretation is a brief description of the meaning or utility of the register field: a more comprehensive description follows this table. octlet bits field name value raπαe interpretation 0 63..16 15..0 octlet 1 Dctlet bits field name value '=' mte r station 2 63 16 15 0 jetlet octlet bits field name value r a- e mterDretation 63 60 59 56 55 54 53 52 51 .48 47 46 45 44 40 39 38 37 36..32 31..30 29..28 27..2 23..21 20..1 15 .0 field name value r ar , αe mtercretation octlet bits fie'd name value r a r ~ce inte r oretat'on 7 63 reset/clear/ 1 P 1 This bit is set when a reset, clear or selftest selftest oceration has been complete completed 62 reset/clear/ P 1 This bit is set when a reset, clear or selftest selftest operation has been status completed successfully 61 meltdown P P 1 This bit is set when the meltdown detected detector has caused a reset 60 double P P 1 [This bit is set when a double machine machine check has caused a reset check 59 other reset P P. 1 (This bit is reserved for indicating cause [additional causes of reset. 53 exception in P P. 1 This bit is set when an exception in event thread event thread has caused a machine check. 57 watchdog P 0 1 This bit is set when a watchdog [timeout error timeout has caused a machine check. 56 Cerberus P P 1 This bit is set when a Cerberus transaction transaction error has caused a error machine check 55 Hermes P O J This bit is set when a Hermes channel channel check byte error has caused check byte a machine check. error 54 Hermes P .J This bit is set when a Hermes channel channel command error has caused command a machine check. error 53 Hermes P P.J This bit is set when a Hermes channel channel timeout has caused a Itimeout error machine check. 52 48 P * P Reserved for other machine check causes. 47 .32 machine P" 0..40 Set to indicate exception code if check detail 95 Exception in event thread. Set to bitmap of which Hermes channels if Hermes channel error. 31 16 machine P P Set to indicate bits 31..16 of the check value of the event thread program program counter at the initiation of a machine counter check. 15 8 raw 0 0..25 Value sampled on specified Hermes channel when input clock is zero (0) 7 0 raw 1 0 25 Value sampled on specitied Hermes channel immediately following sample value in raw 0 register octlet bits field name value ranee i tercretation 8 53 0 oct'et bits field name value value ιnte r Dretatιon 63 0 indirect data 0 20 Read and write to this register to reach physical addresses not otherwise accessable via Cerberus octlet bits field name value raπαe mterDretation 10 24 63 0 octlet 26 233 microunity octlet 31 234 microunity octlet 32 43 field name value ranαe interpretation P P Reserved for use with additional Hermes channel interfaces O / Idenzi-lcaϊon Pegis:e r s The identification registers in octlets 0..3 comply with the requirements of the Cerberus architecture. MicroUnity ' s company identifier is: 0000 0000 0000 0010 1100 0101. MicroUnity ' s architecture code for Euterpe is specified by the following table: Internal coαe name Code numoer Euterpe 0x00 40 a3 24 69 93 Euterpe architecture revisions are specified by the following table: MicroUnity's Euterpe implementor codes are specified by the following table: MicroUnity's Euterpe, as implemented by MicroUnity, uses implementation codes as specified by the following table: MicroUnity's Euterpe, as implemented by MicroUnity, uses manufacturer codes as specified by the following table: MicroUnity's Euterpe, as implemented by MicroUnity, and manufactured by MicroUnity, uses manufacturer revisions as specified by the following table: Architecture Description Registers The architecture description registers in octlets 4 and 5 comply with the Cerberus specification and contain a machine-readable version of the architecture parameters: A and described in this document. These registers are still under construction and will contain non-zero values in a later revision of this document. Parameters will describe number of Hermes ports, size of internal caches, integral ion of Call iope and Mnemosyne functions. Ccn oi Register The control register is a 64-bit register with both read and write access. It is altered only by Cerberus accesses: Euterpe does not alter the values written to this re -g»i*ster. The reset bit of the control register complies with the Cerberus specification and provides the ability to reset an individual Euterpe device in a Terpsichore system. Writing a one ( 1 ) to this bit is equivalent to a power-on reset or a broadcast Cerberus reset (low level on SD for 33 cycles) and resets configuration registers to their power-on values, which is an operating state that consumes minimal current, and also causes all internal high-bandwidth logic to be reset. The duration of the reset is sufficient for the operating state changes to have taken effect. At the completion of the reset operation, the reset/clear/selftest complete bit of the status register is set, the reset/clear/selftest status bit of the status register is set, and the reset bit of the control register is set. The clear bit of the control register complies with the Cerberus specification and provides the ability to clear the logic of an individual Euterpe device in a system. Writing a one (1) to this bir causes all internal high-bandwidth logic to be reset, as is required after reconfiguring power and swing levels. The duration of the reset is sufficient for any operating state changes to have taken effect. At the completion of the reset operation, the reset/clear/selftest complete bit of the status register is set, the reset/clear/selftest status bit of the status register is set, and the clear bit of the control register is set. The selftest bit of the control register complies irh the Cerberus specification and provides the ability to invoke a selftest on an individual Euterpe device in a system. However, Euterpe does not define a selftest mechanism at this time, so setting this bit will immediately set the reset/clear/selftest complete bit and the reset/clear/selftest status bit of the status register. The channel under test field of the control register provides a mechanism to test and adjust skews, on a single Hermes channel at a time. The field is set to the channel number for which the cidle 0, cidle 1, raw 0, and raw 1 fields are active. The cidle 0 and cidle 1 fields of the control register provide a mechanism to repeatedly sent simple patterns on the selected Hermes output channel for purposes of testing and skew adjustment. For normal operation, the cidle 0 field must be set to zero (0), and the cidle 1 field must be set to all ones (255). The status register is a 64-bit register with both read and write access, though the only legal value which may be written is a zero, to clear the register. The result of writing a non-zero value is not specified. The reset/clear/selftest complete bit of the status register complies with the Cerberus specification and is set upon the completion of a reset, clear or selftest operation as described above. The reset/clear/selftest status bit of the status register complies with the Cerberus specification and is set upon the successful completion of a reset, clear or selftest operation as described above. The meltdown detected bit of the status register is set when the meltdown detector has discovered an on-chip temperature above the threshold set by the meltdown threshold field of the Cerberus configuration register, which causes a reset to occur. The double machine check bit of the status register is set when a second machine check occurs that prevents recovery from the first machine check, or which is indicative of machine check recovery software failure. Specifically, the occurrence of an exception in event thread, watchdog timer error, or Cerberus transaction error while any machine check cause bit of the status register is still set, or any Hermes error while the exception in event thread bit of the status register is set in the Cerberus status register results in a double machine check reset. The other reset cause bit of the status register is reserved for the indication of other causes of reset. The exception in event thread bit of the status register is set when an event thread suffers and exception, which causes a machine check. The exception code is loaded into the machine check detail field of the status register. The watchdog timeout error bit of the status register is set when the watchdog timer register is equal to the clock cycle register, causing a machine check. The Cerberus transaction error bit of the status register is set when a Cerberus transaction error (bus timeout, invalid transaction code, invalid address) has caused a machine check. Note that Cerberus aborts, including locally detected parity errors, should cause bus retries, not a machine check. The Hermes check byte error bit of the status register is set when a Hermes check byte error has caused a machine check. The bit corresponding to the Hermes channel number which has suffered the error is set in the machine check detail field of the status re -goi"ster. The Hermes command error bit of the status register is set when a Hermes command error has caused a machine check. The bit corresponding to the Hermes channel number which has sutfered the error is set in the machine check detail field of the status register The Hermes timeout error bit of the status register is set when aByteChannel timeout error has caused a machine check The bit corresponding to the Hermes channel number which has suffered the error is set in the machine check detail field of the status register The machine check detail field of the status register is set when a machine check has been completed. For a Hermes channel error ( check byte, command or timeout), the value indicates, via a bit-mask. BvteChannels for which machine checks have been reported. For an exception in event thread, the value indicates the tvpe of exception for which the most recent machine check has been reported The machine check program counter tield of the status register is loaded with bits 31 16 of the event thread program counter at which the most recent machine check has occurred. The value in this field provides a limited diagnostic capability for purposes of software development or possibly for error recovery The raw 0 and raw 1 fields of the status register contain the values obtained from two adjacent samples of the specified Hermes input channel. The raw 0 field contains a value obtained when the input clock was zero (0), and the raw 1 field contains the value obtained on the immediately following sample, when the input clock was (1). Euterpe must ensure that reading the status register produces two adjacent samples, regardless of the timing of the status register read operation on Cerberus. These fields are read for purposes of testing and control of skew in the Hermes channel interfaces. Power and Swing Calibratio n R egisters Euterpe uses a set of configuration registers to control the power and voltage levels used for internal high-bandwidth logic and memory The details of programming these registers are described below. Eight-bit fields separately control the power and voltage levels used in a portion of the Euterpe circuitry. Each such field contains configuration data in the following format: 7 6 5 4 3 2 0 fb I ref I Iyl | res | power and swing controls O 97/07450 The range of valid values and the interpretation of the fields is given by the following table: Power and swing ccntrol field interpretation The reference voltage level, voltage swing level and resistor load value are model figures for a full-swing, lowest-power logic gate output. The actual voltage levels and resistor load values used in various circuits is geometrically related to the values in the tables below. Designed typical, full-speed settings for the ref, Ivl and res fields are ref=250 millivolts. lvl=500 millivolts, and res=2.5 kilohms. The ref field, together with the swing fine tuning field of the configuration register, control the reference voltage level used for logic circuits in the specified knob domain. Values and interpretations of the ref field are given by the following table, with units in millivolts: Reference level control field interpretation The Ivl field, together with the swing fine tuning field of the configuration register, control the voltage swing level used for logic circuits in the specified knob domain. Values and interpretations of the Ivl field are given by the following table, with units in millivolts: swing fine tuning Ivl 0 1 275 300 325 350 375 400 425 450 475 500 525 550 575 600 650 700 Voltage swing level contro field interpretation The res field, together with the process control field of the configuration register, control the PMOS load resistance value used for logic circuits in the specified knob domain. Values and interpretations of the Ivl field are given by the following table, with units in kilohms The table below giv es resistance values with nominal process parameters. Resistor control πe'α interpretation When the process control field of the configuration register is set equal to the PMOS drive strength field of the configuration register, nominal PMOS load resistance values are as given by the following table, with units in kilohms When Mnemosyne is reset, a default value of 0 is loaded into each 0 field, 3 in each ref field, 3 in each Ivl field and 1 in each res field, which is a byte value of 121. The process control field of the configuration register is set to 5, and the swing fine tuning field is set to 1. These setungs correspond to a chip with nominal processing parameters, low power and high voltage swing operation. For nominal operating conditions, the ref field is set to 2, the Ivl field is set to 2, and the res field is set to 5, which is byte value of 85 The process control field is set equal to the PMOS strength field, and the swing fine tuning field is set to 1 Configuration Register A Configuration register is provided on the Euterpe processor to control the fine- tuning of the Hermes channel configuration, to control the global process parameter settings, to control the two phase-locked loop frequency generators, and to control the temperature sensors and read temperature values. The resistor fine tuning field of the configuration register controls the analog bias settings for PMOS loads in Hermes channel input and output termination circuits. in order to accomodate variations in circuit paramaters due to the manufacturing process, and to provide fine-tuning of the input and output impedence levels. Under normal operating conditions, four times (4") the value read from the PMOS drive strength field should be written into the resistor fine tuning field. In order to provide fine-tuning of the input and output impedence levels, an external measurement of the impedence or voltage levels is required. An change of the resistor fine tuning field causes a proportional change in the input and output impedence levels. The interpretation of the field is given by the table: The swing fine tuning field of the configuration register controls a small offset in the reference voltage and logic swing voltage for internal logic circuits. The swing fine tuning voltage is added to the output current field of the Hermes channel configuration registers to select the output current. The interpretation of the field is given by the table: swing fine tuning field interpretation The process control field of the configuration register controls the analog bias settings for PMOS loads in internal logic circuits, in order to accomodate variations in circuit parameters due to the manufacturing process. Under normal operating conditions, the value read from the PMOS drive strength field should be written into the process control field The interpretation of the field is given by the table: The PMOS drive strength field of the configuration register is a read/only field that indicates the drive strength, or conductance gain, of PMOS devices on the Euterpe chip, expressed as a digital binary value. This field is used to calibrate the power and voltage level configuration, given variations in process characteristics of individual devices. The interpretation of the field is given by the table: There are two identical phase locked-loop (PLL) frequency generators, designated PLLO and PLLl. These PLLs generate internal and external clock signals of configurable frequency, based upon an input clock reference of either 50 MHz or 500 MHz. PLLO controls the internal operating frequency of the Euterpe processor, while PLLl controls the operating frequency of the Hermes channel interfaces. The configuration fields for PLLO and PLLl have identical meanings, described below: The PLLO divide ratio and PLLl divide ratio fields select the divider ratio for each PLL, where legal values are in the range 8..23. These divider ratios permit clock signals to be generated in the range from 400 MHz to 1J5 GHz. when the input clock reference is at 50 MHz, with prescaling bypassed, or at 500 MHz with prescaling used. Setting the PLLO feedback bypass bit or the PLLl feedback bypass bit of the configuration register causes the generated clock bypass the PLL oscillator and to operate off the input clock directly. Setting these bits causes the frequency generated to be the optionally prescaled reference clock. These bits are cleared during normal operation, and set by a reset. The PLLO range field and the PLLO range field of the configuration register are used to select an operating range for the internal PLLs. If the PLL range is set to zero, the PLL will operate at a low frequency (below O.xxx GHz ), if the PLL range is set to one. the PLL will operate at a high frequency (above O.xxx GHz). At reset this bit is cleared, as the input clock frequency is unknown. Setting the PLL prescaler bypass bit of the configuration register causes the phase-locked loops PLLO and PLLl to use the input clock directly as a reference clock. This bit is cleared during normal operation with a 500 MHz input clock, in which the input clock is divided by 10. and is set during normal operation with a 50 MHz input clock. At reset this bit is cleared, as the input clock frequency is unknown. Setting the conversion prescaler bypass bit of the configuration register causes the temperature conversion unit to use the input clock directly as a reference clock. Otherwise, clearing this bit causes the input clock to be divided by 10 before use as a reference clock. The reference clock frequency of the temperature conversion unit is nominally 50 MHz, and in normal operation, this bit should be set or cleared, depending on the input clock frequency. At reset this bit is cleared, as the input clock frequency is unknown. The meltdown margin field controls the setting of the threshold at which meltdown is signalled. This field is used to test the meldown prevention logic. The interpretation of the field is given by the table below with a tolerance of ±6 degrees C. and 5 degrees C hysteresis: The conversion start bit controls the initiation of the conversion of a temperature sensor or reference to a digital value. Setting this bit causes the conversion to begin, and the bit remains set until conversion is complete, at which time the bit is cleared. The conversion selection field controls which sensor or reference value is converted to a digital value. The interpretation of the field is given by the table below: The conversion counter field is set to the two's complement of the downslope count. The counter counts upward to zero, at which point the upslope ramp begins, and continues counting on the upslope until the conversion completes. Configuration registers are provided on the Euterpe processor to control the timing, current levels, and termination resistance for each of the twelve Hermes channel high-bandwidth channels. A configuration register is dedicated to the control of each Hermes channel, and additional information in the configuration register at octlet 31 controls aspects of the Hermes channel circuits in common. The Hermes channel configuration registers are Cerberus registers 32..43, where 32 corresponds to Hermes channel 0, and where 43 corresponds to Hermes channel 11. The quadrature bypass bit controls whether the HiC clock signal is delayed by approximately 7 of a HiC clock cycle to latch the Hi7. . rj bits. In normal, full speed operation, this bit should be cleared to a zero value. If this bit is set, the quadrature delay is defeated and the HiC clock signal is used directly to latch the H17..0 bits. The quadrature range bit is used to select an operating range to the quadrature delay circuit. If the quadrature range is set to zero, the circuit will operate at a low frequency (below O.xxx GHz), if the quadrature range is set to one, the circuit will operate at a high frequency (above O.xxx GHz). The output termination bit is used to select whether the output circuits are resistively terminated. If the bit is set to a zero, the output has high impedence; if the bit is set to one, the output is terminated with a resistance equal to the input termination. At reset, this bit is set to one, terminating the output. The termination resistance field is used to select the impedence at which the Hermes channel inputs, and optionally the Hermes channel outputs are terminated. The resistance level is controlled relative to the setting of the resistor fine tuning field of the configuration register. The interpretation of the field is given by the table, with units in Ohms and nominal PMOS conductance and bias settings: The output current field is used to select the current at which the Hermes channel outputs are operated. The interpretation of the field is given by the table, with units in mA: The output voltage swing is the product- of the composite termination resistance: (input termination resistance" J+output termination resistance" 1 )" 1 , and the output current. The output voltage swing should be set at or below 700 mV, and is normally set to the lowest value which permits a sufficiently low bit error rate, which depends upon the noise level in the system environment. The skew fields individually control the delay between the internal Hermes channel output clock and each of the HoC and Ho7..0 high bandwidth output channel signals. Each skew field contains two three-bit values, named digital skew and analog skew as shown below: 5 3 2 0 I digital skew | analog skew | The digital skew fields set the number of delay stages inserted in the output path of the HoC and the Ho7..0 high-bandwidth output channel signals. The analog skew fields control the power level, and thereby control the switching delay, of a single delay stage. Setting these fields permits a fine level of control over the relative skew between output channel signals. Nominal values for the output delay for various values of the digital skew and analog skew fields are given below, assuming a nominal setting for the Hermes channel knob: When Euterpe is reset, a default value of 0 is loaded into the digital skew and 1 is loaded into the analog skew fields, setting a minimum output delay for the HoC and Ho7..0 signals. Mnemosvne Memorv MicroUnity's Mnemosyne memory architecture is designed for ultra-high bandwidth systems. The architecture integrates fast communication channels with SRAM caches and interfaces to standard DRAM. The Mnemosyne interfaces include byte-wide input and output channels intended to operate at rates of at least 1 GHz. These channels provide a packet communication link to synchronous SRAM cache on chip and a controller for external banks of conventional DRAM components. Mnemosyne provides second- level cache and main memory for MicroUnity ' s Terpsichore system architecture. However, Mnemosyne is useful in many memory applications. Mnemosyne's interface protocol embeds read and write operations to a single memory space into packets containing command, address, data, and acknowledgement. The packets include check codes that will detect single-bit transmission errors and multiple-bit errors with high probability. As many as eight operations in each device may be in progress at a time. As many as four Mnemosyne devices may be cascaded to expand the cache and memory and to improve the bandwidth of the DRAM memory. Mnemosyne's SRAM arrays are organized as a set of small blocks, which are combined to provide a cache containing logical memory data of a fixed word size. Dynamically-configured block-level redundancy supports the elimination of faulty blocks without requiring the use of non-volatile or one-time-programmable storage. Mnemosyne's DRAM interface provides for the direct connection of multiple banks of standard DRAM components to a Mnemosyne device. Variations in access time, size, and number of installed parts all may be accommodated by reading and writing of configuration registers. The interface supports interleaving to enhance bandwidth, and page mode accesses to improve latency for localized addressing. Euterpe uses Mnemosyne devices as a second-level cache, main-memory expansion, and optionally containing directory information. Each Mnemosyne device in turn supports up to four banks of DRAM, each 72 bits wide (64 bits + ECC). Using standard DRAM components, Terpsichore and Mnemosyne achieve bandwidth in excess of 9 Gbytes/sec to secondary cache and 2 Gbytes/sec to main memory. Terpsichore may use twice or four times the number of Mnemosyne devices to expand the cache and memory and to increase the bandwidth of the main memory system to in excess of 8 Gbytes/sec. Architecture Framework The Mnemosyne architecture builds upon MicroUnity's Hermes high-bandwidth channel architecture and upon MicroUnity's Cerberus serial bus architecture, and complies with the requirements of Hermes and Cerberus. Mnemosyne uses parameters A and W as defined by Hermes. The Mnemosyne architecture defines a compatible framework for a family of implementations with a range of capabilities. The following implementation- defined parameters are used in the rest of the document in boldface. The value indicated is for MicroUnity ' s first Mnemosyne implementation. Interfaces and Block Diagram Mnemosyne uses two Hermes unidirectional, byte-wide, differential, packet- oriented data channels for its main, high-bandwidth interface between a memory control unit and Mnemosyne's memory. This interface is designed to be cascadeable, with the output of a Mnemosyne chip connected to the input of another, to expand the size of memory that can be reached via a single set of data W channels. An external memory control unit is in complete control of the selection and timing of operations within Mnemosvne and in complete control of the timing and content of information on the high-bandwidth interfaces. A Cerberus bit-serial interface provides access to configuration, diagnostic and tester information, using TTL signal levels at a moderate data rate. Mnemosyne contains additional interfaces to conventional dynamic random- access memory devices (DRAM) using TTL signals. Each Mnemosyne device contains output signals to independently control four banks of DRAM memory; each bank is nominally 9 bytes wide, and connects to a single set of bidirectional data interface pins. Each DRAM bank may use 24-bit addresses, to handle up to l6M-"word" DRAM memory capacity (such as 16Mx4 organized, 64-Mbit DRAM). Up to four banks of DRAM may be connected to each Mnemosyne device, permitting up to 0.5 Gbyte of DRAλl per Mnemosyne chip. Nearly all Mnemosyne circuits use a single power supply voltage, nominally at 3.3 Volts (5% tolerance). A second voltage of 5.0 Volts (5% tolerance) is used only for TTL interface circuits. Power dissipation is TBD. Initial packaging is TAB (Tape Automated Bonding). Pin assignments are to be defined: there are 174 signal pins and 466 pins for 3.3 V power, 5.0V power and substrate, for a total of 640 pins. "* 8 Internal circuit documentation names this signal VDDO. The following is a diagram of the Mnemosvne device interfaces (Numerical values are shown for MicroUnity ' s first implementation.) Mnemosyne defines two regions: a memory region, implemented by an on-device static RAM memory cache backed by standard DRAM memory devices, and a configuration region, implemented by on-device read-only and read/write registers. These regions are accessed by separate interfaces; the Hermes channel used to access the memory region, and the Cerberus serial interface used to access the configuration region. These regions are kept logically separate. The Mnemosyne logical memory region is an array of 2 8A words of size W bytes. Each memory access, either a read or write, references all bytes of a single block. All addresses are block addresses, referencing the entire block. Mnemosyne's DRAM memory physically consists of one or more banks of multiplexed-address DRAM memory devices. A DRAM bank consists of a set of DRAM devices which have the corresponding address and control signals connected together, providing one word of W bytes of data plus ECC information with each DRAM access. Mnemosyne's SRAM memory is a write-back (write-in) single-set (direct-mapped ) cache for data originally contained in the DRAM memory. All accesses to Mnemosyne memory space maintain consistency between the contents of the cache and the contents of the DRAM memory. Mnemosyne ' s configuration region consists of read-only and read/write registers. The size of a logical block in the configuration memory space is eight bytes: one octlet. Communications Channels High - bandwidth Mnemosyne uses the Hermes high-bandwidth channel and protocols, implementing a slave device. Mnemosyne operates two Hermes high-bandwidth communications channels, one input channel and one output channel. Mnemosyne uses the Hermes packet structure. Mnemosyne's SRAM memory- serves as the Hermes-designated cache, and Mnemosyne DRAM memory corresponds to the Hermes -designated device. Configuration-region registers provide a low-level mechanism to detect skew in the byte-wide input channel, and to adjust skew in the byte-wide output channel. This mechanism may be employed by software to adaptively adjust for skew in the channels, or set to fixed patterns to account for fixed signal skew as may arise in device-to-device wiring. Serial A Cerberus serial bus interface is used to configure the Mnemosyne device, set diagnostic modes and read diagnostic information, and to enable the use of the part within a high-speed tester. The serial port uses the Cerberus serial bus interface. DRAM The DRAM interface uses TTL levels to communicate with standard, high- capacity dynamic RAM devices. The data path of the interface is 8W+ e bits. The DRAM components used may have a maximum size of 2 2P words by k bits, where the minimum value of k is determined by capacitance limits. (Larger values of k, up to 8W+e, meaning fewer components are required to assemble a word of DRAMs, are always acceptable.) Error Handling Mnemosyne performs error handling compliant with Hermes architecture. For the current implementation, the following errors are designed to be detected and known not detected bv design: Detection of an uncorrectable error in either the SRAM cache or the DRAM memory results in the generation of an error response packet and other actions more fully described elsewhere. Upon receipt of the error response packet, the packet originator must read the status register of the reporting device to determine the precise nature of the error. Mnemosyne devices reporting an invalid packet will suppress the receipt of additional packets until the error is cleared, by clearing the status register. However, such devices may continue to process packets which have already been received, and generate responses. Upon taking appropriate corrective actions and clearing the error, the packet originator should then re-send any unacknowledged commands. Because of the large difference in clock rate between the high-bandwidth Hermes channel and the Cerberus serial bus interface, it is generally safe to assume that, after detecting an error response packet, an attempt to read the status register via Cerberus will result in reading stable, quiescent error conditions and that the queue of outstanding requests will have drained. After clearing the status register via Cerberus, the packet originator may immediately resume sending requests to the Mnemosyne device. Cerberus Registers Mnemosyne ' s configuration registers comply with the Cerberus and Hermes specifications. Configuration registers are internal read/only and read/write registers which provide an implementation-independent mechanism to query and control the configuration of a Mnemosyne device. By the use of these registers, a user of a Mnemosyne device may tailor the use of the facilities in a general- purpose implementation for maximum performance and utility. Conversely, a supplier of a Mnemosyne device may modify facilities in the device without compromising compatibility with earlier implementations. Read/only registers supply information about the Mnemosyne implementation in a standard, implementation-independent fashion. A Mnemosyne user may take advantage of this information, either to verify that a compatible implementation of Mnemosyne is installed, or to tailor the use of the part to conform to the characteristics of the implementation. The read/only registers occupy addresses 0..5. An attempt to write these registers may cause a normal or an error response. Read/write registers select the mapping of addresses to SRAM and DRAM banks, control the internal SRAM and DRAM timing generators, and select power and voltage levels for gates and signals. The read/write registers occupy addresses 6..11. 16.J9, and 32. Reserved registers in the range 12..15, 20..31. and 33..63 must appear to be read/only registers with a zero value. An attempt to write these registers may cause a normal or an error response. Reserved registers in the range 64..2 16 -1 may be implemented either as read/only registers with a zero value, or as addresses which cause an error response if reads or writes are attempted. The format of the registers is described in the table below. The octlet is the Cerberus address of the register; bits indicate the posifion of the field in a register. The value indicated is the hard-wired value in the register for a read/only register, and is the value to which the register is initialized upon a reset for a read/write register. If a reset does not initialize the field to a value, or if initialization is not required by this specification, a * is placed in or appended to the value field. The range is the set of legal values to which a read/write register may be set. The interpretation is a brief description of the meaning or utility of the register field; a more comprehensive description follows this table. octlet 0 octlet bits field name value ranαe mterDretation 1 63..16 15..0 ;ctlet 2 cctlet bits 3 63..16 octlet bits field name valu interoret ion 4 63..60 59..56 55..48 47..40 39..36 36..32 31..28 27..24 23..2 19..1 15..0 octlet bits field name value ranαe interoretation 5 63.0 O 97/07450 octlet octlet bits field name ■ ai ue r 2" ιnte r cre'atιon 63 reset/clear/ P 1 This bit is set wnen a reset clear or selftest selftest ooeration has been complete completed 52 reset/clear/ P This bit is set when a reset clear or selftest selftest operation has been status completed successfully 61 check byte P P 1 This bit is set when a receiveα input error packet has an incorrect check byte 60 address erroriO P 1 This bit is set when a receiveα input request has an address not present on the device as configured 59 command P P 1 This bit is set when a packet is error received on the Hermes input channel with an imorooer command 58 un¬ P P 1 This bit is set when an uncorrectable correctable error is discovered in memory ECC error correctable P This bit is set when a correctable ECC error error is discovered in memory other error P P 1 This bit is set when other errors not otherwise specified occur P P Reserved PMOS drive 0 15 This read/only field indicates the strength drive strength of PMOS devices expressed as a digital binary value 47 41 P P Reserved 40 PLL in range P 1 This bit indicates that the Hermes input channel clock and the PLL are at rates such that the PLL can lock 39 30 P P Reserved 29 ECC locationp 0 if ECC error was in cache memory, flag 1 if ECC error was in DRAM memory 28 dirty flag 0 P 1 Dirty bit if error was in cache memory 27 24 ECC P P extend ECC syndrome value when e syndrome > 8 extension 23 16 ECC P 25 Value of syndrome encountered on syndrome previous correctable or uncorrectable ECC error 15 8 raw O P 25 Value sampled on Hermes input channel when input clock is zero (0) 7 0 raw 1 255 0 25 Value sampled on Hermes input 5 channel immediately following sample value in raw O register O 97/07450 octlet cits field name va'ue r aπαe mteroretat'on 8 63 32 31 0 field name value r anαe interoretation 7 0 octlet bits field name value ranαe inter retation 10 63 .56 55 48 47 40 39 32 31 30 .24 23..0 octlet bits field name value ranαe mterDretation 11 15 63. 0 |0 P Reserved octlet 1 6 field name value ra"s interoretation analog skewpxc2 25 Set power and voltage swing leveis bit 7 n Ho7 skew delay circuits. analog skew Pxc2 25 Set power and voltage swing levels bit 6 in Ho6 skew delay circuits. analog skew Pxc2 25 Set power and voltage swing levels bit 5 n Ho5 skew delay circuits. analog skew Pxc2 25 Set power and voltage swing levels bit 4 in Ho4 skew delay circuits. analog skew Pxc2 25 Set power and voltage swing levels bit 3 in Ho3 skew delay circuits. analog skew Pxc2 25 Set power and voltage swing levels bit 2 in Ho2 skew delay circuits. analog skew Pxc2 25 Set power and voltage swing levels bit 1 in Ho1 skew delay circuits. analog skew Pxc2 .25 Set power and voltage swing levels bit 0 in HoO skew delay circuits. octlet bits field name value raroe interoretation 18 63..56 SRAM pipe Pxc2 CO Set power and voltage swing levels in SRAM pipeline circuits. 55..48 DRAM data pxc2 .25 Set power and voltage swing levels n DRAM data circuits. 47..40 DRAM Pxc2 25 Set power and voltage swing levels address in DRAM address circuits. 39..32 PLL in range Pxc2 25 Set power and voltage swing levels indicator i inn P ΓLLL i mn--rraanπggee d αeetieecctioorr c ciirrccuuiittss.. 31..24 PLL phase Pxc2 25 Set power and voltage swing levels detector in PLL phase detector circuits. 23..16 forward Pxc2 ..25 Set power and voltage swing levels logic i inn p paacckKeett f Toorrwwaarrdαiinngg l looggiicc cciirrccuuiittss.. 15..8 forward PLA Pxc2k .25 Set power and voltage swing levels in packet forwarding PLA. 7..0 tester logic Pxc2 .25 Set power and voltage swing levels in tteesstteerr llooααiicc cciirrccuuiittss.. field name value rar ; mterDretation octlet bits field name value ranαe interoretation 33..63 63..0 P P Reserved for use with additional redundant blocks. Identification Registers The identification registers in octlets 0..3 comply with the requirements of the Cerberus architecture. MicroUnity ' s company identifier is: 0000 0000 0000 0010 1100 0101. MicroUnity ' s architecture code for Mnemosyne is specified by the following table: Mnemosyne architecture revisions are specified by the following table: MicroUnity ' s Mnemosyne implementor codes are specified by the following table: MicroUnity ' s Mnemosyne, as implemented by MicroUnity, uses implementation codes as specified by the following table: MicroUnity's Mnemosyne, as implemented by MicroUnity, uses manufacturer codes as specified by the following table: MicroUnity's Mnemosyne, as implemented by MicroUnity, and manufactured by the Rollers, uses manufacturer revisions as specified by the following table: Architecture Descriotipn Registers The architecture description registers in octlets 4 and 5 comply with the Cerberus and Hermes specifications and contain a machine-readable version of the architecture parameters: A , W , C , N , D , R, P , K, E , and I described in this document. Control Register The control register is a 64-bit register with both read and write access. It is altered only by Cerberus accesses: Mnemosyne does not alter the values written to this register. The reset bit of the control register complies with the Cerberus specification and provides the ability to reset an individual Mnemosyne device in a system. Setting this bit is equivalent to a power-on reset or a broadcast Cerberus reset (low level on SD for 33 cycles) and resets configuration registers to their power-on values, which is an operating state that consumes minimal current. At the completion of the reset operation, the reset/clear/selftest complete bit of the status register is set, and the reset/clear/selftest status bit of the status register is set. The clear bit of the control register complies with the Cerberus specification and provides the ability to clear the logic of an individual Mnemosyne device in a system. Setting this bit causes all internal high-bandwidth logic to be reset, as is required after reconfiguring power and swing levels. At the completion of the reset operation, the reset/clear/selftest complete bit of the status register is set, and the reset/clear/selftest status bit of the status register is set. The selftest bit of the control register complies with the Cerberus specification and provides the ability to invoke a selftest on an individual Mnemosyne device in a system. However, Mnemosyne does not define a selftest mechanism at this time, so setting this bit will immediately set the reset/clear/selftest complete bit and the reset/clear/selftest status bit of the status register. The tester bit of the control register provides the ability to use a Mnemosyne part as a component of a high-bandwidth test system for a Mnemosyne or other part using the high-bandwidth Hermes channel. In normal operation this bit must be cleared. When the tester bit is set, Mnemosyne is configured as either a signal source or signal analyzer, depending on the setting of the source bit of the control register. Four Mnemosyne parts are cascaded to perform the signal source or signal analyzer function. When the isolate/synch bit is set, a synchronization pattern is transmitted on the Hermes output channel and received on the Hermes input channel to synchronize the cascade of four Mnemosynes; the isolate/synch bits must be turned off starting at the end of the cascade to properly terminate the synchronization operation. When not in tester mode, the isolate/synch bit of the control register is used to initialize the SRAM cache and perform functional testing of the SRAM cache. This bit must be cleared in normal operation. Setting this bit and setting the ECC disable bit of the control register suppresses cache misses and dirty cache line writebacks, so that the contents of the SRAM cache can be tested as if it were simple SRAM memory. A read-allocate command returns the octlet data from the SRAM cache entry that would be used to cache the requested location, the data is unconditionally returned, regardless of the contents of the tag, dirty and ECC fields of the SRAλl cache entry. A read-noallocate command returns an octlet in the following format: 48 47 8 7 0 tag I undefined | ECC | 1 2 1 3 40 A write-allocate command writes the octlet data, along with the dirty bit set, the tag corresponding to the requested location, and valid ECC data into the SRAM cache entry that would be used to cache the requested location. A wπte- noallocate command writes the octlet data, along with the dirty bit cleared, the tag corresponding to the requested location, and ECC data as if the dirty bit was set, into the SRAM cache entry that would be used to cache the requested location The ECC seed field of the control register can be set to alter the ECC data that would otherwise be written to the SRAM cache entry, to write completely arbitrary patterns, or to write patterns in which the dirty bit is cleared and the ECC data is value. The ECC disable bit of the control register causes Mnemosyne to ignore ECC errors in the SRAM cache and in the DRAM memory. This bit may be set during normal operation of Mnemosyne. The module id field of the control register sets the module address for Mnemosyne. The module address defines which one of four module addresses Mnemosyne will select to answer to read and write requests. Setting the PLL bypass bit of the control register causes the internal clocking of the high-bandwidth logic to operate off the input clock directly. This bit is cleared during normal operation. The PLL range field of the control register is used to select an operating range for the internal PLL. A three-bit field is reserved for this function, of which one bit is currently defined: if the PLL range is set to zero, the PLL will operate at a low frequency (below O.xxx GHz ), if the PLL range is set to one, the PLL will operate at a high frequency (above O.xxx GHz). The output slope fields of the control register set the slew rate for the TTL outputs used for DRAM control, address and data signals, as detailed in a following section. Mnemosyne uses a sufficiently high-frequency clock that internal SRAM timing can be controlled by synchronous logic, rather than asynchronous or self-timed logic. Internal SRAM timing may be controlled by loading values into configuration registers. The current specification reserves four bits for control of SRAM timing; one is currendy used. The SRAM timing bit is normally cleared, providing internal SRAM cycle time of 4 clock cycles. Setting the SRAM timing bit extends the cycle time to 5 clock cycles. The ECC seed field of the control register provides a mechanism to cause ECC errors and thus test the ECC circuits. The field reserves 12 bits for this purpose, 8 bits are used in the current implementation. The field must be set to zero for normal operation The v alue of the held is xor'ed against the ECC value normally computed for write operation The cidle 0 and cidle 1 fields of the control register provide a mechanism to repeatedly sent simple patterns on the Hermes output channel for purposes ot testing and skew adjustment For normal operation, the cidle 0 held must be set to zero (0), and the cidle 1 held must be set to all ones (255) The status register is a 64-bit register with both read and write access, though the only legal value which mav be written is a zero, to clear the register The result of writing a non-zero value is not specified The reset/clear/selftest complete bit of the status register complies with the Cerberus specification and is set upon the completion of a reset, clear or selftest operation as described above The reset/clear/selftest status bit of the status register complies with the Cerberus specification and is set upon the successful completion of a reset, clear or selftest operation as described above. The check byte error bit of the status register is set when a received input packet has an incorrect check byte. The packet is otherwise ignored or forwarded to the Hermes output channel, and an error response packet is generated. The address error bit of the status register is set when a received input request packet has an address which is not present on the device as currently configured An error response packet is generated. The command error bit of the status register is set when a packet is received on the Hermes input channel with an improper command, such as a read, write or error response packet. The uncorrrectable ECC error bit of the status register is set on the first occurrence of an uncorrectable ECC error in either the SRAM cache or the DRAM memory. The ECC location flag is set or cleared, indicating whether the error was in the cache memory (cleared, 0) or the DRAM memory (set, 1). The ECC syndrome field of the status register is loaded with the syndrome of the data for which the error was detected. The ECC addr register is loaded with the address of the data at which the error was detected. An error response packet is generated. Once one uncorrectable ECC error is detected, no further correctable or uncorrectable ECC errors are reported in the status register until this error is cleared by writing a zero value into the status register. The correctable ECC error bit of the status register is set on the first occurrence of a correctable ECC error in either the SRAM cache or the DRAM memory, provided an uncorrectable ECC error has not already been reported. The ECC location flag is set or cleared, indicating whether the error was in the cache memory (cleared, 0) or the DRAM memory (set, 1). The dirty flag indicates, for an error in the cache memory, the value of the dirty bit. The ECC syndrome field of the status register is loaded with the syndrome of the data for which the error was detected. The ECC addr register is loaded with the address of the data at which the error was detected. Once one uncorrectable ECC error is detected, no further correctable ECC errors are reported in the status register until this error is cleared by writing a zero value into the status register. The occurrence of this error will cause a response packet to be generated with a "stomped" check byte pattern, but is not explicitly reported with an error response packet. The other error bit of the status register is set when errors not otherwise specified occur. There are no errors of this class reported by the current implementation. The PMOS drive strength field of the status register is a read/only field that indicates the drive strength, or conductance gain, of PMOS devices on the Mnemosyne chip, expressed as a digital binary value. This field is used to calibrate the power and voltage level configuration, given variations in process characteristics of individual devices. The interpretation of the field is given by the table: The PLL in range bit of the status register indicates that the Hermes input channel clock and the PLL oscillator are running at sufficiently similar rates such that the PLL can lock. This bit is used to verify or calibrate the settings of the PLL range field of the control register. The ECC location flag bit of the status register, described above, indicates the location of an uncorrectable ECC error of a correctable ECC error. If the bit is set, the error was located in the DRAM memory, if the bit is clear, the error was located in the SRAM cache memorv. The dirty flag bit of the status register, described above, exhibits the dirty bit read from cache memory that results in an uncorrectable ECC error or correctable ECC error. The value is undefined if the currently reported ECC error was read from DRAM memory. The ECC syndrome field of the status register, described above, exhibits the syndrome of an uncorrectable ECC error or correctable ECC error. A 12-bit field is reserved for this purpose; the current implementation uses eight bits of the field. The values in this field are implementation-dependent. ECC syndrome values representing single-bit errors for MicroUnity ' s first implementation are detailed by the following table. Entries of * are not covered by the ECC code; syndrome values not shown in this table are uncorrectable errors involving two or more bits. The raw 0 and raw 1 fields of the status register contain the values obtained from two adjacent samples of the Hermes input channel. The raw 0 field contains a value obtained when the input clock was zero (0), and the raw 1 field contains the value obtained on the immediately following sample, when the input clock was (1). Mnemosyne must ensure that reading the status register produces two adjacent samples, regardless of the timing of the status register read operation on Cerberus. These fields are read for purposes of testing and control of skew in the Hermes channel. ECC Address Register The ECC addr register indicates the address at which an uncorrectable ECC error or correctable ECC error has occurred. Bits 63..2P+E of the ECC addr register are reserved; they read as 0. If the ECC location flag bit of the status register is zero, the ECC addr register contains the cache address in bits C- 1..0, and the uncorrected cache tag in bits 2P+E-1..C. ^AM Address appin g Mnemosyne may interleave up to 2* DRAM accesses in order to provide for continuous access of the DRAM memory system at the maximum bandwidth of the DRAM data pins. At any point in time, while some memory devices are engaged in row precharge, others may be driving or receiving data, and others may be receiving row or column addresses. In order to maximize the utility of this interleaving, the logical memory address bits which select the DRAM bank are the least-significant bits. A logical memory address determines which bank of DRAM is accessed, the row and column of such an access, and which interleave set is accessed. The diagram below shows the ordering of such fields in a general DRAM configuration: the bit addresses and field sizes shown are for a four-byte logical memory address and a two-way interleaved configuration of lM-word DRAM devices. 31 22 21 20 1 1 10 1 0 I 0 |sel| row | col int 7 1 10 10 1 An access request which is decoded to contain the same values in the select, row, and int fields as a currently active request is queued until the completion of the active request, at which time the second request may be handled using a page mode access. This mechanism helps to maintain high bandwidth access even when the requests may not be perfectly interleaved, and provides for lower latency access in the event that the address stream is sufficiently local to take advantage of page mode access. Mnemosyne devices may be cascaded for additional capacity, using the ma field in the packet formats. The memory controller must make the mapping between a contiguous address space and each of the separate address spaces made available within each Mnemosyne device. For maximum performance, the memory controller should also interleave such address spaces so that references to adjacent addresses are handled by different devices. DRAM i ing Control An internal state machine uses configurable settings to generate event timing, to accommodate DRAM performance variations. The timing of DRAM read cycles to a single DRAM bank is shown below: The timing of DRAM write cycles to a single DRAM bank is shown below: The timing of a read cycle followed by a write cycle to a single DRAM bank is shown below: The timinε of a refresh cvcle to a single DRAM bank is shown below: DRAM refresh cycle The time intervals shown in the figures above control the following events: Additional DRAM operations may be requested before the corresponding DRAM bank is available, and are placed in a queue until they can be processed. Mnemosyne will queue DRAM writes with lower priority than DRAM reads, unless an attempt is made to read an address that is queued for a write operation. In such a case, DRAM writes are processed until the matching address is written. Mnemosyne may make an implementation-dependent pessimistic guess that such a conflict occurs, using a subset of the DRAM address to detect conflicts. The number of DRAM writes which are queued is implementation-dependent. Mnemosyne uses one address bus for each interleave because dynamic power and noise is reduced by dividing the capacitance load of the DRAM address pins into four parts and only driving one-fourth of the load at a time. A timer (tlO) prevents two address transitions from occurring too close together, to prevent power and noise on each address bus from having an additive effect. In addition, the loading of the already divided RAS, CAS, and WE signals is closer to the loading on the A signal when the address bus is also divided, reducing effects of capacitance loading on signal skew. Power Swing. Skew and Slew Ca'pnavcn Mnemosyne uses a set of configuration registers to control the power and voltage levels used for internal high-bandwidth logic and SRAM memory, to control skew- in the output byte-channel, and to control slew rates in the TTL output circuits of the DRAM interface. The details of programming these registers are described below. Eight-bit fields separately control the power and voltage levels used in a portion of the Mnemosyne circuitry. Each such field contains configuration data in the following format: The range of valid values and the interpretation of the fields is given by the following table: Power an swing control field interpretation Values and interpretations of the Ivl field are given by the following table: Voltage swing level control field interpretation Values and interpretations of the res field are given by the following table: load value control field interpretation When Mnemosyne is reset, a default value of 0 is loaded into each ov field, xxx in each cur field and xxx in each res field. The digital skew fields set the number of delay stages inserted in the output path of the HoC and the Ho7..0 high-bandwidth output channel signals. Setting these fields, as well as the corresponding analog skew fields, permits a fine level of control over the relative skew between output channel signals. Nominal values for the output delay for various values of the digital skew and analog skew fields are given below: When Mnemosyne is reset, a default value of 0 is loaded into the digital skew fields, setting a minimum output delay for the HoC and Ho7..0 signals. " ,9 \X'e need to get the right values for the analog skew setting to get these nominal values. The output slope fields of the control register set the slew rate for the TTL outputs used for DRAM control, address and data signals, according to the following table: SRAM Redundancy Mapping Mnemosyne uses a configurable set of redundant physical memory blocks to enhance the manufacturability of the cache memory. A systematic method for determining the proper configuration is described below. To help clarify the following description, the figure belo shows the logical arrangement of the physical memory blocks in the SRAM cache of MicroUnity's first Mnemosyne implementation. There are 40 physical memory blocks, each containing 2048 x 9 bits of data. The 40 blocks are divided into 4 banks of 10 blocks each. The 40 blocks are also divided into 2 partitions oi 20 blocks each, and for each partition, there are two redundant memory blocks which can be configured to substitute for any of the 20 blocks in that partition. The 40 blocks are also divided up into 5 ranks, containing 8 blocks each, where each rank contains a distinct portion of a cache line. A cache line contains eight bytes of data, a 13 -bit tag, a dirtv bit, four unused bits, and an 8-bit ECC field. Each redundant x field, where x is in the range 0..D*R-1, controls the enabling and mapping address for a single redundant block. Starting at Cerberus address 32 and bits 63..56, each successive byte controls a redundant block, covering each redundant blocks in partition 0, and then in successive bytes, blocks for additional partitions. In other words, the redundant x field is located at Cerberus address 32+ b, bits 63 -(x mod 8)..56-(x mod 8), and specifies the redundant mapping for block (x mod R), of redundant partition is". The format of each redundant x field is detailed in the following figure, with bit field sizes shown for MicroUnity ' s first implementation: redundant block controls The range of valid values and the interpretation of the fields is given by the following table: urrent and voltage control field interpretation Redundancy is configured by first testing the SRAM cache with the isolate/synch bit if the control register set and all redundant x fields set to zero, and then again with each redundant x field set to 128÷(x mod R). The result of the testing should indicate the location of all failures in the primary physical memory blocks and the redundant blocks. Then, each of the failed primary blocks is replaced with a working redundant block by setting the redundant x fields as required. In order to map the address and bit identities of failures to physical block failures, the internal arrangement of bits and fields into blocks must be elaborated. First, a Mnemosyne memory address is divided into four parts according to the following figure, with bit field sizes shown for MicroUnity's first implementation: The interpretation of the fields is given by the following table: nemosyne cache aαdress field interpretation For each cache address and cache bank, a "hne" of information, containing a cache tag. the cache data, and a dirty bit is stored. The internal arrangement of these fields is as shown in the following figure, with bit field sizes shown for MicroUnity ' s first implementation: The interpretation of the fields is given by the following table: Mnemosyne cache line field interpretation From the tables above, for each failure identified in the cache SRAM, a physical memory bank number, ba, can be identified from the Mnemosyne address, and a bit position, bi, can be identified from the Mnemosyne cache line layout. The bit position specifies a physical memory partition number, pa, according to the following formula: ,bi mod s "' D pa = The bit position also identifies a physical memory block rank, ra, according to the following formula: ra = s O So, to correct a failure in the cache SRAM, one of the working redundant blocks in the partition pa must be configured by setting a redundant x field, where x is in the range pa*D+D-l..pa*D, to the value: Multiple Memerv Chips Up to four Mnemosyne memory devices may be cascaded to form effectively larger memories. The cascade of memory devices will have the same bandwidth as a single memory chip, but more latency. cascade of four memory devices Packets are explicitly addressed to a particular Mnemosyne device; any packet received on a device ' s input channel which specifies another module address is automatically passed on via its output channel. This mechanism provides for the serial interconnection of Mnemosyne devices into strings, which function identically to a single Mnemosyne, except that a Mnemosyne string has larger memory capacity and longer response latency. All devices in a cascade must have the same values for A and W parameters, in order that each part may properly interpret packet boundaries. Response Packet Timing In general, a received packet which is interpreted as a command causes a response packet to be generated. The latency between the end of the request packet and the beginning of the response packet is affected by the processing and forwarding of other packets, by the presence or absence of the requested word in the cache, by the setting of the SRAM and DRAM timing generators, by the presence of queued DRAM write and read requests, as well as other non- configurable and implementation-dependent device parameters. With full knowledge of the cache state, configurable parameters and implementation-dependent characteristics, a memory controller may completely model the latency of responses. However, dependence on such characteristics is not recommended, except for testing and characterization purposes. SRAM accesses, DRAM accesses, and forwarded packets typically have differing latency before a response or forwarded packet is generated at the Hermes output channel, so that certain combinations would imply that two output packets would need to overlap. In such a case, Mnemosyne will buffer the later output packet until such time as it can be transmitted. However, the number of requests that can be buffered is stricdy limited to eight (the number of identification numbers) per Mnemosyne device. It is the responsibility of the issuer of command packets to ensure the number of outstanding packets never exceeds the limits of the buffer. Mnemosyne may use non-fair scheduling for forwarded packets to avoid buffer overflow conditions. The use of DRAM page mode accesses and interleaving requires knowledge of the relationship between a pair of transactions. Therefore, additional DRAM requests per interleave level may be transmitted before the time at which the DRAM controller may perform the request. These additional requests are queued and the corresponding response packet is generated at a time controlled bv t he DRAM t i m i ng genera t or. DRAM interleaves are serviced in an implementa t ion- dependent fashion to ensure starvation-free scheduling. Persephone PCI Adaptation MicroUnity ' s Persephone 50 PCI adaptation architecture is designed to enable Terpsichore systems to employ interface cards that conform to the PC - (Peripheral Component Interconnect) standard. 50 lpur*sef'-uh-neel In Greek mythology. Persephone '.also called Kore) was the beautiful daughter of Zeus and Demeter who represented both nature ' s growth cycle and death. Hades, god of the underworld and brother of Zeus, was lonely in his underworld kingdom: therefore Zeus, without consulting Demeter. told him to take Persephone as his wife. Thus, as Persephone was picking flowers one day, Hades came out of the earth and carried her off to be his queen. While the grieving Demeter. goddess of grain, searched for her daughter, the earth became a barren wasteland. Zeus finally obtained Persephone's release, but because she had eaten a pomegranate seed in the underworld, she was oblieed to spend four months (winter) of each year there, during which time barrenness returned to the earth. 5 -PCI standard, version 2.0. Calliope Interface Portions of this section has been temporarily removed to a separate document: "Calliope Interface Architecture. " though it is still a mandatory area of the Terpsichore System Architecture. MicroUnity ' s Calliope interface architecture is designed for ultra-high bandwidth systems. The architecture integrates fast communication channels with SRAM buffer memory and interfaces to standard analog channels. The Calliope interfaces include byte-wide input and output channels intended to operate at rates of at least 1 GHz. These channels provide a packet communication link to synchronous SRAM memory on chip and a controller for interfaces to analog channels. Calliope provides analog interfaces for MicroUnity ' s Terpsichore system architecture. However, Calliope is useful in many interface applications. Calliope ' s interface protocol embeds read and write operations to a single memory space into packets containing command, address, data, and acknowledgement. The packets include check codes that will detect single-bit transmission errors and multiple-bit errors with high probability. As many as eight operations in each device may be in progress at a time. As many as four Calliope devices may be cascaded to expand the buffer and analog interfaces. Architecture Framework The Calliope architecture builds upon MicroUnity's Hermes high-bandwidth channel architecture and upon MicroUnity's Cerberus serial bus architecture, and complies with the requirements of Hermes and Cerberus. Calliope uses parameters A and W as defined by Hermes. O 7/ The Calliope architecture defines a compatible framework for a family of implementations with a range of capabilities. The following implementation- defined parameters are used in the rest of the document in boldface. The value indicated is for MicroUnity ' s first Calliope implementation. Interfaces and Block Diagram Calliope uses two Hermes unidirectional, byte-wide, differential, packet-oriented data channels for its main, high-bandwidth interface between a memory control unit and Calliope ' s memory. This interface is designed to be cascadeable, with the output of a Calliope chip connected to the input of another, to expand the interface resources that can be reached via a single set of data channels. An external memory control unit is in complete control of the selection and timing of operations within Calliope and in complete control of the timing and content of information on the high-bandwidth interfaces. A Cerberus bit-serial interface provides access to configuration, diagnostic and tester information, using TTL signal levels at a moderate data rate. Nearly all Calliope circuits use a single power supply voltage, nominally at 3.3 Volts (5% tolerance). A second voltage of 5.0 Volts (5% tolerance) is used only for TTL interface circuits. Power dissipation is TBD. Initial packaging is TAB (Tape Automated Bonding). Pin assignments are to be defined: there are 174 signal pins and 466 pins for 3.3V power, 5.0V power and substrate, for a total of 640 pins. The following is a diagram of the Calliope device interfaces: (Numerical values are shown for MicroUnity's first implementation.) '^Internal circuit documentation names this si-tnal VDDO. Calliope defines two regions: a memory region, implemented by an on-device static RAλl memory along with high-bandwidth control registers and a configuration region, implemented by on-device read-only and read/write registers. These regions are accessed by separate interfaces; the Hermes channel used to access the memory region, and the Cerberus serial interface used to access the configuration region. These regions are kept logically separate. The Calliope logical memory region is an array of 2 8A words of size W bytes. Each memory access, either a read or write, references all bytes of a single block. All addresses are block addresses, referencing the entire block. 28A-1 r 8W Logical memory organization Calliope ' s SRAM memory is a buffer for data which flows to or from interface devices. Calliope's configuration region consists of read-only and read/ write registers. The size of a logical block in the configuration memory space is eight bytes: one octlet. Communications Channels Hich- bandwidth Calliope uses the Hermes high-bandwidth channel and protocols, implementing a slave device. Calliope operates two Hermes high-bandwidth communications channels, one input channel and one output channel. Calliope uses the Hermes packet structure. There is no structure corresponding to the Hermes-designated cache, so the no-allocate attribute of read and write operations has no effect.. Configuration-region registers provide a low-level mechanism to detect skew in the byte-wide input channel, and to adjust skew in the byte-wide output channel. This mechanism may be employed by software to adaptively adjust for skew in the channels, or set to fixed patterns to account for fixed signal skew as may arise in device-to-device wiring. Serial A Cerberus serial bus interface is used to configure the Calliope device, set diagnostic modes and read diagnostic information, and to enable the use of the part within a high-speed tester. The serial port uses the Cerberus serial bus interface. Error Handling Calliope performs error handling compliant with Hermes architecture. For the current implementation, the following errors are designed to be detected and known not detected by design: Upon receipt of the error response packet, the packet originator must read the status register of the reporting device to determine the precise nature of the error. Calliope devices reporting an invalid packet will suppress the receipt of additional packets until the error is cleared, by clearing the status register. However, such devices may continue to process packets which have already been received, and generate responses. Upon taking appropriate corrective actions and clearing the error, the packet originator should then re-send any unacknowledged commands. Because of the large difference in clock rate between the high-bandwidth Hermes channel and the Cerberus serial bus interface. it is generally safe to assume that, after detecting an error response packet, an attempt to read the status register v Cerberus will result in reading stable, quiescent error conditions and that the queue of outstanding requests will have drained. After clearing the status register via Cerberus, the packet originator may immediately resume sending requests to the Calliope device. Cerberus Registers Calliope ' s configuration registers comply with the Cerberus and Hermes specifications. Cerberus registers are internal read/only and read/write registers which provide an implementation-independent mechanism to query and control the configuration of devices in a Terpsichore system. By the use of these registers, a user of a Terpsichore system may tailor the use of the facilities in a general- purpose implementation for maximum performance and utility. Conversely, a supplier of a Terpsichore system component may modify facilities in the device without compromising compatibility with earlier implementations. These registers are accessed via the Cerberus serial bus. As a device component of a Terpsichore system, each Calliope interface contains a set of Cerberus-accessable configuration registers. Additional sets of configuration registers are present for each device in a Terpsichore system, including Euterpe processor devices, and Mnemosyne memory devices. Read/only registers supply information about the Terpsichore system implementation in a standard, implementation-independent fashion. Terpsichore software may take advantage of this information, either to verify that a compatible implementation of Calliope is installed, or to tailor the use of the part to conform to the characteristics of the implementation. The read/only registers occupy addresses 0..5. An attempt to write these registers may cause a normal or an error response. Read/write registers select operating modes and select power and voltage levels for gates and signals. The read/wrire registers occupy addresses 6..7, 10..14 and 25..32. Reserved registers in the range 8..9, 15..24 and 33..63 must appear to be read/only registers with a zero value. An attempt to write these registers may cause a normal or an error response. Reserved registers in the range 64..2 16 -1 may be implemented either as read/only registers with a zero value, or as addresses which cause an error response if reads or writes are attempted. The format of the registers is described in the table below. The octlet is the Cerberus address of the register; bits indicate the posifion of the field in a register. The value indicated is the hard-wired value in the register for a read/only register, and is the value to which the register is initialized upon a reset for a read/write register. If a reset does not initialize the field to a value, or if initialization is not required by this specification, a " ' is placed in or appended to the value field. The range is the set of legal values to which a read/write register may be set. The interpretation is a brief description of the meaning or utility of the register field: a more comprehensive description follows this table. octlet bits field name value ranσe interoretation 0 63..16 15..0 octlet bits field name value ranσe interoret tion 1 63..16 15..0 octlet 2 octlet bits field name value ranαe mterDretation 3 63..16 15..0 octlet bits field name value raπce interoretation 4 63 60 59 56 55 48 47 0 octlet 5 octlet 6 ϋctiet octlet 8 9 octlet 1 1 octlet 1 2 octlet bits field ame value -anoe ιnte r ore f atιon 13 63 62 56 oo 54 53 52 51 50 51 48 47 40 3932 31 26 25 24 23 16 15 13 12 11 8 7 4 3 0 octlet 14 octlet bits field name value r a n e interoretation 15 24 63 .0 Wo P Reserved for expansion of Ceroerus registers upward or knobcity registers downward 55..48 47 .40 39..32 31 ..24 23..16 15..8 7..0 xeld name vai-e mtercetation 22< lαeoαraohica diαital knob settinαs 22 αeoαraohica diαital knob settinαs 2 loeoαraDhica digital knob settings !224 Igeograohica diαital knob settinαs I224 αeoαraohica diαital knob settinαs 224 lαeoαraDhica digital knob settings 224 geographica digital knob settings 224 αeoαraDhica digital knob settings field name vaiu nteroretation J224 igeograohica digital knob settings I224 P (geographica digital knob settings 22' geographica digital knob settings I224 P geographica digital knob settings I224 igeographica digital knob settings I224 ~ Igeograohica digital knob settings 224 geographica digital knob settings I224 geographica digital knob settings octlet field name val'. mterDretation 29 224 geographica digital knob settings 224 ' - geographical digital knob settings I224 geographica digital knob settings 224 p- ' 27 geographica digital knob settings ,224 • ?7 geographical digital knob settings I224 P ' 7 geographica digital knob settings I224 p -2- geographica digital knob settings 224 P ' 2? geographica digital knob settings octlet bits field name value ra oe terDretation 29 63..56 55..48 47..40 39..32 31..24 23..16 15..8 7..0 field name value ra^ s mtercretation Hermes 0 0..3 Voltage swing selection for Hermes skew swing channel skew circuits 0 0 Reserved resg 0..7 Global resistor mask for all knobs. K) 0 Reserved termination 20 0..31 . Set based on value read from PMOS ; fine-tuning drive strength, used to fine-tune resistor values in Hermes termination. ' 47 .45 0 0 Reserved 44 40 process 20 0..31 Set based on value read from PMOS control dπve strength, used to fine-tune resistor values in knob settings. 39..37 0 0 Reserved 36..32 PMOS drive 0..31 This read/only field indicates the strength ' drive strength of PMOS devices expressed as a digital binary value. 31 .28 swing 3 15 ■O.J 5 Voltage swing knob setting 3 27..24 swing 2 15 0.J 5. Voltage swing knob setting 2 23..20 swing 1 15 IO.J5λ oltage swing knob setting 1 19..16 swing O 15 ■ O.JS'Voltage swing knob setting 0 15..2 reference 3 15 iO.JδiVoltage reference knob setting 3 1 1 ..8 reference 2 15 IP. J 5 'Voltage reference knob setting 2 7..4 reference 1 15 IO.J5iVoltage reference knob setting 1 3..0 reference O 15 'O.JSiVoltage reference knob setting 0 o octlet bits field name value ranee mterDretation 32 63 P I0 Reserved 62 quadrature P' .J Setting this bit causes the bypass quadrature circuit to be bypassed, the input clock signal is used directly. 61 quadrature P' P.J Set to 0 if the Hermes channel is range operating at a low frequency; 1 if the Hermes channel is operating at a high frequency. 60 output P.J Set to enable output terminators. termination Cleared to disable output terminators. 59 .57 termination P..7 Set termination resistance level resistance 56..54 output P..7 Set output current level current 53. 48 skew bit 7 P..63 Set delay in Ho7 skew circuit. 47..42 skew bit 6 P..63 Set delay in Ho6 skew circuit. 41 ..36 skew bit 5 P..63 Set delay in Ho5 skew circuit. 35..30 skew bit 4 P..63 Set delay in Ho4 skew circuit. 29..24 skew bit 3 P..63 Set delay in Ho3 skew circuit- 23..18 skew bit 2 P..63 Set delay in Ho2 skew circuit. 17..12 skew bit 1 P..63 Set delay in Ho1 skew circuit. 1 1 ..6 skew bit O P..63 Set delay in HoO skew circuit- 5..0 skew elk P..63 Set delay in HoC skew circuit. octlet bits fi l n m v l r n interoretation 33 .63 63..0 Iderτ cavon Registers The identification registers in octlets 0..3 comply with the requirements of the Cerberus architecture. MicroUnity's company identifier is: 00C0 0000 0000 0010 1100 0101. MicroUnity ' s architecture code for Calliope is specified by the following table: Calliope architecture revisions are specified by the following table: MicroUnity's Calliope implementor codes are specified by the following table: MicroUnity's Calliope, as implemented by MicroUnity, uses implementation codes as specified by the following table: MicroUnity's Calliope, as implemented by MicroUnity, uses manufacturer codes as specified by the following table: MicroUnity's Calliope, as implemented by MicroUnity, and manufactured by MicroUnity, uses manufacturer revisions as specified by the following table: The architecture description registers in octlets 4 and 5 comply with the Cerberus specification and contain a machine-readable version of the architecture parameters: A, W, C, AI, AO, PO, PI, VI, VO, IR. II. SO, SI, EQ, CI, CO, and QPSK described in this document. The architecture parameters describe characteristics of the Hermes interface, capacity of the Calliope buffer memory, and the number of audio, phone, video, infrared, smartcard, and cable input and output channels, and the number of QPSK cable input channels. Cc trol Register The control register in octlet 6 is a 64-bit register with both read and write access. ly by Cerberus accesses; Calliope does not alter the values written The reset bit of the control register complies with the Cerberus specification and provides the ability to reset an individual Calliope device in a system. Writing a one (1 ) to this bit is equivalent to a power-on reset or a broadcast Cerberus reset (low level on SD for 33 cycles) and resets configuration registers to their power-on values, which is an operating state that consumes nominal current (as determined by external pins), and also causes all internal high-bandwidth logic to be reset. The duration of the reset is sufficient for the operating state changes to have taken effect. At the completion of the reset operation, the reset/clear/selftest complete bit of the status register is set, the reset/clear/selftest status bit of the status register is set, and the reset bit of the control register is set. The clear bit of the control register complies with the Cerberus specification and provides the ability to clear the logic of an individual Calliope device in a system. Writing a one (1) to this bit causes all internal high-bandwidth logic to be reset, as is required after reconfiguring power and swing levels. The duration of the reset is sufficient for any operating state changes to have taken effect. At the completion of the reset operation, the reset/clear/selftest complete bit of the status register is set, the reset/clear/selftest status bit of the status register is set, and the clear bit of the control register is set. The selftest bit of the control register complies with the Cerberus specification and provides the ability to invoke a selftest on an individual Terpsichore device in a system. However, Calliope does not define a selftest mechanism at this time, so setting this bit will immediately set the reset/clear/selftest complete bit and the reset/clear/selftest status bit of the status register. The defer writes bit of the control register provides a mechanism to adjust several octlets of Cerberus registers at one time with a single transition, such as when setting individual power levels within Calliope. Writing a one (1) to this bit causes writes to octlets 10 through 32 to have no effect (to be deferred) until the next logic-clear or a non-deferred write. When writes have been deferred, the values written are lost if a read of these octlets precedes the subsequent logic-clear or non-deferred write. A normal or non-deferred write occurs when writing to octlets 10 through 32 while the defer writes bit is cleared (0). The module id-field of the control register controls the value of the module identifier field of the Hermes input channel which selects this Calliope device. The Hermes channel disable bit of the control register provides the means to begin operations on the Hermes channels after a reset, clear, or error. Writing a one ( 1 ) to this bit causes the Hermes input channel to be ignored and forces idles to be generated on the Hermes output channel. Writing a zero (0) to this bit causes the Hermes input channel phase adjustment to be reset, and after a suitable delay the Hermes channels are available for use. The cidle 0 and cidle 1 fields of the control register provide a mechanism to repeatedly sent simple patterns on the Hermes output channel for purposes of testing and skew adjustment. For normal operation, the cidle 0 field must be set to zero (0 ) , and the cidle 1 field must be set to all ones (255). Status Register The status register is a 64-bit register with both read and write access, though the only legal value which may be written is a zero, to clear the register. The result of writing a non-zero value is not specified. The reset/clear/selftest complete bit of the status register complies with the Cerberus specification and is set upon the completion of a reset, clear or selftest operation as described above. The reset/clear/selftest status bit of the status register complies with the Cerberus specification and is set upon the successful completion of a reset, clear or selftest operation as described above. The meltdown detected bit of the status register is set when the meltdown detector has discovered an on-chip temperature above the threshold set by the meltdown threshold field of the Cerberus configuration register, which causes a reset to occur and the power level to be forced to minimum (1). The low voltage or temperature bit of the status register is set when internal circuits have detected either insufficient voltage or temperature for proper operation of high speed logic circuits, which causes a logic clear until the condition is no longer detected (due to an increase in supply voltage or device temperature). The Cerberus transaction error bit of the status register is set when a Cerberus transaction error (bus timeout, invalid transaction code, invalid address) has occurred. Note that Cerberus aborts, including locally detected parity errors, should cause bus retries, not a machine check. The Hermes check byte error bit of the status register is set when a Hermes check bvte error has occurred. The Hermes command error bit ot the status register is set when a Hermes command error has occurred. The Hermes address error bit of the status register is set when a Hermes address error has occurred. The raw 0 and raw 1 fields of the status register contain the values obtained from two adjacent samples of the specified Hermes input channel. The raw 0 field contains a value obtained when the input clock was zero (0), and the raw 1 field contains the value obtained on the immediately following sample, when the input clock was (1). Calliope ensures that reading the status register produces two adjacent samples, regardless of the timing of the status register read operation on Cerberus. These fields are read for purposes of testing and control of skew in the Hermes channel interfaces. Power and Swing Calibratio n eαist&rs Calliope uses a set of calibration registers to control the power and voltage levels used for internal high-bandwidth logic and memory. The details of programming these registers are described below. Eight-bit fields separately control the power and voltage levels used in a portion of the Calliope circuitry. Each such field used to control digital circuitry (labeled "knob") contains configuration data in the following format: Each such field used to control analog circuitry (labeled "anob") contains configuration data in the following format: 5 4 3 2 1 0 res I ivl I o I Power and swing control field interpretation The reference voltage level, voltage swing level and resistor load value are model figures for a full-swing, lowest-power logic gate output. The actual voltage levels and resistor load values used in various circuits is geometrically related to the values in the tables below. Designed typical, full-speed settings for the ref. Ivl and res fields are ref=250 millivolts. lvl=500 millivolts, and res=2.5 kilohms. The ref field, together with the reference n fields of the configuration register, control the reference voltage level used for logic circuits in the specified knob domain. The value of the ref field is interpreted by the following table: The Ivl field, together with the swing n fields of the configuration register, control the voltage swing level used for logic circuits in the specified knob domain. The value of the Ivl field is interpreted by the following table: Values and interpretations of the swing n and reference n fields are given by the following table, with units in millivolts: The res held, together with the resg field of the configuration register and the meltdown detected bit of the status register, control the PMOS load resistance value used for logic circuits in the specified knob domain, referred here as the resl value. For each res field, the resl value is computed as: resl = res & (meltdown detected 1 resg) The resl value, together with the process control field of the configuration register. control the PMOS load resistance value used for logic circuits in the specified knob domain. Values and interpretations of the Ivl field are given by the following table, with units in kilohms. The table below gives resistance values with nominal process parameters. Resistor control field interpretation When the process control field of the configuration register is set equal to the PMOS drive strength field of the configuration register, nominal PMOS load resistance values are as given by the following table, with units in kilohms. When Mnemosyne is reset, a default value of 0 is loaded into each 0 field, 0 in each ref field, 0 in each Ivl field and 7 in each res field, which is a byte value of 224. The process control field of the configuration register is set to 20, and the reference n and swing n fields are set to 15. These settings correspond to a chip with nominal processing parameters, nominal power and high voltage swing operation. For nominal operating conditions, the ref field is set to 0, the Ivl field is set to 0, and the res field is set to 5, which is byte value of 5. The process control field is set equal to the PMOS strength eld, and the reference n and swing n fields are set to 5. intenace Conr.ouravcn ^eos ^s Interface configuration registers are provided on the Calliope interface to control the [insert summary list of controls]. The CI1 test and CI2 test field of interface configuration register 10 control operating modes of the CIl and CI2 cable input blocks. Eight-bit fields separately control the operating modes of the cable input blocks. Each such field contains configuration data in the following format: cable inDut test controls The range of valid values and the interpretation of the fields is given by the following table: Cable input test control field interpretation The CI1Q filter, CHI filter, CI2Q filter and CI2I filter fields of interface configuration register 10 and 11 control the cutoff frequency of the cable input antialias filters. Four-bit fields separately control the cutoff frequency of each cable input antialias filter. Each such field contains configuration data in the following format: [ I cutoff ] cable input antialias filter controls The range of valid values and the interpretation of the fields is given by the following table: Cable input antialias filter control field interpretation Values and interpretations of the cutoff fields are given by the following table, with units in megahertz, for nominal 3 dB frequency at specified junction temperature: For normal operation a value of 3 is placed in the cutoff fields, selecting a 9 MHz cutoff frequency. The CI1 VCO and CI2 VCO bits of interface configuration registers 10 and 11 control the selection of the VCO used as an input to the tuner of the cable input. Writing a zero (0) to the bit selects the internal VCO, while writing a one ( 1 ) selects an external VCO input. In normal operation a zero is placed in the VCO bit, selecting the internal VCO. The CI1 LNA and CI2 LNA bits of interface configuration registers 10 and 11 enable the LNA (low noise amplifier) used as an input to the tuner of the cable input. Writing a zero (0) to the bit disables the LNA, while writing a one ( 1 ) enables the LNA. In normal operation a one is placed in the LNA bit, enabling the LNA. The CIIQ ADC preamp, CIII ADC preamp, CI2Q ADC preamp and CI2I ADC preamp bits of interface configuration registers 10 and 11 enable the ADC preamplfier output used as an input to the ADC of the cable input. Writing a zero (0) to the bit enables the ADC preamplifier output, while writing a one (1) disables it, allowing the tuner input to be driven from an external pin. In normal operation a zero is placed in the ADC preamp bits, enabling the preamplifiers. The Clla, Cllb, Cl2a, CI2b. COl, CO2, VI, VO, AI, AO, PI, PO invert bits of interface configuration registers 11, 12, and 13 provide for the selective inversion of the relative clock phase of the analog-to-digital section internal interfaces in the respective interfaces. In normal operation, a zero is placed in the invert bits, matching the relative phases of the interface sections The COl configuration and CO2 configuration fields of interface configuration registers 13 and 14 provide for the configuration of external devices which assist in the implementation of the cable output. The configuration fields drive LVTTL outputs which can control external filters and other components. In nornal operation, a zero is placed in the configuration fields. The PI bias, AIR bias and AIL bias fields of interface configuration register 13 control the bias current of the phone and audio input right and left operational amplifiers. Four-bit fields separately control the bias current of each input operational amplifier. Each such field contains configuration data in the following format: The range of valid values and the interpretation of the fields is given by the following table: audio input operational amplifier control field interpretation Values and interpretations of the bias fields are given by the following table, with units in microamperes, for nominal current at specified junction temperature: The mute bit of interface configuration register 13 provides for initial muting of the audio and phone outputs during initial system operation. Writing a zero (0) to the bit enables the audio and phone outputs, while writing a one (1) forces the AO and PO outputs to a constant value (zero with AC coupling). The PO filter, AOR filter and AOL filter fields of interface configuration register 13 control the cutoff frequency of the phone and audio output right and left antialias filters. Four-bit fields separately control the cutoff frequency of each output antialias filter. Each such field contains configuration data in the following format cutoff 1 cable incut antialias filter controls The range of valid values and the interpretation of the fields is given by the following table: audio output antialias filter control fieid interpretation Values and interpretations of the cutoff fields are given by the following table, with units in kilohertz, for nominal 3 dB frequency at specified junction temperature: The EQl test and EQ2 test field of interface configurarion register 14 control operating modes of the EQl and EQ2 cable input equalizers. Eight-bit fields separately control the operating modes of the cable input equalizers. Each such field contains configuration data in the following format: 7 3 2 1 0 1 cable incut eαualizer test controls The range of valid values and the interpretation of the fields is given by the following table: Cable input equalizer test control field interpretation Configuration Register A Configuration register is provided on the Calliope interface to control the fine- tuning of the Hermes channel configuration, to control the global process parameter settings, to control the two phase-locked loop frequency generators, and to control the temperature sensors and read temperature values. The Hermes skew swing field ot the configuration register control the voltage swing used in the Hermes channel skew circuits The held should alwavs be set equal to the value of the Ivl subfield of the Hermes channel knob field The resg held of the configuration register permits the global control of the load resistors in all of Calliope ' s high-speed logic circuits The resg field is initially loaded from external pins to a numinal power level (5 ). and can be changed again to a value in the range 0 .7 to lower or raise the power and speed of the high-speed logic circuits in the Calliope device, or can be set to all ones (7) to enable control of individual sections of the Calliope device power levels By altering the value on the external pins, Calliope can be configured for low-power (0 or 1 ) testing in a restricted packaging environment The termination fine-tuning field of the configuration register controls the analog bias settings for PMOS loads in Hermes termination circuits, in order to accomodate variations in circuit parameters due to the manufacturing process, and to provide intermediate termination resistance levels. Under normal operating conditions, the value read from the PMOS drive strength field should be written into the termination fine-tuning field. The interpretation of the field is given by the table: The process control field of the configuration register controls the analog bias settings for PMOS loads in internal logic circuits, in order to accomodate variations in circuit parameters due to the manufacturing process. Under normal operating conditions, the value read from the PMOS drive strength field should be written into the process control field. The interpretation of the field is given by the table: The PMOS drive strength field of the configuration register is a read/only field that indicates the drive strength, or conductance gain, of PMOS devices on the Terpsichore chip, expressed as a digital binary value. This field is used to calibrate the power and voltage level configuration, given variations in process characteristics of individual devices. The interpretation of the field is given by the table: There are two identical phase locked-loop (PLL) frequency generators, designated PLLO and PLLl. These PLLs generate internal and external clock signals of configurable frequency, based upon an input clock reference of either 54 MHz or 1.08 GHz. PLLO controls the internal operating frequency of the Terpsichore processor, while PLLl controls the operating frequency of the Hermes channel interfaces. The configuration fields for PLLO and PLLl have identical meanings, described below: The PLLO divide ratio and PLLl divide ratio fields select the divider ratio for each PLL, where legal values are in the range 6..21, with a nominal setting of 12 for PLLO, and 20 for PLLl. These divider ratios permit clock signals to be generated in the range from 324 MHz to 1J34 GHz, when the input clock reference is at 54 MHz, with prescaling bypassed, or at 1.08 GHz with prescaling used. Setting the PLLO feedback bypass bit or the PLLl feedback bypass bit of the configuration register causes the generated clock bypass the PLL oscillator and to operate off the input clock directly. Setting these bits causes the frequency generated to be the optionally prescaled reference clock. These bits are cleared during normal operation, and set by a reset. The PLLO range field and the PLLl range field of the configuration register are used to select an operating range for the internal PLLs. If the PLL range is set to zero, the PLL will operate at a low frequency (below O.xxx GHz ), if the PLL range is set to one, the PLL will operate at a high frequency (above O.xxx GHz). At reset this bit is cleared, as the input clock frequency is unknown. Setting the PLL prescaler bypass bit of the configurarion register causes the phase-locked loops PLLO and PLLl to use the input clock directly as a reference clock. This bit is cleared during normal operation with a 1.08 GHz input clock, in which the input clock is divided by 20, and is set during normal operation with a 54 MHz input clock. At reset this bit is cleared, as the input clock frequency is unknown. Setting the conversion prescaler bypass bit of the configuration register causes the temperature conversion unit to use the input clock directly as a reference clock. Otherwise, clearing this bit causes the input clock to be divided by 20 before use as a reference clock. The reference clock frequency of the temperature conversion unit is nominally 54 MHz. and in normal operation, this bit should be set or cleared, depending on the input clock frequencv At reset this bit is cleared, as the input clock frequency is unknown The meltdown margin field controls the setting of the threshold at which meltdown is signalled. This field is used to test the meldown prevention logic. The interpretation of the field is given by the table below with a tolerance of ~β degrees C, and 5 degrees C hysteresis. The conversion start bit controls the initiation of the conversion of a temperature sensor or reference to a digital value Setting this bit causes the conversion to begin, and the bit remains set until conversion is complete, at which time the bit is cleared. The conversion selection field controls which sensor or reference value is converted to a digital value. The interpretation of the field is given by the table below: The conversion counter field is set to the two's complement of the downslope count. The counter counts upward to zero, at which point the upslope ramp begins, and continues counting on the upslope until the conversion completes. Hermes channel Confiouratign Registers Configuration registers are provided on the Calliope interface to control the timing, current levels, and termination resistance for the Hermes channel high- bandwidth channel. A configuration register at ocdet 31 is dedicated to the control of the Hermes channel, and additional information in the configuration register at ocdet 31 controls aspects of the Hermes channel circuits in common. The Hermes channel configuration registers are Cerberus registers 32, where 32 corresponds to Hermes channel 0. The quadrature bypass bit controls whether the HiC clock signal is delayed by approximately 7 of a HiC clock cycle to latch the Hiτ..o bits. In normal, full speed operation, this bit should be cleared to a zero value. If this bit is set, the quadrature delay is defeated and the HiC clock signal is used directly to latch the H17 0 bits. The quadrature range bit is used to select an operating range to the quadrature delay circuit. If the quadrature range is set to zero, the circuit will operate at a low frequency (below O.xxx GHz), if the quadrature range is set to one, the circuit wdl operate at a high frequency (above 0 xxx GHz) The output termination bit is used to select whether the output circuits are resistively terminated. If the bit is set to a zero, the output has high impedence. if the bit is set to one, the output is terminated with a resistance equal to the input termination. At reset, this bit is set to one, terminating the output. The termination resistance field is used to select the impedence at which the Hermes channel inputs, and optionally the Hermes channel outputs are terminated. The resistance level is controlled relative to the setting of the termination fine tuning field of the configuration register. The interpretation of the field is given by the table, with units in Ohms and nominal PMOS conductance and bias settings: The output current field is used to select the current at which the Hermes channel outputs are operated. The interpretation of the field is given by the table, with units in mA: The output voltage swing is the product of the composite termination resistance: (input termination resistance' ^output termination resistance" 1 )" 1 , and the output current. The output voltage swing should be set at or below 700 mV, and is normally set to the lowest value which permits a sufficiently low bit error rate, which depends upon the noise level in the system environment. The skew fields individually control the delay between the internal Hermes channel output clock and each of the HoC and Ho7..0 high bandwidth output channel signals. Each skew field contains two three-bit values, named digital skew and analog skew as shown below: 53 2 0 digital skew analog skew The digital skew fields set the number of delay stages inserted in the output path of the HoC and the Ho7..0 high-bandwidth output channel signals. The analog skew fields control the power level, and thereby control the switching delay, of a single delay stage. Setting these fields permits a fine level of control over the relative skew between output channel signals. Nominal values for the output delay for various values of the digital skew and analog skew fields are given below, assuming a nominal setting for the Hermes channel knob: When Calliope is reset, a default value of 0 is loaded into the digital skew and 1 is loaded into the analog skew fields, setting a minimum output delay for the HoC and Ho7..0 signals. Hermes High-Bandwidth Channel MicroUnity's Hermes high-bandwidth channel architecture is designed to provide ultra-high bandwidth communications between devices within MicroUnity ' s Terpsichore system architecture. Hermes-compliant devices include one or more byte-wide input and output channels intended to operate at rates of at least 1 GHz. These channels provide a packet communication link to general devices, processors, memories, and input- output interfaces. Hermes high-bandwidth channels employ nine signals, one clock signal and eight data signals, using differential low-voltage levels for direct communication from one device to another. The channels are designed to be arranged into a ring consisting of up to four target devices and one initiator. The channels may also be extended to permit multiple initiators in a single ring. The Hermes interface protocol embeds read and write operations to a single memory space into packets containing command, address, data, and acknowledgement. The packets include check codes that will detect single-bit transmission errors and multiple-bit errors with high probability. As many as eight operations in each device may be in progress at a time. As many as four Hermes devices may be cascaded to expand system capacity and bandwidth. Hermes relies upon MicroUnity's Cerberus serial bus to provide access to a low- level mechanism to detect skew in input channels, and to adjust skew in output channels. This mechanism may be employed by software to adaptively adjust for skew in the channels, or set to fixed patterns to account for fixed signal skew as may arise in device-to-device wiring. Architecture Framework The Hermes architecture defines a compatible framework for a family of implementations with a range of capabilities. The following implementation- defined parameters are used in the rest of the document in boldface. The value indicated are for MicroUnity's first implementations. Hermes devices have several optional capabilities, which are identified in the following table: Electrical Signalling Each Hermes channel consists of a one byte wide data path and a single-phase, constant-rate clock signal. Both the data and clock signals are differential-pair signals. The clock signal contains alternating zero and one values transmitted with the same timing as the data signals; thus, the clock signal frequency is one-half the channel byte data rate. Each channel runs at a constant frequency and contains no auxiliary control, handshaking, or flow-control information. The channel transmitter is responsible for transmitting all nine differential-pair signals so as to be received with minimal skew; the receiver is responsible for decoding the signals in the presence of noise and skew as may arise due to differences in the signal environment of the clock and of each data bit. A Hermes device may be capable of responding to Hermes request packets received on a Hermes input channel. Such a device is designated a slave device, and must operate the Hermes output channel at the same clock rate as the input channel. A slave device must generate no more than a specified amount of variation in the output clock phase, relative to the input clock, over changes in system temperature or operating voltage. A Hermes device that is capable of generating Hermes request packets is designated a master device. A master device must be capable of generating the constant-frequency clock signal on the Hermes output channel and accepting signals on the Hermes input channel at the same clock frequency as is generated. In addition, a master device must accept an arbitrary input clock phase, and must accept a specified amount of variation in clock phase, as may arise due to changes in system temperature or operating voltage. Each Hermes input or output channel requires IS pads and the associated Cerberus interface requires an additional 6 pads Each Hermes input channel is terminated at a nominal 50 ohm impedance to ground. Each Hermes output channel is optionallv terminated at the same impedance as the devices input channel An adjustable termination impedance. programmable via Cerberus is recommended In order to provide for planar connections without vias among Hermes devices when connected into rings, all devices must locate Hermes input channels and Hermes output channels to pm assignments which preserve the relative ordering of the conductors which connect the devices In general, the ordering must be consistent on circuit boards by which devices are interconnected The ordering fixes the order of Hermes pms encountered in a clockwise traversal of the pins to alwavs be HiC, HiC_N, HiO, Hi0_N, Hil. Hil.N. Hι2, Hi2_N, Hι3 , Hι3 N, Hι4, Hι4_N, Hi5_N, Hι6,.Hι6_N, Hi7, Hi7_X. Ho7_N, Ho7. Ho6_N, Ho6, Ho5_N, Ho5, Ho4_N, Ho4, Ho3_N, Ho3, Ho2_N, Ho2. Hol_N, Hoi, HoO.N, HoO, HoC.N, and HoC respecitively. No other pins, except for low-bandwidth and power connections which may contain vias, may be placed between these pins. Hermes device dies (or the active die of a sandwich) are generally designed to be placed on circuit boards face-down, so when viewed from the top of the circuit board, this becomes the ordering: When viewed from the top of the device die. this becomes the ordering: Other packaging systems may mount Kermes device dies in a face-up orientation Hermes devices sandwiched with a conductive-only die ( " space transformer " ) have the conductive-only die in a iace-' p orientation For a die mounted in a face¬ up orientation, the ordering of the pms of the die must be reversed, so when viewed from the top of the circuit board or the top of the die, this requires the ordering: The following is a diagram of the Hermes and Cerberus device interfaces, for a device with a single pair of Hermes channel interfaces. Logical Memorv Structure Hermes defines a logical memory region as an array of 2 8A blocks of size W bytes. Each access, either a read or write, references all bytes of a single block. All addresses are block addresses, referencing the entire block. Hermes defines a logical cache for data originally contained in the logical memory region. All accesses to Hermes memory space maintain consistency between the contents of the cache and the contents of the logical memory region. Packet Structure Packets sent on a Hermes channel contain control commands, most commonly read or write operations, along with addresses and associated data. Other commands indicate error conditions and responses to the above commands. When the Hermes channel is otherwise idle, such as during initialization and between packets, an idle packet, consisting of a pair of an all-zero byte and all-one byte is transmitted through the channel. Each non-idle packet consists of two bytes or a multiple of two bytes and must begin with a byte of value other than all- zero (0). All packets begin during a clock period in which the clock signal is zero, and all packets end during a clock period in which the clock signal is one. The general form of a packet is an array of bytes, without a specified byte ordering The first byte contains a module address in the high-order two bits, a packet identifier, usuallv a command, in the next three bits, and a link identification number The remaining b es' interpretation are dependent upon the packet identifier data General Dacket The length of the packet is implied by the command specified by the initial bvte of the packet. The check byte is computed as odd bit-wise parity, with a leftward circular rotation after accumulating each byte. This algorithm provides detection of single- bit and some multiple-bit errors with high probability (1-2' 8 ), but no correction. As an example, the following packet has a proper check byte: data The check byte in this example is calculated as. The general interpretation of the packet command is given in the following table: The module address field provides for as many as four Hermes slave devices to be operated from a single channel. Module address values are assigned via either static/geometric configuration pins (not recommended) or dynamically assigned via a Cerberus configurarion register. The link identification field provides the opportunity for Hermes master devices to initiate as many as eight independent operations at any one time to each Hermes slave device. Each outstanding operation to a Hermes slave device must have a distinct link identification number, and no ordering of operations is implied by the value of the link-identification field. There is no requirement for link-identification field values to be sequentially assigned in requests or responses. The following section provides detailed descriptions oi the structure of each type of command packet. Idle Idle packets fill the space between other packets with an alternating zero-byte and all-ones-byte pattern. Idle packets may be dropped when received and regenerated between outgoing packets. The idle packet is formatted as follows: Idle packet field interpretation No activity is performed upon receipt of a properly formatted idle packet. Read Operation Read packets cause a Hermes device to perform a read operation for the specified address, producing a data value. The value is read from cache, if one is present and the address is present in the cache. If the address is not present in cache, the value is read. A value read is placed in the cache if the command is "read- allocate"; if the command is "read-noallocate" the value is returned without copying the value into the cache. The packet format is as follows: The range of valid values and the interpretation of the fields is given by the following table: ead pao e: field interpretation If the fields are valid and the specified address is within the range of the memory, the memory is read and a read response packet is generated which contains the requested data value. The "read-response" packet is formatted as follows: The range of valid values and the interpretation oi the fields is given by the following table: Read response packet field interpretation In order to reduce the latency of read response, Hermes devices may generate a read response packet before checking redundant information that may alter the contents of the response. If, upon checking the information, but before the last byte of the read response packet is generated, the device detects that the data was transmitted in error, the packet is "stomped." that is, marked as invalid, by transmitting a check byte that is the ones-complement of the proper check byte. Such a packet must be ignored by Hermes masters and may be either ignored or suppressed by Hermes slave devices. If the redundant information indicates a correctable error, the stomped packet is followed by a read response packet which contains the corrected data. Wnte Operation Write packets cause Hermes devices to perform a write operation, placing a data value into the specified address. The value is written into cache, if one is present and the address is present in the cache. If the address is not present in cache, and the command is "write-allocate " , the value is written into cache. If the address is not present in cache, and the command is " wnte-noallocate", the value is written, leaving the cache location unchanged. The packet format is as follows: Write packet field interpretation If the fields are valid and the specified address is within the range of the memory, the memory is written and a write response packet is generated. The "wπte- response" packet is formatted as follows: Write response packet The range of valid values and the interpretation of the fields is given by the following able: Write response packet field interpretation Error Handling The receipt of packets that do not conform to the requirements of this specification over the input channel is an error, as are any conditions internal or external to the device that prevent proper operation, such as uncorrectable memory errors. The level or degree to which an implementation detects errors is implementation-defined; to the extent possible, this architecture specification recommends that all errors should be detected, but this is not strictly required. All implementations must document the level of error detection, and all detected errors must use the method described below for handling errors. For Hermes devices, the following errors should be detected and the level of error detection for each of these errors is required to be documented: errors detected invalid check byte invalid command invalid address uncorrectable error in cache uncorrectable error in device invalid identification number internal buffer overflow invalid module address on idle pacκ=t invalid identification number on idle/error packet invalid check byte on idle packet Packets received by Hermes devices may have an invalid check byte, invalid command, invalid module address, invalid address, invalid identification number, or in some implementations cause internal buffer overflow. For each such error which the implementation may detect, the device causes a response explicitly indicating such a condition (error response); the packet is otherwise ignored. Also, detection of an uncorrectable error in either the cache or the device resulting from a request over a Hermes input channel results in the generation of an error response packet. The error response packet is formatted as follows: 7 0 [malcom j lid check Error response packet The range of valid values and the interpretation of the fields is given by the following table: error response packet fieid interpretation Upon receipt of the error response packet, the packet originator must read the Cerberus status register of the reporting device to determine the precise nature of the error. Hermes devices reporting an invalid packet will suppress the receipt of additional packets until the error is cleared, by clearing the status register. However, such devices may continue to process packets which have already been received, and generate responses. Upon taking appropriate corrective actions and clearing the error, the packet originator should then re-send any unacknowledged commands. Because of the large difference in clock rate between the high-bandwidth Hermes channel and the Cerberus serial bus interface, it is generally safe to assume that, after detecting an error response packet, an attempt to read the status register via Cerberus will result in reading stable, quiescent error conditions and that the queue of outstanding requests will have drained. After clearing the status register via Cerberus, the packet originator may immediately resume sending requests to the Hermes device. Forwarding Hermes devices, whether master or slave, may have the capability to forward packets which are intended for other devices connected to a Hermes channel. For slave devices, this forwarding is performed on the basis of the contents of the module address field in the packet; packets which contain a module address other than that of the current device are forwarded. All non-idle packets which contain such module addresses must be forwarded, including error packets. For master devices, this forwarding is performed on the basis of the identifier number field in the packet; packets which contain identifier numbers not generated by the device are forwarded. To minimize ring latency, it is generally desirable to forward these packets with minimal latency. If a packet arrives at an input channel when the output channel is in use, this latency must increase; at least a single-packet buffer is required. The size of the forwarding buffer is implementation-dependent. Avoiding the generation of an output packet if the forwarding buffer does not have room to hold an additional input packet is required, when the forwarding buffer is smaller than the number of packets which may require forwarding (generally 24 packets). However, this strategy may cause starvation, as output packets may be inhibited indefinately by a stream of input packets that require forwarding. Starvation may be avoided by system-level design and configuration considerations beyond the scope of this specification. Packets which contain a check byte error may be forwarded; however it is recommended that such packets be transmitted with a check byte containing more than one error bit, to minimize the possibility of an undetected second error. Packets which contain a "stomped" check byte may be forwarded as is, or may be ignored by a forwarding device. Note that when a packet is forwarded with minimum latency, the output channel may begin transmitting a packet before the input channel has received the entire packet: in such a case, the only available choice is to continue forwarding the packet even if a check byte error or "stomped" check byte is detected. Ring Configurations Hermes supports a variety of ring configurations. All devices in a cascade must have the same values for A and W parameters, in order that each part may properly interpret packet boundaries. The table below summarizes the characteristics of the configurations available: Hermes ring ccnfigurations Master-slave Pair The simplest ring consists of a single Hermes non-forwarding master device and a single Hermes non-forwarding slave device. No forwarding is required for either device as packets are sent directly to the recipient. The ring may have as many as eight transactions outstanding, each containing distinct id field values. Single-master Ring A single-master ring may contain a cascade of up to four Hermes slave devices. The cascade of devices will have the same or greater bandwidth as a single device, but more latency. Each Hermes slave device must be configured to a distinct module address, and each slave device must forward packets that contain module address fields unequal to their own. Packets are explicitly addressed to a particular Hermes device; any packet received on a device's input channel which specifies another module address is automatically passed on via its output channel. This mechanism provides for the serial interconnection of Hermes devices into strings, which function identically to a single device, except that a string has larger capacity and longer response latency. Each slave device may have as many as eight transactions outstanding, each containing distinct id field values. Dual-master Pair A dual master pair consists of two master devices and no slave devices. Each master device may initiate read and write operations addressed to the other, and each may have up to eight such transactions outstanding. No forwarding is required for either device as packets are sent directly to the recipient. M M Hermes dual-master pair Multiple- master Single-slave Rng A multiple-master ring may contain multiple master devices and a single Hermes slave device, provided that the master devices arrange to use different id values for their requests. Each master may use a share of the eight transactions. Master devices must forward packets not specifally addressed to them, as designated by the values in the id field. The slave device need not forward packets, as all input packets are designated for the slave device. Multiple-master Multiple-slave Ring A multiple-master ring may contain multiple master devices and as many as four Hermes slave devices, provided that the master devices arrange to use different id values for their requests. Each slave may have up to eight transactions outstanding, and each master may use a share of those transactions. Master devices must forward packets not specifally addressed to them, as designated by the values in the id field. Slave devices must forward packets not specifically addressed to them, as designated by the value of the ma field. M M M M Hermes multiple-master multiple-slave ring Resopnse Packet Timing In general, ' a received packet which is interpreted as a command causes a response packet to be generated. The latency between the end of the request packet and the beginning of the response packet is affected by the processing and forwarding of other packets, by the presence or absence of the requested word in the cache, as well as implementation-dependent device parameters and characteristics With full knowledge of the cache state, configurable parameters and implementation-dependent characteristics, a Hermes master may completely model the latency of responses. However, dependence on such characteristics is not recommended, except for testing and characterization purposes A Hermes master must have the capabilitv to detect a time-out condition, where a response to a request packet is never received. The length of the time-out is implementation-defined, and dependent upon the implementation of the Hermes slave devices, so it is recommended that this time-out be long enough to accomodate variation in the design of Hermes slave devices, or be configurable to permit recovery in a minimum implementation-dependent delay. Cerberus Registers The Hermes channel architecture builds upon the Cerberus serial bus architecture. Only the specific requirements of Hermes-compliant devices are defined below. Hermes requires that the values of A and log2 be made available in the high- order byte of the first architecture description register as indicated below The format of the register is described in the table below. The octlet is the Cerberus address of the register; bits indicate the posifion of the field in a register. The value indicated is the hard-wired value in the register for a read/only register, and is the value to which the register is initialized upon a reset for a read/write register. If a reset does not initialize the field to a value, or if initialization is not required by this specification, a w is placed in or appended to the value field. The range is the set of legal values to which a read/write register may be set. The interpretation is a brief description of the meaning or utility of the register field, a more comprehensive description follows this table. octlet bits field name value ranαe interoretation 4 63 60 59 56 55 0 Architecture Description Registers The architecture description registers in octlets 4 and 5 comply with the Cerberus specification and contain a machine-readable version of the architecture parameters: A, W described in this document. Cerberus Serial Bus MicroUnity s Cerberus serial bus architecture is designed to provide bootstrap resources, configuration and diagnostic support tor MicroUnitv's Terpsichore system architecture The Cerberus serial bus emplovs two signals, both at TTL levels, for direct communication among as many as 2& devices One signal is a continuouslv running clock, and the other is an open-collector bidirectional data signal Four additional signals provide a geographic 8-bit address for each device A gatewav protocol and optional configurable addressing each provide a means to extend Cerberus to as manv as 2 buses and 2 24 devices The protocol is designed for universal application among the custom chips used to implement the Terpsichore system architecture It is also designed to be compatible with implementations embodied in FPGA parts, such as those made by Xilinx, Altera, Actel and others Such FPGA parts may be used to adapt the Cerberus protocol in a minimum of logic to attach small serial bus devices, such as those made by Dallas Semiconductor (EEPROM, serial number parts), ITT (1MB bus), Signetics (I 2 C bus). It is also a goal that such FPGA parts can be used to adapt the Cerberus protocol to communication over EIA-232/422/423/485 links to existing systems for the purposes of system development, manufacturing test and configuration, and manufacturing rework The Cerberus serial bus is used for the initial bootstrap program load of Terpsichore; the bootstrap ROM connects to Terpsichore via Cerberus Because the Cerberus must be operational for the fetch of the first instruction of Terpsichore, the bus protocol has been devised so that no transactions are required for initial bus configuration or bus address assignment Electrical Signalling The diagram below shows the signals used in Cerberus. The SC signal is a continuously running clock signal at TTL levels. The rate is specified as 20 MHz maximum. 0 (DC) minimum. The SC signal is sourced from a single point or device, possibly through a fan-out tree, the location of which is unspecified. The actual clock rate used is a function of the length of the bus and quality of the noise and signal termination environment. The amount of skew in the SC signal between any two Cerberus devices should be limited by design to be less than the skew on the SD signal. The SD signal is a non-inverted open-collector (0 = driven = low; 1 = released = high) bidirectional data signal, at TTL levels, used for all communication among devices on Cerberus. One of several termination networks may be used on this signal, depending upon joint design targets of network size, clock rate, and cost. One of the simplest schemes employs a resistive pull-up of the equivalent of 220 Ohms to 3.3 Volts above V$s- A more complex termination network, such as termination networks including diodes, or the "Forced Perfect Termination" network proposed for the SCSI-2 standard may be advantageous for larger configurations. Termination voltages as high as 3.3 V are permitted. The following table specifies parameters that must be met by Cerberus-compliant devices Voltages are referenced to Vss Geographic addressing The objective of the geographic addressing method m Cerberus is to ensure that each device is addressable with a number which is unique among all devices on the bus and which reflects the physical location of the device, so that the address remains the same each time the system is operated. When a system requires at most 16 devices, the geographic addressing method permits the assignment of addresses 0 through 15 by directly wiring the low-order 4 bits of the address in binary code using mput signals SN3 0 For these purposes, wiring to a logic high (H) level supphes a value of 1, and wiring to Vss or -- 0 g ιc -- ow (L) level supphes a value of 0. -^Cerberus recommends, but not require, compliant devices be able to sustain input levels provided by 5V TTL-compatible devices on the SC and SN3 0 inputs ' ■ ♦Devices which fail to comply with the low-state output current specification may operate with Cerberus-compliant devices, but mav require changes to the termination network System designers should evaluate the effect that limited drive current will have on the worst-case Low- state signal level 55 Devιces which fail to complv with the oft-state output current specification mav operate with Cerberus compliant devices, but mav limit the number of devices which may co-exist on a single Cerberus bus System designers should evaluate the effect that additional leakage current will have on the worst-case High-state and Lo -state signal levels The table below indicates the wiring pattern for each device address from 0 through 15: An extension of this method is used for the assignment of addresses 0 through 255 when a system requires more than 16 devices, up to 2 8 devices. Additional code combinations are made available by wiring each of the same input signals SN3 .0 as before to one of four signals: the two described above, L and H, and two additional signals, a buffered copy of the SC signal and an inverted copy of the SC signal (SC_N). Since there are four SN signals, each wired to one of four values, =28=256 combinations are possible. The wiring pattern is constructed using the algorithm: If the desired device address is the value N, for each input signal SN X) where x is in the range 3..0, wire SN X to one of the four signals L, H, SC, or SC_N, according to the following table, depending on the value of bit 4+x and bit x of N. The diagram below shows the waveform of the SC signal and the four signals that each of the SN3 .. 0 inputs may be wired to. The values shown in the diagram above are decoded using four copies of the following logic, one for each value of x in the range 3..0: The NU and NL values are combined together in the order: 7 6 5 4 3 2 1 0 NU 3 | NU 2 | NUi | NUp | NL 3 | NL 2 j NLj | NLp 1 1 1 1 1 1 1 1 to construct an 8-bit device number by which operations are addressed. Bit-Level Prctoccl The communication protocol rests upon a basic mechanism by which any device may transmit one bit of information on the bus, which is received by all devices on the bus at once. Implicit in this mechanism is the resolution of collisions between devices which may transmit at the same time. Each transmitted bit begins at the rising edge of the SC signal, and ends at the next rising edge. The bit value is sampled by all devices at the next rising edge of the SC signal, thus permitting relatively large signal settling time on the SD signal, provided that skew on the SC signal is adequately controlled. The transmission of a zero (0) bit value on the bus is performed by the transmitter driving the SD signal to a logical-low value. The transmission of a one (1) bit value on the bus is performed by the transmitter releasing the SD signal to attain a logical-high value (driven by the signal termination network). If more than one device attempts to transmit a value on the same clock period (of the SC signal), the resulting value is a zero if any device transmits a zero value, and is a one if all devices transmit a one value. We define the occurrence of one or more devices transmitting a zero value on the same clock cycle where one or more devices transmit a one value as a collision. Because of this wired-and collision mechanism, if a device transmits a zero value, it cannot determine whether any other devices are transmitting at the same time. If a device transmits a one value, it can monitor the resulting value on the SD signal to determine whether any other device is transmitting a zero value on the same clock cycle. In either case, if two or more devices transmit the same value on the same clock cycle, neither device, in fact, no device on the bus can detect the occurrence, and we do not define such an occurrence as a collision. This collision mechanism carries over to the higher levels of the protocol, where if two or more devices transmit the same packet or carry on the same transaction, no collision occurs. In such cases, the protocol is designed so that the transaction occurs normally. These transactions may occur frequently if two identical devices are reset at the same time and each initiates bus transactions, such as two processors each fetching bootstrap code from a single shared ROM device. Packet Protocol The packet protocol uses the bit-level mechanism to transmit information on the bus in units of eight bits or a multiple of eight bits, while resolving potential collisions between devices which may simultaneously begin transmitting a packet. The transmission provides for the detection of single-bit transmission errors, and for controlling the rate of information flow, with eight-bit granularity. The protocol also provides for the transmission of a system-level reset. Each packet transmission begins with a single start bit, in which SD always has a zero (driven) value. Then the bits of the first data byte are serially transmitted, starting with the least-significant bit. After transmitting the eight data bits, a parity bit is transmitted. If transmission continues with additional data, a single one (released) bit is transmitted, immediately followed by the least-significant bit of the next byte, as shown in the figure below: sc AΛAAAAAAAΛΛ/W VW l start parity delay Packet transmission Any Cerberus device may abort a transaction, usually because of a detected parity error or a deadlock condition in a gateway, by driving the SD signal (to a zero value ) on the "d" (delay) and the "a" (abort) cycles, as well as the next ten cycles, for a total of 12 cycles. The additional ten cycles ensure that the abort is detected by all devices, even under the adverse condition where a single-bit transmission error has placed devices into inconsistent states. Each device that detects an abort drives the SD signal (to a zero value) for ten cycles after its "a" (abort) cycle state, so in the most adverse case, an abort may have devices driving the bus to as many as 22 consecutive cycles. The figure below shows a typical (12 cycle) transaction abort, followed by an immediate re-transmission of the transaction. Any Cerberus device may reset the Cerberus bus and all Cerberus devices, by driving the SD signal (to a zero value) for at least 33 cycles. This is sufficient to ensure that all devices receive the reset no matter what state the device is in prior to the reset. Transmission may resume after the SD signal is released (to a one value) for two cycles, as shown in the figure below. The state diagram below describes this protocol in further detail: The table below describes the data output and actions which take place at each state in the above diagram. The next state for each state in the table is either column go-0 or go-1, depending on the value of the in column. In order to avoid collisions, no device is permitted to start the transmission of a packet unless no current transaction is underway. To resolve collisions that may occur if two devices begin transmission on the same cycle, each transmitting device must monitor the bus during the transmission of one (released) bits. If any of the bits of the byte are received as zero (driven) when transmitting a one (released), the device has lost arbitration, and must transmit no additional bits of the current byte or transaction. A device which has lost the arbitration of a collision, or has suffered the occurrence of a transaction abort, may retry the transmission immediately after the transmission of the last byte of the current transaction, as shown in the figure below. I * AAAAAAAΛAAAA/ Vλ A. ! s m parity delay sitartI mi II iMm parityF delayXMIM re-transmission after loss of arbitration All other devices must wait one additional SC (clock) cycle before transmitting another message, as shown in the figure below. This ensures that all devices which have collided perform their operations before another set of devices arbitrate again. «• AAAW VAAAAAΛAAAAA so W/W parity de^lay^ start startt MMHMSM& parityF delay IM re-transmission after loss of arbitration All initiator-capable devices must enforce a time-out limit of no more than 256 idle clock cycles between the packets of a transaction. After seeing this many idle clock cycles, at some time within the next 256 clock cycles, such devices must abort the current transaction transmitting a time-out packet, which consists of two bytes of zeroes. Slow devices may require more cycles between the transmission of packets in a transaction than are permitted as idle clock cycles. Such devices may avoid the time-out limit by delaying the completion of the transmission of the previous packet until the idle time is less than the time-out limit, as shown in the figure below. In this way, devices of any speed may be accommodated. It is necessary that initiator-capable and other devices cooperatively avoid collisions between the time-out packet and transaction responses. The responsibility of the initiator devices is to inhibit transmission of a time-out packet if, before the time-out packet can be transmitted, some device begins transmitting, even if such a transmission begins after 256 idle clock cycles have elapsed. If the design of a target device ensures that no more than 256 idle clock cycles elapse between packets of a transaction, it need not be concerned of the possibility of a collision during the transmission of a response packet. Otherwise, the responsibility of the target devices is to inhibit transmission of a response if some other device begins transmitting a time-out packet after at least 256 idle clock cycles have elapsed. A device which requires delay after an aborted transaction or a reset may cause such a delay by forcing the delay bit after the first byte of the immediately following transaction, as required. If in such a case, the device cannot keep a copy of the first byte of the transaction, it may force the transaction initiator to retransmit the byte by aborting that following transaction after a suitable delay has been requested. Transaction Protocol A transaction consists of the transmission of a series of packets. The transaction begins with a transmission by the transaction initiator, which specifies the target net, device, length, type, and payload of the transaction, request. If the type of the packet is in the range 128..255, the target device responds with an additional packet, which contains a length and type code and payload. The transaction terminates with a packet with a type field in the range 0.J27, otherwise the transaction continues with packet transmission alternating between transaction initiator and the specified target. The general form of an initial packet is: I no l n- t | de| L I T 1 PQ | PI 1 |p L .. | The general form of subsequent packets is: The range of valid values and the interpretation of the bytes is given bv the following table: general transaction byte interpretation general transaction byte interpretation All Cerberus devices must support the transaction codes: te, tc, d8, w8, and r8. All Cerberus devices monitor SD to determine when transactions begin and end. A transaction is terminated by the completion of the transmission of the specified number of payload bytes in a transaction with code in the range 128..255, or by the transmission of an abort sequence. For purposes of monitoring transaction boundaries, only the L byte is interpreted; the value of the T byte (except for the high order bit) must be disregarded. This is of particular importance as many transaction codes are reserved for future definition, and the use of such transaction codes between devices which support them must be permitted, even though other devices on the Cerberus bus may not be aware of the meaning of such transactions. A Cerberus device must permit any value in the L byte for transactions addressed to other devices, even if only a limited set of values is permitted for transactions addressed to that device. Transactions addressed to a device which does not provide support for the enclosed transaction code or payload length should be aborted by the addressed target device. The selection of the payload length L and transaction code T for the transaction error packet is of particular note. Because the value of all information bits of the packet is zero, it is guaranteed that a device which transmits this packet will have collision priority over all others. Write Octlet The "write octlet" transaction causes eight bytes of data to be transferred from the transaction initiator to the addressed target device at an octlet-aligned 16-bit device address. The transaction begins with a request packet of the form: I no I ni I de I 10 Iw8 I Ap I Aj I Dp I Di 1 D 2 I P 3 I D 4 I p 5 I P β j P 7 The normal response to this request is of the form: 1 0 I tc l The error response to this request is of the form: 1 0 I te 1 The 16-bit device address is interpreted as an octlet address (not a byte address) and is assembled from the Ao and Ai bytes as (most significant byte is transmitted first): The data to be transferred to the target device is assembled into an ocdet as (most significant byte is transmitted first): 63 5655 4847 4039 3231 2423 16 15 8 7 0 [ Do Pi P 2 I P 3 I P4 I Ps t PG I P Side-effects due to the alteration of the contents of the octlet at the specified address are only permitted if the transaction completes normally. In the event that the write octlet transaction is aborted at or prior to the transmission of the A i byte, the target device must make no permanent state changes. If the transaction is aborted at or after the transmission ot the Do byte, the contents of the octlet at the specified address is undefined. If alterations of the contents normally would cause side-effects in the operation of the Cerberus device or side-effects on the contents of other addressable octlets in the device, these side-effects must be suppressed. If the addressed target device is not present on the Cerberus bus, the transaction will proceed to the point of transmitting the octlet data and then stop until the idle time-out limit is reached. At that point, one or more initiator-capable devices will generate an error response packet. If the addressed target device is present on the Cerberus bus, but the 16-bit device address is not valid for that device, the target must generate an error response packet. Read Octlet The "read octlet" transaction causes eight bytes of data to be transferred to the transaction initiator from the addressed target device at an octlet-aligned 16-bit device address. The transaction begins with a request packet of the form: The normal response to this request is of the form: H I d8 I Dp 1 Pj I P 2 I P 3 I P4 I Ps I Pβ I P? I The error response to this request is of the form: C H The 16-bit device address is interpreted as an ocdet address (not a byte address) and is assembled from the Ao and Ai bytes as (most significant byte is transmitted first): The data to be transferred to the target device is assembled into an ocdet as (most significant byte is transmitted first): 63 5655 4847 4039 3231 2423 16 15 87 0 Do I Di I D2 I Da I P4 I Ps I Pβ I P? Regardless of whether the transaction completes, the read octlet transaction must have no side-effects on the operation of the Cerberus device or the contents of other addressable octlets. If the addressed target device is not present on the Cerberus bus, the transaction will proceed to the point of transmitting the octlet address and then stop untd the idle time-out limit is reached At that point one or more initiator-capable devices will generate an error response packet If the addressed target device is present on the Cerberus bus, but the 16-bit device address is not valid for that dev ice, the target must generate an error response packet. Dedicated Octlets Certain octlet addresses are assigned by which all Cerberus devices may be identified as to device type, manufacturer, revision, and by which devices may be individually reset and tested. All or part of octlet addresses 0..7 are reserved for this purpose. The ocdets at addresses 0 through 3 identifies the company which specifies the device architecture (e g. MicroUnity), the device architecture (e.g Mnemosyne, Terpsichore, Calliope), the implementor (e g MicroUnity, partner), the device implementation and manufacturer and manufacturing version (e.g 1.0,1.1.2.0), and optionally a unique device serial number. Addresses 0 through 2 are read/only; an attempt to write to these addresses may cause either a normal termination or an error response. Address 3 may be read/only or read/write. octlet 63 16 15 O 1 2 48 1 The octlet at address 0 contains an architecture code and revision idenutier The architecture code and revision identities each distinctlv designed architecture version of a device Normallv, a change in the upper byte of the revision indicates a change in which features mav have changed A change in the lower bvte of the revision signifies a change made to repair design defects or upward-compatible revisions The architecture code is a unique 48-bit identifier, comprised of the concatenation of a 24-bit unique company identifier 50 , and a 24-bit value specified by the designated company This code must not duplicate 48-bit identifiers specified for this purpose, or for other purposes including use of unique identifiers for implementation codes, manufacturing codes, or in IEEE 1212, or IEEE 802. IEEE 802 48-bit identifiers are specified in terms of a binary ordering of bits on a single line, for Cerberus, the ordering which is appropriate is that labelled "CSMA/CD and Token Bus," where bits are driven onto Cerberus with the least-significant bit of each byte first MicroUnity's architecture codes are specified by the following table Refer to the designated architecture specification for architecture revision codes ^Company identifiers are a 24-bit value assigned bv authority of the IEEE Ask for a 'unique co panv identifier' tor vour organization Registration Authorm for Company Identifiers The Institute of Electrical and Electronic Engineers 445 Hoes Lane Piscatawav NJ 08855-1331 USA (908) 562-3812 MicroUnity's unique company identifier is 0000 0000 0000 0010 1100 0101 Only MicroUnity may assign unique 48-bit identifiers that begin w ith this value Others may assign 48-bit identifiers that begin with a 24-bit company identifier assigned by authority of the IEEE MicroUnity will, upon request, supply unique 48-bit identifiers for architectures, lmplementors, or manufacturers of designs which are fullv compliant with the Cerberus Serial Bus Architecture For assignment of identifiers, contact MicroUmtv Craig Hansen Chief Architect Registration Authority for Unique Identifiers MicroUmtv Systems Engineering, Inc 255 Caspian Drive Sunnwale. CA 94089-1015 Tel (408) 734-8100 Fax (408) 734-8136 The octlet at address 1 contains an implementation code and revision identifier. The implementation code and revision identifies each distinctly designed engineering version of a device. The implementation code is a unique 48-bit identifier, as for architecture codes. Normally, a change in the upper byte of the revision indicates a change in which features may have changed, or in which all mask layers of a device have been modified. A change in the lower byte of the revision signifies a change made to repair design defects or in which only some mask layers of a device have been modified. Refer to the designated architecture specification for the values of the implementation code and revision fields. The octlet at address 2 contains a manufacturer code and revision identifier. The manufacturer code and revision identifies each distinct manufacturing database of an implementation. The manufacturer code is a unique 48-bit identifier, as for architecture codes. Changes in the manufacturer revision may result from modifications made to any or all mask layers to enhance yield or improve expected device performance. Refer to the designated architecture specification for the values of the manufacturer code and revision fields. The octlet at address 3 optionally contains a unique device serial number or random number .and optionally contains a configurable address register. If the octlet does not contain a serial or random number, it must contain a 64-bit zero value. If the octlet contains a unique device serial number, it must be a unique 48-bit value, as for architecture codes. If the octlet contains a random number, it must be a value chosen from a uniform distribution, selected whenever the device is reset. The optional configurable address register permits a system design in which some devices are set to identical Cerberus device addresses at system reset time, and dynamically have their addresses moved to unique addresses by some Cerberus device. The configurable address register must be set to the address designated by the SN3..0 pins whenever the device is reset. A device which implements the configurable address capability must also implement either a unique device serial number or a random number, must implement the arbitration mechanism during responses from read-ocdet requests, and must ensure that all devices which are originally set to the same address at reset time respond to a read-ocdet with identical latency. An initiator device on Cerberus may set the configurable address register by reading the entire octlet at address 3 , reading both the serial/random number and the configurable address register. By the use of the bitwise arbitration mechanism, only one device completes the read-ocdet response packet. Then, the initiator device writes a value to octlet address 3, where the first 48 bits of the value written must match the value just read. All target devices then examine the first 48 bits of the value written, and only if the value matches the contents of the serial/random number on the device, uses the last 16 bits 57 to load into the configurable address register The initiator will repeat this process until there are no more devices at the original/ reset address, at which time a bus time¬ out occurs on the read-ocdet transaction The octlets at addresses 4 and 5 contain architecture parameters Values are device-architecture-dependent and implementor-independent, refer to the designated architecture specification for information Addresses 4 and 5 are read/only; an attempt to write to these addresses may cause either a normal termination or an error response. octlet 63 0 architecture parameters not specified by Cerberus architecture parameters not specified by Cerberus 64 Octlet 6 designates overall device settings Values in address 6 are changed only by external devices and not by the device itself, this register is read/write Two bits of the first byte have standard meaning for all Cerberus devices. Bits 61..0 are not specified by Cerberus except by the restriction that these values are changed only by external devices, not by the device itself; refer to the designated architecture specification for information. Writing a one to bit 63, r, of ocdet 6 causes the device to perform a device circuit reset, which is equivalent to the reset performed by driving the SD signal (to a zero value) for 33 or more cycles, and sets the device to an initial state in which previous device state may be lost, previous control settings may be lost and variable power settings are set to a minimal, functional value, after which bits 63 and 62 of the status register below are set (to ones). Writing a one to bit 62, c, of octlet 6 causes the device to perform a device logic clear, which initializes the device to a known, quiescent, initial state, in which previous device state may be lost, but does not affect control register settings related to variable power settings, after which bits 63 and 62 of the status register below are set (to ones). Writing a one to bit 61, s, of ocdet 6 causes the device to perform a self-test, after which previous device state may be lost, and after which bit 62 of the status register below is set (to one) if the self-test yields satisfactory results. Bit 63 of the status register below is set (to one) at the end of the self-test. octlet 63 62 61 60 0 6 j r 1 c I s j other device settings not specified by Cerberus { 1 1 1 61 57 A 16-bit field provides for the possibility of configuring devices which respond to addresses directlv that have net numbers set, thereby blurring the dividing line between Cerberus net addresses and device addresses Gateway designers might want to consider this possibilit y Octlet 7 designates device status. Values in address 7 are normally modified only by the device itself, except when an external device may clear status or error conditions; this register is read/write. However, the only valid data which can be written to this register is a zero value, which clears any outstanding status or error reports. Two bits of the first byte have standard meaning for all Cerberus devices. Bits 61..0 are not specified by Cerberus except by the restriction that these values are modified only by the device itself except for clearing by an external device; refer to the designated architecture specification for information. Bit 63 , c, of octlet 7 indicates whether the device has completed reset, clear, or self-test. Bit 62, s, of octlet 7 indicates whether the device has successfully completed reset, clear, or self-test. octlet 63 62 6 1 7 | c | s I other device status not specified by Cerberus 1 1 62 Octlets at addresses 8..2 1 6 -1 are not specified by Cerberus. Refer to the designated architecture specification for information. Gateways The Cerberus bus may be extended into a network of buses using a gateway. Gateways connect between buses that use the wired-and signalling protocol described above. A gateway attaches to a local Cerberus bus and receives and retransmits bus requests and responses over a linkage to other gateways, thereby reaching to additional Cerberus buses. This document does not specify the protocol used to link gateways. The diagram below shows a gateway network connecting several Cerberus buses: Each Cerberus bus in a Cerberus network may, for specification purposes, be assigned a unique network number, in the range 0..2 16 -1. These network numbers never appear directly in Cerberus device addresses, as the target network byte specified in the request packet of a Cerberus transaction contains only a relative net number: the target net either minus, or xor'ed with, the initiator net. Thus, the relative target network address is always zero when the initiator and the target are on the same Cerberus bus, and is always non-zero when they are on different buses. A Cerberus bus permits only one transaction to occur at a time. However, a Cerberus network may have multiple simultaneous transactions, so long as the target and initiator network addresses are all disjoint. In more precise terms, the network addresses must satisfy the relations: target; ≠ initiator ] target; ≠ target ] initiator; ≠ initator j , for all i ≠ j. A Cerberus network may set more restrictive conditions for simultaneous transactions by its internal design, as required by limits of performance or bandwidth of the gateway network. When these conditions are not satisfied, one or more transactions may be selected to be aborted on the local Cerberus bus on which they are initiated by any fair-scheduling mechanism. Each local Cerberus bus is connected to the gateway network by exactly one gateway. When a request packet of a transaction is received by a gateway on a local Cerberus bus, the first byte of the packet specifies a net number. If this byte is non-zero, the gateway, which we will designate the initiator gateway, must carry this transaction across the gateway network. This number is interpreted as a signed byte, relative to the initiator gateway, and specifies a gateway to be the target of the transaction, which we will designate the target gateway. We will refer to the local Cerberus bus to which the initiator gateway is attached as the initiator bus, and the bus to which the target gateway is attacked as the target bus. The request packet is carried via the initiator gateway, through the gateway network, to the target gateway, which then re-transmits the packet on the target bus. When the request packet is re-transmitted on the target bus, the network number byte is zero, designating a target on the target bus. The initiator gateway may delay transmission of the request packet on the initiator bus as required to limit or manage the flow of information through the gateway network, between each byte of the request packet. The initiator gateway must also delay transmission at the end of the last bvte of the request packet in order to ensure that packet aborts on the target bus are propagated back to the initiator bus. The initiator gateway must also ensure that a target device which responds just barely within the time-out limit on the target bus does not cause a time-out on the initiator bus, generally by asserting a delay on the initiator bus until this condition can be assured. When a response packet is generated on the target bus (which may be from either the addressed target or some time-out generator), the packet is carried in the reverse direction by the gateway network. This response and any further packets are carried until the end of the transaction The contents ot the response and further packets are not changed bv the gateway network When a local Cerberus bus reset is receiv ed bv a gatew a , the reset is carried by the gateway network and each other gatew ay then re-transmits a reset transaction on all other local buses Repeater A Cerberus bus may be extended by inserting repeaters A repeater electrically separates two segments of a Cerberus bus, but provides a transparent linkage between these two segments Using a repeater is advantageous when the capacitive load or clock skew between Cerberus devices on a large bus would require a reduction in the clock rate. The system designer must ensure that device addresses remain unique across what is logically a single serial bus Generally, a repeater will repeat each request packet seen on one side of the repeater on the other side, with a delay of at least one clock cycle If two transactions appear nearly simultaneously on each side of the repeater, the repeater must abort one of the transactions and permit the other to be repeated This arbitration must be performed fairly, such as by alternating which side of the repeater is preferred on consecutive collisions. A simple repeater continues until the end of the transaction by repeating the response packets, which may appear on the same or opposite side as the original request packet of the transaction. If the topology of the Cerberus is constructed so that only target devices exist on one side of the repeater, the design may be simplified by the elimination of the arbitration function. In such a case, transactions may only originate from the side designated to contain initiator-capable devices. A more sophisticated repeater may "learn" which addresses are on each side of the repeater, and only repeat transactions which need to cross the repeater to be completed. Alternatively, a repeater may be constructed with knowledge of the addresses to be placed on each side, such as addresses 0.J27 on one side and addresses 128..255 on the other, again permitting the selective repeating of packets across the repeater. Synchronous Repeater A very simple form of repeater may be employed to divide up the capacitive and leakage load on the SD signal of a Cerberus bus into two or more segments, when a common SC clock reference is used. The synchronous repeater samples each electrically-isolated segment of a logically-single Cerberus bus on the falling edge of each SC clock cycle, then broadcasts the logical AND of all the values on each segment during the SC clock low period. For large networks, this repeater improves performance by dividing up the RC delay by a factor of n, though two bus settling periods now occur on each SC clock period, so the speedup is approximately j. This circuit can be economically implemented using a single TTL '621 part and a pull-up resistor: Icarus Interprocessor Protocol MicroUnity ' s Icarus interprocessor protocol uses Hermes high-bandwidth channels to connect Terpsichore processors together, either directly or through external switching components, permitting the construction of shared-memory, coherently- or incoherently- cached multiprocessors. Icarus uses Hermes in the " Dual-Master Pair" configuration, and can be extended for use in "Multiple- Master Ring" configurations. Internal daemons within Terpsichore perform and respond to Hermes write operations upon which the Icarus interprocessor communication protocol is embedded. These daemons provide for the generation of memory references to remote processors, for access to Terpsichore's local physical memory space, and for the transport of remote references to other remote processors. Interprocessor Topologies The simplest multiprocessor configuration that can be built with the Icarus protocols is a dual-processor: The diagram below represents the same dual-processor system, in a simpler notation: T Dual-processor Terpsichore with Icarus interprocessor link In the configuration above, a pair of Hermes channels are connected together to form an Icarus Interprocessor link in the Dual-Master Pair configuration. A Cerberus bus connects all the system components together to facilitate system configuration. The Terpsichore processors all run off of a common frequency clock, as required by the Hermes channels that connect between processors. Dual Terpsichore processors with dual Icarus links may use both links to enhance svstem bandwidth: Dual-processor Terpsichore with Icarus interprocessor link A Terpsichore processor's dual Icarus links, each in the Dual-Master Pair configuration may connect to two different processors. Using the Icarus Transponder daemons in each processor, several processors may be interconnected into a linear network of arbitrary size: The Icarus links may also join at the ends of the linear network, forming a ring or arbitrary size. In the configuration above, two Icarus links are connected to each Terpsichore processor, forming a single ring. By connecting Icarus links into 4-master rings, providing Hermes master forwarding for responses, using the Icarus Transponder daemons in each processor, processors may be interconnected into a two-dimensional network of arbitrary size: In the configuration above, two Icarus links are connected to each Terpsichore processor, forming a single ring. Other multidimensional topologies can be constructed by using multimaster rings as basic building blocks. An n-master ring (n<4) of Terpsichore processors has n Icarus link-pairs available for connection into dual-master or multi-master configurations. For example, with a 4-master ring: These building blocks can then be assembled into radix-n switching networks: By connecting Icarus links to external switching devices, multiprocessors with a large number of processors can be constructed with an arbitrary interconnection topology: H H H H H H Eight-processor Terpsichore with Icarus links to switching fabric In the configuration above, two Icarus links connect each Terpsichore processor to a switching fabric consisting of Hydra s itches. Link- level and Transaction -level Protocol Icarus uses the Hermes protocol at the link-level, and uses Hermes operations to embed a transaction-level protocol. Two-packet link-action nomenclature We designate the term "link-action" to describe the low-level packet protocol used between a Hermes master device and a Hermes slave device. The packets that make up a link-action contain a three-bit link-action identifier, or "lid," which permit up to eight outstanding link-acdons to be in progress at any point in time. Link-actions consist of two actions. Each packet transmitted on the Hermes ring corresponds to an action: Repuest the action taken by a requester to start the transaction. ResDonse the action taken by the responder to finish the transaction. Link-action nomenclature These actions and their relation to the data flow is shown below. Requester ResDonder JUlQuest Response , Liπk-acticn actions and data flow Four- p acket transaction nomenclature We designature the term "transaction" to describe the upper-level packet protocol used when embedding a four-packet, or "split" transaction above the link-level Hermes packet protocol. Transactions are used when the latency of a transaction may require that more than eight actions are outstanding at a point in time, in order to maintain the desired throughput of the protocol. Embedding the transaction protocol above the link-action protocol limits the amount of link-level state which must be implemented. Certain of the packets that make up a transaction contain an eight-bit transaction identifier, or "rid," which permit up to 256 outstanding transactions to be in progress at any point in time. These packets also contain link-action identifiers, lids, which connect these packets with others which are part of the transaction, but do not contain a tid. Transactions consist of four actions. Each action results in one or more link-level Hermes packets transmitted on the channels: Request the action taken by a requester to start the transaction Indication the reception of a request by a responder. Response ! the action taken by the responder to finish the transaction Confirmation ' the reception of the response by the requester Transaction nomenclature These actions and their relation to the data flow is shown below: The following table shows the relationship between transaction-level actions and link-level actions, showing typical transaction messages and link-action commands: Transaction- Typical transaction Link-level Link-action command level action message actions Request read/write-sizelet- Request write-octlet request Indication Remote-indication ! Response ; write-response Response read/wπte-sizelet- I Request write-octlet response Confirmation I Remote-confirmation I Response ι write-response Transaction protocol for Icarus Requester Daemon Icarus Action Format Request and Response actions A series of link-level write octlet operations comprise an Icarus request or response action. The address ot the write operation contains target routing, transaction-id, commands and sequence information in the following format: A remote request is a write octlet to an address of the form: 31 1 6 1 5 8 7 0 | node | tid | com | 16 with data of the form: 63 octlet 64 The tid field contains an 8-bit transaction id code which must be returned along with the remote response. The tid field value must be unique among all transactions originating from a node, but tid field values of transactions originating from distinct nodes may be equal. The com field contains a 6-bit command code which, in the first octlet, designates the operation to be performed in a request action or the result returned in a response action. If the command code is in the range 0..31, in successive octlets, the value of the com field indicates whether the number of octlets to follow (0..9), such that the last ocdet of a message contains a com field with a 0 value. The node field contains a 16-bit node address which is the target of the action. When embedded into a link-level write octlet operation, the Terpsichore requester daemon request appears on the Hermes in the form: A transaction which has a payload of one octlet must use a link-level write octlet operation. A transaction which has a payload of greater than one octlet may successively use link-level write octlet operations to transmit the payload. Indication and Confirmation actions Indication and Confirmation actions consist of a series of link-level write octlet response packets, one for each ocdet of the Request and Response actions. Icarus Reouester Daemon When Terpsichore attempts a load or store to a physical address in which the high-order 16 bits are non-zero, the memory at that address is assumed to be present in the memory space of a remote Terpsichore processor. The Icarus Requester Daemon is an autonomous unit which attempts to satisfy such remote memory references by communicating with an external device, either another Terpsichore processor or a switching device which eventually reaches another Terpsichore processor. These remote references are characterized by an eight-byte physical byte address, of which two bytes are used for specifying a processor node, and the remaining six bytes are used for specifying a local physical address on that processor node. The Icarus Requester Daemon associates each remote memory reference with a transaction identifier 58 of eight bits, permitting up to 256 such remote references to be outstanding at any time, however, implementation limits within Terpsichore may set a smaller bound. The Icarus Requester Daemon takes the role of the Transaction Requester, and an external device takes the role of the Transaction Responder. The daemon generates writes to a specified bvte-channel and module address, which causes an external device to read or write remote octlets or cache lines in a remote memory The daemon may have as manv as two 59 link-level write requests outstanding at any point in time. Terpsichore contains two such requester daemons which act concurrently to two different byte-channel and/or module addresses. Icarus Resppnder Daemon The Icarus Responder Daemon accepts writes from a specified byte-channel and module address, which enable an external device to generate transaction requests to read or write octlets or cache lines in the Terpsichore's local memory, or to generate Terpsichore events. The daemon also generates link-level writes to the same external device to communicate the responses to these transaction requests back to the external device. Terpsichore contains two such responder daemons which act concurrently to two different byte-channel and/or module addresses. An external device takes the role of the Transaction Requester, and the Icarus Responder takes the role of the Transaction Responder. Icarus Transponder Daemon The Icarus Transponder Daemon accepts writes from a specified Hermes channel and module address, which enable an external device to cause an Icarus Requester Daemon to generate a request on another Hermes channel and module address. Terpsichore contains two such transponder daemons which act concurrently (back-to-back) between two different byte-channel and/or module addresses. ' 8 The term "sequence number" is avoided here, because the transaction-tags are not necessarily sequential in nature 59 The number of link-level requests to be outstanding is still under study Icarus Request The rollowing table summarizes the commands used for Icarus requests and responses (response command shown :n bold) : Icarus Recuest commanαs A remote {add.swap.or.and} octlet request is data of the form: 63 address bytes 0..7 64 A remote read incoherent (strong, weakl cache-line request is data of the form: 63 0 I address I 64 A remote read coherent {strong.weak) cache-line request is data of the form: 63 0 address coherence tag 64 A remote write incoherent cache-line r es: is data of the form: 53 A remote write coherent cache-line request is data of the form: 53 A remote read (allocate.noallocate) {strong.weaki octlet request is data of the form: 63 0 | address | A remote write (allocate,noallocatei {strong.weaki octlet request is data of the form: 63 0 address bytes 0..7 A remote read {allocate. noallocate .rong.weakl hexlet request is data of the form: address A remote write (allocate.noallocate! {strong.weaki hexlet request is data of the torm: 63 o address bytes 0..7 bytes 8..15 Icarus Indication An Icarus Indication consists of a link-level write-response packet for each link- level write issued as an Icarus Request. Each link-level write-response packet contains the lid value of the link-level wπte-request packet. This serves both the link-level purpose of issuing a response and the ability to receive additional link- level requests and a transaction-level indication of receipt of the request and the ability to receive additional transaction-level requests. Icarus Resppnse Icarus Responses consist of a series of one or more link-level write-octlet operations. The low-order bits of the addresses of the write operations contain commands and tid information, and the data is the contents read from memory. The octlet stream contains transaction-level responses from the Terpsichore Responder daemon, which are summarized in the table below: Icarus Resoonse codes The c o m field contains an S-bit message command, as given in the table previously. The tid field contains the 8-bιt transaction :d code used in the request message. The node field contains the 16-bit processor number used in the request message. A remote iread.add.≤wapi octlet response .s data of the form: 63 0 bytes 0..7 A remote read hexlet response is data or the form: 63 bytes 0..7 bytes 8..15 A remote read incoherent cache-line response is data of the form: 63 64 A remote write response is data of the form: A remote read coherent cache line response is data ot the torm 63 0 A remote write coherent cache-line response is data ot the torm 63 coherence tag Icarus Confirmation An Icarus Confirmation consists ot a link-level write-response packet for each link-level write issued as an Icarus Response Each link-level write-response packet contains the lid value of the link-level wnte-request packet This serves both the link-level purpose of issuing a response and indicating the abilitv to receive additional link-level requests and a transaction-level confirmation ot receipt of the response and the ability to receive additional transaction-le el requests Deadlock The Icarus Requester, Responder, and Transponder daemons must act cooperatively to avoid deadlock that may arise due to an imbalance of requests in the system which prevent responses from being routed to their destination The requirements vary depending upon the characteristics of the svstem configuration, and the mechanisms for deadlock avoidance are still under study Principal mechanisms to emplov are cycle-free-routing of requests, and the means to prioritize responses above requests in forwarding priority Error handling The link-level packets contain a check bvte which is designed to detect single-bit transmisstion errors in the Hermes channel When either partv in an Icarus transaction receives a packet with a check error, it immediately shuts down input processing to av oid encountering further errors, as mav arise from errors which disrupt the parsing of packets It also generates an error packet, which ensures that the other partv is notified of the error The target of an Icarus transaction must maintain a copy ot the link-level address of the most recent correctlv received link-level write operation in a Cerberus reg'ster Terpsichore then will clear the error using the Cerberus channel, resetting the Hermes input processing Each party then re-issues any outstanding link-level transactions The contents of the address field m the link-level protocol is used to ensure that the error handling mechanism does not result in missing or repeated operations This is important, because unlike the link-level protocol, the transaction-level protocol contains non-idempotent operations Appendices Fixed-point Applications — - ir - i Q_γr- nr' r Cne The following example performs a ' find most-significant one " operation on general register ra. placing the result in general register rb E ALMS rb ra - ro Least-signr cant C e The following example performs a " find least-significant one" operation on general register ra, placing the result in general register rb E ADDI rb ra - 1 E ANDN rb rb 'a E ALMS rb rb Floating-point Applications The following example demonstrates the inner loop of the Linpack benchmark This section is under construction. Digital Signal Processing Applications This section is under construction. Image Processing Applications The following examples demonstrate several applications, listed below in summary form with the performance estimated. The estimates assume single-cycle loads and stores, that is, they do not account for losses due to cache misses. However, the memory reference patterns are very uniform, and with prefetching, they could be kept invisible. Hiterra of Monochrome ' ace Assume operands are 8 bits in size, which implies 16 pixels in a hexlet., 8 pixels in an octlet. We use a 3x3 linear filter. The coefficients are: kOO kOl k02 < j klO kl l kl2 [ k20 k21 k22 J No special handling on array boundaries are shown here, as it should have little effect on performance. A C version of the code is given below: void MonochromeFilter(ιnt8 "src, ιnt8 * dst. int row. int pcount, intβ kOO. ιnt8 k01. ιnt8 k02. intδ k10. intδ k1 1 , ιnt8 k12 intδ k20. intδ k21 , intδ k22) { fcr (ι=0. ι'=pcount: ι++) j dst[ι] = (src[ι-row-1]"k00 -r srcfι-rcw]"k01 + src[ι-row+ 1 ]"k02 + src[ι-1] * k10 + src[ι]'k1 1 + src[ι+1] * k12 + src[l+row-1 ]"k20 + src[i+row] * k21 + src[ι+row+ 1 ]"k22)>>8. We now examine the assembler coding of the inner loop. Because there are eight pixels in an octlet, the input size of the multiplier, this loop filters eight pixels at once. The coefficients are placed in 9 registers symbolically named k00..k22, with a copy of coefficient in each byte of the register. We assume that the coefficients are scaled so that sum of products do not overflow a 16-bit integer accumulation, specifically, the sum of the absolute values of the coefficients <= 256. The row size is in the register symbolically named row. Registers 8, 9, and 10 contain array pointers. 1 Note that our design actually loads each pixel nine times, which is making good use of "excess" load bandwidth and data caching. Filtehng of Color image For a color image, we assume that the image is made up of pixels each 32 bits in size, 8 bits for each of red, green, blue, and alpha. We treat each component identically, so the same algorithm is used, but the offsets change slightly. A C version of the code is: void ColcrFιlter(ιnt8 * src. intδ "dst. int row int pcount. intδ kOO. intβ k01 , intβ k02. intβ k10, intδ kl 1. ιnt8 kl2, intβ k20. intδ k21. intβ k22) { for (ι=0. ι'=4 * pcount: ι++) ( dst[ι] = (src[ι-row-4] * k00 + src[ι-row]"k01 + src[ι-row+4]'k02 + src[ι-4]'k10 + src[ι]'k1 1 + src[ι+4) * k12 + src[ι+row-4] * k20 + src[ι+row] * k21 + src[ι+row+4] * k22)»8, The assembler coding of the inner loop is: This uses the same algorithm as for the color image above. Operations are performed at the same rate, but since a pixel is represented by 32 bits, the pixel rate is four times slower. The inner loop runs at 10 cycles per 2 pixels, or 0.2 pixels/cycle. Ccnve sιon of Monocn pme ~~ Color To convert a monochrome image to a color image, we must triplicate each monochrome pixel level, into levels for red. green, and blue. The alpha level might be set to a constant level of 255, or merged in from a separate array. void MonochromeToColor(ιntβ * src. intβ "dst mt pcount) j for (ι=0 ι'=pcount, ι++) { dst[ι] = srcfj], dst[4 * ι+ 1] = src[ι], dst[4-ι+2]= src[ι], dst[4 * ι+3] = 255. Which results in the following inner loop (addressing operations and loop overhead omitted - they do not influence the operation count): #r5 contains -1 The above sequence is 4 cycles per 8 pixels, or 2.0 pixels/cycle. void Monoc romeWιthAlp aToColor(ιnt8 "src mtδ "alpna, intδ * dst int pcount) mt i. for ( Which results in the following inner loon- The above sequence is 4 cycles per 8 pixels, or 2.0 pixels/cycle. To convert a color image to a monochrome image, a weighted sum of the red. green and blue components is generated. These weights. kO. kl , and k2, are selected so that k0+kl4-k2 = 256, so overflow does not occur. The resulting weighted sum is truncated, rather than rounded, again, to avoid the possibility of overflow. void CoiorToMonoc rome(ιnt8 * src. intδ "cs; mt pcount. intδ kO. intδ k1. intδ k2) { for (ι=0. ι'=pcount: ι++) ( dst[ι] = (src[4 * ι]"k0 + src[4"ι+l ]-ki src[4'ι+2] * k2)>>8. Which results in the following inner loop: #k0k1...k0k1 k200...k200 #k0k1 ...k0k1 k200...k200 #k0k0 ..kOkOklkl ..kl k1 #k2k2.. k2k20000...0000 #toss away low precision The above sequence is 8 cycles and writes 8 pixels, or 1.0 pixels/cycle. for (i=0. i!=p dstfi] = aipha[i] Which results in the following inner loop: LJ28 r2.0(r8) G.DEAL16 r2.r2.r3 I 28 r4J6(r8) #k0kl ...k0k1k200...k200 G.DEAL16 r6.r4.r5 G.DEAL8 r2.r2.r6 #k0k1...k0k1k200...k200 G.DEAL.8 r4.r3.r7 #k0k0...k0k0k1kl ...klkl S.64 r5.0(r10) #k2k2...k2k20000...0000 G.MUL.8 r6.r2.k0 G.MULADD.8 r6.r3.k1.r6 G.MULADD.8 r6.r4.k2.r6 G.CO PRESSJ6 r6.r6.8 S.64 #toss away low precision r6.0(r9) A.ADD r8.32 A.ADD r9.8 A.ADD M0.8 B.NE r β .MOJb The above sequence is 8 cycles and writes 8 pixels, or 1.0 pixels/cycle. ^aoe Warning Image warping is the general process oi selectively stretching and shrinking an image to make it appear to tit into a new shape, such as stretched around a sphere, or drawn on a surface that is tilted with respect to the viewing surface A principal data structure used to generate such an effect is a set of decimated copies of the image, as shown in the diagram below These are of particular value because interpolation of the elements of these copies produces a properly antiahased spatially-warped image. Note that the total size of this structure is alvvavs exactly four times larger than the original image Each subarray is a copy of the image decimated in either the x or y direction, or both. The images get smaller and smaller going right and down in the array, until the image reaches a single dot The original image need not be square or have sizes that are powers of two for this structure. In the sections below, we explore two parts of the problem, the creation of the array containing this decimated image, and the an ialiased selection of items in the table. These are the parts of the process which must be performed in real time for O 97/07450 real-time application of this process, the creation of the warping maps can often be precomputed, and are a function of the rendering system used. • ' : on o orcc" The process of generating the decimated images above can be divided into two parts, decimating in the horizontal direction only, and decimating in the vertical direction only. The former generates all the blocks to the right oi the original image, and the latter generates the remaining blocks from those in the top row. This divides the problem into two parts, each using one-dimensional filtering, which is a great advantage because the amount of computation grows only linearly with the size of the filter function, rather than quadratically, when using two- dimensional filtering. Our first example is the one-dimensional horizontal filter. We use a -point filter, specified by coefficients k0..k4 to specify the filter. These weights. k0..k4, are selected so that k0+kl-fk2+k3+k4 = 256, so overflow does not occur. The resulting weighted sum is truncated, rather than rounded, again, to avoid the possibility of overflow void HoπzontalDecιmatιoπMonocr,rcrr,e(ιn:8 "src mt 8 "dst. irt srcw mt drew mt pcount ιnt8 kO intβ k1. ιnt8 k2 ιnt8 k3 intS k4) ( for (k I ι+ = srow-drow-drow Which results in the following inner loop: This inner loop is 9 cycles per 8 pixels, or 0.9 Gpixels/sec, when the filter kernel size is 5 pixels wide. (For 3 pixels wide, the rate is 6 cycles per 8 pixels, or 1 3 pixels/cycle.) When decimating in the vertical direction, the rate is even higher still: void VertιcalDεcιmatιcnMcnochromeι mt3 * sre , πt 3 * dst mt srow mt drow t pcount ιnt8 kO intδ kl mtδ k2 π:8 -O mt3 K4) ( mt i ] k. fcr (k=0 ,=0. k' =pcount. ) ( f cr (j=0 |' = drow |-t-->.) { dstfk-r-] = (srci ι-2 * ≤'Cw]'kC - 5rc[ι-srow] * k 1 + src[ι] * k2 -r src[ι+srcΛ J 3 - src[ -2"srcwj * k4 )>>8 ι + + I I Which results in the following inner loop- This runs in 6 cycles per 8 pixels, or 1.3 pixels/cycle. (For 3 pixels wide, the rate is 4 cycles per 8 pixels, or 2 pixels/cycle.) To generate the decimated array shown above, for a n^ image, n^ pixels are generated in the horizontal direction, and 2n^ pixels are generated in the vertical direction. Using 5 pixel filter functions, this takes: n2 /0.9 + 2n2 /1.3 = n2*(l/0.9+2/1.3) = 2.63*n^ cycles. Thus, a 1024^ image can be decimated in 2.8 Mcycles. It is also possible to simultaneously decimate in the vertical and horizontal direction. While this may be more expensive that separately decimating in each direction, it permits the use of filter functions which do not factor into two parts. For this example, we assume a 2: 1 decimation rate in each direction, and a 3x3 filter kernel. Real applications of decimation may use larger filter kernels, but this size serves to illustrate the techniques used. We assume here that pcount is a multiple of drow, and that drow<srow/2.. void DecιmateMonochrome(ιnt8 "src int 8 "dst. int srow. mt drow. mt pcount, intδ kOO. intδ k01 , int β k02. -2"(src.v-drow) Assembler code for inner loop: 1 A SUB r2 δ. srow L 123 r6.- 1 (r2) G DEAL 3 r6 r6.r7 G M UL 3 r4 r6.k00 G MULADD 8 r4 r7 k01 r4 L 128 r6. 1 (r2) G DEAL 8 r6.r6.r7 G MULADD 8 r4. r6.k02.r4 L 128 r6.- 1 (rβ) G DEAL 8 r6. r6.r7 G MULADD.8 r4.r6.k10 r4 G MULADD 8 r4.r7.k 1 1 .r4 4 L 128 r6.-1 (r2) G. DEAL 8 r6.r6.r7 G MULADD.8 r4.r6.k00. r4 G MULADD.8 r4.r7.k01 .r4 L 128 r6J (r2) G DEAL.8 r6.r6.r7 G MULADD.8 r4.r6.k02.r4 G. COMPRESS.16 r4,r4.6 S.64 r4,0(r9) A.ADD r8J 6 A.ADD r9,8 B NE r8.r10.1 b After some reordering of the address calculation instructions, the inner loop is 16 cycles per 8 pixels, or 0.5 pixels/cycle. Note that for 2:1 decimation in each direction, this is 4 times larger when expressed in terms of the input pixel rate: 2.0 pixels/cycle. Because the filter function is an odd-number of pixels wide, 1/4 of the multiply bandwidth is effectively unused. For a 5x5 filter function, this would drop to 1/6 unused, and for an even number of pixels wide, none would be wasted. Compared to the two-dimensional filtering case, the multiplier bandwidth is less utilized because the index multiplier required the additional DEAL operations to be added. Our first example is the one-dimensional horizontal filter We use a 5 -point filter, specified by coefficients k0..k4 to specify the filter These weights. k0..k4. are selected so that k0-kl-k2-k3-k4 = 256. so overflow does not occur. The resulting weighted sum is truncated, rather than rounded, again, to avoid the possibility of overflow. vcic Hcriz πtaiDecimationColcrnntS 'src r: 3 'dst mt src.v mt drow int pccunt ir.tS kC mtδ k1 intβ k2 m;S k3 n:5 k4) j mt ι j.k dst[k-^-j = (src[ι-8] * k0 - sreJ4]'k1 + srcfι] * k2 + src[ι+4]'k3 -<- s.Aι ' -3] * k4 )»8. ' ι + + 3St[k+*] = (src[ι-8] * k0 *•- sre>4]- 1 + src[ι] * k2 + src[ι+4]"k3 + src[.-3] * k4 )>>3. ι + + dst[k+ + ] = (src[ι-8] * k0 + srcι ι-4]'k1 + src[ι] * k2 + src[ι+4]'k3 T sre[:-3] * k4 )>>8 ' iτ=5. I ι +=4 * (srow+srow-drow-drow) Which results in the following inner loop: This inner loop is 9 cycles per 2 pixels, or 0.2 pixels/cycle, when the filter kernel size is 5 pixels wide. (For 3 pixels wide, the rate is 6 cycles per 2 pixels, or 0.3 pixels/cycle.) When decimating in the vertical direction, the rate is even higher still: void VertιcalDecιmatιonColor(ιnt8 "src. int 8 * dst. t srow. t drow, mt pcount. intβ kO. intδ k1. intδ k2. intδ k3. intδ k4) { πt i j k Or (k=C ι=3 k ' =pccunt ) { for (j=C ] ' =4 * θrow jτ- ' ι ds.[k-->-] = (src[,-3 "sre .-. j"--C - src[i-i'srow "k * T src[,] * k2 T src[ι+4 * 3ro'.v;'k3 - 3rc[ι+3"s r cw]"k4 )>>6 ' 1 + τ ι- =4'( 5,-e .vτsrcw-dro' ι Which results in the following inner loop 1 A SUB r2 rS -owtS L 64 r3 0f r2) G MUL 3 r4 r3 kO A SUB r2 ,'S rc .vt-i L 64 r3 0(r2) G MULADD 8 r4 r3 k l r4 L 64 r3 Of 'S) G MULADD 3 r4 r3 k2 '4 A ADD r2 --8 'C .vt4 L 64 r3 0(r2) G MULADD 8 r4 r3 k3 r4 A ADD r2.r8 rowtβ L 64 r3.0(r2 G MULADD 8 r4 r3 k4 4 This runs in 6 cycles per 2 pixels, or 0.3 pixels/cycle. (For 3 pixels wide, the rate is 4 cycles per 2 pixels, or 0.5 pixels/cycle.) To generate the decimated array shown above, for a n^ image, n^ pixels are generated in the horizontal direction, and 2n^ pixels are generated in the vertical direction. Using 5 pixel filter functions, this takes: n^/0.2 -*- 2nAθ.3 = n2p 1/0.2+2/0.3) = 10.5*n2 cycles. Thus, a 1024^ image can be decimated in 11 Mcycles. The last example in this section decimates a color signal in both directions simultaneously. We assume a 2:1 decimation rate in each direction, and a 3x3 filter kernel. Real applications of decimation may use larger filter kernels, but this size serves to illustrate the techniques used. We assume here that pcount is a multiple of drow, and that drow<srow/2.. void DecιmateColor(ιnt8 * src. int δ * dst. mt srow t drow, int pcount. intβ kOO, intβ k01 , intβ k02. intβ k10. intβ k1 1 , intβ k12. ιntδ k20. ιnt8 k21 , intδ k22) { + src[ι-4'srow+4]"k02 + src[ι-4 ' 3rθ'.v-4]- 20 - 3re: ι-r4 * srowl * k21 - src ι-4 * 3,-c.vτ4] * k22)>>8. ι + * i - src[ι-4'srcw-4;'kG2 + src(ι -4 * srcv~ij" 22)> >8 l T src[ι«--'3rcw— ι] * k02 + src[i τ4 * srcvτ.ι] * k22.>>8. 1 + src[ι-4'3rowτ4] * kC2 + src[ι+4 * 3rcv-4]'k22)>>3. I ι + = 4 * (srow+srow-drcw-drcw) Assembler code for inner loop: After some reordering of the address calculation instructions, the inner loop is 16 cycles per 2 pixels, or 0J2 pixels/cycle. Fractional Interpolation This section is under construction. Image Compression A pp lications The following examples demonstrate kev portions oi JPEG and MPEG image compression applications. Both JPEG and MPEG applications rely on the use of a 2-dimensιonal Discrete Cosine Transform (DCT) to transform raster-image data into a frequency-based representation that is more amenable to entropy coding. The following examples demonstrate several applications, listed below in summary form with the performance estimated. The estimates assume single-cycle loads and stores, that is. they do not account for losses due to cache misses. However, the memory reference patterns are very uniform, and with prefetching, they could be kept invisible. Internal 8x8 Matrix Transopse A 2 -dimensional DCT can be performed on an 8-by-8 matrix of data by doing a series of 1 -dimensional DCTs on each of the 8 rows of the matrix, and on each of the 8 columns of the matrix. A useful means to implement these operations is to perform a DCT on the rows (or columns) of the matrix, transpose the matrix, then perform a second, identical DCT, then transport the matrix again. This example details the transposition of an 8-by-8 matrix of 16-bit values, stored consecutively in memory. The calculation is performed entirely in registers, using G. SHUFFLE instructions and a technique described in 60 , in which the first and second halves of the matrix are shuffled Iog2N times. Assume the matrix originally is in the order: 60 Scone. Harold. "Parallel Processing with the Perfect Shuffle." IEEE Transactions on Computers. Vol C-20. No. 2, February 1971. 153 After one shuffling, the matrix is in the order: After a second shuffling, the matrix is in the order: C code for procedure: void * src. int 16 "dst) { for (ι=0; i<32; i++) { tm0[2 * ι] = srcfij; tm0[2 * ι+1] = src[ι+32], ' for (i=0: i<32; i++) { tm1[2 * i] = tmO[ι], tml[2 * ι+1] = tm0[ι+32]: for (i=0; i<32; i++) { dst[2"ι] = tm1 [ι]; dst[2 * ι+1 ] = tm1[ι+32], I Assembler code for procedure: # 00 01 02 03 04 05 06 07 # 32 33 34 35 36 37 38 39 # 00 32 01 33 02 34 03 35 # 08 09 10 11 12 13 14 15 # 04 36 05 37 06 38 07 39 # 40 41 42 43 44 45 46 47 # 08 40 09 41 10 42 1 1 43 # 16 17 18 19 20 21 22 23 G SHUFFLE 3 ■ Of- =* 124413 514461547 L 123 I re '29c =43495051 525354 G SHUFFLE 3 r 2S -3 "6 # 1648174918501951 L 123 I r'C '2- i : = 2425252 7 28293031 G SHUFFLE 3 -3C r9 ''7 * 205221 5322542355 L 128 I r:S '2 l"2 = 565 7 535960616263 G SHUFFLE 3 r32 rlC '13 # 2456255726582759 G SHUFFLE 3 r3 * ι ." 0 =28602961 306231 63 G SHUFFLE 8 r4 '23 '23 =0016324801 173349 G SHUFFLE 3 r6 r2l 29 # 0213345003193551 G SHUFFLE 8 r3 '22 '3C ≠ 0420365205213753 G SHUFFLE 3 πc '23 '31 40622385407233955 G SHUFFLE 8 π 2 ,'2 '32 = 0824405609254157 G SHUFFLE 3 r 14 r25 r33 * 1026425811274359 G SHUFFLE 3 r16 r26 '34 s- 1228446013294561 G SHUFFLE 8 M8 '27r3Ξ * 1430466215314763 G SHUFFLE 3 r2G ,' n2 * 0008162432404856 S 128 I r20.'3 J G SHUFFLE 3 r22 '5 -"3 # 0109172533414957 S 123 I r22 '3 '6 G SHUFFLE 3 r2 -6 '1 40210182634425058 S 12SI r24 r3.32 G SHUFFLE 8 r26r7.r15 40311 192735435159 S 128 I r26 r348 G. SHUFFLE 8 r28 r β r16 40412202836445260 S 128 I r28 r36 G SHUFFLE 8 r30.r9r17 #0513212937455361 S 128 I r30 r380 G SHUFFLE.8 r32 r10 r1δ #0614223038465462 S.128I r32.r3.96 G SHUFFLE.8 r34.r11 r19 #0715233139475563 S 128 I r34 r3112 B rO The resulting code transposes an 8-by-S matrix using 25 cycles. 1 -Dimensional Discrete Cosme Transform The following code is based upon the Independent JPEG Group's software "jfwddct.c" 61 , using 16-bit multiplies generating a 32-bit result. #ιnclude "jinclude h" #defιne RIGHT_SHIFT(x.shft) ((x) » (shft)) #defιne LG2_DCT_SCALE 15 / * lose a little precision to avoid overflow 7 #defιne ONE ((INT32) 1) #defιne DCT_SCALE (ONE « LG2_DCT_SCALE) / * In some places we shift the inputs left by a couple more bits, 7 / * so that they can be added to fractional results without too much 7 / * loss of precision 7 #defιne LG2_OVERSCALE 2 #defιne OVERSCALE (ONE << LG2.0VERSCALE) #defιne OVERSHIFT(x) ((x) <<= LG2_OVERSCALE) 61 Copyπght (C) 1991. Thomas G Lane. * Scale a fractional constant ov DCT_SCALΞ ' s fssf.ne FlX(x) ((INT32) ((x) ' DCT_SCALE - Z 5ι) • Scale a fractional constant oy CCT_SCAL≡. OVERSCALE '. " S cn a constant can be muiticlied witn an cverscalea input 7 * tc produce sometmng that 3 scaled by DCT SCALE * / =-ce':re FIXO(x) ((INT32) ((x) ' DCT_SCALE , OVERSCALE + 0.5)) " Descale and correctly round a v=:ue that s scaled by DCT SCALE 7 =αe'me UNFIX(x) RlGHT_SHIFT( xι T (ONE << (LG2_DCT_SCALE-1 )). LG2_DCT_SCALE) . '• Same with an adαiticnal division ov 2. ιe correctly rounded UNFIX(x/2) "/ •define UNFIXH(x) RlGHT_SHIFT((x)P ,'CNE << LG2_DCT_SCALE), LG2_DCT_SCALE- l ) " Take a value scaled by DCT_SCALE and round to integer scaled by OVERSCALE 7 ♦define UNFIXO(x) RlGHT_SHIFT((x) + (ONE << (LG2_DCT_SCALE- 1 -LG2 OVERSCALE;) ' LG2_DCT_SCALE-LG2_OVERSCALE) /' Here are the constants we neeα "/ ,' * SIN J is sine of rpι/j. scaleα by CCT_SCALE 7 , " COSj is cosine of ι * pι/j. scaled cy DCT_3CALE 7 #de f me SIN_1_4 FIX(0.707106781 ) #defme COS_1_4 SIN_1_4 #defιne SIN_1_8 FIX(0.382683432) #defιne COS_1_8 FIX(0.923379533) #defιne SIN_3_8 C0S_1_8 #defme C0S_3_8 SIN_1_8 #defιne SIN_1_16 FIX(0.195090322) #defιne COS_1_16 FIX(0.9δ07δ5280) #defme SIN_7_16 COS_1_16 #defme COS_7_16 SIN_1_16 #defιne SIN_3 16 FIX(0.555570233) #defιne COS_3_16 FIX(0.831469612) #defιne SIN 5_16 COS_3 16 #defme COS_5_16 SIN_3_16 / * OSIN J is sine of ι'pi/j, scaled by DCT_SCALE/OVERSCALE 7 / * OCOS J is cosine of ι * pi/j, scaled by DCT.SCALE/OVERSCALE 7 #defιne OSlN_1_4 FIXO(0.707106781 ) #defιne OCOS_1_4 OSIN_1_4 #define OSIN_1 8 FIXO(0.382683432) #defιne OCOS_1_δ FlXO(0.923β79533) #define OSIN_3_8 OCOS_1_δ #defιne OCOS_3_δ 0SIN_1_8 #defιne OSIN 1 16 FIXO(0.195090322) #defιne OCOS 1_16 FIXO(0.980785280) #defιne OSIN_7 16 0C0S_1_16 #defιne 0C0S_7_16 OSINJ 6 #defιne OSIN_3_16 FIXO(0.555570233) ■ aeUne OCCS_3_1 o FIXOfC 3314636 2 ι ≠de'me 0SIN_5_16 0C0S_3_16 fdefine OCOS_5_16 0SIN_3_16 " Perform a 1 -dimensional DCT * Note trat this ceαe is speciahzeσ :c is CCTSiΣE = 8 INLINE LOCAL void fast oc:_3 (DCTELEM 'm mt stride) ! ," many tmps have ncnoverlaoDiπg lifetime - -iashy registe' colourers * should be able to do this lot very well 7 INT16 inO. in 1. ιn2. ιn3 ιn4. ιn5 mo ιn7 INT16 tmpO tmp 1 , tmp2. tmp3. tmo4. tmcc tmoό tmo7 INT16 tmp10. tmp l l , tmp12. tmpl 3 INT16 tmp14 tmpl5. tmp16. tmDl7 INT 16 tmp25. tmp26. ], J. j. J: J: j; tmp5 = ιn2 - ιn5. tmoδ = ιn 1 - ιn6: tmp7 = inO - in7. tmplO = tmp3 + tmpO: tmp11 = tmp2 + tmp1; tmp12 = tmpi - tmp2; tmpl3 = tmpO - tmp3; ιn[ OJ « (DCTELEM) UNFIXH((tmp10 + tmpi 1) " SIN_1_4), ιn[stπde * 4j = (DCTELEM) UNFIXH((tmp10 - tmp11) * COS_1_4); ιn[strιde * 2J = (DCTELEM) UNFIXH(tmp13 * COS_1_3 + tmp12 * SIN_1_8): ιn[strιde * 6J = (DCTELEM) UNFIXH(tmpl3 * SIN_1_8 - tmp12 * COS_1_8), tmpl6 = UNFIXO((tmp6 + tmp5) * SIN_1_4). tmp15 = UNFIXO((tmp6 - tmp5) * COS_1_4). OVERSHIFT(tmp4), OVERSHIFT(tmp7). :mp4 tmc7 tmp l 5. tmp 16 are cverscaieo cy OVERSCALE 7 -p iα = tmD + tmp15. ~o25 = tmp4 - tmp15. -.026 = tmD7 - tmDl 6. -017 = tmp7 -r tmp16. • fstr.de ] = (DCTELEM) UNFIXHι ' :rrol 7'CCCSj J6 + tmp 14"OSIN_1_16) - strιce'7] = (DCTELEM) UNFIXhf:mp l 7'OCOS_7 16 - tmp 14'OSIN 7 16) ■ rstπde'S] = (DCTELEM) UNF!Xhcmc26'CCOS 5_16 + tmo25'OSIN 5 16). Pstπde-3] = (DCTELEM) UNFIXH(:mc26'OCOS_3_l6 - tmc25'OSIN_3J6): Perform the forward DCT on one block ef samples A 2-D DCT can be done by 1 -D DCT on eacn row 'ciic.ved by 1 -D DCT on each column GLOBAL void jj.va.αct (DCTBLOCK data) { mt ι. fcr (i = 0: ι < DCTSIZE: ι++) fast_dct_8(data+ι'DCTSIZE. 1 ). for (ι = 0: ι < DCTSIZE: i++) fast_dct_8(data+i, DCTSIZE); I The assembler code for the above procedure, called with stride=8, is as follows: '44 ,-44 -4g -£ r -i -2 : r 8 r36 r3Ξ - :mρ ' r44 r4 = SCOS_ _- -> :2763 '46 r49 SCCS_ _-• 5. =276 = r^4 ,-4.1 ,-4c 16 r44 r254 = mfstrιde'4j = r44 ,-42 SC0S_i_5332~68 r46 r43 SC03_1_3332763 r44 ,-40 SSIN_ _3.'44 r46 r41 5SIN_1_3 r46 r44,r44 r46 16 r44 r2.32 # ιn[stπde'2j = r44 r4 SSIN 1 8332768 r46 43 SSIN_1_8.332763 r4 r40 S-CGS_1_8 , r44 r46 r41 S-COS_1_3.r46 r44.r44 r46 16 r44.r2.96 4 ιπ[strιde'6j = r48.r32.r3C 4 = tmp6 -r tmp5 r44 r4β.SSIN_1_434096 r46 r493SIN_1_434096 r44 r44 r4c 14 4 tmDl6 = r48 r32.r30 4 = tmo6 - tmp5 r46.r48.SCOS_1 4 $4096 r48.r49.SCOSj_4.34096 r46.r46.r46 14 # tmpl5 = r28.r28,2 0VERSHIFT(tmp4) r34.r34.2 0VERSHIFT(tmp7) r48.r28.r46 tmp14 = tmp4 + tmp15. r50.r28.r46 tmp25 = tmp4 - tmp15. r52.r34,r44 tmp26 = tmp7 - tmp16. r54,r34.r44 tmp17 = tmp7 + tmp16 r44.r54.SOCOS_1 16,332768 r46.r55.SOCOS_1_16.S32763 r44,r48.SOSlNj 16.r44 r46.r49.SOSINJJ6.r46 r44.r44.r46.16 r44.r2J6 # infstπde] = r44 , r54.$OCOS_7 16.S32768 r46 , r55.SOCOS_7 16,532766 r44.r48.S-0SIN 7 16,r44 r46.r49.$-OSlN_7_16.r46 r44.r44,r46J6 r44.r2J12 # in[stπde * 7] = r44 , r52.SOCOS_5 16.S32768 r46.r53.SOCOS_5_16.S32768 r44.r50.$OSIN_5 16,r44 r46.r51.$OSIN_5_16.r46 r44,r44.r46J6 r44.r2.80 # ιn[strιde * 5j = r44.r52.$OCOS 3J6.S32768 r46 , r53.$OCOS_3 16.S32763 r44.r50.S-OSIN_3 16.r44 r46.r51.S-OSIN_3_16.r46 r44.r44.r46.16 r44.r2.48 # ιn[stπde'3J = rO The above code uses 10 G ADD 10 G SUB 32 G MULADD. 10 G EXTRACT I. and 2 G SHL instructions, which can be scheduled in 64 cycles This code performs 8 1 -dimensional DCTs at once, so it can be described as performing at 64-'64 = 1 0 cycles/pixel. The code for a 2 -dimensional DCT. uses the 1 -dimensional DCT above, an 8x8 transform, a second 1-dιmensιonal DCT, and a second 1 -dιmensιonal DCT The load and store operations which are performed between these steps can be eliminated by procedure miming, so we can estimate the performance by counting the Group instructions alone, which total to 2 " 64-r2 " 24 or 176 cvcles The 2- dimensional DCT covers 64 pixels, which works out to a rate of '2.8 cycles/pixel An inverse DCT should have simdar performance characteristics. The DCT can also be performed using half-precision ( 16-bit) floating-point operations In this case, the accumulation of intermediate terms is performed using half-precision floating-point, so 50% of the G. MULADD instructions and 100% of the G.SHL and G.EXTRACT.I instructions can be removed Also, 10 of the G.MULADD operations become simple G.MUL. Thus 8 1 -Dimensional DCTs would use 10 GF.ADD, 10 GF.SUB, 10 GF.MUL, 3 GF.MULADD, 3 GF MULSUB instructions, using 36 cycles, or 0.6 cycles/pixel, and the 2-dιmensιonal 8x8 DCT uses 2 " 36+2 " " " 24 = 120 cycles, or 1.9 cycles/pixel. An inverse DCT should have similar performance characteristics. Furthe r enhancements whe used in JPEG alαonthm Because the output of the DCT is scanned into a linear sequence of items, the final transpose operation can easily be eliminated. This reduces the fixed-point DCT cost to 2"64+24 = 152 cycles, or 2.4 cycles/pixel; the floating-point DCT cost is reducted to 2 " 36+24 = 96 cycles, or 1.5 cycles/pixel. The following section demonstrates that die transpose cost can be reduced to 16 cycles, by using a combination of memory loads and stores and the G. SHUFFLE operations, producing a fixed-point DCT in 2 " 64 + 16 = 144 cycles, or 2.3 cycles/pixel and floating-point DCT in 2 "36 + 16 = 88 cycles, or 1.4 cycles/pixel. Other Matrix Applications Internal 4χΛ Matrix Transopse This example details the transposition of a 4-by-4 matrix of 16-bit values, stored consecutively in memory. The calculation is performed entirely in registers, using G SHUFFLE instructions and a technique described in A in which the first and second halves of the matrix are shuffled lo-zA times Assume the matrix onginallv is in the order for (ι=0. ι<8. ι++) ( tm0[2 * ιj = srcfi], tm0f2"ι-1 ] = src[ι+δj for (ι=0 ι<8 ι++) { dst[2 * ι] = tmOfiJ, dst[2'ι- j = tm0[ι+8J I Assembler code for procedure: SuoMatπxTranspose L 128 I r4,r2,0 40001020304050607 L 128 I r6.r2J6 # 0809101112131415 G SHUFFLE 8 r8,r4,r6 #0008010902100311 G.SHUFFLE 8 r10,r5.r7 #0412051306140715 G SHUFFLE 8 r4,rδ,r10 # 0004081201050913 S 128 I r4,r3,0 G SHUFFLE δ r6.r9.r1 1 #0206101403071115 S 126 ! r6.r3J 6 B rO The resulting code transposes a 4-by-4 matrix using 5 cycles. 62 Stone, Harold, "Parallel Processing with the Perfect Shuffle." IEEE Transactions on Computers, Vol C-20, No 2. February 1971, 153 —xte^ 1 Mat χ ι "a^socse A large matrix mav not fit in the register rile all at once, and e en if it could, the internal matrix transpose algorithm pertorms O(XlogN). as each doubling of the matrix size requires an additional shurfle To support the transpose of a large matrix, the internal matrix transpose algorithm can be extended to transpose individual blocks, or sub-matrices, of a large matrix, by modifying the code to specify the row size oi of the matrix. 63 If we consider each element in the left matrix below to be an 8-bv-S submatπx as above, the transpose of the matrix is the right matrix below, where each element of the right matrix is the transpose of the corresponding element in the left matrix Note that elements 0, 9, 18, 27, 36. 45. 54. and 63 are transposed ln-place. and that each of the other elements are transposed and exchanged with another element in the matrix. Thus another useful extension of the submatπx transpose algorithm transposes two submatnces simultaneously, writing them back in exchanged locations. bA 0 1 2 3 4 5 6 7 0 8 16 24 32 40 48 56 8 9 10 11 12 13 14 15 1 9 17 25 33 41 49 57 16 17 18 19 20 21 22 23 2 10 18 26 34 42 50 58 24 25 26 27 28 29 30 31 3 11 19 27 35 43 51 59 32 33 34 35 36 37 38 39 4 12 20 28 36 44 52 60 40 41 42 43 44 45 46 47 5 13 21 29 37 45 53 61 48 49 50 51 52 53 54 55 6 14 22 30 38 46 54 62 56 57 58 59 60 61 62 63 J 7 15 23 31 39 47 55 63 A preceding section describes ho to transpose a 4x4 matrix, which can be easily extended to handle a 4x4 submatnx by splitting the L.128.1 and S 128 I instructions each into pairs of L.64.1 and S 64Ϊ instructions. The cost of the 4x4 transpose is less than 25% of the cost of the 8x8 transpose, so an external matrix transpose using the 4x4 submatnx can be faster than using the 8x8 submatnx transpose. Shaded Graphics Applications This section is under construction. Mnemosvne System Application MicroUnity's Terpsichore system architecture uses nine Mnemosyne memory devices in its base configuration, providing a nine byte-wide paths between the processor and memory. The memory devices are used to build a 0.5 Mbyte cache between Terpsichore's first level caches and DRAM-based main memory. The 63 Thιs modification uses A-type instructions to increment the src pointer bv the row size between each L instructions, taking no additional cvcles b For such a case, it is useful to use the indexed addressing form, so that the same index can be applied to the two pointers for the L and S instructions main memory store consists oi 9, IS or 36 banks of arrays (each bank is eighteen 4 Mbit DRAMs). which yields 64J2S or 256 Mbytes of ECC memory with 8J6. or 32 Mbvtes of director.- storage. To further expand the DRAM memory and improve the bandwidth to memory, two or four λϊnemosyne memory devices may be placed in each of the nine byte- wide paths. Such configurations use 18. 36, 72. or 144 banks of lMx72 arrays, which yields 128, 256, 512, or 1024 Mbytes of ECC memory with 16, 32, 64, or 128 Mbytes of directory storage. Mnemosyne provide sufficient address bits to support up to 16Mx72 DRAM array banks, using as large as 64M bit DRAM parts when available. In such a configuration, memory sizes as large as 16 Gbytes of ECC memory can be constructed. Terpsichore uses a 64-byte cache line size. Each cache line is associated with an ocdet (8 bytes) of directory information, using one of the nine "Hermes channels" provided by a Mnemosyne device with its associated DRAM. The remaining eight of the nine Hermes channels contain the eight octlets (eight byte units) of the cache line data. In order to provide the means to access individual ocdets of cache data and directory information at maximum bandwidth, the directory information is scattered evenly among eight of the nine byte lanes. Ty p ical Cerberus confourations The number of devices in a typical Cerberus bus may vary from a minimum of about 1 1 devices ι S Mnemosyne. 1 Terpsichore. 1 Calliope. 1 FPGA). to a moderate amount ot about 40 '36 Mnemosyne, 1 Terpsichore. 1 Calliope. 1 Hydra. 1 FPGA), or about 48 (36 Mnemosyne. 4 Terpsichore, 4 Calliope. 4 Hydra. 1 FPGAi to a maximum of about 157 devices ( 144 Mnemosvne. 4 Terpsichore. 4 Calliope. 4 Hydra, 1 FPGAi. When determining the performance ct Cerberus this 15: 1 variation m the number ot devices on the bus has a critical effect The performance oi these configurations with a resistive termination is estimated below: The use of a synchronous repeater, as described previously, would result in a significant performance increase in the Extended system.

Claims: WE CLAIM: 1. An execution unit that maintains substantially peak data throughput in the unified execution of multiple media data streams, the execution unit having a data path, comprising: a multi-precision arithmetic unit coupled to the data path, the multi- precision arithmetic unit capable of dynamic partitioning based on the elemental width of data received from the data path; a switch coupled to the data path and programmable to manipulate data received from the data path, the switch providing data streams to the data path; and an extended mathematical element coupled to the data path and programmable to implement additional mathematical operations at substantially peak data throughput. 2. The execution unit defined in claim 1, wherein the multi-precision execution unit is configurable to divide the data into component symbols of various sizes, analyze the component symbols based upon instructions, and re-synthesize the component symbols for communication over the data path. 3. The execution unit defined in claim 2, wherein the multi-precision execution unit is operable to perform unique operations on each component symbol. 4. The execution unit defined in claim 2, wherein the mathematical element is operable to perform finite group, finite field, finite ring and table look¬ up operations on the symbols. 5. The execution unit defined in claim 1, wherein the arithmetic unit is programmable to perform Boolean, integer and floating point mathematical operations. 6. The execution umt defined in claim 5, wherein the operations performed by the arithmetic unit are capable of being performed at various levels of precision. 7. The execution unit defined in claim 1 , wherein the manipulation of data comprises copying, shifting and re-sizing data. 8. The execution unit defined in claim 1, further comprising control to maximize use of the execution unit by performing operations at peak data width of the data path. 9. The execution unit defined in claim 2, wherein the size of component symbols match. 10. An execution unit having a data path, comprising: at least one register file coupled to the data path; a multi-precision arithmetic unit coupled to the data path, the multi- precision arithmetic unit capable of dynamic partitiomng based on the elemental width of data received from the data path; a switch coupled to the data path and programmable to manipulate data received from the data path, the switch providing data streams to the data path; and an extended mathematical element coupled to the data path and programmable to implement additional mathematical operations at substantially peak data throughput. 11. An execution unit having a data path, comprising: a multi-precision arithmetic unit coupled to the data path, the multi- precision arithmetic unit capable of dynamic partitioning based on the elemental width of data received from the data path; means coupled to the data path for manipulating data received from the data path, the means for manipulating data being programmable and providing a data signal to the data path; and an extended mathematical element coupled to the data path and programmable to implement additional mathematical operations at substantially peak data throughput. 12. A general purpose programmable media processor having an instruction path and a data path to digitally process a plurality of media data streams, comprising: a high bandwidth external interface operable to receive a plurality of data of various sizes from an external source and communicate the received data over the data path at a rate that maintains substantially peak operation of the media processor; at least one register file configurable to receive and store data from the data path and to communicate the stored data to the data path; and a multi-precision execution unit coupled to the data path, the multi- precision execution unit configurable to partition data received from the data path to account for the elemental symbol size of the plurality of media data streams, and programmable to operate on the data to generate a unified symbol output to the data path. 13. The media processor defined in claim 12, wherein the execution unit is dynamically configurable to partition data received from the data path. 14. The media processor defined in claim 12, further comprising: means for moving data between registers and memory by performing load and store operations, and for coordinating the sharing of data among a plurality of tasks by performing synchronization operations based upon instructions and data received by the execution unit; means for securely controlling the sequence of execution by performing branch and gateway operations based upon instructions and data received by the execution unit; and a memory management unit, the memory management unit operable to retrieve data and instructions for timely and secure communication over the data path and instruction path. 15. The media processor defined in claim 14, further comprising: a combined instruction cache and buffer, the combined instruction cache and buffer dynamically allocated between cache space and buffer space to ensure real-time execution of multiple media instruction streams; and a combined data cache and buffer, the combined data cache and buffer dynamically allocated between cache space and buffer space to ensure real¬ time response for multiple media data streams. 16. The media processor defined in claim 15, wherein real-time execution is ensured by dynamically allocating instruction buffer space to the smallest and most frequently executed blocks of media instructions. 17. The media processor defined in claim 15, wherein real-time response is ensured by dynamically allocating data buffer space to the smallest and most frequently accessed working sets of media data. 18. The media processor defined in claim 12, wherein media data streams comprise Nyquist sampled inputs and outputs. 19. The media processor defined in claim 12, wherein media data streams originate from standard computer memory and I/O interfaces. 20. The media processor defined in claim 12, wherein the multi- precision execution unit is configurable to divide the data into component symbols of various sizes, analyze the component symbols based Upon instructions, and re- synthesize the component symbols for communication over the data path. 21. The media processor defined in claim 12, wherein the plurality of media data streams comprise presentation media information, transmission media information, and storage media information. 22. The media processor defined in claim 21. wherein presentation media information comprises audio, video, image, and graphical information 23. The media processor defined in claim 21, wherein transmission media information comprises radio and network data transmissions;. 24. The media processor defined in claim 21, wherein storage media information comprises data encoded in moving and solid-state memory media. 25. The media processor defined in claim 12, wherein the width of the data path is at least 128 bits. 26. The media processor defined in claim 12, wherein the multi- precision execution unit comprises a dynamically partitionable arithmetic unit, a register controllable cross-bar switch, and an extended mathematical element. 27. The media processor defined in claim 24, wherein the register controllable cross-bar switch comprises a Benes network design. 28. The media processor defined in claim 26, wherein the register controllable cross-bar switch is programmable and is operable to manipulate symbols. 29. The media processor defined in claim 22. wherein the extended mathematical element is operable to perform finite group, fmite field, finite ring and table look-up operations on the symbols. 30. The media processor defined in claim 12, further comprising a set of predefined instructions accessible by a user. 31. The media processor defined in claim 13, wherein the means for performing load, store, and synchronization operations and the means for performing branch and gateway operations comprises a set of predefined instructions accessible by a user. 32. The media processor defined in claim 31, wherein the predefined instructions are combinable to implement composite functions on the plurality of media data streams. 33. A high bandwidth processor interface for receiving and transmitting a media stream, comprising: a data path, the data path operable to transmit media information at sustained peak rates; a plurality of memory controllers, the plurality of memory controllers coupled to the data path in series to communicate stored media information to and from the data path; and a plurality of memory elements coupled to each of the plurality of memory controllers in parallel, the plurality of memory elements for storing and retrieving the media information. 34. The high bandwidth processor interface defined in claim 33, wherein the data path comprises a plurality of data paths forming a high bandwidth data channel. 35. The high bandwidth processor interface defined in claim 34, wherein the high bandwidth data channel is uni-directional. 36. The high bandwidth processor interface defined in claim 33. further comprising a general purpose programmable media processor coupled to the high bandwidth data channel to receive, process and transmit media information at substantially peak rates. 37. The high bandwidth processor interface defined in claim 33, wherein the peak rate of operation comprises at least one gigabyte of information per second from point to point. 38. The high bandwidth processor interface defined in claim 33, wherein the plurality of memory controllers each comprise a paired link disposed between each memory controller, the paired links each for transmitting and receiving plural bits of data and having differential data inputs and outputs and a differential clock signal. 39. The high bandwidth processor interface defined in claim 38, wherein the paired link further comprises a digital skew calibrator to adjust the plural bits of data relative to the differential clock signal to eliminate skew between the data. 40. The high bandwidth processor interface defined in claim 38, wherein the paired link further comprises a phase locked loop to eliminate jitter in the differential clock signal transmitted between paired links. 41. The high bandwidth processor interface defined in claim 38, wherein the plural bits comprise eight bits of data. 42. The high bandwidth processor interface defined in claim 38, wherein the paired links each further comprise termination resistors to form matched impedances for each paired link. 43. The high bandwidth processor interface defined in claim 34, wherein the high bandwidth data channel comprises plural parallel high bandwidth data channels. 44. A system for unified media processing comprising: a plurality of general purpose media processors, each media processor operable at sustained peak data rates and having a dynamically partitioned execution unit and a high bandwidth interface, the high bandwidth interface coupled to external memory and input/output elements to receive and transmit data to the media processor at substantially peak rates; a bi-directional communication fabric, the plurality of media processors coupled to the bi-directional commumcation fabric to transmit and receive at least one media stream comprising presentation, transmission, and storage media information. 45. The system defined in claim 44, wherein the bi-directional communication fabric comprises a fiber optic network. 46. The system defined in claim 44, wherein the bi-directional commumcation fabric comprises an heterogeneous network. 47. The system defined in claim 44, wherein the bi-directional commumcation fabric comprises a coaxial cable network. 48. The system defined in claim 44, wherein the bi-directional communication fabric comprises a wireless network. 49. The system defined in claim 44. wherein a subset of the plurality of media processors comprise network servers. 50. The system defined in claim 44, wherein the plurality of media processors are programmable by downloading program information over the bi¬ directional communication fabric. 51. The system defined in claim 44, wherein the each of the plurality of media processors can access an idle execution unit of another media processor in a shared manner to efficiently process presentation, transmission and storage media information at substantially peak data rates. 52. The system defined in claim 44, wherein each media processor further comprises dedicated memory and wherein the each of the plurality of media processors can employ any unused portion of the dedicated memory of another media processor in a shared manner to efficiently store and retrieve presentation, transmission and storage media information at substantially peak data rates. 53. A parallel multi-processor system that maintains substantially peak data throughput in the unified execution of multiple media streams, the system having a data path, comprising: at least one high bandwidth external interface, the at least one high bandwidth external interface coupled to the data path and operable to receive a plurality of data of various sizes from an external source and communicate the received data at a rate that maintains substantially peak operation of the parallel multi-processor system; a plurality of register files, each register file having at least one general purpose register coupled to the data path and operable to store a working set of media data; and at least one multi-precision execution unit coupled to the data path, the at least one multi-precision execution unit dynamically configurable to partition data within a working set of media data received from the data path to account for the elemental symbol size of the plurality of media streams, and programmable to operate in parallel on working sets of data stored in the plurality of register files to generate a unified symbol output for each register file. 54. The parallel multi-processor system defined in claim 53, wherein the at least one execution unit alternates in a round robin manner to operate on data stored in the plurality of register files. 55. The parallel multi-processor system defined in claim 53, further comprising an instruction pre-fetch pipeline. 56. The parallel multi-processor system defined in claim 55, wherein the instruction pre-fetch pipeline comprises a super-string pipeline. 57. The parallel multi-processor system defined in claim 55, wherein the instruction pre-fetch pipeline comprises a super-spring pipeline. 58. The parallel multi-processor system defined in claim 53, further comprising a data pre-fetch pipeline. 59. The parallel multi-processor system defined in claim 58, wherein the data pre-fetch pipeline comprises a super-string pipeline. 60. The parallel multi-processor system defined in claim 58, wherein the data pre-fetch pipeline comprises a super-spring pipeline. 61. The parallel multi-processor system defined in claim 53, further comprising a requester, responder and transponder daemon. 62. A method for processing unified streams of media data, comprising the steps of: receiving a stream of unified media data including presentation, transmission and storage information; dynamically partitioning the unified stream of media data into component fields of at least one bit based on the elemental symbol size of data received; and processing the unified stream of media data at substantially peak operation. 63. The method defined in claim 62, wherein the step of processing the unified stream of media data comprises the steps of: storing the stream of unified media data in a general register file; performing multi-precision arithmetic operations on the stored stream of unified media data based on programmed instructions, the multi- precision arithmetic operations including Boolean, integer and floating point mathematical operations; manipulating the component fields of unified media data based on programmed instructions that implement copying, shifting and re-sizing operations; and performing multi-precision mathematical operations on the stored stream of umfied media data based on programmed instructions, the mathematical operations including fimte group, finite field, finite ring and table look-up operations. 64. The method defined in claim 63, further comprising the steps of: pre-fetching instructions and data to fill instruction and data pipelines; performing memory management operations to retrieve instructions and data from external memory; storing instructions and data in instruction and data cache/buffers; and dynamically allocating buffer storage in the instruction and data cache/buffers to ensure real-time execution. 65. The method defined in claim 63. further comprising the step of providing a set of instructions to process the stream of unified media data, the set of instructions including load, store, synchronization, branch and gateway instructions. 66. The method defined in claim 65, further comprising the step of programming a sequence of at least one instruction from the set of instructions. 67. A method for achieving high bandwidth communications between a general purpose media processor and external devices, comprising the steps of: providing a high bandwidth interface disposed between the media processor and the external devices, the high bandwidth interface comprising at least one uni-directional channel pair having an input port and an output port; and transmitting and receiving a plurality of media data streams, comprising component fields of various sizes between the media processor and the external devices at a rate that sustains substantially peak data throughput at the media processor. 68. The method defined in claim 67, wherein the step of providing a high bandwidth interface further comprises providing a plurality of external devices, the plurality of external devices coupled in series on the at least one uni¬ directional channel pair. 69. The method defined in claim 67, wherein the step of providing a high bandwidth interface further comprises providing a plurality of parallel uni¬ directional channel pairs. 70. A method for processing streams of media data, comprising the steps of: providing a bi-directional communications fabric for transmitting and receiving at least one stream of unified media data, the at least one stream of unified media data comprising presentation, transmission and storage information; and providing at least one programmable media processor within the communications network, the at least one programmable media processor for receiving, processing and transmitting the at least one stream of unified media data over the bi-directional communications fabric.

Inventors: HANSEN CRAIG C, MOUSSOURIS JOHN, HANSEN, CRAIG, MOUSSOURIS, JOHN
Applicants: HANSEN CRAIG C, MICROUNITY SYSTEMS ENG, MOUSSOURIS JOHN, HANSEN, CRAIG, MICROUNITY SYSTEMS ENGINEERING, INC., MOUSSOURIS, JOHN
Application year: 1996
Main classification: G06F7
IPC codes: G06F9, G06F12, G06F15, H04N7