A bipolar power transistor with buried base and interdigitated geometry

Abstract: A bipolar power transistor of interdigitated geometry having a buried P type base region (320), a buried N type emitter region (325), a P type base-contact region (330), an N type emitter-contact region (335, 355), connected to an emitter electrode (370) and an N type connection region (340) disposed around the emitter-contact region (335, 355). The emitter region (325) is buried within the base region (320) in such a way that the buried emitter region (325) and the connection region (340) delimit a P type screen region (345); the transistor further includes a biasing P type region (350) in contact with the emitter electrode (370), which extends up to the screen region (345).

Description: The present invention relates to a bipolar power transistor with buried base and interdigitated geometry, and in particular, to a bipolar transistor according to the preamble of the first claim. A bipolar power transistor of this type is described in European patent application EP-A-0544364, and is illustrated in the partially sectioned schematic view of Figure 1. As usual, the concentrations of impurities of N and P type are indicated by adding the + or - sign to the letters N and P to indicate, respectively, a high or low concentration of impurities; the letters N and P without the additional + or - sign denote concentrations of intermediate values. Such a bipolar transistor is made from a chip 100 of semi-conductor material comprising a substrate 105 of N+ type, on which there are two epitaxial layers, 110 and 115, of N- type. Between the first and second epitaxial layers 110 and 115, there is a buried base region 120 of P type, and a buried emitter region 125 of N+ type, which form between them a buried P-N junction. A deep P+ base-contact region 130 and a deep N+ emitter-contact region 135 extend from the upper surface of the chip 100 to the buried base region 120 and the buried emitter region 125 respectively. A surface emitter-contact region 140 of N+ type extends from the upper surface of the chip 100 around the region 135; the emitter-contact region constituted by the regions 135 and 140 define a ballast resistor, the purpose of which is that of uniformly distributing the current around the entire perimeter of the emitter region. on the upper surface of the chip 100, which is covered with an insulating layer 145, there are metal tracks 150 and 155 in contact with surface zones of the regions 130 and 140 respectively, which form the base and emitter electrodes respectively of the bipolar power transistor; on the bottom of the chip 100, there is a metal layer 160 in contact with the substrate 105, which forms the collector electrode of the transistor. The bipolar power transistor has in plan a so-called interdigitated geometry in which the emitter electrode 155 is in the form of a comb, the elongate (finger) portions of which lie within the base electrode 150. This structure has an emitter region with a very high perimeter-to-area ratio, and a uniform distribution of current in the various fingers of the emitter, so that the bipolar power transistor can support high currents whilst having a small size. The bipolar power transistor described above is made utilising the VIPower fabrication process (VIPower is a TM of SGS-THOMSON MICROELECTRONICS S.r.l.), described in European patent application EP-A-0322040. Such bipolar power transistors have the disadvantage in operation of a high working current due to the fact that part of the current provided to the base terminal flows directly to the emitter terminal through the portion of the epitaxial layer between the regions 130 and 140, and does not, therefore, contribute to the current gain of the transistor. Moreover, the emitter current does not only flow from the buried region 125 to the metal track 155 through the contact regions 135 and 140; there are, in fact, parallel direct paths through the epitaxial layer from the buried emitter region 125 to the metal track 155, which partially short-circuit the ballast resistor, creating a non-uniform current distribution in the various fingers of the emitter. These phenomena reduce the current gain and the safe operation area, or SOA, of the bipolar transistor. A known arrangement for reducing these disadvantages is described in European patent application EP-A-0632505, and is illustrated in the partially sectioned schematic view of Figure 2 (the elements already shown in Figure 1 are identified with the same reference). This figure illustrates a bipolar transistor made from a chip 200 of semi-conductor material, in which there is a connection region 210 of N+ type, which extends from the upper surface of the chip to the buried emitter region 125 at the perimeter thereof. A screen region 220 of P- type, delimited laterally from the connection region 210 and interposed between a major part of the emitter-contact regions 135, 140 and the buried emitter region 125, extends from the upper surface of the chip 200. A further metal track 230 connects the deep contact region 210 and the screen region 220 together to allow the correct biasing of this latter. The screen region 220, the connection region 210 and the metal track 230 extend, in plan, around the entire perimeter of each emitter finger. This structure makes it possible to avoid the current losses from the base terminal and the buried emitter regions described above; this translates into a greater current gain, and a greater robustness of the bipolar transistor. The known bipolar transistor described above, however, takes up more space on the semi-conductor chip, in that the biasing of the screen region requires an additional metal track. Moreover, it requires a dedicated layer for the formation of the screen region. The object of the present invention is to overcome the above-mentioned disadvantages. To achieve this object, there is provided a buried base bipolar power transistor of interdigitated geometry as described in the first claim and a process for producing a bipolar transistor of unter digitated geometry as described in claim 7. The bipolar transistor of the present invention makes it possible to reduce the current losses and to achieve a good balancing of the emitter current between the elementary portions of the structure without, however, penalising the electrical characteristics, or increasing the dimensions on the chip. The bipolar transistor of the present invention, has, in fact, a smaller size than that of the prior art described, in that the biasing of the screen region utilises the metal track which constitutes the emitter electrode. The structure in accordance with the present invention does not require a dedicated layer for the formation of the screen region; the structure can therefore be produced with a standard fabrication process in that all the layers of semi-conductor material utilised for its production are already present in the basic sequence for the production of the bipolar power transistor. Further characteristics and advantages of the bipolar power transistor according to the present invention will become apparent from the following description of a preferred embodiment, given purely by way of non-limitative example, with reference to the attached drawings, in which; Figure 1 is a schematic, partially sectioned view of a known buried-base bipolar power transistor having interdigitated geometry; Figure 2 is a partially sectioned schematic view of a known bipolar power transistor with a screen region; Figure 3 is a partially sectioned schematic view of a bipolar power transistor according to the present invention; and Figure 4 is an equivalent circuit diagram of the bipolar transistor of Figure 3. With reference now to the drawings, and in particular with reference to Figure 3 (Figures 1 and 2 have already been described above), a partially sectioned schematic view of a bipolar power transistor according to the present invention is illustrated. For simplicity of description reference will always be made hereinafter to a bipolar power transistor of NPN type made on a substrate and an epitaxial layer doped with impurities of N type; equivalent considerations are applicable if the N type regions are replaced with corresponding P type regions and vice versa. The bipolar power transistor is formed in a chip 300 of semi-conductor material comprising a substrate 305, typically mono-crystalline silicon strongly doped with impurities of N (N+) type; a first epitaxial layer 310 of the same conductivity type, but low concentration of (N-) impurities is formed by epitaxial growth on the substrate 305. On the upper surface of the epitaxial layer 310, there is formed by ion implantation and subsequent diffusion, a P type region having a concentration of impurities of intermediate value (P); a doped region of N+ type is then formed on this P type region by a subsequent implantation and diffusion phase. A second epitaxial layer 315 of N type having an impurity concentration greater than or equal to that of the first layer 310, is formed thereon by epitaxial growth. In this phase, which takes place at high temperature, the previously implanted P type and N type impurities diffuse further into the two epitaxial layers 310 and 315, giving rise to buried regions; in particular, the P type impurities define a buried base region 320 of the bipolar power transistor, whilst the N type impurities define a buried emitter region 325 of the same bipolar transistor. The concentration and type of the P type and N type impurities in the buried base region 320 and emitter region 325 are chosen in such a way that, as a result of the different speed of diffusion of the different doping elements of P and N type, the region 325 is buried within the region 320. For example, utilising low diffusivity N type impurities, (such as antimony or arsenic), the concentration of P type impurity (for example boron) is greater than 10 13 atoms/cm 2 (the concentration of the N type impurities is not affected in this case). In the second epitaxial layer 315, there are then formed, using known techniques of masking and ion implantation with subsequent diffusion, regions having high concentration of impurities, which substantially traverse the whole of the second epitaxial layer 315. In particular, a region 330 of P+ type joins with the buried base region 320 to define a deep base-contact, whilst a region 335 of N+ type joins up with the buried emitter region 325 to define a deep emitter-contact. A connection region 340 of N+ type extends to the buried emitter region 325 along the perimeter thereof. The connection region 340 and the buried emitter region 325 delimit a portion 345 of the buried base region 320; the portion 345 defines a screen region which is interposed between part of the emitter-contact region (described hereinafter), and the buried emitter region 325. The connection region 340 and the screen region 345 extend, in plan, along the entire perimeter of each emitter finger. With similar ion implantation and diffusion techniques there are then formed one or more biasing regions 350 of P+ type, which extend through the epitaxial layer 315 to contact the screen region 345; preferably these regions are adjacent to the deep emitter-contact region 335. Around the deep emitter-contact region 335 there is then formed the surface emitter-contact region 355 of N+ type, which has in plan an enlarged structure with respect to that of the region 335; the emitter-contact region constituted by the regions 335 and 355 define a ballast resistor for the emitter of the bipolar transistor. As shown in the drawing, the biasing regions 350 are formed in such a way as not completely to surround the deep emitter-contact region 335, so as not to interrupt the ballast resistor. Preferably, the biasing regions 350 are constituted by stud portions distributed in a uniform manner around the deep emitter-contact region 335. Subsequently, on the front of the chip 300, which is covered with an insulating layer 360 (typically silicon dioxide), using known techniques for deposition, masking and etching, there are formed conductive tracks, for example metal or polycrystalline silicon, 365 and 370 in contact with surface zones of the regions 330 and 335, 355 respectively, which respectively form the base and emitter electrodes of the bipolar power transistor; the metal track 370 is moreover also in contact with the surface zones of the regions 350 to allow correct biasing of the screen region 345. The bipolar power transistor has in plan a so-called interdigitated geometry, in which the emitter electrode 370 extends in the form of a comb with the elongate (finger) portions within the base electrode 365. On the bottom of the chip 300, there is a metal layer 375 in contact with the substrate 305 which forms the collector electrode of the bipolar power transistor. The equivalent circuit diagram of the bipolar transistor described above is shown in Figure 4. The circuit illustrated comprises an NPN bipolar power transistor T, having an emitter terminal E (connected to the track 370), a base terminal B (connected to the track 365), and a collector terminal C (connected to the layer 375). The bipolar transistor T further has an internal base terminal B' (buried base region 320), and an internal emitter terminal E' (buried emitter region 325). Between the terminals B-B' and between the terminals E-E', there are, respectively, a base resistor Rb and an emitter resistor Re which represent the internal resistances respectively of the base-contact region 330 and the emitter-contact region 335,355. The circuit then includes a lateral PNP bipolar transistor T1 created by the P type region 320 (emitter in the conduction phase of the transistor T), the N type region 340 (base) and the P type region 345 (collector), and a vertical bipolar NPN transistor T2 created by the N type region 355 (emitter in the conduction phase of the transistor T), the P type region 345 (base) and the N type region 325 (collector). As illustrated in the drawing, the emitter, base and collector terminals of the transistor T1 are connected, respectively, to the internal base terminal B' (common region 320), the internal emitter terminal E' (contact region 340 with region 325), and base terminal of the transistor T2 (common region 345); the emitter and collector terminals of the transistor T2 are respectively connected to the terminal E (contact track 370 with region 355), and internal emitter terminal E' (common region 325). The collector terminal of the transistor T1 and the base terminal of the transistor T2 are, moreover, connected to the terminal E by the biasing region 350. Analysing the equivalent circuit illustrated in the drawing shows that the transistor T2, with the base and emitter terminals short-circuited, is always switched off. The two transistors T and T1 have the same base-emitter voltage, but of opposite sign; because their base-emitter threshold voltage is substantially the same, the transistor T1 will always be in conduction when the power transistor T is in conduction. The transistor T1 subtracts part of the current provided to the base terminal B, which does not therefore contribute to the current gain of the power transistor T. With reference to Figure 3, note however that the transistor T1 has a low current, because of the high resistance of the collector region 345. Advantageously, the biasing regions 350 are disposed alongside the deep emitter-contact regions 335, in such a way that the collector region of the transistor T1 has a greater length, and therefore a greater resistivity. In a preferred embodiment of the present invention, the N+ type region 340, i.e. the base region of the transistor T1 is doped with a very high concentration of N type impurities; this further reduces the gain of the transistor T1, and therefore the magnitude of the current subtracted thereby from the power transistor T. The structure in accordance with the present invention therefore has very little base current loss which, above all, is substantially constant with an increase in working current, so that its percentage effect diminishes with an increase in the working current. From experimental results it has been established that the bipolar transistor in accordance with the present invention has a current gain variation, as a function of the working current, which is better than that presented by known structures for high currents. Moreover, this structure makes it possible to obtain a uniform distribution of the current in the various emitter fingers, so that current concentrations in limited regions are not recorded; this allows a greater robustness to be obtained even for high values of working current.

Claims: A bipolar power transistor of interdigitated geometry formed in a chip (300) of semi-conductor material (305, 310, 315) of a first conductivity type, comprising: a buried base region (320) of a second conductivity type and a buried emitter region (325) of the first conductivity type buried in the semi-conductor material (310, 315) and forming, between them, a buried junction, a base-contact region (330) of the second conductivity type and an emitter-contact region (335, 355) of the first conductivity type extending from a surface of the chip (300) to, respectively, the buried base region (320) and the buried emitter region (325), the emitter-contact region (335, 355) defining a ballast resistor, and being in contact on the said surface with conductive means (370) constituting an emitter electrode of the transistor a screen region (345) of the second conductivity type disposed around the emitter-contact region (335, 355) and a connection region (340) of the first conductivity type extending from the said surface to the buried emitter region (325) said connection region disposed around the screen region (345), characterised in that the buried emitter region (325) is buried within the buried base region (320), the buried emitter region (325) and the connection region (340) delimiting a portion (345) of the buried base region (320) constituting the screen region, the transistor further including at least one biasing region (350) of the second conductivity type in contact on the said surface with the conductive means (370) and extending to the screen region (345). A bipolar transistor according to Claim 1, in which the emitter-contact region (335, 355) is constituted by a deep contact region (335) extending from the said surface to the buried emitter region (325) and a surface contact region (355) extending from the said surface towards the buried emitter region (325) around the deep emitter-contact region (335), the at least one biasing region (350) being formed in such a way as not to surround the deep emitter-contact region (335) completely. A bipolar transistor according to Claim 2, in which the at least one biasing region (350) lies adjacent to a portion of the deep emitter-contact region (335). A bipolar transistor according to Claim 2 or Claim 3, comprising a plurality of non-adjacent biasing regions (350) distributed in a uniform manner around the deep emitter-contact region (355). A bipolar transistor according to any of Claims 1 to 4, in which the connection region (340) has a greater impurity concentration than that of the buried emitter region (325) and the emitter-contact region (335, 355). A bipolar transistor according to any of claims from 1 to 5, in which the first conductivity type is N and the second conductivity type is P. A process for producing a bipolar power transistor of interdigitated geometry comprising the steps of: growing a first epitaxial layer (310) of a first conductivity type on a first surface of a substrate 305 of the first conductivity type, the first epitaxial layer (310) having a second surface opposite the first surface, implanting and diffusing a buried base region (320) of a second conductivity type on the second surface, and a buried emitter region (325) of the first conductivity type on the buried base region (320), growing a second epitaxial layer (315) of the first conductivity type on the second surface, the second epitaxial layer (315) having a third surface opposite the second surface, further diffusing the buried base region (320) and the buried emitter region (325), the concentration and type of the impurities of the buried base (320) and emitter (325) regions having been chosen in such a way that the buried emitter region (325) is buried within the buried base region (320), implanting and diffusing a base-contact region (330) of the second conductivity type, and a deep emitter-contact region (335) of the first conductivity type, extending from the third surface to, respectively, the buried base region (320) and the buried emitter region (325), and a connection region (340) of the first conductivity type extending from the third surface to the buried emitter region (325) around the deep emitter-contact region (335), the buried emitter region (325) and the connection region (340) delimiting a portion of the buried base region (320), constituting a screen region (345), implanting and diffusing at least one biasing region (350) of the second conductivity type extending from the third surface up to the screen region (345), implanting and diffusing a surface emitter-contact region (355) of the first conductivity type extending from the third surface towards the buried emitter region (325) around the deep emitter-contact region (335), the deep emitter-contact region (335) and the surface emitter-contact region (355) defining a ballast resistor, forming on the third surface conductive means (370) constituting an emitter electrode of the transistor in contact with the surface emitter-contact region (355) and with the biasing region (350). A process according to Claim 7, in which the first conductivity type is N and the second conductivity type is P.

Inventors: PATTI DAVIDE, PATTI, DAVIDE
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1996
Main classification: H01L29
IPC codes: H01L21, H01L29