AREA AND TIME EFFICIENT FIELD EXTRACTION CIRCUIT

Abstract: The present invention is a data word extraction circuit that receives n data words DWx (for x equal 0 through n-1), where each of the data words DWx having m bit positions BPy (for y = 0 through m-1). The circuit provides at least one of the data words DWx to an extraction circuit output responsive to an extraction indicator signal. Specifically, a group of data selector elements DSEy, each corresponding to a separate one of the bit positions BPy in the received data words. Each data selector element includes a data output DOy and a plurality of data inputs DIx. Each data input DIx is connected to receive a bit from the bit position BPy to which the data selector element DSEy corresponds, of a data word DWx to which the data input DIx corresponds. A select input is responsive to the extraction indicator signal such that the data selector element DSEy provides, at the data output, the bit received at one of the data inputs DIx that corresponds to the extraction indicator signal. The bits provided at the data outputs of the group of data selector elements are collectively provided to the extraction circuit output.

Description: AREA AND TIME EFFICIENT FIELD EXTRACTION CIRCUIT Technical Field of the Invention The present invention relates to field extraction circuits and in particular, to a high-speed field extraction circuit which has a minimum wiring complexity. Background of the Invention Processor machine code instructions are typically have pre-defined instruction "fields" which may be predictably located within each instruction. Referring to the processor decoder described in commonly-assigned U.S. patent application Serial No. 08/ , entitled "TAGGED PREFETCH AND INSTRUCTION DECODER FOR VARIABLE LENGTH INSTRUCTION SET AND METHOD OF OPERATION" (atty. docket no. NSC 1-64100), filed on even date herewith and which is hereby incorporated by reference in its entirety, the decoder extracts particular fields of an instπiction to be decoded from an instruction stream. Well known methods of instruction field extraction involve loading the instruction to be decoded into a register and then shifting the bits of the instruction such that a field of interest is located in a portion of the register (usually the least significant portion of the register) from which the field can be manipulated. However, particularly with the quest for smaller and faster processors, such methods usually require shifting (or transposition) circuitry, which is area and time inefficient. Long wiring distances usually contribute to this area and time inefficiency. For a background on shifting circuitry, the reader is referred to a basic textbook on CMOS design (e.g., CA. Mead and L.A. Conway, Introduction to VLSI Systems. Section 5.7, Addison- Wesley, Reading, Mass., 1980). What is desired is a circuit for extracting instruction fields which has relatively low wiring complexity and area, and which operates at relatively high speed. Summary of the Invention The present invention is a data word extraction circuit that receives n data words DW χ (for x equal 0 through n-1), where each of the data words DW χ having m bit positions BP (for y = 0 through m-l). The circuit provides at least one of the data words DW χ to an extraction circuit output responsive to an extraction indicator signal. Specifically, a group of data selector elements DSE , each corresponding to a separate one of the bit positions BP γ in the received data words. Each data selector element includes a data output DO and a plurality of data inputs DI χ . Each data input DI χ is connected to receive a bit from the bit position BP V to which the data selector element DSE V corresponds, of a data word DW to y y x which the data input Dl χ corresponds. A select input is responsive to the extraction indicator signal such that the data selector element DSE provides, at the data output, the bit received at one of the data inputs Dl χ that corresponds to the extraction indicator signal. The bits provided at the data outputs of the group of data selector elements are collectively provided to the extraction circuit output. In a further embodiment of the invention, a second group of data selector elements DSE2 is also provided. Each of the data selector elements corresponds to a separate one of the bit positions BP in the received data words DW χ . Like the first group of data selector elements, each of the second group of data selector elements includes a data output D02 . Each of the second group of data selector elements further includes a plurality of data inputs DI2 χ . Each data input DI2 χ is connected to receive a bit from the bit position BP to which the data selector element DSE2 y corresponds, of a data word DW ( x _nR£Mn t0 nicn tne data in P ut DI X corresponds. Also like the first group of data selector elements, each of the second group of data selectors includes a select input that is responsive to the extraction indicator signal. The data selector element DSE y provides, at the data output, the bit received at one of the data inputs DI χ that corresponds to the extraction indicator signal. The bits provided at the data outputs of the second group of data selector elements are also collectively provided to the extraction circuit output. A better understanding of the features and advantages of the invention will be obtained by reference to the following detailed description and accompanying drawings which set forth an illustrative embodiment in which the principles of the invention are utilized. Brief Description of the Figures Fig. 1 schematically illustrates a field extraction circuit in accordance with the present invention. Detailed Description Referring to the field extraction circuit 100 illustrated in Fig. 1, a first row 1 10 of four-to-one data selectors 1 12a through 1 12d are each configured to receive four bits of an instruction. In particular, four- to-one data selector 112a receives, at its four inputs, the least significant bit (i.e., bit 0) of each of four words —words 0 through 3— of an input data stream. The input data stream may be, for example, instructions to be decoded by a processor decoder. The least significant input, DO, of four-to-one data selector 1 12a receives bit 0 of word 0; the next significant input, Dl, receives bit 0 of word 1; the next significant input, D2, receives bit 0 of word 2; and the most significant input, D3, receives bit 0 of word 3. Four-to-one data selector 1 12b receives, at its four inputs, the next to least significant bit (i.e., bit 1) of each of words 0 through 4. Similar to four-to-data selector 112a, input DO receives bit 1 of word 0; input Dl receives bit 1 of word 1; input D2 receives bit 1 of word 2; and input D3 receives bit 1 of word 3. Referring to Fig. 1, it can be seen that a similar pattern is followed for four-to-one data selectors 112c and 112d. A second row 120 of four-to-one data selectors 122a through 122d are each configured to receive the same four bits received by the data selectors 112a through 112d, respectively, of the first row 110, but rotated. That is, referring to Fig. I, it can be seen that the four bits received by each of four-to-one data selectors 122a through 122d of row 120 are rotated by one bit from the four bits received by each of the four-to-one data selectors 112a through 122d, of row 110. For example, the least significant input of four-to-one data selector 122a, DO, receives bit 0 of word 1, as compared to the least significant input of four-to-one data selector 112a receiving bit 0 of word 0. A third row 130 of four-to-oπe data selectors 132a through 132d are each configured to receive the same four bits received by the data selectors 112a through 112d, respectively, of the first row 1 10 and the data selectors 122a through 122d, respectively, of the second row 120. However, the four bits received by each of four-to-one data selectors 132a through 132d of the third row 130 are rotated by one bit from the four bits received by the four-to-one data selectors 122a through 122d, respectively, of the second row 120; and by two bits from the four bits received by the four-to-one data selectors 1 12a through 112d, respectively, of the first row 110. Finally, a fourth row 140 of four-to-one data selectors 142a through 142d are each configured to receive the same four bits received by the data selectors 112a through 1 12d, respectively, of the first row 110, but rotated by three bits; by the data selectors 122a through 122d, respectively, of the second row 120, but rotated by two bits; and by the data selectors 132a through 132d, respectively, of the third row 130, but rotated by one bit. Referring still to Fig. 1, a two-to-one decoder 160 receives a two bit address, ADR [0..1]. When the two-to-one decoder 160 receives the two-bit address, ADR [0..1 ], at its data inputs, DO and Dl, the decoder 160 operates in a conventional manner to assert one, and only one, of the four decoder outputs, Q0 through Q3. The decoder outputs, Q0 through Q3, are connected to a four bit bus 162. It is an important feature that the four bit bus 162 is connected to the select input, S, of every one of the four-to- one data selectors I 12a-1 12d, 122a-122d, 132a-132d, and 142a-142d. Furthermore, each of the four-to-one data selectors 112a- 1 12d, 122a-122d, 132a-132d, and 142a- 142d behave conventionally, and in an identical manner. That is, if decoder output Q0 is asserted, each four-to-one data selector outputs, to its Q data output, the value provided at its DO data input. If decoder output Ql is asserted, each four-to-one data selector outputs, to its Q data output, the value provided at its Dl data input. If decoder output Q2 is asserted, each four-to-one data selector outputs, to its Q data output, the value provided at its D2 data input. Finally, if decoder output Q3 is asserted, each four-to- one data selector outputs, to its Q data output, the value provided at its D3 data input. Taking, for example, four-to-one selector 112a, if decoder output Q0 is asserted, then four-to-one selector 1 12a selects bit 0 of input data stream word 0 to be provided to its output, Q. Otherwise, if decoder output Ql is asserted, then four-to-one selector 112a selects bit 0 of word 1 to be provided to its output, Q. If decoder output Q2 is asserted, then four-to-one selector 112a selects bit 0 of word 2 to be provided to its output, Q. Finally, if decoder output Q3 is asserted, then four-to-one selector 112a selects bit 0 of word 3 to be provided to its output, Q. The Q data outputs of the four-to-one data selectors of a particular one of the four rows 110, 120, 130, and 140 collectively provide one of four extracted output values EXTR[0], EXTRfl], EXTR[2], and EXTR[3], respectively. Thus, the value of the address, ADR [0..1], determines which word of the input data stream will be provided to the extracted outputs, EXTR [0] through EXTR [3]. That is, first, if ADR[0..1] is 0, then word 0 is provided to EXTR [0], word 1 is provided to EXTR [1], word 2 is provided to EXTR [2], and word 3 is provided to EXTR [3]. Second, if ADR [0..1] is 1, then word 1 is provided to EXTR [0], word 2 is provided to EXTR [1], word 3 is provided to EXTR [2], and word 0 is provided to EXTR [3]. Third, if ADR[0..1] is 2, then word 2 is provided to EXTR [0], word 3 is provided to EXTR [1], word 0 is provided to EXTR [2], and word 1 is provided to EXTR [3]. Finally, if ADR [0..1] is 3, then word 3 is provided to EXTR [0], word 0 is provided to EXTR [1], word 1 is provided to EXTR [2], and word 2 is provided to EXTR [3]. A particular embodiment in accordance with the invention having been described, it should be understood that various alternatives to the embodiment of the invention described herein may be employed in practicing the invention. For example, the size of the input data stream words may vary from four, as may the number of input data stream words. The invention embodiments described herein have been implemented in an integrated circuit which includes a number of additional functions and features which are described in the following co-pending, commonly assigned patent applications, the disclosure of each of which is incorporated herein by reference: U.S. patent application Serial No. 08/ , entitled "DISPLAY CONTROLLER CAPABLE OF ACCESSING AN EXTERNAL MEMORY FOR GRAY SCALE MODULATION DATA" (atty. docket no. NSC 1-62700); U.S. patent application Serial No. 08/ , entitled "SERIAL INTERFACE CAPABLE OF OPERATING IN TWO DIFFERENT SERIAL DATA TRANSFER MODES" (atty. docket no. NSC 1-62800); U.S. patent application Serial No. 08/ , entitled "HIGH PERFORMANCE MULTIFUNCTION DIRECT MEMORY ACCESS (DMA) CONTROLLER" (atty. docket no. NSC 1-62900); U.S. patent application Serial No. 08/ , entitled "OPEN DRAIN MULTI-SOURCE CLOCK GENERATOR HAVING MINIMUM PULSE WIDTH" (atty. docket no. NSC 1-63000); U.S. patent application Serial No. 08/ , entitled "INTEGRATED CIRCUIT WITH MULTIPLE FUNCTIONS SHARING MULTIPLE INTERNAL SIGNAL BUSES ACCORDING TO DISTRIBUTED BUS ACCESS AND CONTROL ARBITRATION" (atty. docket no. NSC 1-63100); U.S. patent application Serial No. 08/ , entitled "EXECUTION UNIT ARCHITECTURE TO SUPPORT x86 INSTRUCTION SET AND x86 SEGMENTED ADDRESSING" (atty. docket no. NSC1-63300); U.S. patent application Serial No. 08/ , entitled "BARREL SHIFTER" (atty. docket no. NSC 1-63400); U.S. patent application Serial No. 08/ , entitled "BIT SEARCHING THROUGH 8, 16, OR 32-BIT OPERANDS USING A 32-BIT DATA PATH" (atty. docket no. NSC 1-63500); U.S. patent application Serial No. 08/ , entitled "DOUBLE PRECISION (64-BIT) SHIFT OPERATIONS USING A 32-BIT DATA PATH" (atty. docket no. NSC 1-63600); U.S. patent application Serial No. 08/ , entitled "METHOD FOR PERFORMING SIGNED DIVISION" (atty. docket no. NSC 1-63700); U.S. patent application Serial No. 08/ , entitled "METHOD FOR PERFORMING ROTATE THROUGH CARRY USING A 32-BIT BARREL SHIFTER AND COUNTER" (atty. docket no. NSC 1-63800); U.S. patent application Serial No. 08/ , entitled "AREA AND TIME EFFICIENT FIELD EXTRACTION CIRCUIT" (atty. docket no. NSC 1-63900); U.S. patent application Serial No. 08/ , entitled "NON-ARITHMETICAL CIRCULAR BUFFER CELL AVAILABILITY STATUS INDICATOR CIRCUIT' (atty. docket no. NSC 1-64000); U.S. patent application Serial No. 08/ , entitled "TAGGED PREFETCH AND INSTRUCTION DECODER FOR VARIABLE LENGTH INSTRUCTION SET AND METHOD OF OPERATION" (atty. docket no. NSC 1-64100); U.S. patent application Serial No. 08/ , entitled "PARTITIONED DECODER CIRCUIT FOR LOW POWER OPERATION" (atty. docket no. NSC 1-64200); U.S. patent application Serial No. 08/ , entitled "CIRCUIT FOR DESIGNATING INSTRUCTION POINTERS FOR USE BY A PROCESSOR DECODER" (atty. docket no. NSC 1-64300); U.S. patent application Serial No. 08/ , entitled "CIRCUIT FOR GENERATING A DEMAND-BASED GATED CLOCK" (atty. docket no. NSC 1-64500); U.S. patent application Serial No. 08/ , entitled "INCREMENTOR DECREMENTOR" (atty. docket no. NSC 1-64700); U.S. patent application Serial No. 08/ , entitled "A PIPELINED MICROPROCESSOR THAT PIPELINES MEMORY REQUESTS TO AN EXTERNAL MEMORY" (atty. docket no. NSC 1-64800); U.S. patent application Serial No. 08/ , entitled "CODE BREAKPOINT DECODER" (atty. docket no. NSC 1-64900); U.S. patent application Serial No. 08/ , entitled "TWO TIER PREFETCH BUFFER STRUCTURE AND METHOD WITH BYPASS" (atty. docket no. NSC 1-65000); U.S. patent application Serial No. 08/ , entitled "INSTRUCTION LIMIT CHECK FOR MICROPROCESSOR" (atty. docket no. NSC 1-65100); U.S. patent application Serial No. 08/ , entitled "A PIPELINED MICROPROCESSOR THAT MAKES MEMORY REQUESTS TO A CACHE MEMORY AND AN EXTERNAL MEMORY CONTROLLER DURING THE SAME CLOCK CYCLE" (atty. docket no. NSC 1-65200); U.S. patent application Serial No. 08/ , entitled "APPARATUS AND METHOD FOR EFFICIENT COMPUTATION OF A 486™ MICROPROCESSOR COMPATIBLE POP INSTRUCTION" (atty. docket no. NSC 1-65700); U.S. patent application Serial No. 08/ , entitled "APPARATUS AND METHOD FOR EFFICIENTLY DETERMINING ADDRESSES FOR MISALIGNED DATA STORED IN MEMORY" (atty. docket no. NSC1-65800); U.S. patent application Serial No. 08/ , entitled "METHOD OF IMPLEMENTING FAST 486™ MICROPROCESSOR COMPATIBLE STRING OPERATION" (atty. docket no. NSC 1-65900); U.S. patent application Serial No. 08/ , entitled "A PIPELINED MICROPROCESSOR THAT PREVENTS THE CACHE FROM BEING READ WHEN THE CONTENTS OF THE CACHE ARE INVALID" (atty. docket no. NSC 1-66000); U.S. patent application Serial No. 08/ , entitled "DRAM CONTROLLER THAT REDUCES THE TIME REQUIRED TO PROCESS MEMORY REQUESTS" (atty. docket no. NSC 1-66300); U.S. patent application Serial No. 08/ , entitled "INTEGRATED PRIMARY BUS AND SECONDARY BUS CONTROLLER WITH REDUCED PIN COUNT" (atty. docket no. NSC 1-66400); U.S. patent application Serial No. 08/ , entitled "SUPPLY AND INTERFACE CONFIGURABLE INPUT/OUTPUT BUFFER" (atty. docket no. NSC1-£6500); U.S. patent application Serial No. 08/ , entitled "CLOCK GENERATION CIRCUIT FOR A DISPLAY CONTROLLER HAVING A FINE TUNEABLE FRAME RATE" (atty. docket no. NSC1-66600); U.S. patent application Serial No. 08/ , entitled "CONFIGURABLE POWER MANAGEMENT SCHEME" (atty. docket no. NSC 1-66700); U.S. patent application Serial No. 08/ , entitled "BIDIRECTIONAL PARALLEL SIGNAL INTERFACE" (atty. docket no. NSC 1-67000); U.S. patent application Serial No. 08/ , entitled "LIQUID CRYSTAL DISPLAY (LCD) PROTECTION CIRCUIT' (atty. docket no. NSC 1-67100); U.S. patent application Serial No. 08/ , entitled "IN-CIRCUIT EMULATOR STATUS INDICATOR CIRCUIT' (atty. docket no. NSC 1-67400); U.S. patent application Serial No. 08/ , entitled "DISPLAY CONTROLLER CAPABLE OF ACCESSING GRAPHICS DATA FROM A SHARED SYSTEM MEMORY" (atty. docket no. NSC 1-67500); U.S. patent application Serial No. 08/ , entitled "INTEGRATED CIRCUIT WITH TEST SIGNAL BUSES AND TEST CONTROL CIRCUITS" (atty. docket no. NSC 1-67600); U.S. patent application Serial no. 08/ , entitled "DECODE BLOCK TEST METHOD AND APPARATUS" (atty. docket no. NSC 1-68000). It is intended that the following claims define the scope of the invention and that methods and apparatus within the scope of these claims and their equivalents be covered thereby.

Claims: WHAT IS CLAIMED IS: 1. A data word extraction circuit that receives a plurality (n) of data words DW χ (for x equal 0 through n-1), each of said data words DW χ having a plurality (m) of bit positions BP (for y = 0 through m-l), and that provides one of said data words DW χ to an extraction circuit output responsive to an extraction indicator signal, said data element extraction circuit comprising: a group of data selector elements DSE y , each of said data selector elements corresponding to a separate one of the bit positions BP in the received data words and including a data output DO ; a plurality of data inputs DI χ , each data input DI χ connected to receive a bit from the bit position BP, y, to which the data selector element DSE V corresponds, of a data word DW V Λ to which the data input DI χ corresponds; and a select input responsive to the extraction indicator signal such that the data selector element DSE provides, at the data output, the bit received at one of the data inputs DI χ that corresponds to the extraction indicator signal, the bits provided at the data outputs of the group of data selector elements being collectively provided to the extraction circuit output. 2. A data word extraction circuit as in claim 1, wherein the group of data selector elements DSE V is a first group of data selector elements DSE1 , and further comprising: a second group of data selector elements DSE2 y , each of said data selector elements corresponding to a separate one of the bit positions BP y in the received data words DW χ and including a data output D02 ; a plurality of data inputs DI2 χ , each data input DI2 χ connected to receive a bit from the bit position BP to which the data selector element DSE2 corresponds, of a data word ^^(x+nREMn to mcn tne data ' n P ut D'χ corresponds; and a select input responsive to the extraction indicator signal such that the data selector element DSE y provides, at the data output, the bit received at one of the data inputs DI χ that corresponds to the extraction indicator signal, the bits provided at the data outputs of the second group of data selector elements also being collectively provided to the extraction circuit output. 3. A data word extraction circuit as in claim 1, wherein the group of data selector elements DSE is a first group of data selector elements DSEl y , and further comprising: a second group of data selector elements DSE2 γ , each of said data selector elements corresponding to a separate one of the bit positions BP y in the received data words DW χ and including a data output D02 ; a plurality of data inputs DI2 χ , each data input DI2 χ connected to receive a bit from the bit position BP to which the data selector element DSE2 y corresponds, of a data word Dw 7x+i ) REMn t0 wn ' cn tne tlata m P ut DI χ corresponds, where j is an integer between 1 and n-1, inclusive; and a select input responsive to the extraction indicator signal such that the data selector element DSEy provides, at the data output, the bit received at one of the data inputs DI χ that coπesponds to the extraction indicator signal, the bits provided at the data outputs of the second group of data selector elements also being collectively provided to the extraction circuit output.

Inventors: PHILLIPS CHRISTOPHER E, SANKAR NARENDRA, PHILLIPS, CHRISTOPHER, E., SANKAR, NARENDRA
Applicants: NAT SEMICONDUCTOR CORP, NATIONAL SEMICONDUCTOR CORPORATION
Application year: 1996
Main classification: G06F7
IPC codes: G06F7