Improvements in or relating to semiconductor chip separation

Abstract: A method of scribing and separating chips on a semiconductor wafer (21) wherein the wafer (21) is patterned and a pattern of intersecting grooves is etched on a selected surface of the semiconductor wafer (21) in a pattern, preferably in a grid pattern, to define chip areas on that surface. Trenches (27) are then formed in the shape of the pattern and the selected surface is adhered to a tape (29). Light is then passed through the tape (29) and semiconductor wafer (21) from the pattern and a pattern of intersecting saw cuts or grooves (28) aligned with the light passing through the wafer (21) is formed. The saw cuts (28) extend from a surface of the wafer (21) opposing the selected surface and are aligned with the pattern of intersecting trenches (27).

Description: BACKGROUND OF THE INVENTION FIELD OF THE INVENTION This invention relates to a method for separating semiconductor chips formed on a semiconductor wafer, and more particularly to a method of the type defined in the precharacterizing portion of claim 1. BRIEF DESCRIPTION OF THE PRIOR ART Chips formed on a single wafer of semiconductor material have generally been scribed and separated in the prior art by one of several available procedures. These prior art procedures generally provide for attachment of the wafer to an adhesive handling film with subsequent fracturing taking place along "streets" between rows and columns of chips to separate the chips. The chips are then removed from the handling film and processed in standard manner. Fracturing of the wafer has generally been accomplished by (1) laser scribing a depression in the wafer along the "streets" and then breaking the wafer the rest of the way, (2) sawing a depression in the wafer along the "streets and then breaking the wafer the rest of the way, or (3) sawing entirely through the wafer along the "streets". A problem arising from the above described prior art techniques has been the large amount of semiconductor material or chip surface area wasted due to the large "street" widths required in order to prevent damage to chips during chip separation. In the case of fracturing by the procedures listed above as (1) and (2), there is the possibly that the break in the wafer below the depression will not be straight, resulting in chips of nonuniform dimensions. Also, sawing can cause fractures at the wafer surface, this being a source of defects and decreased yields when sawing takes place at the surface containing the electrical components. A method of the type mentioned in the beginning is known from Patent Abstracts of Japan JP-A-04107155. This document discloses a technique to improve printing quality by accurately cutting the surface of a silicon substrate with grooves for cutting processes prepared beforehand by employing anisotropic etching to the surface side of the silicon substrate. European Patent Application EP-A-0 305 204 discloses a process for forming individual dies wherein the active side of a wafer is etched to form small V-shaped grooves defining the die faces, relatively wide grooves are cut in the inactive side of the wafer opposite each V-shaped groove, and the wafer cut by sawing along the V-shaped grooves, the saw being located so that the side of the saw blade facing the die is aligned with the bottom of the V-shaped groove so that there is retained intact one side of the V-shaped groove to intercept and prevent cracks and chipping caused by sawing from damaging the die active surface and any circuits thereon. SUMMARY OF THE INVENTION In accordance with the present invention, there is provided a method for separating chips formed on and in semiconductor wafers of the type mentioned in the beginning and further comprising the features of the characterizing portion of claim 1. In a preferred embodiment, trenches are etched in the wafer of semiconductor material, wherein etching takes place in standard manner with patterning and etching to define each chip area on the wafer surface, either at the commencement, during or after fabrication of the chips. Chip separation then involves securing the trench-containing surface to a die bonding adhesive tape and then sawing a groove from the reverse side in the direction of the trench spaced from the trench. Separation is completed by breaking. The saw or other groove-forming procedure is aligned with the trench at this time by passing a light to which the wafer is somewhat transparent, such as infrared in the case of a silicon wafer, through the masked wafer. This procedure minimizes the damage to the active surface of the chip caused by sawing on the chip surface containing the electrical components as practiced in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will now be further described, by way of example, with reference to embodiments of the accompanying drawings in which:- FIGURE 1 is a top view of a portion of a partially fabricated semiconductor wafer in accordance with the prior art; FIGURE 2 is a cross sectional view taken along the line 2-2 of FIGURE 1; and FIGURES 3 to 5 are a partial process flow for fabrication of semiconductor chips in accordance with the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENT Referring first to FIGURES 1 and 2, there is shown a portion of a typical, partially fabricated prior art wafer 1 having "streets" 3 in the vertical direction and 5 in the horizontal direction defining chips or dice 7. The chips 7 are separated from each other by use of one of the above described prior art techniques which initially provides a cut 9 in the "street" 3 and a similar cut in the "street" 5 (not shown) followed by severing or breaking along the line 13. The "streets" 3 and 5 generally have a width in the range of about 3 to 5 mils to accommodate for some misalignment of the scribing apparatus as well as to minimize surface damage to the chip from sawing or the like. The prior art fabrication techniques involve securing the wafer to a handling film 11, which is generally a flexible film with an adhesive thereon, prior to commencement of any of the scribing operations as shown in FIGURE 2. Referring now to FIGURES 3 to 5, there is shown a partial process flow for fabrication of chips in accordance with the present invention. In FIGURE 3, there is shown a cross section of a semiconductor wafer 21 in accordance with the present invention showing the wafer with the active surface 25 and a trench 27 which has been etched into the active surface of the wafer to define chips on the wafer. The wafer 21 is secured by the active surface 25 thereon to a saw tape 29, which can be an adhesive material similar to the handling film and transmissive to the light frequencies to be passed therethrough as discussed hereinbelow if such light is utilized, as shown in FIGURE 4. A saw cut or groove 28 is then made which is aligned with the trench 27 and preferably extends to a small distance above the trench as shown in FIGURE 4. The groove 28 can extend to the trench 27 as an alternate embodiment. The light can be, for example, infrared light in the case of a silicon wafer since silicon is transparent to such light frequencies. The light or other aligning operation will be chosen to be compatible with the semiconductor wafer material being used to provide the alignment function. The wafer 21 is then removed from the saw tape 29 and the surface with the groove 28 is again secured to a handling film 33, which can be an adhesive material similar to the handling film discussed hereinabove, and the chips are then separated by breaking or the like as in the prior art along the line 31 between trench 27 and groove 28 as shown in FIGURE 5. The breaking step is not required if the groove 28 has been sawed to contact the trench 27. It can be seen that there has been provided a procedure for defining and separating chips fabricated on a wafer which requires far less spacing between chip areas than is required by prior art procedures, thereby saving surface areas and permitting more chips to be fabricated in the same wafer area compared with the prior art. Though the invention has been described with reference to a specific preferred embodiment thereof, many variations and modifications will immediately become apparent to those skilled in the art.

Claims: A method of separating chips on a semiconductor wafer (21) comprising the steps of etching a pattern of intersecting trenches (27) on a selected surface (25) of said wafer (21) to define chip areas on said surface (25); and forming a groove (28) extending from a surface of said wafer (21) opposing said selected surface (25) and aligned with said pattern of intersecting trenches (27); and characterized in that the method further comprises the step of breaking the region of semiconductor material in said wafer (21) between said groove (28) and said pattern of intersecting trenches (27) to form individual chips; and that said step of forming a groove (28) comprises the steps of passing light having a frequency transmissive through said semiconductor wafer (21) from said trenches (27) through said semiconductor wafer (21) and forming said groove (28) aligned with said trenches (27). The method of claim 1, wherein said step of etching a pattern includes the steps of masking said selected surface (25) to define a grid pattern and etching said grid pattern to form said trenches (27). The method of claim 1 or claim 2, wherein said step of forming a groove (28) further comprises the step of adhering said wafer (21) to a tape (29) transmissive to light having said frequency prior to passing light through said wafer (21). The method of any preceding claim, wherein said method further comprises the steps of securing said surface of said wafer (21) opposing said selected surface (25) to an adhesive surface before breaking the region of semiconductor material in said wafer (21), and removing said individual chips from said adhesive surface after breaking the region of semiconductor material in said wafer (21).

Inventors: ORCUTT JOHN W, ORCUTT, JOHN W.
Applicants: TEXAS INSTRUMENTS INC, TEXAS INSTRUMENTS INCORPORATED
Application year: 1996
Main classification: H01L21
IPC codes: H01L21