Method of manufacturing capacitor included in semiconductor device

Abstract: A method of manufacturing a capacitor comprises a step of forming a first dielectric layer (5) composed of a ferroelectric material or a dielectric material possessing high permittivity on a first electrode (2), a step of sintering the first dielectric layer, a step of forming a second dielectric layer (7) on the first dielectric layer, and a step of forming a second electrode (4) on the second dielectric layer (7).

Description: BACKGROUND OF THE INVENTION The present invention relates to a method of manufacturing a capacitor included in a semiconductor device, more particularly, a capacitor using a ferroelectric layer or a dielectric layer having high permittivity as a capacitor insulating layer. Recent trends demonstrate that semiconductor devices which are commonly used in consumer electronic appliances are becoming higher in density and integration. As a result, the integrated circuit patterns of these semiconductor devices are required to be miniaturized. These electronic appliances containing high density integrated semiconductor devices produce electromagnetic noise thereby generating unwanted radiation, poising serious problems. As a means for reducing this unwanted radiation capacitors having large capacitance are incorporated into the semiconductor integrated circuits using a ferroelectric layer or a dielectric layer having high permittivity. Turning to the operation of low voltage electronic appliances and the development of nonvolatile RAMs which are capable of writing/reading signals at high speed, technological developments in the electronics industry have found a need of forming a capacitor which has a ferroelectric layer possessing spontaneous polarization on the semiconductor integrated circuit. Referring to the Drawings, Figures 2(a), 2(b) and 2(c) illustrate a capacitor produced by the conventional method of manufacturing a capacitor by using a ferroelectric layer as a capacitor insulating layer is described. First, as shown in Fig. 2 (a), a first electrode 2 composed of Pt is formed by sputtering selectively on a substrate 1. Then, as shown in Fig. 2(b), a ferroelectric layer 3 composed of SrBi 2 Ta 2 O 9 is formed on the first electrode 2, in a layer thickness range of 100 to 250 nm, by spin coating method, CVD (chemical vapor deposition) method, or sputtering method, and sintered in a temperature range of 650 to 800 °C in oxygen atmosphere. Successively, as shown in Fig. 2(c), a second electrode 4 of Pt is formed on the ferroelectric layer 3 in a thickness range of 100 to 300 nm by sputtering method, thereby forming a capacitor. In the conventional manufacturing method, however, in order that the capacitor insulating layer may have a sufficiently high permittivity and a sufficient spontaneous polarization, it is necessary to form the capacitor insulating layer having a crystal grain size of about 100 nm or more. However, this grain size is too large for the necessary thickness of 200 nm as a capacitor insulating layer. Accordingly, the surface of the capacitor insulating layer becomes very rough. When the capacitor is manufactured by using such a capacitor insulating layer, the dielectric strength is low, large fluctuations occur in electric characteristics such as permittivity and spontaneous polarization, or breakage may occur in interconnections formed on a second electrode, and ultimately the semiconductor device incorporating such capacitor has lower reliability. None of the conventional manufacturing methods of the capacitors and the capacitors thereof described above provides the important advantages of manufacturing a capacitor having excellent electric properties and high reliability, by flattening the surface of the capacitor insulating layer. Reference may be made to US-A-5 390 072 which describes a method for forming a high capacitance thin film capacitor comprising forming an amorphous layer of a dielectric material on the surface of a polycrystalline layer of said dielectric material and arranging the resulting double layer between upper and lower electrodes. Reference may also be made to "Thin Solid Films", vol. 29, No. 2, 1995, pages 264-269 which describes a technique for fabricating low leakage ferroelectric BaTiO 3 (BTO) thin film capacitors. BTO thin films with thicknesses range from 220nm to 265 nm were deposited using reactive r.f. magnetron sputtering. A highly stable and conductive metallic oxide, RuO 2 , was used as the bottom electrode of the capacitors on SiO 2 /Si substrates. Layers of BTO deposited at low temperature were amorphous and those deposited at high temperature above 600°C were polycrystalline. Microcrystallization of amorphous BTO took place at a thermal treatment temperature of above 600°C. Capacitors with a bilayer configuration of polycrystalline layers on microcrystalline layers were said to show a capacitance per unit area of around 2.4 x 10 5 pF cm -2 and a leakage current density of (8.5±0.5) x 10 -8 A.cm -2 at a field intensity of 2 x 10 5 V.cm -1 . A capacitance per unit area of around 1.4 x 10 5 pF.cm -2 and a leakage current density of around 10 -10 A.cm -2 at a field intensity of 2 x 10 5 V.cm -1 were said to be achieved on the capacitors with a nanolayer configuration of amorphous layers on a number of stacked cycles of polycrystalline layers on microcrystalline layers. SUMMARY OF THE INVENTION As pointed out above a primary object of the invention is to present a method of manufacturing a capacitor having excellent electric properties and high reliability, achieved by flattening the surface of the capacitor insulating layer. Aspects of the invention are defined in the claims. Therefore, according to the invention, the first dielectric layer composed of a ferroelectric material or a dielectric material having high permittivity is sintered, and the rough surface of the first dielectric layer is covered with the second dielectric layer having the mean grain size smaller than the mean grain size of the first dielectric layer, or containing an amorphous region aside from crystal region, so that the capacitor insulating layer with a smooth surface is obtained, and thereby the dielectric strength is extremely enhanced, electric properties such as permittivity and spontaneous polarization are stabilized, and the reliability of the semiconductor device may be enhanced. The invention itself, together with further objects and attendant advantages, will best be understood by reference to the following detailed description taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1(a), Fig. 1(b), Fig. 1(c), and Fig. 1(d) are cross sectional views showing a capacitor in an embodiment of the invention as produced by the claimed manufacturing method. Fig. 2(a), Fig. 2(b), and Fig. 2(c) are cross sectional views showing a capacitor as known in the prior art as produced by the conventional manufacturing method. DETAILED DESCRIPTION OF THE INVENTION A first embodiment of the invention is described below while referring to Fig. 1(a) to Fig. 1(d). Same components as in the conventional capacitor shown in Fig. 2 are identified with same reference numerals. As shown in Fig. 1 (a), a first electrode 2 of Pt is formed on a substrate 1 in a thickness range of 50 to 400 nm. Then, as shown in Fig. 1 (b), a first dielectric layer 5 made of SrBi 2 Ta 2 O 9 is formed on the first electrode 2 in a thickness range of 50 to 250nm by spin coating method, CVD method or sputtering method, and sintered at a temperature of 650 to 800°C in oxygen atmosphere. Consequently, as shown in Fig. 1(c), Ta 2 O 5 layer is formed as a second dielectric layer 6 on the first dielectric layer 5 having the surface roughened by crystallization. Finally, as shown in Fig. 1(d), a second electrode 4 of Pt in a thickness range of 50 to 300 nm is formed on the second dielectric layer 6. As a result, a capacitor is obtained. In this way, the second dielectric layer 6 of Ta 2 O 5 is buried in the recess of rough surface of the first dielectric layer 5 made of SrBi 2 Ta 2 O 9 , so that the capacitor insulating layer composed of the first dielectric layer 5 and second dielectric layer 6 comes to have a flat surface. Meanwhile, the second dielectric layer 6 may contain an amorphous region. In this embodiment, Ta 2 O 5 is used as the second dielectric layer, but same effects are obtained by using other dielectric material such as Bi 2 O 3 . A second embodiment of the invention is described below. The manufacturing process of the capacitor in this embodiment is nearly the same as in the first embodiment, and the difference from the first embodiment lies in the material of the second dielectric layer. A first electrode 2 of Pt is formed on a substrate 1, and a first dielectric layer 5 of SrBi 2 Ta 2 O 9 is formed on the first electrode 2 and sintered at a temperature of 650 to 800°C in oxygen atmosphere. A second dielectric layer 7 of (Ba x Sr 1-x )TiO 3 is formed on the first dielectric layer 5 by spin coating method, and a second electrode 4 is formed thereon. As a result, a capacitor of the second embodiment is formed. In this way, in the recess of rough surface of the first dielectric layer 5 made of SrBi 2 Ta 2 O 9 , the (Ba x Sr 1-x )TiO 3 of the second dielectric layer 7 having smaller crystal grains than crystal grains of SrBi 2 Ta 2 O 9 is buried, so that the capacitor insulating layer composed of the first dielectric layer 5 and second dielectric layer 7 comes to have a flat surface. In this embodiment, the second dielectric layer 7 of (Ba x Sr 1-x )TiO 3 is used, but the same effects are obtained by using other ferroelectric material or high permittivity dielectric material having crystal grain size smaller than that of the first dielectric layer 5. In yet a third embodiment of the invention, the manufacturing process of the capacitor in this embodiment is nearly the same as in the first embodiment, and the difference from the first embodiment is that the dielectric material for the second dielectric layer is the same material as the first dielectric layer, while the heat treatment method is different. Same as in the first embodiment, a first electrode 2 of Pt is formed on a substrate 1, and a first dielectric layer 5 of SrBi 2 Ta 2 O 9 is formed on the first electrode 2 and sintered. Then, a second dielectric layer 8 of SrBi 2 Ta 2 O 9 is formed on the first dielectric layer 5 by spin coating method, CVD method or sputtering method, in a thickness range of 20 to 50 nm. After heat treatment at 600°C, a second electrode 4 is formed on the second dielectric layer 8, thereby forming a capacitor of the third embodiment. Crystal grain size of the second dielectric layer 8 is smaller than that of the first dielectric layer 5, because the heat treatment temperature is lower than the sintering temperature. Therefore, the recess of the rough surface of the first dielectric layer 5 made of SrBi 2 Ta 2 O 9 is filled up with the SrBi 2 Ta 2 O 9 of the second dielectric layer 8 having smaller crystal grain size. As a result, the capacitor insulating layer composed of the first dielectric layer 5 and second dielectric layer 8 comes to have a flat surface. Moreover, in this embodiment, though the heat treatment temperature of the second dielectric layer 8 is different from the sintering temperature of the first dielectric layer 5, the first and second dielectric layers are made of same material. Therefore, other equipment for depositing the second dielectric layer 8 is not needed, and hence the manufacturing process may be simplified, so that the cost may be saved. Since the same material is used, among other benefits, separation due to thermal stress or the like often occurring between the first dielectric layer and second dielectric layer will not take place. In the first, second, and third embodiments, SrBi 2 Ta 2 O 9 of ferroelectric material is used as the first dielectric layer 5, but other ferroelectric material or dielectric material having high permittivity may be also used. In particular, when the first dielectric layer 5 is composed of ferroelectric material containing Bi, such as Bi 4 Ti 3 O 12 , SrBi 2 Ta 2 O 9 , and SrBi 2 Nb 2 O 9 , since their grain size is larger than that of other dielectric material, the dielectric strength of the capacitor manufactured by the invention is extremely enhanced. In the foregoing embodiments, Pt film is used as the material for the first electrode and second electrode of the capacitor, but same effects may be obtained by using Pd or other metal, or RuO 2 or other conductive oxide.

Claims: A method of manufacturing a capacitor comprising: a step of forming a first electrode (2) on a substrate (1); a step of forming a first dielectric layer (5) comprising a ferroelectric material or a dielectric material having high permittivity, on the first electrode (2); a step of sintering the first dielectric layer (5); after the sintering of the first dielectric layer a step of forming a second dielectric layer (6; 7; 8) on the first dielectric layer (5); and a step of forming a second electrode (4) on the second dielectric layer (6; 7; 8); wherein the first and second dielectric layers one at least partially crystalline, and the mean crystal grain size of the material of the second dielectric layer (6; 7; 8) is smaller than the mean crystal grain size of the material of the first dielectric layer (5). A method of manufacturing a capacitor according to claim 1, wherein a principal component of the material of the second dielectric layer (6; 7; 8) is the same as a principal component of the material of the first dielectric layer (5). A method of manufacturing a capacitor according to claim 1, further comprising a step of heating the second dielectric layer (6; 7; 8), wherein the heating temperature of the heating step is lower than the sintering temperature of the sintered step. A method of manufacturing a capacitor according to claim 1, wherein the material comprised in the first dielectric layer (5) is a ferroelectric material containing at least bismuth. A capacitor comprising: a first electrode (2) formed on a substrate (1); a first at least partially crystalline sintered dielectric layer (5) comprising a ferroelectric material or a dielectric material having high permittivity formed on the first electrode (2); a second at least partially crystalline dielectric layer (6; 7; 8) formed on the first dielectric layer (5); and a second electrode (4) formed on the second dielectric layer (6; 7; 8); wherein the mean crystal grain size of the material of the second dielectric layer (6; 7; 8) is smaller than the mean crystal grain size of the material of the first sintered dielectric layer (5) and wherein the surface of the capacitor insulating layer is substantially planar.

Inventors: ARITA KOJI, MATSUDA AKIHIRO, NAGANO YOSHIHISA, NASU TORU, UEMOTO YASUHIRO, ARITA, KOJI, MATSUDA, AKIHIRO, NAGANO, YOSHIHISA, NASU, TORU, UEMOTO, YASUHIRO
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1996
Main classification: H01L21
IPC codes: H01L27, H01L21