Data sensing timing modulating circuit, particularly for non-volatile memories

Abstract: A data sensing timing modulating circuit, particularly for non-volatile memories, the particularity whereof is that it comprises means (1) for generating a first voltage (V=f(Icell)) that is a function of the conductivity of a memory cell and of a second substantially constant reference voltage (V=Vref), and a first delay circuit (2) and a second delay circuit (3) supplied by the first and second voltages, the first delay circuit (2) being adapted to modulate, as a function of the first voltage, the start time of the switching of an equalization signal (EQ) that is normally present in the memory device, the switching of this signal indicating the beginning of a data sensing step. The second delay circuit (3) is adapted to modulate the slope of the switching of the equalization signal (EQ), as a function of the first voltage, so as to determine the instant when the equalization signal (EQ) ends the switching to start the subsequent data sensing step.

Description: The present invention relates to a data sensing timing modulating circuit, particularly for non-volatile memories. It is known that in memories which use dynamic sense amplifiers (but a similar case occurs with static amplifiers, i.e., amplifiers that do not read the data of the memory at particular times and therefore allow reading at any freely selectable time), it is very important to determine the moment of data sensing and the sensitivity of the amplifier, i.e., the timing of the control step meant to capture the data, so as to obtain the best possible result in any operating condition. The sensing step generally follows a first precharge step that very quickly brings the bit lines to which the various memory cells are connected to the operating level and equalizes them. Indeed because they are equalized, these lines must then have time enough to assume a difference, however small, allowing certain and correct data reading. However, the time intervals that determine a timing for reading a non-volatile memory are not absolute but depend on a certain number of variables, such as: the conductivity characteristics of the memory cells; the levels transmitted to the cells at the given instant; the capacitance of the associated lines; the minimum sensitivity of the sense amplifiers; the impedances of the memory access paths; the presence/absence of supply voltage boosting circuits; the operating temperature. It is thus evident that it is not possible. to establish beforehand a given data sensing timing, with the purpose of optimizing the read times of a memory device. Even if one considerably expands the timing of the sensing step, with a consequent slowing of the data capture, the case may in fact occur in which the levels transmitted to the cells are still insufficient to determine their possible conductivity, and if one proceeded nonetheless with the reading operation, the result would be unreliable. A memory device with scarcely conductive cells requires a longer settling time than a similar device with more conductive cells. In any case, the sensing step must be followed by a data capture step that must be performed as quickly as possible. European publication EP-A1-0 818 376 filed on July 28, 1995 in the name of the same Applicant disclosed a circuit for generating a signal with a slope capable of being modulated, which is a function of the conductivity of a memory cell. Slope modulation is therefore performed in close correlation to the conductivity of the memory cell. A principal aim of the present invention is therefore to provide a data sensing timing modulating circuit, particularly for non-volatile memories, that is capable of modulating the data sensing and capture times as a function of the conductivity of the memory cells. Within the scope of this aim, an object of the present invention is to provide a data sensing timing modulating circuit, particularly for non-volatile memories, that is capable of correlating the moment when the data sensing step starts to the conductivity of the memory cells. Another object of the present invention is to provide a data sensing timing modulating circuit, particularly for non-volatile memories, that allows to optimize the sensitivity of the sense amplifiers of the memory device, as a function of the conductivity of the memory cells of said device. Another object of the present invention is to provide a data sensing timing modulating circuit for a memory device that allows to suspend and delay the timing for the extraction of the data item if the minimal conditions for correct and certain reading are not achieved. Another object of the present invention is to provide a data sensing timing modulating circuit for a memory device, which allows to modulate the data sensing timing according to the voltage applied to the memory device at a given instant. Another object of the present invention is to provide a data sensing timing modulating circuit that allows to modulate the timing of the data according to the operating temperature of the memory device at a given instant. Another object of the present invention is to provide a data sensing timing modulating circuit that allows to modulate data timing according to the intrinsic conductivity characteristics of the memory device. Another object of the present invention is to provide a data sensing timing modulating circuit that allows to modulate the data timing according to the technological and process characteristics used in the memory device. Another object of the present invention is to provide a sensing timing modulating circuit for the data of a memory device that is highly reliable and relatively easy to produce at competitive costs. This aim, these objects, and others which will become apparent hereinafter are achieved by a data sensing timing modulating circuit for a memory device particularly for non-volatile memories, characterized in that it comprises means for generating a first voltage that is a function of the conductivity of a memory cell and of a second substantially constant reference voltage, and a first delay circuit and a second delay circuit supplied by said first and second voltages, said first delay circuit being adapted to modulate, as a function of said first voltage, the start time of the switching of an equalization signal that is normally present in the memory device, the switching of said signal indicating the beginning of a data sensing step, said second delay circuit being adapted to modulate the slope of the switching of said equalization signal, as a function of said first voltage, so as to determine the instant when said equalization signal ends the switching to start the subsequent data reading step. Further characteristics and advantages of the invention will become apparent from the description of a preferred but not exclusive embodiment of the circuit according to the invention, illustrated only by way of non-limitative example in the accompanying drawings, wherein: figure 1 is a block diagram of the circuit according to the invention; figure 2 is a chart of the timings of the circuit according to the invention;. figure 3 is a circuit diagram of a portion of the circuit according to the invention shown in figure 1; figure 4 is a circuit diagram of another portion of the circuit according to the invention shown in figure 1; figure 5 is a chart of the timings of signals of the circuit according to the invention; and figure 6 is another chart of the timings of signals of a portion of the circuit according to the invention. With reference to the above figures, the circuit according to the invention comprises voltage generating means 1 that are adapted to generate two voltages, one whereof is a substantially constant reference voltage. Said voltages are designated by Vref and V=f(Icell). The second voltage is a function of the conductivity of an elementary cell, which reproduces a generic memory cell of a memory device. The first voltage Vref is instead substantially constant as the conductivity of the elementary cell varies. The methods for generating said voltages are disclosed in a copending patent application in the name of the same Applicant. Said voltages Vref and V=f(Icell) produced by the voltage generation means 1 are sent simultaneously and respectively to a first delay circuit 2 and to a second delay circuit 3. Advantageously, the first and second delay circuits 2 and 3 are both constituted by a circuit for generating a signal the slope whereof can be modulated as a function of the conductivity of a memory cell. The first delay circuit 2 receives in input the precharge signal PCn, in addition to the two voltages generated by the voltage generating means 1, and produces in output a first signal UST the delay whereof can be modulated; said signal UST is fed as input to the second delay circuit 3. The signal UST generated by the first delay circuit is a signal the transition whereof from 0 to 1 is a function of the conductivity of the memory cell affected by the reading operation. This signal sets a delay time that determines the beginning of the switching, with a variable' slope, of the equalization signal. The output of the second delay circuit 3 is taken from the node with modulated slope, so as to generate a signal the slope whereof can be modulated, i.e, the equalization signal EQ modulated appropriately as a function of the conductivity of the cell. Therefore, this second delay circuit modulates the slope with which the equalization signal switches from high to low, as a function of the conductivity of the involved memory cell. Figure 2 plots the timing of the precharge and equalization signals PCn and EQ. The three delays t 1 , t 2 , and t 3 show three different modulations of the starting point of the switching of the signal EQ as a function of three different conductivity values of the memory cell. The delay t 1 corresponds to the most conductive cell, whereas the delay t 3 corresponds to the least conductive cell. The delays t 4 , t 5 , and t 6 correspond respectively to the modulation of the sensitivity of the sense amplifier as a function of the conductivity of the current. In this case, too, t 4 defines the lowest sensitivity of the sense amplifier, whereas t 6 refers to a higher sensitivity than t 4 . This delay, designated by the output signal EQ of the second delay circuit 3, determines the slope with which the signal EQ switches. The line 1 defines the time of assured data capture, which must therefore be instantaneous. The signal EQ then switches suddenly to zero from this line onward. With reference to figures 3 and 4, said figures illustrate the two delay circuits 2 and 3 in their circuital details. It is easily noticeable that the two circuits are identical, and accordingly only the circuit 2 will be described, assigning the same reference numerals to identical elements in the two circuits 2 and 3. For the circuit 3, said reference numerals will be primed. With reference to figure 3, the delay circuit 2 comprises a first P-channel transistor 4 and a second N-channel transistor 5. The signal PCn is sent to-the gate terminals of the transistors 4 and 5. The source terminal of the transistor 4 is connected to the supply voltage V DD and its drain terminal is connected to the drain terminal of the transistor 5. The source terminal of the transistor 5 is connected to the drain terminal of a third N-channel transistor 6, the gate terminal whereof receives the reference voltage Vref generated by the voltage generating means 1. The drain terminal of the transistor 6 is connected to the ground. Capacitive means 7 are connected between the source terminal of the transistor 4 and the ground. A fourth transistor of the native N-channel type 8 and a fifth N-channel transistor 9 are interposed between the supply voltage V DD and the ground. In particular, the drain terminal of the transistor 8 is connected to the supply voltage, its gate terminal is connected to the source terminal of the transistor 4, and its source terminal is connected to the drain terminal of the transistor 9. A control signal DIS, adapted to disable/enable the circuit, is sent to the gate terminal of the transistor 9. The source terminal of the transistor 9 is connected to the ground. There is a sixth N-channel transistor 10, in which the drain terminal is connected to the gate terminal of the transistor 8 and the source terminal is connected to the ground. The gate terminal of the transistor 10 is connected to a branch that comprises a seventh, an eighth, and a ninth transistors, designated respectively by the reference numerals 11, 12, and 13. The transistor 11 is of the P-channel type and the transistors 12 and 13 are of the N-channel type. The source terminal of the transistor 11 is connected to the supply voltage V DD and its gate terminal is connected to the line that connects the source and drain terminals of the transistors 8 and 9 respectively. The drain terminal of the transistor 11 is connected to the drain terminal of the transistor 12. The source terminal of the transistor 12 is connected to the drain terminal of the transistor 13, the source terminal whereof is connected to the ground. The gate terminal of the above-described transistor 10 is connected to the line that connects the source terminal and the drain terminal of the transistors 11 and 12 respectively. The gate terminals of the transistors 11, 12, and 13 are connected to a second branch of the circuit, which comprises a tenth, an eleventh, and a twelfth transistors, designated by the reference numerals 14, 15, and 16 respectively. The transistor 14 is of the P-channel type, whereas the transistors 15 and 16 are of the N-channel type. The gate terminal of the transistor 11 is also connected to the ground by means of a capacitor 19. The source terminal of the transistor 14 is connected to the supply voltage, whereas its drain terminal is connected to the drain terminal of the transistor 15, the source terminal whereof is connected to the drain terminal of the transistor 16. The source terminal of the transistor 16 is connected to the ground. The signal PCn is sent to the gate terminals of the transistors 14 and 15. The gate terminals of the above-described transistors 11, 12, and 13 are respectively connected to the line that connects the drain terminals of the transistors 14 and 15 (for the gate terminals of the transistors 11 and 12) and to the voltage signal V, which is a function of the conductivity of the memory cell and is generated by the voltage generating means 1. The signal UST is emitted by the output node C of the circuit of figure 3 and is fedback in input to the gate terminal of a thirteenth N-channel transistor 17, the drain and source terminals whereof are respectively connected to the line that connects the source terminal and the drain terminal of the transistors 15 and 16 and to the ground. The circuit of figure 4 is, as mentioned, similar to the circuit of figure 3, except for the presence of an additional N-channel transistor 18 that is connected, by means of its drain terminal, to the line for connecting the source and drain terminals of the transistors 5' and 6' and in which the source terminal is connected to the ground. The voltage signal V, which is a function of the conductivity of the memory cell, is sent to the gate terminal of the transistor 18. The charts of figures 5 5 and 6 will be explained with reference to the operation of the circuit according to the invention. With reference to the above figures, the operation of the circuit according to the invention is as follows. The operation of the circuit 2 is similar to the operation of the circuit 3. The difference between the two circuits is given by the fact that the circuit 3 receives, in input to the transistors 4' and 5', the signal UST produced by the circuit 2, instead of the signal PCn, as occurs for the circuit 2. The voltage generating means 1 generate a first voltage V=f(Icell) that is a function of the conductivity of the memory cell and a second substantially constant voltage Vref; these voltages are fed to the gate terminals of the transistors 6, 13, 16, and 6', 18, 13', 16', for the first delay circuit 2 and for the second delay circuit 3 respectively. In the inactive situation, i.e., when a precharging step is not in progress (PCn=1), the nodes A and B of the circuit 2 are low, whereas the node C is high. When the signal PCn switches from high to low (i.e., during the precharging step: PC1), the transistors 4 and 14 are on and the transistors 5 and 15 are off. Then the node A of the circuit 2 is high (at V DD ) and so is the node B. The control signal DIS is set to zero when PCn is low. The output signal UST (i.e., the node C) starts from zero when PCn switches to zero. Thus, to summarize, when PCn switches from high to low the nodes A and B are high and the node C is low. When PCn switches to the high level, the transistor 4 is off, the transistor 5 is on, the transistor 14 is off, and the transistor 15 is on. The capacitor 7 that had charged begins to discharge with a constant current, which is determined by the substantially constant reference voltage Vref. At this point the voltage level of the node A starts to decrease in a linear fashion. Likewise, the node B also decreases in level, but remains below the level of the node A by a threshold that is determined by the threshold voltage of the N-channel transistor 8. The voltage level of the node B is applied to the gate terminal of the P-channel transistor 11. When the threshold level of the transistor 11 is reached, said transistor switches on and the node C rises slowly at first and then quickly, while the node B drops to zero together with the node A. This behavior of the nodes A, B, and C is shown by way of example in figure 6. The signal UST (given by the behavior of the node C) in output from the circuit 2 is fed to the circuit 3. For the second circuit 3, the node the behavior whereof must be plotted is the node A', which is the node corresponding to A. If there is no current in the memory cell, the node B does not drop, since the voltage V=f(Icell) does not activate the transistors 13 and 16. The circuit 2 then produces an output signal UST, the delay whereof is set by the conductivity of the cell and constitutes a delay that can be modulated for the start of the drop (switching to zero) of the signal EQ in output from the circuit 3. The modulation of the time of activation of the signal UST therefore leads to a delay for the signal EQ, whereas the slope that can be modulated, which can be obtained from the circuit 3 in a manner similar to the one described for the circuit 2 since the two circuits are identical, is the actual slope with which the signal EQ is brought to zero, and is always a function of the conductivity of the memory cell involved in the reading operation. The delay of the signal EQ is given, by way of example, by the reference signs t 1 , t 2 , and t 3 of figure 2 for three different values of the conductivity of the memory cell. The signal EQ, i.e., the behavior of the node A', is exemplified in figure 5. The second circuit 3 therefore produces a signal EQ that has the purpose of modulating the sensitivity of the sense amplifier as a function of the conductivity of the memory cell. The variable slope of the signal EQ is indicated by the reference signs t 4 , t 5 , and t 6 of figure 2 for the same conductivity values of the memory cell mentioned above. In practice it has been observed that the circuit according to the invention fully achieves the intended aim, since it allows to modulate the sensing timing of the data of a memory device as a function of the conductivity of the memory cells involved in the reading operation. Therefore, the circuit according to the invention allows to determine the instant (and therefore the delay) when the equalization signal must start to switch from high to low, as well as the slope with which this switching must occur, always as a function of the conductivity of the memory cells. In this manner, sensing timing is highly flexible and independent of the particular technology being used, and is instead closely tied to the supply voltage applied to the device at reading time. Data reading is therefore performed with the best timing for the conditions that are present for the memory device. The circuit thus conceived is susceptible of numerous modifications and variations, all of which are within the scope of the inventive concept. Thus, for example, the two voltages Vref and V=f(Icell) can be swapped without altering the inventive concept. Furthermore, the first delay means can be replaced with any delay network, as long as its delay is linked to the conductivity of a non-volatile matrix cell, i.e., can be modulated by a cell current. Finally, all the details may be replaced with other technically equivalent elements. In practice, the materials employed, so long as they are compatible with the specific use, as well as the dimensions, may be any according to the requirements and the state of the art. Where technical features mentioned in any claim are followed by reference signs, those reference signs have been included for the sole purpose of increasing the intelligibility of the claims and accordingly such reference signs do not have any limiting effect on the interpretation of each element identified by way of example by such reference signs.

Claims: Data sensing timing modulating circuit for a memory device, particularly for non-volatile memories, characterized in that it comprises means (1) for generating a first voltage (V=f(Icell)) that is a function of the conductivity of a memory cell (8) and of a second substantially constant reference voltage (V=Vref), and a first delay circuit (2) and a second delay circuit (3) supplied with said first and second voltages, said first delay circuit (2) being adapted to modulate, as a function of said first voltage, the start time of the switching of an equalization signal (EQ) that is present in the memory device, the switching of said signal indicating the beginning of a data sensing step, said second delay circuit (3) being adapted to modulate the slope (C=UST) of the switching of said equalization signal (EQ), as a function of said first voltage, so as to determine the instant when said equalization signal ends the switching to start the subsequent data reading step. Circuit according to claim 1, characterized in that said first delay circuit (2) is a circuit adapted to generate a first signal (UST) the delay whereof can be modulated as a function of the conductivity of the memory cell (8) involved in the reading operation. Circuit according to claim 1, characterized in that said second delay circuit (3) is a circuit adapted to generate a second signal (C') the slope whereof can be modulated as a function of the conductivity of the memory cell (8') involved in the reading operation. Circuit according to claim 2, characterized in that said first delay circuit (2) receives in input a control signal (PCn) of the memory device and emits in output said first signal (UST) the delay whereof can be modulated as a function of the conductivity of the memory cell (8) involved in the reading operation, said first signal (UST) the delay whereof can be modulated determining the timing of the beginning of the switching of said equalization signal (EQ). Circuit according to claim 2, characterized in that said second delay circuit (3) receives in input said first signal (UST) the slope whereof can be modulated and emits in output (C') said second signal the slope whereof can be modulated, said second signal (C') the slope whereof can be modulated determining the slope of the switching of said equalization signal (EQ), as a function of the conductivity of the memory cell (8') involved in the reading operation. Circuit according to claim 1, characterized in that said first delay circuit (2) is driven by a disable/enable signal (PCn). Circuit according to claim 6, characterized in that said second delay circuit (3) is driven by said disable/enable signal (PCn). Method for modulating the data sensing timing for a memory device, particularly for non-volatile memories, characterized by the steps of: generating a first voltage (V=f(Icell)) that is a function of the conductivity of a memory cell (8) and a second substantially constant voltage (V=Vref) as reference for said first voltage; determining the start time of the switching of an equalization signal (EQ), which is present in the memory device, as a function of the conductivity of said memory cell (8) involved in a reading operation; and determining the slope of the switching of said equalization signal as a function of the conductivity of said memory cell. Method according to claim 8, characterized in that the step of determining the start time of the switching of said equalization signal (EQ) is adapted to produce a first Signal (UST) the delay whereof can be modulated as a function of the conductivity of said memory cell (8), the delay whereof determines the switching time of said equalization signal (EQ). Method according to claim 9, characterized in that said step of determining the start time of the switching of said equalization signal (EQ) is performed by means of a first circuit (2) for generating a first signal (UST) the delay whereof can be modulated. Method according to claim 10, characterized in that said step of determining the switching slope of said equalization signal (EQ) is performed by means of a second circuit (3) for generating a second signal (C') the slope whereof can be modulated, which receives in input said first signal (UST) the delay whereof can be modulated, the output signal (C') of said second circuit (3) for generating a second signal the slope whereof can be modulated determining the switching configuration of said equalization signal (EQ).

Inventors: PASCUCCI LUIGI, PASCUCCI, LUIGI
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1996
Main classification: G11C16
IPC codes: G11C16