SWITCHED CURRENT DIFFERENTIATOR

Abstract: A switched current differentiator comprises first and second interconnected current memory cells (M1, M2). An input current is applied to terminal (1) and is fed on line (2) to the current memory cells (M1, M2). A first output current is derived from the first current memory cell (M1) via transistor (T3) and a second output current is derived from the second current memory cell (M2) via transistor (T4). The second output current is inverted (A1) and summed with the first output current. The summed current is inverted (A2) and fed to an output (3) via a switch (S3) on odd phases of a clock signal and is fed directly to the output (3) via a switch (S4) on even phases of a clock signal. A damped differentiator may be formed using a feedback loop (T5, T6, A3, A4, S5, S6). In a fully differential version of the differentiator the inverters (A1 to A4) may be constructed by the correct interconnection of the differential signals i.e. by crossing over connections.

Description: DESCRIPTION SWITCHED CURRENT DIFFERENTIATOR The invention relates to a switched current bilinear differentiator. Differentiators are of general interest as an alternative to integrators for the implementation of active ladder filters or filters using biquadratic sections. Further even when integrators are used in biquadratic sections the cascaded sections frequently require a differentiated input and while there are known methods for producing from integrator outputs they must be generated explicitly for the first section. A switched current differentiator has been disclosed in EP-A-0 416 699 (PHB 33584). However this circuit requires a unity gain positive amplifier which is difficult to create with sufficient accuracy and is thus a rather complex solution. It is an object of the invention to enable the provision of a switched current differentiator which performs with a bilinear mapping but which does not require the presence of a unity gain positive amplifier. The invention provides a switched current bilinear differentiator comprising first and second interconnected current memory cells, means for feeding an input current to be differentiated to the input of the current memory cells, said first current memory cell being arranged to sample the current at its input during a first period of a clock signal, said second current memory cell being arranged to sample the current at its input during a second period of the clock signal, means for summing a first current related to that in the first current memory cell and second current being an inverted version of a current related to that in the second current memory cell, means for connecting the summed current to an output during the first period of the clock signal and means for feeding an inverted version of the summed signal to the output during a second period of the clock signal; wherein the current at said output is the differentiated current. The differentiator may comprise a feedback loop for feeding back a current related to the output current to the input of the differentiator. This enables a damped (lossy) differentiator to be realised. The feedback loop may comprise means for generating a third current related to that in the first current memory cell, means for generating a fourth current, said fourth current being an inverted version of a current related to that in the second current memory cell, means for summing the third and fourth currents, means for feeding the summed current to the input of the current memory cells during the first period of the clock signal, and means for feeding an inverted version of the summed current to the input of the current memory cells during a second period of the clock signal. This provides a convenient way of producing a scaled replica of the output current for feeding back to the imput. The first and second currents and/or the third and fourth currents may be derived from those in the first and second current memory cells by means of current mirror arrangements, The differentiator may have differential inputs and outputs and comprise first and second differential current memory cells in which the necessary current inversions are effected by appropriate interconnection of the differential outputs of the current memory cells and/or the means for generating output currents related to those in the current memory cells. This enables the current inverters to be replaced by appropriate selection and combination of the differential outputs. Thus a current inversion is obtained merely by swapping the senses of the differential currents at the various nodes within the arrangement. The current memory cells may be arranged to sense and store the currents at these inputs using a coarse and fine step. Such current memory cells are disclosed in EP-A-0 608 936 (PHB 33830), the contents of which are hereby incorporated by reference, to which reference may be made for a more detailed description of its construction and operation than that given with reference to Figures 3 and 4 of the present application. Embodiments of the invention will now be described, by way of example with reference to the accompanying drawings, in which:- Figure 1 shows in schematic form a bilinear z transform differentiator according to the invention, Figure 2 shows a balanced version of the differentiator shown in Figure 1 , Figure 3 shows a two step current memory cell which may be used in the differentiator of Figure 1 or Figure 2, Figure 4 shows clockwave forms associated with the current memory shown in Figure 3, and Figure 5 shows a bilinear z transform differentiator using the current memory cell shown in Figure 3. Figure 1 shows in schematic form a bilinear z transform differentiator according to the invention. It is purely a schematic diagram and does not include bias currents which would normally as is well known be included in practice to enable bidirectional currents to be handled and includes current inverters to invert the signal currents. These current inverters are present for ease of understanding and are not required in a fully differential structure as will be explained hereinafter. As shown in Figure 1 an input 1 is connected over a line 2 to the drain electrodes of first and second n channel field effect transistors T1 , and T2. The drain electrode of transistor T1 is connected by a switch S1 to its gate electrode while the drain electrode of transistor T2 is connected by a switch S2 to its gate electrode. Transistor T1 and switch S1 form a first current memory cell M1 whilst transistor T2 and switch S2 form a second current memory cell M2. The current memory cell M1 further comprises a second transistor T3 which has its gate electrode connected to the gate electrode of transistor T1 and whose drain electrode is connected to one side of two switches S3 and S4. Similarly the current memory cell M2 comprises a further transistor T4 whose gate electrode is connected to the gate electrode of transistor T2 and whose drain electrode is connected by a unity gain inverting amplifier A1 to the junction of switches S3 and S4. The source electrodes of transistors T1 to T4 are all connected to a common supply rail. Consequently the current in transistor in T3 mirrors that in transistor T1 and the current in transistor T4 mirrors that in transistor T2. The junctions of switches S3 and S4 forms a summing node where the currents from transistors T3 and T4 are summed. The other side of switch S4 is connected to an output 3 while the other side of switch S3 is connected via a unity gain inverting amplifier A2 to the output 3. The switches S1 and S4 are closed during an even period of the clock while the switches S2 and S3 are closed during an odd period. The operation of the circuit shown in Figure 1 can be summarised as follows: Following an even period the current stored in the left hand memory cell M1 is increased by the change in the input current from the previous (odd period). Similarly the current stored in the right hand memory cell following an odd period is increased by the change in input current from the previous even (period). The stored currents are mirrored and subtracted and then inverted on odd periods to produce the output current. The analysis which follows shows that the circuit performs undamped differentiation according to the bilinear s-z transformation. odd phase i.e. (n-1) i 2 (n-1) = i (n-1) - i, (n-1) i 0 (n-1) = σ{i 1 (n-1) - i 2 (n-1)} where i is the input current, i, is the current in transistor T1, i 2 is the current in transistor T2, i 0 is the output current, and a is the ratio of transistor T1 to transistor T3 and of transistor T2 to transistor T4. Even phase i.e. (n) i, (n) = i (i) - i 2 (n) but i 2 (n) = i 2 (n-1) i, (n) = i(n) - i(n-1) + i, (n-1) output, i 0 (n) = -a {i,(n) - i 2 (n)} = -σ{i(n)-i(n-1) + i 1 (n-1) - i 2 (n-1)} buti 0 (n-1) = σ{i 1 (n-1)- i 2 (n-1)} Λ i 0 (n) = -σ{i(n)- i (n-1)}- i 0 (n-1) (n) + i 0 (n-1) = -σ{i (n) - i (n-1)} In the z domain:- i 0 (z)(1+z- 1 ) = oϊ (z)(1-z-1 ) For the next odd phase (n+1) i 2 (n+1) = i (n+1)-^ (n+ 1) and i, (n+1) = i, (n) .'. i 2 (n+1) = i (n+1) - i, (n) = i (n+1) - i (n) +i 2 (n) i 0 (n+1) =σ{i 1 (n+1)-i 2 (n+1)} =σ{\, (n)-i 2 (n+1)} = a{\, (n) - i (n+1) + i (n) - i 2 (n)} = σ{i(n+1)-i(n)} + σ{i 1 (n)-i 2 (n)} =-σ{i(n+1)-i(n)}-i 0 (n) i 0 (n+1) + i 0 (n) =-σ{i(n+1)-i(n)} .-. H(z) = — — = - α -same as even phase ( 2 ) i(z) 1 +z-. From (1) and (2), the z domain response is the same for both odd and even phases. The bilinear z - transform is So, H(S) = -α-. S (3) 2 which describes an ideal (undamped) differentiator. In order to produce a damped differentiator the circuit described so far has the following additions. In order to produce a damped (lossy) differentiator an additional feedback loop is included. To produce this feedback loop an n-channel field effect transistor T5 has its gate electrode connected to the gate electrode of transistor T1 , its source electrode connected to the common supply rail, and its drain electrode connected to the junction of two switches S5 and S6. A further n-channel field effect transistor T6 has its gate electrode connected to the gate electrode of transistor T1 , its source electrode connected to the common supply rail, and its drain electrode connected by means of an inverting amplifieer A3 to the junction of switches S5 and S6. The other side of switch S5 is connected via an inverting amplifier A4 to the line 2 while the other side of switch S6 is directly connected to the line 2 It can be seen that this provides a feedback signal to line 2 which is of the same form as the output signal at output 3. The feedback factor which determines the damping of the differentiator characteristic is controlled by appropriately choosing the geometry of transistors T5 and T6 relative to that of transistors T1 and T2. Similarly the overall gain of the differentiator is determined by the geometry of transistors T3 and T4 relative to that of transistors T1 and T2. It can be shown by standard circuit analysis that the response of the arrangement shown in Figure 1 is given by H{z)= - "(1^ ) 1 + z " + α/ (1 - ) 1 -z f) [lz ^ + «/7 z which is the expression for damped differentiation: where a is the ratio of transistors T1 and T2 to transistors T3 and T4 a f is the ratio of transistors T1 and T2 to transistors T5 and T6. Figure 2 shows a fully differential version of a bilinear z-transform differentiator which performs the same algorithm as expressed in the analysis of the circuit of Figure 1 but with signal current inversions achieved simply by crossing over the signal pairs. The p-channel MOS transistors T101 to T108 have their source electrodes connected to a positive supply rail V dd and their gate electrodes connected to a reference voltage V ref . As is well known in switched current circuits each of these transistors forms a constant current source which produces a bias current to enable bidirectional input signals to be handled. A differential input current i is fed on input lines 101 and 102. The line 101 is connected to the junction of the drain electrodes of transistors T102 and T103 while the line 102 is connected to the junction of the drain electrodes of transistors T106 and T107. The drain electrodes of transistors T101 to T108 are connected to the drain electrodes of N-channel MOS transistors T111 to T118 respectively. The source electrodes of transistors T111 to T118 are connected to a negative supply rail V ss . A switch S101 is connected between the drain electrode of transistor T112 and its gate electrode. Similarly, a switch S102 is connected between the drain and gate electrodes of transistor T113, a switch S103 is connected between the drain and gate electrodes of transistor T116, and a switch S104 is connected between the drain and gate electrodes of transistor T117. The gate electrode of transistor T111 is connected to the gate electrode of transistor T112, the gate electrode of T113 is connected to the gate electrode T114, the gate electrode of transistor T115 is connected to the gate electrode of transistor T116, and the gate electrode of transistor T117 is connected to gate electrode of T118. The drain electrode of transistor T112 is connected to the drain electrode of transistor T113. The drain electrode of transistor T114 is connected to the drain electrode of transistor T115, the drain electrode of transistor T116 is connected the drain electrode of transistor T117 and the drain electrode of transistor T118 is connected to the drain electrode of transistor T111. The junction of the drain electrodes of transistors T114 and T115 are connected via a first switch S105 to an output line 103 and via switch S106 to an output line 104. The junction of the drain electrodes of transistors T111 and T118 is connected to the output 104 via a switch S107 and to the output 103 via a switch S108. The transistors T112 and T116 together with the switches S101 and S103 form a differential version of a current memory cell equivalent to that of the memory cell M1 in Figure 1. The transistors T111 and T114 produce the second output which is taken from transistor T3 in Figure 1. Similarly the transistors T113 and T117 and associated switches S102 and S104 form a differential version of the current memory M2 shown in Figure 1. Transistors T111 and T115 with switches S106 and S107 together with transistors T114 and T118 with switches S105 and S108 produce a differential version of the currents produced by transistors T3 and T4, amplifiers A1 and A2, and switches S3 and S4 shown in Figure 1. Since the true and inverted versions of the current are always available at the output of the current memory cells M1 and M2 the inversion function can be selected merely by choosing the correct interconnection of the outputs of the current memory cells. Figure 3 shows a current memory circuit which is an improvement on the current memory circuit shown in Figure 1. Figure 4 shows the various clock wave forms used in the current memory of Figure 3. The current memory shown in Figure 3 comprises a first N-channel field effect transistor T41 which has its source electrode connected to a negative supply rail 40 and its drain electrode connected to the drain electrode of the P-channel field effect transistor T42 whose source electrode is connected to a positive supply rail 41. A capacitor C41 is connected between the gate and source electrodes of transistor T41 while a switch S41 is connected between the drain and gate electrodes of transistor T41. Similarly a capacitor C42 is connected between the source and gate electrodes on transistor T42 while a switch S42 is connected between the gate and drain electrodes of transistor T42. An input 44 is connected via a switch S44 to the junction of the drain electrodes of transistors T41 and T42 and an input 43 to which a voltage reference V rθf is applied is connected by a switch S43 to the gate electrode of transistor T42. A switch S45 is connected between the junctions of transistors T42 and T41 and output 45. As shown in Figure 4 there is a master clock which has two phases ø1 and ø2. The switch S44 is closed on phase ø1 while the switch S45 is closed on phase ø2, that is the input is sampled on phase ø1 and the output is produced on phase ø2. In addition there is a double frequency clock which gives phases ø1a, ø1b, ø2a, ø2b. Switches 41 and S43 are closed during phase ø1a, while switch S42 is closed during phase ø1b. The process of memorising the sampled and held input current i which is applied to input 44 is made in two steps. The first is a coarse step in which the input sample is memorised approximately in a coarse memory CM which comprises transistor T41 switch S41 and capacitor C41. This is followed by a fine step during which the error of the coarse step is derived and memorised in the memory CF which comprises transistor T42 capacitor C42 and switch S42. The output is then delivered in phase ø2 from both memory cells so that the coarse error is subtracted to leave an accurate replica of the input sample. The input phase ø1 is divided into two sub-phases ø1a and ø1b, during which the coarse and then the fine memorising steps occur. During phase ø1a the transistor T42 has its gate electrode connected to V ref and generates a bias current j. The current in the diode connected transistor T41 is then j + i. At the end of phase ø1a the coarse memory switch S41 is opened and the transistor T41 holds a current j + i +Δi. Where Δi is the signal dependent error resulting from all the usual errors associated with the basic switched current memory cell. During phase ø1b, the transistor T42 is configured as a diode and with the signal current i still flowing at the cells input its drain current settles towards the current j + Δi. At the end of phase ø1b, since Δi is very much less than j the voltage at the two transistor drains is close to the value with no signal present, that is the circuit develops a voltage at the drain electrodes of both memory transistors which is akin to a virtual earth. During phase ø2 the gate of transistor T42 is opened and an error Si occurs in the fine memory mainly due to charge injection. If the output is fed to a second cell of a similar type the second cell establishes a similar virtual earth at its input during the input phase ø2b. The drains of the first cells memory are therefore held at nearly the same voltage at the end of both input and output phases, a condition established by negative feedback in conventional cells and which gives a much reduced conductance ratio error. Further because the current in the fine memory transistor and the voltage on its switch are similarly constant during these phases the charge injection error of the fine memory is much reduced. Even though the clock phases ø1 and ø2 are sub divided into a and b sub-phases this does not double the required transistor bandwidths as the settling error on the a sub-phase is transmitted to the transistor T42 where settling may continue on the b sub-phase Figure 5 shows a bilinear differentiator of essentially the same form as that shown in Figure 2 but using the improved memory cell shown in figure 3 rather than the basic memory cell. Elements in Figure 5 corresponding to those in Figure 2 have been given the same reference signs. The following description highlights only the differences between this embodiment and that shown in Figure 2. In order to form the S 2 I current memory cells the direct connection to the gate electrodes of transistors T101 to T108 of the reference voltage V ref is replaced by a switched connection and the switches S101 to S104 are controlled by the waveforms ø1a and ø2a. The reference voltage V ref is applied to the gate electrodes of transistors T101 and T102 via a switch s111 , to the gate electrodes of transistors T103 and T104 via a switch S112, to the gate electrodes of transistors T105 and T106 via a switch S113, and to the gate electrodes of transistors T107 and T108 via a switch S114. The gate electrode of transistor T102 is connected to its drain electrode via a switch S121, the gate electrode of transistor T103 is connected to its drain electrode via switch S122, the gate electrode of transistor T106 is connected to its drain electrode via a switch S123, and the gate electrode of transistor T107 is connected to its drain electrode via a switch S124. The switches are controlled by the clock waveforms shown in Figure 4. Switches S106 and S108 are closed when ø1 is high, switches S105 and S107 are closed when ø2 is high, switches S102, S112, S104 and S114 are closed when ø1a is high, switches S122 and S124 are closed when ø1b is high, switches S101, S111 , S103 and S113 are closed when ø2a is high, and switches S121 and S123 are closed when Q2b is high. The operation of the differentiator shown in Figure 5 is basically the same as that of the differentiator shown in Figure 2, the only differences being as a result of the modified memory cells. These result in the provision of the double frequency clocks ø1a and ølb and ø2a and ø2b. Both the embodiments of Figures 2 and 5 could be further modified to produce lossy (or damped) differentiators by the provision. From reading the present disclosure, other modifications will be apparent to persons skilled in the art. Such modifications may involve other features which are already known in the design and use of electrical or electronic circuits and component parts thereof and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure of the present application also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation of one or more of those features which would be obvious to persons skilled in the art, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention. The applicants hereby give notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present applicaiton or of any further application derived therefrom.

Claims: CLAIMS 1. A switched current bilinear differentiator comprising first and second interconnected current memory cells, means for feeding an input current to be differentiated to the input of the current memory cells, said first current memory cell being arranged to sample the current at its input during a first period of a clock signal, said second current memory cell being arranged to sample the current at its input during a second period of the clock signal, means for summing a first current related to that in the first current memory cell and second current being an inverted version of a current related to that in the second current memory cell, means for connecting the summed current to an output during the first period of the clock signal and means for feeding an inverted version of the summed signal to the output during a second period of the clock signal, wherein the current at said output is the differentiated current. 2. A differentiator as claimed in Claim 1 comprising a feedback loop for feeding back a current related to the output current to the input of the differentiator. 3. A differentiator as claimed in Claim 2 in which said feedback loop comprises means for generating a third current related to that in the first current memory cell, means for generating a fourth current, said fourth current being an inverted version of a current related to that in the second current memory cell, means for summing the third and fourth currents, means for feeding the summed current to the input of the current memory cells during the first period of the clock signal, and means for feeding an inverted version of the summed current to the input of the current memory cells during a second period of the clock signal. 4. A differentiator as claimed in any of Claims 1 to 3 in which each current memory cell comprises a field effect transistor having its gate and drain electrodes connected via a switch. 5. A differentiator as claimed in Claim 4 in which the first and second currents are derived from those in the first and second current memory cells by means of current mirror arrangements. 6. A differentiator as claimed in Claim 4 or Claim 5 in which the third and fourth currents are derived from those in the first and second current memory cells by means of current mirror arrangements. 7. A differentiator as claimed in any preceding claim having differential inputs and outputs and comprising first and second differential current memory cells in which the necessary current inversions are effected by appropriate interconnection of the differential outputs of the current memory cells and/or the means for generating output currents related to those in the current memory cells. 8. A differentiator as claimed in any preceding claim in which the current memory cells are arranged to sense and store the currents at these inputs using a coarse and fine step. 9. A switched current bilinear integrator substantially as described herein with reference to Figure 1 or to Figure 2 or to Figures 3 to 5 of the accompanying drawings. 10. Any novel feature or novel combination of features disclosed herein either explicitly or implicitly whether or not it relates to the same invention as that claimed in any preceding claim.

Inventors: HUGHES JOHN BARRY, MOULDING KENNETH WILLIAM, HUGHES, JOHN, BARRY, MOULDING, KENNETH, WILLIAM
Applicants: PHILIPS ELECTRONICS NV, PHILIPS NORDEN AB, PHILIPS ELECTRONICS N.V.
Application year: 1996
Main classification: G06G7
IPC codes: G06G7