A HIGH AVAILABILITY COMPUTER SYSTEM AND METHODS RELATED THERETO

Abstract: A high availability computer system and methodology including a backplane, having at least one backplane communication bus (208a-d) and a diagnostic bus (206), a plurality of motherboards (202a-h), each interfacing to the diagnostic bus (206). Each motherboard (202a-h) also includes a memory system (252) including main memory distributed among the plurality of motherboards (202a-h), at least one daughterboard (250a-b) and a scan chain that electrically interconnects functionalities mounted on each motherboard (202a-h) and daughterboard (250a-b). The system including instructions and criteria to automatically test the functionalities and electrical connections, using the scan chain, to determine the presence of faulted components and to functionally remove the faulted components from the computer system.

Description: A HIGH AVAILABILITY COMPUTER SYSTEM AND METHODS RELATED THERETO This application claims the benefit of U.S. Provi¬ sional Application Serial No. 60/002,320 filed August 14, 1995, the teaching of which are incorporated herein by reference (see also Appendix A) . FIELD OF INVENTION The present invention relates to computer sys¬ tems and more particularly to a high availability comput¬ er system that automatically senses, diagnoses and de- configures/ re-configures a faulted computer system to improve availability as well as related methods for pro¬ viding high availability. BACKGROUND OF THE INVENTION When procuring a computer system in a business envi¬ ronment, an important factor considered is the availabil¬ ity of the computer to perform/operate. This can affect profitability as well as work/ job performance. There are four basic design concepts used alone or in combina- tion to improve availability. One design technique is commonly referred to as "fault tolerant." A computer system employing this tech¬ nique is designed to withstand a hard fault that could shut down another type of computer system. Such a design typically involves replicating hardware and software so an applications program is running simultaneously in multiple processors. In this way, if a hard fault occurs in one processor or subsystem, the application program running in the other processor(s)/ subsystem(s) still provides an output. Thus, as to the user, the computer system has performed its designated task. In addition to multiple processors, a voting scheme can be implemented, whereby the outputs from the multiple processors are compared to determine the correct output. Fault tolerant systems are complex, essentially require multiple independent processing systems and, as such, are very expensive. Further, although the system is fault tolerant, once a fault occurs it is necessary for a service representative to arrive on site, diagnosis and repair the faulted path/ sub-system. This makes maintenance expensive. Another technique, involves designing components such that they are highly reliable and, therefore, un¬ likely to fail during an operational cycle. This tech¬ nique is common for space, military and aviation applica- tions where size and weight limitations of the intended use (e.g., a satellite) typically restrict the available design techniques. Highly reliable components are typi¬ cally expensive and also make maintenance activities expensive to maintain these design characteristics. Such expenses may make a computer system commercial¬ ly unacceptable for a given application. In any event, once a system has a failure, a service repreεentative must be dispatched to diagnosis and repair the failed system. When dealing with military/ aviation applica¬ tions, the vehicle/ item housing the failed component must be brought to a repair facility. However, until the system is repaired it is unavailable. As such, this increases maintenance costs and makes such repairs/ re¬ placement activities critical path issues. A third technique involves clustering multiple inde¬ pendent computer systems together such that when one computer system fails, its work is performed by any one of the other systems in the cluster. This technique is limited to those applications where there are, or there is a need for, a number of independent systems. It is not usable for a stand alone system. Also, in order for this type of system to work each independent computer system must be capable of accessing the data and applica¬ tion program of any of the systems in the cluster. For example, a central data storage device (e.g. hard drive) is provided that can be accessed by any of the computer systems. In addition to the limited applicability, the foregoing is complex, expensive and raises data security issues. A fourth technique involves providing redundant power supplies and blowers. Thus, the failure of a blow- er or power supply does not result in shutdown of the computer system. However, providing redundancy for other computer systems components is not viable because a ser- vice representative must be brought in to diagnosis the cause of failure so the machine can be repaired and re¬ turned to operability. The fourth technique also has included providing a computer system with a mechanism to automatically re-boot the system following a system crash or hang. This tech¬ nique may allow recovery from transient problems, howev¬ er, there is no diagnosing done in connection with re¬ storing the system to operability. Thus, if the system is faulted a service representative must be brought in to diagnosis the cause of failure so the machine can be repaired and restored to operation. As such, there is a need for a computer system that can automatically recover from a large percentage of the potential failure modes (i.e., recover without requiring operator/ service rep. action) . In particular, there is a need for a methodology that involves self-diagnosis by a computer of its and its components' functionally, as well as a computer being capable of de-configuring/ re- configuring system hardware to isolate the failed compo¬ nent (s) . Thus, allowing the computer to automatically continue system operation albeit in a possibly degraded condition. There also is a need for a computer system having such high availability design characteristics. SUMMARY OF THE INVENTION The methods and multi-processor computer system of the present invention result from the realization that availability of multiple processor computer systems is improved by designing the system so it automatically senses and diagnosis any of a number of failures that interrupt system operation. Further, upon diagnosing and isolating the failure that would prevent continued system operation, the computer system automatically de-configur- es the system so the isolated failed component/ sub-sys¬ tem is functionally removed from system. The computer system then automatically re-boots itself, the operating system and applications program. The computer system continues operation, albeit in a degraded condition, until the failed component is re¬ placed/ repaired by a service representative. However, and in contrast to other computer systems, this replace¬ ment can be scheduled around normal system operation (e.g., replacement during non-production hours) . In this way, repair and/or replacement activities are not criti¬ cal path issues to restoring system operability. In general, most systems, particularly multi-processor type of computer systems, can be operated in a degraded condi¬ tion with little or no real performance penalty. The computer system also is designed so a complete system diagnosis is performed in parallel at power-up by scanning the system (i.e, chips and boards) to identify any component/ sub-system failures. In this way, the system is verified as being in a run condition before any code is loaded. This is preferable to finding a faulted condition after the system has gone into operation. The scanning includes using integrated JTAG test logic, to locate open and short circuits at the chip and at the board level, as well as to determine the functionality of the application specific integrated circuits, processor and boards comprising the system. The scanning operation performed during power up also includes initializing any one of a number of the ASICs. This yields a simple, fast and low cost diagnosis and repair strategy that can be implemented in various stages or levels commensurate with the cost and type of use for the computer system. In its broadest applica¬ tion, the system automatically de-configures and re-conf¬ igures the system around virtually all failures that can lead to a system failure while providing accurate and complete fault isolation and detection. However, it is within the scope of the instant invention to tailor the amount of system redundancy required to allow continued system operation based on the intended use as well as to minimize the user's cost. In addition, to components of the processing opera- tion of the computer system, the system is configured to included N+l redundant blowers and power supplies. The power supplies are preferably grouped so each power sup- ply grouping supplies power to a discrete portion of the system. Preferably, there are N+l power supplies provid¬ ed for each group. The blowers and power supplies are hot repairable so they can be replaced in the field with- out shutting the system down. The high availability computer system further in¬ cludes a microcontroller mounted on each motherboard and a diagnostic bus that, in conjunction with an applica¬ tions program and board mounted components (e.g., scan chain, test bus controller) , perform diagnostic tests to determine the integrity of the system prior to the load¬ ing of any applications program. The application specific integrated circuits on each motherboard and daughter board include a gated balanced clock tree to supply the clocks to the logical flip/flops (F/F) . The clock tree includes a clock trunk with a plurality of branches extending therefrom. An AND gate is disposed in at least one of the branches and is under the control of control circuitry so that only certain clock pulses are passed through to the logical F/Fs. The control circuitry is configured so the AND gate automatically allows pulses to pass through the branches during a first operational condition of the computer system, i.e., normal system operation, and εo the AND gate blocks the pulseε when the system is in a second operational condition, i.e., when the system experiences a fatal error. The control circuitry is also configured so pulses are passed when the computer system undergo diagnostic teεting. The system also includes two redundant clock genera¬ tion and distribution circuits where one circuit is desi- gnated aε being the εource of system clocks. If a fail¬ ure to generate the clock pulses is identified, the clock generation and diεtribution circuitry automatically caus¬ es the system to failover to the redundant clock circuit¬ ry and the system returned to service. Preferably, the circuitry is mounted on each motherboard of the εyεtem. In a εpecific embodiment, the clock generation and diε¬ tribution circuitry on the motherboard in slot 0 of the backplane is the normal source of system clockε and the backup source iε the circuitry mounted on the motherboard in εlot 1. In εum, the above methodology of the inεtant inven¬ tion yieldε a high availability computer syεtem that can be configured baεed on the intended uεe and coεt of the εystem. Thus, the amount of system redundancy required to allow continued system operation can be tailored to the use as well as to minimize the user's cost. Such syεtems allow the repair or replacement of failed compo¬ nents to be scheduled for those times where it would have the least impact on the user. DEFINITIONS The instant invention is moεt clearly understood with reference to the following definitions: "ASIC" shall be underεtood to mean application spe- cific integrated circuit. "Board Maεter JP" εhall be understood to mean the lowest-numbered functional job processor/ central pro¬ cessing unit on each motherboard. The board master is determined by running isolated board-level tests. "Degrade", and the related terms, εhall be under¬ εtood to mean the loεε or removal of a component, e.g., a FRU, from a computer εystem. An actual reduction in operation or performance of the computer system may or may not occur with the loss or removal of the component. "Diagnostic Master JP (DM) " shall be understood to mean the job procesεor/ central processing unit in the syεtem that coordinateε all inter-board teεting and in control when the εystem first halts into the main user interface. "Fault detection" shall be understood to mean the ability to recognize that a failure has occurred and that current system data may be corrupted. "Fault Isolation/ Isolation of Fault", and the re¬ lated termε, εhall be underεtood to mean the ability to identify the location of the failure to εome level of definition. Isolation may be defined at the syεtem, sub- syεtem, board, component, FRU or sub-FRU-level. "FRU" εhall be underεtood to mean field replaceable unit. The field replaceable unit is a component (e.g., board, daughter board, bus, power supply, blower) of a computer syεtem that iε deεigned to be removed and re- placed aε a unit in the field by a field εervice repre¬ εentative (i.e., not repaired in field) . "Master Microcontroller" εhall be understood to mean the microcontroller in the system that does baεic sizing of which boards exist and teεts off-board scanning, in- eluding the midplane SEEPROM. "Scannable Mailbox" shall be understood to mean a register accesεed through the DBUS by microcontrollers as a means of communication. "SEEPROM" shall be underεtood to mean Serial Elec- trically Erasable Programmable Read Only Memory. There is one of these on each FRU except for SIMMε. "TCK" εhall be understood to mean test clocks, the IEEE 1149.1 Test Clock signal. "TMS" shall be understood to mean the IEEE 1149.1 Test Mode Select signal. "TDI" εhall be understood to mean the IEEE 1149.1 Test Data In εignal. "TDO" εhall be underεtood to mean the IEEE 1149.1 Test Data Out signal. "TRST" shall be underεtood to mean the IEEE 1149.1 Teεt Reset signal. BRIEF DESCRIPTION OF THE DRAWING For a fuller understanding of the nature and desired objects of the present invention, reference is made to the following detailed description taken in conjunction with the accompanying drawing figures wherein like reference character denote corresponding partε throughout the εeveral viewε and wherein: FIGS. 1A-C is a high level flow chart of the high availabi¬ lity methodology for a multiple parallel processor; FIG. 2 is a high level block diagram of the high availability computer syεtem of the inεtant invention; FIG. 3 is a block diagram of a motherboard for the computer system of FIG 2; FIG. 4 is a block diagram of one daughter board for the motherboard of FIG 3; FIG. 5 iε a block diagram of the PLL gated balanced clock tree for an ASIC of the inεtant invention; FIG. 6 is a hierarchial depiction of the BCT; FIG. 7 is a block diagram of the PLL module of an ASIC according to the instant invention; FIG. 8 is a block diagram of the circuitry/ logic for the ASIC internal reset and clock generation; FIG. 9 is a block diagram of the clock generation and detection circuitry/ logic of the instant invention; FIG. 10 iε a block diagram of the clock failure detection circuitry; FIG. 11 is an exemplary block diagram of the distri¬ bution of clocks to the motherboard and daughter boards; FIG. 12 is the scan chain/ scan logic for the mothe¬ rboard located at position "0" on the backplane; FIGs. 13A, B is a tabulation of power up tests per¬ formed by the microcontroller; FIGε. 14 is a tabulation of the power up teεtε per- formed by the job proceεεor (JP) ; FIG. 15A, B iε a tabulation of the power up tests performed by the diagnostic maεter JP; and FIG. 16 iε a tabulation of the power teεtε performed by the diagnostic mater JP. DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to the various figures of the drawing wherein like reference characters refer to like parts, there is shown in FIGS. 1A-C a flow chart of the high availability methodology for a multiple processor comput¬ er syεtem of the inεtant invention. The computer syεtem and aεεociated methodology of the inεtant invention yields a system that succeεεfully detectε a failure event occurring while running the uεers application code, iso- lates the event to at least a FRU, de-configureε the FRU/ faulted component, rebootε the operating εyεtem and rebo¬ ots the user application code. Thiε proceεε of detec- tion, isolation, de-configuration and rebooting is per¬ formed automatically by the computer syεtem without re¬ quiring uεer/service representative interaction/ input. When the computer syεtem iε being powered-up or εtarted, εtep 100, the power εyεtemε controller performs a number of functions. This includeε bringing operating voltageε to nominal valueε, bringing the blower fanε up to normal speed and appropriately clearing any diagnostic interrupts or other status under its control. While in this mode, other functionε of the computer system are inhibited. It should be noted, that syεtem operation is not limited to the illustrative sequence of operations, but rather operations may be performed in parallel and/ or in a different sequence. When the system is started up, a syεtem clock pro¬ vides the clocking signals (i.e., clocks) required for proper syεtem operation. Aε described hereinafter, the clock circuitry/ logic 256 (FIG. 3) monitors the opera¬ tion of the normal εyεtem clock εource and provideε a clock fail output when the normal εyεtem clock εource failε, step 102. The system clock monitoring function is begun at power-up and continues during all modes of sys¬ tem operation until the system is powered off. In a preferred embodiment, the computer syεtem in- eludes redundant or back up clock circuitry/ logic so the computer syεtem can withεtand a εingle system clock fail¬ ure. Thuε, if a failure of the normal εyεtem clock source is identified, the computer system automatically redesignates the redundant clock circuitry as being the deεignated source for εyεtem clocks, step 104. It should be noted that the failure of the clock circuitry/ logic 256 on the slot 0 motherboard, doeε not automatically require the εlot 0 motherboard to be functionally deconf¬ igured from the εyεtem. Becauεe a loss of the system clock is an irretrievable failure, the computer εystem automatically returns to the beginning of the diagnostic teεting proceεε. For purpoεes of the present invention, such an automatic re-start of the syεtem will be referred to aε a cold reεet of the εystem. However, this cold reset does not involve removing and re-establiεhing power to the system. Assuming that no other syεtem faultε are diεcovered during the cold reεet power up proceεε, aε deεcribed below, the operating εyεtem will be automatically booted and re-invoked. Alεo, aε part of the εyεtem εtart up proceεε, meεεageε are εent to the user and local service center regarding the clock failure. In sum, the above deεcribed clock failover proceεε iε performed automati¬ cally by the εyεtem without requiring the uεer to inter¬ vene and εwitch the clockε. When the above initial power-up proceεε iε complet- ed, the computer εyεtem iε released to perform a number of diagnostic testing and evaluation operations. These operations check out variouε componentε (e.g., chipε, boardε, buses) to verify the integrity and operability of the computer system prior to the loading of applications (e.g., the operating syεtem) . In a preferred embodiment, the computer εyεtem is designed to include integrated JTAG teεt circuitry/ logic and scan chains εo the diag- noεtic teεting and evaluation can be automatically per¬ formed by the εystem. Specifically, the computer system checks for elec¬ trical continuity (i.e checkε for εhorts and opens) at the board and chip level, step 110. In addition to the continuity checks, the computer performs functionality checkε, e.g., to identify a hard εtuck, step 112. All components identified as being faulted are so tagged. If there are faulted componentε (YES, step 114) , then the computer syεtem attempts to de-configure the faulted components εo they are not logical or operation¬ ally functional components of the computer syεtem, εtep 116. The computer εystem as a practical matter should not de-configure itself below the minimum number of com- ponents required for system operation. For example, the syεtem cannot functionally remove the laεt εyεtem board. If de-configurement of the computer εyεtem iε not poεεi¬ ble (NO), then the εyεtem shuts itεelf down, εtep 118. If the computer system can be de-configured (YES, step 116) , then the computer εyεtem takeε the neceεsary actions required to remove the faulted component, func¬ tionally and operationally, from the syεtem, εtep 120. The computer εystem preferably operates so fault isola¬ tion is at least to the FRU which failed or to the FRU on which the component believed to be faulted is located. Iεolation to the FRU makes the diagnosis and fault isola- tion procesε accurate, faεt and complete. The εystem also updates a syεtem memory chip (e.g., EEPROM) to iden¬ tify the active and de-configured componentε including a failed syεtem clock. After de-configurement iε completed, the proceεε and computer system returns to re-performing the diagnostic tests, steps 110-114. Thus, the operability and integri¬ ty of the de-configured εyεtem iε verified prior to load¬ ing of the applications. The diagnoεtic teεting and evaluation process is repeated until there are no faults identified or a system shutdown iε required. If no further faults are detected, or if there was no fault detected in the initial diagnoεtic tests (NO, step 114) , then the system proceeds to load the operating syεtem, step 122. If the operating system is succeεεful- ly loaded (YES, εtep 124) , then the computer εyεtem iε available for uεe, namely to load and run the applica¬ tions program(s) of the uεer(ε), εtep 126. Aε provided in the following, the εyεtem outputs a mesεage about deconfigurement or εhutdown to the user and, preferably, to the appropriate service center. Thiε includes adviεing of a failed εyεtem clock (i.e., losε of redundancy) . In thiε way, the εervice center and uεer are informed of the failure. Also, thiε allows the uεer and εervice center to εchedule the replacement of the component at a time that iε convenient for the uεer. While the applicationε program(ε) is being run, the computer system is monitoring for errors that may be representative of the presence of a faulted component (s) . If no errors are detected (NO, step 128) , then the uεer continues to run the applications program. If an error iε detected (YES, step 128) , then the operating syεtem and/ or the computer εystem determineε if the error is fatal or non-fatal, step 130. Non-fatal errors are those errors that do not result in an immediate shutdown of the computer system and/ or irretrievable corruption of information, data or state. An example of a non-fatal error iε a single bit error. Fatal errors on the other hand are those errors that indicate the potential failure of component which would cause a system shutdown, those where the program running has crashed or hung or a failure in which there is a corruption of information, data or state. An example, of a fatal error is when the watch dog timer for a given operation/ component times out indicating a hung condi¬ tion. If the error is determined to be fatal (YES) , then the computer εyεtem iε put in a condition to save comput¬ er syεtem information εuch aε that found in the εyεtem's memory and in component buffers/ registers, εtep 150. As discussed below, the board mounted ASICs include regis¬ ters for storing state or bus transaction information. Also, the ASICs are in general configured to maintain their state when a fatal error iε detected. However, saving this information does not require the system clockε to be frozen aε iε required with a number of prior art suggested techniques. In this way, the syεtem auto¬ matically saves information that can be later used, e.g., in the manufacturing/ repair facility, to identify the failed component/ failure cause. After placing the system in its save information condition, the computer syεtem retrieves the information concerning the state of the system step 152. Preferably, this is accomplished using the integrated JTAG test log- ic/ circuitry and scan chains to scan the information out of the variouε registers/ buffers and ASICs Flip/Flops (F/Fs) in the syεtem. After retrieving the information, a warm reset is asserted, step 154. The computer system/ operating syεtem, where posεi- ble, alεo take those actions that can resolve the identi¬ fied error so the computer syεtem may be re-εtarted by the warm reεet for the purpose of retrieving the memory's contents. As such, if the warm reset is succeεεful (YES, εtep 156) , then the computer εystem causes the memory to be dumped and saved, e.g., in the system's hard drive. After completing the memory dump, or if the system faults again after assertion of the warm reset (YES, step 156) , then the process returns to performing the system diag¬ nostic evaluation process, step 102 (i.e., a cold reεet asserted) . Thus, before system operation is continued, computer system integrity and operability is again veri- fied. If the error iε non-fatal (NO, εtep 130) then the computer εyεtem/ operating system takes the necesεary ac¬ tions to correct or reεolve the initially identified error, εtep 132. For example, re-obtaining/ re-writing the data involved in the single bit error. For some non- fatal errors, the computer system/ operating system, as part of this procesε, alεo determineε if the occurrence of non-fatal errors has exceeded a threshold criteria. If yes, then a notation is made so the component or re- lated FRU is de-configured during the next power-up or cold reset of the system. For example, if the single bit errors for a given SIMM exceed the threshold limit, then the SIMM is tagged for later de-configurement. The oper¬ ation of the computer system and the running of user applications program is continued (i.e., computer system not shutdown) . There is shown in FIG. 2 a high level block diagram of the high availability multi-procesεor computer system 200 of the instant invention. The multi-processor com- puter system 200 of the instant invention preferably employε a CC-NUMA architecture as described in a co-pend¬ ing commonly assigned U.S. patent application Serial No. 08/ , entitled "SYMMETRIC MULTIPROCESSING COMPUTER WITH NON-UNIFORM MEMORY ACCESS ARCHITECTURE" (Attorney Docket No. 46, 585, filed August dy, 1996) the teachings of which are incorporated herein by reference. The multi-proceεεor computer system 200 includes a plu¬ rality of board complexes or motherboards 202a-h that are each interconnected to the four busses 208a-d that make up the PI BUS 208. The PI BUS 208 is the bus traversing the backplane and interconnecting all the motherboards of the syεtem. The four buεεes 208a-d allow information, data and instructionε to be communicated among and be¬ tween the motherboardε. Each motherboard 202 also in¬ cludes a diagnostic bus interface (DBI) 204 that inter¬ connects each motherboard to the diagnostic bus (DBUS) 206. While the illustrated computer syεtem includeε 8 motherboardε 202a-h, this is not a limitation aε the εyεtem can be configured with at leaεt two motherboards. Referring also to FIG. 3, a block diagram of a moth- er- board, each motherboard 202 includes two job procesεor (JP) daughter boardε 250a,b that are plugged into the mother¬ board; a memory εubεyεtem 252, an I/O subεyεtem 254, clock circuitry/ logic 256, a buε/ PIBUS interface εub- system 258, and local resourceε 260. The clock circuitry 256 included with the motherboardε at εlot 0 normally generates and selectively provideε system and test clocks to the motherboardε in all backplane positions/ εlots. The clock circuitry/ logic 256, including its distribu¬ tion, is discussed further below in connection with FIGS. 9-11. Similarly, the job processor daughter boards 250a- ,b will be discusεed below in connection with FIG. 4. The memory εubεyεtem 252 on each motherboard 202 in¬ cludeε a plurality of SIMMs 270, two Error Detection and Correction Unit ASICs (EDiiAC) 272, a directory 274 and a memory controller ASIC (MC) 276. The memory subsystem 252 is capable of providing up to 512MB of syεtem memory on each motherboard 202 for the computer εystem 200. Actual random access memory storage iε provided by up to eight (8) 16Mx36 εtandard SIMMs 270 provided on the moth¬ erboard 202. The motherboard 202, however, can be popu- lated with 4 or 8 SIMMs. Memory data is protected using ECC which is generated/ corrected uεing the two EDiiAC ASICs 272. Each EDiiAC provides a 64 bit data path and the two are used to interleave with a cache block. The memory εubεyεtem 252 also includes a storage for the directory 274 which is used to maintain cache coher¬ ency. The directory 274 includes 4Mx4 dynamic random accesε memorieε that are mounted to the motherboard 202. The ECC codeε for both the directory and the main data store (i.e., the SIMMs 270) are capable of correcting all single-bit errors and detecting all double-bit errors. The MC ASIC 276 controlε the execution of physical memory operations. This involves managing both the di- rectory 274, which maintainε εyεtem coherency, and the memory data εtore SIMMs 270. The MC ASIC 276 procesεeε memory tranεaction packetε that are driven onto the MCBUS by the BAXBAR 292. The I/O εubεyεtem 254 on each motherboard 202 in¬ cludes two I/O subsystem interface ASICs (GG) 280, two Peripheral Component Interface (PCI) expansion cards 282, two Small Computer System Interfaceε (SCSI) 284, and one Local Area Network (LAN) interface 286. Each of which are mounted to the motherboard 202. The I/O εubεyεtem 254 of each motherboard 202 com¬ priεes two independent PCI channels operating at 25MHz. Each PCI channel is interfaced to the GG bus of the buε/ bus interface εubεyεtem 258 by meanε of a GG ASIC 280. Each GG 280 containε an integrated cache for I/O trans- ferε and also contains all the necesεary logic to provide the interface between the GG bus and the PCI buε, includ¬ ing PCI arbitration. The GG 280 alεo serves as a gather¬ er of interrupts from the motherboard and connected pe- ripherals and combines these interruptε and directε them to the appropriate job proceεsor (JP) on a JP daughter board 250a,b by means of a bus packet. Each of the two PCI busses is connected to an inte¬ grated SCSI interface 284 and to a single PCI expansion board 282. One of the two PCI buεεeε also is connected to an integrated 10Mb LAN interface 286. The two SCSI in¬ terfaces are implemented using an NCR825 Integrated PCI-- SCSI controller as a pair of Wide Differential SCSI-2 interfaces. Each controller is connected through a set of differential transceivers to the 68pin High Density SCSI connector on the airdam. No onboard termination of the SCSI bus is provided allowing the connection of the motherboard 202 into Multi-initiator or other SCSI clus¬ ter configurations. The single LAN connection is made using the DECchip 21040 PCI-Ethernet controller. Thiε provideε a εingle chip integrated LAN which is connected to an RJ-45 connector on the airdam. The bus/ PIBUS interface subsyεtem 258 on each moth¬ erboard 202 includeε four PIBUS interface ASICS (PI) 290, a croεεbar εwitch (BAXBAR) 292 that serves as the inter¬ connect path for the motherboard level busεeε, an arbi- tration ASIC (ORB) 294 and a plurality of board level busses. The ORB ASIC 254 controls arbitration for the motherboard level buses and controls the BAXBAR bus tran¬ sceiver. The BAXBAR (BB) 292 is implemented as four ASICS and includes a mode switch to select between the ORB ASIC functions and the BAXBAR ASIC functions. The primary communication between job proceεεorε acroεε the backpanel iε accomplished using the PIBUS Interface portion of the bus/ PIBUS Interface εubsystem 258. A single PIBUS 208a consiεtε of a multiplexed 72-b- it Address-CTRL/ Data bus and asεociated arbitration and control εignalε. Each motherboard 202 includeε 4 identi¬ cal Pis 280, where each PI is interconnected to one of buses 208a making up the PIBUS 208. Traffic is parti¬ tioned across the four busses 208a-d, so that each bus iε approximately equally utilized. Aε indicated above, the subεyεtem 258 includeε a plurality of board level buses. The following lists each of the individual busses and includes a brief deεcription for each. RI bus: Bus that interconnects the BAXBAR 292 to the Resources Interface ASIC (RI) 306 and to the debug buffers/ debug connector. GG bus: Bus that interconnects the BAXBAR 292 to the two GG ASICs 280. MC Bus: Bus that interconnects the BAXBAR 292 to the MC ASIC 276. CI 0 Bus: Bus that interconnects the BAXBAR 292 to the Cache Interface ASIC (CI) 414 that is mounted on the JP 0 daughterboard 250a. Cl 1 Bus: Bus that interconnectε the BAXBAR 292 to the Cache Interface ASIC (CI) 414 that iε mounted on the JP X daughterboard 250b. PIX Buε: Buε that interconnects the BAXBAR 292 to the four PI ASICs 290. MUD L, MUD H Bus: The two busεes that interconnect the BAXBAR 292 to the two EDiiAC ASICs 272 of the memory subεystem. Each motherboard 202 contains all the local resourc- eε that are required of the εystem, with the exception of the System ID PROM 204, which is contained on the backpa- nel. The local resources 260 includes a microcontroller (uC) 300, EEPROMε 302, SRAM, NOVRAM, DUARTs, SCAN inter¬ face logic 304, MACH logic, and a Reεourceε Interface (RI) ASIC 306. Although the local resources 260 is du¬ plicated on each motherboard 202, the computer εyεtem 200 only uses the local resourceε εection of the board in either εlot 0 or slot 1 on the backplane as the syεtem wide Global Reεourceε. The RI ASIC 306 provideε the interface between the RI Buε/ BAXBAR 292 and the deviceε within the local resources 260. The microcontroller 300 performs low-level early power-up diagnoεtics of the syεtem prior to de-asserting RESET to the JPs on the JP daughterboardε 250a,b. It also is the controller/ engine used for all scan opera¬ tions. If a JP 400a,b on a daughterboard 250a needs to do a scan operation, it makes a request to the micro-con¬ troller 300 which then performs the required operation. Scan alεo iε used to configure the ASICs during power up, communicate with the power supplieε and blowerε, communi¬ cate with the variouε ID PROMs within the system, and to dump failure information after a hardware fatal error. There are four 512Kx8 EEPROMs 302 that store all the JP 400a,b and microcontroller 300 firmware. The EEPROMε 302 alεo contain the appropriate teεt vectors for per¬ forming JTAG scan testε during power-up. A 512Kx8 SRAM iε included in the local reεourceε 260 to be uεed as scratchpad RAM for early power-up and for microcontroll¬ er stack space. A 128Kx8 NOVRAM/RTC is also provided to give an extra area for storing critical information in non-volatile storage and to provide a real-time clock for the system. The local resourceε 260 provideε the DUARTs for implementing the three required UART ports for the syε¬ tem. The fourth UART port also is used as part of a loopback circuit to allow a JP to monitor what iε being driven on the main εyεtem conεole. In addition, the local reεourceε εection 260 also provides the logic 304 to do JTAG baεed εcanning of all the board mounted ASICε, the power εupplieε, the blowerε, the SEEPROM and SYSID PROM. The logic iε in place to allow the system to be scanned either during manufactur¬ ing test using an external tester or during normal opera¬ tion/power-up uεing the microcontroller 300 on the motherboard 202. Thiε logic allowε εimple boundary scan testing to be used as part of the power-up system testing to detect and isolate posεible faulty components (e.g., FRUs) . Additionally, the MACHs on the resource buε can be programmed uεing its JTAG interface from an external connector. Also, the microcontroller can be uεed with an external connector to program the EEPROMs on the reεource buε. Thiε allowε manufacturing to aεsemble the boards with blank MACHs and EEPROMε and then "burn" them as part of the teεt procedure, rather than εtocking "burned" verεionε of the parts to be inεtalled during aεsembly. This "incircuit programmability" feature also makes up¬ dates for ECO activity as simple as plugging in the pro- gramming connector and re-programming the parts, rather than removing the old part and inεtalling a new part in its place. Referring back to FIG. 2, the computer syεtem 200 also includes a group of three power supplies 210a-c for each pair of motherboards 202, three blowers 212 that cool the system, and a system ID SEEPROM 204. When there are eight motherboards 202, there iε a total of 12 power supplies. The three power supplieε 210a-c in each group repreεentε N+l redundant power εupplieε for the pair of motherboards. Also, the three blowers 212 represent N+l redundant blowers for the syεtem 200. The power εupplieε 210a-c for each group alεo are interconnected to each motherboard 202 of the correεpond¬ ing pair of motherboardε. In thiε way, and as described below, each motherboard 202 haε the capability to ascer¬ tain (e.g., scan, diagnose) the operability statuε of the power supplies for that pair of motherboards. The blow¬ ers 212 also are interconnected to the motherboards 202 in slotε 0 and 1 on the backplane. In thiε way, and aε deεcribed below, the motherboardε 202 in theεe εlotε have the capability to aεcertain (e.g., scan, diagnose) the operability statuε of the blowerε 212. The System ID SEEPROM 204 provides a non-volatile place to store important system information such as seri¬ al number and back panel configuration. Because the System ID SEEPROM 204 does not have a true JTAG inter- face, it cannot be connected directly to a IEEE 1149.1 scan chain (see discussion below) . Thus, a buffer is used to provide the interface between the two εerial protocolε. Referring to FIG. 4, there iε shown an exemplary block diagram for a JP procesεor daughter board 250. Each JP daughter board includes two 50 MHz Motorola 88110 central proceεεing units or job procesεorε (JPε) 400a,b, each JP having aεεociated therewith 1MB of εtatic random access memory (SRAM) as a level 2 cache 402a,b and a 88410 cache controller (SLCC) 404a,b. Alεo mounted on each daughter board 250 is 16MB of dynamic random accesε memory (DRAM) , a third level cache (TLC) 406 and a third level cache controller (TLCC) ASIC 408 which controls the TLC. The third level cache 408 is shared by both JPs 400a,b. The DRAMS are protected by ECC, which iε gener¬ ated and checked by two EDiiAC ASICS 410 that are under the control of the TLCC ASIC 408. The cache tags for the third level cache 406 are stored in a SRAM 412. Each JP daughter board 250 also includeε a Cache Interface (CI) ASIC 414. The main function of the CI ASIC 414 is to serve as a translation/ sequencer between the packet-εwitched local buε protocol on the motherboard 202 and the 88410 cache controller buε protocol on the JP daughter board 250. All off JP daughter board communica¬ tionε, with the exception of clockε and reεet, are part of the motherboard level buεes and the CI is directly connected to the CIBUS. The two EDiiAC ASICs 410 are interconnected to the daughter board level buses via six ABT16260 latching 2:1 muxes 416. For purpoεes of multiplexing, the 32 bit S A Bus and the 32 bit S D Bus are multiplexed into the S AD bus by meanε of four LVT162245 buε crossovers 418. Each daughter board 250 includes a SEEPROM 420 that provides a non-volatile place to store important daughter board information εuch aε the board number, εerial number and reviεion hiεtory. Becauεe the SEEPROM 420 doeε not have a true JTAG interface, a buffer 422 is used to pro¬ vide the interface between the two serial protocols. Each of the above described ASICs useε a Phaεe Locked Loop (PLL) baεed "gated" balanced clock tree (BCT) deεign, aε εhown in FIG. 5. ASIC clock control iε han- died by the Teεt Acceεs Port (TAP) module and ASIC Clock/ Reset (CLK RST) module 602 of each board mounted ASIC. The BCT circuitry/ logic 600 includeε a clock trunk 604 that haε a plurality of brancheε therefrom. All but one of these is a gated branch 606 that includes an AND gate 608 which iε controlled by the enable function ASIC_CLK_- EN from the CLK RST Module. FIG. 6 illuεtrateε how the BCT iε connected in the ASIC hierarchy (GIOOO level) . The uncontrolled branch 610 is a "free running" leg of the clock tree and it provides a delayed clock input to the PLL 612 for clock deskewing. The clocks being inputted to the PLL 612 are paεεed through a delay cell 614, that adjust the feedback clocks so they are repre¬ sentative of the travel time delay through a set branch length. Preferably, the delay cell 614 is configured/ set so the expected travel times or branch line lengthε for the longest and εhortest branches lieε within the acceptable range for the set branch length/ time. As such, the PLL feedback path is always active so the PLL 612 can stay in synch with the ASIC's reference clock input CLK. The uncontrolled branch alεo feedε a LOOP- BACK_CLK 616 to the Clock Reεet (CLK RST) module 602 that iε used for εynchronization of the Teεt clocks (TCK) . The PLL module, as shown in FIG. 7, is a common module for all system ASICs that use the above described BCT ASIC design. The ATE_TEST input is uεed to control teεt modeε for the VCO logic. The EN, TSTN and IDDTN εignalε need to be controlled at the ASIC pin level dur¬ ing manufacturing package teεting εo all PLL baεed ASICε provide theεe pinε diεcretely or share this pin with some other input pinε. Thiε εaveε on pin count. The ATE_TEST input pin iε uεed to enable shared pins pin level control of these signals. For example, the Pl shares the EN func¬ tion with the PI_ORDERED_OP input and the IDDTN function with the PI_MED_CUSTOMER input. The ASIC Clock/ Reset (CLK RST) module 602 generates the ASIC internal reset and clock signals as well as the enable function (ASIC_CLK_EN) which causeε the F/Fε in the ASIC deεign to see only certain clock pulses. There is shown in FIG. 8, a block diagram of the circuitry/ logic for ASIC internal reset and clock generation. The CLK RST module 602 for each ASIC operates in one of three modes; Normal Mode, Scan Mode and Reset Mode. If not in one of these three Modes, then the CLK RST module gener¬ ally acts so as to maεk out or block the clockε from reaching the F/Fε in the gated brancheε 606. In the Normal Mode, the CLK RST module 602 continu¬ ously generates the ASIC_CLK_EN enabling function. Thuε, the AND gates 608 in the gated branches 606 of the BCT are configured εo the clockε paεε therethrough. If a FATAL_IN_N iε asserted by the computer system 200, then the gates 608 for all board mounted ASICs, except for the MC ASIC 276 (FIG. 3) , are re-configured so as to block or mask out the clocks. Eεεentially, the ASIC_CLK iε free- running until the ASIC experienceε an aεεertion of FA- TAL_IN_N. The clockε remain blocked/ masked out until the Scan Mode or Reset Mode is entered. In the Scan Mode, the JTAG TAP controls the ASIC clocks. ASIC_CLK is allowed to pulse once every 80 nano seconds (nsec), but only if the TCK_EN enable signal is asεerted from the TAP. The Scan Mode overrideε Reset Mode or Normal Mode. When in Reset Mode, the ASIC__CLK also is allowed to pulεe once every 80 nεec. Thiε allowε the board mounted ASICS to be εynchronized and reset all at the same time. The Reset Mode overrides the Normal Mode. When either the reεet or scan inputs to the CLK RST module 602 is aεεerted, the clockε generally are εwitched from the normal system clocks (SYS CLK), e.g., the 50 MHz clocks, to the teεt clockε (TCK), e.g., the 12.5 MHz clockε. However, for the MC ASIC 276, only a COLD_RESET_N will εwitch the clockε; WARM_RESET_N will be regiεtered on TCK mode and iε expected to make εetup to all flops in one 20nεec cycle. The clock enable iε generated εuch that the ASIC_CLK will εwitch from SYS CLK to TCK at the end of the TCK cycle in which the external reεet iε aεεerted. The inter¬ nal reset εignalε will not assert until two TCK cycles after the external reset assertε. When the external reεet iε deasserted, the internal reset deasεertε two TCK cy- cleε later. The TCK_EN is used for scan functionality. It must be aεserted in order to pass TCK through the clock gating logic. TCK_EN is generated in the TAP controller. As such, there are three basic modes of clock opera- tion that affect the internal flip/flop (F/F) clocks. The first mode is where all of the logical F/F clocks are synchronized to the CLk/CLK_N input clocks phase uεing the on chip Voltage Controlled Oscillator (VCO) in the CM_PLL module. The second mode is where the internal F/F clocks are stopped on detection of an error detected via X_FATAL_IN_N input pin. Thiε is done for all board moun- ted ASICs except the MC ASIC 275 (FIG. 3) . The last mode iε where a particular TAP inεtruction is loaded into the TAP instruction register and resultε in the internal F/F clockε being clocked in phaεe with the TCK input pin when the TAP controller is in the "Capture-DR" and "Shift- DR" TAP states. This last mode of operation iε uεed to εcan initialize or scan dump the ASIC εtate. In εum, the "free running" running leg of the clock tree allowε the internal F/F clocks to be stopped on detection of a fatal error while keeping the system clocks running and the PLL maintained in synch with the ASIC's reference clock input CLK. As such, when an ASIC iε being scan dumped for its state, the ASIC clocks will be in sync with the clockε of the computer εyεtem. Thiε is in comparison to known BCT designs where such a clock stop/ restart would require the PLL to re-sync itεelf and thuε prevent scan dumping of the ASIC state. Such a deεign alεo allowε the εystem clock to continue providing clock signals to the other components of the computer system (e.g., microcontroller 300- FIG. 3) particularly those that are used for scanning and diagnosing of the computer system following receipt of a fatal error as hereinafter described. Aε indicated above, the internal F/F clocks of the MC ASIC 276 (FIG. 3) are not stopped by a X_FATAL_IN_N input. Thiε iε done becauεe stopping the internal F/F clocks would destroy the memory image being stored on the motherboard 202 (i.e., interfere with memory refresh) . The memory image is maintained so the core can be dumped which is required for operating system (i.e., DG/UX) debug. The MC ASIC 276 does εupport a mode where the internal F/F clockε can be εtopped for lab debugging. On receipt of an X_FATAL_IN_N input repreεentative of the detection of a fatal error εomewhere in the εyε¬ tem, the MC ASIC 276 will abort the current operation and will remain idle except for refreshing the memory (i.e.,- DRAMε/ SIMMε) . The MC ASIC'ε input and output queues are cleared and some internal εtate machines are reset to idle. The MC ASIC will not respond to any bus activity until it receives a warm reset. After the warm reεet, the MC ASIC'ε control-εpace registers can be read to get error information that was saved when the fatal error was detected. Because the MC ASIC 276 cannot be scanned to collect information about a fatal error, it freezeε copieε of εome of itε current state into shadow registerε when a fatal error occurε. Shadow regiεterε are copieε only and freezing them doeε not affect normal ASIC behavior. Many of theεe εhadow regiεterε are control space accesεible. The information in the εhadow regiεterε remains valid through a warm reset and will not change until after the error regiεterε have been cleared by εpecific control εpace writeε. The other ASICε on the motherboard 202 and the daughter boards 250a,b also include εhadow regiεterε for freeze copying εome εtate information therein. When a fatal error originateε at the MC ASIC 276, the MC ASIC immediately freezeε shadow copies of internal εtate relating to the operation currently being executed. Thiε allowε state to be captured before it advances with- out using εeveral levels of shadow registers. Shadow registers containing less volatile state are not frozen until the MC ASIC generated fatal error is sent back to the MC ASIC as a syεtem fatal error. As indicated above, and for purposeε of maintaining a high level of availability, the computer εystem 200 of the instant invention includes redundant εyεtem clock circuitry/ logic. Preferably, the clock circuitry/ logic 256 generateε the system clocks and test clocks, monitorε the clockε being generated to identify a failure of the clock generation and diεtribution circuitry and iε pro¬ vided on each motherboard 202. Such circuitry and logic iε provided on each motherboard 202 at leaεt to simplify manufacturing and the stocking of εpareε. In a εpecific embodiment, the computer εyεtem and test clocks are sour- ced to the clock circuitry/ logic 256 on one of the moth¬ erboards in backplane slots 0 and 1. In this arrange¬ ment, circuitry/ logic on the motherboard in slot 0 nor- mally sources the system and test clocks and the circuit¬ ry/ logic on the motherboard in slot 1 is the backup clock source. There is shown in FIGS. 9-10, the clock circuitry and logic that generateε the εyεtem and teεt clockε aε well aε monitoring the clockε being generated to detect a failure. The manner in which theεe clockε are diεtribut¬ ed to a motherboard 202 and itε JP daughter boardε 250a,b is shown in FIG. 11. The clock circuitry/ logic 256 includes two oscilla¬ tors. The primary oscillator 500 is for the normal clocks and in a specific embodiment is a 100 MHz crystal. The other oscillator, the margin oscillator 502, provides a 5% fast margin feature and in a specific embodiment is a 105 MHz cryεtal. Each of the oεcillators 500,502 drives a divide by two circuit 504 to generate a 50% duty cycle clock (e.g., 50 MHz and 55 MHz clocks) . The out¬ puts of the divide by two circuits 504 are inputed to a two to one mux 506, which is preferably configured so its output is the normal clockε (e.g., 50MHz clockε) . Howev¬ er, the two to one mux 506 doeε allow the clocks to be sourced by the margin crystal 502. The clocks from the two to one mux 506, the system clocks, are provided to an Elll one to nine clock fanout circuit 508. One output from the one to nine fanout circuit 508 is feed to an E431 divide by four circuit 510 that iε driven to form the teεt clockε synchronizing signal (test clock εync εignal) which in turn iε provided to an Elll one to nine clock fanout circuit 512. Both the system clock and test clock εync εignal drive their reεpective Elll fanout circuits 508, 512 so as to fanout and distribute the system and test clock sync εignal (across the back panel) to all the motherboards 202. All εyεtem clockε are fanned out with equal line lengths to all the motherboards 202 where they are routed through more Elll one to nine clock fanout circuits 514. These in turn drive the board mounted ASICs and TTL clock buffers which drive the JPs, SLCCs, EDAC'ε, FPGA'ε, and other elementε requiring TTL clockε. On each ASIC, the system and test clocks are automatically deskewed with a PLL, so the clock delay through all ASICs is compenεated. The TTL clock buffer, like the ASICε, alεo has a PLL to compenεate for both the delay through the buffer and for the etch and load on the bufferε. Similarly, the teεt clock εync εignal iε fanned out to all the motherboardε 202. The teεt clockε generated on the motherboard are fanned out to all componentε requiring a teεt clock via an Elll one to nine fanout circuit 512 and H641 PECL to TTL level translators 516. The test clocks are used for both scan and reset control and to control the resource εection of the boardε. The εyεtem clockε alεo are uεed to generate the PCI clocks on each motherboard 202. This is accompliεhed by inputing the system clocks to a divide by two circuit 518. The PCI clock preferably operates at 25 MHz and fans out to all PCI bus circuits, including the GG ASIC 280. The GG ASIC 280 synchronizeε the 25 Mhz clock with ASIC_CLK (ASIC's internal version of the System Clock) for use in gating the D inputs to internal F/Fs. This is accomplished by first clocking on a falling edge of ASIC- _CLK and then clocking on a leading edge of ASIC_CLK. The clock circuitry/ logic 256 alεo includeε clock failure detection circuitry 210 that εenses a stoppage of εignal pulεeε from the primary oεcillator 500 or distri¬ bution logic. The detection circuitry alεo is capable of senεing other failureε εuch aε a stuck high or low condi¬ tion. The clock failure detection circuitry 520 includes four E431 F/Fs 522a-d, two OR gateε 524 and an E431 di¬ vide by 2 F/F. An output from the E131 divide by two 404 for the margin clocks (e.g., 55MHz) provideε clock input for the E431 divide by two F/F 526. The output from the E431 divide by two F/F 526 provideε clock input for two of the E431 F/Fε 522a-b (i.e., setε the F/Fε) . The motherboard level clocks are also feed to the reset of theεe two E431 F/Fε 522. In thiε way, a failure of the primary oεcilla¬ tor 500 (e.g., no output) will result in the failure of the F/F reεet to be asserted. The OR gates 524 and the remaining E431 F/Fs 522c-d are interconnected to the outputs from the E431 divide by two 526 and the first two E431 F/Fε 522a-b εuch that, when there is a failure to generate system clocks from the primary crystal 400, the third E431 F/F 522c provides an output representative of the failure. The fourth E431 F/F 522d generates an output to the back panel to force εelection of the backup motherboard's clock circuitry logic 256, i.e., the slot 1 motherboard. The motherboard at either backplane slots 0 or 1 can switch or re-designate the source of the clocks from the normal clock source (i.e., circuitry on motherboard in slot 0) to the backup clock source. This is accomplished by the assertion of a wire-or PECL_MUX_SEL_OUT wire on the backpanel. The clock source is switched to the backup clock and the resources section on the motherboard desig- nated as the Diagnostic Master will force the system to go through COLD_RESET_N. Once the backup clock has been selected, the clock failure detection circuit 520 will continue to monitor the clocks εource from the backup clock circuitry/ logic. If a failure iε identified while the PECL_MUX_SEL_OUT is aεεerted, the microcontroller 300, on each motherboard 202 that detects the error, will activate the TN pins on all of the board ASICS. This tri-stateε the ASIC out¬ putε and eliminateε part damage due to extended bus fig- hting. If there is only one motherboard 202 in the com¬ puter system 200, and the clock fails, the clock failure detection circuitry 520 will cause the TN pins to be activated, thereby protecting the board components. Because the microcontroller 300 has the capability to switch clock sources from nominal to margin clocks, one can bring the motherboard 202 back on line at margin speed. The computer system 200 of the instant invention scans the boards, board mounted chipε, busses, blowers and power supplies comprising the syεtem to verify the integrity and operability of the εyεtem before applica- tions are loaded. Such scanning is done when the syεtem iε powered up and alεo after the εystem detects a fatal error. The scanning operation includes automatically detecting a fault, automatically isolating the fault to at least a FRU and automatically de-configuring the sys- tem so as to logically and functionally removed the iso¬ lated component/ FRU. After the syεtem iε deconfigured, the εyεtem automatically re-bootε itεelf and re-loads any applications program. In thiε way, the system has the capability to automatically recover the system after it has suffered a failure event without requiring interven¬ tion of the user or service representatives. The board mounted ASICs and the boards are designed with integrated JTAG IEEE 1149.1 test logic so test pat¬ terns can be shifted into one device, driven onto the logic board and captured at another device. In this way, board interconnect can be verified. The standard also provides for the verification of proper component selec- tion and proper device insertion. The computer εyεtem will implement both the boundary scan and full scan im¬ plementations of the IEEE standard. There is shown in FIG. 12 the scan the scan chains and aεsociated logic for a portion of the computer sys¬ tem, specifically those for the motherboard 202 located in slot "0" on the backplane. The scan chainε for the motherboardε in the other backplane slots are established based on the components which are to be εcanned by that motherboard (e.g., board/ board level components and power supplies) . Scan chains will be used as a basiε for test of the boards and board mounted ASICs. Board-level opens, adjacent pin bridging, proper component selection and insertion will be tested via 1149.1 boundary scan. Each motherboard 202 includeε a microcontroller 300 that is responsible for reset generation, scan-baεed powerup interconnect teεting and ASIC testing. The micr¬ ocontroller 300 εhares the Resourceε bus with the RI ASIC 306. When reset is firεt applied, the microcontroller 300 aεserts a signal to the RI ASIC 306 that forceε the RI ASIC off the Resources bus. The microcontroller 300 can then test the bus and use the Test Bus Controller (TBC) 700 for scan-based tests. Following powerup interconnect and ASIC scan-baεed tests, the microcontroller 300 deasε- ertε the control signal to the RI ASIC 306, allowing the RI ASIC to provide normal εystem accesε to the Resourceε bus and its associated devices. Scan chains will be used to identify all boards and board mounted ASICs in the computer syεtem. Specifical¬ ly, the presence of each motherboard 202 and the associ¬ ated JP daughter boards 250 will be detected and board serial numbers and the syεtem ID will be read via scan. Alεo, ASIC part numberε and revision numbers will be read on powerup via εcan. For EEPROMS and SEEPROMS, a buffer iε included so information can be extracted during the scanning process. Scan chains also are used to communicate with the power supplies 210a-c and the cooling blowers 212. Power εupply status functions, e.g., turned on, over tempera¬ ture, over/under voltage, and disabled, and control func¬ tions, e.g., fault masks and disable, are alεo performed through εcan. Blower εtatuε, e.g, high εpeed, low speed, ambient over temperature, turned off and control, e.g., fault masks, speed up, disable) is communicated through εcan. The εcan interface part iε the Test Bus Controller (TBC) 700, an off the-shelf part no. 74ACT8990 available from TI (see also Texas Instruments, Advanced Loσic and Bus Interface Logic Databook" . 1991) . The TBC 700 func¬ tionε aε an 1149.1 controller, where parallel data iε written to and read from the TBC, while serial 1149.1 data is generated and received. The TBC resides in the local resources 260 of each motherboard. The microcontr- oiler 300 uses the registers inside the TBC to perform system scan operations. To perform a scan operation, the PROM code loaded in the microcontroller accesses the registerε inεide the TBC 700. Data will be tranεmitted in order to εpecify the target board, the target device, and the operation to be performed. Operations will consiεt of εcan chain εhift operations, loopback operations, and others as they be¬ come known. The TBC 700 uses the Addressable Shadow Port (ASP) to select and communicate with one or all of the board scan chains in the syεtem. Each ASP haε hardwired node addreεs input signals that allow the ASP to distinguish mesεageε directed to itε local chain. The node address inputs are based upon the "node ID" that is hardwired to the motherboard's backpanel connector. A "broadcast" address can be used that allows the master TBC to commu¬ nicate with all board scan chains in the system, should this be desired. The ASP protocol is detailed in A Pro- poεed Method of Accessing the 1149.1 in a Backplane Envi¬ ronment, Lee Whetsel, International Teεt Conference, 1992, the teachingε of which are incorporated by refer¬ ence. The Diagnoεtic Bus Interface (DBI) , a PAL, interfac- es the TBC with the backpanel DBus 208 and the ASP. The DBI's job is to allow three modes of operation: local mode, remote mode, and manufacturing test mode. In local mode, data from the TBC 700 iε sent direct¬ ly to the local scan chain and data from the local scan chain is sent directly to the TBC. The DBus 206 is not disturbed by local scan operations. As such, the mother- boards can operate in the local scan mode in parallel and simultaneously. Theεe simultaneous scan operations will occur during powerup testing. In remote mode, data from the TBC 700 is εent out to the DBuε 206 and data on DBus is returned to the TBC. The local scan chain is also connected to DBus 206 through the ASP part. This allows the TBC 700 to address any motherboard in the system as well as its own. When the address broadcast by the TBC 700 onto DBus 206 match¬ es a board's hardwired addreεs, or a broadcast address, the ASP connects the local scan chain to the DBus. In manufacturing test mode, the DBus 206 is connect¬ ed directly to the local scan chain and the TBC 700 and ASP are not used. This mode allows manufacturing to directly apply test vectors to the local scan chain through the backpanel DBuε εignalε. of no intereεt to the current scan operation may be placed in bypass mode. The Master microcontroller useε the TBC 700 and DBI to communicate over the backpanel diagnostic bus DBus 206 and to the DBI/ASPs on the other motherboardε. The maε- ter TBC tranεmitε a "select" protocol to address and enable the ASP connected to the slave DBI of the selected board(s) . Once εelected, the maεter and εlave are "con- nected" and the maεter TBC can perform scan operations transparently on the remote board(s) , using standard IEEE 1149.1 protocol. The DBus 206 conεiεts of the four standard IEEE 1149.1 signals (TCK, TDI, TDO, and TMS) and a "Diagnostic Interrupt Request" signal, DIRQ_N. During system power¬ up, DIRQ_N is used in determining diagnostic maεtership. During normal system operation, the DIRQ_N is uεed by the Power Syεtem componentε to interrupt the maεter microcon- troller. A number of IEEE 1149.1 featureε help to ensure that teεt circuitry does not interfere with normal system operation, should signals become stuck. Logic levels are chosen such that, in the event of a broken driver, sig- nals float to levels that cause the test interfaces to go into 'Test Logic Reset' mode. When the test interfaces are reset, the test logic is placed in a benign state. A "driving DBus" LED also is included on each motherboard to assiεt-in iεolating some types of DBus faults. It will be lit whenever a board's DBI is driving any DBus output. The DIRQ_N DBus εignal serves a number of functions. As mentioned above, it is used to determine diagnostic masterεhip during the powerup procedure. During normal system operation, the DIRQ_N signal is used by a power supply 210 or blower 212 to attract the attention of the master microcontroller. When the device detects a fault condition, it sets its DIRQ register bit and the interrupt is forwarded to the master microcon¬ troller by driving DIRQ_N on the backpanel DBus 206. The master microcontroller then attempts to access the TBC 700 through the normal motherboard level busses on the DM's motherboard and the RI ASIC 306. If the motherboard level buεεeε function normally, the maεter microcontroller can εuccessfully acceεε itε maεter TBC 700. The maεter microcontroller beginε scan¬ ning the slave DBIs in the computer εyεtem 200 to deter- mine which device aεεerted DIRQ_N. When a device'ε DIRQ regiεter bit iε found aεserted, it is cleared and the device is serviced. If a hard failure occurs on the motherboard level busεeε, the DM may not be able to acceεs the master TBC or the watchdog timer (WDT) , which is also in the local resources 260. In this caεe, DIRQ_N will remain aεεerted on DBuε 206 * for an unacceptably long time and the comput¬ er εyεtem will hang. When the hardware WDT timer times out, NMI, warm reset, and finally cold reεet will be εucceεsively invoked to break the hang. During the ensu¬ ing powerup testing asεociated with cold reεet, the hard failure will be iεolated and a new diagnostic maεter may be choεen. Aε indicated above, for purposes of providing high availability, the power supply εyεtem for the computer εyεtem iε designed as an (N+l) redundant configuration. Where pairs of motherboards share three power supplies 210a-c, but require only two. A εingle mother board uεeε two εupplies, but only requireε one. Each power εupply featureε a 74BCT8373 εcannable latch part that iε ac- cesεed by the local scan chain 702 on one of the two related motherboards. Fault status can be scanned out, and control commands can be scanned in. Power supplies 210a-c can be disabled, after a delay, and the DIRQs can be masked. Becauεe PIBuε electrical characteristicε dictate that the motherboards are populated left-to-right, an even-slot-numbered motherboard will always be preεent, e.g., εlot 0, in an even/odd motherboard pair being pow¬ ered by the (up to) three power εupplies 210a-c. There¬ fore, the even-slot-numbered motherboard's local scan chain will always be uεed to communicate with the power εupplies for that motherboard pair. In addition to communicating with power supplies, the local scan chains on the master microcontroller' s motherboard are used to communicate with the three blow- erε 212 and the εystem ID buffer. The system ID is stored in a SEEPROM part 204 that is socketed on the backpanel. The SEEPROM also will be used to store system history information. The blowers 212 of the computer system 200 also are configured as (N+l) redundant. Three blowers are provid¬ ed, but only two are needed. The maεter microcontrol¬ ler'ε motherboard local scan chain 704 communicates with the three blowers of the computer syεtem 200. The two main functionε provided for the blowers are notification of blower faults and adjustment of blower speed. When a blower fault occurs, circuitry on the blower interface detects the fault and sets a bit in a IEEE 1149.1 scannable regiεter. The circuitry alεo εets the blower's individual DIRQ regiεter bit, which cauεes the backpanel DIRQ_N signal to become asεerted. Thiε iε then handled by the maεter microcontroller as previously de- εcribed for the power εupplieε. The speed of the blowers can be adjusted by means of a scannable register part on the blower interface board. In εpecific embodimentε, the εcan teεt εuite of the inεtant invention for the design of the board mounted ASICs includes using the Synopεyε Test Compiler. The compiler supports 6 different scan methodologies: muxed flip-flop, clocked scan, single latch LSSD (Level Sensi¬ tive Scan Design) , double latch LSSD, clocked LSSD, and auxiliary clock LSSD (see Scan Methodologieε. Marshall Wood, the teachings of which are incorporated herein by reference) . In a preferred embodiment, the muxed flip- flop methodology iε uεed. Becauεe muxed flip-flop uses the normal system clock, the test access port ("TAP") controls the syεtem clock enable within the each ASIC. All board mounted ASICε of the instant invention will be IEEE 1149.1-compliant and include a TAP and asso¬ ciated pins TCK, TMS, TDI, and TDO. All ASICs and the other 1149.1-compliant components on each motherboard are incorporated into a single logical 1149.1 chain. The TDI and TDO signalε will be cascaded from one device to an¬ other and the required signals TCK and TMS are buffered appropriately. All 1149.1 compliant devices of the computer syεtem include a boundary εcan regiεter. Thiε provides a hard- ware-aεsiεted meanε of verifying that the correct parts are properly inserted on the board. Further, this veri- fies that the I/O drivers, boundary scan cells and bond¬ ing wireε in the parts are functioning correctly and that board etch between parts is intact. Each board mounted ASIC, will include a device iden¬ tification register, e.g., the 32-bit "Device Identifica- tion Register" of the IEEE 1149.1 standard. The device ID register for each board mounted ASIC contains a unique code that identifies the part (e.g., aε a DG part, εome derivative of the DG part number) and the revision number of the ASIC. At least some of the board mounted ASICε include design-specific Test Data Regiεterε (TDRε) that are acceεεed through the TAP. The board mounted ASICS alεo are deεigned to allow full εcan so that every logical flip-flop in the ASIC will be scannable. This feature provides a number of benefits, including the ability to scan-access machine state following fatal errors and improved coverage during chip teεting. The Full Scan TDR will acceεε the full scan circuitry embedded in the ASICs. Dedicated TDRε will provide control and εtatuε for hardware-detected errors within the ASIC and the circuit- ry it controls (if any) . Each ASIC's Error Status TDR will also have a read/write bit that indicateε, when aεεerted to a logic 1, that the ASIC is currently driving its FATAL_OUT_N signal. The external εignal iε active-- low (logic 0) and iε driven to the ORB ASIC, where it iε combined with other ASICε' fatal εignalε and diεtributed through-out the εyεtem. The Error Maεk TDR containε one bit for each error detected by the ASIC, and one bit for FATAL_OUT_N, where a "1" maεks the error out (normally register written with all O's) . Each ASIC's Error Maεk regiεter will be de¬ εigned such that the bit positionε for each error's maεk correεpond to the bit poεitionε in the Error Status reg¬ ister. The Error Forcing TDR contains one bit for each error detected by the ASIC. A logic "1" in this register causeε the ASIC to generate an error of that type ( nor¬ mally regiεter contains all O's) . The status bit for each error will be read/write, active high, and will indicate, when asserted, that the error has been detected. Therefore, a "0" in this bit means that no error has been detected and reading "all zeros" from the Error Status TDR will indicate that no errors have been detected. The following deεcribeε how the εcan chainε will be used in connection with the testing of the computer sys¬ tem 200. Following deasεertion of powerfail reεet, the microcontroller 300 on each motherboard 202 takeε control of the Reεourceε buε and the aεεociated DBI, thereafter having reign over the εcan environment for that mother¬ board. Firεt, the microcontroller 300 teεtε the Reεourc¬ eε εection to aεcertain its integrity. Then the micro¬ controller 300 initializes the εcan environment by uεing the TBC to place all the TAP controllerε in the 1149.1 deviceε into the Teεt-Logic-Reset state. TMS will be forced to logic 1 for at least 5 TCK cycles. Next, the microcontroller 300 begins performing interconnect tests on the motherboard. This is done by fetching teεt vectorε εtored in on-board EEPROM 302, and applying the vectorε through the DBI . Failures in these tests can be reported through console meεsages, and by lighting a failure LED on the board. Finally, the microcontroller 300 performs ASIC test- ing by applying test vectors through the TBC 700 to the board mounted ASIC. These test vectors alεo are εtored in the EEPROM 302. When thiε phaεe of teεting is com¬ plete, the microcontroller 300 gives up control of the Resourceε bus and allows normal procesεor requests to come through the RI. The microcontroller for each motherboard begins sizing the computer εyεtem by again placing the TAP con- trollerε in the Test-Logic-Reset state. In this state, the TAP controller loads the IDCODE instruction (or BY¬ PASS, if IDCODE is not supported) into the 1149.1 Inst¬ ruction Register. The IDCODE inεtruction cauεes the device ID register to be connected between the TDI and TDO pins of each device. BYPASS selects the single bit ('0') "bypass"register. The device ID register is 32bits long and beginε with '1'. Theεe bit definitions allow a bit stream from multiple devices to be parsed for device IDε. The TBC 700 will uεe the Scan Path Linker (SPL) deviceε or εcan bridgeε to multiplex the correεponding optional TDI/TDO chain into the main TDI/TDO chain for the motherboard 202. The SPL devices feature parallel input signalε that can be connected to "board preεent" εignals. The microcontroller can read these signals and connect the appropriate JP daughterboard scan chains. There are a number of ways to verify that the JP daugh¬ terboard chains are connected. When microcontroller reads the device ID registers from all the devices on the chain, it can determine if devices known to exist only on the JP daughterboard are present, or simply count the number of devices scanned. Either method can determine that optional devices are present. Ordering of hardwired scan componentε and option card componentε will be choεen εuch that an option card'ε poεition can be determined with certainty. I/O daughterboardε (e.g., PCI Expansion cards 282) can be detected by polling the PCI channels for devices. The microcontroller can then decide if the I/O daughter¬ board(ε) should be muxed into the TDI/TDO chain. Each motherboard 202 sizeε itself by checking for daughterboard options and checking all ASIC revisionε. The microcontroller can temporarily store the sizing information in a concise format in an easily-accessed on-board location, e.g, the RAM in the local resourceε 260. The DM can read this RAM later and build the over¬ all system configuration table. To determine if a motherboard remote to the master microcontroller is present, the master microcontroller transmits an ASP "select" protocol to the motherboard'ε addreεε. If an ASP "acknowledge" response is received, then the remote motherboard iε preεent and the microcont¬ roller may begin communicating with it. If no acknowl¬ edge reεponse is received, it will be assumed that the addresεed motherboard iε not present in the system. No further communication with this addresε will be attempt¬ ed. Deviceε available only through the εlot 0/εlot 1 DBI can be εized in the same manner as the motherboard is sized for optional daughterboards. The backpanel SEEPROM should alwayε be found preεent. If it is not present, then a break will be detected in the chain at the SEEPROM component's position and the SEEPROM will be reported missing. Each blower or all blowers is connected to one of the slot 0/slot 1 DBI'ε optional TDI/TDO chainε. It is important to note that the sizing process at this point uses only dedicated diagnostic hardware. The "nor- mal" system logic, such as the PI arrayε, does not par¬ ticipate in this phase of sizing. As indicated above, the computer system 200 is de¬ signed to iεolate the fault to at leaεt a FRU and then deconfigure i.e., functional and logically remove the FRU from the εystem. To deconfigure a section of logic, the 1149.1 optional HIGHZ instruction is invoked and when used, the instruction placeε all outputε in a high-- impedance state. Because every board mounted ASIC imple¬ ments this instruction, a fine granularity of dynamically reconfigurable units ("DRUs") will be achieved. To deconfigure a JP daughter board 250, the CI ASIC 414 and the TLCC ASIC 408 mounted thereon is placed in HIGHZ mode. Alternatively, the JP 250 also can be placed in reεet through a control regiεter in the CI 414. To deconfigure a motherboard 202, all PI ASICε are placed in HIGHZ mode. Becauεe the motherboard alεo has I/O devices on it, the I/O bus(ses) εhould be diεabled via a control regiεter in the GG ASIC 280. During the powerup proceεs, of the board mounted ASICs (e.g., PI ASICS 290) are initialized by means of the scanning process. At a later stage of the powerup teεting process, IDs and memory ranges are loaded into the ASICs by control space writeε. Aε provided above, the EEPROMS 302 include the firm¬ ware for the microcontroller 300 and the JPs 250, partic- ularly the JP designated as the diagnostic master and the microcontroller designated as the master microcontroller. The firmware for the microcontroller includeε powerup testing, scan testing, error handling, εyεtem εniffing during run-time, and εcanning error εtate when system fatal error occurs. The JP firmware includes powerup teεtε, XDIAG testε, manufacturing mode teεts, and error handling. The microcontroller 300 is the first piece of hard¬ ware in the computer syεtem 200 to be uεed for firmware diagnoεtics. It comes out of cold reset and is able to test itself and its resources while the rest of the εyε¬ tem is being held in warm reset. It initiates JTAG boun¬ dary scan on all of the scannable components in the sys¬ tem and will initialize internal scan state as well. It is responsible for bringing all other sections of the system out of reset in an individual manner, to keep iεolatability at a high level. It monitorε the per-board powerup teεts, controls the Watch dog timer (WDT) mecha¬ nism and takes care of EEPROM flaεhing. During runtime, when the operating system is up, the microcontroller 300 is responsible for sniffing tasks to make sure system operations are still functioning properly. A tabulation of the powerup teεtε performed by the microcontroller 300 is provided in FIGs. 13A, B. The sequence of events executed by each microcontroller 300 on each motherboard 200 during powerup is as follows. Each microcontroller 300 comes out of reset at ap¬ proximately the same time. Each microcontroller then checksumε its on-chip EEPROM and tests its access to on- chip SRAM. IP as an error iε detected, then the microc¬ ontroller executes a generic error handling function. An attempt alεo is made to set the resource bus LED to pro¬ vide an indication of a failure. The microcontroller then execute a STOP instruction. Each microcontroller initializeε itε on-chip hard¬ ware moduleε. Once its on-chip UART is initialized, code revision information and cause of microcontroller reεet are printed to the individual auxiliary consoles. Each microcontroller runs on-board diagnosticε for the following εectionε of the Resource Bus hardware: TBC 700, SRAM, EEPROM 302, NOVRAM/RTC, DUARTs, LSM, RSM, P555, GM, and clocks. Once board 0 DUART testing has been performed, board O's microcontroller 300 prints a meεsage to the syεtem console. All microcontrollers except slot 1's microcontroller will test DUARTs early in their re¬ source bus test suite. Slot 1's microcontroller will test DUARTs late in itε teεt εuite. Thiε is to prevent external loopback collisions when slot 0 and εlot 1 write to the system console and feedback DUARTε. Any errors or faults of the these components are considered fatal for the motherboard and will reεult in the deconfiguration of that board. The following deε- cribeε the deconfiguration proceεs which will occur on the board when the failure is detected. As soon as an error is detected, a generic error handling function will be executed. An error code is printed to the auxiliary console and an attempt is made to set the resource bus LED in order to indicate a fail- ure. An attempt is made to write failure information (error code, test/ sub- test, slot, and FRU/sub-FRU) to the NOVRAM error log. This information will not be acces¬ sible by any system JP since the board is held in cold reset and no Scan testing/ initialization has been per¬ formed. A mesεage is placed in the onboard scannable mailbox to inform the master microcontroller that an error was taken. The content of thiε message will simply state that a fatal motherboard deconfiguration error occurred. If the attempt to write the mailbox fails, this too iε valid information aε the default master microcontroller, i.e., slot 0 microcontroller, will eventually poll every¬ one's scanbox. It will find a RESET status in the of- fending motherboard's mailbox which will be enough of an indication that the motherboard failed cataεtrophically. If the error occurs on the current default master micro- controller, then the εame steps are taken. Eventually the secondary master microcontroller will time out, hav¬ ing not received either a scan meεεage or DUART loopback traffic and take mastership over the system. Finally, the microcontroller will execute a STOP instruction and the motherboard will be held in cold reεet, while in this state. An attempt will be made to keep the microcontroller in an idle loop instead of exe¬ cuting the STOP instruction. In this manner, the NOVRAM error log can be potentially read by the diagnostic mas¬ ter JP later in the powerup procesε. Cold reset is deaεserted for the εyεtem and for each εlot, and each microcontroller determineε in-εlot εizing information aε well aε executeε in-slot scan tests. At this point the first of three NOVRAM tableε, that table deεcribing each motherboard'ε phyεical hardware is built. In slot sizing will bypass the SB1 and SB2 Scan Bridges for the Power Supply and Blowers, as these will be tested by the master microcontroller during off-board scan test. Should any error be detected while performing in-slot scan testing follow the same εtepε as outlined above for deconfiguration with the following exceptions. The scan tests, unlike the on-board microcontroller diagnostic testing, can fail without the need to deconfi- gure the motherboard. For example, if any of the daugh¬ ter board εpecific teεts fail, only the daughter board need be deconfigured. If any of the motherboard specific tests fall, however, then the motherboard will be deconf¬ igured. If the motherboard/ daughter board interconnect test fails, then either the daughter board or the entire motherboard will be deconfigured depending upon the de- gree of iεolation provided by that test. Once a FRU has been determined bad during scan testing (e.g. JP 0 daughter board during TAPIT) , it will be immediately deconfigured and, therefore, bypassed for the remainder of the scan testing. All specific error information, as well as on- board sizing information, will be kept locally in each motherboards NOVRAM. Once the on-board scan testing has been completed or the motherboard has been determined bad at any point during the scan testing, then a message is placed in the scannable mailbox to inform the master microcontroller as to the outcome of the scan testing. The content of this message will simply εtate that a fatal motherboard decon- figuration error occurred or the motherboard passed test¬ ing. A paεε/ fail meεsage is also placed in the micro- controller's mail/ εcan box for the εlot 0 motherboard, the location of the default maεter microcontroller. In the case of a slot 0 motherboard failure, the slot 1 motherboard will eventually timeout, assume masterεhip, and then gain access to slot 0 motherboard's scanbox information. The microcontrollers deassert DIRQ_N to εynchronize with the maεter microcontroller and await further com- mands through their respective scannable mailbox. A master microcontroller iε then choεen. The purpoεe of εuch a maεter is to allow only one microcontroller to gather εystem sizing information and run out-of-εlot εcan tests. In addition, microcontrollers will become unsync- hronized due to previous test failures as well as differ¬ ences in slot hardware configurations. It is the job of the master microcontroller to synchronize all microcont- rollerε in the εyεtem. If the microcontroller on the slot 1 motherboard is chosen as master microcontroller, then from thiε point onward there will be no master micr¬ ocontrollers to default. The maεter microcontroller waitε for the microcont- rollerε on the other motherboards to finiεh in-εlot εcan tests. This is accomplished by first having all micro- controllerε drive DIRQ_N low prior to initiating εcan operationε. Aε each microcontroller finiεheε scan test¬ ing, they individually drive their DIRQ_N high. The master microcontroller, upon finiεhing its own testing, monitors the DIRQ_N line and once the DIRQ_N line is high, the master microcontroller will know that all εcan teεting has been completed. All microcontrollers should be synchronized at this point. The maεter microcontroller then εizeε the computer εystem to determine which boards are present. As part of sizing, each microcontroller's scannable mailbox is polled by the master microcontroller to determine if there haε been a resource bus or on-board Scan failure. The contents of the mailboxes are left intact and the pending requests unacknowledged in the event master mic¬ rocontrollership passes and the stepε have to be repeated again. The mailbox information will indicate failed motherboard εtatuε for each board, or a pass indication. If no indication is present in the scanbox (i.e. a reset value) then the asεumption iε that the motherboard failed. If failures exists, the asεociated mother- board(s) will be excluded from off- board scan testing. At this point the SEEPROM system backpanel ID test is performed and using data from the SEEPROM, the master microcontroller constructs the second of the three NOVRAM tables. This table contains SEEPROM sizing information indicating what the εystems hardware was the last time the syεtem waε powered up. The Midplane SEEPROM iε not updated with the new configuration data until after the "diagnostic master" JP has been choεen. The master microcontroller runs the remaining off- board scan teεtε including power εupply, blower, and backpanel interconnect testing. Any motherboards that were deconfigured as a reεult of previous testing will not be included in backpanel interconnect testing. If off-board εcan teεting iε εucceεsful, a mesεage to that effect iε placed in the εlot 1 motherboard'ε mailbox. The εlot 1 motherboard microcontroller, now in an idle loop, periodically checks for a special non-printable character printed to the εystem console, via the feedback DUART, as well aε a εtatus mesεage in itε εcannable mail¬ box. Thiε DUART character will be issued by the slot 0 motherboard at the same time as the scan mesεage is sent, i.e., right after off-board εcan teεting haε completed. If the maεter microcontroller is on the slot 1 mo¬ therboard, then the message buffer and DUART checking described above will not be performed. If off-board Scan teεting fails in a manner which is attributable to the εlot 0 motherboard or in a way which iε not iεolatable and the current maεter iε the εlot 0 motherboard, then microcontroller maεterεhip is passed to the slot 1 mothe¬ rboard via the scannable mailbox. This is the first of two caεeε where maεterεhip iε paεεed directly by the εlot 0 motherboard, omitting the timeout mechaniεm. If off- board Scan teεting fallε in a manner which is attribut¬ able to another motherboard and the current master is board 0, then the offending motherboard is deconfigured and mastership is retained by board 0. If off-board Scan testing failε, and the current maεter iε board 1, then the slot 1 motherboard takes the neceεsary steps to deconfigure all offending motherboards indicated by the failures. If the error is attributable to the slot 1 motherboard then a fatal syεtem error re- εultε. The DUART and meεεage pasεing protocolε provide alternate meanε of detecting εcan test failures from the εlot 0 motherboard, aεεuming maεtership has not already been pasεed for any of the reasonε already described. If the slot 1 motherboard fails to receive either form of communication and it is not already master, then after a specified timeout period, it will assume microcontroller masterεhip and perform the above described actions of the master microcontroller. If the εlot 0 motherboard does experience a self or non- attributable off-board scan test failure, the error is logged in it's NOVRAM, and mastership is paεsed. However, the motherboard is not deconfigured because it has up to now proven itself to be a good board with ex¬ ception of being capable of off board testing. This in and of itself poses no threat to the remainder of the syεtem just so long as it is not responεible for perform¬ ing system scan functions. The slot 1 motherboard, when it takes over must begin off-board εcan testing from the very beginning regardless of how far the slot 0 mother¬ board had already gotten just to prove that it has no problem accessing all off-board resourceε. If the slot 1 motherboard detects a problem with the εlot 0 mother¬ board, then the slot 0 motherboard will be deconfigured. If no problem is found, then the slot 0 motherboard's problem is attributable to it'ε off-board εcan hardware. It εtill remainε a healthy εystem board unless proven otherwise as testing continues. To deconfigure, the maεter microcontroller will issue a command via the scannable mailbox. The reception of a deconfiguration message causeε the offending mother¬ board to update it'ε local copy of current board status kept in a NOVRAM table. The master microcontroller, via the scannable mail¬ boxes, tells every microcontroller to deassert warm reset for both the system and the slot and begin taking the JPS out of reset. All microcontrollers should be synchro- nized at this point. Each motherboards' microcontroller sees to it that the deconfigured daughter boards and motherboards indicated in the NOVRAM tables, are not included in the JP testing which iε about to take place. Aε noted above, all of the εcannable mailboxeε still contain the pass/fall indication of each motherboard. This information is maintained in the event that local NOVRAMs are inaccesεible by the "diagnoεtic master", thus maintaining at least some indication of the failure. The microcontrollers take each in-εlot JP out of reεet, one at a time. Each JP runε a Suite of "primary teεtε" which includes basic sanity diagnostics. The microcontrollers monitor the status of these tests by reading on-board SRAM locations updated by the in-slot JPs. In this manner, microcontrollerε can recognize test completions, failures, and hangs. Each Microcontroller chooses an in-slot JP (which succeεsfully completes itε "primary teεts") to run its "εecondary teεt" εuite. This test suite includes the time consuming operationε of memory and I/O initializa- tion/teεting. However, allowing εuch testing to occur in parallel, i.e., acrosε motherboardε, will help decreaεe overall powerup time. As in primary testing, each micro¬ controller recognizes test completions, failures, and hangε. Secondary teεtε will be run until at least one in- slot JP passes all extensive testε or all in-slot JPs have been exhausted. Each microcontroller will then send "board slave" and "board master" meεεageε to the appro¬ priate in-slot JPs. The maεter microcontroller will await the completion of all of the JP'ε "secondary teεts" via the DIRQ_N mech¬ anism already explained above. The master microcon- troller will then tell its Board Master JP to run "ter¬ tiary teεts. " The first part of thiε teεting begins when the master, via the RI/Resource Bus path, reads extensive configuration information from each non-deconfigured motherboard's NOVRAM. This information is required by the master in order to conduct tertiary teεting. Thiε teεt εuite includeε all off-board JP and memory diagnos¬ tics. If the testing succeeds, a "diagnostic master" mes¬ εage is sent to this Board Master JP. If the slot 0 motherboard fails tertiary teεting, the error iε marked in the NOVRAM and the εystem attempts powerup again only with the microcontroller of the slot 1 motherboard as the default master. If the slot 1 motherboard also fails tertiary teεting then a fatal system error results. If either master detects problems with other motherboardε during tertiary teεting, then thoεe failing motherboards will be deconfigured. Once the "diagnostic master" iε finally choεen, itε aεsociated motherboard will be mapped aε the global resource board. During the entire process of selecting a diagnostic master all failing tests and resulting motherboard/ daug- hter board deconfigurationε will be logged in each boardε NOVRAM error log and the NOVRAM configuration tableε. Just as had been done for the on-board microcontroller diagnoεtics and scan failures. At the completion of selecting the "diagnostic maεter", the diagnostic master JP will poll the various NOVRAMs to determine complete error and deconfiguration information, if any. All cur¬ rent εystem configuration information is now be written to the system ID SEEPROM 204. A machine initiated (MI) callout is now be iεsued flagging all failed testε and deconfigurationε and all scanboxes are cleared. This polling of the NOVRAM will be performed by the diagnostic master via RI ASIC accesε of the resource bus. Should thiε RI path acceεε fail for any of the motherboardε which have already been deconf- igured, then the scanbox information, which is still present, can be used aε a limited εource of information. Alternatively, the DM can requeεt the failing motherboard microcontroller to accesε the NOVRAM and return the in¬ formation via the falling motherboards scanbox. In yet another way, error and deconfiguration information is copied into the local motherboard SEEPROM just before a board is deconfigured. From there the master microcontr¬ oller can acceεε the information via off-board scan. Finally, each microcontroller enters its "idle loop". Within the loop, the microcontrollers will period¬ ically read on-board SRAM in order to process (global or local) requestε from εystem JPs. Additionally, watchdog processing, board sniffing, and run-LED blinking will be periodically performed in this loop. By the time which each JP comes out of reset, the aεsumption is that the microcontroller on each board has tested everything in its local resources 260 (e.q. NOVRA- M, EEPROM, SRAM etc.), the blowers, and the power sup- plieε. Alεo the motherboard haε been εcan tested. If there is any failure in the above tests, the microcon¬ troller has taken the action(s) to ensure that the moth- erboard meets the minimum requirements to function cor¬ rectly. Otherwise, none of the JP'S for that motherboard is taken out of reset and the motherboard will be put back into reset. In addition, JPs will not check for any blower and power supply failure during powerup. The JP PROM powerup sequence is divided into three stages. Upon executing each step, each JP will εend a message to the microcontroller on its board, and writes the FRUs or DRUs which is/are going to be teεted in the NOVRAM. An error code alεo is written in the NOVRAM so that in case of a failure/hang, the syεtem will know where the problem is and have the information to make a MI callout. If the test failed, the microcontroller gets a error meεεage from the JP and in the caεe of a hang, the microcontroller will timeout. There iε provided in FIGs. 14-16, a tabulation of the powerup tests performed by the JP and the DM JP. JPs on each board will be taken out of reεet in the order of JP 0 , JP lf JP 2 , and JP 3 . Three actionε will be preformed by each JP for each of the following steps: 1) it informs the microcontroller which test will be run next; 2) writes the FRU(s) name involved in the test and the error code in NOVRAM; and 3) executes the test. Upon finishing each stage, the JP waits for instruction from the microcontroller what to do next, i.e., continue to next stage or εtay idle. For primary εtage testing, the microcontroller brings each JP on its motherboard out of reset one after another. The following testε are performed at the prima¬ ry εtage. - JP runs self-teεtε to verify it is functioning properly. - JP runs the PROM Accesε Test to make sure it can accesε PROM correctly. - JP teεts local SRAM accesses. - JP testε NOVRAM accesses. - JP initializes the stacks, the SCM, FE. and the spadε in SRAM - JP runε teεtε that will iεolate faultε to the daughter board (i.e., 88110/884108 Caches, CI, TLCC, EDAC tests) . Some of these testε will be rerun when there are multiple JPs out of reset so that inter¬ actions among the JPs can be tested and still iso¬ late to the daughter board. - JP runs RI register access (write/read) testε, including uεing backdoor method to write/read from itεelf. - JP runs PI register access (write/read) tests. - JP runs GG register accesε (write/read) tests. - JP runs MC register access (write/read) tests. - JP sizeε and initializeε the MC, PI, EDAC regis¬ ters and main memory on the motherboard. - JP runs a quick main memory test, if there is any SIMM, on its motherboard. This test will be run on the first SIMM in the first bank of memory (i.e. at most 32MB will be teεted) only. Thiε teεt will verify that the JP can accesε memory. The microcontroller will put the JP which failed any of the above steps back into reset. If anyone of the two JPs on a JP daughter board failed any of the tests, that JP and the daughter board shall be marked dead and decon- figured. Also a MI call will be made later by the DM. If both JP daughter boards are deconfigured, the rest of the associated motherboard will be tested after the DM is determined. If all the daughter boards are bad in both slot 0 and 1, the system will be powered down. After each JP finisheε the primary εtage, it waits to be told by the microcontroller whether to go onto secondary stage or become a slave JP and go into an idle loop. The following tests are performed at the secondary stage. - JP sizes its own board and writeε the information into NOVRAM. - JP writes a global test pattern and set a pattern- _valid flag in SRAM for later testing. - JP sets all the MADV register(s) on its board. - JP runs εome extensive tests on the MC EDACs, the Directory SIMMs, and the on-board main memory. - On a SIMM failure, JPPROM will deconfigure the SIMM bank in error. The entire memory subsystem will be deconfigured if any of the teεtε on MC, EDACs, and the Directory failed. - JP runs the on-board caches testε using its on¬ board main memory (if any exist) . - if any of theεe teεts failed, the daughter board on which the JP resides will be deconfigured. - JP sizes all the PCI devices and initializes the GGs on its own board. - JP runs extensive tests on the integrated SCSI and LAN controllers. Theεe teεtε are run on each GG ASIC on a motherboard, one after another. If any of the teεts failed, then that GG/PCI Bus subsyεtem will be deconfigured. Failure of both GG ASICε will cause the motherboard to be deconfigured. - Each Board Master collects all on-board informa¬ tion (e.g. which ASIC is good/bad, which JP is good/bad, itε PROM reviεion number etc.) and writeε it into NOVRAM. - Each Board Master initializes whatever is left on the board e.g. modem. The foregoing tests are run in parallel with each other on the other boards. These tasks are done before the boards are enabled on PI busseε. This testing is used to determine whether a particular board can be con¬ sidered for Diagnoεtic Maεterεhip. The maεter microcontroller will tell the firεt JP on itε motherboard that εucceεsfully completed the secondary stage of testing to be the acting diagnoεtic maεter (ADM) and to go on and perform the tertiary stage of testing, while the other JPε await instruction. The following testε are performed at the tertiary εtage. - ADM runs self Pis loopback test (ThD) . - ADM runs off-board tests to determine if it can access other boards in the system. - ADM tells JPs in the syεtem to run extenεive cache teεtε. - ADM collectε each ACTIVE board's configuration information using the RI back-door method. - ADM enables itself on the midplane, i.e. resets the global bits both in Ris and Pis. - ADM initializes and teεts other motherboards that don't have any working JPs on them, or runs I/O testε on boards that don't have any near memory. The DM useε memory on itε board for SCSI scripts locations. - ADM makes a MI call if the hardware configuration information among Table 1, 2, and 3 in its NOVRAM are different. - ADM tells the Master microcontroller to update the SEEPROM on the back- panel according to the informa¬ tion in its NOVRAM - Table 3. - ADM does the final initialization for the whole system and sets up some control space registerε for the operating syεtem, i.e., DG/UX. - ADM takeε all good εlave JPε Out of the idle loops and SCM is entered. There are four posεible outcomes from the foregoing: 1) All testε paεεed. The ADM becomeε the DM and finiεheε the remaining steps and halt to SCM. 2) A test failed and the ADM knows that it is the problem on its own motherboard. 3) The ADM hangs when running these tests and its microcontroller timeouts. 4) A teεt failed and the ADM knowε which board is the problem. In all caseε, except for caεe 3, the ADM tells the master microcontroller the result of the tests. For cases 2 and 3, the master microcontroller will mark it- εelf dead in itε SEEPROM, and re-powerup the system. For case 4, the master microcontroller tells the failing board's microcontroller to deconfigure itself from the system. After the master microcontroller getε an acknow¬ ledgment, it will tell the ADM to restart tertiary test- ing with the running of the cache teεtε. After the forgoing microcontroller and JP testε are done, the computer εystem boots from the default boot path. After booting the operating system (DC/UX) , all JPs are under control of the operating syεtem and no JPPROM will be run except when a εystem call is made. While the system is running, the microcontroll¬ er 300 on each motherboard 202 executes sniffing tasks that verify the proper functioning of certain parts of the computer εyεtem. The reεource buε specific tests include: NOVRAM Checksum, DUART Functionality, Power Supply/ Blower status via the PSSS mach, EEPROM Checksum and TBC test. The master microcontroller also is re- sponsible for statuting the power supply and blowers via a Scan chain operation. The microcontroller will need to check semaphore lockε before accessing any of these areas in sniffing tasks so that no data iε lost when a JP is trying to update or access an area. As indicated above only the microcontroller and JPε on the motherboardε in εlot 0 and 1 on the backplane are viable candidateε reεpectively for the maεter microcontr¬ oller and the diagnostic master. In default, the microc- ontroller and one of the JPε on the εlot 0 motherboard are εo designated. If the motherboardε in both εlotε and/or the JPε in both slotε are faulted and deconfigura- ble, then the εystem is shutdown. Although a preferred embodiment of the invention has been described using specific terms, such description is for illustrative purposes only, and it is to be under¬ stood that changeε and variations may be made without departing from the spirit or scope of the following claimε.

Claims: What is claimed is: 1. A method for automatically recovering a computer syεtem following discovery of a fault condition, comprising the stepε of: providing a computer εystem having self-teεting and εelf-diagnoεing capability; automatically teεting the computer εyεtem; automatically identifying the presence of one or more faulted components from εaid step of testing; and de-configuring the computer system to functionally remove the faulted component from the computer system as identified by said step of automatically identifying. 2. The method of claim 1, wherein before said step of testing the method further includes the step of recov¬ ering the content of a memory of εaid computer system. 3. The method of claim 1, further said step of recovering includes step of testing includes performing continuity checks on the computer system components and interconnections between the components and, wherein said identifying includes analyzing the continuity checks to identify faulted components and interconnections. 4. The method of claim 1, wherein the computer system provided includes at least one application specif¬ ic integrated circuit (ASIC) having a gated balanced clock tree circuit that automatically and selectively distributes clock pulses to logical F/Fs of the ASIC, the clock tree having a plurality of branches therefrom; and wherein the method further includes the steps of: configuring the gated balance clock tree circuit so clock pulεeε are diεtributed to at leaεt εome of the logical F/Fε when a computer system is in a firεt opera¬ tional condition; and re-configuring the gated balance clock tree circuit to block the distribution of the clock pulses to the at least εome of the logical F/Fs when the computer syεtem iε in a second operational condition. 5. The method of claim 1, wherein the computer εyεtem further includeε two redundant system clocks, where the clocks of one εyεtem clock are provided to the computer system at a time; wherein the method further includes the stepε of monitoring the system clock providing the clocks to the computer εyεtem for a failure; and configuring the computer system to functionally remove the failed system clock and to source the clocks thereafter from the redundant system clock, when said εtep of monitoring identifieε a failure of the εyεtem clock, 6. A gated balanced clock tree circuit that auto¬ matically and selectively supplies clock pulseε to the logical flip-flopε (F/Fs) of an application specific integrated circuit (ASIC) comprising: a clock trunk in which flows the clock pulseε to the logical F/Fε of the ASIC, the clock tree having a plural¬ ity of branches extending therefrom; at least one AND gate being disposed in at least one of the branches of the clock trunk feeding at least some of the logical F/Fs; control circuitry that controls each of the at least one AND gate εo at leaεt some of the logical F/Fs are feed only certain clock pulses; and wherein said control circuitry is configured εo the AND gate automatically allows clock pulses to be feed to the at least some of logical F/Fε during a firεt opera¬ tional condition of a computer εyεtem uεing the ASIC and wherein said control circuitry is also configured so clock pulses are automatically blocked by the AND gate when in a second operational condition of the computer system. 7. The gated balanced clock tree circuit of claim 6 further comprising: a phaεed locked loop device (PLL) that controlε the clock signals being fed into the clock trunk; a delay cell being electrically interconnected to said PLL and a selected branch of said clock tree, where¬ in the delay cell delays each clock pulse from the se¬ lected branch of the clock tree by a predetermined amount for deskewing the clock pulεeε to the logical F/Fs; and wherein the clock pulses through the selected branch are not blocked from going to the PLL when in the second operational condition of the computer εyεtem. 8. The gated balanced clock tree circuit of claim 6, wherein εaid control circuitry iε configured εo the AND gate allowε clock pulεeε to be feed to the logical F/Fε when in a third operational condition. 9. The gated balanced clock tree circuit of claim 8, wherein the firεt operational condition correεponds to normal operation of the computer system, wherein the second operational condition corresponds to a fatal error condition of the computer system and wherein the third operational condition corresponds to a system testing of the computer syεtem during at least one of powerup and following the fatal error condition. 10. The gated balanced clock tree circuit of claim 6 further comprising a plurality of AND gates to control the clock pulseε through all branches but the selected branch of the clock trunk. 11. A method for controlling clock pulses to logi¬ cal flip-flops F/Fs) of an application specific integrat¬ ed control circuit (ASIC) comprising the steps of: providing an ASIC having a gated balanced clock tree circuit that automatically and selectively distributes clock pulses to the logical F/Fs, the clock tree having a plurality of branches therefrom; configuring the gated balance clock tree circuit so clock pulεes are distributed to at leaεt εome of the logical F/Fs when a computer system is in a first opera¬ tional condition; and re-configuring the gated balance clock tree circuit to block the diεtribution of the clock pulεeε to the at leaεt εome of the logical F/Fs when the computer system is in a second operational condition. 12. The method for controlling clock pulseε of claim 11, wherein the gated balance clock tree circuit includes at least one AND gate and wherein said εtep of configuring includes providing one signal to the AND gate so the clock pulses are distributed and wherein said step of re-configuring includes providing a second signal to the AND gate to block the clock pulses. 13. The method for controlling clock pulses of claim 11, wherein the gated balance clock tree circuit includes a phased locked loop device (PLL) that controls the clock signals being fed into the clock trunk and wherein said method further compriseε the steps of: feeding back clock pulses to the PLL from a selected branch of the clock tree circuit; delaying the clock pulεeε being feedback a predeter¬ mined amount for deεkewing the clock pulεeε to the logi¬ cal F/Fε; and wherein the clock pulεeε being feed back are not blocked from going to the PLL when in the second opera¬ tional condition of the computer syεtem. 14. The method for controlling clock pulses of claim 11, wherein said step of configuring the gated balance clock tree circuit εo clock pulses are distribut¬ ed alεo iε done when the computer εyεtem is in a third operational condition. 15. The method for controlling clock pulses of claim 14, wherein the first operational condition corre¬ sponds to normal operation of the computer system, where¬ in the second operational condition corresponds to a fatal error condition of the computer system and wherein the third operational condition corresponds to a system testing of the computer system during at least one of powerup and following the fatal error condition. 16. The method for controlling clock pulseε of claim 11, wherein the gated balance clock tree circuit includes at plurality of AND gate and wherein said step of configuring includes providing one signal to the plu¬ rality of AND gates so the clock pulses are distributed and wherein said step of re-configuring includes provid¬ ing a second signal to the plurality of AND gates to block the clock pulses. 17. The method for controlling clock pulses of claim 16, wherein clock pulses are blocked in all branch¬ es but a selected branch of the clock tree circuit by the second signal. 18. A system to supply clock pulses in a computer system comprising: at leaεt first and εecond clock generation and diε- tribution devices, where the first clock generation and distribution device is set as the source for clock pulseε being supplied by the εyεtem; wherein each of the firεt and second clock genera¬ tion and distribution deviceε includes: primary oscillator circuitry being electrically configured so as to generate periodic signal pulεeε, detection circuitry being configured electrically to monitor the periodic pulses generated by the oscil- lator circuitry to detect a failure of that circuit¬ ry, and εignal generating circuitry, reεponsive to the de¬ tection circuitry, that is configured to provide an output signal representative of the detection of a failure of the oεcillator circuitry; and clock pulse failover circuitry that is configured sb the clock supply system automatically redesignateε the source of clock pulses being supplied aε the εecond clock generation and diεtribution device reεponεive to a fail¬ ure εignal from the εignal generating circuitry of the first clock generation and distribution device. 19. The clock pulse supply syεtem of claim 18 wher¬ ein the detection circuitry includeε a secondary oscilla¬ tor circuitry for generating a periodic signal at a dif¬ ferent frequency than oεcillator circuitry and three flip/flops (F/Fs) ; and wherein the three F/Fε are elec¬ trically interconnected to each other and the primary and secondary oscillators circuitry so the F/Fε detect the failure of the primary oεcillator circuitry and provide an output repreεentative of the failure. 20. The clock pulεe εupply system of claim 19 wher¬ ein the output representative of the failure is a signal output from two of the three F/Fs. 21. The clock pulse εupply εyεtem of claim 19 wher¬ ein the three F/Fε are reεpectively firεt, second and third F/S where the first F/F is electrically intercon¬ nected to the εecond and third F/Fs and the secondary oεcillator circuitry and wherein the εecond and third F/Fs are electrically interconnected to the primary os¬ cillator circuitry. 22. The clock pulεe supply system of claim 19 wher¬ ein the primary oscillator circuitry includes a 100 MHz crystal and wherein the secondary oscillator circuitry includes a 105 MHz crystal. 23. A method for εupplying clock pulses in a com¬ puter system comprising: providing a clock εupply εystem including two redun¬ dant signal generating devices that generate periodic signal pulses and circuitry for automatically and select¬ ably controlling the εource of the clock pulεe being εupplied, where one device iε initially designated as being the source of the clock pulses being supplied; monitoring the periodic εignals being generated by the signal generating deviceε εourcing the clock pulεeε for the εyεtem; automatically failing over to the redundant εignal producing device in reεponεe to the detection of a fail¬ ure of the firεt device to generate periodic signal puls¬ es. 24. The method for supplying clock pulses of claim 23 wherein each signal generating device includes a pri¬ mary and secondary oεcillator circuitry that generate periodic εignal pulses at different frequencies and wher¬ ein said step of monitoring includeε monitoring the out¬ put of the primary and secondary oscillators circuitry to detect a failure of the primary oscillator circuitry. 25. A high availability scalable multiprocesεor computer εyεtem, compriεing: a backplane, including at least one backplane commu¬ nication bus and a diagnoεtic buε; a plurality of motherboards, detachably connected to said backplane; each motherboard interfacing to said at least one backplane communication buε and to said diag¬ nostic bus, each of said plurality of motherboards in¬ cluding: at least one backplane communication bus inter¬ face mechaniεm interfacing at least one of said plurality of motherboards to said at least one back¬ plane communication bus; a memory εyεtem including main memory diεtrib¬ uted among said plurality of motherboards, directory memory for maintaining main memory coherency with caches on other motherboards, and a memory control¬ ler module for accessing said main memory and direc¬ tory memory and interfacing to said motherboard communication bus; at least one daughterboard, detachably connect¬ ed to said motherboard and interfacing to said moth¬ erboard communication buε, said at least one daught¬ erboard further including: a motherboard communication bus interface module, for interfacing said at least one daug¬ hterboard to said motherboard communication bus and a local bus on said daughterboard; and at least one cache memory system including cache memory and a cache controller module mai¬ ntaining said cache memory for a processor of said εcalable multiproceεsor computer syεtem; a backplane diagnostic bus interface mechanism interfacing each of said plurality of motherboardε to εaid backplane diagnoεtic buε; a microcontroller for proceεsing information and providing outputs; and a test bus controller mechanism including registers therein; a scan chain that electrically interconnects functionalities mounted on each motherboard and each of said at least one daughter board to said test bus con¬ troller; and an applications program for execution with said microcontroller, said applications program including inεtructions and criteria to automatically test the func¬ tionalities and electrical connections and interconnec¬ tions, to automatically determine the presence of a faul¬ ted component and to automatically functionally remove the faulted component from the computer εystem. 26. The high availability scalable multiprocessor computer system of claim 25, wherein at least one of said plurality of motherboards and said at leaεt one daughter board further includes at least one application εpecific integrated circuit (ASIC) having a gated balanced clock tree circuit that automatically and selectively distrib- uteε clock pulses to logical F/Fs of the ASIC, wherein said gated balanced clock tree circuit includeε: a clock trunk in which flowε the clock pulεeε to the logical F/Fε of the ASIC, the clock tree having a plural¬ ity of brancheε extending therefrom; at leaεt one AND gate being diεpoεed in at least one of the branches of the clock trunk feeding at leaεt some of the logical F/Fs; control circuitry that controlε each of the at leaεt one AND gate so at least some of the logical F/Fs are feed only certain clock pulses; and wherein said control circuitry is configured εo the AND gate automatically allows clock pulses to be feed to the at least some of logical F/Fs during a first opera¬ tional condition of the computer system and wherein said control circuitry is also configured so clock pulses are automatically blocked by the AND gate when in a second operational condition of the computer system. 27. The high availability scalable multiproceεsor computer syεtem of claim 26 wherein said gated balanced clock tree circuit further includes: a phased locked loop device (PLL) that controlε the clock signalε being fed into the clock trunk; a delay cell being electrically interconnected to εaid PLL and a εelected branch of said clock tree, where- in the delay cell delays each clock pulse from the se¬ lected branch of the clock tree by a predetermined amount for deskewing the clock pulses to the logical F/Fs; and wherein the clock pulεeε through the εelected branch are not blocked from going to the PLL when in the εecond operational condition of the computer εystem. 28. The high availability scalable multiprocessor computer system of claim 26 wherein said control circuit¬ ry is configured so the AND gate allows clock pulses to be feed to the logical F/Fs when in a third operational condition. 29. The high availability scalable multiproceεεor computer εyεtem of claim 28, wherein the first operation¬ al condition corresponds to normal operation of the com¬ puter system, wherein the second operational condition correspondε to a fatal error condition of the computer εyεtem and wherein the third operational condition corre¬ sponds to a system testing of the computer εystem during at least one of powerup and following the fatal error condition. 30. The high availability scalable multiprocessor computer syεtem of claim 26, wherein εaid gated balanced clock tree circuit further includes a plurality of AND gateε to control the clock pulses through all branches but the selected branch of the clock trunk. 31. The high availability scalable multiproceεεor computer εyεtem of claim 26, wherein each of said at least one ASIC are interconnected to said at leaεt one εcan chain so said micrcontroller can teεt each of εaid at leaεt one ASIC. 32. The high availability εcalable multiproceεεor computer syεtem of claim 25, further compriεing a εystem to supply clock pulseε in a computer εyεtem, the εyεtem including: at least first and second clock generation and dis¬ tribution devices, where the first clock generation and distribution device iε εet as the source for clock pulses being supplied by the syεtem; wherein each of the firεt and εecond clock genera¬ tion and distribution devices includes: primary oscillator circuitry being electrically configured so as to generate periodic signal pulses, detection circuitry being configured electrically to monitor the periodic pulses generated by the oscil¬ lator circuitry to detect a failure of that circuit¬ ry, and signal generating circuitry, responsive to the de¬ tection circuitry, that is configured to provide an output signal representative of the detection of a failure of the oscillator circuitry; and clock pulse failover circuitry that is configured so the clock supply syεtem automatically redeεignateε the εource of clock pulses being supplied as the second clock generation and distribution device responsive to a fail¬ ure signal from the signal generating circuitry of the first clock generation and distribution device. 33. The high availability scalable multiprocesεor computer εystem of claim 32, wherein the detection cir¬ cuitry includes a secondary oscillator circuitry for generating a periodic signal at a different frequency than oscillator circuitry and three flip/flops (F/Fs) ; and wherein the three F/Fs are electrically interconnect¬ ed to each other and the primary and secondary oscilla¬ tors circuitry so the F/Fs detect the failure of the primary oscillator circuitry and provide an output repre¬ εentative of the failure.

Inventors: BAXTER WILLIAM F, COX JOSEPH, GELINAS ROBERT G, GILLOTT BARRY E, GUYER JAMES M, HEYDA ANDREA, HUCK DAN R, HUNT MICHAEL F, KEATING DAVID L, KIMMELL JEFF S, PIKE ROB J, RADOGNA TOM V, ROUX PHIL J, SHERMAN ART A, SPORTER MICHAEL, TRUEBENBACH LIZ M, TUCKER DOUG J, VALENTINE ROB P, WEILER PAT J, YEUNG SIMON N, BAXTER, WILLIAM, F., COX, JOSEPH, GELINAS, ROBERT, G., GILLOTT, BARRY, E., GUYER, JAMES, M., HEYDA, ANDREA, HUCK, DAN, R., HUNT, MICHAEL, F., KEATING, DAVID, L., KIMMELL, JEFF, S., PIKE, ROB, J., RADOGNA, TOM, V., ROUX, PHIL, J., SHERMAN, ART, A., SPORTER, MICHAEL, TRUEBENBACH, LIZ, M., TUCKER, DOUG, J., VALENTINE, ROB, P., WEILER, PAT, J., YEUNG, SIMON, N.
Applicants: BAXTER WILLIAM F, COX JOSEPH, DATA GENERAL CORP, GELINAS ROBERT G, GILLOTT BARRY E, GUYER JAMES M, HEYDA ANDREA, HUCK DAN R, HUNT MICHAEL F, KEATING DAVID L, KIMMELL JEFF S, PIKE ROB J, RADOGNA TOM V, ROUX PHIL J, SHERMAN ART A, SPORTER MICHAEL, TRUEBENBACH LIZ M, TUCKER DOUG J, VALENTINE ROB P, WEILER PAT J, YEUNG SIMON N, BAXTER, WILLIAM, F., COX, JOSEPH, DATA GENERAL CORPORATION, GELINAS, ROBERT, G., GILLOTT, BARRY, E., GUYER, JAMES, M., HEYDA, ANDREA, HUCK, DAN, R., HUNT, MICHAEL, F., KEATING, DAVID, L., KIMMELL, JEFF, S., PIKE, ROB, J., RADOGNA, TOM, V., ROUX, PHIL, J., SHERMAN, ART, A., SPORTER, MICHAEL, TRUEBENBACH, LIZ, M., TUCKER, DOUG, J., VALENTINE, ROB, P., WEILER, PAT, J., YEUNG, SIMON, N.
Application year: 1996
Main classification: G06F11
IPC codes: G06F1, G06F11