Device for detecting error from digital data

Abstract: Device for detecting an error from a digital data during decoding the digital data, is disclosed, including a storage means (210) for temporary storage of received arbitrary bytes of data(a parallel data) in response to a control signal (L 0 ∿ L 3 ) and producing the data in byte units separately; logical operation means for subjecting each of the byte unit data from the storage means to an operation according to a preset logical operation equation in response to a control signal for producing a data separately; error detecting means for comparing the data from the logical operation means in determining an occurrence of error; and, controlling means for providing the control signals.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a decoder in a CD ROM driver and, more particularly, to a device for detecting an error from a digital data during decoding the digital data. Discussion of the Related Art In general, the CD ROM decoder has an error corrected in case the error is occurred in a data and determines final correction of the error in the data using an EDC(Error Detection Code). Fig. 1 illustrates a data recording format on the CD ROM, in which the error detection code is shown. Referring to Fig. 1, the error detection code is a 4 bytes parity calculated with the following equation for a total 2064 bytes including 12 bytes sync, 4 bytes header and 2048 bytes information data. P(X) = (X 16 + X 15 + X 2 + 1)x(X 16 + X + 1) X 32 + X 31 + X 16 + X 15 + X 4 + X 3 + X + 1 That is, the CD ROM determines that there is error(s) in a data if a remainder after making a dividing operation of the 2068 bytes including the sync, header, information data and error detection code with the above equation (1) is not "0". The process for decoding a signal recorded on a digital signal recording medium, such as the CD ROM includes a step for correcting errors, in which cases when a regular signal could not be read-in due to defects in the disc, mistakes in manufacturing, and errors in a servo or synchronizing signal, are corrected, and also included therein is an error detection step, in which the error corrected data is once again inspected to make confirmation on the state of the regular error correction. A conventional device for detecting an error from a digital data in a CD ROM will be explained with reference to the attached drawings. Fig. 2 illustrates a block diagram showing the conventional device for detecting an error from a digital data in a CD ROM, and Fig. 3 illustrates a circuit diagram showing a detail of the dividing operation part shown in Fig. 2. Referring to Fig. 2, the conventional device for detecting an error from a digital data in a CD ROM includes a data converting part 100 for converting a received byte unit parallel data into a bit unit series data in response to an operation clock signal, and an operation part 110 for subjecting the converted series data in bit unit series data to an operation according to the equation (1) in response to an operational clock signal, for producing final error(s). Referring to Fig. 3, the operation part 110 includes a plurality of D-flipflops D1 ∼ D32 connected in series for temporary storage of the bit unit series data from the data converting part 100 in response to an operational clock signal, and producing the stored data after shifted, a first exclusive OR gate E1 for receiving and subjecting the bit unit series data from the data converting part 100 and an output from the flipflop D32 to an exclusive OR operation and applying the exclusive OR operation result to the flipflop D1, a second exclusive OR gate E2 for receiving and subjecting the output from the flipflop D32 and an output from the flipflop D1 to an exclusive OR operation and applying the exclusive OR operation result to the flipflop D2, a third exclusive OR gate E3 for receiving and subjecting the output from the flipflop D32 and an output from the flipflop D3 to an exclusive OR operation and applying the exclusive OR operation result to the flipflop D4, a fourth exclusive OR gate E4 for receiving and subjecting the output from the flipflop D32 and an output from the flipflop D4 to an exclusive OR operation and applying the exclusive OR operation result to the flipflop D5, a fifth exclusive OR gate E5 for receiving and subjecting the output from the flipflop D32 and an output from the flipflop D15 to an exclusive OR operation and applying the exclusive OR operation result to the flipflop D16, a sixth exclusive OR gate E6 for receiving and subjecting the output from the flipflop D32 and an output from the flipflop D16 to an exclusive OR operation and applying the exclusive OR operation result to the flipflop D17, a seventh exclusive OR gate E7 for receiving and subjecting the output from the flipflop D32 and an output from the flipflop D31 to an exclusive OR operation and applying the exclusive OR operation result to the flipflop D32 again, and a NOR gate N1 for receiving each of the outputs from the flipflops D1 ∼ D32 and subjecting to an NOR operation. The operation of the aforementioned system will be explained. Fig. 4 illustrates a sequence of data reception for detecting an error. Byte unit parallel data stored in a memory(not shown), such as an SRAM or an DRAM, i.e., the 2068 bytes including the sync, header, information data, error detection code shown in Fig. 1 are received at the data converting part 100. The received byte unit parallel data are converted into bit unit series data in response to a provided operation clock and applied to the operation part 110. The applied series data are 2068 bytes x 8 bits = 16544 bits of series data, for each of which bits an operation clock is required, i.e., 16544 operation clocks are required. In the application of data to the operation part 110, the 16544 bits of data are applied from the least significant bit(LSB) to the most significant bit(MSB) in an order as shown in Fig. 4. The operation of the operation part 110 will be explained with reference to Fig. 3. As explained, the operation part 110 has 32 flipflops D1 ∼ D32 connected in series, and, of the 32 flipflops D1 ∼ D32 , one of the exclusive OR gates E1 ∼ E7 is connected to an input terminal of the first flipflop D1, the second flipflop D2, the fourth flipflop D4, the fifth flipflop D5, 16th flipflop D16, 17th flipflop D17 and 32nd flipflop D32. All the exclusive OR gates E1 ∼ E7 receive the output Q31 from the 32nd flipflop D32, and 16544 number of operation clocks are applied to each of the flipflops D1 ∼ D32. The NOR gate N1 receives each of the outputs Q0 ∼ Q31 from the flipflops D1 ∼ D32 and conducts an NOR operation to determine occurrence of error data finally. That is, when each of the data obtained in each of the flipflops D1 ∼ D32 according to the equation (1) is applied to the NOR gate N1, if all these applied data are "0", "0", i.e., a low signal is produced, to determine that no error has been occurred. And, of each of the data applied from each of the flipflops D1 ~ D32 to the NOR gate N1, if a data of "1" is applied from any one of the data, a data of "1" is produced, to determine that an error has been occurred with the data correction having not been done properly, finally. The processing time for operations of digital data storage, error correction, error detection and data transmission in a conventional CD ROM drive will be examined with reference to Fig. 5. Fig. 5 illustrates time basis operations of the CD ROM decoder, wherein it can be seen that the CD ROM decoder processes one block data of 2352 bytes for the data storage, error correction, error detection and data transmission in time sharing. In case of 1X CD ROM, the processing time a process shown in Fig. 5 takes about 13.33 msec, and in case of 8X CD ROM, it takes 13.33 msec/8, i.e., about 1.67 msec. And, in case of 10X CD ROM, it takes 13.33 msec/10, i.e., about 1.333 msec. As can be know from this process, since reduction in the time required for the error detection allows allocation of more time to the data transmission and the like, a higher speed CD ROM drive could be realized. Since the conventional device for detecting an error from a recorded digital data for the CD ROM driver converts bit unit parallel data stored in a memory into bit unit series data and applies an operation clock to every converted data bit, the lengthy error detection time causes a problem of hindering the CD ROM driver from being provided with a higher speed. SUMMARY OF THE INVENTION Accordingly, it would be desirable to provide a device for detecting an error from a digital data that substantially obviates one or more of the problems due to limitations and disadvantages of the related art. It would also be desirable to provide a device for detecting an error from a recorded digital data for a CD ROM driver, which can minimize the number of operation clocks for higher speed error detection. It would also be desirable to provide a method corresponding to the aforementioned device. Accordingly, the present invention provides a device as set out in Claim 1, and a method as set out in Claim 9. Embodiments of the invention provide a device for detecting an error from a recorded digital data for a CD ROM driver, including, in the device for detecting an error from a recorded digital data for a CD ROM driver, a storage means for temporary storage of a received arbitrary bytes of data (a parallel data) in response to a control signal and producing the data in byte units, logical operation means for subjecting each of the byte unit data from the storage means to an operation according to a preset logical operation equation in response to a control signal for producing a data, error detecting means for comparing the data from the logical operation means in determining an error occurrence, and controlling means for providing the control signal. Embodiments of the invention also provide a device for detecting an error from a recorded digital data for a CD ROM driver, including, in the device for detecting an error from a recorded digital data for a CD ROM driver, a first storage part for receiving byte unit received data from an arbitrary data block in digital data recorded in the CD ROM after error correction, temporary storage of the data by an arbitrary bit unit, and producing the stored data in response to a production timing control signal, a logic circuit part for composing a status after an arbitrary number of bytes x 8 clocks based on the data from the first storage part and logical processing of the status, a second storage part for temporary storage of the data from the logic circuit part and feeding the data back to the logic circuit part, an error determining part for mutual operation of each of the produced data in determining the data of an error occurrence, and a timing controlling part for providing the production timing control signal and the clock signal. Embodiments of the invention also provide a method for detecting an error from a recorded digital data for a CD ROM driver, including the steps of, (1) temporary storage of received arbitrary byte data(parallel data) in response to a control signal and producing the data in byte units, (2) subjecting each of the produced byte unit data to an operation according to a preset logical operation equation in response to a control signal for producing a data, and (3) subjecting the produced data in the (2) step to an NOR operation in determining occurrence of an error. Embodiments of the invention also provide a method for detecting an error from a recorded digital data for a CD ROM driver, including the steps of, (1) receiving byte unit received data from an arbitrary data block in digital data recorded in the CD ROM after error correction, temporary storage of the data by an arbitrary bit unit, and producing the stored data in response to a production timing control signal, (2) composing a status after an arbitrary number of bytes x 8 clocks based on the data from the (1) step and logical processing of the status according to a preset logical operation equation, (3) temporary storage of the logically processed data in response to a clock signal and feeding the data back to the (2) step, mutual comparison of each of the produced data in determining the data of an error occurrence It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the drawings: In the drawings: Fig. 1 illustrates a data recording format on a general CD ROM; Fig. 2 illustrates a block diagram showing a conventional device for detecting an error from a digital data for a CD ROM driver; Fig. 3 illustrates a circuit diagram showing a detail of the operation part shown in Fig. 2; Fig. 4 illustrates a sequence of data reception for detecting an error; Fig. 5 illustrates time basis operations of a conventional CD ROM decoder; Fig. 6 illustrates a block diagram showing a device for detecting an error from a digital data in a CD ROM decdder in accordance with a preferred embodiment of the present invention; and, Figs. 7a ∼ 7g show operation timings of the device shown in Fig. 6. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings Fig. 6 illustrates a block diagram showing a device for detecting an error from a digital data in a CD ROM decoder in accordance with a preferred embodiment of the present invention. Referring to Fig. 6, the device for detecting an error from a digital data in a CD ROM decoder includes a first storage part 210 for receiving byte unit received data from an arbitrary block of data in recorded digital data after error correction, temporary storage of arbitrary bytes of data, and producing b 0 ∼ b 31 the stored data in response to a production timing control signal L 0 ∼ L 3 , a logic circuit part 220 for composing a status after arbitrary bytes x 8 clocks based on the data b 0 ∼ b 31 from the first storage part 210 and logically processing the status, a second storage part 230 for temporary storage of the data D 0 ∼ D 31 from the logic circuit part in response to a clock signal CLK and producing Q 0 ∼ Q 31 the data D 0 ∼ D 31 , an error determining part 240 for mutual operation of each of the produced data Q 0 ∼ Q 31 in determining occurrence of an error in the data, and a timing controlling part 200 for providing the production timing control signal L 0 ∼ L 3 and the clock signal CLK. The first storage part 210 includes a first latch 211 for latching the first byte data from four byte data in response to a first production timing control signal L 0 to produce one byte data b 0 ∼ b 7 , a second latch 212 for latching the second byte data from four byte data in response to a second production timing control signal L 1 to produce one byte data b x ∼ b 15 , a third latch 213 for latching the third byte data from four byte data in response to a third production timing control signal L 2 to produce one byte data b 16 ∼ b 23 , and a fourth latch 214 for latching the fourth byte data from four byte data in response to a fourth production timing control signal L 3 to produce one byte data b 24 ∼ b 31 . The operation of the aforementioned device will be explained with reference to the attached drawings. Figs. 7a ∼ 7g show operation timings of the device shown in Fig. 6. First, of the byte unit parallel data stored in a memory(not shown) in the CD ROM driver, 4 byte unit parallel data is received at the first storage part 210. Of the 4 byte unit parallel data received at the first storage part 210, each of the first, second, third and fourth latches 211, 212, 213 and 214 receives by one bytes. Each of the latches 211, 212, 213 and 214 stores the one byte unit data temporarily in response to a sequence of signals L 0 ∼ L 3 from the timing controlling part 200 and applies b 0 ∼ b 31 them the logic circuit part 220 on the same time. In this instant, the timing controlling part 200 generates the latch control signals L 0 ∼ L 3 as shown in Figs. 7b ∼ 7e in a sequence for each of the bytes received at each of the latches 211, 212, 213 and 214. The data b 0 ∼ b 31 from the first storage part 210 and the data Q 0 ∼ Q 31 fed from the second storage part 230 back to the logic circuit part 220 are subjected to operations in the logic circuit part 220 according to each of the following logical equations, to form a status after the prior clock The operation equations performed in the logic circuit part 220 are as follows. Each of the data D 0 ~ D 31 produced from the logic circuit part 220 are; D 0 =Q 0 ⊕ Q 1 ⊕ Q 2 ⊕ Q 3 ⊕ Q 4 ⊕ Q 5 ⊕ Q 6 ⊕ Q 7 ⊕ Q 8 ⊕ Q 9 ⊕ Q 10 ⊕ Q 11 ⊕ Q 12 ⊕ Q 13 ⊕ Q 14 ⊕ Q 15 ⊕ Q 28 ⊕ Q 29 ⊕ Q 30 ⊕ b 31 . D 1 = Q 0 ⊕ Q 16 ⊕ Q 28 ⊕ Q 31 ⊕ b 30 . D 2 = Q 1 ⊕ Q 17 ⊕ Q 29 ⊕ b 29 . D 3 = Q 0 ⊕ Q 1 ⊕ Q 2 ⊕ Q 3 ⊕ Q 4 ⊕ Q 5 ⊕ Q 6 ⊕ Q 7 ⊕ Q 8 ⊕ Q 9 ⊕ Q 10 ⊕ Q 11 ⊕ Q 12 ⊕ Q 13 ⊕ Q 14 ⊕ Q 15 ⊕ Q 18 ⊕ Q 28 ⊕ Q 29 ⊕ b 28 . D 4 = Q 0 ⊕ Q 3 ⊕ Q 16 ⊕ Q 19 ⊕ Q 28 ⊕ b 27 . D 5 = Q 1 ⊕ Q 4 ⊕ Q 17 ⊕ Q 20 ⊕ Q 29 ⊕ b 26 . D 6 = Q 2 ⊕ Q 5 ⊕ Q 18 ⊕ Q 21 ⊕ Q 30 ⊕ b 25. D 7 = Q 3 ⊕ Q 6 ⊕ Q 19 ⊕ Q 22 ⊕ Q 31 ⊕ b 24 . D 8 = Q 4 ⊕ Q 7 ⊕ Q 20 ⊕ Q 23 ⊕ b 23 . D 9 = Q 5 ⊕ Q 8 ⊕ Q 21 ⊕ Q 24 ⊕ b 22 . D 10 = Q 6 ⊕ Q 9 ⊕ Q 22 ⊕ Q 25 ⊕ b 21 . D 11 = Q 7 ⊕ Q 10 ⊕ Q 23 ⊕ Q 26 ⊕ b 20 . D 12 = Q 8 ⊕ Q 11 ⊕ Q 24 ⊕ Q 27 ⊕ b 19 . D 13 = Q 9 ⊕ Q 12 ⊕ Q 25 ⊕ Q 28 ⊕ b 18 . D 14 = Q 10 ⊕ Q 13 ⊕ Q 26 ⊕ Q 29 ⊕ b 17 . D 15 = Q 0 ⊕ Q 1 ⊕ Q 2 ⊕ Q 3 ⊕ Q 4 ⊕ Q 5 ⊕ Q 6 ⊕ Q 7 ⊕ Q 8 ⊕ Q 9 ⊕ Q 10 ⊕ Q 11 ⊕ Q 12 ⊕ Q 13 ⊕ Q 15 ⊕ Q 27 ⊕ Q 28 ⊕ Q 29 ⊕ b 16 . D 16 = Q 0 ⊕ Q 12 ⊕ Q 15 ⊕ Q 16 ⊕ b 15 . D 17 = Q 1 ⊕ Q 13 ⊕ Q 16 ⊕ Q 17 ⊕ b 14 . D 18 = Q 2 ⊕ Q 14 ⊕ Q 17 ⊕ Q 18 ⊕ b 13 . D 19 = Q 3 ⊕ Q 15 ⊕ Q 18 ⊕ Q 19 ⊕ b 12 . D 20 = Q 4 ⊕ Q 16 ⊕ Q 19 ⊕ Q 20 ⊕ b 11 . D 21 = Q 5 ⊕ Q 17 ⊕ Q 20 ⊕ Q 21 ⊕ b 10 . D 22 = Q 6 ⊕ Q 18 ⊕ Q 21 ⊕ Q 22 ⊕ b 9 . D 23 = Q 7 ⊕ Q 19 ⊕ Q 22 ⊕ Q 23 ⊕ b 8 . D 24 = Q 8 ⊕ Q 20 ⊕ Q 23 ⊕ Q 24 ⊕ b 7 . D 25 = Q 9 ⊕ Q 21 ⊕ Q 24 ⊕ Q 25 ⊕ b 6 . D 26 = Q 10 ⊕ Q 22 ⊕ Q 25 ⊕ Q 26 ⊕ b 5 . D 27 = Q 11 ⊕ Q 23 ⊕ Q 26 ⊕ Q 27 ⊕ b 4 . D 28 = Q 12 ⊕ Q 24 ⊕ Q 27 ⊕ Q 28 ⊕ b 3 . D 29 = Q 13 ⊕ Q 25 ⊕ Q 28 ⊕ Q 29 ⊕ b 2 . D 30 = Q 14 ⊕ Q 26 ⊕ Q 29 ⊕ Q 30 ⊕ b 1. D 31 = Q 0 ⊕ Q 1 ⊕ Q 2 ⊕ Q 3 ⊕ Q 4 ⊕ Q 5 ⊕ Q 6 ⊕ Q 7 ⊕ Q 8 ⊕ Q 9 ⊕ Q 10 ⊕ Q 11 ⊕ Q 12 ⊕ Q 13 ⊕ Q 14 ⊕ Q 27 ⊕ Q 28 ⊕ Q 29 ⊕ Q 31 ⊕ b 0 . The results of the operation thus conducted in the logic circuit part 220 are applied to the second storage part 230. The second storage part 230 applies each of the received data from the logic circuit part 220 to the 32 flipflops therein, respectively. In this instant, the 32 flipflops are applied of a clock signal CLK provided from the timing controlling part 200. In response to the clock signal, the second storage part 230, i.e., each of the flipflops produces a data Q 0 ∼ Q 31 . Herein, it is assumed that each of the flipflops in the second storage part 230 is operative at a rising edge of the clock signal CLK as shown in Fig. 7f provided from the timing controlling part 200. Each of the outputs Q 0 ∼ Q 31 from the second storage part 230 is fed back to the logic circuit part 220 and applied to the error determining part 240. Each of the applied 32 data is subjected to an NOR operation by the error determining part 240. That is, only if all the outputs Q 0 ∼ Q 31 from the second storage part 230 are "0", an output EDC-OK from the logic circuit part 240 becomes logic high, if not, it becomes logic low. The logic high represents detection of no error, and the logic low represents detection of error(s). The error determining part 240 includes an NOR gate. Together with this, of the one block data, last bytes from 2065th to 2068th are also applied to the first storage part 210, latched, and applied to the logic circuit part 220 and the second storage part 230. Then, an output EDC-OK for one block data(2068 bytes) from the error determining part 240 produced only when a rising edge of the clock signal CLK from the timing controlling part 200 as shown in Fig. 7f is received is determined to be an effective value as shown in Fig. 7g, and to generate a right error detection confirmation signal. The clock signal CLK from the timing controlling part 200 is a signal having the rising edge after the generation of the control signals L 0 ∼ L 1 in succession to be applied to each of the latches 211, 212, 213 and 214 in the first storage part 210, but before the activation of the first latch control signal L 0 . In other word, the operation is completed through the logic circuit part 220 and the second storage part 230 before the reception of new 4 byte parallel data. Since the device for detecting an error in a recorded digital data detects error(s), not in bit units after converting the received parallel data into series data, but in byte units, i.e., as parallel data, the device can minimize the error detecting time, allowing a CD ROM capable of driven at a higher speed.

Claims: A device for detecting an error in first digital data, comprising: first storage means (210) arranged to receive and provide temporary storage for received bytes of said first digital data in response to a control signal, and to output said data in byte units as second data (b 0 -b 31 ); second storage means (230) arranged to receive and provide temporary storage for fourth data (D 0 -D 31 ), and to output said stored data as third data (Q 0 -Q 31 ); a logic circuit part (220) arranged to receive said second and third data, to apply a preset logical operation to said received second and third data in response to a control signal, and to output the result of said operation as said fourth data; error detecting means (240) arranged to receive said third data and to determine therefrom an occurrence of an error in said first digital data; and controlling means (200) for providing the control signals. A device as claimed in claim 1, wherein the error detection means (240) is arranged to generate an error detection signal from said third data when the last byte of a block of said first digital data has been received by said first storage means (210) and has been processed by said logic circuit part (220) in combination with said second storage means (230). A device as claimed in claim 1 wherein said first storage means includes a plurality of 8 bit latches (211-214). A device as claimed in claim 1, wherein the logic circuit part (220) subjects the second data and the third data to an exclusive OR operation. A device as claimed in claim 1, wherein the first storage means (210) includes a plurality of D type flipflops. A device as claimed in claim 5 wherein the number of D type flipflops is 32. A device as claimed in claim 1 wherein the error detection means (240) includes a NOR gate having 32 inputs. A device as claimed in claim 3, wherein the number of 8 bit latches is 4. A method of operating a CD ROM driver to detect an error in first recorded digital data, comprising the steps of: temporarily storing, in first storage means (210) in response to a control signal, received bytes of said first recorded digital data, and outputting said stored data in byte units as second data; temporarily storing, in second storage means (230), received fourth data, and outputting said stored data as third data; receiving said second and third data in a logic circuit part (220), applying therein a preset logical operation to said received data in response to a control signal, and outputting the result of said operation in byte units as said fourth data; and receiving, in error detecting means (240), said third data, and therein determining from said received data an occurrence of an error in said first recorded digital data. A method as claimed in claim 9, wherein the step of determining further comprises the step of generating an error detection signal from said third data when the last byte of a block of said first recorded digital data has been received by said first storage means (210) and has been processed by said logic circuit part (220) in combination with said second storage means (230).

Inventors: KOO BON HO, KOO, BON HO
Applicants: LG ELECTRONICS INC, LG ELECTRONICS INC.
Application year: 1996
Main classification: G11B20
IPC codes: G11B20