Power stage, particularly for an operational amplifier

Abstract: A power stage (3) for an operational amplifier (1), including an output stage (6) formed by a first and second NPN output transistor (12, 13) in Totem-Pole configuration, having respective resistors (16, 17) between the respective base and emitter terminals; the output transistors (12, 13) are biased in class AB by a quiescent current supplied by a current source stage (8), and are controlled dynamically by a gain stage (5) including an NPN gain transistor (18) with the collector terminal connected to the base terminal of the first output transistor (12), and the emitter terminal connected to the base terminal of the second output transistor (13).

Description: The present invention relates to a power stage, particularly for an operational amplifier. As is known, a wide variety of power stages exist for operational amplifiers featuring NPN power output transistors, and which are classed according to the type of biasing employed. In the following description, reference will be made to a class AB amplifier, in which, even when in quiescent condition, the transistors are supplied with a weak current to eliminate crossover distortion. Accurate control of the quiescent current is especially important in the case of class AB amplifiers, and is normally done using complex circuit networks including numerous NPN and PNP components, which, however, involve several drawbacks. The control network, in fact, introduces numerous poles, which impair the operational amplifier band, involves a far from negligible increase in the area required for integrating the operational amplifier, and is not always capable of accurately controlling and reproducing the quiescent current. Power stages of this type are also unstable when a capacitive load is connected to the output; this instability is eliminated by providing a network (known as a Boucherot cell) comprising the series connection of a resistor with a very low resistance (a few Ω), and a capacitor with a capacitance in the order of hundreds of nF and located between the output of the operational amplifier and ground. Such a cell, however, presents the drawback of increasing the cost of the amplifier. A power stage according to the preamble of claim 1 is disclosed in US-A-4 295 101, and in particular in figure 3 thereof. It is an object of the present invention to provide an amplifier stage designed to overcome the aforementioned drawbacks. According to the present invention, there is provided a power stage for an operational amplifier, as claimed in Claim 1. Two preferred, non-limiting embodiments of the present invention will be described by way of example with reference to the accompanying drawings, in which: Figure 1 shows a circuit diagram of a first embodiment of the power stage according to the present invention; Figure 2 shows a circuit diagram of a second embodiment of the power stage according to the present invention. Number 1 in Figure 1 indicates an operational amplifier comprising a differential input stage 2 shown only schematically and not described in detail; and a power stage 3 connected to the output 4 of differential input stage 2. Power stage 3 in turn comprises a gain stage 5; a power output stage 6 connected to gain stage 5 and defining an output terminal 7 supplying an output signal V o ; and a current source stage 8 for biasing output stage 6. Output stage 6 comprises two NPN transistors 12, 13 in Totem-Pole configuration; transistor 12 has the emitter terminal connected to output terminal 7, the base terminal defining a node 35, and the collector terminal connected to a supply line 14 (at supply voltage V cc ): transistor 13 has the emitter terminal connected to a ground line 15, the base terminal defining a node 36, and the collector terminal connected to output terminal 7; and transistors 12, 13 occupy respective areas A 12 , A 13 , have respective inverted saturation currents I s,12 , I s,13 and respective voltages V be,12 , V be,13 between the base and emitter terminals, and are supplied with respective currents I 12 , I 13 . Output stage 6 also comprises two resistors 16 and 17 of the same resistance R and located between the base and emitter terminals of respective transistors 12 and 13. Gain stage 5 comprises an NPN transistor 18 with the base terminal connected to output 4 of input stage 2, the collector terminal connected to the base terminal of transistor 12 (node 35), and the emitter terminal connected to the base terminal of transistor 13; and a stabilizing capacitor 19 located between the base and collector terminals of transistor 18. Current source stage 8 comprises an NPN reference transistor 21 with the emitter terminal connected to ground line 15, the collector terminal connected to supply line 14 via an equivalent current source 22, and the base terminal connected to ground line 15 via a resistor 23 of resistance R/2, where R is the resistance of resistors 16, 17 as indicated above. Reference transistor 21 has an area A 21 and a voltage drop V be,21 between the base and emitter terminals; and equivalent current source 22 supplies a current I r to reference transistor 21. A transistor 24 has the base and emitter terminals connected respectively to the collector and base terminals of reference transistor 21, and the collector terminal defining a node 38. Finally, current source stage 8 comprises two PNP transistors 25, 26 arranged so as to form a current mirror. More specifically, transistors 25, 26 have the base terminals connected to each other, and the emitter terminals connected to supply line 14; transistor 25 has the collector and base terminals connected to each other and to node 38; and transistor 26 has the collector terminal connected to node 35 of output stage 6 to which it supplies a bias current I p proportional to current I r supplied by equivalent current source 22. Operation of the output stage will be described with reference firstly to the quiescent condition in which no signal is present at the input of the operational amplifier, and disregarding to begin with the base currents of the circuit transistors. All of current I p generated by equivalent source 22 flows into reference transistor 21 to produce a voltage drop V be,21 , which in turn produces, in resistor 23 of resistance R/2, a current 2V be,21 /R, which is mirrored by current mirror 25, 26 and supplied to node 35 as current I p . In the quiescent condition, current I p is divided so that currents I 12 and I 13 supplied by transistors 12 and 13 of output stage 6 are equal. In the event transistors 12 and 13 are identical (i.e. A 12 =A 13 and I s,12 =I s,13 ), currents I 1 and I 2 supplied to transistors 12 and 13 equal V be,21 /R. In this case, voltages V be,12 and V be,13 between the base and emitter terminals of transistors 12 and 13 are equal to each other and to V be,21 . Since the quiescent performance of transistor 13 is identical to that of transistor 12, reference will be made in the following description solely to the quantities relative to transistor 12 for the sake of simplicity. In the Figure 1 circuit, the quiescent current I 12 in transistor 12 is given by the equation: I 12 = I s ,12 ·exp V be ,12 V t = I s ,12 ·exp R · I p 2 V t where V t is the thermal voltage. The current I r in reference transistor 21 equals: I r = I s ,21 exp( V be ,21 V t ) where I s,21 is the saturation current of reference transistor 21, so that: V be ,21 = V t ln( I r I s ,21 ) and, since, as stated, I p = 2V be,21 /R : Substituting (4) in (1) gives: I 12 = I s ,12 · I r I s ,21 and, since the saturation current of a transistor is directly proportional to the area occupied, this gives: I 12 = I r · A 12 A 21 Dynamic operation will now be described assuming transistor 12 supplies the maximum current. In this condition, all of current I p =2V be,21 /R flows into the branch comprising transistor-12, and from there partly through resistor 16 and partly into transistor 12 via the base terminal. As compared with the quiescent condition, voltage drop V be,12 between the base and emitter of transistor 12 is increased by: where V be,12,max is the voltage drop between the base and emitter of transistor 12 in the maximum current supply condition; and I 12,max is the maximum current supplied by transistor 12. The current component through resistor 16 and which causes the increase in V be,12 is: The increase in current at the base of transistor 12, on the other hand, equals: δ I b ,12 = I 12,max - I 12 β where β is the current gain of transistor 12. Given the maximum current I 12,max to be supplied, resistance R of resistor 16 must be fairly low to ensure the excess current, with respective to the quiescent condition, is sufficient to supply the increase in current at the base of transistor and the increase in current in resistor 16 due to the increase in voltage between the base and emitter of transistor 12. In practice, if I R is the current through resistor 16, the following equation must apply: V be ,21 R ≥δ I b ,12 +δ I R . Substituting δI R and δI b,12 resulting from equations (7) and (8) in (9), this gives: The same also applies if maximum current is supplied by transistor 13. In calculating the quiescent current as shown above, no account has been taken of the base current I b,12 of transistor 12, which introduces an error into quiescent current I 12 so that the actual current is less than the theoretical one calculated above. If the base current is also accounted for, and bearing in mind that I b,12 =I 12 /β, where I 12 is the collector current of transistor 12, the voltage drop of resistor 16, which determines the base-emitter voltage drop of transistor 12, is less than reference voltage V be,21 by a quantity equal to: dV' be =- I ' 12 b · R where I' 12 is the nominal quiescent current of transistor 12 (and hence of transistor 13). Taking into account the above variation in the voltage drop of resistor 16, quiescent current I 12,r approximately equals: As can be seen, resistance R affects the quiescent current via the base current; and, by establishing the maximum permissible error via the ratio between the actual and nominal quiescent currents I 12,r /I' 12 , the minimum R value may be calculated as follows: In the Figure 2 embodiment, the power stage, in this case indicated 3', comprises a gain stage 5', which differs from gain stage 5 by presenting, as opposed to transistor 18, a first pair of transistors 18a, 18b in Darlington configuration. Power stage 3' also comprises an output stage 6', which differs from output stage 6 by presenting, instead of transistors 12 and 13, a second pair of transistors 12a, 12b and a third pair of transistors 13a, 13b also in Darlington configuration. Transistors 12a, 12b, 13a, 13b of output stage 6' respectively present base-emitter voltages V be,12a , V be,12b , V be,13a , V be,13b ; saturation currents I s,12a , I s,12b , I s,13a , I s,13b ; and areas A 12a , A 12b , A 13a , A 13b . Output stage 6' also differs from output stage 6 by presenting, instead of resistors 16 and 17, resistors 28, 29 located between the base and emitter terminals of respective transistors 12a, 13a, and resistors 30, 31 interposed between the base and emitter terminals of respective transistors 12b, 13b. Resistors 28, 29, 30 and 31 all have the same resistance value R 1 . Bias current I p1 supplied by current source stage 8, in which resistor 23 now has a resistance value of R/4, equals: Disregarding the base currents of transistors 12a and 13a, and assuming the bias current, in the quiescent condition, is divided equally between transistors 12a, 12b and 13a, 13b, as described with reference to Figure 1, the voltage drop of identical resistors 28, 30 equals: The base-emitter voltage drop of transistor 12b (or transistor 13b, assumed identical to transistor 12b) equals: so that the quiescent current equals: I 12b = I s ,12 b · I s ,12a V be ,12 b R 1 · I r 2 I s,21 2 = A 12 b · A 12 a A 21 2 · I r 2 V be ,12 b R 1 In this case also, as shown clearly in equation (17), the quiescent current value may be regulated by working on the resistance value. The advantages of the power stage according to the present invention are as follows. The quiescent currents are controlled by simply providing additional resistive elements in the output stage, i.e. with no need for complex circuit networks, so that the circuit is simple in design, easy to integrate, reliable by virtue of its parameters being accurately controllable, and presents a small area. The power stage so formed comprises exclusively NPN power transistors, which are superior to PNP transistors as regards frequency response and size; presents no local feedback loops; can withstand capacitive loads of up to a few tens of nF with no need for a Boucherot cell; and presents a wide band. The topology of the power stage described is similar to that of Totem-Pole TTL devices, which, however, operate in class C with digital logic. Conversely, the stage according to the invention provides for class AB biasing, and may be used in low-distortion analog applications. Clearly, changes may be made to the power stage as described and illustrated herein without, however, departing from the scope of the present invention as defined in the appended claims. In particular, the above sizings may be modified to suit specific requirements, and any of the components may be replaced by technical equivalents.

Claims: A power stage (3; 3') for an operational amplifier (1), comprising an output stage (6; 6') operating in class AB, having an output terminal (7), and comprising a top transistor element (12; 12a, 12b) and a bottom transistor element (13; 13a, 13b); said top transistor element (12; 12a, 12b) having a first terminal connected to said output terminal (7), a second terminal connected to a first reference potential line (14), and a control terminal; and said bottom transistor element (13; 13a, 13b) having a first terminal connected to a second reference potential line (15), a second terminal connected to said output terminal (7), and a control terminal; the power stage (3; 3') further comprising a first resistive element (16; 28, 29) connected between said control terminal and said first terminal of said top transistor element (12; 12a, 12b); and a second resistive element (17; 30, 31) connected between said control terminal and said first terminal of said bottom transistor element (13; 13a, 13b), characterized by a gain stage (5; 5') connected between said control terminals of said top (12; 12a, 12b) and bottom (13; 13a, 13b) transistor elements of said output stage (6; 6'); and a current source stage (8) connected to said control terminal of said top transistor element (12; 12a, 12b) of said output stage (6; 6'), wherein said gain stage (5; 5') comprises a gain transistor element (18; 18a, 18b) having a control terminal connected to an input (4), and a first terminal connected to said control terminal of said top transistor element (12; 12a, 12b), and a second terminal connected to said control terminal of said bottom transistor element (13; 13a, 13b). A power stage as claimed in claim 1, characterized in that said top transistor element and said bottom transistor element comprise Darlington transistors (12a, 13a, 12b, 13b). A power stage as claimed in Claim 2, characterized in that said top transistor element comprises a first (12a) and second (12b) transistor, and said bottom transistor element comprises a third (13a) and fourth (13b) transistor, each of said transistors having a first and second terminal and a control terminal; said control terminals of said first and third transistors (12a, 13a) respectively defining said control terminals of said top and bottom transistor elements; and said first terminals of said second and fourth transistors (12b, 13b) respectively defining said first terminals of said top and bottom transistor elements; and in that said first resistive element comprises a first (28) and second (29) resistor, and said second resistive element comprises a third (30) and fourth (31) resistor; said first resistor (28) being connected between said control terminal of said first transistor (12a) and said first terminal of said second transistor (12b); said second resistor (29) being connected between said control terminal and said first terminal of said second transistor (12b); said third resistor (30) being connected between said control terminal of said third transistor (13a) and said first terminal of said fourth transistor (13b); and said fourth resistor (31) being connected between said control terminal and said first terminal of said fourth transistor (13b). A power stage as claimed in Claim 1 or 2, characterized in that said gain transistor element of said gain stage (5') comprises a fifth (18a) and sixth (18b) transistor in Darlington configuration. A power stage as claimed in any one of the foregoing Claims , characterized in that said top (12; 12a, 12b) and bottom (13; 13a, 13b) transistor elements of said output stage (6) and said gain transistor element (18; 18a, 18b) of said gain stage (5) comprise NPN transistors. A power stage as claimed in any one of the foregoing Claims, characterized in that said first terminal of said top (12; 12a, 12b) and bottom (13; 13a, 13b) transistor elements is an emitter terminal, said second terminal is a collector terminal, and said control terminal is a base terminal.

Inventors: CHIOZZI GIORGIO, STORTI SANDRO, TAVAZZANI CLAUDIO, CHIOZZI, GIORGIO, STORTI, SANDRO, TAVAZZANI, CLAUDIO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1996
Main classification: H03F3
IPC codes: H03F3