Vertical MOS semiconductor with recessed gate and method of manufacturing the same

Abstract: A parasitic transistor of an insulated gate semiconductor device does not easily turn on, so that an SOA of the insulated gate semiconductor device is improved. P + semiconductor layers (45) having a higher impurity concentration than that N + emitter layers (44) are disposed so that the P + semiconductor layers (45) overlap adjacent edges of the N + emitter layers (44) of a U-type IGBT and so that bottom portions of the P + semiconductor layers (45) contact P base layers (43). An emitter electrode (51) contacts the P base layers (43) through the P + semiconductor layers (45). A trench pitch is small, and therefore, a parasitic transistor which is formed by an N + emitter region (4), a P base layer (3) and an N - layer (2) does not easily turn on.

Description: The present invention relates to an insulated gate semiconductor device and a method of manufacturing the same. More particularly, the present invention relates to a device structure in which a parasitic transistor of an insulated gate bipolar transistor which comprises a trench MOS gate does not turn on easily so that an safe operating area (hereinafter "SOA") is large, and also relates to a method of manufacturing the same. Fig. 26 is a partial sectional view of a conventional insulated gate semiconductor device. As an example, an insulated gate bipolar transistor (hereinafter "IGBT"), in particular, an IGBT having a trench gate structure (An IGBT having a trench gate structure will be hereinafter referred to as a "U-type IGBT.") will be described. In recent years, in a voltage oscillating circuit which serves as a high frequency invertor, a general use invertor, an AC servo, an air conditioner, etc., IGBTs have been very often used in various devices such as an intelligent power module which controls a variable speed of a tri-phase motor, to reduce energy consumption, the size and the weight of electric household appliances. While a switching characteristic, a saturation voltage and an SOA are in a trade-off relationship with each other in IGBTs, i.e., key devices in these various devices, IGBTs with a better switching characteristic, a low saturation voltage and a large SOA are demanded. In Fig. 26, denoted at 1 is a P + collector layer, denoted at 2 is an N - layer, denoted at 3 is a P base layer, denoted at 4 are N + emitter regions, denoted at 5 are trenches, denoted at 6 are gate insulation films, denoted at 7 are gate electrodes, denoted at 8 is an interlayer insulation film, denoted at 9 is an N + buffer layer, denoted at 10 is an emitter electrode, denoted at 11 is a collector electrode, and denoted at 12 are channel regions. Now, an operation of an IGBT will be described. When a predetermined collector voltage V CE is applied across the emitter electrode 10 and the collector electrode 11 and a predetermined gate voltage V GE is applied across the emitter electrode 10 and the gate electrodes 7, that is, when gates are turned on, the channel regions 12 are inverted into the N type, thereby creating channels. Through these channels, electrons are injected into the N - layer 2 from the emitter electrode 10. Injected electrons apply a forward bias across the P + collector layer 1 and the N - layer 2 so that holes are injected into the N - layer 2 from the collector electrode 11 through the P + collector layer 1 and the N + buffer layer 9. The conductivity is changed consequently, and the resistance of the N - layer 2 is largely decreased to increase a current capacity of the IGBT. Collector-emitter voltage drop during this state (ON state) in the IGBT defines an ON-voltage (V CE (sat)). To change the IGBT from an ON state into an OFF state, the gate voltage V GE applied across the emitter electrode 10 and the gate electrodes 7 is changed to 0V or a reverse bias is applied across the emitter electrode 10 and the gate electrodes 7, thereby turning the gates off. As a result, the channel regions 12 inverted into the N type return to the P type so that injection of electrons from the emitter electrode 10 stops. Electrons and holes accumulated in the N - layer 2 then flow into the collector electrode 11 and the emitter electrode 10, respectively, or recombine with each other to perish. The ON-voltage of the IGBT is primarily determined by a substantial resistance of the N - layer 2 which is necessary to hold a breakdown voltage. One of the factors which determines the substantial resistance is an ability of a MOSFET which forms the IGBT to supply electrons. In a U-type IGBT in which narrow and deep grooves (trenches) are formed in a surface of a chip and MOSFETs are formed in side walls of the trenches, the ability of the MOSFETs to supply electrons is enhanced by reducing intervals between unit cells as much as possible. In general, a cut-off current value under an applied high voltage is an important electric characteristic of an IGBT. It is therefore preferable to ensure as high cut-off current value as possible. The better this electric characteristic is, the larger a reverse bias safe operating area (hereinafter "RBSOA") becomes. Meanwhile, as can be clearly understood from Fig. 26 which shows the structure of the U-type IGBT, the U-type IGBT includes a parasitic bipolar transistor which is formed by the N + emitter regions 4, the P base layer 3 and the N - layer 2. When the parasitic bipolar transistor is turned on, the gate voltage V GE alone can not control a current which flows in the U-type IGBT any more, whereby the U-type IGBT is destroyed. Hence, as measure to enlarge the RBSOA, various device structures have been proposed in which the cell size is small, using a trench gate structure so that the parasitic bipolar transistor does not easily turn on. Fig. 27 is a partial sectional view showing an example of a conventional insulated gate semiconductor device which is described in Japanese Patent Unscreened Publication No. 60-253275. In Fig. 27, denoted at 13 is a semiconductor substrate, denoted at 14 is a first major surface of the semiconductor substrate 13, and denoted at 15 are P + regions. The other reference symbols are similar to those used in Fig. 24. The P + regions 15 of the N + emitter regions 4 are disposed simply to ensure a better contact with the emitter electrode 10. The impurity concentration of the P + regions 15 is lower than that of the N + emitter regions. In this conventional insulated gate semiconductor device, when the same mask is used as a mask for forming the N + emitter regions 4 and a mask for forming the V-shaped gate electrodes 7, alignment of masks becomes unnecessary and intervals between cells are reduced. However, since the gate electrodes 7 project from the first major surface 14 of the semiconductor substrate 13, to ensure the N + emitter regions 4 contact the P + regions 15 while allowing the interlayer insulation film 8 to be interposed across the emitter electrode 10 and the gate electrodes 7, the N + emitter regions 4 must be formed large including an additional margin, when masks are aligned to each other during formation of the interlayer insulation film 8. This serves as an obstacle to an effort to reduce the intervals between the cells. Fig. 28 is a schematic diagram showing a contact margin in the conventional technique. In Fig. 28, the gate electrodes 7 are trench type electrodes rather than V-shaped electrodes. Fig. 28 shows additional areas which are necessary for the N + emitter regions 4 to deal with misalignment of the masks (i.e., gate contact margins). Fig. 29 is a partial sectional view showing an example of a conventional insulated gate semiconductor device which is described in USP No. 5,034,785. The intervals between cells are shorter in the illustrative device since the illustrative device does not use the gate contact margins which are used in the conventional technique of Fig. 28. The device shown in Fig. 29 is a DMOS power transistor, and includes a gate of a trench structure. The gate electrodes 7 has a surface which is recessed from the first major surface 14 of the semiconductor substrate 13. Denoted at 16 is a source electrode. In the illustrative structure, the surfaces of the gate electrodes 7 is recessed from the first major surface 14 of the semiconductor substrate 13. This makes a mask unneeded to form the gate electrodes 7 and makes it unnecessary for the source electrode to have a margin for alignment of the masks. Hence, it is possible to reduce the trench pitch. However, it is necessary to form the N + source region 16 deeper than the surfaces of the gate electrodes 7. The N + source region 16 therefore tends to be deeper. Since the N + source region 16 is formed by diffusion in most cases, when the N + source region 16 is diffused deep, the N + source region 16 is diffused wide. This increases the trench pitch. Fig. 30 is a schematic diagram showing side diffusion in the conventional structure. The illustrative device is an IGBT. In Fig. 30, to ensure that the surfaces of the gate electrodes 7 are recessed from the surfaces of the N + emitter regions 4, the N + emitter regions 4 are formed deeper and therefore side diffusion of the N + emitter regions 4 is large. Hence, to make an exposed surface of the P base layer 3 and the surfaces of the N + emitter regions 4 contact each other at the emitter electrode 10, the trench pitch must be formed large. This allows the parasitic transistor to easily turn on. Another value which is related to the SOA of an element is saturation current I C (sat). The value of a current which flows in an IGBT in response to a certain applied gate voltage is expressed as I C (sat). If the value I C (sat) is too large, the parasitic transistor easily turns on, which in turn destroys the IGBT. Further information regarding the prior art can be found in the Proceedings of the International Symposium on Power Semiconductor Devices, "600V Trench IGBT in Comparison with Planar IGBT Performance," May 31, 1994, Davos, Switzerland, pages 411-416, which discusses the development of a large area trench MOS process as well as a trench IGBT. JP-A-1198076 discloses a semiconductor device for enabling the increase of latch-up yield strength. by forming trench to reduce a first conductivity type base on the source side of a vertical gate structure IGBT, and forming a source electrode stretching as far as the trench bottom, or installing, instead of the trench, a first conductivity type diffusion region of high impurity concentration. In this semiconductor device, the source side surface of a vertical gate structure IGBT is flattened, and the source side surface except the exposed region of a P + base layer is covered with a resist film. By using the resist film as a mask, a second trench is dug, the surface side region of the P + base layer is shaved off. The resist film is eliminated, and a source electrode stretching as far as the side surface and the bottom surface of the second trench is formed. A drain electrode is formed, and polysilicon is buried in the second trench to complete a semiconductor device. A P ++ high concentration diffusion region of low resistance is installed instead of the trench, and the series resistance component between the P + base layer and the source electrode is reduced. Thereby, latch-up yield strength can be improved. JP-A-6350071 discloses a longitudinal type MOS field effect transistor in which a pattern pitch is extremely miniaturized, integration density is increased, and miniaturization of a chip is realized and reduction of an ON-resistance is possible by forming a short-circuit between a source region and a diffusion region for a channel with a source electrode. In particular, on a semiconductor substrate which is to serve as a drain region, a P-type region for a channel is formed, and then a mesh-shaped N + type region for a source is formed in a plane in the manner in which a region appears here and there on the surface. Further, an U-shaped groove is formed, and a gate oxide film is formed. In order to make a short-circuit between the P-type and N + -type regions with a source electrode, a window for forming an electrode with the same width as that of the mesh of the N + -type region for a mesh-shaped source is formed. After that, an electrode for a gate, an electrode for a source, and an electrode for a drain are formed. EP-A-68945 discloses a bipolar transistor controlled by field effect by means of an isolated gate in which a bipolar semiconductor structure, the conductive and blocked states of which are controlled by an isolated gate comprises a P + type substrate constituting the emitter of a bipolar transistor, an N type epitaxial layer constituting the base, a P + type area having a large surface, constituting a collector, covered with a collector contact and surrounded by an area wherein the epitaxial N type layer is exposed, an N + type source area included in the collector area and extending along the border of the same so as to define an interval which constitutes the control gate of the structure, a resistive source access zone connected, on the one hand, to the source, and on the other hand, to the collector contact, the resistance of this zone being sufficient for preventing the structure from being rendered conductive in an irreversible manner. US-A-5,169,793 discloses a method of manufacturing an insulated gate bipolar transistor having a gate shielded region in which a p type pad well layer is formed at the surface of an n - type drain layer under a gate bonding pad and the surface thereof is provided with a p ++ type pad layer to be provided with lower resistivity. The p ++ type pad layer is connected with a source electrode through a contact hole. Since the gate electrode supplying each cell with gate potential is of a pattern having extensions in a comb-teeth form arranged along the boundary between the pad region and the cell region, there is present substantially no gate electrode under the pad. Hence, the introduction of impurities into the entire surface of the well layer under the pad region can be performed simultaneously with formation of p ++ type contact layers after the formation of the gate electrode, and accordingly, the low resistance p ++ type pad layer can be easily formed. The p ++ type pad layer serves as a low resistance path for allowing the holes flowing into the region under the pad region of the insulated gate bipolar transistor to escape to the source electrode, whereby occurrence of latch-up and an increase in the turn-off time due to the minority carriers concentrating into the border portion cell located adjacent to the pad region can be prevented. Accordingly, it is an object of the present invention to provide for an insulated gate semiconductor device which has a device structure in which a parasitic transistor does not easily turn on and therefore the SOA is improved, and a method of manufacturing such a device. To achieve these and other objects cited hereinafter, the present invention provides an insulated gate semiconductor device as reflected in independent claim 1 as well as a method of manufacturing an insulated gate semiconductor device as reflected in independent claim 7. Preferred embodiments of the invention are reflected in the dependent claims. The invention as claimed is based, inter alia, on the technical background described hereinbelow. In the insulated gate semiconductor device constructed in accordance with the present invention, the fifth semiconductor layer is disposed on the surfaces of the third and the fourth semiconductor layers to extend across the third and the fourth semiconductor layers, a junction between the fifth and the fourth semiconductor layers is exposed to a surface, and the bottom surface of the fifth semiconductor layer is located at a shallower position than the thickness of the fourth semiconductor layer. Therefore, even when the exposed surface of the third semiconductor layer which is adjacent to the fourth semiconductor layer becomes small, since the first major electrode creates a contact between the third and the fourth semiconductor layers through the fifth semiconductor layer, the cell size remains small, the ON-voltage is reduced, a parasitic transistor does not easily turn on, and the value of a current which can be terminated at turning off does not drop. Hence, the insulated gate semiconductor device uses small consumption power, an RBSOA of the insulated gate semiconductor device is large, and the reliability of the insulated gate semiconductor device is high. Since the plurality of the groove-shaped inner walls are disposed, the exposed surface of the fifth semiconductor layer is formed between adjacent inner walls, and the exposed surface extends along the inner walls in the direction of the longitudinal extension of the inner walls, it is possible to form a plurality of the control electrodes. Further, even when adjacent fourth semiconductor layers are extremely close to each other through the exposed surface of the fifth semiconductor layer, the first major electrode creates a contact between the third and the fourth semiconductor layers through the fifth semiconductor layer. In such an insulated gate semiconductor device, trench intervals are small and the device is small and dense. As the exposed surface of the fifth semiconductor layer has a scattered configuration, at the link portion of the fourth semiconductor layer which separates the exposed surface portions of the fifth semiconductor layer which are located between adjacent inner walls, the first major electrode creates a contact between the third and the fourth semiconductor layers. Therefore, trench intervals are small in the insulated gate semiconductor device, and the insulated gate semiconductor device is small and dense. Since the film covers the inner walls, the portions of the surfaces of the fourth semiconductor layers which are adjacent to each other along the inner walls and the portions of the surfaces of the fifth semiconductor layers which are adjacent to the portions of the fourth semiconductor layers, the link portions of the fourth semiconductor layers, which separate the fifth semiconductor layers which are located between adjacent inner walls, and the fifth semiconductor layers alternately contact the first major electrode, but the fourth semiconductor layers which are sandwiched by the fifth semiconductor layers and the inner walls do not contact the first major electrode. Hence, these portions serve as a resistance between the fourth semiconductor layers which contact the first major electrode. When a large current flows, the resistance induces a voltage drop within the fourth semiconductor layers. Hence, a parasitic transistor does not easily turn on in the insulated gate semiconductor device, an RBSOA of the insulated gate semiconductor device is large, the insulated gate semiconductor device is small and dense, and the reliability of the insulated gate semiconductor device is high. As the fourth semiconductor layers sandwich the fifth semiconductor layer in the form of columns, the plurality of the inner walls are formed along this column-like arrangement, the interlayer insulation film is formed on the surface of the control electrode, and the first major electrode is disposed on the surfaces of the fourth and the fifth semiconductor layers and the interlayer insulation film, it is possible to form a plurality of the control electrodes. It is also possible to form the exposed surface of the fifth semiconductor layer small. Even without creating the additional area to the interlayer insulation film for the sake of aligning a mask, the first major electrode creates a contact between the third and the fourth semiconductor layers through the fifth semiconductor layer. This reduces trench intervals and the cell size. Therefore, the ON-voltage is reduced, a parasitic transistor does not easily turn on, and the value of a current which can be terminated at turning off does not drop. Hence, the insulated gate semiconductor device uses small consumption power, an RBSOA of the insulated gate semiconductor device is large, the reliability of the insulated gate semiconductor device is high, and the insulated gate semiconductor device is small and dense. As the exposed surface of the fifth semiconductor layer has a scattered configuration, the link portion of the fourth semiconductor layer which separates exposed surface portions of the fifth semiconductor layer which are located between adjacent inner walls is not coated with the interlayer insulation film. This link portion of the fourth semiconductor layer allows the first major electrode to create a contact between the third and the fourth semiconductor layers. Hence, the insulated gate semiconductor device has even smaller trench intervals, a small size and a high density. On the fourth semiconductor layers which are disposed through the fifth semiconductor layer which has a scattered configuration between adjacent inner walls, the insulation film may cover those fourth semiconductor layers which are adjacent to each other along the wall surfaces and the portion of the fifth semiconductor layer which is in the vicinity of those fourth semiconductor layers. Hence, the link portions of the fourth semiconductor layers, which separate the fifth semiconductor layer into the scattered configuration, and the fifth semiconductor layer alternately contact the first major electrode. Since the fourth semiconductor layers which are sandwiched between the fifth semiconductor layer and the inner walls do not contact the first major electrode in this configuration, these portions serve as a resistance between the fourth semiconductor layers which contact the first major electrode. When a large current flows, the resistance induces a voltage drop within the fourth semiconductor layers. Hence, a parasitic transistor does not easily turn on in the insulated gate semiconductor device, and an RBSOA of the insulated gate semiconductor device is large. Further, the breakdown characteristic during shorting is improved without increasing the cell size. The insulated gate semiconductor device is small and dense, and the reliability of the insulated gate semiconductor device is high. In the method of manufacturing an insulated gate semiconductor device according to the present invention, even when the exposed surface of the third semiconductor layer becomes small, the first major electrode creates a contact between the third and the fourth semiconductor layers through the fifth semiconductor layer. Hence, it is possible to manufacture an insulated gate semiconductor device which uses small consumption power, which has a large RBSOA and which is highly reliable, at an inexpensive cost without complex manufacturing steps. It is possible to manufacture an insulated gate semiconductor device in which an additional area to the interlayer insulation film for the sake of aligning a mask is small, cell intervals are small, consumption power is small, an RBSOA is large, and the reliability is high, at an inexpensive cost without complex manufacturing steps. If the interlayer insulation film does not cover the link portions of the fourth semiconductor layers, which separate the exposed surface of the fifth semiconductor layer which are located between adjacent inner walls, and the link portions of the fourth semiconductor layers and the fifth semiconductor layer allow the first major electrode to create a contact between the third and the fourth semiconductor layers, it is possible to manufacture an insulated gate semiconductor device in which cell intervals are small, at an inexpensive cost without complex manufacturing steps. The fourth semiconductor layers which are sandwiched between the fifth semiconductor layer and the inner walls serve as a resistance between the fourth semiconductor layers which contact the first major electrode. When a large current flows, the resistance induces a voltage drop within the fourth semiconductor layers. Hence, it is possible to manufacture a small, dense and reliable insulated gate semiconductor device in which a parasitic transistor does not easily turn on and an RBSOA is large, at an inexpensive cost without complex manufacturing steps. Having given regard to the above background of the invention, the invention itself will now be discussed on the basis of figures illustrating specific embodiments. The aforementioned as well as other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings, in which Fig. 1 is a plan view of an insulated gate semiconductor device according to the present invention; Fig. 2 is a partial plan view showing some cells of an insulated gate semiconductor device not forming part of the claimed invention Fig. 3 is a partial cross sectional view showing some cells of the insulated gate semiconductor device taken along lines A-A; Fig. 4 is a schematic partial cross sectional view showing the present invention; Fig. 5 is a graph showing a relationship between a trench pitch and an ON-voltage in a U-type IGBT; Figs. 6 to 14 are partial cross sectional views of an element during manufacturing steps of the insulated gate semiconductor device according to the present invention; Fig. 15 is a partial plan view of an insulated gate semiconductor device according to a first embodiment of the present invention; Fig. 16 is a partial cross sectional view of the insulated gate semiconductor device according to the first embodiment of the present invention, taken along lines A-A; Fig. 17 is a partial cross sectional view of the insulated gate semiconductor device according to the first embodiment of the present invention, taken along lines B-B; Fig. 18 is a partial plan view of an insulated gate semiconductor device of a related technology, not forming part of the claimed invention; Fig. 19 is a partial cross sectional view of the insulated gate semiconductor device, taken along lines A-A; Fig. 20 is a partial cross sectional view of the insulated gate semiconductor device, taken along lines B-B; Fig. 21 is a partial plan view of an insulated gate semiconductor device according to another preferred embodiment of the present invention; Fig. 22 is a partial cross sectional view of the insulated gate semiconductor device of the Fig. 21 taken along lines A-A; Fig. 23 is a partial cross sectional view of the insulated gate semiconductor device of Fig. 21 taken along lines B-B; Figs. 24 and 25 are partial cross sectional views of an element during further manufacturing steps of the insulated gate semiconductor device; Fig. 26 is a partial sectional view of a conventional insulated gate semiconductor device; Fig. 27 is a partial sectional view of another conventional insulated gate semiconductor device; Fig. 28 is a schematic diagram showing a contact margin in the another conventional insulated gate semiconductor device; Fig. 29 is a partial sectional view of still another conventional insulated gate semiconductor device; and Fig. 30 is a schematic diagram showing side diffusion in the still another conventional insulated gate semiconductor device. Fig. 1 is a plan view of an insulated gate semiconductor device according to the present invention. As an example of an insulated gate semiconductor device, a U-type IGBT will be described in the following. Fig. 2 is a partial plan view showing some cells of the U-type IGBT of Fig. 1, and Fig. 3 is a partial cross sectional view showing some cells of Fig. 2 taken along lines A-A. In Fig. 2, the cells are shown as they are with an emitter electrode 51 and an interlayer insulation film 50 removed. In Fig. 1, denoted at 30 is a U-type IGBT, denoted at 31 is an emitter electrode which functions as a first major electrode, denoted at 32 are gate lines, denoted at 33 is a gate pad, and denoted at 34 is a part of cells. In Figs. 2 and 3, denoted at 41 is a P + collector layer which serves as a first semiconductor layer, denoted at 42 is an N - layer which serves as a second semiconductor layer, denoted at 43 is a P base layer which serves as a third semiconductor layer, denoted at 44 are N + emitter layers which serve as a fourth semiconductor layer, denoted at 45 are P + semiconductor layers which serve as a fifth semiconductor layer, denoted at 46 is an N + buffer layer, denoted at 47 are inner walls each formed in the shape of a groove. Trenches are defined by the inner walls 47. Denoted at 48 are gate insulation films, denoted at 49 are gate electrodes each serving as a control electrode, denoted at 50 is the interlayer insulation film, and denoted at 51 is the emitter electrode which serves as the first major electrode. The emitter electrode 51 is a portion of the emitter electrode 31 of Fig. 1. Denoted at 52 is a collector electrode which serves as a second major electrode, and denoted at 53 are channel regions. Areas C defined by brackets and dashed-and-dotted lines in Fig. 2 are areas which are covered with the interlayer insulation film 50. In the embodiments which will be described later, similar reference symbols denote similar structures. Usually, the gate insulation films 48 are thermal oxidation films of SiO 2 , and the gate electrodes 49 are made of polysilicon doped with N-type impurities. The interlayer insulation film 50 is made of silicate glass containing boron and phosphorus (hereinafter "BPSG"). The emitter electrode 51, the gate lines 32 and the gate pad 33 are made of Al containing Si (hereinafter "Al-Si"). The collector electrode 52 is made of AlMoNiAu alloy. The gate lines 32 are connected to the gate electrodes 49 so that polysilicon portions in paths from the gate electrodes 49 to the gate pad 33 are small so that an electric resistance from the gate electrodes 49 to the gate pad 33 is reduced and so that the element is controlled uniformly over the entire surface of the element. In this U-type IGBT, the N + buffer layer 46 is disposed on a surface of the P + collector layer 41, and the N - layer 42 is disposed on a surface of the N + buffer layer 46. Further, the P base layer 43 is disposed on the N - layer 42. The N + emitter layers 44 are disposed on a surface of the P base layer 43 at intervals so as to form stripes. Along the longitudinal extension of the stripes of the N + emitter layers 44, the trench-shaped inner walls 47 are formed, extending from surfaces of the N + emitter layers 44 and penetrating into the N - layer 42 through the P base layer 43. In a surface defined by the P base layer 43 and the N + emitter layers 44 which are present between two adjacent inner walls 47, the P + semiconductor layers 45 are formed in such a manner that bottom surfaces of the P + semiconductor layers 45 contact the P base layer 43, and partially overlap the N + emitter layers 44 at the both ends, and that junctions between the N + emitter layers 44 and the P + semiconductor layers 45 are exposed to a surface. The impurity concentration of the P + semiconductor layers 45 is generally higher than that of the N + emitter layers 44. If the impurity concentration of the N + emitter layers 44 is set at about 1×(10 18 - 10 19 ), the impurity concentration of the P + semiconductor layers 45 is set around 2×(10 18 - 10 19 ), i.e., about twice higher than the impurity concentration of the N + emitter layers 44. The gate insulation films 48 are disposed in the inner walls 47. The gate insulation films 48 extend up to the surfaces of the N + emitter layers 44 which are adjacent to openings 56 of the inner walls 47. In each trench which is surrounded by each inner wall 47 through each gate insulation film 48, each gate electrode 49 is filled in up to each opening at the surfaces of the N + emitter layers 44. Surfaces of the gate electrodes 49 are lower than surfaces of the gate insulation films 48 which are formed on the surfaces of the N + emitter layers 44 which are adjacent to the openings 56 of the inner walls 47. In Fig. 3, the surfaces of the gate electrodes 49 are flush with the surfaces of the N + emitter layers 44. Although the surfaces of the gate electrodes 49 may be further recessed from the surfaces of the N + emitter layers 44, to form channels, the surfaces of the gate electrodes 49 must be located at a shallower position than the bottom of the N + emitters layers 44. The gate electrodes 49 are faced with the surfaces of the P base layer 43 through the gate insulation films 48. The surfaces of the P base layer 43 serves as the channel regions 53. The surfaces of the gate electrodes 49 are covered with the interlayer insulation film 50. Through the interlayer insulation film 50, the emitter electrode 51 is disposed on a surface of the element in which the N + emitter layers 44 and the P + semiconductor layers 45 are formed. The N + emitter layers 44 and the P base layer 43 contact the emitter electrode 51 through the P + semiconductor layers 45. The gate lines 32 and the gate pad 33 which are connected to the gate electrodes 49 are disposed on the surface of the element, while insulated from the N + emitter layers 44 and the P + semiconductor layers 45. The collector electrode 52 is disposed on the other surface of the P + collector layer 41. If the element has a breakdown voltage on the order of 2,000 V, for example, the thickness from the surface of the element, i.e., the exposed surfaces of the P + semiconductor layers 45, or from the surfaces of the N + emitter layers 44 to a boundary between the N - layer 42 and the N + buffer layer 46 is about 200 µm, the impurity concentration of the N - layer 42 is 5×10 13 cm -3 , the intervals between the trench-shaped inner walls 47, i.e., the intervals between the cells are about 4 µm, and the depth of the inner walls 47 measured from the surfaces of the P + semiconductor layers 45 is about 8 µm. The depth of a junction between bottom surfaces of the N + emitter layers 44 and the P base layer 43 is about 1 µm, either from the N + emitter layers 44 or from the surfaces of the P + semiconductor layers 45. The thickness of the N + buffer layer 46 is about 10 µm, and the thickness of the P + collector layer 41 is about 300 µm. Now, an operation will be described. When a predetermined collector voltage V CE is applied across the emitter electrode 51 and the collector electrode 52 and a predetermined gate voltage V GE is applied across the emitter electrode 51 and the gate electrodes 49, that is, when gates are turned on, the channel regions 53 are inverted into the N type, thereby creating channels. Through these channels, electrons are injected into the N - layer 42 from the emitter electrode 51. Injected electrons apply a forward bias across the P + collector layer 41 and the N - layer 42 through the N + buffer layer 46 so that holes are injected into the N - layer 42 from the collector electrode 52 through the P + collector layer 41 and the N + buffer layer 46. The conductivity is changed consequently, and the resistance of the N - layer 42 is largely decreased to increase a current capacity of the IGBT. To change the IGBT from an ON state into an OFF state, the gate voltage V GE applied across the emitter electrode 51 and the gate electrodes 49 is changed to 0V or a reverse bias is applied across the emitter electrode 51 and the gate electrodes 49, thereby turning the gates off. As a result, the channel regions 53 inverted into the N type return to the P type so that injection of electrons from the emitter electrode 51 stops and injection of holes from the P + collector layer 41 into the N - layer 42 stops. Electrons and holes accumulated in the N - layer 42 then flow into the collector electrode 52 and the emitter electrode 51, respectively, or recombine with each other to perish. Since holes can easily move within the P + semiconductor layers 45 at this stage, the switching speed becomes faster. Fig. 4 is a schematic partial cross sectional view showing the present invention. Fig. 4 describes an effect of the P + semiconductor layers 45 in the present invention. The surfaces of the gate electrodes 49 are located at about half the depth of the N + emitter layers 44, measured from the surfaces of the N + emitter layers 44. When the surfaces of the gate electrodes 49 are located at a low position, the thickness of the N + emitter layers 44 needs be large. Since the N + emitter layers 44 are formed by diffusion in most cases, when the N + emitter layers 44 are formed thick, due to side diffusion, adjacent edge portions of the N + emitter layers 44 which are disposed between adjacent trench-shaped inner walls 47 are positioned extremely close to each other. This forces an exposed surfaces of the P base layer 43 to be extremely small. In some cases, the adjacent edge portions of the N + emitter layers 44 contact each other, thereby completely eliminating the exposed surfaces of the P base layer 43. When this happens, it is impossible for the P base layer 43 to contact the emitter electrode 51. In conventional techniques, this problem is prevented by increasing the trench intervals. Instead, between the edge portions of the N + emitter layers 44 which are positioned between the inner walls 47, the P + semiconductor layers 45 are formed partially overlapping the N + emitter layers 44 so that the bottom portions of the P + semiconductor layers 45 contact the P base layer 43, and further, the junctions between the P + semiconductor layers 45 and the N + emitter layers 44 are exposed to the surface of the element. As a result, a large contact is made between the P + semiconductor layers 45 and the emitter electrode 51. Hence, it is possible to reduce the trench intervals, without becoming sensitive to whether the adjacent edge portions of the N + emitter layers 44 are close to each other. When the surfaces of the gate electrodes 49 are at a position recessed from the surfaces of the N + emitter layers 44, in particular, it is necessary to form the N + emitter layers 44 thick. Therefore, because of reduced trench intervals, the adjacent edge portions of the N + emitter layers 44 are positioned close to each other, or even may contact each other in some cases. However, even if the adjacent edge portions of the N + emitter layers 44 contact each other, since the P + semiconductor layers 45 penetrating the N + emitter layers 44 contact the P base layer 43, the P base layer 43 and the N + emitter layers 44 contact the emitter electrode 51 through the P + semiconductor layers 45. Since the N + emitter layers 44 are formed by diffusion into the P base layer 43, the impurity concentration of the N + emitter layers 44 must be higher than that of the P base layer 43. Further, since the P + semiconductor layers 45 are diffused so as to overlap adjacent edge portions of the N + emitter layers 44, the impurity concentration of the P + semiconductor layers 45 must be higher than that of the N + emitter layers 44. If the P + semiconductor layers 45 are formed first and the N + emitter layers 44 are then formed to have a higher impurity concentration than that of the P + semiconductor layers 45, adjacent edge portions of the N + emitter layers 44 come close to each other. As a result, the P + semiconductor layers 45 are eliminated by the N + emitter layers 44 in the present embodiment, and therefore, the effect of disposing the P + semiconductor layers 45 in the first preferred embodiment is not created. Fig. 5 is a graph showing a relationship between the trench pitch and the ON-voltage in the U-type IGBT. As shown in Fig. 5, the smaller the trench pitch of the U-type IGBTs, the lower the ON-voltage becomes and hence the better various characteristics which affect the ON-voltage become. In the present invention, since the P + semiconductor layers 45 are formed so as to overlap adjacent edge portions of the N + emitter layers 44 and so as to contact the P base layer 43, the emitter electrode 51 and the P base layer 43 contact each other through the P + semiconductor layers 45. As a result, the trench pitch and hence the ON-voltage are reduced. Further, the element becomes smaller and denser and the reliability is improved. In addition, since the trench pitch is small, the parasitic transistor which is formed by the N + emitter regions 4, the P base layer 3 and the N - layer 2 does not easily turn on. That is, even when the IGBT within the RBSOA is in the OFF state, electrons and holes accumulated in the N - layer 2 (the N + buffer layer 9 if the N + buffer layer 9 is disposed) flow into the collector electrode 11 and the emitter electrode 10, respectively, or recombine with each other to perish, as in the case of a change from the normal ON state into the OFF state. In this case, when holes flow into the emitter electrode 10, if the cell size is small, the quantity of holes which flow into one cell becomes small. Since the hole current serves as a base current of the parasitic bipolar transistor, if the potential of the P base layer 3 exceeds a built-in potential (0.6 V, in general) between the P base layer 3 and the N + emitter regions 4, the parasitic bipolar transistor turns on. However, a voltage drop becomes small since the hole current is small, and therefore, the built-in potential between the P base layer 3 and the N + emitter regions 4 is not easily reached, thereby making it difficult for the parasitic bipolar transistor to turn on. In other words, the RBSOA becomes large. Next, an example of a manufacturing method of the U-type IGBT according to the invention will be described. Figs. 6 to 14 are partial cross sectional views showing the element during the respective stages of manufacturing. First, an N + layer 61 and an N - layer 62 are epitaxially grown on P + silicon substrate 60, successively. Next, P-type impurities are implanted and annealed in a surface of the N - layer 62, whereby a P base layer 63 is defined (See Fig. 6). Following this, a resist is stacked on a surface of the P base layer 63, and through photolithographic processes, a resist pattern 64 which includes a plurality of strip-shaped openings is formed. Using the resist pattern 64 as a mask, the surface of the P base layer 63 is doped with N-type impurities to a high concentration. The resist pattern 64 is thereafter removed. The impurities are annealed and diffused to define N + emitter regions 65 (See Fig. 7). An oxide film 66 which serves as a shielding film is then formed on a surface of the P base layer 63 and the N + emitter regions 65. On surfaces of the N + emitter regions 65, a silicon etching mask is formed which includes a strip-like shaped opening which has a narrower width than the N + emitter regions 65, using the oxide film 66. Using the silicon etching mask, RIE (Reactive Ion Etching) is performed, thereby defining trench-shaped inner walls 67 which extend from the surfaces of the N + emitter regions 65 and penetrate into the N - layer 62 (See Fig. 8). The oxide film 66 is then removed by etching. Next, a thermal oxidation film 68 which serves as an insulation film is formed on surfaces of the inner walls 67, a surface of the P base layer 63 and the surfaces of the N + emitter regions 65. Electrically conductive polysilicon 69 doped with N-type impurities is stacked on the thermal oxidation film 68, whereby the grooves formed by the inner walls 67 are filled up (See Fig. 9). The stacked polysilicon 69 is then etched back so that a surface of the polysilicon 69 filling up the grooves formed by the inner walls 67 is recessed from a surface of the thermal oxidation film 68 which is formed on the surfaces of the N + emitter regions 65 (See Fig. 10). Etching back must be performed so that the surface of the polysilicon 69 is positioned at a shallower position than the bottom of the N + emitter regions 65. A resist 70 is then stacked on the surface of the polysilicon 69 filling up the grooves formed by the inner walls 67 and on the surface of the thermal oxidation film 68. In the resist 70, an opening is formed by photolithographic processes to surround the surface of the P base layer 63 and portions of the N + emitter regions 65 which are adjacent to the P base layer 63 and which extend along the inner walls 67, whereby a resist pattern is obtained. Using the resist pattern as a mask, P-type impurities are implanted through the thermal oxidation film 68, at a higher impurity concentration than that of the N + emitter regions 65. The resist pattern is thereafter removed. By a thermal process, the P-type impurities are diffused shallower than the bottom of the N + emitter regions 65, to define a P + semiconductor layer 71 whose bottom surface contacts the P base layer 63 (See Fig. 11). Next, a BPSG 72 which serves as an insulation is stacked on the surface of the polysilicon 69 filling up the grooves formed by the inner walls 67 and on the surface of the thermal oxidation film 68 (See Fig. 12). Following this, a resist 73 is stacked on a surface of the BPSG 72. In the resist 73, an opening is formed by photolithographic processes which surrounds the P + semiconductor layer 71 and portions of the N + emitter regions 65 which are adjacent to the P + semiconductor layer 71 and which extend along the inner walls 67, whereby a resist pattern is obtained. Using the resist pattern as a mask, the BPSG 72 and the thermal oxidation film 68 are etched so that an interlayer insulation film 72 is formed on the surface of the polysilicon 69 filling up the grooves formed by the inner walls 67 (See Fig. 13). The resist pattern is thereafter removed. To short-circuit the P + semiconductor layer 71 and the N + emitter regions 65 which are exposed by etching, Al-Si is stacked which serves as a conductive layer on a surface of the element in which the P + semiconductor layer 71, the N + emitter regions 65 and the interlayer insulation film 72 are formed. This creates a gate line and a gate pad at the same time which are connected to the polysilicon 69 which is buried in the grooves which are defined by the emitter electrode 73 and the inner walls 67 (See Fig. 14). Further, AlMoNiAu alloy which serves as a conductive layer is stacked on the surface of the P + silicon substrate 60, thereby forming a collector electrode 75. Through such manufacturing processes, the U-type IGBT is manufactured at an inexpensive cost. Fig. 15 is a partial plan view of an insulated gate semiconductor device according to an embodiment of the present invention, Fig. 16 is a partial cross sectional view of some cells of Fig. 15 taken along lines A-A, and Fig. 17 is a partial cross sectional view of some cells of Fig. 15 taken along lines B-B. In Fig. 15, the cells are shown as they are with the emitter electrode 51 and the interlayer insulation film 50 removed. Areas C defined by brackets and dashed-and-dotted lines in Fig. 15 are areas which are covered with the interlayer insulation film 50. In Figs. 15, 16 and 17, in the U-type IGBT according to the present embodiment, the N + emitter layers 44 which are formed between the groove-shaped inner walls 47 have a ladder-like plan configuration. In other words, the N + emitter layers 44 are arranged in the shape of strips, sandwiching the exposed surfaces of the P + semiconductor layers 45. The groove-shaped inner walls 47 including openings at the surfaces of the N + emitter layers 44 extend along the longitudinal direction of the N + emitter layers 44. Adjacent N + emitter layers 44 which are disposed between the gate electrodes 49 which are buried in the inner walls are connected to each other through link portions 55. The exposed surfaces of the P + semiconductor layers 45 and the link portions 55 are disposed alternately. The area C of the interlayer insulation film 50 covers the gate electrodes 49 and extends over adjacent N + emitter layers 44 which are adjacent to and along the groove-shaped inner walls 47, but does not extend over the exposed surfaces of the P + semiconductor layers 45. The illustrative U-type IGBT is otherwise similar in structure to the U-type IGBT according to Fig. 3. Since the plan configuration of the N + emitter layers 44 is a ladder-like configuration, a contact area at which the emitter electrode 51 contacts the N + emitter layers 44 is ensured by the link portions 55 as well, which eliminates the necessity to additionally create an additional contact area to deal with misalignment of masks. That is, since it is not necessary to ensure an additional area to deal with misalignment of masks when the emitter electrode 73 shown in Fig. 13 is formed and since the cell intervals can be reduced accordingly, as compared in the structure in which the N + emitter layers 44 are disposed simply to extend along the gate electrodes 49 as shown in Fig. 2, it is possible for the cells to have fine geometry. Further, it is possible to arrange contact areas in a good balance all over the element. Hence, the element is formed denser and to have a low ON-voltage. It is possible to unify operation characteristics of the respective cells all over the element. In addition, when the plan configuration of the N + emitter layers 44 is a ladder-like configuration, the P + semiconductor layers 45 are not formed, and the exposed surfaces of the P base layer 43 is simply formed, the thicker the N + emitter layers 44 become, the wider the link portions 55 of the N + emitter layers 44 become due to diffusion in the horizontal direction, whereby the quantity of a hole current which flows immediately below the link portions 55 becomes large. Since the holes serve as a base current for the parasitic transistor which is formed by the N + emitter regions 44, the P base layer 43 and the N - layer 42, the parasitic transistor is easily turned on. However, since the P + semiconductor layers 45 are disposed which restrict the diffusion of the link portions 55 in the direction of the width of the link portions 55, the parasitic transistor does not tend to turn on. Hence, it is possible to prevent a reduction of the RBSOA. As compared with the manufacturing processes according to Figs. 6-14, the manufacturing processes according to the present embodiment use a different resist pattern to form the N + emitter regions 65. In the manufacturing processes according to the present embodiment, the resist is stacked on the surface of the P base layer 63, the plurality of the openings which are in the shape of parallel strips and the openings which are linked to these openings are formed by photolithographic processes, the resist pattern in which resists are left scattered in the shape of columns is formed, and using this resist pattern 64 as a mask, N-type impurities are implanted into the surface of the P base layer 63 at a high doping concentration and diffused by annealing to thereby define the N + emitter regions 65. Further, unlike in the manufacturing processes according to Figs. 6-14, after etching back the polysilicon 69, the P + semiconductor layers 71 are formed using a resist pattern which has a different shape. In a resist, openings are formed in correspondence with the exposed surfaces of the P base layers 63 which are formed on the N + emitter regions 65 in a scattered configuration. Using such a resist as a resist pattern, impurities are implanted and then diffused by thermal processing, to thereby define the P + semiconductor layers 71. Fig. 18 is a partial plan view of a U-type IGBT according to an alternative configuration not covered by the scope of the present invention, Fig. 19 is a partial cross sectional view of some cells of Fig. 18 taken along lines A-A, and Fig. 20 is a partial cross sectional view of some cells of Fig. 18 taken along lines B-B. In Fig. 18, the cells are shown as they are with the emitter electrode 51 and the interlayer insulation film 50 removed. Areas C defined by brackets and dashed-and-dotted lines in Fig. 18 are areas which are covered with the interlayer insulation film 50. In Figs. 18, 19 and 20, in the U-type IGBT according to this alternative configuration, the N + emitter layers 44 which are formed between the groove-shaped inner walls 47 have a ladder-like plan configuration. In this configuration, the P + semiconductor layers 45 are not disposed. Exposed surfaces of the P base layer 43 are formed in a scattered configuration in the N + emitter layers 44 which are present between the inner walls 47, along the longitudinal extension of the inner walls 47. That is, the N + emitter layers 44 are arranged in the shape of strips, sandwiching the exposed surfaces of the P base layer 43. The groove-shaped inner walls 47, which include openings at the surfaces of the N + emitter layers 44, extend along the longitudinal extension of the N + emitter layers 44. Adjacent N + emitter layers 44, which are disposed between the gate electrodes 49 which are buried in the inner walls, are connected to each other through the link portions 55. The exposed surfaces of the P base layer 43 and the link portions 55 are disposed alternately. The areas C of the interlayer insulation film 50 cover the gate electrodes 49, the N + emitter layers 44 which are adjacent to and along the groove-shaped inner walls 47, and further extend over the P base layer 43 which is in the vicinity of the N + emitter layers 44. Hence, the emitter electrode 51 contacts the link portions 55 linking the N + emitter layers 44 and the exposed surfaces of the P base layer 43, alternately. However, between the link portions 55 which are arranged in a scattered configuration, the N + emitter layers 44 which are sandwiched by the exposed surfaces of the P base layer 43 and the groove-shaped inner walls 47 are covered with the interlayer insulation film 50. Hence, these N + emitter layers 44 do not contact the emitter electrode 51. The N + emitter layers 44 which are sandwiched by the exposed surfaces of the P base layer 43 and the groove-shaped inner walls 47 therefore serve as emitter resistance regions 57. This means that emitter resistances are interposed, associated with the emitter electrode. Next, an operation according to this alternative configuration will be described. Since emitter resistance values of the emitter resistance regions 57 which are sandwiched by the exposed surfaces of the P base layer 43 and the groove-shaped inner walls 47 are small, when a current as small as a rated current flows, the emitter resistances of the emitter resistance regions 57 are almost non-existent. Alternatively, the emitter resistance regions 57 are formed so as to have such emitter resistance values which do not change V CE (sat). However, even if the emitter resistances are determined not to change V CE (sat), when a large current flows as in shorting, as far as emitter resistances are disposed, a voltage drop occurs at the N + emitter layers 44 as well. Such a voltage drop functions to eliminate a voltage difference between the P base layer 43 and the N + emitter layers 44. In short, such a voltage drop functions to prevent the built-in potential (0.6 V, in general) of the parasitic transistor which is formed by the N + emitter regions 44, the P base layer 43 and the N - layer 42 from getting exceeded, thereby making it difficult for the parasitic transistor to turn on. Hence, the RBSOA is large. Another current characteristic which is associated with destruction of the element is I C (sat). When shorting occurs, for instance, that is, the IGBT turns on while a high voltage is applied to the IGBT, a current which flows in the. IGBT changes depends on I C (sat). Heat which is generated during short-circuit condition is determined by: Applied Voltage × Current Flowing in IGBT × Short-circuit Condition Time When the IGBT reaches at a certain temperature because of such generated heat, the IGBT is destroyed. Meanwhile, it is known that I C (sat) becomes smaller if an emitter resistance is disposed. In this alternative configuration, the emitter resistance regions 57 are formed within a simple structure in which the interlayer insulation film 50 covers the N + emitter regions 44 which are sandwiched by the exposed surfaces of the P base layer 43 and the groove-shaped inner walls 47, and a breakdown characteristic during short-curcuit condition is improved due to the emitter resistances. The manufacturing processes according to this alternative configuration are different from the manufacturing processes according to the second preferred embodiment in that the step of forming the P + semiconductor layers 71 is omitted, and in that the openings surrounding the link portions linking the P base layers 63 and the N + emitter regions 65 are formed in the resist 73 which is stacked during the step of forming the interlayer insulation film, at areas except for portions of the N + emitter regions 65 which extend along the inner walls 67 and except for portions of the exposed surfaces of the P base layers 63 which are partially close to the N + emitter regions 65, to thereby obtain a resist pattern. Fig. 21 is a partial plan view of a U-type IGBT according to another preferred embodiment of the present invention, Fig. 22 is a partial cross sectional view of some cells of Fig. 21 taken along lines A-A, and Fig. 23 is a partial cross sectional view of some cells of Fig. 21 taken along lines B-B. In Fig. 21, the cells are shown as they are with the emitter electrode 51 and the interlayer insulation film 50 removed. Areas C defined by brackets and dashed-and-dotted lines in Fig. 21 are areas which are covered with the interlayer insulation film 50. In Figs. 21, 22 and 23, in the U-type IGBT according to the present embodiment, the N + emitter layers 44 which are formed between the groove-shaped inner walls 47 have a ladder-like plan configuration. That is, the N + emitter layers 44 are arranged in the shape of strips, sandwiching the exposed surfaces of the P + semiconductor layers 45. The groove-shaped inner walls 47, which include openings at the surfaces of the N + emitter layers 44, extend along the longitudinal extension of the N + emitter layers 44. The N + emitter layers 44 which are present between the gate electrodes 49 which are buried in the inner walls are connected to each other through the link portions 55. The exposed surfaces of the P + semiconductor layers 45 and the link portions 55 are disposed alternately. The areas C of the interlayer insulation film 50 cover the gate electrodes 49 and extend over adjacent N + emitter layers 44 which are adjacent to and along the groove-shaped inner walls 47, and further extend over the exposed surfaces of the P + semiconductor layers 45. The emitter electrode 51 contacts the link portions 55 linking the N + emitter layers 44 and the exposed surfaces of the P + semiconductor layers 45, alternately. However, between the link portions 55 which are arranged in a scattered configuration, the N + emitter layers 44 which are sandwiched by the exposed surfaces of the P + semiconductor layers 45 and the groove-shaped inner walls 47 are covered with the interlayer insulation film 50. Hence, these N + emitter layers 44 do not contact the emitter electrode 51. The N + emitter layers 44 which are sandwiched by the exposed surfaces of the P + semiconductor layers 45 and the groove-shaped inner walls 47 therefore serve as the emitter resistance regions 57. This means that emitter resistances are interposed, associated with the emitter electrode. Hence, as in the alternative configuration mentioned above, when a large current flows as in short-circuit condition, as far as emitter resistances are disposed, a voltage drop occurs at the N + emitter layers 44 as well. Such a voltage drop functions to eliminate a voltage difference between the P base layer 43 and the N + emitter layers 44. That is, such a voltage drop functions to prevent the built-in potential (0.6 V, in general) of the parasitic transistor which is formed by the N + emitter regions 44, the P base layer 43 and the N - layer 42 from getting exceeded, thereby making it difficult for the parasitic transistor to turn on. Hence, the RBSOA is large. Further, as in the alternative configuration, the emitter resistance regions 57 are formed within a simple structure in which the interlayer insulation film 50 covers the N + emitter regions 44 which are sandwiched by the exposed surfaces of the P base layer 43 and the groove-shaped inner walls 47, and a breakdown characteristic during short-circuit condition is improved due to the emitter resistances. Still further, the structure according to the present embodiment is the same as the structure according to the alternative configuration as it is modified to dispose the P + semiconductor layers 45 in the exposed surfaces of the P base layer 43. As in the first preferred embodiment, the P + semiconductor layers 45 have an impurity concentration higher than that of the N + emitter regions 44. If the impurity concentration of the N + emitter layers 44 is set at about 1×(10 18 - 10 19 ), the impurity concentration of the P + semiconductor layers 45 is set around 2 × (10 18 - 10 19 ), i.e., about twice higher than the impurity concentration of the N + emitter layers 44. When diffusion of N + impurities in the horizontal direction during formation of the N + emitter layers 44 is insufficient or when the gate contact margin is not formed sufficiently large during formation of the interlayer insulation film 50, the adjacent edge portions of the N + emitter layers 44 which are disposed between adjacent trench-shaped inner walls 47 are positioned extremely close to each other. To avoid this, there has been no conventional way but to increase the trench intervals. However, even in such a case, since the P + semiconductor layers 45 are disposed between the adjacent edge portions of the N + emitter layers 44, the N + emitter layers 44 and the P base layer 43 contact each other through the P + semiconductor layers 45 and the emitter electrode. Since this reduces the trench intervals, the parasitic transistor does not easily turn on. The ON-voltage is reduced and the density of the element is increased. Further, according to the present embodiment, the emitter resistance regions 57 are formed within a simple structure in which the diffusion regions of the P + semiconductor layers 45 are expanded, and that the N + emitter layers 44, which are sandwiched between the exposed surfaces of the P + semiconductor layers 45 and the groove-shaped inner walls 47, are covered with the interlayer insulation film 50. Therefore, the breakdown characteristic during shorting is improved without creating a space for disposing emitter resistances and without increasing the cell size. In addition, the P + semiconductor layers 45 are formed thinner than the N + emitter layers 44 in Fig. 22. However, according to the present embodiment, through the P + semiconductor layers 45 and the emitter electrode, the contact between the N + emitter layers 44 and the P base layer 43 is made within the link portions 55 of the N + emitter layers 44, not within the N + emitter layers 44 which are sandwiched by the exposed surfaces of the P + layer 45 and the groove-shaped inner walls 47. Hence, even if the N + emitter layers 44 sandwiched by the exposed surfaces of the P + layer 45 and the groove-shaped inner walls 47 are formed small as a result of the side diffusion during formation of the P + semiconductor layers 45, since the N + emitter layers 44 only have to be large enough to form the emitter resistance regions 57, it is not always necessary to diffuse the P + semiconductor layers 45 shallower than the bottom of the N + emitter layers 44, considering side diffusion. Figs. 24 and 25 are partial cross sectional views of a cell during manufacturing steps in the present embodiment. As compared with the manufacturing processes according to Figs. 6-14 the manufacturing processes according to the present embodiment use a different resist pattern to form the N + emitter regions 65, and also use a different resist pattern to form the interlayer insulation film which is shown in Fig. 13. The other manufacturing steps are similar. More precisely, the resist is stacked on the surface of the P base layer 63, the plurality of the openings which are in the shape of parallel strips and the openings which are linked to these openings are formed by photolithographic processes, the resist pattern in which resists are left scattered in the shape of columns is formed, and using this resist pattern 64 as a mask, N-type impurities are implanted into the surface of the P base layer 63 at a high doping concentration and diffused by annealing to thereby define the N + emitter regions 65. Further, after forming the P + semiconductor layers 71 along the inner walls 67 so that the P + semiconductor layers 71 and the link portions of the N + emitter regions 65 appear alternately, the BPSG 72 is stacked on the surface of the polysilicon 69 filling up the grooves formed by the inner walls 67 and on the surface of the thermal oxidation film 68, and the resist 73 is stacked on a surface of the BPSG 72. By photolithographic processes, openings surrounding the P + semiconductor layers 71 and the link portions of the N + emitter regions 65 are formed in the resist 73, at areas except for portions of the N + emitter regions 65 which extend along the inner walls 67 and except for portions of the P + semiconductor layers 71 which are in the vicinity of the N + emitter regions 65, to thereby obtain a resist pattern. Using the resist pattern as a mask, the BPSG 72 and the thermal oxidation film 68 are etched, whereby the interlayer insulation film 72 is formed on the surface of the polysilicon 69 which is buried in the grooves which are defined by the inner walls 67 (See Fig. 24). The resist pattern is then removed. Following this, to short-circuit the P + semiconductor layer 71 and the N + emitter regions 65 which are exposed by etching, Al-Si is stacked which serves as a conductive layer, on a surface of the element in which the P + semiconductor layer 71, the N + emitter regions 65 and the interlayer insulation film 72 are disposed. This creates a gate line and a gate pad at the same time which are connected to the polysilicon 69 which is buried in the grooves which are formed by the emitter electrode 73 and the inner walls 67 (See Fig. 25). Further, AlMoNiAu alloy which serves as a conductive layer is stacked on the surface of the P + silicon substrate 60, thereby forming a collector electrode 75. Through such manufacturing processes, the U-type IGBT according to the present embodiment is manufactured at an inexpensive cost. In addition, although the description above has described that the P + semiconductor layer 71 is formed in the present embodiment in a similar manner to that in the first preferred embodiment, the present embodiment does not always require to diffuse the P + semiconductor layers 45 shallower than the thickness of the N + emitter layers 44, considering side diffusion, as described earlier. Hence, during the manufacturing processes in the present embodiment, P-type impurities may be implanted through the thermal oxidation film 68 at a higher impurity concentration than that of the N + emitter regions 65 and then thermally diffused deeper than the bottom of the N + emitter regions 65 to obtain the P + semiconductor layer 71 whose bottom surface contacts the P base layers 63. Although the foregoing has described the present invention in relation to a U-type IGBT of an N - channel type, the present invention is applicable to a U-type IGBT of a P-channel type.

Claims: An insulated gate semiconductor device based on a semiconductor substrate (41, 42, 43, 44, 45) defining an upper major surface and a lower major surface, said insulated gate semiconductor device comprising: a first semiconductor layer (41) of a first conductivity type, said first semiconductor layer (41) including a lower surface corresponding to said lower major surface of said semiconductor substrate and an upper surface; a second semiconductor layer (42) of a second conductivity type which is disposed on said upper surface of said first semiconductor layer (41), said second semiconductor layer having a low impurity concentration; a third semiconductor layer (43) of the first conductivity type which is disposed on an upper surface of said second semiconductor layer (42); a plurality of fourth semiconductor layers (44) of the second conductivity type which are disposed parallel to each other in the shape of columns on a portion of an upper surface of said third semiconductor layer (43); a plurality of groove-shaped inner walls (47) defining openings (56) respectively which open in respective upper surfaces of said fourth semiconductor layers (44) so as to extend in a direction along said columns of said fourth semiconductor layers (44), said groove-shaped inner walls (47) extending downward from said surfaces of said fourth semiconductor layers (44) to said second semiconductor layer (42); a fifth semiconductor layer (45) of the first conductivity type which is disposed along said fourth semiconductor layers (44) between adjacent two of said groove-shaped inner walls (47), a junction between said fifth (45) and said fourth (44) semiconductor layers being exposed to said upper major surface; an insulation film (48) covering said groove-shaped inner walls (47); a control electrode (49) which is disposed in the interior of said openings (56) on inner surfaces of said groove-shaped inner walls (47) with said insulation film (48) interposed therebetween; an interlayer insulation film (50) which is disposed on an upper surface of said control electrode (49); a first major electrode (51) which is disposed on said upper surfaces of said fourth (44) and said fifth (45) semiconductor layers and on said interlayer insulation film (50); and a second major electrode (52) which is disposed on said lower second major surface of said first semiconductor substrate layer; wherein said fifth semiconductor layer has (45) a higher impurity concentration than said fourth semiconductor layers (44) and is disposed on said surfaces of said third (43) and said fourth (44) semiconductor layers to extend across said third (43) and said fourth (44) semiconductor layers; said insulation film (48) further covers a portion of said upper surfaces of said fourth semiconductor layers (44) which are continuous to, adjacent to, and lying along said groove-shaped inner walls (47); said control electrode (49) has an upper recessed surface which is recessed from an upper surface of a portion of said insulation film (48) covering a portion of said upper surfaces of said fourth semiconductor layers (44); in said surface of said third semiconductor layer (43), said fourth semiconductor layers (44) further include a plurality of link portions (55) linking those adjacent portions of said fourth semiconductor layers (44) which are disposed in the shape of columns, in a regularly scattered configuration, so that a surface configuration of said fourth semiconductor layers (44) is a ladder-like configuration in areas which are sandwiched between adjacent two of said groove-shaped inner walls (47); and exposed upper surfaces of said fifth semiconductor layer (45) are disposed in a regularly scattered configuration along adjacent two of said columns of said fourth semiconductor layers (44) so as to be surrounded by said ladder-like configuration formed by said adjacent portions of said fourth semiconductor layers (44) in the shape of columns and said link portions (55) linking the same. The insulated gate semiconductor device of claim 1, wherein said insulation film (48) further covers a portion of a surface of said fifth semiconductor layer (45) which is in the vicinity of said columns of said fourth semiconductor layers (44). The insulated gate semiconductor device of any of the preceding claims, wherein a bottom surface of said fifth semiconductor layer (45) is located at a position shallower than a bottom surface of said fourth semiconductor layers (44). The insulated gate semiconductor device of any of the preceding claims, wherein the impurity concentration of said fifth semiconductor layer (45) is about twice the impurity concentration of said fourth semiconductor layer (44). The insulated gate semiconductor device of any of the preceding claims, wherein said upper surface of said conductive material (49) is positioned at a position shallower than the bottom of the fourth semiconductor layers (44). The insulated gate semiconductor device of any of the preceding claims, wherein said second semiconductor layer comprises an upper region (42) of an impurity concentration lower than that of a lower region (46) thereof. A method of manufacturing an insulated gate semiconductor device according to one of the preceding claims, comprising: a first step of preparing a semiconductor substrate (41, 42; 60, 62) which comprises a first semiconductor layer (41; 60) of a first conductivity type and a second semiconductor layer (42; 62) of a second conductivity type disposed on an upper surface of said first semiconductor layer (41; 60), wherein a lower surface of said first semiconductor layer (60) defines a lower major surface of said semiconductor substrate, and an upper surface of said second semiconductor layer (62) defines an upper major surface of said semiconductor substrate; a second step of implanting impurities of the first conductivity type into said upper major surface of said semiconductor substrate to thereby form a third semiconductor layer (43; 63) of the first conductivity type; a third step of stacking a first resist (64) onto said upper major surface, selectively removing said first resist (64) to leave a portion of said first resist (64) as a plurality of regions which are arranged in the shape of columns parallel to each other and a portion of said first resist (64) as a plurality of regions which are regularly scattered between adjacent two of said parallel column-shaped regions so as to link adjacent two of said column-shaped regions in a ladder-like configuration so that a first resist pattern is formed, selectively implanting impurities of the second conductivity type using said first resist pattern as a mask, and diffusing said impurities of the second conductivity type in an upper surface of said third semiconductor layer (63) to thereby form fourth semiconductor layers (44; 65) of the second conductivity type having a higher impurity concentration than said upper region of said second semiconductor layer (62); a fourth step of forming a shielding film (66) on said upper major surface, forming an opening in said shielding film (66) on a portion of an upper surface of said fourth (65) semiconductor layers so that said opening extends along an upper surface of said columns of said fourth semiconductor layers (65), selectively removing a semiconductor down to said second semiconductor layer (62) while using said shielding film (66) as a mask which includes said opening to thereby form groove-shaped inner walls (67) which define grooves, and thereafter removing said shielding film (66); a fifth step of forming an insulation film (68) on surfaces of said groove-shaped inner walls (67) and on said upper major surface; a sixth step of stacking a conductive material (69) on said insulation film (68) so that said grooves are filled up; a seventh step of uniformly removing said conductive material (69) while leaving said insulation film (68) until an upper surface of said conductive material (69) which is buried in said grooves is recessed from a surface of a portion of said insulation film (68) which is formed on said upper major surface; an eighth step of stacking a second resist (70) on a portion of said insulation film (69), which is exposed on said upper major surface after said seventh step, and said surface of said conductive material (69), forming an opening therein at such a position as to surround an area which corresponds to said first resist (64) which is left at said third step in the shape of said ladder-like configuration of column-shaped regions and scattered portions and to surround portions of surfaces of said fourth semiconductor layers (65) which are adjacent to said area of said opening in said second resist (70), and to surround portions of surfaces of said fourth semiconductor layers (65) which are adjacent to said area, selectively implanting impurities of the first conductivity type at a higher impurity concentration than that of said fourth semiconductor layers (65) through said insulation film (68) while using said second resist (70) as a mask which includes said opening, and diffusing said impurities of the first conductivity type to thereby selectively form a fifth semiconductor layer (71) of the first conductivity type connecting said third semiconductor layer (63); a ninth step of stacking an insulation material (72) on said portion of said insulation film (68), which is exposed after said seventh step, and on said upper surface of said conductive material (69); a tenth step of stacking a third resist (73) on an upper surface of said insulation material (72), forming an opening therein which surrounds said fifth semiconductor layer (71) and portions of said fourth semiconductor layers (65), except for said portions of said upper surfaces of said fourth semiconductor layers (65) which are adjacent to and along said inner walls (67), selectively removing said insulation material (72) and said insulation film (68) while using said third resist (73) as a mask which includes said opening to thereby expose said fifth semiconductor layer (71) and said fourth semiconductor layers (65); an eleventh step of stacking a conductive layer (74) on said fourth (65) and fifth (71) semiconductor layers which are exposed after said tenth step and on said surface of said insulation material (72); and a twelfth step of stacking a conductive layer (75) on said lower major surface of said semiconductor substrate. The method of claim 7, wherein at said tenth step said opening is formed in said third resist (73) stacked on said insulation material (72) as to surround said fifth semiconductor layer (71) and portions of said fourth semiconductor layers (65), further except for a portion of an upper surface of said fifth semiconductor layer (71). The method of any of claims 7-8, wherein at said eight step said impurities of the first conductivity type are diffused shallower than the bottom of said fourth semiconductor layers (65) whose bottom surface contacts said third semiconductor layer (63). The method of any of claims 7-9, wherein at said eight step said impurities of the first conductivity type are diffused at an impurity concentration of about twice the impurity concentration of said fourth semiconductor layers (65). The method of any of claims 7-10, wherein at said seventh step the removing of said conductive material (69) is performed so that said upper surface of said conductive material (69) is positioned at a position shallower than the bottom of the fourth semiconductor layers (65). The method of any of claims 7-11, said second semiconductor layer comprising an upper region (62) of an impurity concentration lower than that of a lower region (61) thereof.

Inventors: TAKAHASHI HIDEKI, TAKAHASHI, HIDEKI, TAKAHASHI, HIDEKI, C/O MITSUBISHI DENKI K. K.
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1996
Main classification: H01L29
IPC codes: H01L21, H01L29