Viterbi detector with path-memory of reduced size

Abstract: A data reproducing apparatus for reproducing data subjected to convolution by partial response, by using maximum likelihood, includes a path memory including a plurality of memory arrays (S 0 ,S 1 ,S 2 ,S 3 ) which respectively correspond to plural states that the data can take and each of which has a predetermined number of regions each corresponding to a time point (T1,...,T5), a detecting device for periodically detecting, from the data, states before the plural states have been shifted, and control device for causing values respectively representing the detected states before shifting to be sequentially stored in said regions of said memory arrays every time detection is performed by said detection means, causing the values previously stored in said memory arrays to be replaced in accordance with the detected states before shifting, and when all values stored in said regions of said memory arrays corresponding to the same time point match, reproducing the data on the basis of the matching value.

Description: The present invention relates to a method and apparatus for reproducing data from a signal read out from a recording medium or transferred by a communication means and, more particularly, to a method and apparatus for reproducing data subjected to convolution based on partial response, by using maximum likelihood. In recent years, high-density information recording or information transfer at a high transfer rate has become popular for a data reproducing apparatus. For example, a signal processing method called PRML is known as a means for realizing such high-density recording or high transfer rate. The PRML signal processing method uses a combination of PR (Partial Response) and ML (Maximum Likelihood). Partial response is a technique of reproducing data by waveform equalization. A signal read out from a recording medium or transferred by a communication means is output while its waveform is distorted by intercode interference. To properly reproduce data from this signal, the noise component may be removed by filtering. However, the frequency band of the noise component overlaps that of the data signal component over a wide range in fact, and it is therefore difficult to remove the noise component. In partial response, data convolution is performed on the basis of predetermined rules to narrow the band of the data signal, thereby performing data reproduction with a high S/N ratio. The use of partial response allows high-density signal recording in a recording medium and also can cope with an increase in influence of intercode interference on the signal read out from the medium, so that the capacity of information recordable in the recording medium can be increased. Several schemes are known as partial response, and the above scheme is normally expressed as "PR(1,1)". "PR" is the initials of "partial response". The first "1" in the parentheses represents the original signal, and the second "1" represents that a signal delayed by one bit is superposed on the original signal. Assume a binary signal "010100101100", as shown in Fig. 14A. A signal shown in Fig. 14B, which is delayed by one bit, is superposed on the binary signal, thereby obtaining a signal shown in Fig. 14C. The signal shown in Fig. 14C is called a signal obtained upon waveform equalization by PR(1,1). This signal is a ternary signal with signal amplitude levels "1", "0", and "-1". The signal shown in Fig. 14C has a frequency band narrower than that of the original signal. Similarly, PR(1,2,1) represents that a signal (Fig. 15B) obtained by delaying a binary signal as shown in Fig. 15A by one bit and doubling its amplitude and a signal (Fig. 15C) obtained by delaying the signal (Fig. 15A) by two bits and imparting the same amplitude as that of the original signal (Fig. 15A) are superposed on the original binary signal. Consequently, a signal shown in Fig. 15D is obtained. The signal shown in Fig. 15D is called a signal obtained upon waveform equalization by PR(1,2,1). This signal is a quinary signal with signal amplitude levels "2", "1", "0", "-1", and "-2". The signal shown in Fig. 15D has a frequency band narrower than that of the original signal. It can be regarded in PR(1,2,1) that signals obtained upon waveform equalization by PR(1,1) are shifted from each other by one bit, and convolution is further performed. Maximum likelihood is a technique used when data is to be detected in accordance with information convolution by the above-described partial response. Data with the highest probability is selected to determine the data. For a signal obtained upon waveform equalization by partial response, a value at a certain time point contains previous information, e.g., information two bits before in PR (1,2,1). For this reason, the original data cannot be determined on the basis of only that value. When maximum likelihood is performed, the data can be properly reproduced from the signal obtained by partial response. As a specific technique of realizing such maximum likelihood, a matrix method is proposed in e.g. "A Reliable Signal Detection method for the Combination of PRMOL Method and Ternary Recording Code", S. Tazaki, et al., Proc. '94 IEEE ISIT, p. 214 (June 1994). The present inventors have filed Japanese Patent Application No. 6-181363 relating to an information recording/reproducing apparatus which employs partial response PR(1,1) and reproduces binary digital information by maximum likelihood. In the former technique, however, a large usable memory must be ensured, and the calculation time is long In the latter apparatus, detection data is input to a shift register array, and signal processing performed. Data "1" and "0" stored in the shift register correspond to the number of states, so this apparatus can hardly cope with four or more states. Path memories operated in the register exchange mode are known for example from document US 5 095 392 (Shimazaki et al.), which concerns Viterbi detection for partial response channel in presence of intersymbol interference and from the article from INTEGRATION, THE VLSI JOURNAL, vol. 12, no. 1,1 November 1991, pages 79-91, Paaske et al., 'An area-efficient path memory structure for VLSI implementation of high speed viterbi decoders'. This article describes the operation of shifting the content of the rows of the path memory according to the decision bits from an add-compare-select (ACS) unit. According to the present invention there is disclosed a method of reproducing information using detection means for partial response detection of a reproduction signal by detecting a level of the reproduction signal, and a memory array for storing most likelihood path information, thereby reproducing the information according to a most likelihood path, wherein said memory array has an N x M arrangement comprising N memory rows corresponding to respective states and containing state values representative of state transitions and M memory columns storing the most likelihood path information, the method comprising the steps of: sampling the reproduction signal at a data discrimination point t to detect a reproduction signal level and, based on the reproduction signal level, determining the most likely transition to each state; storing into each memory row corresponding to a respective state, the state value S k t (k=0, 1, ...N-1) representative of the preceding state connected by the most likelihood branch as determined from the detection reproduction signal level at the data discrimination point t; and rewriting for each of said most likely transitions the past state values stored in a respective first memory row into a respective second memory row so that the first memory rows correspond to the states from which the most likely transitions originate and the second memory rows correspond to the states to which the most likely transitions end, thereby storing a respective surviving path into each memory row and providing the reproduced data at the Mth column of the memory array. Embodiments of the present invention will now be described with reference to the accompanying drawings, in which: Fig. 1 is a block diagram showing a data reproducing apparatus according to an embodiment of the present invention; Fig. 2 is a chart showing the waveform of a reproduction signal obtained upon waveform equalization by PR(1,2,1); Fig. 3 is a state diagram showing state transition observed when waveform equalization by PR(1,2,1) is performed; Fig. 4 is a graph showing a distribution of the reproduction signal at data identification points, which is observed when waveform equalization by PR(1,2,1) is performed; Fig. 5 is a circuit diagram showing an arrangement of the binarizing circuit of the apparatus shown in Fig. 1; Fig. 6 is a trellis diagram showing an example of state transition of the reproduction signal; Figs. 7A to 7E are views for explaining the operation principle of reproduction/decoding when the states change as shown in Fig. 6 in the apparatus shown in Fig. 1; Fig. 8 is a circuit diagram showing an arrangement of the maximum likelihood circuit of the apparatus shown in Fig. 1; Fig. 9 is a circuit diagram showing an arrangement of a 2-bit memory used in the maximum likelihood circuit shown in Fig. 8; Fig. 10 is a circuit diagram showing an arrangement of a select circuit used in the maximum likelihood circuit shown in Fig. 1; Fig. 11 is a circuit diagram showing another arrangement of the binarizing circuit of the apparatus shown in Fig. 1; Fig. 12 is a circuit diagram showing another arrangement of the maximum likelihood circuit of the apparatus shown in Fig. 1; Fig. 13 is a circuit diagram showing an arrangement of a select circuit used in the maximum likelihood circuit shown in Fig. 12; Figs. 14A to 14C are views for explaining waveform equalization by PR(1,1); and Figs. 15A to 15D are views for explaining waveform equalization by PR(1,2,1). DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the accompanying drawings. Fig. 1 is a block diagram showing a data reproducing apparatus according to an embodiment of the present invention. Referring to Fig. 1, a reproduction signal 1 is read out from a recording medium (not shown) such as an optical disk, which is a reproduction signal obtained upon waveform equalization by partial response. In this embodiment, partial response PR(1,2,1) is employed. A binarizing circuit 2 detects the level of the reproduction signal 1 and outputs state transitions. A maximum likelihood circuit 3 receives an output signal from, the binarizing circuit 2, performs maximum likelihood processing and outputs reproduction data 4. The maximum likelihood circuit 3 is constituted by a memory 5 and a control circuit 6. The arrangements and operations of the binarizing circuit 2 and the maximum likelihood circuit 3 will be described later in detail. Fig. 2 is a chart showing the waveform of the reproduction signal 1 shown in Fig. 1, i.e., a reproduction signal read out from the recording medium and subjected to waveform equalization by partial response. Referring to Fig. 2, the reproduction signal 1 is divided into five values at a data identification point (time: 0.0) by performing information convolution based on waveform equalization by partial response. More specifically, the reproduction signal is divided into five values "-2", "-1", "0", "1", and "2" from the lower amplitude level side. V th1 to V th4 represent comparison levels for detecting the state transition of the reproduction signal by the binarizing circuit 2 as will be described later. In this embodiment, partial response PR(1,2,1) is employed, as described above. When information convolution is performed by imparting intercode interference by partial response, the reproduction signal as shown in Fig. 2 is obtained. A description of partial response PR(1,2,1) has been made above with reference to Figs. 15A to 15D. Fig. 3 is a state transition diagram showing state transition of the reproduction signal shown in Fig. 2 In Fig. 3, S 0 to S 3 represent the states of the reproduction signal. For example, the state S 0 changes from the state S 0 or the state S 2 , as indicated by arrows. A change from the state S 0 to the state S 0 is represented by -2/000 in which "-2" represents the detection level at the data identification point shown in Fig. 2, and "000" represents the reproduction data candidate at that time. In a change from the state S 2 to the state S 0 as well, "-1" of -1/100 represents the detection level at the data identification point, and "100" represents the reproduction data candidate. The state S 1 changes from the state S 0 or the state S 2 , the state S 2 changes from the state S 1 or the state S 3 , and the state S 3 changes from the state S 1 or the state S 3 , as indicated by arrows. In each case, an arrow represents the direction of state transition together with the detection levels at the data identification point and the reproduction data candidate at that point. The number of states is determined depending on the manner of convolution by partial response. For example, in PR(1,2,1), convolution of information two bits before is made, so that the number of states is 2 x 2 = 4. When convolution of information n bits before is made, the number of states is 2 n . Fig. 4 is a graph showing the reproduction signal amplitude distribution at the data identification point shown in Fig. 2. As is apparent from Fig. 4, the reproduction signal amplitude distribution is a Gaussian distribution having peaks at amplitude levels "-2", "-1", "0", "1", and "2". The width of the Gaussian distribution can be considered to be determined by the S/N ratio of the reproduction signal. As for state transition from a certain time point to the next time point, which has been described above with reference to Fig. 3, transition with a high probability is selected in accordance with the Gaussian distribution shown in Fig. 4. In maximum likelihood, a reproduction data string with the highest probability is selected by selecting state transition, thereby reproducing data. Fig. 5 is a circuit diagram showing an arrangement of the binarizing circuit 2 in detail. The binarizing circuit 2 comprises four comparators 14 to 17. Each comparator compares the reproduction signal 1 with a predetermined comparison level, and outputs the comparison result. The reproduction signal 1 is a reproduction signal obtained upon waveform equalization, as described above. The comparison level V th1 is input to the comparator 14, the comparison level V th2 is input to the comparator 15, the comparison level V th3 is input to the comparator 16, and the comparison level V th4 is input to the comparator 17. Each comparator compares the reproduction signal with the comparison level and outputs the comparison result to the maximum likelihood circuit 3. The comparison levels V th1 to V th4 correspond to those shown in Figs. 2 and 4. The comparator 14 compares the reproduction signal with the comparison level V th1 in Fig. 2 at the data identification point and outputs the comparison result. In this case, when the amplitude level of the reproduction signal at the data identification point is higher than the comparison level V th1 , there is a high probability that the amplitude level of the reproduction signal at the data identification point is "-1" rather than "-2", as is apparent from Fig. 4. To the contrary, when the amplitude level of the reproduction signal at the data identification point is lower than the comparison level V th1 , there is a high probability that the amplitude level of the reproduction signal at the data identification point is "-2" rather than "-1". This difference corresponds to determination of state transition described above with reference to the state diagram of Fig. 3, i.e., whether the state before the state S 0 is the state S 0 or the state S 2 . More specifically, the comparator 14 compares the reproduction signal with the comparison level V th1 as shown in Fig. 2 to detect the level of the reproduction signal at the data identification point and outputs data representing the state before the state S 0 , i.e., the state S 0 or the state S 2 . In this manner, the comparator 14 detects the level of the reproduction signal, detects the state transition on the basis of the level of the reproduction signal, and outputs the detection result from its output terminal and ground line to the maximum likelihood circuit 3 as an output 10, i.e., 2-bit data "00" or "10". The comparator 15 compares the reproduction signal with the comparison level V th2 in Fig. 2 and outputs the comparison result. In this case as well, as in the above description, when the amplitude level of the reproduction signal at the data identification point is higher than the comparison level V th2 , there is a high probability that the amplitude level of the reproduction signal at the data identification point is "0" rather than "-1", as is apparent from Fig. 4. To the contrary, when the amplitude level of the reproduction signal at the data identification point is lower than the comparison level V th2 , there is a high probability that the level of the reproduction signal at the data identification point is "-1" rather than "O". This difference also corresponds to determination in the state diagram of Fig. 3, i.e., whether the state before the state S 1 is the state S 0 or the state S 2 . The comparator 15 compares the reproduction signal with the comparison level V th2 , detects the level of the reproduction signal at the data identification point, and outputs data representing the state before the state S 1 , i.e., the state S 0 or the state S 2 . This data is output from the output terminal and ground line of the comparator 15 to the maximum likelihood circuit 3 as an output 11, i.e., 2-bit data "00" or "10". The comparator 16 compares the reproduction signal with the comparison level V th3 in Fig. 2 and outputs the comparison result to the maximum likelihood circuit 3. In this case as well, when the amplitude level of the reproduction signal at the data identification point is higher than the comparison level V th3 , there is a high probability that the level of the reproduction signal at the data identification point is "1" rather than "0", as is apparent from Fig. 4. To the contrary, when the amplitude level of the reproduction signal at the data identification point is lower than the comparison level V th3 , there is a high probability that the level of the reproduction signal at the data identification point is "0" rather than "1". This difference also corresponds to determination in the state diagram of Fig. 3, i.e., whether the state before the state S2 is state S 1 or the state S 3 . The comparator 16 compares the reproduction signal with the comparison level V th3 , detects the level of the reproduction signal at the data identification point, and outputs data representing the state before the state S 2 , i.e., the state S 1 or the state S 3 . This data is output from the output terminal and power supply line of the comparator 16 to the maximum likelihood circuit 3 as an output 12, i.e., 2-bit data "01" or "11". Finally, the comparator 17 compares the reproduction signal with the comparison level V th4 in Fig. 2. In this case as well, when the amplitude level of the reproduction signal at the data identification point is higher than the comparison level V th4 , there is a high probability that the level of the reproduction signal at the data identification point is "2" rather than "1", as is apparent from Fig. 4. To the contrary, when the amplitude level of the reproduction signal at the data identification point is lower than the comparison level V th4 , there is a high probability that the level of the reproduction signal at the data identification point is "1" rather than "2". This difference also corresponds to determination in the state diagram of Fig. 3, i.e., whether the state before the state S 3 is the state S 1 or the state S 3 . The comparator 17 compares the reproduction signal with the comparison level V th4 , detects the level of the reproduction signal at the data identification point, and outputs data representing the state before the state S 3 , i.e., the state S 1 or the state S 3 . This data is output from the output terminal and power supply line of the comparator 17 to the maximum likelihood circuit 3 as an output 13, i.e., 2-bit data "01" or "11". As described above, the binarizing circuit 2 detects the level of the reproduction signal at the data identification point by using the four comparators and outputs the detection result to the maximum likelihood circuit 3 as the state transition of the reproduction signal. The above operation will be described in more detail. One of the states S 0 to S 3 , from which each of the four states S 0 to S 3 has changed at a time point T 1 , is detected in the following manner. First, the state S 0 changes from the state S 0 or the state S 2 , as can be seen from Fig. 3. When the signal level at the time point T 1 is "-1", the state S 0 has changed from the state S 2 , and when the signal level is "-2", the state S 0 has changed from the state S 0 , as is apparent from Fig. 3. When the output from the comparator 14 shown in Fig. 5 is "10", there is a high probability that the signal level at the time point T 1 is "-1", and it is therefore determined that the state S 0 has changed from the state S 2 at the time point T 1 , as shown in Fig. 6. Similarly, it is determined that the state S 1 has changed from the state S 0 , the state S 2 has changed from the state S 3 , and the state S 3 has changed from the state S 1 . In this manner, state transition is periodically detected on the basis of the outputs from the binarizing circuit 2. The operation principle of the maximum likelihood circuit 3 will be described below with reference to Figs. 6 and 7A to 7E. In this embodiment, a maximum likelihood operation performed when the states have changed as shown in the trellis diagram of Fig. 6 will be described. Fig. 6 shows state transition detected by the binarizing circuit 2, as described above. Figs. 7A to 7E are views showing the contents of data stored in the memory 5 in correspondence with the state transition. Time points T 1 to T 5 in Figs. 7A to 7E correspond to time points T 1 to T 5 in Fig. 6. As described above in Fig. 1, the maximum likelihood circuit 3 is constituted by the memory 5 and the control circuit 6 for controlling data storage in the memory 5. The memory 5 has four 2-bit memories in correspondence with the four states shown in Fig. 6. The four 2-bit memories corresponding to 16 clocks are time-serially ensured. The path memory length of the memory 5 may be three or more times the number of states. In this case, a path memory length corresponding to 16 clocks is provided. The operation principle will be described in detail. At the time point T 1 in Fig. 6, the state S 0 has changed from the state S 2 , as indicated by an arrow. In this case, as shown in Fig. 7A, data "2" representing that the state S 0 has changed from the state S 2 is stored in a memory corresponding to the state S 0 by the control circuit 6. Similarly, at the time point T 1 , the state S 1 has changed from the state S 0 , the state S 2 has changed from the state S 3 , and the state S 3 has changed from the state S 1 . Therefore, data "0", "3", and "1" are stored in memories corresponding to the state S 1 , the state S 2 , and the state S 3 , respectively, by the control circuit 6, as shown in Fig. 7A. At the time point T 2 , the state S 0 has changed from the state S 0 , as shown in Fig. 6. Therefore, data "0" representing that the state S 0 has changed from the state S 0 is stored in the memory corresponding to the state S 0 , as shown in Fig. 7B (second column). Similarly, the state S 1 has changed from the state S 2 , the state S 2 has changed from the state S 3 , and the state S 3 has changed from the state S 1 . Therefore, data "2", "3", and "1" are stored in the memories corresponding to the states S 1 , S 2 , and S 3 , respectively, as shown in Fig. 7B. Similarly, the control circuit 6 performs processing of shifting the data stored in the memory 5 at the time point T 1 in accordance with the data stored at the time point T 2 . More specifically, since the state S 0 has changed from the state S 0 at the time point T 2 , the data for the state S 0 at the time point T 1 is transferred as data corresponding to the state S 0 . That is, since the data "2" is stored in correspondence with the state S 0 at the time point T 1 , the control circuit 6 stores the data "2" in the memory corresponding to the state S 0 , as shown in Fig. 7B (first column). At the time point T 2 , the state S 1 has changed from the state S 2 , the state S 2 has changed from the state S 3 , and the state S 3 has changed from the state S 1 . Therefore, the data "3" for the state S 2 at the time point T 1 is stored as data corresponding to the state S 1 , the data "1" for the state S 3 at the time point T 1 is stored as data corresponding to the state S 2 , and the data "0" for the state S 1 at the time point T 1 is stored as data corresponding to the state S 3 . Similar processing is performed at the time point T 3 . The state S 0 has changed from the state S 2 , so that the data "2" is stored in the memory corresponding to the state S 0 , as shown in Fig. 7C (third column). Similarly, the state S 1 has changed from the state S 2 , the state S 2 has changed from the state S 3 , and the state S 3 has changed from the state S 1 . Therefore, as shown in Fig. 7C (third column), the data "2", "3", and "1" are stored in the memories corresponding to the states S 1 , S 2 , and S 3 , respectively. At the same time, the data stored at the time points T 1 and T 2 are shifted in accordance with the data at the time point T 3 . More specifically, when the data at the time point T 2 are to be shifted in accordance with the data at the time point T 3 , the data "3" for the state S 2 at the time point T 2 is stored in the memory corresponding to the state S 0 , as shown in Fig. 7C (second column), because the state S 0 has changed from the state S 2 at the time point T 3 . Similarly, at the time point T 3 , the state S 1 has changed from the state S 2 , the state S 2 has changed from the state S 3 , and the state S 3 has changed from the state S 1 . Therefore, as shown in Fig. 7C (second column), the data "3" for the state S 2 at the time point T 2 is stored in the memory corresponding to the state S 1 , the data "1" for the state S 3 at the time point T 2 is stored in the memory corresponding to the state S 2 , and the data "2" for the state S 1 at the time point T 2 is stored in the memory corresponding to the state S 3 . The data are shifted in the memory 5 in the this manner. As a result, data of the second column in the memory is represented as "3", "3", "1", and "2", as shown in Fig. 7C. When the data at the time point T 1 are to be shifted in accordance with the data at the time point T 3 , the data "1" for the state S 2 at the time point T 1 is stored as data corresponding to the state S 0 , as shown in the first column of Fig. 7C, because the state S 0 has changed from the state S 2 at the time point T 3 . Similarly, at the time point T 3 , the state S 1 has changed from the state S 2 , the state S 2 has changed from the state S 3 , and the state S 3 has changed from the state S 1 . Therefore, as shown in the first column of Fig. 7C, the data "1" for the state S 2 at the time point T 1 is stored in the memory corresponding to the state S 1 , the data "0" for the state S 3 at the time point T 1 is stored in the memory corresponding to the state S 2 , and the data "3" for the state S 1 at the time point T 1 is stored in the memory corresponding to the state S 3 . As a result, data of the first column of the memory 5 is represented as "1", "1", "0", and "3", as shown in Fig. 7C. At the time point T 4 as well, the same processing as described above is performed. At the time point T 4 , the state S 0 has changed from the state S 2 , the state S 1 has changed from the state S 0 , the state S 2 has changed from the state S 1 , and the state S 3 has changed from the state S 1 . Therefore, as shown in Fig. 7D (fourth column), "2", "0", "1", and "1" are stored in the memories corresponding to the states S 0 , the state S 1 , the state S 2 , and the state S 3 , respectively. In addition, the data stored at the time points T 1 , T 2 , and T 3 are shifted in accordance with the data stored in the time point T 4 . This processing is performed on the basis of the same principle as described above. When the data at the time point T 3 are shifted in accordance with the data at the time point T 4 , "3" is stored in the memory corresponding to the state S 0 , "2" is stored in the memory corresponding to the state S 1 , "2" is stored in the memory corresponding to the state S 2 , and "2" is stored in the memory corresponding to the state S 3 , as shown in Fig. 7D (third column). The data stored at the time point T 2 are shifted in accordance with the data at the time point T 4 on the basis of the same principle as described above. As shown in Fig. 7D (second column), "1" is stored in the memory corresponding to the state S 0 , the"3" is stored in the memory corresponding to the state S 1 , "3" is stored in the memory corresponding to the state S 2 , and "3" is stored in the memory corresponding to the state S 3 . When the data at the time point T 1 are shifted in accordance with the data at the time point T 4 on the basis of the same principle, "0" is stored in the memory corresponding to the state S 0 , "1" is stored in the memory corresponding to the memory state S 1 , "1" is stored in the memory corresponding to the state S2, and "1" is stored in the memory corresponding to the state S 3 , as shown in Fig. 7D (first column). The same processing is performed at the time point T 5 as well. At the time point T 5 , the state S 0 has changed from the state S 2 , the state S 1 has changed from the state S 2 , the state S 2 has changed from the state S 1 , and the state S 3 has changed from the state S 3 . Therefore, as shown in Fig. 7E (fifth column), "2" is stored in the memory corresponding to the state S 0 , "2" is stored in the memory corresponding to the state S 1 , "1" is stored in the memory corresponding to the state S 2 , and "3" is stored in the memory corresponding to the state S 3 . In addition, the data stored at the time point T 4 are shifted in accordance with the data at the time point T 5 on the basis of the same principle as described above. As a result, "1" is stored in the memory corresponding to the state S 0 , "1" is stored in the memory corresponding to the memory state S 1 , "0" is stored in the memory corresponding to the state S 2 , and "1" is stored in the memory corresponding to the state S 3 , as shown in Fig. 7E (fourth column). The data at the time point T 3 are shifted in accordance with the data at the time point T 5 . As shown in the third column in Fig. 7E, "2" is stored in all the memories corresponding to the states S 0 to S 3 . When the data at the time point T 2 are shifted in accordance with the data at the time point T 5 , "3" is stored in all the memories corresponding to the states S 0 to S 3 , as shown in the second column in Fig. 7E. When the data at the time point T 1 are shifted in accordance with the data at the time point T 5 , "1" is stored in all the memories corresponding to the states S 0 to S 3 , as shown in the first column in Fig. 7E. In this manner, the control circuit 6 controls the data in the memory 5 in accordance with the state transition. As is apparent from Fig. 7E, at the time point T 5 , the contents of data stored in the memory before the time point T 3 match in the memories corresponding to all the states. More specifically, at the time point T 2 , "2" is stored in all the memories corresponding to the states S 0 to S 3 . At the time point T 1 , "3" is stored in all the memories corresponding to the states S 0 to S 3 . At a time point T 0 , "1" is stored in all the memories corresponding to the state S 0 to S 3 . This means that the state has changed from the state S 2 at the time point T 2 , from the state S 3 at the time point T 1 , and from the state S 1 at the time point T 0 . Consequently, as is apparent from the state diagram shown in Fig. 3, since the data for the state S 2 is "10", the data for the state S 3 is "11", and the data for the state S 1 is "01", the reproduction data can be determined as "0110". A detailed arrangement of the maximum likelihood circuit 3 will be described below. Fig. 8 is a circuit diagram showing an example of the maximum likelihood circuit 3. Referring to Fig. 8, the inputs 10 to 13 correspond to the outputs from the binarizing circuit 2 shown in Fig. 5. These outputs are input to the corresponding memory arrays of the memory 5 in the maximum likelihood circuit 3, respectively. More specifically, the output 10 is input to a memory array consisting of 2-bit memories 20 to 24p corresponding to the state S 0 , the output 11 is input to a memory array consisting of 2-bit memories 21 to 25p corresponding to the state S 1 , the output 12 is input to a memory array consisting of 2-bit memories 22 to 26p corresponding to the state S 2 , and the output 13 is input to a memory array consisting of 2-bit memories 23 to 27p corresponding to the state S 3 . As the path memory length of each memory array, a length corresponding to 16 clocks is ensured, as described above. In addition, select circuits 28a to 28o for shifting data are arranged between the memories of each memory array (to be described later in detail). As the 2-bit memory, two DFFs (data flip-flops) 31 and 32 are used, as shown in Fig. 9. A reproduction clock 33 is input from a PLL circuit (not shown) to the two DFFs 31 and 32, so that data is shifted by this reproduction clock. The data input to the 2-bit memories 20 to 23 are output as outputs 10a, 11a, 12a, and 13a in synchronism with the reproduction clock. These outputs are input to the next 2-bit memories 24a, 25a, 26a, and 27a. These 2-bit memories have the same arrangement as shown in Fig. 9. The 2-bit memories 24a, 25a, 26a, and 27a are respectively connected to 2-bit memories 24b, 25b, 26b, and 27b through the select circuit 28a. When data are to be shifted, as described above, the select circuit 28a shifts the data by switching connection of the memories. Fig. 10 is a circuit diagram showing an arrangement of the select circuit 28a. The select circuit 28a is constituted by four multiplexers 40 to 43 corresponding to the states S 0 to S 3 . The multiplexers 40 to 43 are connected to the input-side memories 24a, 25a, 26a, and 27a, respectively, so that the data in the memories are shifted in accordance with the switching operation of the multiplexers 40 to 43. In this case, the switching operation of the multiplexers 40 to 43 is controlled such that the data stored in the memories 24a, 25a, 26a, and 27a are shifted in accordance with the corresponding outputs 10a, 11a, 12a, and 13a, i.e., currently input data. Though not illustrated in Fig. 8, the control circuit 6 controls the switching operation of the multiplexers. At the time point T 1 in Fig. 6, the memory 5 stores data contents as shown in Fig. 7A. In fact, these data are positioned at the second memory of each memory array shown in Fig. 8. More specifically, at the time point T 1 , "2" is stored in the memory 24a, "0" is stored in the memory 25a, "3" is stored in the memory 26a, and "1" is stored in the memory 27a. In this state, the next data shown in the second column of Fig. 7B are input to the memory array, so that "0" is stored in the memory 20, "2" is stored in the memory 21, "3" is stored in the memory 22, and "1" is stored in the memory 23. At this time, the select circuit 28a shifts the data at the time point T 1 in accordance with the data input at that time under the control of the control circuit 6, as in the above description of the operation principle. More specifically, since the data input to the memory array corresponding to the state S 0 is "0", data corresponding to the state S 0 at the time point T 1 , i.e., "2" stored in the memory 24a is shifted to the next memory 24b corresponding to the state S 0 . The data is shifted by connecting the memories 24a and 24b through the multiplexer 40 in the select circuit 28a. The data input to the memory array corresponding to the state S 1 is "2". Similarly, data corresponding to the state S 2 , i.e., "3" stored in the memory 26a is shifted to the next memory 25b corresponding to the state S 1 . In this case, the memories 26a and 25b are connected through the multiplexer 41. The data input to the memory array corresponding to the state S 2 is "3", and the data corresponding to the state S 3 , i.e., "1" as the data stored in the memory 27a is shifted to the next memory 26b. At this time, the memories 27a and 26b are connected through the multiplexer 42. Finally, the data "1" is input to the memory array corresponding to the state S 3 . The data corresponding to the state S 1 , i.e., "0" stored in the memory 25a is shifted to the next memory 27b. At this time, the memories 25a and 27b are connected through the multiplexer 43. The select circuit 28a shifts the data in this manner. In the respective memory arrays, a select circuit is connected to the memories 24b, 25b, 26b, and 27b, 2-bit memories are connected to the select circuit, and another select circuit is connected the 2-bit memories. In this manner, memories and select circuits are alternately arranged, and 2-bit memories 24p, 25p, 26p, and 27p are arranged at the end of the memory arrays. The data shift operation in the memories by the select circuit 28a has been described above. At the subsequent memories of the memory arrays, the control circuit 6 controls each select circuit to shift the data in accordance with the corresponding data inputs, as in the description of the operation principle with reference to Figs. 6 and 7. In each memory array, data is sequentially shifted in synchronism with the reproduction clock. As in the above description of the operation principle, when data are output to the memory 24p, 25p, 26p, and 27p at the output stage, the data contents match for all the states. Therefore, when upper or lower bits are extracted from the 2-bit memories 24p, 25p, 26p, and 27p at the output stage, reproduction data can be obtained. As described above, in this embodiment, information can be reproduced using the memory arrays corresponding to the number of the states of the reproduction signal and the memory 5 having a predetermined path memory length. Maximum likelihood can be performed with a smaller memory capacity than that of the prior art. When the number of states is large, the number of memory arrays of the memory 5 is increased accordingly. With this arrangement, maximum likelihood can be similarly performed, so this arrangement can cope with a large number of states. Another embodiment of the present invention will be described below. As shown in the state diagram of Fig. 3, the number of possible state transitions from each state is two. Therefore, the number of bits necessary to transfer state transition information can be one instead of two. In this embodiment, data corresponding to each state is represented by one bit. Fig. 11 is a circuit diagram showing a binarizing circuit 2 used in this embodiment. In this binarizing circuit, each of comparators 14 to 17 outputs one signal, i.e., 1-bit data representing state transition to a maximum likelihood circuit 3. The operation of the binarizing circuit 2 is the same as in the first embodiment shown in Fig. 5. Fig. 12 is a circuit diagram showing the maximum likelihood circuit 3 used in this embodiment. In this case as well, 1-bit memories 50 to 52 are arranged in place of the 2-bit memories 20 to 23 of the first embodiment. Select circuits 68a to 68o are also different from those of the first embodiment. Fig. 13 shows the select circuit of this embodiment. In Fig. 13, since the number of state transitions is two, each of multiplexers 60 to 63 has two input terminals. The operation of the maximum likelihood circuit shown in Fig. 12 is the same as in the first embodiment. In this embodiment, 1-bit data is processed. Therefore, the memory capacity can be further decreased as compared to the first embodiment, and the circuit arrangement can be simplified.

Claims: A method of reproducing information using detection means (2) for partial response detection of a reproduction signal by detecting a level of the reproduction signal, and a memory array (3) for storing most likelihood path information, thereby reproducing the information according to a most likelihood path, wherein said memory array (3) has an N x M arrangement comprising N memory rows (24, 25, 26 and 27) corresponding to respective states (K=0, 1, ...N-1) and containing state values representative of state transitions and M memory columns (24a,...,27P) storing the most likelihood path information, the method comprising the steps of: sampling the reproduction signal at a data discrimination point t to detect a reproduction signal level and, based on the reproduction signal level, determining the most likely transition to each state; storing into each memory row corresponding to a respective state, the state value S k t (k=0, 1, ...N-1) representative of the preceding state connected by the most likelihood branch as determined from the detection reproduction signal level at the data discrimination point t; and rewriting for each of said most likely transitions the past state values stored in a respective first memory row into a respective second memory row so that the first memory rows correspond to the states from which the most likely transitions originate and the second memory rows correspond to the states to which the most likely transitions end, thereby storing a respective surviving path into each memory row and providing the reproduced data at the Mth column of the memory array. A method according to claim 1, wherein the number of columns of said memory array is at least three times the number (N) of states. A method as claimed in preceding claim, wherein the data is subjected to convolution based on PR(1,2,1). A method according to any preceding claim, wherein said detecting means detects the level of the reproduction signal by comparing the reproduction signal with a plurality of threshold values (V th1 , V th2 , V th3 , V th4 ). A method according to any preceding claim, comprising the step of determining when all of the N state values of said Mth column are the same and outputting reproduction data corresponding to the state value. An information reproducing apparatus provided with detection means (2) for partial response detection of a reproduction signal and for detecting a level of the reproduction signal, and a memory array (3) for storing in use most likelihood path information, for thereby reproducing the information according to a most likelihood path, wherein said memory array (3) has an N x M arrangement comprising N memory rows (24, 25, 26 and 27) corresponding to respective states (K=0, 1, ...N-1) for containing state values representative of state transitions and M memory columns (24a,...,27P) for storing the most likelihood path information, the apparatus comprising: sampling means for sampling the reproduction signal at a data discrimination point t to detect a reproduction signal level and, based on the reproduction signal level, determining the most likely transition to each state; storing means for storing into each memory row corresponding to a respective state the state value S k t (k=0, 1, ...N-1) representative of the preceding state connected by the most likelihood branch as determined from the reproduction signal level at the data discrimination point t; and control means (28a-28o) for rewriting for each of said most likely transitions the past state values stored in a respective first memory row into a respective second memory row so that the first memory rows correspond to the states from which the most likely transitions originate and the second memory rows correspond to the states to which the most likely transitions end, for thereby storing a respective surviving path into each memory row and providing the reproduced data at the Mth column of the memory array. An apparatus according to claim 6, wherein the number of columns of said memory array is at least three times the number (N) of states. An apparatus according to any of claims 6 and 7, wherein the data is subjected to convolution based on PR(1,2,1). An apparatus according to any of claims 6 to 8, wherein said detection means comprises a plurality of comparators (14, 15, 16, 17) for comparing the reproduction signal with a plurality of threshold values (V th1 , V th2 , V th3 , V th4 ) and outputting comparison results to said control means. An apparatus according to any of claims 6 to 9, wherein said memory array comprises a plurality of parallelly arranged memory sub-arrays each having a plurality of series-connected 2-bit memories (20-23, 24a-24p, 25a-25p, 26a-26p, 27a-27p), and said control means comprises select means (28a-28o), arranged between said 2-bit memories, for replacing values stored in said 2-bit memories. An apparatus according to claim 10, wherein said 2-bit memory comprises two data flip-flops (31,32) which are parallelly arranged. An apparatus according to any of claims 10 and 11, wherein said select means comprises a plurality of multiplexers (40-43, 60-63) for switching connection of said plurality of memory sub-arrays. Apparatus according to any of claims 6 to 12, further comprising means for detecting that all of the N state values of the Mth memory column are the same, and output means operable, when the all of the N state values in the Mth column are the same to output the reproduction data corresponding to the state value.

Inventors: HIRAMATSU MAKOTO, TAZAKI SABURO, HIRAMATSU, MAKOTO, TAZAKI, SABURO
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1996
Main classification: H03M13
IPC codes: H04L25, G11B20, H03M13