Ferroelectric memory and method of reading out data from the ferroelectric memory

Abstract: A method of reading data from a ferroelectric memory has a memory cell (29) which uses a ferroelectric capacitor (31) as a storage medium. The method includes the steps of (a) applying first and second electric fields having opposite directions to the ferroelectric capacitor (31), wherein polarization of the ferroelectric capacitor (31) is changed according to a variation of the first and second electric fields; and (b) reading out the data stored in the memory cell (29) by detecting a variation of the polarization of the ferroelectric capacitor (31).

Description: The present invention generally relates to a ferroelectric memory and a method of reading out data from the ferroelectric memory, and more particularly, to a ferroelectric memory having memory cells in which ferroelectric capacitors formed by ferroelectric substances such as Pb(Zr, Ti)O 3 are used as storage mediums. The present invention is also directed to a ferroelectric memory and a method of reading out data from the ferroelectric memory so as to carry out a stable reading-out operation by increasing a signal margin for reading out the data. A semiconductor memory using ferroelectric capacitors formed by ferroelectric substances such as Pb(Zr, Ti)O 3 is a non-volatile memory and has a feature of having substantially the same writing-and-reading speed as that of a DRAM. Therefore, it is assumed that a demand for a large number of ferroelectric memories will increase in the future. With respect to an operation method of the ferroelectric memory, several kinds of methods are known, and these operation methods are disclosed, for example, in U. S. Patent No.4,873,664 (Ramtron), and Japanese Patent Publication 7-13877 (Toshiba CO. LTD). In theses methods, by applying a voltage to the ferroelectric capacitor, the data is discriminated according to an inversion of a polarization of the ferroelectric capacitor. When a memory cell is constructed with one transistor and one capacitor, in order to determine whether or not the polarization is inverted, a reference circuit (dummy cell) generating an intermediate load (or voltage) needs to be constructed with the ferroelectric capacitor. However, characteristics of this reference circuit may be easily varied by process dispersion of a ferroelectric film and fatigue due to inversion (referred to as inversion fatigue, hereinafter) of the ferroelectric capacitor. Therefore, there is a problem in that the signal margin is reduced-, and a stable reading-out operation may not be conducted. In the following, a more detailed description will be given of the operation of the above-discussed prior-art ferroelectric memory. FIG. 1 shows a schematic diagram for illustrating a part of one embodiment of a prior-art ferroelectric memory. The ferroelectric memory shown in FIG. 1 includes memory cells 1, 2, which have ferroelectric capacitors 3, 4, and transistors 5, 6 forming transmission gates. The transistors 5, 6 are so-called cell transistors. In FIG. 1, symbols "WL0 and WL1" indicate word lines for selecting a memory cell, and the symbols "PL0 and PL1" indicate plate lines for driving a plate electrode of the ferroelectric capacitor of a selected memory cell. The ferroelectric memory shown in FIG. 1 further includes dummy cells 7, 8 which have ferroelectric capacitors 9, 10 having an overlapped area of opposite electrodes half that of the ferroelectric capacitors 3, 4, and cell transistors 11, 12. In this embodiment, into the ferroelectric capacitors 9, 10, a logic "1" is written. In FIG. 1, symbols "DWL0 and DWL1" indicate word lines for selecting the dummy cell, and the symbols "DPL0 and DPL1" indicate plate lines for driving a plate electrode of the ferroelectric capacitor of a selected dummy cell. Further, symbols "BL and /BL" indicate bit lines forming data lines (data transmission lines), and the ferroelectric memory further includes a sense amplifier which amplifies a voltage difference between the bit lines BL and /BL when data is read out, and detects data read out from the selected memory cell. FIG. 2 and FIG. 3 show illustrations for explaining a data-writing sequence in the memory cell of the ferroelectric memory. In these drawings, an example of the data-writing sequence in the memory cell 1 is shown. A horizontal axis indicates a voltage between the bit line BL and the plate line PL0, namely, a voltage V BL of the bit line BL to an earth ground minus a voltage V PL0 of the plate line PL0 to the earth ground. A vertical axis indicates a polarization P of the ferroelectric capacitor 3. For example, when a logic "1" is written into the memory cell 1, the voltage V PL0 of the plate line PL0 is set to 0 V, and the cell transistor 5 is set to be conductive. Under this condition, the voltage V BL of the bit line BL is changed from 0 V to VCC, and is subsequently changed to 0 V. In the above sequence, a state of the polarization P of the ferroelectric capacitor 3 changes, as shown in FIG. 2, from a point a to a point b, and then to a point c. At the point c, the polarization P of the ferroelectric capacitor 3 becomes a positive polarization Ps. As a result, a logic "1" is stored in the ferroelectric capacitor 3. A closed curved line of b to c to d to e to b indicates a hysteresis loop. On the other hand, when a logic "0" is written into the memory cell 1, the voltage V BL of the bit line BL is set to 0 V, and the cell transistor 5 is set conductive. Under this condition, the voltage V PL0 of the plate line PL0 is changed from 0 V to VCC, and is further changed to 0 V. In the above sequence, a voltage of a storage electrode 3A to that of a plate electrode 3B of the ferroelectric capacitor 3 changes from 0 V to - VCC, and is further changed to 0 V. A state of the polarization P of the ferroelectric capacitor 3 changes, as shown in FIG. 3, from a point a to a point d, and then to a point e. At the point e, the polarization P of the ferroelectric capacitor 3 becomes a negative polarization -Ps. As a result, a logic "0" is stored in the ferroelectric capacitor 3. FIG. 4 shows waveforms for explaining a data-reading sequence from the memory cell of the ferroelectric memory. In the drawing, an example of the data-reading sequence from the memory cell 1 is shown. A waveform A indicates a variation of the voltage of the word lines WL0, DWL0, a waveform B indicates a variation of the voltage of the plate lines PL0, DPL0, and a waveform C indicates a variation of the voltage of the bit line BL. FIG. 5 shows an illustration for explaining the data-reading sequence from the memory cell of the ferroelectric memory. When data is read out from the memory cell 1, the bit lines BL, /BL are set to 0 V, and the word lines WL0, DWL0 are increased to VCC + VTH (a threshold voltage of the cell transistor) so as to set the cell transistors 5, 11 conductive. Further, the plate lines PL0, DPL0 are increased to VCC. At this time, for example, when the logic "1" is previously written in the ferroelectric capacitor 3, the polarization P of the ferroelectric capacitor 3, as shown in FIG. 5, changes from a point c to a point K1. In this case, a charge δQ1, by which the voltage V BL of the bit line BL is the same as the voltage of the storage electrode 3A of the ferroelectric capacitor 3, is provided from the ferroelectric capacitor 3 to the bit line BL. As a result, the voltage V BL of the bit line BL increases from 0 V to V1 V as shown in FIG. 4. On the other hand, for example, when the logic "0" is previously written in the ferroelectric capacitor 3, the polarization P of the ferroelectric capacitor 3, as shown in FIG. 5, changes from a point e to a point K2. In this case, a charge δQ2, by which the voltage V BL of the bit line BL is the same as the voltage of the storage electrode 3A of the ferroelectric capacitor 3, is provided from the ferroelectric capacitor 3 to the bit line BL. As a result, the voltage V BL of the bit line BL increases from 0 V to V2 V shown in FIG. 4. Since the overlapped area of the opposite electrodes of the ferroelectric capacitor 9 in the dummy cell 7 is half that of the ferroelectric capacitor 3 in the memory cell 1, and the logic "1" is written in the ferroelectric capacitor 9 in an initial condition, the voltage V /BL of the bit line /BL becomes an intermediate level between V1 and V2. This intermediate voltage may be the reference voltage (operable as a function of the dummy cell). Therefore, when the logic "1" is previously written in the ferroelectric capacitor 3, since the voltage V BL (=V1) of the bit line BL is larger than the voltage V /BL of the bit line /BL, the sense amplifier 13 increases the voltage V BL of the bit line BL to the voltage VCC, and decreases the voltage V /BL of the bit line /BL to 0 V. On the contrary, when the logic "0" is previously written in the ferroelectric capacitor 3, since the voltage V BL (=V2) of the bit line BL is smaller than the voltage V /BL of the bit line /BL, the sense amplifier 13 decreases the voltage V BL of the bit line BL to 0 V, and increases the voltage V /BL of the bit line /BL to the voltage VCC. In this way, the dummy cell 7 is used for the reference voltage of all of the memory cells connected to the bit line. Therefore, in the above-discussed ferroelectric memory, the dummy cell 7 is driven every time when any memory cell connected to the bit line BL, for example, the memory cell 1, is selected. The dummy cell 8 is driven every time when any memory cell connected to the bit line /BL, for example, the memory cell 2, is selected. Therefore, fatigue due to inversion (referred to as inversion fatigue, hereinafter) of the ferroelectric capacitors 9, 10 of the dummy cells 7, 8 increases as compared to the ferroelectric capacitors of the normal memory cell such as ferroelectric capacitors 3, 4. In this way, characteristics of the memory cell changes, and, thus, a reading-out margin decreases. It is difficult to design the dummy cells taking into account the characteristics change due to the inversion fatigue. Therefore, there is a problem in that the prior-art ferroelectric memory shown in FIG. 1 may not stably operate for a long term. There is another ferroelectric memory, in which the overlapped area of the opposite electrodes of the ferroelectric capacitors 9, 10 is twice that of the memory cells 3, 4, and a logic "0" is written in the ferroelectric capacitors 9, 10. However, this ferroelectric memory also has the same problem as that of the ferroelectric memory shown in FIG. 1. Next, a description will be given of an operating method of the ferroelectric memory disclosed in the above-mentioned Japanese Patent Publication No.7-13877. This ferroelectric memory is also disclosed in "Proposal of an operation method of a non-volatile ferroelectric memory having a Vcc/2 common plate", proceedings of EIC Electronics Society, C-509, 1995, in Japanese. The proposed ferroelectric memory has a cell structure similar to a DRAM using the ferroelectric film for a capacitor. The ferroelectric memory is operative in a DRAM mode at a normal operation state, stores information by remanent polarization of the ferroelectric capacitor at a power-off state, and reads the information when the power source is supplied. Therefore, the ferroelectric memory is operable as a non-volatile memory. In the following, a detailed description will be given of the above-discussed ferroelectric memory. When the ferroelectric memory is operating in the DRAM mode, data is not stored by the remanent polarization of the capacitor, but is stored by a charge stored in linear capacitance. At this time a plate voltage level is set to a Vcc/2 voltage, and a voltage level of a storage node is set to Vcc or 0 V according to the data. In this case, when the ferroelectric memory operates in the DRAM mode, a refresh operation is required. Subsequently, when the power source is turned off, the data is held as the remanent polarization of the ferroelectric capacitor. Further, when the power source is supplied, the remanent polarization is changed to a storage charge. Therefore, after a reading operation is carried out in all memory cells in an FRAM mode, the memory is set to be the DRAM mode. In this case, the plate voltage level is set to a Vcc/2 voltage, and the bit line is precharged to be 0 V. Further, a word line is selected, and a voltage level of the selected word line is increased. When the bit line is connected to the capacitor, the voltage level of the bit line increases over 0 V. However, since a degree of the increase varies according to a direction of polarization inversion, the data may be discriminated by the variance. In this way, after the data in all memory cells is read out, the ferroelectric memory is set to be the DRAM mode. However, there is also a problem in the ferroelectric memory disclosed in Japanese Patent Publication No.7-13877. Different from the Ramtron method, when the data is read from the ferroelectric memory, the plate line is not driven, but the voltage level of the bit line is varied. In this case, in order to discriminate whether the polarization inversion occurs, the dummy cell for generating the reference voltage is required. Therefore, characteristics of the dummy cell influences on a reliability of the reading operation. Particularly, since a voltage applied to the capacitor is relatively small, i.e., Vcc/2, for compatibility with the DRAM mode, a signal voltage decreases, and, thus, there is a problem in that a reading error may easily occur. US 5262982 discloses a method of reading data from a ferroelectric memory having a memory cell, the memory cell including a transmission gate having a first charge input-and-output port connected to a data line and a second charge input-and-output port, and a ferroelectric capacitor having a first electrode connected to the second charge input-and-output port and a second electrode connected to a driving voltage line . The method comprises successively applying first and second electric fields having opposite directions to the ferroelectric capacitor. The electric fields which are applied are such as to leave the polarization of the ferroelectric capacitor substantially unchanged. Charge which is transferred while the first field is applied is stored in a first capacitor, and charge which is transferred while the second electric field is applied is stored in a second capacitor. The first and second capacitors are connected in parallel to an amplifier to obtain the data. The method disclosed in US 5262982 requires the provision of first and second capacitors together with associated switches and driving circuits in order to read the data. It is an object of the present invention to provide a ferroelectric memory and a method of reading data from the ferroelectric memory. The ferroelectric memory does not need a dummy cell which is used for detecting data read out from a memory cell in a prior art ferroelectric memory. Also, a stable operation of the ferroelectric memory can be carried out for a long term. According to a first aspect of the present invention there is provided a method of reading data from a ferroelectric memory having a memory cell, said memory cell including a transmission gate having a first charge input-and-output port connected to a data line and a second charge input-and-output port, and a ferroelectric capacitor having a first electrode connected to said second charge input-and-output port and a second electrode connected to a driving voltage line, said method comprising the steps of: controlling said transmission gate to be non-conductive; subsequently controlling said transmission gate to be conductive; and applying a driving voltage to said second electrode of the ferroelectric capacitor through the driving voltage line to successively apply first and second electric fields having opposite directions to the ferroelectric capacitor while said transmission gate is conductive, characterised in that: said data line is precharged to a precharge voltage that is substantially half of a power source voltage while said transmission gate is non-conductive; and the first electric field sets the second electrode to a voltage higher than the precharge voltage, and the second electric field sets the second electrode to a voltage lower than the precharge voltage, such that the polarization of the ferroelectric capacitor is changed from a first value prior to application of the first and second electric fields to a second value following application of the first and second electric fields, the first and second values being sufficiently different to allow data to be read from the memory cell by detecting a difference between the voltage of the data line and the precharge voltage. According to the above-mentioned method of reading the data in the ferroelectric memory, the data read out from the memory cell may be detected in the same way as that of, for example, a dynamic random access memory (DRAM) using a method of precharging the bit line to a voltage VCC (power-source voltage) /2. Therefore, the method according to the present invention does not need a dummy cell. According to a second aspect of the invention there is provided a ferroelectric memory comprising: a memory cell including a transmission gate having a first charge input-and-output port connected to a data line and a second charge input-and-output port, and a ferroelectric capacitor having a first electrode connected to said second charge input-and-output port and a second electrode connected to a driving voltage line; and driving voltage applying means for applying a driving voltage to said second electrode of the ferroelectric capacitor through said driving voltage line so as to apply successively first and second electric fields having opposite directions to said ferroelectric capacitor, characterised in that: precharging means are provided for precharging said data line to a voltage that is substantially half of a power source voltage; the first electric field sets said second electrode to a voltage higher than the precharge voltage, and the second electric field sets said second electrode to a voltage lower than the precharge voltage, such that the polarization of the ferroelectric capacitor is changed from a first value prior to application of the first and second electric fields to a second value following application of the first and second electric fields, the first and second values being sufficiently different to allow data to be read from the memory cell by detecting a difference between the voltage of the data line and the precharge voltage; and means are provided for reading data from the memory cell by detecting a difference between the voltage of the data line and the precharge voltage. According to the above-mentioned ferroelectric memory, the data read out from the memory cell may be detected in the same way as that of, for example, the DRAM using the method of precharging the bit line to the voltage VCC/2. Therefore, the ferroelectric memory according to the present invention does not need the dummy cell. Preferred features of the invention are recited in the dependent claims. Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings, in which: FIG. 1 shows a schematic diagram for illustrating a main part of a prior-art ferroelectric memory; FIG. 2 and FIG. 3 show illustrations for explaining a data-writing sequence in a memory cell of the ferroelectric memory; FIG. 4 shows waveforms for explaining a data-reading sequence from the memory cell of the ferroelectric memory; FIG. 5 shows an illustration for explaining the data-reading sequence from the memory cell of the ferroelectric memory; FIG. 6 shows a schematic diagram for illustrating a main part of one embodiment of a ferroelectric memory according to the present invention; FIG. 7 shows a schematic diagram for illustrating main parts of a memory cell array 20, a line of sense amplifiers 25, and a line of column selection gates 27 shown in FIG. 6; FIG. 8 shows a schematic diagram for illustrating main parts of a row decoder 21 and a line of word-and-plate drivers 24 shown in FIG. 6; FIG. 9 shows a schematic diagram of a first embodiment of a plate-electrode driving-voltage generation circuit 23 shown in FIG. 6; FIG. 10 shows waveforms for explaining an operation of the first embodiment of the plate-electrode driving-voltage generation circuit 23 shown in FIG. 9; FIG. 11 shows a schematic diagram of a second embodiment of the plate-electrode driving-voltage generation circuit 23 shown in FIG. 6; FIG. 12 shows waveforms for explaining an operation of the second embodiment of the plate-electrode driving-voltage generation circuit 23 shown in FIG. 11; FIG. 13 shows a schematic diagram of a third embodiment of the plate-electrode driving-voltage generation circuit 23 shown in FIG. 6; FIG. 14 shows waveforms for explaining an operation of the third embodiment of the plate-electrode driving-voltage generation circuit 23 shown in FIG. 13; FIG. 15 and FIG. 16 show illustrations for explaining a data-writing sequence in the memory cell of the embodiment of the ferroelectric memory according to the present invention; FIG. 17 shows waveforms for explaining a data-reading sequence from the memory cell of the embodiment of the ferroelectric memory according to the present invention; FIG. 18A shows a variation of polarization P of a ferroelectric capacitor 31 shown in FIG. 7; FIG. 18B shows a relationship between the variation of the polarization P of the ferroelectric capacitor 31 and a variation of a voltage of the bit line BL; FIG. 19A shows a variation of polarization P of the ferroelectric capacitor 31 shown in 7; FIG. 19B shows a relationship between the variation of the polarization P of the ferroelectric capacitor 31 and a variation of the voltage of the bit line BL; FIG. 20 shows waveforms for explaining a method of positively re-writing the data in an embodiment of the ferroelectric memory according to the present invention; FIG. 21 shows an illustration for explaining preferred values of voltages VH and VL; FIG. 22 shows an illustration for explaining a relationship of a voltage applied between a storage electrode and a plate electrode of the ferroelectric capacitor at a second time, namely, VL - VCC/2, and a variation of the polarization δP of the ferroelectric capacitor, namely, an amount of charge appearing at the electrodes; FIG. 23 shows an illustration for explaining a relationship of the voltage VL - VCC/2 and the variation of the polarization δP of the ferroelectric capacitor; FIG. 24 shows waveforms for explaining another data-reading sequence from the memory cell of an embodiment of the ferroelectric memory according to the present invention; FIG. 25A shows the variation of polarization P of the ferroelectric capacitor 31 shown in FIG. 7; FIG. 25B shows the relationship between the variation of the polarization P of the ferroelectric capacitor 31 and the variation of the voltage of the bit line BL; FIG. 26A shows the variation of polarization P of the ferroelectric capacitor 31 shown in FIG. 7; FIG. 26B shows the relationship between the variation of the polarization P of the ferroelectric capacitor 31 and the variation of the voltage of the bit line BL; FIG. 27 shows an illustration for explaining a preferred voltage applied to the plate electrode 31B of the ferroelectric capacitor 31 when the data is read out from the memory cell; FIG. 28 shows a simplified circuit configuration of the ferroelectric memory according to an embodiment of the present invention; FIG. 29 shows hysteresis characteristics of the ferroelectric capacitor, where information of the logic "1" and "0" is respectively stored in conditions represented by symbols "a" and "b" FIG. 30 shows a timing chart of the reading-out operation; FIG. 31A to FIG. 31C show illustrations for explaining polarization variation when the data is read out from the ferroelectric capacitor in the circuits shown in FIG. 28. FIG. 31A shows variation of the plate-line voltage V PL , FIG. 31B shows polarization variation when the logic "1" is read out from the ferroelectric capacitor, and FIG. 31C shows polarization variation when the logic "0" is read out from the ferroelectric capacitor; FIG. 32 shows an illustration for explaining dependence of voltage deviation dVBL in the bit line BL upon bit-line capacitance C BL for each voltage δVL in the operation described by referring to FIG. 31A to FIG. 31C; FIG. 33A and FIG. 33B show variation of the polarization of the ferroelectric capacitor for the bit-line capacitance C BL of 1 nF and 8 nF. FIG. 33A shows a case where the logic "1" is read out from the ferroelectric capacitor, and FIG. 33B shows a case where the logic "0" is read out from the ferroelectric capacitor; FIG. 34 shows an illustration for explaining dependence of the voltage deviation dVBL in the bit line BL upon the bit-line capacitance C BL in a case where a voltage δVH is 2.65 V; FIG. 35A to FIG. 35C show illustrations for explaining polarization variation of the ferroelectric capacitor under the condition shown in FIG. 34. FIG. 35A shows variation of the plate-line voltage V PL , FIG. 35B shows polarization variation when the logic "1" is read out from the ferroelectric capacitor, and FIG. 35C shows polarization variation when the logic "0" is read out from the ferroelectric capacitor; and FIG. 36A and FIG. 36B respectively show configuration examples of an internal level-down power-supply converter and an internal level-up power-supply converter. First, a description will be given of an embodiment of a ferroelectric memory according to the present invention. FIG. 6 shows a schematic diagram for illustrating a main part of one embodiment of the ferroelectric memory according to the present invention. The ferroelectric memory shown in FIG. 6 includes a memory-cell array 20 in which a plurality of memory cells are arranged and a row decoder 21 decoding a row-address signal to select a row. The memory further is provided with a word-line driving-voltage generation circuit 22 generating a word-line driving voltage WL which drives a word line, and a plate-electrode driving-voltage generation circuit 23 generating a plate-electrode driving voltage PL which drives a plate electrode of a ferroelectric capacitor. The plate electrode of the ferroelectric capacitor constructs the memory cell. Further, a line of word-and-plate drivers 24 in which word-and-plate drivers corresponding to the rows are arranged is provided in the memory. Each word-and-plate driver provides the word-line driving voltage WL and the plate-electrode driving voltage PL to the word line and the plate line corresponding to the row, respectively. Also, a line of sense amplifiers 25 in which sense amplifiers are arranged is provided, each sense amplifier detecting data read out from the selected memory cell. The ferroelectric memory further includes a column decoder 26 decoding a column-address signal to generate a column selection signal, and a line of column selection gates 27 in which a plurality of column selection gates are arranged. The column selection gate selects a column based on the column selection signal generated from the column decoder 26. FIG. 7 shows a schematic diagram for illustrating main parts of the memory cell array 20, the line of sense amplifiers 25, and the line of column selection gates 27. In FIG. 7, the memory cell array 20 includes memory cells 29, 30, which have ferroelectric capacitors 31, 32 constituting storage mediums and cell transistors 33, 34 formed by nMOS transistors constituting transmission gates. Symbols "WL0 and WL1" indicate word lines for selecting the memory cell, the symbols "PL0 and PL1" indicate plate lines for driving a plate electrode of the ferroelectric capacitor of a selected memory cell, and symbols "BL and /BL" indicate bit lines constituting data lines (data transmission lines). The memory cell array 20 further includes a precharge circuit 35 precharging the bit lines BL, /BL. The precharge circuit 35 has a precharge-voltage line 36 providing VCC(power source voltage)/2 as a precharge voltage VPR, a precharge-control-signal line 37 transmitting a precharge control signal PR, and nMOS transistors 38 to 40 which are controlled to be in a conductive state (referred to as "ON", hereinafter) or a non-conductive state (referred to as "OFF", hereinafter) based on the precharge control signal PR. The line of sense amplifiers 25 includes a sense amplifier 43. The sense amplifier 43 has a sense-amplifier driving-voltage line 41 providing a sense-amplifier driving voltage P, a sense-amplifier driving-voltage line 42 providing a sense-amplifier driving voltage N, pMOS transistors 44, 45, and nMOS transistors 46, 47. The line of column selection gates 27 includes a column selection gate 48. The column selection gate 48 has nMOS transistors 49, 50 controlled to be ON or OFF according to a column selection signal CL. Symbols "IO" and "/IO" indicate input and output buses used for a plurality of columns in common. FIG. 8 shows a schematic diagram for illustrating main parts of the row decoder 21 and the line of word-and-plate drivers 24. In FIG. 8, the row decoder 21 includes a dynamic-type NAND circuit 52 decoding column-address signals Xi, Xj, Xk to select a word line WLm and a plate line PLm. The NAND circuit 52 has a pMOS transistor 53 controlled to be ON or OFF by a reset signal PR, and nMOS transistors 54, 55, 56 of which ON and OFF states are controlled by the column-address signals Xi, Xj, Xk, respectively. In the NAND circuit 52, before decoding, the reset signal RP is set to a low level (referred to as "an L level"), a state of the pMOS transistor 53 is set to ON, and a node 57 is precharged to the power source voltage VCC. When decoding is carried out, the reset signal RP is set to a high level (referred to as "an H level"), and the state of the pMOS transistor 53 is set to OFF. When another word line except for the word line WLm is selected and the reset signal RP is set to the L level, one or all of the column-address signals Xi, Xj, Xk becomes the L level, and one or all of the nMOS transistors 54, 55, 56 are controlled to be OFF. As a result, a level of the node 57 is maintained at the power source voltage VCC. On the other hand, when the word line WLm is selected, all of the column-address signals Xi, Xj, Xk become the H level, and all of the nMOS transistors 54, 55, 56 are controlled to be ON. As a result, the level of the node 57 becomes 0 V. In FIG. 8, the line of word-and-plate drivers 24 includes a word-and-plate driver 58 driving the word line WLm and the plate line PLm. The word-and-plate driver 58 has an inverter 59 inverting an output of the NAND circuit 52, and nMOS transistors 60, 61 of which gate electrodes are provided with the power source voltage VCC. The word-and-plate driver 58 further includes an nMOS transistor 62 having a gate provided with an output of the inverter 59 through the nMOS transistor 60, and a drain provided with the word-line driving voltage WL. The word-and-plate driver 58 still further includes an nMOS transistor 63 having a gate provided with the output of the inverter 59 through the nMOS transistor 61, and a drain provided with the plate-electrode driving voltage PL. Also, nMOS transistors 64, 65 are provided. The nMOS transistors 64, 65 are controlled to be ON or OFF by the output of the NAND circuit 52. A source of the nMOS transistor 64 is grounded, and a source of the nMOS transistor 65 is provided with VCC/2. In this embodiment, the word line WLm is connected to a connection point of a source of the nMOS transistor 62 and a drain of the nMOS transistor 64, and the plate line PLm is connected to a connection point of a source of the nMOS transistor 63 and a drain of the nMOS transistor 65. In the line of word-and-plate drivers 24, when the output of the NAND circuit 52 is VCC, namely, when another word line except the word line WLm is selected, states of the nMOS transistors 64, 65 become ON, the output of the inverter 59 switches to 0 V, states of the nMOS transistors 62, 63 are controlled to be OFF, the word line WLm becomes 0 V, and the plate line PLm becomes VCC/2. On the other hand, when the output of the NAND circuit 52 is 0 V, namely, when the word line WLm is selected, the states of the nMOS transistors 64, 65 are controlled to be OFF, the output of the inverter 59 switches to VCC, the states of the nMOS transistors 62, 63 are controlled to be ON, the word line WLm is provided with the word-line driving voltage WL through the nMOS transistor 61, and the plate line PLm is provided with the plate-electrode driving voltage PL through the nMOS transistor 63. FIG. 9 shows a schematic diagram of a first embodiment of the plate-electrode driving-voltage generation circuit 23. The first embodiment of the plate-electrode driving-voltage generation circuit 23 generates the plate-electrode driving voltage PL according to the plate-electrode driving-voltage generation control signals 1, 2. In FIG. 9, the plate-electrode driving-voltage generation circuit 23 includes a NAND circuit 67 processing a NAND operation with the plate-electrode driving-voltage generation control signals 1, 2, an inverter 68 inverting the plate-electrode driving-voltage generation control signal 1, and a NOR circuit 69 processing a NOR operation with an output of the inverter 68 and the plate-electrode driving-voltage generation control signal 2. The plate-electrode driving-voltage generation circuit 23 further includes a pMOS transistor 70 controlled to be ON or OFF by an output of the NAND circuit 67, an nMOS transistor 71 controlled to be ON or OFF by an output of the inverter 68, and an nMOS transistor 72 controlled to be ON or OFF by an output of the NOR circuit 69. A source of the pMOS transistor 70 is provided with a voltage VH, a drain of the nMOS transistor 71 is provided with VCC/2, and a source of the nMOS transistor 72 is provided with a voltage VL. The voltage VH is set higher than VCC/2, and the voltage VL is set lower than VCC/2. For example, when VCC/2 is 1.5 V, the voltage VH may be 2.5 V, and the voltage VL may be 1.0 V. In this embodiment, a drain of the pMOS transistor 70, a source of the nMOS transistor 71, and a drain of the nMOS transistor 72 are connected to each other at a connection point, and from the connection point, the plate-electrode driving voltage PL is obtained. The voltage VL and the voltage VH may be generated, for example, using an internal level-down power-supply converter and an internal level-up power-supply converter shown later in FIG. 36A and FIG. 36B. FIG. 10 shows waveforms for explaining an operation of the first embodiment of the plate-electrode driving-voltage generation circuit 23 shown in FIG. 9. FIG. 10 illustrates the waveforms of the plate-electrode driving-voltage generation control signals 1, 2 and the plate-electrode driving voltage PL. In the first embodiment of the plate-electrode driving-voltage generation circuit 23, when the plate-electrode driving-voltage generation control signals 1, 2 are at the L level, the output of the NAND circuit 67 becomes the H level, the output of the inverter 68 becomes the H level, and the output of the NOR circuit 69 becomes the L level. As a result, in this case, the state of the pMOS transistor 70 is controlled to be OFF, the state of the nMOS transistor 71 is controlled to be ON, the state of the nMOS transistor 72 is controlled to be OFF, and the plate-electrode driving voltage PL becomes VCC/2. From the above situation, when the plate-electrode driving-voltage generation control signals 1, 2 become the H level, the output of the NAND circuit 67 becomes the L level, the output of the inverter 68 becomes the L level, and the output of the NOR circuit 69 is maintained at the L level. As a result, in this case, the state of the pMOS transistor 70 is controlled to be ON, the state of the nMOS transistor 71 is controlled to be OFF, and the state of the nMOS transistor 72 is maintained at OFF. Accordingly, the plate-electrode driving voltage PL becomes VH. From the above situation, when the plate-electrode driving-voltage generation control signal 2 becomes the L level, the output of the NAND circuit 67 becomes the H level, the output of the NOR circuit 69 becomes the H level, and the output of the inverter 68 is maintained at the L level. As a result, in this case, the state of the pMOS transistor 70 is controlled to be OFF, the state of the nMOS transistor 72 is controlled to be ON, and the state of the nMOS transistor 71 is maintained to be OFF. Accordingly, the plate-electrode driving voltage PL becomes VL. From the above situation, when the plate-electrode driving-voltage generation control signal 1 becomes the L level, the output of the NAND circuit 67 becomes the H level, and the output of the inverter 68 becomes the H level. Further, the output of the NOR circuit 69 becomes the L level. As a result, in this case, the state of the nMOS transistor 71 is controlled to be ON, the state of the nMOS transistor 72 is controlled to be OFF, and the state of the pMOS transistor 70 is maintained at OFF. Accordingly, the plate-electrode driving voltage PL returns to VCC/2. FIG. 11 shows a schematic diagram of a second embodiment of the plate-electrode driving-voltage generation circuit 23 shown in FIG. 6. The second embodiment of the plate-electrode driving-voltage generation circuit 23 generates the plate-electrode driving voltage PL according to the plate-electrode driving-voltage generation control signal 1. In FIG. 11, the plate-electrode driving-voltage generation circuit 23 includes an inversion-and-delay circuit 74 inverting and delaying the plate-electrode driving-voltage generation control signal 1. The inversion-and-delay circuit 74 has inverters 75 to 77, resistors 78 to 80, and capacitors 81 to 83. The plate-electrode driving-voltage generation circuit 23 shown in FIG. 11 further includes a NAND circuit 84 processing a NAND operation with the plate-electrode driving-voltage generation control signal 1 and an output A of the inversion-and-delay circuit 74, an inverter 85 inverting the output A of the inversion-and-delay circuit 74, a NOR circuit 86 processing a NOR operation with the plate-electrode driving-voltage generation control signal 1 and an output of the inverter 85, and a NOR circuit 87 processing a NOR operation with the plate-electrode driving-voltage generation control signal 1 and the output A of the inversion-and-delay circuit 74. The plate-electrode driving-voltage generation circuit 23 shown in FIG. 11 further includes a pMOS transistor 88 controlled to be ON or OFF by an output of the NAND circuit 84, an nMOS transistor 89 controlled to be ON or OFF by an output of the NOR circuit 86, and an nMOS transistor 90 controlled to be ON or OFF by an output of the NOR circuit 87. A source of the pMOS transistor 88 is provided with the voltage VH, a drain of the nMOS transistor 89 is provided with VCC/2, and a source of the nMOS transistor 90 is provided with the voltage VL. In this embodiment, a drain of the pMOS transistor 88, a source of the nMOS transistor 89, and a drain of the nMOS transistor 90 are connected to each other at a connection point, and from the connection point, the plate-electrode driving voltage PL is obtained. FIG. 12 shows waveforms for explaining an operation of the second embodiment of the plate-electrode driving-voltage generation circuit 23 shown in FIG. 11. FIG. 12 illustrates the waveforms of the plate-electrode driving-voltage generation control signal 1, the output A of the inversion-and-delay circuit 74 and the plate-electrode driving voltage PL. In the second embodiment of the plate-electrode driving-voltage generation circuit 23, when the plate-electrode driving-voltage generation control signal 1 is at the L level, the output A of the inversion-and-delay circuit 74 becomes the H level, the output of the NAND circuit 84 becomes the H level, the output of the inverter 85 becomes the L level, the output of the NOR circuit 86 becomes the H level and the output of the NOR circuit 87 becomes the L level. As a result, in this case, a state of the pMOS transistor 88 is controlled to be OFF, a state of the nMOS transistor 89 is controlled to be ON, a state of the nMOS transistor 90 is controlled to be OFF, and the plate-electrode driving voltage PL becomes VCC/2. From the above situation, when the plate-electrode driving-voltage generation control signal 1 becomes the H level, the output of the NAND circuit 84 becomes the L level, the output of the NOR circuit 86 becomes the L level, and the output of the NOR circuit 87 is maintained at the L level. As a result, in this case, the state of the pMOS transistor 88 is controlled to be ON, the state of the nMOS transistor 89 is controlled to be OFF, and the state of the nMOS transistor 90 is maintained to be OFF. Accordingly, the plate-electrode driving voltage PL becomes VH. From the above situation, when the plate-electrode driving-voltage generation control signal 1 becomes the L level and the output A of the inversion-and-delay circuit 74 becomes the L level, the output of the NAND circuit 84 becomes the H level, the output of the inverter 85 becomes the H level, the output of the NOR circuit 87 becomes the H level, and the output of the NOR circuit 86 is maintained at the L level. As a result, in this case, the state of the pMOS transistor 88 is controlled to be OFF, the state of the nMOS transistor 90 is controlled to be ON, and the state of the nMOS transistor 89 is maintained at OFF. Accordingly, the plate-electrode driving voltage PL becomes VL. From the above situation, when the output A of the inversion-and-delay circuit 74 becomes the H level, the output of the inverter 85 becomes the L level, the output of the NOR circuit 86 becomes the H level, the output of the NOR circuit 87 becomes the L level, and the output of the NAND circuit 84 is maintained at the H level. As a result, in this case, the state of the nMOS transistor 89 is controlled to be ON, the state of the nMOS transistor 90 is controlled to be OFF, and the state of the pMOS transistor 88 is maintained at OFF. Accordingly, the plate-electrode driving voltage PL returns to VCC/2. FIG. 13 shows a schematic diagram of a third embodiment of the plate-electrode driving-voltage generation circuit 23 shown in FIG. 6. The third embodiment of the plate-electrode driving-voltage generation circuit 23 generates the plate-electrode driving voltage PL according to the plate-electrode driving-voltage generation control signals 1, 2, 3, 4. In FIG. 13, the plate-electrode driving-voltage generation circuit 23 includes a NAND circuit 92 processing a NAND operation with the plate-electrode driving-voltage generation control signals 1, 2, an inverter 93 inverting the plate-electrode driving-voltage generation control signal 1, and a NOR circuit 94 processing a NOR operation with an output of the inverter 93 and the plate-electrode driving-voltage generation control signal 2. With respect to the above-discussed gate circuits, the plate-electrode driving-voltage generation circuit 23 includes a pMOS transistor 95 controlled to be ON or OFF by an output of the NAND circuit 92, and an nMOS transistor 96 controlled to be ON or OFF by an output of the NOR circuit 94. A source of the pMOS transistor 95 is provided with the voltage VH, and a source of the nMOS transistor 96 is provided with the voltage VL. Also, the plate-electrode driving-voltage generation circuit 23 includes a NAND circuit 97 processing a NAND operation with the plate-electrode driving-voltage generation control signals 3, 4, an inverter 98 inverting the plate-electrode driving-voltage generation control signal 3, and a NOR circuit 99 processing a NOR operation with an output of the inverter 98 and the plate-electrode driving-voltage generation control signal 4. With respect to the above-discussed gate circuits, the plate-electrode driving-voltage generation circuit 23 includes a pMOS transistor 100 controlled to be ON or OFF by an output of the NAND circuit 97, and an nMOS transistor 101 controlled to be ON or OFF by an output of the NOR circuit 99. A source of the pMOS transistor 100 is provided with a voltage VHH, and a source of the nMOS transistor 101 is provided with a voltage VLL. The voltage VHH is set higher than the voltage VH, and the voltage VLL is set lower than the voltage VL. For example, when VCC/2 is 1.5 V, the voltage VH is 2.5 V, the voltage VL is 1.0 V, the voltage VHH may be 3.0 V, and the voltage VLL may be 0 V. Further, the plate-electrode driving-voltage generation circuit 23 includes a NOR circuit 102 processing a NOR operation with the plate-electrode driving-voltage generation control signals 1, 3, and an nMOS transistor 103 controlled to be ON or OFF by an output of the NOR circuit 102. A drain of the nMOS transistor 103 is provided with the voltage VCC/2. In this embodiment, drains of the pMOS transistors 95,100, drains of the nMOS transistors 96, 101, and a source of the nMOS transistor 103 are connected to each other at one connection point, and from the connection point, the plate-electrode driving voltage PL is obtained. FIG. 14 shows waveforms for explaining an operation of the third embodiment of the plate-electrode driving-voltage generation circuit 23 shown in FIG. 13. FIG. 14 illustrates the waveforms of the plate-electrode driving-voltage generation control signals 1, 2, 3, 4, and the plate-electrode driving voltage PL. In the third embodiment of the plate-electrode driving-voltage generation circuit 23 shown in FIG. 13, when the plate-electrode driving-voltage generation control signals 1, 2, 3, 4 are at the L level, the output of the NAND circuit 92 becomes the H level, the output of the inverter 93 becomes the H level, the output of the NOR circuit 94 becomes the L level, the output of the NAND circuit 97 becomes the H level, the output of the inverter 98 becomes the H level, the output of the NOR circuit 99 becomes the L level and the output of the NOR circuit 102 becomes the H level. As a result, in this case, states of the pMOS transistors 95, 100 are controlled to be OFF, states of the nMOS transistor 96, 101 are controlled to be OFF, a state of the nMOS transistor 103 is controlled to be ON, and, thus, the plate-electrode driving voltage PL becomes VCC/2. From the above situation, when the plate-electrode driving-voltage generation control signals 1, 2 become the H level, the output of the NAND circuit 92 becomes the L level, the output of the inverter 93 becomes the L level, the output of the NOR circuit 102 becomes the L level, the output of the NOR circuit 94 is maintained at the L level, the output of the NAND circuit 97 is maintained at the H level, the output of the inverter 98 is maintained at the H level, and the output of the NOR circuit 99 is maintained at the L level. As a result, in this case, the state of the pMOS transistor 95 is controlled to be ON, the state of the nMOS transistor 103 is controlled to be OFF, the state of the pMOS transistor 100 is maintained at OFF, the states of the nMOS transistors 96, 101 are maintained at OFF and the plate-electrode driving voltage PL becomes the voltage VH. From the above situation, when the plate-electrode driving-voltage generation control signal 2 becomes the L level, the output of the NAND circuit 92 becomes the H level, the output of the NOR circuit 94 becomes the H level, the output of the NAND circuit 97 is maintained at the H level, the output of the inverter 98 is maintained at the H level, the output of the NOR circuit 99 is maintained at the L level and the output of the NOR circuit 102 is maintained at the L level. As a result, in this case, the state of the pMOS transistor 95 is controlled to be OFF, the state of the nMOS transistor 96 is controlled to be ON, the state of the pMOS transistor 100 is maintained at OFF, the states of the nMOS transistors 101, 103 are maintained at OFF, and, thus, the plate-electrode driving voltage PL becomes the voltage VL. From the above situation, when the plate-electrode driving-voltage generation control signal 1 becomes the L level, the output of the inverter 93 becomes the H level, the output of the NOR circuit 94 becomes the L level, the output of the NOR circuit 102 becomes the H level, the output of the NAND circuit 92 is maintained at the H level, the output of the NAND circuit 97 is maintained at the H level, the output of the inverter 98 is maintained at the H level, and the output of the NOR circuit 99 is maintained at the L level. As a result, in this case, the state of the nMOS transistor 96 is controlled to be OFF, the state of the nMOS transistor 103 is controlled to be ON, the states of the pMOS transistors 95, 100 are maintained at OFF, the state of the nMOS transistor 101 is maintained at OFF, and, thus, the plate-electrode driving voltage PL returns to VCC/2. From the above situation, when the plate-electrode driving-voltage generation control signals 3, 4 become the H level, the output of the NAND circuit 97 becomes the L level, the output of the inverter 98 becomes the L level, the output of the NOR circuit 99 is maintained at the L level, the output of the NAND circuit 92 is maintained at the H level, the output of the inverter 93 is maintained at the H level, and the output of the NOR circuit 94 is maintained at the L level. As a result, in this case, the state of the pMOS transistor 100 is controlled to be ON, the state of the nMOS transistor 103 is controlled to be OFF, the state of the pMOS transistor 95 is maintained at OFF, the states of the nMOS transistors 96, 101 are maintained at OFF, and, thus, the plate-electrode driving voltage PL becomes the voltage VHH. From the above situation, when the plate-electrode driving-voltage generation control signal 4 becomes the L level, the output of the NAND circuit 97 becomes the H level, the output of the NOR circuit 99 becomes the H level, the output of the NAND circuit 92 is maintained at the H level, the output of the inverter 93 is maintained at the H level, the output of the NOR circuit 94 is maintained at the L level and the output of the NOR circuit 102 is maintained at the L level. As a result, in this case, the state of the pMOS transistor 100 is controlled to be OFF, the state of the nMOS transistor 101 is controlled to be ON, the state of the pMOS transistor 95 is maintained at OFF, the states of the nMOS transistors 96, 103 are maintained at OFF, and, thus, the plate-electrode driving voltage PL becomes the voltage VLL. From the above situation, when the plate-electrode driving-voltage generation control signal 3 becomes the L level, the output of the inverter 98 becomes the H level, the output of the NOR circuit 99 becomes the L level, the output of the NOR circuit 102 becomes the H level, the output of the NAND circuit 97 is maintained at the H level, the output of the NAND circuit 92 is maintained at the H level, the output of the inverter 93 is maintained at the H level, and the output of the NOR circuit 94 is maintained at the L level. As a result, in this case, the state of the nMOS transistor 101 is controlled to be OFF, the state of the nMOS transistor 103 is controlled to be ON, the state of the pMOS transistors 95, 100 are maintained at OFF, the state of the nMOS transistor 96 is maintained at OFF, and, thus, the plate-electrode driving voltage PL returns to VCC/2. FIG. 15 and FIG. 16 show illustrations for explaining a data-writing sequence in the memory cell of the embodiment of the ferroelectric memory according to the present invention. These drawings show examples of the data-writing sequence regarding the memory cell 29 shown in FIG. 7. A horizontal axis indicates the voltage of the bit line BL to the voltage of the plate line PL0, V BL - V PL0 . A vertical axis indicates polarization P of the ferroelectric capacitor 31. For example, when the logic "1" is written into the memory cell 29, the voltage V PL0 of the plate PL0 is set to VCC/2, and the cell transistor 33 is set to be conductive. Under this condition, the voltage V BL of the bit line BL is changed from VCC/2 to VCC (wherein the cell transistor turns off), and is subsequently changed to VCC/2. In the above sequence, a state of the polarization P of the ferroelectric capacitor 31 changes, as shown in FIG. 15, from a point A to a point B, and then to a point C by a leak of the cell transistor. At the point C, the polarization P of the ferroelectric capacitor 31 becomes a positive polarization Pr. As a result, the logic "1" is stored in the ferroelectric capacitor 31. A closed curved line of B to C to D to E to B indicates a hysteresis loop. On the other hand, when the logic "0" is written into the memory cell 29, the voltage V PL0 of the plate line PL0 is set to VCC/2, and the cell transistor 33 is set to be conductive. Under this condition, the voltage V BL of the bit line BL is changed from VCC/2 to 0 V (wherein the cell transistor turns off), and is further changed to VCC/2. In the above sequence, a voltage of a storage electrode 31A to that of a plate electrode 31B of the ferroelectric capacitor 31 changes from 0 V to - VCC/2, and is subsequently changed to 0 V by a leak of the cell transistor. The state of the polarization P of the ferroelectric capacitor 31 changes, as shown in FIG. 16, from a point A to a point D, and then to a point E. At the point E, the polarization P of the ferroelectric capacitor 31 becomes a negative polarization -Pr. As a result, the logic "0" is stored in the ferroelectric capacitor 31. In the following, a description will be given of a first embodiment of a method of reading out data in the ferroelectric memory according to the present invention. FIG. 17 shows waveforms for explaining a data-reading sequence from the memory cell of the embodiment of the ferroelectric memory according to the present invention. The drawing shows an example of the data-reading sequence regarding the memory cell 29 shown in FIG. 7. In FIG. 17, a waveform A indicates a variation of the voltage of the word line WL0, a waveform B indicates a variation of the voltage of the plate line PL0, waveforms C indicate variations of the voltages of the bit lines BL, /BL in a case where the logic "1" is written in the ferroelectric capacitor 31, and waveforms D indicate variations of the voltages of the bit lines BL, /BL in a case where the logic "0" is written in the ferroelectric capacitor 31. Before the data is read out from the memory cell 29, the precharge control signal PR is previously set to the H level, the states of the nMOS transistors 38 to 40 are previously controlled to be ON, and the bit lines BL, /BL are precharged to VCC/2. Further, through the word-and-plate driver, the word line WL0 is increased to VCC + VTH (VTH is a threshold voltage of the cell transistor) to control the cell transistor 33 to be ON. Subsequently, through the word-and-plate driver, as shown in FIG. 10, FIG. 12, and FIG. 14, the plate-electrode driving voltage PL is changed from VCC/2 to the voltage VH, to the voltage VL, and to VCC/2. FIG. 18A and FIG. 18B show illustrations for explaining a variation of the voltage of the bit line BL in a case where the logic "1" is written in the ferroelectric capacitor 31. FIG. 18A shows a variation of polarization P of the ferroelectric capacitor 31, and FIG. 18B shows a relationship between the variation of the polarization P of the ferroelectric capacitor 31 and a variation of the voltage of the bit line BL. In FIG. 18A, a straight line 105 indicates a relationship of Q BL = C BL V BL , where Q BL is a charge which transfers from the ferroelectric capacitor 31 to the bit line BL, and C BL was a value of capacitance of the bit line BL. In a case where the logic "1" is previously written in the ferroelectric capacitor 31, when the plate-electrode driving voltage PL is successively changed from VCC/2 to the voltage VH, to the voltage VL, and to VCC/2, the polarization P of the ferroelectric capacitor 31, as shown in FIG. 18A, successively changes from a point C to a point Z1, to a point Z2, to a point Z3, and to a point Z4. Finally, a charge δQ3, by which the voltage V BL of the bit line BL is the same as the voltage of the storage electrode 31A of the ferroelectric capacitor 31, transfers from the ferroelectric capacitor 31 to the bit line BL. As a result, the voltage V BL of the bit line BL increases to VCC/2 + Vα. In this way, in the case where the logic "1" is written in the ferroelectric capacitor 31, the voltage V BL of the bit line BL increases to VCC/2 + Va, and the voltage V /BL of the bit line /BL is maintained at VCC/2. Therefore, as shown in the waveform C of FIG. 17, by the sense amplifier 43, the voltage V BL of the bit line BL increases to VCC, and the voltage V /BL of the bit line /BL decreases to 0 V. As a result, a voltage difference between the bit lines BL, \BL is amplified. In this case, since the plate-electrode driving voltage PL is maintained at VCC/2, the voltage V BL of the bit line BL increases from VCC/2 + Vα to VCC. As a result, in the ferroelectric capacitor 31, the logic "1", namely, the data which has been read out, is re-written. FIG. 19A and FIG. 19B show illustrations for explaining a variation of the voltage of the bit line BL in a case where the logic "0" is written in the ferroelectric capacitor 31. FIG. 19A shows a variation of polarization P of the ferroelectric capacitor 31, and FIG. 19B shows a relationship between the variation of the polarization P of the ferroelectric capacitor 31 and a variation of the voltage of the bit line BL. In a case where the logic "0" was previously written in the ferroelectric capacitor 31, when the plate-electrode driving voltage PL is successively changed from VCC/2 to the voltage VH, to the voltage VL, and to VCC/2, the polarization P of the ferroelectric capacitor 31, as shown in FIG. 19A, successively changes from a point E to a point W1, to a point W2, to a point W3, and to a point W4. Finally, a charge δQ4, by which the voltage V BL of the bit line BL is the same as the voltage of the storage electrode 31A of the ferroelectric capacitor 31, transfers from the bit line BL to the ferroelectric capacitor 31. As a result, the voltage V BL of the bit line BL decreases to VCC/2 - Vβ. In this way, in the case where the logic "0" is written in the ferroelectric capacitor 31, the voltage V BL of the bit line BL decreases to VCC/2 - Vβ, and the voltage V /BL of the bit line /BL is maintained at VCC/2. Therefore, as shown in the waveform D of FIG. 17, by the sense amplifier 43, the voltage V BL of the bit line BL decreases to 0 V, and the voltage V /BL of the bit line /BL increases to VCC. As a result, the voltage difference between the bit lines BL, \BL is amplified. In this case, since the plate-electrode driving voltage PL is maintained at VCC/2, the voltage V BL of the bit line BL decreases from VCC/2 - Vβ to 0 V. As a result, in the ferroelectric capacitor 31, the logic "0", namely, the data which has been read out, is re-written. As discussed above, in the embodiment of the ferroelectric memory according to the present invention, for example, when the data is read out from the memory cell 29, and after the bit lines BL, /BL are precharged to VCC/2, the cell transistor 33 is controlled to be ON. Also, the voltage applied to the plate electrode 31B of the ferroelectric capacitor 31 is successively changed from VCC/2 to the voltage VH, to the voltage VL, and to VCC/2. At this time, when the logic "1" is written in the ferroelectric capacitor 31, the voltage V BL of the bit line BL increases to VCC/2 + Vα, and when the logic "0" is written in the ferroelectric capacitor 31, the voltage V BL of the bit line BL decreases to VCC/2 - Vβ. In this way, the voltage difference between the bit lines BL, \BL is amplified. According to the ferroelectric memory of the present invention, the data which has been read out from the selected memory cell to the bit line may be detected in the same way as that of a DRAM using a method of precharging the bit line to VCC/2. Since the ferroelectric memory according to the present invention does not need a dummy cell, a stable operation for a long term may be expected. In the above-discussed embodiment of the ferroelectric memory according to the present invention, in the case where the plate-electrode driving-voltage generation circuit 23 is constructed as shown in FIG. 13, when the data is re-written after the plate-electrode driving voltage PL is successively changed from VCC/2 to the voltage VH, to the voltage VL, and to VCC/2, the data may positively be written by successively changing the plate-electrode driving voltage PL from VCC/2 to the voltage VHH, to the voltage VLL, and to VCC/2, as shown in FIG. 20. When the data is re-written, and when the plate-electrode driving voltage PL is successively changed from VCC/2 to the voltage VHH, to the voltage VLL, and to VCC/2, for example, when the logic "1" is previously written in the ferroelectric capacitor 31, the difference between the voltage V BL of the bit line BL and the voltage V PL0 of the plate line PL0, V BL - V PL0 , may be VCC. Accordingly, a sufficient polarization indicating that stored data is the logic "1" may be obtained. On the other hand, when the logic "0" is previously written in the ferroelectric capacitor 31, the difference between the voltage V BL of the bit line BL and the voltage V PL0 of the plate line PL0, V BL - V PL0 , may be -VCC. Accordingly, a sufficient polarization indicating that stored data is the logic "0" may be obtained. In the above-discussed embodiment of the ferroelectric memory according to the present invention, the descriptions has been given under the assumption that VHH (i.e. 3.0 V) > VH (i.e. 2.5 V), and VLL (i.e. 0 V) < VL (i.e. 1.0 V). However, the above assumption is not necessarily required. In the embodiment of the ferroelectric memory according to the present invention, when the voltage VH is set so that a voltage larger than a writing voltage is applied to the ferroelectric capacitor 31, namely, when the voltage VH is set so as to satisfy a relationship such that a voltage applied between the storage electrode 31A and the plate electrode 31B of the ferroelectric capacitor 31 = V BL - V PL0 = V BL - VH < -VCC/2, when the logic "0" is written in the ferroelectric capacitor 31, the polarization P of the ferroelectric capacitor 31 changes from a point E along a solid line 107, and returns to the point E, as shown in FIG. 21. In this situation, the voltage V BL of the bit line BL may be substantially the same as the voltage V /BL of the bit line /BL, or the polarization P may further increase as compared to that before the data is read out in a negative direction, and the voltage V BL of the bit line BL increases larger than the voltage V /BL of the bit line /BL. As a result, the data of the logic "1" may be read out in error. Further, in a case in which the voltage VL is set so as to satisfy a relationship (VH - VCC/2) < (VCC/2 - VL), when the logic "1" is written in the ferroelectric capacitor 31, the polarization P of the ferroelectric capacitor 31 changes from a point C along a solid line 108, and returns to the point C, as shown in FIG. 21. In this situation, the voltage V BL of the bit line BL may be substantially the same as the voltage V /BL of the bit line /BL, or the polarization P may further increase as compared to that before the data is read out in a positive direction, and the voltage V BL of the bit line BL decreases less than the voltage V /BL of the bit line /BL. As a result, the data of the logic "0" may be read out in error. Therefore, in the embodiment of the ferroelectric memory according to the present invention, to prevent a voltage larger than the writing voltage from being applied to the ferroelectric capacitor, it is preferred that the voltage VH is selected so as to satisfy a relationship (V BL - VH) > -VCC/2, and the voltage VL is selected so as to satisfy a relationship (VCC/2 - VL) < (VH - VCC/2). Therefore, it is preferred that an electrical-field strength applied to the ferroelectric capacitor when the voltage VH is applied to the plate electrode is set to be less than an electrical-field strength applied when the data is written into the ferroelectric capacitor, and an electrical-field strength applied to the ferroelectric capacitor when the voltage VL is applied to the plate electrode is set to be less than the electrical-field strength applied to the ferroelectric capacitor when the voltage VH is applied to the plate electrode. Further, in the embodiment of the ferroelectric memory according to the present invention, it is preferred that the voltages VH and VL are set so that a reading margin when the logic "0" is written in the ferroelectric capacitor is substantially equal to a reading margin when the logic "1" is written in the ferroelectric capacitor. FIG. 22 shows an illustration for explaining a relationship of a voltage applied between the storage electrode and the plate electrode of the ferroelectric capacitor at a second time, namely, VL - VCC/2, and a variation of the polarization δP of the ferroelectric capacitor, namely, an amount of charge appearing at the electrodes. In FIG. 22, the writing voltage is set to 5 V, and when the data is read out, a voltage applied between the storage electrode and the plate electrode of the ferroelectric capacitor at a first time, namely, VH - VCC/2, is set to 5 V. Also, a curved line 110 indicates a case where the logic "0" is written in the ferroelectric capacitor, and a curved line 111 indicates a case where the logic "1" is written in the ferroelectric capacitor. In this case, when the voltage VL is set so as to satisfy a relationship VL - VCC/2 = -1.6 V, the reading margin when the logic "0" is written in the ferroelectric capacitor may be substantially equal to the reading margin when the logic "1" is written in the ferroelectric capacitor. FIG. 23 shows an illustration for explaining a relationship of the voltage VL - VCC/2 and the variation of the polarization δP of the ferroelectric capacitor. In FIG. 23, the writing voltage is set to 5 V, and the voltage VH - VCC/2 is set to 2.5 V. Also, a curved line 113 indicates the case where the logic "0" is written in the ferroelectric capacitor, and a curved line 114 indicates a case where the logic "1" is written in the ferroelectric capacitor. In this case, when the voltage VL is set so as to satisfy a relationship VL - VCC/2 = -1.3 V, the reading margin when the logic "0" is written in the ferroelectric capacitor may be substantially equal to the reading margin when the logic "1" is written in the ferroelectric capacitor. To amplify the voltage difference between the bit lines BL, /BL by the sense amplifier 43, when at least 10 fC/1 cell charge is required, a required variation of the polarization δP is 1 µC/cm 2 in a case where an area of the ferroelectric capacitor is 1 µm 2 . Therefore, a pulse applied to the plate electrode of the ferroelectric capacitor may be reduced within a range satisfying the above-discussed condition. By the reduction of the pulse, inversion fatigue of the ferroelectric capacitor may be reduced, and a life time of the device may be increased. Further, since an amount of charging for the ferroelectric capacitor and an amount of discharging for the ferroelectric capacitor may be reduced, speed of the reading operation may be increased, and power consumption may be reduced. In the following, a description will be given of a second embodiment of a method of reading out the data in the ferroelectric memory according to the present invention. FIG. 24 shows waveforms for explaining another data-reading sequence from the memory cell of the embodiment of the ferroelectric memory according to the present invention. The drawing shows an example of the data-reading sequence regarding the memory cell 29 shown in FIG. 7. In FIG. 24, a waveform A indicates a variation of the voltage of the word line WL0, a waveform B indicates a variation of the voltage of the plate line PL0, waveforms C indicate variations of the voltages of the bit lines BL, /BL in the case where the logic "1" is written in the ferroelectric capacitor 31, and waveforms D indicate variations of the voltages of the bit lines BL, /BL in the case where the logic "0" is written in the ferroelectric capacitor 31. In the embodiment of the ferroelectric memory according to the present invention, for example, when VCC/2 is set to 1.5 V, and when the voltage VL is set to 0.5 V and the voltage VH is set to 2.0 V, even if the plate-electrode driving voltage PL is changed from VCC/2 to the voltage VL, to the voltage VH, and to the voltage VCC/2, the data may be read out from the memory. FIG. 25A and FIG. 25B show illustrations for explaining a variation of the voltage of the bit line BL in the case where the logic "1" is written in the ferroelectric capacitor 31. FIG. 25A shows a variation of polarization P of the ferroelectric capacitor 31, and FIG. 25B shows a relationship between the variation of the polarization P of the ferroelectric capacitor 31 and the variation of the voltage of the bit line BL. In FIG. 25A, a straight line 116 indicates the relationship of Q BL = C BL V BL , where Q BL is the charge which transfers from the ferroelectric capacitor 31 to the bit line BL, and C BL is the capacitance value of the bit line BL. In the case where the logic "1" is previously written in the ferroelectric capacitor 31, when the plate-electrode driving voltage PL is successively changed from VCC/2 to the voltage VL, to the voltage VH, and to VCC/2, the polarization P of the ferroelectric capacitor 31, as shown in FIG. 25A, successively changes from a point C to a point S1, to a point S2, to a point S3, and to a point S4. Finally, a charge δQ5, by which the voltage V BL of the bit line BL is the same as the voltage of the storage electrode 31A of the ferroelectric capacitor 31, transfers from the ferroelectric capacitor 31 to the bit line BL. As a result, the voltage V BL of the bit line BL increases to VCC/2 + V . In this way, in the case where the logic "1" was previously written in the ferroelectric capacitor 31, the voltage V BL of the bit line BL increases to VCC/2 + V , and the voltage V /BL of the bit line /BL is maintained at VCC/2. Therefore, as shown in the waveform C of FIG. 24, by the sense amplifier 43, the voltage V BL of the bit line BL increases to VCC, and the voltage V /BL of the bit line /BL decreases to 0 V. As a result, the voltage difference between the bit lines BL, \BL is amplified. In this case, since the plate-electrode driving voltage PL is maintained at VCC/2, the voltage V BL of the bit line BL increases from VCC/2 + V to VCC. As a result, in the ferroelectric capacitor 31, the data of the logic "1" which has been read out is re-written. FIG. 26A and FIG. 26B show illustrations for explaining the variation of the voltage of the bit line BL in the case where the logic "0" is written in the ferroelectric capacitor 31 shown in FIG. 7. FIG. 26A shows the variation of polarization P of the ferroelectric capacitor 31, and FIG. 26B shows the relationship between the variation of the polarization P of the ferroelectric capacitor 31 and the variation of the voltage of the bit line BL. In the case where the logic "0" was previously written in the ferroelectric capacitor 31, when the plate-electrode driving voltage PL is successively changed from VCC/2 to the voltage VL, to the voltage VH, and to VCC/2, the polarization P of the ferroelectric capacitor 31, as shown in FIG. 26A, successively changes from a point E to a point T1, to a point T2, to a point T3, and to a point T4. Finally, a charge δQ6, by which the voltage V BL of the bit line BL is the same as the voltage of the storage electrode 31A of the ferroelectric capacitor 31, transfers from the bit line BL to the ferroelectric capacitor 31. As a result, the voltage V BL of the bit line BL decreases to VCC/2 - Vδ. In this way, in the case where the logic "0" was previously written in the ferroelectric capacitor 31, the voltage V BL of the bit line BL decreases to VCC/2 - V6, and the voltage V /BL of the bit line /BL is maintained at VCC/2. Therefore, as shown in the waveform D of FIG. 24, by the sense amplifier 43, the voltage V BL of the bit line BL decreases to 0 V, and the voltage V /BL of the bit line /BL increases to VCC. As a result, the voltage difference between the bit lines BL, \BL is amplified. In this case, since the plate-electrode driving voltage PL is maintained at VCC/2, the voltage V BL of the bit line BL decreases from VCC/2 - Vδ to 0 V. As a result, in the ferroelectric capacitor 31, the data of the logic "0" which has been read out is re-written. For example, when the relationship V BL - VL > VCC/2 is satisfied and when the logic "1" is written in the ferroelectric capacitor 31, the polarization P of the ferroelectric capacitor 31 changes from a point C along a solid line 118, and returns to the point C, as shown in FIG. 27. In this situation, the voltage V BL of the bit line BL may be substantially the same as the voltage V /BL of the bit line /BL, or the polarization P may further increase as compared to that before the data is read out in a positive direction, and the voltage V BL of the bit line BL may decrease less than the voltage V /BL of the bit line /BL. As a result, the data of the logic "0" may be read out in error. Further, when the relationship (VCC/2 - VL) < (VH - VCC/2) and when the logic "0" was previously written in the ferroelectric capacitor 31, the polarization P of the ferroelectric capacitor 31 changes from a point E along a solid line 119, and returns to the point E, as shown in FIG. 27. In this situation, the voltage V BL of the bit line BL may be substantially the same as the voltage V /BL of the bit line /BL, or the polarization P may further increase as compared to that before the data is read out in a negative direction, and the voltage V BL of the bit line BL may increase larger than the voltage V /BL of the bit line /BL. As a result, the data of the logic "1" may be read out in error. Therefore, in the embodiment of the ferroelectric memory according to the present invention, to prevent such an error, it is preferred that the voltage VL is selected so as to satisfy a relationship (V BL - VL) < VCC/2, and the voltage VH is selected so as to satisfy a relationship (VH - VCC/2) < ( VCC/2 - VL). Therefore, it is preferred that the electrical-field strength applied to the ferroelectric capacitor when the voltage VL is applied to the plate electrode is set less than the electrical-field strength applied when the data is written into the ferroelectric capacitor, and the electrical-field strength applied to the ferroelectric capacitor when the voltage VH is applied to the plate electrode is set less than the electrical-field strength applied to the ferroelectric capacitor when the voltage VL is applied to the plate electrode. In this case, after the plate-electrode driving voltage PL is successively changed from VCC/2 (for example, 1.5 V) to the voltage VL (for example, 0.5 V), to the voltage VH (for example, 2.0 V), and to VCC/2, when the plate-electrode driving voltage PL is changed from VCC/2 to the voltage VLL (for example, 0 V), to the voltage VHH (for example, 3.0 V), and to VCC/2, the data may positively be re-written. As discussed above, according to the present invention, without providing the dummy cell, the data may positively be read out from the memory cell, and, thus, a stable operation of the ferroelectric memory may be performed for a long term. In the above description, in the ferroelectric memory according to the present invention, the preferred method of setting the voltages VH and the VL is shown. However, in practical use, a reading-out margin (an amplitude of the read-out signal) varies according to a ratio of a bit-line capacitance (shows parasitic capacitance of the bit line) to capacitance of the ferroelectric capacitor. Therefore, for obtaining a sufficient reading-out margin, a proper capacitance ratio and the voltages VH and VL need to be set. In the following, a description will be given of the optimum capacitance ratio of the bit-line capacitor and the ferroelectric capacitor. First, the basic operation of the above-discussed ferroelectric memory according to the present invention is summarized as follows. FIG. 28 shows a simplified circuit configuration example of the ferroelectric memory according to the present invention. FIG. 29 shows hysteresis characteristics of the ferroelectric capacitor, where information of the logic "1" and "0" is respectively stored in conditions represented by symbols "a" and "b". FIG. 30 shows a timing chart of the reading-out operation. During storing of the data, the plate line (PL) and bit line (BL) are maintained at the voltage VCC/2. When reading out the data, the voltage of the word line (WL) is increased, a cell transistor is turned on, and opposite pulses having different polarization are provided to the plate line (PL). A horizontal axis in FIG. 29 indicates the voltage difference (= V BL - V PL ) between the bit-line voltage V BL and the plate-line voltage V PL , and the polarization of the ferroelectric capacitor 204 varies as shown in FIG. 29. Finally, the bit-line voltage V BL varies in a positive or negative direction from the voltage VCC/2 according to the direction of the stored polarization. At this time, voltage deviation (dVBL) of the bit-line voltage V BL is represented by a decrease of the remanent polarization (δPrS) and the bit-line capacitance C BL is shown as follows: dVBL = δPrS / C BL . Since the voltage V /BL of the complement bit line /BL is set to the voltage VCC/2, a voltage difference between the bit line BL and the bit line /BL is amplified in a sense amplifier 206. In this way, the data is externally read out, and a re-writing operation of the data to the capacitor is carried out. The amplitude of the reading-out signal depends on an amplitude of the input pulse provided to the plate line PL. In the following, a voltage difference between the voltage VCC/2 and the voltage VH provided as the first pulse of the plate line voltage is represented by δVH, and a voltage difference between the voltage VCC/2 and the voltage VL provided as the second pulse of the plate line voltage is represented by δVL. When the logic "1" is written in the ferroelectric capacitor 204, the reading-out margin increases, as δVH is larger and δVL is smaller, and when the logic "0" is written in the ferroelectric capacitor 204, the reading-out margin increases, as δVL is larger. In the above-discussed ferroelectric memory, it is shown that the voltages VH and VL are preferably set so that the reading-out margin in a case where the logic "1" is written in the ferroelectric memory 204 may be substantially equal to that in a case where the logic "0" is written in the ferroelectric memory 204. However, as discussed above, the reading-out margin (amplitude of the reading-out signal) varies according to the ratio of the bit-line capacitance C BL and the capacitance of the ferroelectric capacitor 204. In the following, a description will be given of the methods of setting the optimum capacitance ratio and voltages VH and VL in the ferroelectric memory according to the present invention. FIG. 31A to FIG. 31C show illustrations for explaining polarization variation when the data is read out from the ferroelectric capacitor in the circuits shown in FIG. 28. FIG. 31A shows variation of the plate-line voltage V PL , FIG. 31B shows polarization variation when the logic "1" is read out from the ferroelectric capacitor, and FIG. 31C shows polarization variation when the logic "0" is read out from the ferroelectric capacitor. Operation parameters are shown in the drawing in FIG. 31A. When the signal shown in FIG. 31A is provided to the plate line, the polarization of the ferroelectric capacitor 204 varies as shown in FIG. 31B and FIG. 31C. From these drawings, the voltage deviation dVBL appearing in the bit line BL may be the reading-out signal. This operation have been described in detail in the previous description, by referring to FIG. 17 to FIG. 19B. FIG. 32 shows an illustration for explaining dependence of the voltage deviation dVBL in the bit line BL upon the bit-line capacitance C BL for each voltage δVL in the operation described by referring to FIG. 31A to FIG. 31C. In FIG. 32, a horizontal axis indicates the bit-line capacitance C BL , and a vertical axis indicates the voltage deviation dVBL in the bit line BL. When the voltage δVL is -0.8V, the voltage deviation dVBL for reading out the logic "1" and the voltage deviation dVBL for reading out the logic "0" are substantially the same. In this case, when the bit-line capacitance C BL is 4.26 nF, the margin for the reading-out signal is maximized. Therefore, a stable reading-out operation may be expected. At this time, the ratio of the bit-line capacitance C BL and the capacitance of the ferroelectric capacitor 204 is 1.9 [V -1 ] (= C BL / PrS [C]). However, the bit-line capacitance C BL has an influence on consumption power and operation speed. In the following, a comparison of different bit-line capacitance C BL , for example, 1 nF and 8 nF, will be discussed. In FIG. 32, for the two bit-line capacitance C BL , 1 nF and 8 nF, the voltage deviation dVBL in the bit line BL has substantially the same value. FIG. 33A and FIG. 33B show a variation of the polarization of the ferroelectric capacitor 204 for the bit-line capacitance C BL of 1 nF and 8 nF. FIG. 33A shows a case where the logic "1" is read out from the ferroelectric capacitor 204, and FIG. 33B shows a case where the logic "0" is read out from the ferroelectric capacitor 204. As shown in FIG. 33A and FIG. 33B, variation of the polarization in the case where the bit-line capacitance C BL is 8 nF is larger than that in the case where the bit-line capacitance C BL is 1 nF. Namely, when the bit-line capacitance C BL is 8 nF, the power consumption may increase and the operation speed may decrease. Therefore, it is preferred that the bit-line capacitance C BL is smaller. As a result, considering the above-discussed method of increasing the reading-out margin (the ratio of the bit-line capacitance and the capacitance of the ferroelectric capacitor 204, C BL [F] / PrS [C] is set to 1.9 [V -1 ]), the ratio is preferably set so as to be less than the value that the reading-out signal dVBL is maximized. Therefore, for the ratio of the bit-line capacitance C BL and the capacitance of the ferroelectric capacitor, it is preferred to satisfy the following condition, 0.5 [V -1 ] < (C BL [F] / PrS [C]) < 2. In addition to the above-discussed method, by increasing the driving voltage VH of the plate line PL larger than the voltage VCC using the internal level-up power-supply converter shown later in FIG. 36B, the reading-out signal (voltage deviation dVBL in the bit line BL) may be increased. FIG. 34 shows an illustration for explaining dependence of the voltage deviation dVBL in the bit line BL upon the bit-line capacitance C BL in a case where the voltage 6VH is 2.65 V. In this case, when the voltage δVL is -1.0 V, the reading-out margins for the logic "1" and the logic "0" are substantially the same, and when the bit-line capacitance C BL is 2 to 3 nF, the reading-out margins are maximized, at 90 mV for the logic "1" and -80 mV for the logic "0". FIG. 35A to FIG. 35C show illustrations for explaining polarization variation of the ferroelectric capacitor under the condition shown in FIG. 34. FIG. 35A shows variation of the plate-line voltage V PL , FIG. 35B shows polarization variation when the logic "1" is read out from the ferroelectric capacitor, and FIG. 35C shows polarization variation when the logic "0" is read out from the ferroelectric capacitor. Compared with the drawings of FIG. 31B and FIG. 31C, an amount of variation of the polarization during the operation is substantially the same as compared with each other, but finally obtained signal margins in FIG. 35B and FIG. 35C are larger than those in FIG. 31B and FIG. 31C because the bit-line capacitance C BL has a smaller value. In this way, by reducing the value of the bit-line capacitance C BL , and using the level-up voltage provided from the level-up power-supply converter for the voltage VH, a larger reading-out signal may be obtained without increasing power consumption (since the polarization variation is reduced). The above-mentioned voltages VL and VH may be provided from, for example, the internal level-down power-supply converter and the internal level-up power-supply converter shown in FIG. 36A and FIG. 36B. The internal level-down power-supply converter includes a comparator, and the internal level-up power-supply converter includes a ring oscillator. Since these circuits are well known, a description of these circuit operations is eliminated here. As discussed above, by optimizing the ratio of the bit-line capacitance C BL and the capacitance of the ferroelectric capacitor 204, or by increasing the driving voltage VH of the plate line PL, a larger reading-out signal may be obtained, and, thus, a memory device operable for a long term may be provided. Further, the present invention is not limited to these embodiments, but other variations and modifications may be made without departing from the scope of the present invention.

Claims: A method of reading data from a ferroelectric memory having a memory cell (29), said memory cell (29) including a transmission gate (33) having a first charge input-and-output port connected to a data line (BL) and a second charge input-and-output port, and a ferroelectric capacitor (31) having a first electrode (31A) connected to said second charge input-and-output port and a second electrode (31B) connected to a driving voltage line (PL0), said method comprising the steps of: controlling said transmission gate (33) to be non-conductive; subsequently controlling said transmission gate (33) to be conductive; and applying a driving voltage to said second electrode (31B) of the ferroelectric capacitor (31) through the driving voltage line (PL0) to successively apply first and second electric fields having opposite directions to the ferroelectric capacitor (31) while said transmission gate is conductive, characterised in that : said data line (BL) is precharged to a precharge voltage that is substantially half of a power source voltage while said transmission gate is non-conductive; and the first electric field sets the second electrode (31B) to a voltage higher than the precharge voltage, and the second electric field sets the second electrode (31B) to a voltage lower than the precharge voltage, such that the polarization of the ferroelectric capacitor (31) is changed from a first value prior to application of the first and second electric fields to a second value following application of the first and second electric fields, the first and second values being sufficiently different to allow data to be read from the memory cell (29) by detecting a difference between the voltage of the data line (BL) and the precharge voltage. A method according to claim 1, said memory comprising a further memory cell (30) including a further transmission gate (34), the further transmission gate (34) having a first charge input-and-output port connected to a further data line (/BL), wherein in said precharging step, both the data line (BL) and the further data line (/BL) are precharged to said precharge voltage, and in said reading step, the data is read from the selected memory cell (29) through a corresponding one of the data line (BL) and the further data line (/BL). A method according to claim 1 or 2, wherein a strength of said first electric field is smaller than that of an electric field applied to said ferroelectric capacitor (31) when the data is written, and strength of said second electric field is smaller than that of said first electric field. A method according to any of the preceding claims, further comprising the step of successively applying third and fourth electric fields having opposite directions, a strength of said third and fourth electric fields being respectively larger than that of said first and second electric fields applied to said ferroelectric capacitor (31), and polarization of the ferroelectric capacitor (31) being changed according to a variation of said third and fourth electric fields. A method according to any of the preceding claims, wherein a strength of said first and second electric fields is set so that a reading-out margin when a logic "1" is written in said ferroelectric capacitor (31) is substantially equal to a reading-out margin when a logic "0" is written in said ferroelectric capacitor (31). A method according to any of the preceding claims, wherein said data line (BL) has a parasitic capacitance C BL , the parasitic capacitance C BL being equal to or less than a value for which a voltage difference generated in said data line (BL) when a logic "1" and a logic "0" are read out is substantially maximized. A method according to claim 6, wherein one of said first and second electric fields is larger than an internal power-supply voltage, and when the data is read out, a voltage generated in said data line (BL) increases as compared with a case where said one is substantially the same as the internal power-supply voltage. A method according to claim 7, wherein said ferroelectric capacitor includes Pb (Zr, Ti) O 3 , and a ratio of said parasitic capacitance C BL in the data line (BL) to capacitance Prs of said ferroelectric capacitor substantially satisfies the following condition: 0.5 [V -1 ] < (C BL [F] / PrS [C]) < 2. A ferroelectric memory comprising: a memory cell (29) including a transmission gate (33) having a first charge input-and-output port connected to a data line (BL) and a second charge input-and-output port, and a ferroelectric capacitor (31) having a first electrode (31A) connected to said second charge input-and-output port and a second electrode (31B) connected to a driving voltage line (PL0); and driving voltage applying means for applying a driving voltage to said second electrode (31B) of the ferroelectric capacitor (31) through said driving voltage line (PL0) so as to apply successively first and second electric fields having opposite directions to said ferroelectric capacitor (31), characterised in that : precharging means are provided for precharging said data line (BL) to a voltage that is substantially half of a power source voltage; the first electric field sets said second electrode (31B) to a voltage higher than the precharge voltage, and the second electric field sets said second electrode (31B) to a voltage lower than the precharge voltage, such that the polarization of the ferroelectric capacitor (31) is changed from a first value prior to application of the first and second electric fields to a second value following application of the first and second electric fields, the first and second values being sufficiently different to allow data to be read from the memory cell (29) by detecting a difference between the voltage of the data line (BL) and the precharge voltage; and means are provided for reading data from the memory cell (29) by detecting a difference between the voltage of the data line (BL) and the precharge voltage. A ferroelectric memory according to claim 9, further comprising a further memory cell (30) including a further transmission gate (34), the further transmission gate (34) having a first charge input-and-output port connected to a further data line (/BL) wherein said precharging means is arranged to precharge both the data line (BL) and the further data line (/BL) to said precharge voltage, and the data is read from the selected memory cell (29) through a corresponding one of the data line (BL) and the further data line (/BL). A memory according to claim 9 or 10, wherein said driving voltage is set so that a strength of said first electric field is smaller than that of an electric field applied to said ferroelectric capacitor (31) when the data is written, and a strength of said second electric field is smaller than that of said first electric field. A memory according to any of clams 9 to 11, wherein said driving-voltage applying means further comprises means for providing a driving voltage for successively applying third and fourth electric fields having opposite directions, the strengths of said third and fourth electric fields being respectively larger than that of said first and second electric fields applied to said ferroelectric capacitor (31), and polarization of the ferroelectric capacitor (31) being changed according to a variation of said third and fourth electric fields. A memory according to any of claims 9 to 12, wherein said driving-voltage applying means further comprises means for providing a driving voltage which is set so that a reading-out margin when a logic "1" is written in said ferroelectric capacitor (31) is substantially equal to a reading-out margin when a logic "0" is written in said ferroelectric capacitor (31). A memory according to any of claims 9 to 13, wherein said data line (BL) has a parasitic capacitance C BL , the parasitic capacitance C BL being equal to or less than a value for which a voltage difference generated in said data line (BL) when a logic "1" and a logic "0" are read out is substantially maximized. A memory according to claim 14, wherein one of said first and second electric fields is larger than an internal power-supply voltage, and when the data is read out, a voltage generated in said data line (BL) increases as compared with a case where said one is substantially the same as the internal power-supply voltage. A memory according to claim 15, wherein said ferroelectric capacitor includes Pb (Zr, Ti) O 3 , and a ratio of said parasitic capacitance C BL in the data line (BL) to capacitance Prs of said ferroelectric capacitor substantially satisfies the following condition: 0.5 [V -1 ] < (C BL [F] / Prs [C]) < 2 .

Inventors: TAIRA SHIGENOBU, TAKAI KAZUAKI, TAMURA TETSURO, TAIRA, SHIGENOBU, TAKAI, KAZUAKI, TAMURA, TETSURO, Taira, Shigenobu, c/o Fujitsu Ltd, Takai, Kazuaki, c/o Fujitsu Ltd, Tamura, Tetsuro, c/o Fujitsu Ltd
Applicants: FUJITSU LTD, FUJITSU LIMITED
Application year: 1996
Main classification: G11C11
IPC codes: G11C11