CURRENT MEMORY

Abstract: A current memory comprises an input (1) which is connected via a switch (S1) which is closed on a phase phi 1 of a clock signal to inputs of a coarse memory cell (CM) and a fine memory cell (FM). The coarse memory cell samples the input current on phase phi 1a of the clock and outputs a current thereafter. The fine memory cell senses the difference between the input current and the output of the coarse memory (CM) on phase phi 1b of the clock. A switch (S5) which is closed on phase phi 2 of the clock passes the combined outputs of the coarse (CM) and fine (FM) memories to an output (2). A resistor rs is provided having a resistance equal to the "on" resistance of the output switch (S5). This compensates for the voltage drop across the output switch (S5).

Description: DESCRIPTION CURRENT MEMORY The invention relates to an analogue current memory comprising a first, coarse, current memory cell, a second, fine, current memory cell, an input for receiving a current to be stored, an output for delivering the stored current, first switch means for applying the input current to the first current memory cell 0 during a first part of a first portion of a clock cycle, second switch for applying the input current to the second current memory cell during a second part of the first portion of the clock cycle, and third switch means for delivering the combined output currents of the first and second current memory cells to the output of the current memory during a later portion of the clock cycle or during 5 a subsequent clock cycle. Such an analogue current memory is disclosed in EP-A-0608 936 (PHB33830). While this current memory, which is known as S 2 I current memory, gives a better performance than the simple current memory earlier proposed for switched current circuits and shown in Figure 3.4 at page 36 of 0 the book edited by C. Toumazou, J.B. Hughes, and N.C. Battersby entitled "SWITCHED-CURRENTS an analogue technique for digital technology" and published by Peter Peregrinus Limited in 1993, it still does not give an ideal performance. It is an object of the invention to enable the provision of an analogue 5 current memory as set forth in the opening paragraph and as disclosed in EP- A-0608936 which produces a more accurate replica of the input current at its output. The invention provides an analogue current memory as set forth in the opening paragraph; characterised in that resistance means having a resistance o substantially equal to the "on" resistance of the third switch means is coupled between the first and second switch means and the outputs of the first and second current memory cells. The invention is based on the realisation that one of the sources of error in the current memory disclosed in EP-A-0608936 is the "on" resistance of the output switch means, since when the output current passes through it a potential difference will be developed across it due to the finite resistance when the switch is "on". Thus, the nominally equal voltages at the output of a first current memory and the input of a second current memory connected in cascade will differ by the voltage drop across the output switch. This error voltage gives rise to a current transport error due to the finite drain resistances and drain-gate capacitances of the field effect transistors making up the coarse and fine current memory cells. By adding the resistance means this error voltage can be compensated to substantially reduce the current transport error. When the third switch means comprises a field effect transistor whose gate electrode receives a switching signal derived from the clock signal, the resistance means may comprise a further field effect transistor having substantially the same dimensions and being switched on by the same potential as the first mentioned transistor. This enables a resistance value very close to and which accurately tracks that of the "on" resistance of the third switch means. The invention further provides a delay line for analogue currents comprising a plurality of such current memories connected in cascade or parallel. The above and other features and advantages of the invention will become apparent from the following description, by way of example, of embodiments of the invention with reference to the accompanying drawings, in which:- Figure 1 is a circuit diagram of a current memory as disclosed in EP-A-0 608 936, Figure 2 illustrates the source of errors when two current memories as shown in Figure 1 are connected in cascade, Figure 3 is a circuit diagram of an embodiment of a current memory according to the invention, Figure 4 shows the operation of the current memory of Figure 3 on a) input and b) output phases, Figure 5 shows clock waveforms for operating the switch means of the current memories, and Figure 6 shows the schematic form an analogue current delay line according to the invention. As shown in Figure 1 the current memory has an input 1 which is connected via a switch S1 to the junction of the drain electrodes of a p-channel field effect transistor T1 and an n-channel field effect transistor T2. The source electrode of transistor T1 is connected to a supply rail V dd while the source electrode of transistor T2 is connected to a supply rail V ss . The switch S1 is connected to a further switch S2 the other end of which is connected to the gate electrode of transistor T1. The switch S1 is also connected to a further switch S3 whose other side is connected to the gate electrode of transistor T2. An input terminal 3 to which a reference voltage V e is applied, is connected via a switch S4 to the gate electrode of transistor T1. The junction of the drain electrode of transistors T1 and T2 is connected to an output 2 via a switch S5. A capacitor C1 is connected between the source and gate electrodes of transistor T1 , this capacitor C1 may be formed by the gate source channel capacitance of transistor T1. Similarly a capacitor C2 is connected between the gate and source electrodes of transistor T2. The capacitor C2 may be formed by the gate source channel capacitance of transistor T2. Transistor T2, capacitor C2, and switch S3 form a coarse memory CM, while transistor T1 , capacitor C1 , switch S2, and switch S4 form a fine memory FM. The operation of the current memory shown in Figure 1 will be described with the aid of the clock waveforms shown in Figure 5. In this embodiment the memory is arranged to sample the input current during phase φ . of the clock signal and to produce the stored current during phase ø2 of the clock signal. Clearly the current memory cell could sample the input current during phase ø2 of a clock signal and output the stored current during phase ø1 of a later clock signal cycle. It is not essential that the clock timings are as shown, it could be that the input signal is sampled during one clock sample and the output is produced during a later clock cycle not necessarily the next clock cycle. In order to operate the current memory as shown in Figure 1 the clock cycle is split into two phases ø1 and ø2. The first phase ø1 is further subdivided into two sub-phases ø1a and ø1b. Phases ø1 and ø2 are non overlapping while sub-phases ø1a and ø1b are overlapping. There are also phases ø2a and ø2b so that a cascade of current memories can be implemented, two current memories in cascade forming a one clock period delay. In this case the input current to the second current memory is sampled during phase ø2 and under these circumstances phases ø2a and ø2b are required. During phase ø1 switch S1 is closed and the input current applied to input 1 is sampled. During the sub-phase ø1a switches S3 and S4 are closed while switches S2 and S5 are open. Under these circumstances the transistor T1 forms a current source which produces a current J whose current is dependent on the dimensions of the transistor T1 and the bias voltage V e . As switch S3 is closed transistor T2 is configured as a diode and the input current i plus the bias current J produced by transistor T1 is conducted by the transistor T2 and the capacitance C2 is charged via the switch S3. At the end of the phase ø1a the switch S3 opens but the transistor T2 continues to conduct the current J + i because of the charge on the capacitance C2 holding the gate voltage of the transistor T2 at such a level that the current J + i is conducted. In practice the current conducted is not precisely J + i since the transistor is non-ideal in a number of aspects which causes the current stored in the current memory cell CM to differ from that sampled during sub-phase ø1a. Thus the current actually produced by transistor T2 will be J + i + Δi; where Δi is an error current. At the end of sub-phase ø1a the switch S4 also opens and the charge on capacitor C1 will cause the transistor T1 to continue to supply the current J. On phase ø1b transistor T1 becomes configured as a diode and will conduct the current J + Δi and at the end of phase ø1b the charge on capacitor C1 maintains the current through transistor T1 at J + Δi when the switch S2 opens. Thus on phase ø2 when switch S5 opens the total current produced at the junction of the transistors T1 and T2 become substantially equal to i and this current i will be fed to the output 2. At the end of the input phase ø1b the transistor T1 has a nearly fixed drain current which is substantially independent of the signal current i. This is because it only produces the small error current which remains after the transistor T2 in the coarse memory cell has sampled the input current. Thus the signal related portion of the current produced by transistor T1 is Δi which is merely the error from the coarse memory cell CM. The bias current J will be substantially in excess of this error current. Consequently the voltage at the internal node S, that is the junction of the drain electrodes of transistors T1 and T2 is substantially independent of the signal and is approximately equal to the bias voltage V e . A cascade of such memories each has its internal node S at a voltage close to V e at the end of both its input phase, due to its own intemal P memory, and its output phase, due to the P memory of the following cell. This feature enables the memory to reduce substantially the error which results from finite drain resistance and drain gate capacitance in both the transistors T1 and T2. However, the "on" resistance ofthe input and output switches S1 and S5 gives rise to additional errors as is illustrated in Figure 2. Figure 2 illustrates the case where the memory M1 is driving a second memory M2 and illustrates the situation close to the end of the period ø2b. Under these circumstances the switch S5 of memory M1 is closed and also forms the switch S1 of memory M2. The switch has an on resistance of r s . At the end of the ø2b phase the node S of memory M2 is close to the voltage V e . The switch "on" resistance r s develops a voltage drop i 0 r s so that the voltage at the intemal node S of memory M1 becomes V e - i 0 r s This error voltage i 0 r s gives a current transport error due to the finite drain resistances and drain gate capacitances of transistors T1 and T2. This can be reduced by using wide switch transistors to Iower r s but this gives increased capacitances and consequently increased current glitches. Figure 3 is an embodiment of a current memory according to the invention. Elements in Figure 3 corresponding to those in Figure 1 have been given the same reference signs. The essential difference between the current memory cell illustrated in Figure 3 and that shown in Figure 1 is that a resistor having a value r s is connected between the node S and the junction of switches S1 , S2 and S3. The resistance of resistor r s is made equal to that of the "on" resistance of the input and output switches S1 and S5. This can be easily achieved by making it from a transistor with the same dimensions as those of the switches and held on by the same gate voltage as is applied to the switches. Figure 4 illustrates the internal voltages at the end of the input and output phases. In Figure 4a it can be seen that the voltage V e which is present at the gate electrode of transistor T1 is decreased by the value r s x i so that the voltage at node S is V e -ir s . Similarly at the end of phase ø2 the voltage V e from the succeeding stage is dropped by the value i x r s through the closed switch resistance of switch S5 to produce the voltage V e - ir s at the node S. Consequently at each stage the internal node voltage is held at a value V e -ir s and consequently no transport error results from the effect of the resistance r s of the switch S5 when "on". As a result of this modification to the current memory the memory may be designed with small input and output switches, that is switches having a higher "on" resistances r s to reduce the current glitches since smaller switches will have correspondingly smaller parasitic capacitances. This will give greater precision and linearity in both data converters (e.g. as delay cells in pipelined converters) and filters (in sample and hold circuits and delay lines). Figure 6 illustrates how a plurality of current memories as shown in Figure 3 may be used to form a delay line. The delay line has an input 61 which is connected via a switch S60-1 to the input of a first current memory which comprises a coarse memory cell CM-1 and a fine memory cell CF-1. The combined outputs of the memory cells CM-1 and CF-1 is fed via a switch S60-2 to a second current memory which comprises a coarse memory cell CM- 2 and a fine memory cell CF-2. This structure is repeated until the final current memory, which comprises a coarse memory cell CM-n and a fine memory cell CF-n, is reached. The output of the current memory is fed via a switch S60- (n+1) to the output 62 of the delay line. The odd numbered switches 60 are closed when ø2 is high. The coarse memories CM and fine memories CF are of the form described with reference to Figure 3 while an input 63 has the reference voltage V e applied to it. Each current memory is provided with a resistor r s -1 to r s -n whose value is chosen to compensate for the "on" resistance of its output switch. From reading the present disclosure, other modifications will be apparent to persons skilled in the art. Such modifications may involve other features which are already known in the design and use of electrical or electronic circuits and component parts thereof and which may be used instead of or in addition to features already described herein. Although claims have been formulated in this application to particular combinations of features, it should be understood that the scope of the disclosure of the present application also includes any novel feature or any novel combination of features disclosed herein either explicitly or implicitly or any generalisation of one or more of those features which would be obvious to persons skilled in the art, whether or not it relates to the same invention as presently claimed in any claim and whether or not it mitigates any or all of the same technical problems as does the present invention. The applicants hereby give notice that new claims may be formulated to such features and/or combinations of such features during the prosecution of the present application or of any further application derived therefrom.

Claims: CLAIMS 1. An analogue current memory comprising a first, coarse, current memory cell, a second, fine, current memory cell, an input for receiving a current to be stored, an output for delivering the stored current, first switch means for applying the input current to the first current memory cell during a first part of a first part of a first portion of a clock cycle, second switch for applying the input current to the second current memory cell during a second part of the first portion of the clock cycle, and third switch means for delivering the combined output currents of the first and second current memory cells to the output of the current memory during a later portion of the clock cycle or during a subsequent clock cycle; characterised in that resistance means having a resistance substantially equal to the "on" resistance of the third switch means is coupled between the first and second switch means and the outputs of the first and second current memory cells. 2. An analogue current memory as claimed in Claim 1 in which the third switch means comprises a field effect transistor whose gate electrode receives a switching signal derived from the clock signal and the resistance means comprises a further field effect transistor having substantially the same dimensions and being switched on by the same potential as the first mentioned transistor. 3. An analogue current memory substantially as described herein with reference to the accompanying drawings. 4. A delay line for analogue currents comprising a plurality of current memories as claimed in any of Claims 1 to 3 connected in cascade or parallel. 5. A delay line for analogue currents substantially as described herein with reference to the accompanying drawings. 6. Any novel feature or novel combination of features disclosed herein either implicitly or explicitly whether or not it relates to the same invention as that claimed in any preceding claim.

Inventors: HUGHES JOHN BARRY, MOULDING KENNETH WILLIAM, HUGHES, JOHN, BARRY, MOULDING, KENNETH, WILLIAM
Applicants: PHILIPS ELECTRONICS NV, PHILIPS NORDEN AB, PHILIPS ELECTRONICS N.V.
Application year: 1996
Main classification: G11C27
IPC codes: G11C27