Input circuit and semiconductor integrated circuit device including same

Abstract: The disclosed input circuit incorporated in an semiconductor integrated circuit device will not be operated erroneously due to fluctuations of a supply (or reference) potential (V DD ) caused by noise, for instance. The input circuit comprises: a signal input terminal for applying an external input signal (V in ); a first input potential detecting circuit (1) for comparing a potential of the input signal with a predetermined supply (or reference) potential (V DD ) to detect a potential difference between the two; a second input potential detecting circuit (2) activated in response to a control signal (C), for comparing the potential of the input signal (V in ) with the predetermined supply (or reference) potential (V DD ) to detect the potential difference between the two; a delay circuit (3) for delaying an output of the first input potential detecting circuit by a predetermined delay time; a latch circuit (4) for inputting an output signal of the delay circuit as data and an output signal of the second input potential detecting circuit as a clock, to generate an output signal (V out ) according to potentials of these two inputted signals; and a signal output terminal for outputting the output signal of the latch circuit.

Description: BACKGROUND OF THE INVENTION The present invention as defined in the appended claims relates to an input circuit and a semiconductor integrated circuit device including the same input circuit, and more specifically to an input circuit including circuits for detecting the potential of an input signal in order to prevent the input circuit from being operated erroneously due to fluctuations of supply voltage from which a reference voltage is generated. In the semiconductor integrated circuit device, the operating characteristics thereof are subjected to the influence of fluctuations of the supply or reference voltage and temperature to some extent, with the result that there are cases where the integrated circuit device may be operated erroneously. On the other hands, however, the importance of the precision and stability of the supply or reference voltage has increased more and more with the advance of complicated and high speed operation of the integrated circuit device. Fig. 1 is a block diagram showing a prior art input potential detecting circuit incorporated in a semiconductor integrated circuit device. The circuit construction and operation of this input potential detecting circuit shown in Fig. 1 will be described hereinbelow with reference to Figs. 4A, 4C and 4D. In Fig. 1, a supply voltage V DD is applied to the gate of a P-channel MOS transistor 101 as a reference potential. Further, an input signal V in (where [V in ] also expresses the potential value thereof) is applied to any one of the source and drain of the same P-channel MOS transistor 101, and a signal is outputted from the other of the two thereof. Further, any one of the source and drain thereof (from which the signal is outputted) is grounded via a resistance element 102. The signal outputted via the P-channel MOS transistor 101 is outputted through two inverters 103 and 104 as an output signal V out (where [V out ] also expresses the potential value thereof). In the prior art input circuit as shown in Fig. 1, when the potential of the input signal V in is higher than a value of (V DD + |V tp |) which is an addition of the reference voltage V DD and an absolute value |V tp |) of the threshold voltage of the P-channel MOS transistor 101 (during the periods from t 5 to t 7 and from t 15 to t 17 as shown in Fig. 4A), the P-channel MOS transistor 101 is turned on and thereby the input level to the inverter 103 becomes an "H" level (during the periods from t 6 to t 8 and from t 16 to t 18 as shown in Fig. Fig. 4D). As a result, the output signal V out changes to the "H" level. In contrast with this, when the potential of the input signal V in is lower than the addition (V DD + |V tp |), the P-channel MOS transistor 101 is turned off and thereby the input level of the inverter 103 becomes an "L" level. As a result, the output signal V out changes to the "L" level. As the input signal V in , an external signal used as an address signal or a control signal is often used, and the input signal V in is so set as to lie within a range between a ground potential V SS and the reference voltage V DD in the ordinary operation. Further, as already explained, the potential of the input signal V in is compared with the voltage (V DD + |V tp |) by the P-channel MOS transistor 101, and the potential of the output signal V out is determined as being the "H" or "L" level when the input signal V in is higher or lower than the voltage (V DD + |V tp |), respectively. By utilization of the above-mentioned potential change of the input signal V in , it is possible to change the semiconductor integrated circuit device (e.g., memory device) from the ordinary operation status to another status (e.g., an operation test status) or vice versa. In the above-mentioned prior art input potential detecting circuit as described above, however, there exists a following problem: During the ordinary operation of the semiconductor memory device, the potential of the external input signal, that is, the input signal V in of the input circuit shown in Fig. 1 lies within a range between the ground potential V SS and the supply potential V DD , as already explained. In this case, when the potential of the input signal V in is roughly the same as that of the supply potential V DD , and further when the supply potential V DD is lowered due to fluctuations (e.g., noise) and thereby the difference in potential between the input signal V in and the supply potential V DD exceeds the absolute value |V tp | of the threshold value of the P-channel MOS transistor 101 (i.e., V in - V DD ≥ |V tp | )(periods from t 1 to t 3 and from t 11 to t 13 ), the P-channel MOS transistor 101 is turned on erroneously, so that the "H" level potential signal is outputted erroneously as the output signal V out (during the periods from t 2 to t 4 and from t 12 to t 14 as shown in Fig. 4C). In other words, the semiconductor memory device is changed from the ordinary operation status to another status (e.g., the operation test status) erroneously. To overcome this problem, it may be possible to consider a method of increasing the absolute value |V tp | of the threshold voltage of the P-channel MOS transistor 101. In this method, however, when the reference potential V DD is set to a usual potential level or a level higher the usual potential level, the potential of the input signal V in for changing the ordinary status of the memory device to another status (e.g., the test status) must be set to a a very high potential value, thus resulting in another problem in that the characteristics of the transistor deteriorate due to the voltage stress. In addition, a method of reducing resistance of the resistance element 102 connected to the P-channel MOS transistor 101 may be considered to prevent the above-mentioned erroneous operation. In this case, however, since the transistor current increases in the other status (e.g., the test status), there arises the other problem in that the current consumption increases. SUMMARY OF THE INVENTION Accordingly, it is the object of the present invention to provide an input circuit and a semiconductor integrated circuit device including the same input circuit, which are so constructed as not to be operated erroneously even if the supply or reference potential V DD fluctuates due to noise, for instance. According to the first aspect of the present invention, there is provided an input circuit comprising: a signal input terminal for applying an external input signal; a first input potential detecting circuit for comparing a potential of the input signal with a predetermined reference potential to detect a potential difference between the two; a second input potential detecting circuit activated in response to a control signal, for comparing the potential of the input signal with the predetermined reference potential to detect the potential difference between the two; a delay circuit for delaying an output of said first input potential detecting circuit by a predetermined delay time; a latch circuit for inputting an output signal of said delay circuit as data and an output signal of said second input potential detecting circuit as a clock, to generate an output signal according to potentials of these two inputted signals; and a signal output terminal for outputting the output signal of said latch circuit. The input circuit is provided with first and second input potential detecting circuits; an output of the first input potential detecting circuit is inputted to a latch circuit via a delay circuit; the second input potential detecting circuit is controlled by a control signal; and an output of the second potential input detecting circuit is inputted to the same latch circuit. Therefore, even if the supply (reference) potential V DD fluctuates due to noise, for instance and thereby the input circuit operates erroneously as a result of the comparison between the input signal and the reference signal, as far as the control signal inputted to the second input potential detecting circuit is not changed from a specific potential, the output potential of the input circuit can be kept at the status prior to the erroneous operation. Further, the output potential of the input circuit can be changed, by changing the input signal on condition that the control signal is changed from the specific potential. Further, according to the second aspect of the present invention, there is provided an input circuit, comprising: a signal input terminal for applying an external input signal; a first input potential detecting circuit for comparing a potential of the input signal with a predetermined reference potential to detect a potential difference between the two; a second input potential detecting circuit activated in response to a control signal, for comparing the potential of the input signal with the predetermined reference potential to detect the potential difference between the two; a delay latch circuit for delaying an output of said first input potential detecting circuit by a predetermined delay time to obtain a first signal, obtaining an output of said second input potential detecting circuit as a second signal, and generating an output signal thereof in cooperation with the first signal and the second signal; and a signal output terminal for outputting the output signal of said delay latch circuit. The outputs of the first and second input potential detecting circuits are inputted to a delay latch circuit so constructed as to have both the functions of the delay circuit and the latch circuit in combination; only the output of the first input potential detecting circuit is delayed by a predetermined time; and the second input potential detecting circuit is controlled by the control signal. Therefore, in the same way, even if the supply or reference potential V DD fluctuates due to noise, for instance and thereby the input circuit operates erroneously as a result of the comparison between the input signal and the reference signal, as far as the control signal inputted to the second input potential detecting circuit is not changed from a specific potential, the output potential of the input circuit can be kept at the status prior to the erroneous operation. Further, the output potential of the input circuit can be changed, by changing the input signal on condition that the control signal is changed from the specific potential. Further, when the control signal is generated on the basis of the chip-enable signal, the construction of the input circuit can be facilitated. Further, when the control signal is inputted from the outside independently, it is possible to stabilize the input circuit operation more securely. According to third aspect of the present invention, there is provided an input circuit, comprising: a signal input terminal for applying an external input signal; a first input potential detecting circuit for comparing a potential of the input signal with a predetermined reference potential to detect a potential difference between the two; a plurality of second input potential detecting circuits each activated in response to a different control signal respectively, for comparing the potential of the input signal with the predetermined reference potential to detect the potential difference between the two, respectively; a logic circuit for generating an effective output when at least one of outputs of a plurality of said second input potential detecting circuits is effective; a delay circuit for delaying an output of said first input potential detecting circuit by a predetermined delay time; a latch circuit for inputting an output signal of said delay circuit as data and an effective output signal of said logic circuit as a clock, to generate an output signal according to potentials of these two inputted signals; and a signal output terminal for outputting the output signal of said latch circuit. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a circuit diagram showing an example of the prior art input potential detecting circuits; Fig. 2 is a circuit diagram showing a first embodiment of the input circuit according to the present invention, which is formed on a part of a semiconductor integrated circuit device; Fig. 3 is a circuit diagram showing a second embodiment of the input circuit according to the present invention, which is formed on a part of a semiconductor integrated circuit device; Figs. 4A to 4E are waveform diagrams showing the potential changes of the various signals V DD and V out caused by change in potential of the input signal V in and the control signal C; and Fig. 5 is a circuit diagram showing a third embodiment of the input circuit according to the present invention, which is formed on a part of a semiconductor integrated circuit device. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments of the input circuit according to the present invention will be described hereinbelow with reference to the attached drawings. The input circuit is formed on a part of a substrate of a semiconductor integrated circuit device. Fig. 2 is a circuit diagram showing the first embodiment thereof. In Fig. 2, the input circuit is composed of a main input potential detecting circuit 1, a subsidiary input potential detecting circuit 2, a delay circuit 3, and a latch circuit 4. The main input potential detecting circuit 1 includes a P-channel MOS transistor 11, a resistance element 12, and an inverter 13. The P-channel MOS transistor 11 whose gate terminal is supplied with a supply voltage V DD as a reference voltage and the resistance element 12 are connected between a signal input terminal and to and the inverter 13 are connected between a signal input terminal and an output node a1 of the main input potential detecting circuit. The input signal V in is applied to the signal input terminal, and is applied to a gate of the P-channel MOS transistor 11 as a reference potential. Further, the resistance element 12 is connected between an input node of the inverter 13 and a ground potential. The output node a1 of the main input potential detecting circuit 1 is connected to an input node of the delay circuit 3 composed of four series-connected inverters 31, 32, 33 and 34. An output node of the delay circuit 3 is connected to a latch circuit 4 composed of two loop like connected NOR circuits 41 and 42. The two NOR circuits 41 and 42 for constructing the latch circuit 4 have two inputs respectively, and connected in such a way that an output of one NOR circuit is connected to one input of the other NOR circuit mutually. In more detail, an output node c2 of the NOR circuit 42 is connected to one input of the NOR circuit 41, and an output node of the NOR circuit 41 is connected to one input of the NOR circuit 42. Further, an output node of the delay circuit 3 is connected to the other input (data input terminal) of the NOR circuit 41, and an output node b1 of the subsidiary input potential detecting circuit 2 is connected to the other input (clock input terminal) of the NOR circuit 42. The subsidiary input potential detecting circuit 2 includes a P-channel MOS transistor 21, an N-channel MOS transistor 22, a resistance element 23, and an inverter 24. The P-channel MOS transistor 21, the N-channel MOS transistor 22, and the inverter 24 are connected between the signal input terminal and an output node b1 of the subsidiary input potential detecting circuit 2. The input signal V in is applied to the signal input terminal; the supply voltage V DD is applied to a gate of the P-channel MOS transistor 21 as a reference potential; and a control signal C is inputted to a gate of the N-channel MOS transistor 22. Further, the resistance element 23 is connected between an input node of the inverter 24 and the ground potential. As the control signal C applied to the gate of the N-channel MOS transistor 22, a chip enable signal is usually used. Without being limited only thereto, any signal can be used, as far as the control signal C can change the output signal level of the input circuit in cooperation with the input signal V in , in such a way that the ordinary operation status of the integrated circuit device can be changed over to another mode (e.g., a test operation status thereof) or vice versa. For example, the control signal can be supplied from outside of the integrated circuit on which the input circuit is formed. Further, the output node b1 of the subsidiary input potential detecting circuit 2 is connected to one input of the NOR circuit 42, as already explained. Further, the output V out of the input circuit 2 shown in Fig. 2 is the same as the output node of the NOR circuit 41 for constituting the latch circuit 4. The operation of the input circuit 2 shown in Fig. 2 will be described hereinbelow with reference to Figs. 4A to 4C and 4E. At time t 10 in Fig. 4B, when the control signal C applied to the gate of the N-channel MOS transistor 22 changes to the "L" level, since the N-channel MOS transistor 22 is turned off, the potential at the output node b1 of the subsidiary input potential detecting circuit 2 is at the "H" level, irrespective of the potential of the input signal V in , so that the internal node c2 of the latch circuit 4 is at the "L" level. Accordingly, the potential of the output signal of the input circuit shown in Fig. 2 can be determined on the basis of the operation of the main input potential detecting circuit 1. In more detail, when the potential of the input signal is higher than the potential (V DD + |V tp |) (where V tp denotes the threshold voltage of the two P-channel transistors 11 and 21) (during the period from t 15 to t 17 shown in Fig. 4A), since the P-channel MOS transistor 11 is turned on and thereby the input of the inverter 13 changes to the "H" level, the potential at the output node a1 of the main input potential detecting circuit 1 is at the "L" level, so that the potential of the output signal V out of the input circuit shown in Fig. 2 is at the "H" level (during the period from t 16 ' to t 18 ' in Fig. 4E). On the other hand, when the potential of the input signal V in becomes lower than the potential (V DD + |V tp |), since the P-channel MOS transistor 11 is turned off and thereby the input of the inverter 13 changes to the "L" level, the potential at the output node a1 of the main input potential detecting circuit 1 is at the "H" level, so that the potential of the output signal V out of the input circuit shown in Fig. 2 is at the "L" level. Further, when the supply or reference potential V DD is lowered due to noise, for instance on condition that the input potential V in is at roughly the same level as the supply or reference potential V DD , since the potential difference between the input signal V in and the supply potential V DD becomes higher than the absolute value |V tp | of the threshold voltage of the P-channel MOS transistor 11 (V in - V DD ≥ |V tp |) (during the period between t 11 and t 13 as shown in Fig. 4C), the P-channel MOS transistor 11 is turned on erroneously, with the result that the "H" level output signal develops (during the period from t 12 ' to t 14 ' shown in Fig. 4E) as the output signal V out of the input circuit shown in Fig. 2. Further, when the control signal "C" is at the "H" level (prior to time t 10 shown in Fig. 4C), the N-channel MOS transistor 22 is turned on. Under these conditions, when the potential of the input signal V in becomes lower than (V DD + |v tp |), since the two MOS transistors 11 and 12 are both turned off, both the inputs to the two inverters 13 and 24 are both at the "L" level, so that the two output nodes a1 and b1 of the main and subsidiary input potential detecting circuits 1 and 2 are both at the "H" level. As a result, the internal node c2 of the latch circuit 4 is at the "L" level, so that the potential of the output signal V out of the input circuit shown in Fig. 2 changes to the "L" level. Further, when the potential of the input signal V in changes from a level lower than (V DD + |V tp |) to a high level at time t 5 in Fig. 4A, since the two MOS transistors 11 and 12 are both turned on, both the inputs of the two inverters 13 and 24 are both at the "H" level, so that the two output nodes a1 and b1 of the main and subsidiary input potential detecting circuits 1 and 2 are both at the "L" level. Here, since being supplied to the latch circuit 4 via the delay circuit 3, the output signal (the potential at the node al) of the main input potential detecting circuit 1 is inputted to the latch circuit 4, after the output signal (the potential at the node b1) of the subsidiary input potential detecting circuit 2 has been supplied to the latch circuit 4. Consequently, at the time point when the "L" level output signal of the subsidiary input potential detecting circuit 2 is inputted to the latch circuit 4, since the output signal V out of the input circuit shown in Fig. 2 is still kept at the "L" level (the same as the output potential obtained where the potential of the input signal V in is lower than (V DD + |V tp |), the internal node c2 of the latch circuit 4 is at the "H" level. As a result, the output signal V out of the input circuit shown in Fig. 2 is kept at the "L" level, irrespective of the output signal level of the main input potential detecting circuit 1. Further, in the circuit construction of the first embodiment shown in Fig. 2, on condition that the control signal C is at the "H" level and further the potential of the input signal V in is fixed at the potential lower than the (V DD + |V tp |), in case the supply potential V DD is lowered due to the noise fluctuations, for instance and thereby the potential difference between the input signal V in and the supply potential V DD exceeds the threshold voltage |V tp | of the P-channel MOS transistors 11 and 12 (V in - V DD ≥ |V tp |), the P-channel MOS transistors 11 and 12 are both turned on erroneously. In this case, however, the potential of the output signal V out of the input circuit can be kept at the "L" level. As described above, in the first embodiment, it is possible to prevent the erroneous operation of the input circuit, even if any one of the input signal V in and the supply or reference potential V DD fluctuates. In other words, in the case where when the semiconductor integrated circuit device (e.g., a memory device) is set to the ordinary operation status when the potential of the output signal V out thereof is at the "L" level but set to another status (e.g., an operation test status) when at the "H" level, even if the supply or reference potential V DD fluctuates due to noise, for instance, it is possible to prevent the semiconductor integrated circuit device from being shifted erroneously from the ordinary operation status to another status (e.g., the operation test status). Fig. 3 is a circuit diagram showing the second embodiment of the input circuit according to the present invention formed in a substrate of the semiconductor integrated circuit device. The input circuit shown in Fig. 3 is composed of a main input potential detecting circuit 5, a subsidiary input potential detecting circuit 6, and a delay latch circuit 7. The main input potential detecting circuit 5 includes a P-channel MOS transistor 51, a resistance element 52, and an N-channel MOS transistor 53. The P-channel MOS transistor 51 is connected between a signal input terminal and an output node a2 of the main input potential detecting circuit 5. The input signal V in is applied to a signal input terminal; a supply voltage V DD is applied to a gate of the P-channel MOS transistor 51 as a reference potential. Further, the resistance element 52 is connected between an output node a2 of the main input potential detecting circuit 5 and a ground potential. Further, the N-channel MOS transistor 53 is connected between the output node a2 of the main input potential detecting circuit 5 and the ground potential, in order to discharge the potential at the output node a2. A signal described later is supplied to a gate of this N-channel MOS transistor 53. The subsidiary input potential detecting circuit 6 includes a P-channel MOS transistor 61, an N-channel MOS transistor 62, a resistance element 63, and an inverter 64. The input signal V in is applied to the signal input terminal; the supply voltage V DD is applied to a gate of the P-channel MOS transistor 61 as a reference potential; and a control signal C is applied to a gate of the N-channel MOS transistor 62. Further, the resistance element 63 is connected between an input node of the inverter 64 and the ground potential. The output node b2 of the subsidiary input potential detecting circuit 6 is connected to one of two inputs of a NOR circuit 76, as described later. The delay latch circuit 7 includes three NAND circuits 71, 73 and 75, three NOR circuits 72, 74 and 76, and two inverters 77 and 78 in combination. These three NAND circuit 71, 73 and 75 and NOR circuits 72, 74 and 76 are all of two-input type. The output node a2 of the main input potential detecting circuit 5 is connected to one input of the NAND circuit 71; the output of the NAND circuit 71 is connected to one input of the NOR circuit 72; the output of the NOR circuit 72 is connected to one input of the NAND circuit 73; the output of the NAND circuit 73 is connected to one input of the NOR circuit 74; the output of the NOR circuit 74 is connected to one input of the NAND circuit 75; and the output of the NAND circuit 75 is connected to an input of the inverter 77, respectively. These three NAND circuit 71, 73 and 75, two NOR circuits 72 and 74, and the inverter 77 construct a delay circuit section. The output node b2 of the subsidiary input potential detecting circuit 6 is connected to one input of the NOR circuit 76; an output of the inverter 77 is connected to the other input of the NOR circuit 76; and an output of the NOR circuit 76 is connected to a gate of the N-channel MOS transistor 53 and the other inputs of the two NOR circuits 72 and 74, respectively. Further, the output of the NOR circuit 76 is connected to the other inputs of the three NAND circuits 71, 73 and 75 via an inverter 78, respectively. Accordingly, the NAND circuit 75, the inverter 77, the NOR circuit 76, and the inverter 78 are all connected circularly in a loop manner so as to construct a latch circuit section. Further, the output V out of the input circuit shown in Fig. 3 is an output of the inverter 77 for constituting the delay latch circuit 7. The second embodiment shown in Fig. 3 is basically the same in construction as that of the first embodiment shown in Fig. 2. In this second embodiment, however, the main input potential detecting circuit 5 is additionally provided with the N-channel MOS transistor 53 to discharge the potential at the output node a2; the two outputs of the main and subsidiary input potential detecting circuits 5 and 6 are both supplied to the delay latch circuit 7, respectively; and the output of the delay latch circuit 7 is the output signal V out of the input circuit 2 shown in Fig. 3. In addition, the potential of the output signal V out decided on the basis of the potentials of the input signal V in and the control signals C are quite the same as with the case of the first embodiment shown in Fig. 2. The operation of the input circuit shown in Fig. 3 will be described hereinbelow. When the control signal C inputted to the gate of the N-channel MOS transistor 62 is at the "L" level (after time t 10 shown in Fig. 4B), since the N-Channel MOS transistor 62 is turned off, the potential at the output node b2 of the subsidiary input potential detecting circuit 6 is at the "H" level, irrespective of the potential of the input signal V in , so that the potential at the node c2 is at the "L" level and the potential at the node d2 is at the "H" level. Accordingly, the potential of the output signal V out of the input circuit shown in Fig. 3 can be decided on the basis of the potential at the output node a2 of the main input potential detecting circuit 5. In more detail, when the potential of the input signal V in is lower than the potential (V DD + |V tp |), the potential at the output node a2 is at the "L" level, so that the potential of the output signal V out of the input circuit is at the "L" level. Further, when the potential of the input signal V in is higher than the potential (V DD + |V tp |) (during the period from t 15 to t 17 shown in Fig. 4A), the potential at the output node a2 of the main input potential detecting circuit 5 is at the "H" level, so that the potential of the output signal V out of the input circuit shown in Fig. 3 is at the "H" level (during the period from t 16 ' to t 18 ' shown in Fig. 4E). Further, when the supply potential V DD is lowered in such a way as to satisfy the relationship between (V in - V DD ≥ ·|V tp |) (during the period from t 11 to t 13 shown in Fig. 4C), since the P-channel MOS transistor 51 operates erroneously, the "H" level signal develops at the output V out (during the period from t 12 ' to t 14 ' shown in Fig. 4E). Here, however, when the potential of the control signal C is at the "H" level, the N-channel MOS transistor 62 is turned on. In this case, if the input signal V in is lower than (V DD + |V tp |), since the potential at the output node b2 of the subsidiary input potential detecting circuit 6 is at the "H" level, the potential at the node c2 is at the "L" level and the potential at the node d2 is at the "H" level. Here, since the potential at the output node a2 of the main input potential detecting circuit 5 is at the "L" level, the potential of the output signal V out is at the "L" level. Further, when the potential of the input signal V in changes from a potential lower than (V DD + |V tp |) (at this time, the output signal V out is at the "L" level) to a high potential level, the output node b2 of the subsidiary input potential detecting circuit 6 is at the "L" level, and the output node a2 of the main input potential detecting circuit 5 is at the "H" level. Therefore, although the potential of the output signal V out is changed to the "H" level, since this level-change time is later than the time when the potential at the node b2 changes to the "L" level, the potential of the output signal V out is still kept at the "L" level at the time when the potential at the node b2 changes to the "L" level. Therefore, at this time, since the potential at the node c2 changes to the "H" level and thereby the N-channel MOS transistor 53 is turned on, so that the potential at the node a2 is discharged through the transistor 53 from the "H" level to the "L" level. Further, since the node c2 changes to the "H" level, the potential at the node d2 changes to the "L" level. As a result, the output signal V out of the input circuit shown in Fig. 3 is held at the "L" potential level, irrespective of the detection status of the main input potential detecting circuit 5. In other words, even if the supply potential V DD is lowered due to fluctuations by noise and thereby the potential difference between the input signal V in and the supply potential V DD becomes higher than the threshold voltage |V cp | (V in - V DD ≥ |V tp |); that is, even when the P-channel MOS transistors 51 and 61 are both turned on erroneously, it is possible to keep the potential of the output signal V out at the "L" level as it is. As described above, when the control signal C is at the "L" level, in case the input signal V in or the supply or reference potential V DD fluctuates, the erroneous operation signal develops as the output signal V out . However, when the control signal C is at the "H" level, in case the input signal V in or the supply or reference potential V DD fluctuates, the erroneous operation signal will not develop at the signal output terminal as the output signal V out , so that it is possible to prevent the succeeding stage circuits responsive to the output signal V out from being operated erroneously. Fig. 5 is a circuit diagram showing a third embodiment of the input circuit according to the present invention. In this third embodiment, two subsidiary input potential detecting circuits each the same as with the case of the first embodiment shown in Fig. 2 are provided. In Fig. 5, the same reference numerals have been retained for the similar circuit elements which have the same functions as with the case of the first embodiment, without repeating the similar description. In Fig. 5, the subsidiary input potential detecting circuit 2-1 is quite the same as the subsidiary input potential detecting circuit 2 shown in Fig. 2, and further the subsidiary input potential detecting circuit 2-2 is composed of the similar circuit elements 25 to 28 corresponding to the circuit elements 21 to 24 of the subsidiary input potential detecting circuit 2-1. Although the circuit construction is quite the same in both, the control signal C' applied to the gate of the N-channel MOS transistor 26 is different from the control signal C applied to the gate of the N-channel MOS transistor 22. The output of the subsidiary circuit 2-1 and the output of the subsidiary circuit 2-2 are both supplied to a NOR circuit 81. The output of this NOR circuit 81 is inverted by an inverter 82, and further the inverted output at a node C1 is given to one input of the NOR circuit 42 of the latch circuit 4. In the first embodiment shown in Fig. 2, when the control signal is at the "H" level, even if the input signal V in becomes higher than (V DD + |V tp |), the potential at the output terminal V out is kept at the "L" level. In this third embodiment shown in Fig. 5, as far as any one of the two control signals C and C' is at the "L" level, since the node C1 changes to the "H" level irrespective of the potential of the input signal V in through the NOR circuit 81 and the inverter 82, the potential value of the output terminal V out can be decided on the basis of the output signal of the main input potential detecting circuit 1. In other words, when the potential of the input signal V in becomes higher than (V DD + |V tp |), the output signal V out changes from the "L" level to the "H" level. Consequently, it is possible to switch the mode (output levels) of the input circuit according to the potential of the input signal V in by controlling the control signal C', irrespective of the control signal C. It is preferable that the input circuits described above are formed on a substrate with circuits which are supplied signals outputted therefrom to constitute semiconductor integrated circuits.

Claims: An input circuit, comprising: a signal input terminal for applying an external input signal (V in ); a first input potential detecting circuit (1) for comparing a potential of the input signal with a predetermined reference potential to detect a potential difference between the two; a second input potential detecting circuit (2) (C) activated in response to a control signal, for comparing the potential of the input signal with the predetermined reference potential to detect the potential difference between the two; a delay circuit (3) for delaying an output of said first input potential detecting circuit by a predetermined delay time; a latch circuit (4) for inputting an output signal of said delay circuit as data and an output signal of said second input potential detecting circuit as a clock, to generate an output signal according to potentials of these two inputted signals; and a signal output terminal for outputting the output signal (V OUT ) of said latch circuit. The input circuit according to claim 1, wherein: said first input potential detecting circuit (1) comprises: a first first-conductivity type transistor (11), the predetermined reference potential being inputted to a gate thereof, the input signal being applied to one of a source and a drain thereof, and the other of the source and the drain thereof being connected to a supply potential via a first resistance element (12) and used as an output end thereof; and said second input potential detecting circuit (2) comprises: a second first-conductivity type transistor (21), the predetermined reference potential being inputted to a gate thereof, and the input signal being applied to one of a source and a drain thereof; and a second-conductivity type transistor (22), the control signal being inputted to a gate thereof, one of a source and a drain thereof being connected to the other of the source and the drain of said second first-conductivity type transistor, and the other of the source and the drain thereof being connected to the supply potential via a second resistance element (23) and used as an output end thereof. The input circuit according to claim 1, wherein said delay circuit is composed of an even number of inverters (31-34) connected in series. The input circuit according to claim 1, wherein the control signal is a chip enable signal or a signal derived from the chip enable signal. The input circuit according to claim 1, wherein the control signal is a signal supplied from the outside independently. A semiconductor integrated circuit including circuit according to claim 1, wherein said input circuit and circuits to which a signal outputted from the input circuit is supplied. An input circuit, comprising: a signal input terminal for applying an external input signal (V IN ); a first input potential detecting circuit (5) for comparing a potential of the input signal with a predetermined reference potential to detect a potential difference between the two; a second input potential detecting circuit (6) activated in response to a control signal (C), for comparing the potential of the input signal with the predetermined reference potential to detect the potential difference between the two; a delay latch circuit (7) for delaying an output of said first input potential detecting circuit by a predetermined delay time to obtain a first signal, obtaining an output of said second input potential detecting circuit as a second signal, and generating an output signal thereof in cooperation with the first signal and the second signal; and a signal output terminal for outputting the output signal (V OUT ) of said delay latch circuit. The input circuit according to claim 7, wherein: said first input potential detecting circuit (5) comprises: a first first-conductivity type transistor (51), the predetermined reference potential being inputted to a gate thereof, the input signal being applied to one of a source and a drain thereof, and the other of the source and the drain thereof being connected to a supply potential via a first resistance element (52) and used as an output end thereof; and said second input potential detecting circuit comprises: a second first-conductivity type transistor (61), the predetermined reference potential being applied to a gate thereof, and the input signal being applied to one of a source and a drain thereof; and a second-conductivity type transistor (62), the control signal being inputted to a gate thereof, one of a source and a drain thereof being connected to the other of the source and the drain of said second first-conductivity type transistor (61), and the other of the source and the drain thereof being connected to the supply potential via a second resistance element (63) and used as an output end thereof. The input circuit according to claim 7, wherein said delay latch circuit (7) comprises: a gate assembly composed of a plurality of gate stages (71-75) each having logical inversion function, an output of said first input potential detecting circuit being applied to a first stage thereof; and at least two gates circularly connected to a final stage of said gate assembly and each having a logical inversion function. The input circuit according to claim 9, wherein each of said gates having the logical inversion function, respectively is selected from the group consisting of NOR circuit, NAND circuit, and inverter circuit. The input circuit according to claim 9, which further comprises a transistor connected to an output node of said first input potential detecting circuit, a gate thereof being controlled by an output of said two circularly connected gates. The input circuit according to claim 7, wherein the control signal is a chip enable signal or a signal derived from the chip enable signal. The input circuit of claim 7, wherein the control signal is a signal inputted from the outside independently. A semiconductor integrated circuit including circuit according to claim 7, wherein said input circuit and circuits to which a signal outputted from the input circuit is supplied. An input circuit, comprising: a signal input terminal for applying an external input signal (V in ); a first input potential detecting circuit (1) for comparing a potential of the input signal with a predetermined reference potential to detect a potential difference between the two; a plurality of second input potential detecting circuits (2-1, 2-2) each activated in response to a different control signal respectively, for comparing the potential of the input signal with the predetermined reference potential to detect the potential difference between the two, respectively; a logic circuit (81, 82) for generating an effective output when at least one of outputs of a plurality of said second input potential detecting circuits is effective; a delay circuit (3) for delaying an output of said first input potential detecting circuit by a predetermined delay time; a latch circuit (4) for inputting an output signal of said delay circuit as data and an effective output signal of said logic circuit as a clock, to generate an output signal according to potentials of these two inputted signals; and a signal output terminal for outputting the output signal (V out ) of said latch circuit. A semiconductor integrated circuit including circuit according to claim 15, wherein said input circuit and circuits to which a signal outputted from the input circuit is supplied.

Inventors: NAKAJIMA TAKAO, NAKAMURA KENICHI, NAKAJIMA, TAKAO, NAKAMURA, KENICHI
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1996
Main classification: H03K19
IPC codes: G01R19, H03K17