Data input/output managing device, particularly for a non-volatile memory

Abstract: A data input/output managing device, particularly for non-volatile memories that comprise at least one matrix of memory cells, which has the particularity that it comprises: at least one bidirectional internal bus (1) for the transfer of data from and to the memory; a redundancy management line (2) that is associated with the internal bus (1); means (8) for enabling/disabling the transmission, over the internal bus (1), of the data from the memory toward the outside; means (11) for enabling/disabling access to the internal bus on the part of data whose source is other than the memory matrix, for transmission to the memory matrix; and means (5, 12, 13) for enabling/disabling the connection between the outside of the memory and the redundancy line (2) during the reading of the memory matrix and during its programming.

Description: The present invention relates to a data input/output managing device, particularly for a non-volatile memory. It is known that in non-volatile memories the data can originate from the memory to be read outside it or can originate from the outside to be written in the memory; in this case, they follow the reverse path. The read step and the programming step are therefore usually performed by using data transfer paths that are unidirectional and are therefore strictly dedicated to one step or the other. This separation of the reading and programming paths entails the use of several specifically provided lines that branch from the output terminals of the memory toward said memory and from the memory toward the output terminals. In order to perform transfers of data whose source or destination is not the memory matrix, it is necessary to implement additional data transmission lines that add to the existing programming and reading lines. The need for these additional lines arises for example in implementing the redundancy function, by virtue of which a column (or line) of the memory matrix that is found to be defective is replaced, i.e., made redundant, by means of an appropriate alternative line, on which the data item that would have otherwise been sent to or from the defective line is sent. In this manner it is possible to obviate the presence of lines having defective memory cells that would not ensure correct storage of the data and their subsequent retrieval. All the above-mentioned transmission lines therefore entail considerable space occupation. If a memory architecture that entails placement of the output terminals adjacent or in any case near to the memory circuits is used, these lines have a rather limited length, although even so they still occupy a considerable area. If instead the memory matrix has bit lines that are not connected in an adjacent manner but in a manner that is distributed along the transverse extension of the memory, which is advantageously organized into two half-matrices, duplication of the input and output paths toward and from the memory matrix that has thus been split in two entails the drawback of doubling the area occupied by the lines as well as an extremely complicated architecture for said memory. Indeed, in the case of a split 16-bit memory matrix, i.e., with words formed by 16 bits, with transmission structures that are arranged transversely with respect to the arrangement of the terminals, sixteen output terminals are required. Two lines, one for reading the data of the matrix and one for programming it, branch out of each output terminal; furthermore, a line dedicated to redundancy management branches out of each terminal. Moreover, a line dedicated to DMA (Direct Memory Access), i.e., to direct access to the memory matrix by the outside world, for checking the correct operation of each individual cell, branches out of each output terminal. Therefore, on the whole, there are four transmission lines for each terminal, and this obviously entails a highly complex memory architecture. IEEE JOURNAL OF SOLID-STATE CIRCUITS, vol. 27, no. 11, 1 November 1992, pages 1525-1531, XP000320438 AKIRA TANABE ET AL: 'A 30-NS 64 MB DRAM WITH BUILT-IN SELF-TEST AND SELF-REPAIR FUNCTION' discloses a DRAM with built-in self test and self-repair functions with a bidirectional internal bus, but does not disclose a single bidirectional bus for transferring data to and from the memory matrix, and a redundancy management line associated with the bus, with a lower number of required internal data transmission lines. The aim of the present invention is therefore to provide a data input/output managing device, particularly for a non-volatile memory, that allows to improve the organization of the paths for the transmission of data to and from the memory matrix. Within the scope of this aim, an object of the present invention is to provide a data input/output managing device, particularly for a non-volatile memory, that allows to drastically reduce the data transmission lines required for the memory, concentrating their information on "single points", thus simplifying their architecture. Another object of the present invention is to provide a data input/output managing device, particularly for non-volatile memories, that allows to manage x8 or x16 parallelism of the memory. Another object of the present invention is to provide a data input/output managing device, particularly for non-volatile memories, that is capable of managing redundancy for the memory. Another object of the present invention is to provide a data input/output managing device, particularly for non-volatile memories, that allows to provide direct memory access. Another object of the present invention is to provide a data input/output managing device, particularly for non-volatile memories, that is highly reliable and relatively easy to produce at competitive costs. This aim, these objects, and others which will become apparent hereinafter are achieved by a data input/output managing device, as defined in the appended claims. Further characteristics and advantages of the invention will become apparent from the description of a preferred but not exclusive embodiment of the device according to the invention, illustrated only by way of non-limitative example in the accompanying drawings, wherein: figure 1 is a block diagram of the data input/output managing device according to the invention; and figure 2 is a circuit diagram of the input/output managing device shown in figure 1. With reference to the above figures, the device according to the invention comprises a bidirectional internal data bus, split into two buses 1 L and 1 H , where the suffixes L and H relate respectively to the half-word referenced as L and to the half-word referenced as H. The internal bus 1 (where 1 references hereinafter the set constituted by the two buses 1 L and 1 H ) is dedicated to the transfer of the data to and from the memory matrix, which is not shown in the figures. A data line 2 for the transmission of the redundancy data is associated with the internal bus 1. The bus 1 L is connected to corresponding output buffers 3 L and from there to output terminals 4 L . The output buffers 3 L also comprise structures of the tristate type that notoriously interface with the outside. The output terminals 4 L are data input/output (I/O) means that are adapted to allow the output of data from the memory (during reading) and the input of data into the memory (during programming). In view of the symmetry of the architecture of the device for the internal bus 1 L and 1 H , hereinafter, to avoid redundancy in the description, the architecture of the device according to the invention will be described hereinafter with reference to the portion of the device that is referenced as L. Every remark made regarding this part should be understood as being applicable to the symmetrical part H. The output terminals 4 L and the output buffers 3 L are actually eight output terminals and eight output buffers, since the memory device being considered is of the 16-bit type, i.e., with words (bytes) that are 16 bits long; therefore, there is an output buffer and an output terminal for each bit. Likewise, the internal bus 1 L is constituted by eight lines (eight lines for the internal bus 1 H as well). The connecting paths between the internal bus 1 L , the output buffer 3 L , and the output terminal 4 L (these paths are always buses) are as follows. There is a path for direct connection between the internal bus 1 L and the output terminal 4 L that is managed by means for enabling/disabling the direct connection between the internal bus 1 L and the output terminals 4 L . Said means are advantageously constituted by switches 5 L and 6 L . Said path is bidirectional and branches in input to programming enabling means 7 L that are adapted to program the memory device, and thus to send data on the internal bus 1 L in the opposite direction with respect to the normal stream of data provided for reading. The programming means 7 L actually include eight programming enabling means, as in the case of the output buffers 3 L and of the output terminals 4 L . The programming enabling means 7 L comprise structures of the bidirectional type, such as for example pairs of CMOS pass transistors. The path for direct connection between the internal bus 1 L and the output buffer 3 L is also managed by means for enabling/disabling direct connection of the data from the internal bus 1 L to the buffer 3 L . Said enabling/disabling means are advantageously constituted by a switch 8 L . In the position shown in figure 1, the switch 8 L enables the connecting path between the internal bus 1 L and the output buffer 3 L to read the data that arrive from the memory. Means for enabling/disabling the management of x16 or x8 parallelism are advantageously constituted by an additional switch 9 (in this case, the switch 9 is shared by the two portions L and H of the device), which enables the management of x16 or x8 data reading parallelism, receiving in input a line 10 that is dedicated to parallelism management. Hereinafter, said line is referenced as WORD/BYTE line. In the position shown in figure 1 for the switch 9, x16 parallelism management is enabled, whereas management of x8 parallelism of the memory would be enabled in the other position. The output of the programming means 7 L is constituted by the data to be programmed in the memory and is sent to the path for connection to the internal bus 1 L by virtue of means for enabling/disabling access on the part of the outside world to the internal bus 1 L and therefore to the memory. Said means are advantageously constituted by a switch 11 L that receives in input a programming signal that is carried by the line PG. The output buffer 3 L receives in input a signal for enabling said buffer, which is carried by a line referenced as LOAD-L. Likewise, the output buffer 3 H receives in input an enabling signal that is carried by a line LOAD-H. A direct memory access signal, carried by a line DMA, drives the switch 6 L and redundancy structures that will be described hereinafter. A signal for disabling the programming means 7 L , carried by a line DIdis, is fed in input to said programming means 7 L . Column redundancy management means are constituted by logic means that comprise the AND logic gates 12 L , 13 L , and 14. In detail, the AND logic gate 12 L receives in input a column redundancy signal for the half-matrix L, REDL, which also drives the switch 8 L , and the signal PG. The output of the AND gate 12 L drives a switch 15 L that is adapted to carry the data on the redundancy line 2 if a redundancy event occurs. The AND logic gate 13 L instead receives in input the signal DMA and the signal REDL and its output drives the opening or closing of the switch 5 L . The AND logic gate 14 instead receives in input a no-redundancy signal REDdn (which is high in case of no redundancy and low otherwise) and the programming signal PG to drive a switch 16 that is adapted to connect the redundancy line 2 to the ground, in case of no redundancy, or to remain open in case of redundancy exclusively during programming. With reference to figure 2, which shows in detail the circuits of the architecture of the input/output managing device shown in figure 1, the individual elements of the above-described architecture are analyzed from the circuital point of view. In the two figures, identical reference numerals designate identical elements. As in the case of figure 1, only the lower portion of the circuit, which corresponds to the half-word L, is described; any remark made for this half-word must be understood as being valid for the circuital part related to the other half-word H as well. The individual elements that constitute the circuits of the portion of the half-word H and of the half-word L are designated by the same reference numerals, for the sake of simplicity, without the suffixes H or L. The switch 9 for managing x8 or x16 parallelism includes two pairs of CMOS pass transistors 23 and 24, each of which comprises a P-type transistor and an N-type transistor. The signal WORD/BYTE is sent to the gate terminal of the P-type transistor of the pair of pass transistors 23 and to the gate terminal of the N-type transistor of the pair of pass transistors 24. The signal WORD/BYTE, inverted by means of the inverter 25, is instead fed to the gate terminals of the N-type transistor of the pair of pass transistors 23 and of the P-type transistor of the pair of pass transistors 24. The signal WORD/BYTE performs the byte/word data configuration function. The pairs of pass transistors 23 and 24 are furthermore connected to the output buffers 3 H and 3 L respectively. The circuit referenced by 21 L corresponds to the switch 15 L and to the AND logic gate 12 L . Said circuit comprises two N-type transistors 26 and 27 that are connected as shown in the figure. The programming signal PG is sent to the gate terminal of the transistor 26. Said signal performs the function of forcing the wire 1 L to zero in case of redundancy during programming. The source terminal of the transistor 26 is connected to the line 1 L , whereas the drain terminal of the transistor 27 is connected to the ground. The gate terminal of the transistor 27 is instead connected to the gate terminals of pairs of pass transistors 28 and 29 that belong to the block designated by the reference numeral 8 L . Said circuit block corresponds to the switch 8 L . The pairs of pass transistors 28 and 29 are constituted respectively by two transistors, respectively of the P type and of the N type. The signal REDLn (the inverted redundancy signal) is sent to the gate terminal of the N-type transistor of the pair of pass transistors 28 and to the gate terminal of the P-type transistor of the pair of pass transistors 29. The pairs of pass transistors 28 and 29 are connected respectively to the line 1 L and to the line that connects the redundancy line 2 and the programming means 7 L . Said connecting line is in turn connected, by means of the wire 30, to the line 1 L . The wire 30 performs the function of rerouting the data path in case of redundancy both during programming and during reading (but hot during DMA). The switch 11 L , adapted to enable the closure of the programming path toward the line 1 L (or the line 2 upon redundancy), comprises a pair of pass transistors 11 L that is constituted by an N-type transistor and by a P-type transistor. The programming signal PG is sent to the gate terminal of the N-type transistor, whereas the inverted programming signal PGn is sent to the gate terminal of the P-type transistor of the pair of pass transistors 11 L . The programming means 7 L comprise a logic gate 31, whose output is sent through two cascade-connected inverters 32 and 33 to the redundancy line 2 or to the line 1 L over the wire 30, depending on the conditions. The inputs of the logic gate 31, which is advantageously constituted by a NOR gate, are the signal DIdis for disabling the programming means and the signal that arrives from the input/output means 4 L that carries the data to be programmed. The switch 16 and the logic gate 14 of figure 1 are generally shown in the circuit 20 of figure 2, which comprises two N-type transistors 34 and 35. The drain terminal of the transistor 34 is connected to the redundancy line and the source terminal of said transistor 34 is connected to the drain terminal of the transistor 35. The source terminal of the transistor 35 is connected to the ground. Its object is to force the redundancy line 2 to the ground when there is no redundancy during programming. The programming signal PG is sent to the gate terminal of the transistor 34, whereas the no-redundancy signal REDdn is sent to the gate terminal of the transistor 35. The switch 5 L , the logic gate 13 L , and the switch 6 L are generally shown by the circuit 22 L of figure 2. Said circuit comprises two transistors 36 and 37 of the N type that are adapted to enable the path for direct access to the memory (therefore with the switch 6 L closed and with the switch 5 L in the position shown in figure 1) or to enable the path for direct access to the redundancy line 2 if the data item to be read is subjected to redundancy. The circuit 22 L also comprises two pairs of pass transistors 38 and 39, each of which is constituted by two transistors, one of the N type and one of the P type. The inverted DMA signal (DMAn) for direct memory access is sent to the gate terminals of the two P-type transistors of the pairs of pass transistors 38 and 39. The signal DMA for direct memory access is instead sent to the gate terminals of the two N-type transistors of the pairs of pass transistors 38 and 39. The circuit 22 L is completed by two additional N-type transistors 40 and 42, whose gate terminals receive the inverted direct memory access signal DMAn. The source terminals of said transistors are connected to the ground. The drain terminal of the transistor 40 is connected to the gate terminal of the transistor 36, whereas the drain terminal of the transistor 42 is connected to the gate terminal of the transistor 37. The inverted redundancy signal REDLn is sent to the pass transistor 38 and the redundancy signal REDL is sent to the pass transistor 39. With reference to the above figures, the operation of the device according to the invention is as follows. The device according to the invention, in the configuration shown in figure 1, is in the condition for normal reading from the memory matrix in the word mode. The path followed by the data of the matrix lies along the internal bus 1 up to the I/O means 4 i (where i=L, H). For the sake of simplicity in description, only operation as regards the memory half-word L is described. In this situation for the normal reading of the memory matrix, the switches 8 L and 9 are in the condition shown in figure 1. The redundancy path, the programming path, and x8 parallelism management are disabled. In the absence of redundancy and programming, the no-redundancy signal REDdn is high and the programming signal is low; therefore, the switch 16 is open and the redundancy line is not connected to the ground and is thus left free. If the programming signal goes high, indicating a programming request, it is necessary to enable the reverse path for the data (with respect to reading from the memory matrix), i.e., from the I/O means 4 L to the internal bus 1 L and then to the matrix. When PG is high, and in the absence of redundancy (REDL=0, REDLn=1, and REDdn=0), both P-type and N-type transistors of the pair of pass transistors 11 L constitute short circuits: therefore, the switch designated again by 11 L in figure 1 is closed, allowing the data to pass from the programming means 7 L to the internal bus 1 L . In this case, the switch 8 L is in the position shown in figure 1, since we are dealing with the case of programming in the absence of redundancy. When PG is high and in the absence of redundancy, the switch 16 is closed and the redundancy line 2 is forced to the ground, in order to avoid accidental programmings of the redundancy lines. If direct memory access now occurs, i.e., when DMA is high, the transistor 36 behaves like a short circuit, whereas the transistor 37 behaves like. an open circuit (therefore the switch 6 L is closed) and the data are routed by the I/O means directly to the internal bus 1 L , bypassing the output buffers 3 L . It is now necessary to consider the following cases: request for reading from the memory in the presence of redundancy, request for programming in the presence of redundancy, and request for direct memory access again in the presence of redundancy. We will first consider reading from the memory in the presence of redundancy. In this case, therefore, the signal REDL is high, the signal DMA is low, and the programming signal PG is low. The switches 5 L and 6 L are not affected, since DMA=0. The switch 8 L , in case of redundancy, assumes the position for connection to the connector 41 that leads to the redundancy line 2. If REDL is high, the two pass transistors 28 form an open circuit and the signal is routed through the two pass transistors 29 and from there over the wire 20, in order to be sent to the output buffers 4 L . In case of programming with redundancy, and therefore if the signal PG is high and the signal REDL is high, the switch 15 L closes, selectively connecting to the ground one line of the internal bus 1 L , specifically the line that should be programmed but is made redundant. In turn, the switch 8 L moves to the position for connection to the wire 41 and thus to the redundancy line 2; i.e., the two pass transistors 28 behave like an open circuit, whereas the two pass transistors 29 behave like a short circuit, enabling the transfer of the programming data on the redundancy line 2. In this case, the switch 16 remains open. Consider now the case of a request for direct memory access in the presence of redundancy, therefore when DMA and REDL are both high. In this situation, it is necessary to perform a direct memory access but by accessing the line thereof that has been made redundant instead of the natural line. This occurs only for the line that has been made redundant and not for all the other ones. Therefore, when REDL is high, the switch 8 L , which corresponds to the line that has been made redundant, assumes the position for connection to the redundancy line, as already described earlier; when REDL is high, the switch 6 L closes, enabling the direct connection to the I/O means 4 L , and the switch 5 L assumes the position for connection to the redundancy line 2. The switches 15 L and 16 remain open because they are meant for programming activity and are therefore controlled by this activity. As regards instead the management of x16 (word) or x8 (byte) parallelism, when the signal on the line WORD/BYTE is high, indicating x16 parallelism, the pair of pass transistors 23 behaves like an open circuit and the pass transistor 24 behaves like a short circuit; therefore, the switch 9 of figure 1 is in the condition shown in figure 1; otherwise, when the signal on the line WORD/BYTE is low, it is the pair of pass transistors 24 that behaves like an open circuit, thus allowing the connection of the internal bus 1 H to the output buffers 3 L . This characteristic allows to use a 16-bit memory device even if one wishes to use only a parallelism that uses 8 out of 16 possible bits. It should be noted that in this case, too, the redundancy that relates to the part H performs its function during reading (programming is always x16, and so is DMA). In practice, it has been observed that the device according to the invention fully achieves the intended aim, since it allows to provide a data input/output managing device that assumes bidirectionality characteristics by virtue of the introduction of an internal bus, which becomes bidirectional for the transmission of data from the memory matrix to the outside and from the outside to the memory matrix for programming. At the same time, the device according to the invention allows to manage redundancy during reading of the memory matrix, during its programming, and during DMA. The device according to the invention also allows to directly access the memory matrix to directly read said memory matrix or the redundancy lines if direct access to a redundancy line must be performed. Finally, the device according to the invention allows to manage x8 or x16 parallelism of the memory matrix during reading. In this manner, the internal bus provided to bidirectionally transmit information and data to and from the memory allows to drastically reduce the number of lines required to perform these operations between mutually communicating structures that are arranged in mutually distant positions, conveying all the information on "single" points by means of the internal bus. Each operation for memory access or for reading from the memory is handled in an exclusive manner, never in a parallel manner, thus ensuring maximum reliability of the transmission of the data and information related to the memory. All the paths for access to the data bus are controlled by bidirectional structures that allow the flow of data in two directions, toward the memory and from the memory, in an exclusive manner. The device thus conceived is susceptible of numerous modifications and variations. In practice, the materials employed, so long as they are compatible with the specific use, as well as the dimensions, may be any according to the requirements and the state of the art. Where technical features mentioned in any claim are followed by reference signs, those reference signs have been included for the sole purpose of increasing the intelligibility of the claims and accordingly such reference signs do not have any limiting effect on the interpretation of each element identified by way of example by such reference signs.

Claims: A data input/output managing device for a memory that comprises at least one matrix of memory cells, comprising: at least one bidirectional internal bus (1) for the transfer of data from and to said memory matrix; a redundancy management line (2) that is associated with said internal bus; means (8) for enabling/disabling the transmission, over said internal bus, of the data from the memory matrix toward the outside; means (11) for enabling/disabling the transmission, over said internal bus, of data whose source is other than the memory matrix to said memory matrix; and means (5, 12, 13) for enabling/disabling the connection between the outside of the memory and said redundancy line during the reading of said memory matrix and during its programming. The device according to claim 1, characterized in that it comprises means (5) for enabling/disabling direct memory access by means of said internal bus (1). The device according to claim 1, characterized in that it also comprises means (9) for setting to either 8 or 16 a number of parallel bits of each word of said memory matrix accessed by means of said internal bus. The device according to claim 1, characterized in that said bidirectional internal bus (1) comprises 16 lines for transmitting data from and to said at least one memory matrix. The device according to claim 4, characterized in that it comprises means for forcing said redundancy line (2) to the ground and means for forcing the lines of said internal bus (1) to the ground. The device according to claim 1, characterized in that said means (8) for enabling/disabling transmission, by means of said internal bus (1), of the data from the memory matrix to the outside of said memory matrix comprise bidirectional structures. The device according to claim 1, characterized in that said means (8) for enabling/disabling the transmission, over said internal bus (1), of data whose source is other than the memory matrix to the memory matrix comprise bidirectional structures. The device according to claim 1, characterized in that said means (8) for enabling/disabling the connection between the outside of the memory and said redundancy line (2) by means of the path for reading or programming the data of said memory matrix receive in input a redundancy occurrence signal (REDL). The device according to claim 2, characterized in that said means (7) for enabling/disabling direct access to said memory matrix by means of said internal bus comprise rerouting means (30) that are adapted to reroute onto said redundancy line (2) said path for direct access to the memory matrix, said rerouting means receiving in input a signal for enabling direct access to the memory matrix and a redundancy occurrence signal. The device according to claim 5, characterized in that said means (34,35) for forcing said redundancy line (2) to the ground include two transistors (34,35) that receive in input respectively a signal (PG) for enabling the programming of said memory matrix and a no-redundancy signal (REDdn). The device according to claim 10, characterized in that said means for forcing the lines of said internal bus (1) to the ground receive in input said signal (PG) for enabling the programming of said memory matrix and a redundancy occurrence signal (REDL). The device according to claim 1, characterized in that said means (8) for enabling/disabling transmission, over said internal bus, of data whose source is other than said memory matrix to said memory matrix, are connected to rerouting means (30) that are adapted to reroute the data arriving from outside on said internal bus (1), said rerouting means (30) receiving in input a programming enable signal (PG). The device according to claim 3, characterized in that said means (9) for setting to either 8 or 16 a number of parallel bits of each word of said memory matrix by means of said internal bus receive in input a parallelism signal (WORD/BYTE) that is adapted to select either an 8 bit or a 16 bit word length. The device according to any of the preceding claims, applied to a non-volatile memory.

Inventors: BARCELLA ANTONIO, FONTANA MARCO, PASCUCCI LUIGI, ROLANDI PAOLO, BARCELLA, ANTONIO, FONTANA, MARCO, PASCUCCI, LUIGI, ROLANDI, PAOLO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1996
Main classification: G06F11
IPC codes: G11C16, G11C7, G11C17, G11C29