Pin diode with insulated gate.

Abstract: A pin diode is formed by a p + collector region (1), an n type buffer region (3), an n - region (5) and an n + cathode region (7). A trench (9) is formed from the surface of n + cathode region (7) through n + cathode region (7) to reach n - region (5). An insulating film (11) is formed along an inner wall surface of trench (9). A gate electrode layer (13) is formed to oppose to the sidewall of n + cathode region (7) with insulating film (11) interposed. A cathode electrode (17) is formed to be electrically connected to n + cathode region (7). An anode electrode (19) is formed to be electrically connected to p + collector region (1). The n + cathode region (7) is formed entirely over the surface between trenches (9) extending parallel to each other. Thus, a power semiconductor device in which gate control circuit is simplified and which has good on property can be obtained.

Description: Field of the Invention The present invention relates to a vertical power semiconductor device having self turn-off function. Description of the Background Art First, a conventional semiconductor device will be described. Fig. 96 is a cross sectional view schematically showing a structure of a semiconductor device in accordance with a first prior art example. Referring to Fig. 96, the first prior art example has an SITh (Static Induction Thyristor). The SITh includes a pin diode porion, a p type gate region 307, a gate electrode layer 309, a cathode electrode 311 and an anode electrode 313. A pin diode portion has a stacked structure including a p + , anode region 301, an n - region 303 and a cathode region (n + emitter region) 305. The p type gate region 307 is formed in n - region 303. Gate electrode 309 is electrically connected to p type gate region 307. Cathode electrode 311 is electrically connected to cathode region 305, and anode electrode 313 is electrically connected to p + anode region 301, respectively. The SITh can realize on-state by setting gate voltage applied to gate electrode 309 positive. At this time, current flows through pin diode from p + anode region 301 to the side of cathode region 305. Fig. 97 is a cross sectional view schematically showing a structure of a semiconductor device in accordance with a second prior art example. Referring to Fig. 97, the second prior art example shows a GTO (Gate Turn-Off) thyristor. The GTO thyristor has a p + anode region 351, an n - region 353, a p base region 355, a cathode region 357, a gate electrode 359, a cathode electrode 361 and an anode electrode 363. The p + anode region 351, n - region 353, p base region 355 and cathode region 357 are stacked successively. The p type base region 355 is electrically connected to gate electrode 359. Cathode electrode 361 is electrically connected to cathode region 357, and anode electrode 363 is electrically connected to p + anode region 351, respectively. In this GTO thyristor also, on-state can be realized by setting the gate voltage positive. By setting gate voltage positive, current flows through a pnpn diode from p + corrector region 351 to the side of cathode region 357. Both in the first and second prior art examples, off-state can be realized by applying a negative voltage to the gate electrode. When a negative voltage is applied to gate electrode 309 or 359, minority carriers (holes) remaining in the device are extracted from gate electrode 309 or 359. Thus, the main current is cut off. Fig. 98 is a cross sectional view schematically showing a structure of a semiconductor device in accordance with a third prior art example. Referring to Fig. 98, the third prior art example shows an example of a trench IGBT (Insulated Gate Bipolar Transistor). The trench IGBT includes a p + collector region 101, n + buffer region 103, n - region 105, p type base region 107, n + emitter region 109, a p + contact region 111, a gate oxide film 115, a gate electrode layer 117, a cathode electrode (emitter) 121 and an anode electrode (collector) 123. On p + collector region 101, n - region 105 is formed with n + buffer region 103 interposed. On n - region 105, n + emitter region 109 and p + contact region 111 are formed adjacent to each other with p type base-region 107 interposed. On the surface where n + emitter region 109 is formed, there is provided a trench 413. Trench 413 passes through n + emitter region 109 and p type base region 107 and reaches n - region 105. The depth T P of trench 413 from the surface is 3 to 5 µm. Along inner wall surface of trench 413, gate oxide film 115 is formed. Gate electrode layer 117 is formed to fill the trench 413 and with its upper end projecting from trench 413. Gate electrode layer 117 opposes to n + emitter region 109, p type base region 107 and n - region 105 with gate oxide film 115 interposed. Interlayer insulating layer 119 is formed to cover an upper end of gate electrode layer 117. In interlayer insulating layer, there is provided an opening which disposes the surfaces of n + emitter region 109 and p + contact region 111. Cathode electrode (emitter) 121 is formed so as to electrically connect n + emitter region 109 and p + contact region 111 through the opening. Anode electrode (collector) 123 is formed to be electrically connected to p + collector region 101. Hereinafter, the surface of the semiconductor substrate on which cathode electrode 121 is formed will be referred to as a cathode surface or a first main surface, and the surface where anode electrode 123 is formed will be referred to as an anode surface or the second main surface. A trench MOS gate structure in which gate electrode layer 117 is formed in trench 413 with gate oxide film 115 interposed is manufactured through the following steps. First, in a semiconductor substrate, a relatively deep trench 413 of about 3 to about 5 µm is formed by common anisotropic dry etching. Sacrificial oxidation or cleaning is performed on the inner wall of trench 413. Thereafter, a silicon thermal oxide film (hereinafter referred to as a gate oxide film) 115 is formed at a temperature from 900°C to 1000°C in, for example, vapor ambient (H 2 O). A polysilicon film doped with an n type impurity such as phosphorous or a polycrystalline silicon film doped with a p type impurity such as boron fills the trench 413. The doped polysilicon film is patterned so that trench 413 is filled and doped polysilicon film is drawn out at least from a porion of trench 413 to the surface of the cathode side. The patterned doped polysilicon film is electrically connected to a gate surface interconnection formed of a metal such as aluminum, provided entirely over the semiconductor device, while insulated from cathode electrode 121. The method of controlling on-state and off-state in the third prior art example will be described. On-state is realized by applying a positive (+) voltage to gate electrode 117 while a forward bias is applied between cathode electrode 121-anode electrode 123, that is, while a positive (+) voltage is applied to anode electrode 123 and a negative (-) voltage is applied to cathode electrode 121. A turn-on process in which the device transits from off-state to the on-state will be described in the following. When a positive (+) voltage is applied to gate electrode layer 117, an n channel (inverted n region) which is inverted to n type and having very high electron density is generated at p base region 107 near gate oxide film 115. Electrons, which are one of the current carriers (hereinafter referred to as carriers) are injected from n + emitter region 109 through the n channel to n - region 105, and flow to p + collector region 101 to which the positive (+) voltage is applied. When the electrons reach p + collector region 101, holes, which are other current carrier are injected from p + collector region 101 to n - region 105 and flow to n + emitter region 109 to which the negative (-) voltage is applied. Thus, the flow reaches the position where the aforementioned n channel is in contact with n - region 105. This process is referred to as storage process, and the time necessary for this process is referred to as storage time (t storage ) or turn-off delay time (td( off )). Power loss during the storage time is so small that it can be neglected, as compared with steady loss, which will be described layer. Thereafter, from anode electrode 123 and cathode electrode 121, sufficient current carriers are stored in n - region 105 to such an amount that is larger by two or three orders of magnitude than the concentration of semiconductor substrate (1 x 10 12 to 1 x 10 15 cm -3 ), in accordance with the difference between potentials applied to both electrodes. Accordingly, a low resistance state referred to as conductivity modulation is caused by the hole-electron pairs, thus turn-on is completed. This process is referred to as a rise process, and the time necessary for this process is referred to as rise time (t rise ). Power loss during this time is approximately the same or larger than the steady loss, which will be described layer later, and constitutes roughly one fourth of the entire loss. The steady state after the completion of turn-on is referred to as on-state, and the power loss represented by a product of on-state voltage caused by on resistance (effectively, potential difference between both electrodes) and the conduction current is referred to as on-loss or steady loss. When a positive voltage is applied to gate electrode layer 117, an n + accumulation region 425a having high electron density is formed along the sidewalls of trench 113, as shown in Fig. 99. Off-state is realized by applying a negative (-) voltage to gate electrode layer 117, even when forward bias is being applied to anode electrode 123-cathode electrode 121. A turn off process in which the device transits from on state to off state will be described in the following. When a negative (-) voltage is applied to gate electrode layer 117, n channel (inverted n region) formed on the side surface of gate electrode layer 117 is eliminated, and supply of electrodes from n + emitter region 109 to n - region 105 is stopped. The process up to here is referred to as storage process, and the time necessary for this process is referred to as storage time (ts) or turn off delay time (td( off )). The power loss during this time is very small as compared with the turn on loss and the steady loss, and it can be neglected. As the electron density reduces, the density of electrons which has been introduced to n - region 105 gradually reduces from the vicinity of n + emitter region 109. In order to maintain charge neutralize condition, holes which have been introduced to n - region 105 also reduce, and p base region 107 and n - region 105 are reversely biased. Consequently, depletion layer begins to extend at the interface between p base region 107 and n - region 105, and tends to have a thickness which corresponds to the applied voltage in the off state between both electrodes. The process up to here is referred to as a fall process, and the time necessary for this process is referred to as fall time (tf). The power loss during this time is approximately the same or larger than the aforementioned turn off loss and steady loss, and it constitutes roughly one fourth of the entire loss. Further, holes in an electrically neutral region where both carriers remain outside the aforementioned depletion region (p + collector region 101) pass through the depletion region and extracted through p + contact region 111 to emitter electrode 121, thus carriers are all eliminated and turn off is completed. This process is referred to tail process, and the time necessary for this process is referred to as tail time (t tail ). The power loss during the tail time is referred to as tail loss, which is approximately the same or larger than the turn on loss, loss during the fall time and steady loss, and it constitutes roughly one fourth of the entire loss. The steady state after the completion of turn off is referred to as off state and power loss caused by the product of leak current in this state and the voltage between both electrodes is referred to as off loss. However, generally it is smaller than other power losses and it can be neglected. The above described first and second prior art examples relate to current control type devices in which minority carriers are extracted from gate electrodes 309 and 359 to set off-state. Therefore, at the time of turn off, it is necessary to extract a considerable amount of the main current from the gate electrode. When a relatively large current is to be extracted, there will be a large surge current caused by inductance of interconnections or the like, and heat radiation caused by current must also be taken into consideration. Therefore, it becomes necessary to provide a protecting circuit against surge voltage and excessive current, in the circuit for controlling the gate voltage. This makes the gate control circuit complicated. Further, it is possible that the control circuit is thermally destroyed or suffers from thermal runaway because of heat, and hence a cooling mechanism must be provided. This makes the device larger. A semiconductor device which solves these problems is disclosed in Japanese Patent Laying-Open No. 5-243561. The semiconductor device disclosed in this application will be described as a fourth prior art example. Fig. 100 is a plan view schematically showing the structure of the semiconductor device in accordance with the fourth prior art example, and Figs. 101 and 102 are cross sectional views taken along the lines P-P' and Q-Q' of Fig. 100, respectively. Referring to Figs. 100 to 102, the fourth prior art example shows an electrostatic induction thyristor. On one surface of a high resistance n type base layer 501, a p type emitter layer 503 is formed with an n type buffer layer 502 interposed. On the other surface of n type base layer 501, a plurality of trenches 505 are formed spaced by a small distance from each other. In these trenches 505, gate electrodes 507 are formed embedded, with gate oxide film 506 interposed. At every other region between the trenches 505, n type turn off channel layer 508 is formed. On the surface of turn off channel layer 508, a p type drain layer 509 is formed. At a surface portion sandwiched between p type drain layers 509, an n type source layer 510 is formed. A cathode electrode 511 is formed to be electrically connected to p type drain layer 509 and n type source layer 510. An anode electrode 512 is formed to be electrically connected to p type emitter layer 503. In the fourth prior art example, when the positive voltage is applied to gate electrode 507 to raise the potential of n type base layer 501 sandwiched between the trenches 505, electrons are introduced from n type source layer 510, so that the device turns on. Meanwhile, when a negative voltage is applied to a gate electrode layer 507, a p type channel is formed on a side surface of the trench of n type turn off channel layer 508, carriers of n base layer 501 are discharged through p drain layer 509 to cathode electrode 511, and therefore the device turns off. In the fourth prior art example, the gate electrode 507 has an insulated gate structure. Therefore, in the fourth prior art example, the gate electrode 507b is not of the current control type in which current is directly drawn out from the substrate, but it is of a voltage controlled type in which control is realized by the voltage (gate voltage) applied to the gate electrode. Since the fourth prior art example is of the voltage controlled type, it is not necessary to extract a large current from gate electrode layer 507 at the time of turn off. Accordingly, it is not necessary to provide a protecting circuit or a cooling mechanism in consideration of surge current and heat caused when large current is extracted. Therefore, the fourth prior art example is advantageous in that the gate control circuit can be simplified. However, in the fourth prior art example, at the surface region sandwiched between trenches 507 extending parallel to each other as shown in Fig. 100, there are p type drain layer 509 and n type source layer 510 adjacent to each other. Since p type drain layer 509 has a potential barrier with respect to the electrons, the electron current entering the cathode electrode 511 flows only through the portion of n type source layer 510. Therefore, there is inhibiting factor such as partial increase in current density, which results in degraded on characteristics. In the third prior art example shown in Fig. 98, it is not possible to improve on-state voltage vf, and hence power consumption of the semiconductor device is considerably large. This will be described in greater detail. As a method of improving ON voltage (on-state voltage Vf of a diode) which is a basic characteristic of IGBT, there is a method of improving injection efficiency of electrons on the side of the cathode. In order to improve injection efficiency of electrons, it is necessary to increase impurity concentration on the side of the cathode or to increase the effective cathode area. The effective cathode area means the area of a portion (denoted by the solid line in the figure) where n + region (effective cathode region) including n + emitter region 109 and storage region 425a is in contact with p type base region 107 and n - region 105. In the third prior art example, the depth of the trench 413 is 3-5 µm, as already described. Therefore, when a positive voltage is applied to gate electrode layer, extension of the storage layer generated around the trench 113 is limited. Accordingly, it is not possible to ensure the large effective cathode area. This hinders improvement in injection efficiency of electrons on the side of the cathode, and hence ON voltage of IGBT cannot be reduced. From each of US 5 360 746 A and EP-A-0 565 349 a semiconductor device according to the preamble of claim 1 can be taken. The gate electrode layer is opposed to the third impurity region. SUMMARY OF THE INVENTION An object of the present invention is to provide a power semiconductor device which allows simplification of gate control circuit, provides good on characteristic and reduces steady loss. Another object of the present invention is to provide a power semiconductor device which allows simplification of gate control circuit, has low on-state voltage Vf and low steady loss. The semiconductor device in accordance with the present invention is defined in the appended claims. In accordance with an aspect of the present invention, the semiconductor device includes a diode structure in which main current flows between both main surfaces with an intrinsic or first conductivity type semiconductor substrate sandwiched therebetween, which device includes a first impurity region of a first conductivity type, a second impurity region of a second conductivity type, a third impurity region of the second conductivity type, a fourth impurity region of the first conductivity type, a control electrode layer, a first electrode layer and a second electrode layer. The first impurity region of the first conductivity type is formed as the first main surface of the semiconductor substrate, and has an impurity concentration higher than that of the semiconductor substrate. The second impurity region of the second conductivity type is formed on the second main surface of the semiconductor substrate. The semiconductor substrate has trenches extending parallel to each other and sandwiching the first impurity region. The third impurity region of the second conductivity type is a sidewall of the trench and formed at the first main surface. The fourth impurity region of the first conductivity type is provided immediately below the third impurity region to be in contact with the sidewall of the trench and the semiconductor substrate region, and has lower concentration than the first impurity region. The control electrode layer is formed to oppose to the third and fourth impurity regions and semiconductor substrate region with an insulating film interposed, in the trench. The first electrode layer is formed on the first main surface of the semiconductor substrate and is electrically connected to the first and third impurity regions. The second electrode layer is formed at the second main surface of the semiconductor substrate and electrically connected to the second impurity region. In the semiconductor device in accordance with aforementioned still further aspect of the present invention, the control electrode layer opposes to the third and fourth impurity regions and the semiconductor substrate region with the insulating film interposed. In other words, the gate control is of voltage control type. Therefore, it is not necessary to extract a large current from the control electrode layer at the time of turn off. Therefore, it is not necessary to provide a protecting circuit or a cooling mechanism in the gate control circuit in consideration of surface voltage or heat radiation generated when a large current flows. Therefore, as compared with the first and second prior art examples, the gate control circuit can be simplified. Further, the device is a bipolar device. In the bipolar device, both the holes and the electrons contribute to the operation. Therefore, even if the substrate thickness is increased to meet the demand of higher breakdown voltage and current path in the on state becomes longer, there will be conductivity modulation by the holes and electrons. Therefore, the resistance can be maintained low. Accordingly, the amount of heat radiation is small and increase in steady loss can be suppressed. Further, the control electrode layer opposes to the third and fourth impurity regions and the semiconductor substrate region. Therefore, by applying a positive voltage to the control electrode layer, regions near the trenches in which control electrode layers are filled can have such high electron density that is approximately the same as in the first impurity region. Therefore, all the regions near the trench can be regarded as the first impurity region, and a state as if the first impurity region is enlarged can be realized. When the first impurity region is enlarged, the contact area between the enlarged first impurity region and the semiconductor substrate region, that is, the effective cathode area is increased. Thus, the efficiency in injecting electrons on the side of the cathode is improved, and on-state voltage Vf of the diode can be reduced. By applying a voltage to the control electrode layer, the region of the opposite conductivity type near the trench can have approximately the same high electron density as that of the first impurity region. Therefore, the region of the opposite conductivity type such as the third impurity region as well as the fourth impurity region can be regarded as the first impurity region. Since the third impurity region is also regarded as a first impurity region in addition to the fourth impurity region, the effective cathode area can further be increased. Thus, the efficiency in injecting electrons on the cathode side can further be improved, and the on-state voltage Vf on the diode can further be reduced. Preferably, in the above described aspect, an isolating impurity region is further provided, formed at the first main surface of the semiconductor substrate. On one side of the outermost of the plurality of trenches extending parallel to each other, another trench is positioned, while on the other side, the isolating impurity region is formed in contact with the outermost trench and deeper than the trench. Since isolating impurity region is provided to surround the region in which a diode structure or a thyristor structure is formed, the effect of electrical isolation from other elements can be enhanced, and breakdown voltage of the device is improved and stabilized. Preferably, in the above described aspect, the depth of the trench from the first main surface is at least 5 µm and at most 15 µm. As the depth of the trench is at least 5 µm, the storage region having high electron density can be generated widely along the sidewall of the trench at on-state. Therefore, as compared with the third prior art example, wider effective cathode area is ensured. Therefore, the efficiency in injecting electrons on the cathode side can further be improved, and the on-state voltage Vf can be reduced. Further, since it is difficult to form a trench deeper than 15 µm with a minute width (of at most 0.6 µm), the depth of the trench is at most 15 µm. The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS In the following description Embodiments 1 to 8 do not represent the invention but are necessary for its understanding. Fig. 1 is a schematic plan view showing a structure of a semiconductor device in accordance with Embodiment 1 of the present invention. Fig. 2 is a schematic plan view showing the device of Fig. 1 with cathode electrode provided. Fig. 3 is a schematic cross sectional view taken along the line A-A' of Fig. 2. Figs. 4 to 9 are schematic cross sectional views showing, in order, the steps of manufacturing the semiconductor device in accordance with Embodiment 1 of the present invention. Fig. 10 is a schematic cross sectional view showing a main current conducting state of the semiconductor device in accordance with Embodiment 1 of the present invention. Fig. 11 is a schematic plan view showing a structure of a semiconductor device in accordance with Embodiment 2 of the present invention. Fig. 12 is a schematic plan view showing the device of Fig. 11 with cathode electrode provided. Fig. 13 is a schematic cross sectional view taken along the line B-B' of Fig. 12. Figs. 14 to 16 are schematic cross sectional views showing, in order, the steps of manufacturing the semiconductor device in accordance with Embodiment 2 of the present invention. Fig. 17 is a schematic plan view showing the structure of the semiconductor device in accordance with Embodiment 3 of the present invention. Fig. 18 is a schematic plan view showing the device of Fig. 17 with cathode electrode provided. Fig. 19 is a schematic cross section taken along the line C-C' of Fig. 18. Figs. 20 and 21 are schematic cross sectional views showing, in order, the steps of manufacturing the semiconductor device in accordance with Embodiment 3 of the present invention. Fig. 22 is a graph showing relation between on-state voltage Vf and the ratio Rn. Fig. 23 is a schematic plan view showing a structure of the semiconductor device in accordance with Embodiment 4 of the present invention. Fig. 24 is a schematic plan view showing the device of Fig. 23 with cathode electrode provided. Fig. 25 is a schematic cross sectional view taken along the line D-D' of Fig. 24. Fig. 26 is a schematic plan view showing a structure of a semiconductor device in accordance with Embodiment 5 of the present invention. Fig. 27 is a schematic plan view showing the device of Fig. 26 with cathode electrode provided. Fig. 28 is a schematic cross sectional view taken along the line E-E' of Fig. 27. Figs. 29 and 30 are schematic cross sectional views showing, in order, the steps of manufacturing the semiconductor device in accordance with Embodiment 5 of the present invention. Fig. 31 is a schematic plan view showing the structure of the semiconductor device in accordance with Embodiment 6 of the present invention. Fig. 32 is a schematic plan view showing the device of Fig. 31 with cathode electrode provided. Fig. 33 is a schematic cross section taken along the line F-F' of Fig. 32. Fig. 34 is a plan view schematically showing the structure of the semiconductor device in accordance with Embodiment 7 of the present invention. Fig. 35 is a schematic plan view showing the device of Fig. 34 with cathode.electrode provided. Fig. 36 is a schematic cross sectional view taken along the line G-G' of Fig. 35. Figs. 37 and 38 are schematic cross sectional views showing, in order, the steps of manufacturing the semiconductor device in accordance with Embodiment 7 of the present invention. Fig. 39 is a plan view schematically showing a structure of a semiconductor device in accordance with Embodiment 8 of the present invention. Fig. 40 is a schematic plan view showing the device of Fig. 39 with cathode electrode provided. Fig. 41 is a schematic cross sectional view taken along the line H-H' of Fig 40. Fig. 42 is a schematic plan view showing the structure of a semiconductor device in accordance with Embodiment 9 of the present invention. Fig. 43 is a schematic plan view showing the device of Fig. 42 with cathode electrode provided. Fig. 44 is a schematic cross sectional view taken along the line I-I' of Fig. 43. Figs. 45 to 48 are schematic cross sectional views showing, in order, the steps of manufacturing the semiconductor device in accordance with Embodiment 9 of the present invention. Fig. 49 is a schematic cross sectional view showing a main current conducting state of the semiconductor device in accordance with Embodiment 9 of the present invention. Fig. 50 is a plan view schematically showing a structure of a semiconductor device in accordance with Embodiment 10 of the present invention. Fig. 51 is a schematic plan view showing the device of Fig. 50 with cathode electrode provided. Fig. 52 is a schematic cross sectional view taken along the line K-K' of Fig 51. Fig. 53 is a schematic cross sectional view showing the method of manufacturing the semiconductor device in accordance with Embodiment 10 of the present invention. Fig. 54 is a schematic plan view showing trenches arranged concentrically. Fig. 55 is a schematic plan view showing trenches arranged concentrically. Fig. 56 is a schematic plan view showing trenches arranged concentrically. Fig. 96 is a schematic cross sectional view showing a structure of a semiconductor device in accordance with a first prior art example. Fig. 97 is a schematic cross sectional view showing a structure of a semiconductor device in accordance with a second prior art example. Fig. 98 is a schematic cross sectional view showing a structure of a semiconductor device in accordance with a third prior art example. Fig. 99 is a schematic cross sectional view showing how an n + accumulation layer is generated in the third prior art example. Fig. 100 is a plan view schematically showing a structure of a semiconductor device in accordance with a fourth prior art example. Fig. 101 is a schematic cross sectional view taken along the line P-P' of Fig. 100. Fig. 102 is a schematic cross sectional view taken along the line Q-Q' of Fig. 100. DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to the figures. In the following, for convenience, the cathode region, which is an n + high concentration impurity region will be sometimes referred to as n + emitter region, and the anode region which is p + high concentration impurity region will be sometimes referred to as p + collector region. [Embodiment 1] Referring to Figs. 1 to 3, the present embodiment shows an example which includes a pin diode. The pin diode includes a p + anode (collector) region 1 of a second conductivity type formed at a second main surface, an n type buffer region 3, an n - region 5 which is the semiconductor substrate of a first conductivity type of low impurity concentration. An n + cathode region (n + emitter region) 7 of the first conductivity type formed at the first main surface, insulating films 11 and 15; a gate electrode layer 13 which is the control electrode layer, a cathode electrode 17 which is a first electrode layer, and an anode electrode 19 which is a second electrode layer. At the first main surface where the cathode region 7 is provided, there is formed a trench 9, which reaches the n- region 5 of the substrate through n + cathode region 7. As shown in Fig. 1, the trench 9 has such planer shape that approximately surrounds a rectangle, and has portions extending parallel to each other within the rectangle. The n + cathode region 7 is formed entirely at the first main surface of the semiconductor substrate sandwiched between trenches 9 extending in parallel. The width W of trench 9 is, for example, at least 0.8 µm and at most 1.2 µm. The depth D 1 is, practically, from 5.0 µm to 15.0 µm. Along the inner wall surface of trench 9, a gate insulating film 11 (for example, a silicon thermal oxide film) is provided. Gate electrode layer 13 is formed of phosphorus doped polycrystalline silicon film to fill the trench 9, with its upper end projecting from first main surface. Gate electrode layer 13 opposes to the side surface of n + cathode region 7 and to the side surface and bottom surface of n - region 5, with gate insulating film 11 interposed. Gate electrode layer 13 may be pulled up to a portion where insulating film is provided on the first main surface, from the trench (not shown). An insulating film 15 of, for example, a silicon thermal oxide film and BPSG (Boro Phospho-Silicate Glass) is formed to cover the upper end of the gate electrode layer 13. There is provided an opening at a portion of the BPSG insulating film 15, and metal interconnection is connected to the gate electrode through the opening (not shown). The cathode electrode 17, which is the first electrode layer, is electrically connected to cathode region 7. Cathode region 7 is formed on a region surrounded by trenches 9. The planer region where the cathode electrode 17 is formed is referred to as a diode forming region here. Anode electrode 19, which is the second electrode layer, is electrically connected to p + collector region 1 formed at the second main surface. As to the impurity concentrations of respective portions, the surface concentration of p + collector region 1 is from 1 x 10 16 cm -3 to 5 x 10 21 cm -3 , the peak concentration of n·type buffer region 3, 1 x 10 13 cm -3 to 1 x 10 19 cm -3 , of n - region 5, 1 x 10 12 cm -3 to 1 x 10 17 cm -3 , and of cathode region 7, the surface concentration must be at least 1 x 10 17 cm -3 . The surface impurity concentration of p + collector region is higher than the peak impurity concentration of n type buffer region 3, the peak impurity concentration of n type buffer region 3 is higher than peak impurity concentration of n - region 5, and the surface impurity concentration of n + cathode region 7 is higher than the peak concentration of n - region 5. The impurity concentration of n type buffer region 3 has only to be lower than the impurity concentration of p + collector region 1 and higher than that of n - region 5. The method of manufacturing the semiconductor device in accordance with the present embodiment will be described. First, referring to Fig. 4, p + collector region 1, n type buffer region 3 and n - region 5 are formed stacked in this order. Referring to Fig. 5, trenches 9a are selectively formed, for example, by photolithography and anisotropic plasma etching used in a common semiconductor process, to extend from the surface of n - region 5 to the inside. Referring to Fig. 6, an insulating film 11 of, for example, silicon oxide film, which will be the gate insulating film, is formed along the inner wall surface of trench 9 by, for example, thermal oxidation. Before formation of gate oxide film 11, sacrificial oxidation and isotropic plasma etching (CDE) may be performed to improve MOS characteristic. Referring to Fig. 7, gate electrode layer 13 is formed to fill the trench 9 with its upper end protruding from trench 9 by common photolithography and etching technique. Gate electrode layer 13 is formed of a material such as polycrystalline silicon doped with an n type impurity such as phosphorus (hereinafter referred to as doped polysilicon). Referring to Fig. 8, an insulating film 15 formed of a silicon thermal oxide film and a CVD oxide film such as BPSG is formed to cover the upper end of gate electrode layer 13 protruding from trench 9. Referring to Fig. 9, thereafter, selective ion implantation of n type impurity element such as Sb, As, P or the like is performed to the surface of n - region 5 sandwiched between the trenches 9. Thereafter, introduced impurity is diffused by heat treatment, for example, and n + cathode region 7 is formed entirely at the surface of n - region 5 sandwiched between the trenches. The cathode region 7 is made shallower than the depth of trench 9. Thereafter, the cathode electrode 17 is formed to be electrically connected to cathode region 7, and anode electrode 19 is formed to be electrically connected to p + collector region 1. Thus, the semiconductor device shown in Figs. 2 and 3 is completed. The method of operating the semiconductor device in accordance with a present embodiment will be described. Referring to Fig. 3, on-state is realized by applying a small positive voltage to the gate electrode layer 13. In this case, current flows from p + collector region 1 to n + cathode region 7. This operation is the same as the pin diode, so that electrons are introduced from n + cathode region 7 to n - semiconductor substrate 5, holes are introduced from p - collector region 1, whereby conductivity modulation occurs in substrate 5. Thus, on-state voltage becomes lower. Off-state is realized by applying a negative voltage to gate electrode layer 13. When a negative voltage is applied to gate electrode layer 13, a depletion layer extends around the trench 9, the current path of the main current is cut off, and thus the device can be turned off. In the semiconductor device in accordance with the present embodiment, gate electrode layer 13 opposes to n - region 5 and the sidewall of cathode region 7 with insulating film 11 interposed, as specifically shown in Fig. 3. In other words, the control method by the gate electrode layer 13 is of voltage controlled type. therefore, different from SITh in which gate is formed by pn junction, gate electrode layer 13 never extracts a part of the main current as gate current in the turn off operation. Therefore, it is not necessary to provide large current to the gate control circuit. Therefore, the gate drive circuit can be simplified, it is not necessary to provide a protecting circuit in consideration of a surge current which is generated when a gate current flows, and a cooling apparatus in consideration of heat radiation is not necessary, either. Therefore, as compared with the first and second prior art examples, gate control circuit can be simplified in the semiconductor device in accordance with the present embodiment, and the system as a whole can be reduced in size, simplified and enables low energy loss. Further, the pin diode is a bipolar device. In the bipolar device, both holes and electrons contribute to the operation. Therefore, even if the substrate thickness is increased to meet the demand of higher breakdown voltage, especially the thickness T 0 of n - region 5 of Fig. 3 is increased and current path when the pin diode operates becomes longer, there will be conductivity modulation generated by holes and electrons. Therefore, on-state voltage can be maintained low. Therefore, increase in steady loss can be suppressed and the amount of heat radiation can be reduced. Further, as shown in Fig. 3, gate electrode layer 13 opposes to n - region 5 and cathode region 7, as shown in Fig. 3. Therefore, when a positive voltage is applied to gate electrode layer 13 at on-state, there is generated an n + accumulation region 21 where the large number of electrons are pulled, around the trench 9, as shown in Fig. 10. Therefore, n + region serving as cathode region 7 is enlarged. Now, as a method of improving on-state voltage Vf of the diode, it has been known to increase effective cathode area, as already described. The effective area of cathode here means the interface area between n - region and n + region, and n + region connected with cathode electrode. In the semiconductor device in accordance with the present embodiment, since there is generated n + accumulation region 21 as shown in Fig. 10, n + cathode region 7 is enlarged. Therefore, the contact area between the entire effective cathode region including n + cathode region 7 plus n + accumulation region 21 and n - region 5 is enlarged. Thus, injection efficiency of electron on the side of the cathode can be improved, and on-state voltage Vf of the diode can be reduced. In this manner, even when the first main surface (cathode side) is the n + cathode region in its entirety, it becomes possible to reduce on loss by increasing n + region in the semiconductor chip as a whole, by enlarging effective cathode region. In other words, power loss of the semiconductor device can be reduced. In the semiconductor device in accordance with the present embodiment, since n + cathode region 7 is formed entirely at the first main surface on the cathode side, as compared with the example in which n region and p region exist at the first main surface (Figs. 100 to 102), the electron current entering from the cathode side flows uniformly through the first main surface of the semiconductor device sandwiched by the trenches 9. Therefore, partial increase of current density can be prevented, and good on characteristic is obtained. [Embodiment 2] Referring to Figs. 11 to 13, as compared with the semiconductor device in accordance with Embodiment 1, the semiconductor device of the present embodiment is different in that a p + isolation impurity region 23 is provided. The p + isolation impurity region 23 is formed at the surface of n - region 5 to surround planer region of diode forming region and to be in contact with trenches 9. Further, p - isolation impurity region 23 is made deeper than trench 9. Except this point, the present embodiment is the same as Embodiment 1. Therefore, corresponding portions are denoted by the same reference characters and description thereof is not repeated. The method of manufacturing the semiconductor device in accordance with the present embodiment will be described. The method of manufacturing the semiconductor device in accordance with the present embodiment first includes the same steps as Embodiment 1 shown in Fig. 4. Thereafter, referring to Fig. 14, a p + region 23a is formed selectively at a position surrounding the diode forming region, by deposition or ion implantation of an element such as B, serving as p type impurity. Thereafter, heat treatment or the like is performed. Referring to Fig. 15, by the above described heat treatment, p type impurity is diffused, and p + isolation impurity region 23 is formed at a prescribed position. Referring to Fig. 16, thereafter, a trench 9a is formed having portions extending parallel to each other at the surface of n - region 5. Thereafter, approximately similar processes as in Embodiment 1 are performed. Therefore, the description thereof is not repeated. The method of operating the semiconductor device by the gate is approximately the same as Embodiment 1. Referring to Fig. 13, the p + isolation impurity region 23 is connected to cathode electrode 17 by an inverted layer formed around gate electrode layer 13, when a negative voltage is applied to gate electrode layer 13. Therefore, the pn junction formed by p + isolation impurity region 23 and n - region 5 is reversely biassed. Therefore, main breakdown voltage maintaining capability of the device can be enhanced. According to a semiconductor device of the present embodiment, p type impurity region 23 is formed deeper than trench 9 to surround diode forming region, as shown in Figs. 12 and 13. Therefore, p + isolated region 23 is electrically isolated from the diode at on-state, on-state voltage can be maintained low. And, p + isolated region 23 is electrically connected cathode electrode 17 at off-state, breakdown voltage can be improved. [Embodiment 3] Referring to Figs. 17 to 19, the semiconductor device of the present embodiment differs from the semiconductor device of Embodiment 1 in that a p + high concentration region 31 (hereinafter referred to as p + contact region) is provided. The p + contact region 31 is formed at the first main surface in diode forming region, to be adjacent to n + cathode region with trenches 9b and 9c interposed. The p + contact region 31 is formed at the surface region sandwiched by trenches 9b and 9c extending parallel to each other, as shown in Fig. 18. The p + contact region 31 is electrically connected to cathode electrode 17. The p + contact region 31 has a surface impurity concentration of at least 1 x 10 17 cm -3 . The p + contact region 31 and the n + cathode region 7 are arranged alternately, with trenches interposed. The number of trenches 9a and 9b, ... may be arbitrarily selected. Except this point, the present embodiment is almost similar to Embodiment 1. Therefore, corresponding portions are denoted by the same reference characters and description thereof is not repeated. The method of manufacturing the semiconductor device in accordance with the present embodiment will be described. One of the method of manufacturing the semiconductor device in accordance with the present embodiment includes similar steps as Embodiment 1 shown in Figs. 4 to 8. Then, referring to Fig. 20, by common photolithography process, portions other than the portion where p + contact region is to be formed are masked by photoresist, and by ion implantation, depletion or the like of element such as boron serving as p type impurity, a p + contact region 31 is formed at the surface of n - region 5 sandwiched between trenches 9b, 9c and so on extending parallel to each other. The p + contact region 31 has the depth of about 0.5 µm to about 1.0 µm, and is made shallower than trench 9. Again, referring to Fig. 21, by the combination of photolithography process and ion implantation process similar to those described above, n + cathode region 7 is formed entirely at the surface of n - region 5 sandwiched between trenches 9a and 9b, and 9c and 9d, to be adjacent to p + contact region 31 with trench 9b or 9c interposed. The following steps are approximately similar to those of Embodiment 1, and therefore, description thereof is not repeated. The order of forming p + contact region 31 and n + cathode region 7 may be reversed. Elements and heat treatment used for diffusion of respective regions may be adjusted in accordance with the desired depth of diffusion. The method of operating the semiconductor device in the present embodiment is also the same as Embodiment 1. Therefore, description thereof is not repeated. In the semiconductor device in accordance with the present embodiment, p + contact region 31 is arranged to be adjacent to n + cathode region 7 with trench 9b or 9c interposed, as shown in Fig. 19. Therefore, on-state voltage Vf can be reduced, and turn-off time can be reduced. These points will be described in greater detail in the following. Fig. 22 is a graph showing relation between on-state voltage Vf and ratio Rn, which is obtained by a simulation of a general trench IGBT or a trench diode. The ratio Rn here means the ratio of existence of n type impurity region when there are n type impurity region 7 and p type impurity region 31 on the side of the first main surface (cathode side) as shown in Figs. 18 and 19, which is obtained in accordance with the following equation. Here, the..effective cathode region includes n + accumulation region 21 (Fig. 10) provided when a positive voltage is applied to the gate electrode. Rn = n + region (effective cathode region) / (n + region (effective cathode region) + p type region) As is apparent from Fig. 22, the larger the ratio Rn, that is, the larger the ratio of existence of n type impurity region, the lower the on-state voltage Vf. Accordingly, on-state voltage can be minimized, when there is no p type impurity region (that is, when the ratio Rn = 1). As shown in Fig. 19, in the semiconductor device in accordance with the present embodiment, p + contact region 31 is provided adjacent to n + cathode region 7. Therefore, hole current I 1 is drawn out from p + contact region 31 to cathode electrode 17. Hole current I 1 is a part of the total hole current at turn-off. Therefore, current I flowing though the diode is reduced, and especially the tail current tends to decrease quickly. Thus, the turn- off time can be reduced. Accordingly, in the semiconductor device in accordance with the present embodiment, by adjusting the ratio of existence of cathode region 7 and p + contact region 31 at the surface of n - region 5, optimum on-state voltage Vf and turn-off time in accordance with various diode properties can be selected in accordance with the expression (1) above. [Embodiment 4] Referring to Fig. 23 to 25, the semiconductor device in accordance with the present embodiment differs from Embodiment 3 in that a p + isolation impurity region 23 is provided. The p + isolation impurity region 23 is formed at the surface of n - region 5 to surround the planer region of the diode forming region and to be in contact with trench 9. The p + isolation impurity region 23 is made deeper than the trench 9. Except these points, the present embodiment is the same as Embodiment 3. Therefore, corresponding portions are denoted by the same reference characters and description thereof is not repeated. Referring to Fig. 25, the p + isolation impurity region 23 is connected to cathode electrode 17 by an inverted layer formed around gate electrode layer 13, when a negative voltage is applied to gate electrode layer 13. Therefore, the pn junction formed by p + isolation impurity region 23 and n - region 5 is reversely biased. Therefore, main breakdown voltage maintaining capability of the device can be enhanced. According to a semiconductor device of the present embodiment, p type impurity region 23 is formed deeper than trench 9 to surround diode forming region, as shown in Figs. 24 and 25. Therefore, p + isolated region 23 is electrically isolated from the diode at on-state, on-state voltage can be maintained low. And, p + isolated region 23 is electrically connected cathode electrode 17 at off-state, breakdown voltage can be improved. [Embodiment 5] Referring to Figs. 26 to 28, the present embodiment shows an example which has four layered pnpn thyristor. The four layered pnpn diode includes p + collector region 1, an n type buffer region 3, an n - region 5, a p type base region 41 and an n + cathode region 7. These p + collector region 1, n type buffer region 3, n - region 5, p type base region 41 and n + cathode region 7 are stacked successively. From the surface of n + cathode region 7, a trench 9 is formed to reach n - region 5 through n + cathode region 7 and p type base region 41, and to have portions extending parallel to each other. The n + cathode region 7 is formed entirely at the surface sandwiched between the trench 9 extending parallel to each other. The p type base region 41 has peak impurity concentration of from 1 x 10 14 cm -3 to 5 x 10 17 cm -3 , and the n + cathode region 7 has a surface impurity concentration of at least 1 x 10 17 cm -3 . The surface impurity concentration of n + cathode region 7 is higher than the peak impurity concentration of p type base region 41. Other structures are the same as those of Embodiment 1. Therefore, corresponding portions are denoted by the same reference characters and description thereof is not repeated. The method of manufacturing the semiconductor device in accordance with the present embodiment will be described. First, the method of manufacturing of the present embodiment includes the same steps as those of Embodiment 1 shown in Figs. 4 to 8. Thereafter, referring to Fig. 29, p type base region 41 is formed at a portion of the first main surface of n - region 5 sandwiched by parallel trenches 9 by ion implantation and diffusion, for example. The p type base region 41 is formed such that it has peak impurity concentration of 1 x 10 14 cm -3 to 5 x 10 17 cm -3 , and that is shallower than trench 9 and deeper than n + cathode region 7, which will be described later. That is, it is formed to have the depth of 1.0 µm to 15.0 µm, for example. Referring to Fig. 30, n + cathode region 7 is formed by ion implantation and diffusion, for example, at the first main surface sandwiched by trenches 9 extending parallel to each other. The n + cathode region 7 is formed such that it has surface impurity concentration of at least 1 x 10 18 cm -3 and that it is shallower than p type base region 41. Subsequent steps are the same as those of Embodiment 1. Therefore, description thereof is not repeated. The method of operating the semiconductor device in accordance with the present embodiment will be described. On-state is realized by applying a positive voltage to gate electrode layer 13 shown in Fig. 28. When a positive voltage is applied to gate electrode layer 13, the portion of p type base region 41 which opposes to gate electrode layer 13 is inverted to n + region, thus providing a channel and electron current flows. Then, corresponding to the electron current, holes are introduced from p + anode region 1 to n - semiconductor substrate 5, causing conductivity modulation. Further, the hole current eventually enters p base region 41. When this current increases, the potential and p type base region 41 increases, and if the potential becomes larger than the internal potential, the diode provided by p type base region 41 and n + cathode region 7 becomes turned on. Thus, current flows from n + cathode region 7 through p base region 41 directly to n - semiconductor substrate 5. Thus the four layered pnpn thyristor turns on, realizing on-state of the present embodiment. Off-state is realized by applying a negative voltage to gate electrode layer 13 shown in Fig. 28. When a negative voltage is applied to gate electrode layer 13, n + channel, which was formed in the on state, is eliminated, supply of electrons from n + cathode region is stopped, and simultaneously, depletion layer extends from gate electrode layer 13 to n - region 5. Thus, current path is pinched off, and current is reduced. And the device is turn off, when current is smaller than holding current of the thyristor provided by n + cathode 7, p type base region 41, n - region 5, and p + anode region 1. After the main current is cut off, the same breakdown voltage is maintained by the above described p type base region 41. Therefore, in the present embodiment, it is not necessary to apply a gate voltage to maintain off-state. In the present embodiment, gate electrode layer 13 opposes to n - region 5, p type base region 41 and cathode region 7 with insulating layer 11 interposed as shown in Fig. 28. In other words, the gate control method is of voltage controlled type. Therefore, as already described with reference to Embodiment 1, the gate control circuit can be simplified as compared with the current controlled type device. Further, cathode region 7 having a large area is formed at the first main surface sandwiched between the trenches. Therefore, as already described with reference to Embodiment 1, on-state voltage Vf can be reduced. Further, in accordance with the present embodiment, it is not necessary to apply a gate voltage to maintain off-state of the device. Namely, the device has a normally off type structure. Therefore, as compared with a structure which requires continuous application of gate voltage, the gate control circuit can be simplified in the present embodiment. [Embodiment 6] Referring to Figs. 31 to 33, the semiconductor device of the present embodiment differs from Embodiment 5 in that p + isolation impurity region 23 is formed. The p + isolation impurity region 23 is formed to surround planer region of diode forming region and to be in contact with trenches 9. The p + isolation impurity region 23 is made deeper than the trench 9. Except these points, the present embodiment is the same as Embodiment 5. Therefore, corresponding portions are denoted by the same reference characters, and description thereof is not repeated. The method of manufacturing p + isolation impurity region 23 is approximately similar to the method described with reference to Figs. 14 to 16. Therefore, description thereof is not repeated. Referring to Fig. 33, the p + isolation impurity region 23 is connected to cathode electrode 17 by an inverted layer formed around gate electrode layer 13, when a negative voltage is applied to gate electrode layer 13. Therefore, the pn junction formed by p + isolation impurity region 23 and n- region 5 is reversely biased. Therefore, main breakdown voltage maintaining capability of the device can be enhanced. According to a semiconductor device of the present embodiment, p type impurity region 23 is formed deeper than trench 9 to surround diode forming region, as shown in Figs. 32 and 33. Therefore, p + isolated region 23 is electrically isolated from the diode at on-state, on-state voltage can be maintained low. And, p + isolated region 23 is electrically connected cathode electrode 17 at off-state, breakdown voltage can be improved. [Embodiment 7] Referring to Figs. 34 to 36, the semiconductor device in accordance with the present embodiment differs from Embodiment 5 in that a p + contact region 31 is provided. The p + contact region 31 is formed to be adjacent to cathode region 7 with trench 9c or 9d interposed, and is electrically connected to cathode electrode 17. The p + contact region 31 has an surface impurity concentration of at least 1 x 10 17 cm -3 . The p + contact region 31 and n + cathode region 7 are arranged alternately, with the trenches interposed. Further, the number of trenches 9a, 9b, ... extending parallel to each other can be arbitrarily selected. Other structures are the same as those of Embodiment 5. Therefore, corresponding portions are denoted by the same reference characters and description thereof is not repeated. The method of manufacturing the semiconductor device in accordance with the present embodiment will be described. The method of manufacturing in accordance with the present embodiment first includes the same steps as Embodiment 1 shown in Figs. 4 to 8. Thereafter, referring to Fig. 37, p + contact region 31 is formed at the surface of n - region 5 sandwiched between trenches 9b and 9c extending parallel to each other, by photolithography process, ion implantation and diffusion, for example. Referring to Fig. 38, through the same steps as shown in Figs. 30 and 31, p type base region 41 and n + cathode region 7 are formed adjacent to p + contact region 31 with trenches 9b and 9c interposed. Subsequent steps are the same as those of Embodiment 1. Therefore, description thereof is not repeated. In the present embodiment, since p + contact region 31 is formed to be adjacent to n + cathode region 7 with trench 9 interposed, turn-off time can be reduced, as described with reference to Embodiment 3. [Embodiment 8] Referring to Figs. 39 to 41, the semiconductor device in accordance with the present embodiment differs from Embodiment 7 in that p + isolation impurity region 23 is formed. The p + isolation impurity region 23 is provided to surround, two dimensionally, the diode forming region, to be in contact with trench 9. The p + isolation impurity region 23 is formed to be deeper than the trench 9. Other structures are the same as those of Embodiment 7. Therefore, corresponding portions are denoted by the same reference characters and description thereof is not repeated. The method of manufacturing p + isolation impurity region 23 of the semiconductor device in accordance with the present embodiment is the same as the method shown in Figs. 14 to 16 described above. Referring to Fig. 41, the p + isolation impurity region 23 is connected to cathode electrode 17 by an inverted layer formed around gate electrode layer 13, when a negative voltage is applied to gate electrode layer 13. Therefore, the pn junction formed by p + isolation impurity region 23 and n - region 5 is reversely biased. Therefore, main breakdown voltage maintaining capability of the device can be enhanced. According to a semiconductor device of the present embodiment, p type impurity region 23 is formed deeper than trench 9 to surround diode forming region, as shown in Figs. 40 and 41. Therefore, p + isolated region 23 is electrically isolated from the diode at on-state, on-state voltage can be maintained low. And, p + isolated region 23 is electrically connected cathode electrode 17 at off-state, breakdown voltage can be improved. [Embodiment 9] Referring to Figs. 42 to 44, the present embodiment shows an example which includes a diode structure. The diode has a stacked structure of p + collector region 1, an n type buffer region 3, an n - region 5 and an n + cathode region 7. Trench 9 is formed from the surface of n + cathode region 7 through n + cathode region 7 to reach n - region 5. At the substrate surface, p + contact region 62 is provided to be in contact with trench 9. Immediately below p + contact region 62, there is provided n - region 61 to be in contact with trench 9 and p + contact region 62. The p + contact region 62 has surface impurity concentration of at least 1 x 10 17 cm -3 and n - region 61 has impurity concentration of, for example, 1 x 10 12 cm -3 to 1 x 10 17 cm -3 , which is lower than that of n + cathode region 7. Other structures are the same as those of Embodiment 1. Therefore, corresponding portions are denoted by the same reference characters and description thereof is not repeated. The method of manufacturing a semiconductor device in accordance with the present embodiment will be described. Referring to Fig. 45, first, p + collector region 1, n type buffer region 3 and n - region are formed stacked in this order. At the surface of n - region 5, an epitaxially grown layer having low concentration corresponding to n-region 61 is formed, and thereafter selective ion implantation, diffusion and the like are performed, so that an island-shaped n - region 61 is left. Referring to Fig. 46, at a region between n - regions 61, n + cathode region 7 is formed by ion implantation and diffusion, for example. The depth of diffusion of cathode region 7 is made approximately the same as the depth of diffusion of n - region 61. Referring to Fig. 47, at a substrate surface above n - region 61, p + contact region 62 is formed by ion implantation and diffusion, for example. The p + contact region 62 is formed shallower than n + cathode region 7. Referring to Fig. 48, a trench 9a is from the substrate surface to reach n - region 5 through p + contact region 62 and n - region 61. Thereafter, several steps as in Embodiment 1 are carried out, and thus the semiconductor device shown in Fig. 44 is completed. Here, n - region 61 should be formed to have impurity concentration lower than n - region 5. The method of control of the semiconductor device in accordance with the present embodiment will be described. First, on-state is realized by applying a positive voltage to gate electrode layer 13. AT this time, an n type accumulation region 65 having high electron density is formed as trench 9, as shown in Fig. 49. Therefore, present embodiment works in same manner of Embodiment 1. Off-state can be realized by applying a negative voltage to gate electrode layer 13. When a negative voltage is applied to gate electrode layer 13, similar to Embodiments 1 to 8 described above, n + accumulation layer (channel) which is an electron current path is eliminated, thus the current path becomes pinched off, and the device becomes turned off. Further, n - regions 5 and 61 in contact with trench 9 are turned to p + inversion regions. In order to reduce turn-off time, it is necessary to quickly extract minority carriers (here, hole). In the present embodiment, the holes, which are the minority carriers are extracted through the path of p + inversion region and p + contact region 62 generated around trench 9. As already described with reference to Embodiment 2, the turn-off time can be reduced in the present embodiment, also. Referring to Fig. 49, at on-state, there is generated an n type accumulation channel region 65 having high electron concentration around trench 9, and n type accumulation region 65 is regarded as an extension of n + cathode region 7. Namely, it is considered that effective cathode region becomes large. Thus cathode area, which is the area of contact between n + cathode region 7 and n - region 5 is increased. This enhances injection efficiency of electron, and this can reduce on-state voltage Vf. [Embodiment 10] Referring to Figs. 50 to 52, the structure of the semiconductor device in accordance with the present embodiment differs from Embodiment 9 in that p + isolation impurity region 23 is provided. The p + isolation diffusion region 23 is formed to surround, two dimensionally, the diode forming region, and to be in contact with trench 9. The p + isolation impurity region 23 is made deeper than trench 9. The method of manufacturing a semiconductor device in accordance with the present embodiment will be described. The method of manufacturing a semiconductor device in accordance with the present embodiment first includes the same steps as Embodiment 2 shown in Figs. 14 and 15. Thereafter, the step shown in Fig. 45 is performed, and the state of Fig. 53 is attained. Thereafter, similar steps as in Embodiment 1 are performed, and the semiconductor device shown in Fig. 52 is completed. Referring to Fig. 52, the p + isolation impurity region 23 is connected to cathode electrode 17 by an inverted layer formed around gate electrode layer 13, when a negative voltage is applied to gate electrode layer 13. Therefore, the pn junction formed by p + isolation impurity region 23 and n - region 5 is reversely biased. Therefore, main breakdown voltage maintaining capability of the device can be enhanced. According to a semiconductor device of the present embodiment, p type impurity region 23 is formed deeper than trench 9 to surround diode forming region, as shown in Figs. 51 and 52. Therefore, p + isolated region 23 is electrically isolated from the diode at on-state, on-state voltage can be maintained low. And, p + isolated region 23 is electrically connected cathode electrode 17 at off-state, breakdown voltage can be improved. Here, the trench 9 formed in respective embodiments may be arranged concentrically as shown in Figs. 54 to 56, for example. The planer structure shown in Fig. 54 corresponds to Embodiments 2 and 6. The cross section taken along the line L-L' of Fig. 54 corresponds to schematic cross sectional views of Figs. 13 and 33. The planer structure shown in Fig. 55 corresponds to Embodiments 4 and 8. The cross section taken along the line M-M' of Fig. 55 corresponds to schematic cross sectional views of Figs. 25 and 41. The number of trenches 9 shown in Figs. 25 and 41 may be arbitrarily selected. The planer structure shown in Fig. 56 corresponds to Embodiment 10. The cross section taken along the line N-N' of Fig. 56 corresponds to the schematic cross view of Fig. 52. In all the embodiments above, the conductivity types, that is, p an n types may be reversed. In all the embodiments above, n type buffer region 3 and 103 are formed. However, dependent on the rate or desired function of the device, n type buffer region 3 or 103 may be omitted. Further, by changing thickness and impurity concentration of n type buffer region 3, 103, necessary main breakdown voltage, on switching property or the like of the device can be obtained. Further, in the embodiment described above, an example in which entire surface of p + collector region 1, 101 is in contact with anode electrode 19, 123 has been described. However, an n type high concentration region may be electrically connected so as to cause short circuit of a portion of semiconductor substrate 5 or n - region 105 with a portion of anode electrode 19, 123. As the n type region is connected to anode region 19 and 123, electrical characteristic of the diode can be varied. Though the cross sectional shape at the bottom of trench 9 is flat in Embodiments 1 to 9, the cross sectional shape of the bottom of the trench may be rounded. In Embodiments 1 to 10 also, semiconductor device superior in on-state voltage Vf can be obtained by making the depth of trench 9 to be within the range of 5 µm to 15 µm. In each embodiment, if the depth of trench 9 or 113 is at least 10 µm, the on-state voltage Vf can further be reduced. For all the embodiments described above, gate electrode layers 13 and 117 are electrically connected to each other at a region not shown. In each embodiment, gate electrode layer 13, 117 is formed to project upward from the first main surface (cathode surface) of the semiconductor substrate. This facilitates control of etching to form the gate electrode layer, and it also ensures stable device operation. This point will be described in greater details in the following. In the device structure shown in Figs. 100 to 102, gate electrode layer 507 is filled in trench 505. In this case, gate electrode layer 507 is completed by once forming conductive layer entirely over the first main surface of the semiconductor substrate to fill the trench 505 and by performing etch back on the entire surface of the conductive layer. However, if the amount of etching is excessive, gate electrode layer 507 comes not to oppose to a part of or whole n type turn off channel layer 508. In such a case, channel is not generated at n type turn off channel layer 508 even when a voltage is applied to gate electrode layer 507, and hence device does not operate. Meanwhile, in each embodiment, gate electrode 13, 117 have only to be formed to project upward from the first main surface of the semiconductor substrate. This facilitates control of etching. In this case, gate electrode layer 13, 117 completely fills the trench. Therefore, instable operation caused by insufficient generation of the channel can be prevented.

Claims: A semiconductor device including a diode structure in which main current flows between first and second main surfaces sandwiching a first conductivity type semiconductor substrate (5), comprising: a first impurity region (7) of a first conductivity type formed at said first main surface of said semiconductor substrate (5) and having a higher impurity concentration than that of said semiconductor substrate (5); and a second impurity region (1) of a second type, opposite to the first conductivity type, formed at said second main surface of said semiconductor substrate (5); wherein said semiconductor substrate (5) has trenches (9) extending parallel to each other formed at said first main surface to sandwich said first impurity region (7); said device further comprising: a third impurity region (62) of the second conductivity type formed on a sidewall of the trench (9) at said first main surface adjoining to said first impurity region (7); a first electrode layer (17) formed on said first main surface of said semiconductor substrate (5) and electrically connected to said first and third impurity regions (7, 62); and a second electrode layer (19) formed at said second main surface of said semiconductor substrate (5) and electrically connected to said second impurity region; characterized by : a fourth impurity region (61) of the first conductivity type having a lower concentration than said first impurity region (7) and said semiconductor substrate (5), formed immediately below said third impurity region (62) to be in contact with the sidewall of said trench (9) and the region of said semiconductor substrate (5) and adjoining to said first impurity region (7); and a control electrode layer (13) formed in said trench (9) to oppose to said region of said semiconductor substrate (5) and said third and fourth impurity regions (62, 61) with an insulating film (11) interposed. The semiconductor device according to claim 1, further comprising an isolation impurity region (23) of the second conductivity type formed at said first main surface of said semiconductor substrate (5), wherein at one side of outermost one of said plurality of trenches (9) extending parallel to each other, another one of said trenches (9) is positioned, and at the other side, said isolation impurity region (23) is formed in contact with the outermost trench (9) and deeper than said trench (9), said isolated impurity region (23) is not directly connected to said first electrode layer (17).

Inventors: HARADA MASANA, MINATO TADAHARU, NAKAMURA KATSUMI, TAKAHASHI TETSUO, HARADA, MASANA, MINATO, TADAHARU, NAKAMURA, KATSUMI, TAKAHASHI, TETSUO
Applicants: MITSUBISHI ELECTRIC CORP, MITSUBISHI DENKI KABUSHIKI KAISHA
Application year: 1996
Main classification: H01L29
IPC codes: H01L29