A method and system for image generation

Abstract: A system for generating images having display based computation. The system of the present invention divides the image generation process between the display (209) and a host computer system. The computation element of the display includes a rendering mesh comprising a plurality of processing elements. Each processing element of the rendering mesh corresponds to one or more pixels of the display. The host computer system includes a processing means (201) for generating a rendering mesh map (203). The rendering mesh map (203) is used to identify processing elements of the rendering mesh which will receive "seed" pixel values. The rendering mesh map (203) is stored in a rendering mesh map buffer. The "seed" pixel values are stored in a frame buffer and represent an original rendering of an image. When the rendering mesh is seeded, pixel values are determined for the "unseeded" processing elements. The final pixel values are determined from the contents of the corresponding processing elements.

Description: The present invention relates to the field of image generation, in particular to methods and systems which provide discrete processing elements for each pixel in a display. Various methods and architectures exists for generating pixel data for displaying images on a bit-mapped, raster scan display. A bit-mapped, raster scan display is one where each pixel on the display can be independently addressed and driven. Figure 1 illustrates the basic architecture for a bit-mapped display system. An image processor 101 receives image data 100 and renders pixel data 102. The image processor 101 may be a single processor, a string of pipelined processors, an array of processors or be part of a general purpose processor. The image data 100 will be some abstract representation of the image to be displayed. The image processor 101 will then render the image data 100 according to some specified rendering technique. The resulting pixel data 102 is then stored in a frame buffer 103. The frame buffer 103 will typically have at least as many addressable storage locations as there are pixels on a display 104. When the image is ready to be displayed, it is transferred from the frame buffer 103 to the display 104. The values for each pixel in the pixel data 102 are then used to determine the color or intensity emitted by the corresponding pixel. As noted above various architectures exist for generating pixel data. A related architecture to the present invention is described in "Developing Pixel-Planes, A Smart Memory-Based Raster Graphics Systems", Fuchs, et al., Proceedings of the 1982 MIT Conference on Advanced Research in VLSI, 137-146. In Pixel-Planes, a small amount of processing circuitry is added to each pixel storage location of the memory comprising a frame buffer. The Pixel-Planes work utilizes advances in Very Large Scale Integration (VLSI) chip design and fabrication technologies to facilitate rendering of three-dimensional color rendered surfaces. Pixel Planes are further described in US-A-4, 590, 465, US-A-4,827,445 and US-A-4,783,649. In an article entitled "Fast Spheres, Shadows, Textures, Transparencies, and Image Enhancements in Pixel-Planes", Fuchs, et al., Siggraph '85, Volume 19, Number 3 (1985), it is stated that the Pixel-planes architecture is to be integrated with a silicon-based flat-screen display so that display itself would be capable of handling display computations. Another related field is smart optical sensors. Smart optical sensors enable certain image processing functionality for use with image capture devices. One such smart optical sensor is described in "MAPP2200- A Second Generation Smart Optical Sensor", Forchheimer et al., SPIE Vol. 1659 Image Processing and Interchange Pgs 2-11 (1992). In such smart optical sensors, processing circuitry is provided on the same chip as the image capture circuitry. One of the objects of the present invention is to provide a system and method for image generation having a fast rendering speed. Accordingly, the present invention is defined as in the appending claims. A system for image generation having display based computation is disclosed. The system of the present invention divides the image generation process between the display and a host computer system. The computation element of the display includes rendering mesh comprising a plurality of processing elements. Each processing element of the rendering mesh corresponds to one or more pixels of the display. The host computer system includes a processing means for generating a rendering mesh map. The rendering mesh map is used to identify processing elements of the rendering mesh which will receive "seed" pixel values. The rendering mesh map is stored in a rendering mesh map buffer. The "seed" pixel values are stored in a frame buffer and represent an original rendering of an image. The creation of an image in the present invention starts with the rendering of an image. The rendered image is typically stored in the frame buffer of the host computer system. It is assumed that the pixel values are stored at their display coordinates. The display coordinates of the rendered image are then transformed into coordinate addresses of processor elements in the rendering mesh. The transformation that occurs will depend on the desired image processing function. For example, it may be desirable to distort an image prior to display. The rendering mesh is then seeded based on corresponding pairs of pixel values from the frame buffer and coordinate addresses from the rendering mesh map. The rendering mesh will then propagate the seeded pixel values to the remainder of the processor elements based on some flooding methodology. A final value for each pixel is then generated based on the values contained in the processor elements for the corresponding pixels. The display of the present invention is a polysilicon Liquid Crystal Display wherein the pixels and the rendering mesh are fabricated on the same substrate. The placement of processing capacity on the same substrate as the pixel reduces the data transfer bandwidth requirements between the host computer system and the display. Further, such placement enables the use of analog processing techniques for creation of the rendered image. Other advantages of the present invention include faster rendering speeds due to parallel processing and economic benefits resulting from more efficient use of the display substrate. The present invention will be described further, by way of examples, with reference to the accompanying drawings, in which: Figure 1 is a block diagram of a prior art architecture for a bit-mapped display system; Figure 2 is a block diagram of the basic components of the bit-mapped display system of the currently preferred embodiment of the present invention; Figure 3 illustrates the logical relationship between a processor element and a pixel in the currently preferred embodiment of the present invention; Figure 4 illustrates a single pixel and the corresponding processing elements of a rendering mesh in the currently preferred physical embodiment of the present invention; Figure 5 is a block diagram illustrating in greater detail the functional components of a processing element in the currently preferred embodiment of the present invention; Figure 6 is a flowchart illustrating the steps for rendering an image using the bit-mapped display system of the currently preferred embodiment of the present invention; Figure 7 illustrates a transformed image in relation to a processing mesh in the currently preferred embodiment of the present invention; Figure 8 is a state diagram illustrating the states of the processing mesh of the currently preferred embodiment of the present invention; Figure 9 illustrates the spatial location of a group of pixels in display coordinate system; Figure 10 illustrates the group of pixels of Figure 9 after they have been transformed and mapped to a mesh coordinate system of the currently preferred embodiment of the present invention; Figure 11 illustrates a seeded mesh in the currently preferred embodiment of the present invention; and Figures 12 and 13 are diagrams illustrating successive steps in "flooding" a mesh in the currently preferred embodiment of the present invention. A system for image generation having displayed based computation is disclosed. In the following description numerous specific details are set forth, such as the operation of Liquid Crystal Displays, in order to provide a thorough understanding of the present invention. It would be apparent, however, to one skilled in the art to practice the invention without such specific details. In other instances, specific implementation details, such as fabrication processes for polysilicon Liquid Crystal Displays, have not been shown in detail in order not to unnecessarily obscure the present invention. In the foregoing, the term pixel refers to a single light emitting element of a display. The term pixel value refers to a generated or rendered value used by a display to indicate a pixels intensity level. The term subpixel refers to a logical element representing a spatial portion of a pixel and which contains a component of the ultimate intensity value for the corresponding pixel. A grouping of subpixels will correspond to a pixel. The image generation and display system of the currently preferred embodiment is described with reference to Figure 2. Referring to Figure 2, a host computer system is comprised of a processor 201, an internal memory (e.g. ROM and RAM memories), a frame buffer 202 and a rendering mesh map 203 which are connected via bus 205. The bus 205 is for transferring information between the components of the host computer system. It should be noted that the bus 205 would typically be comprised of a plurality of busses, e.g. address, data and control busses and/or a high speed system bus coupled to a lower speed peripheral bus. The processor 201 is used to perform various processing functions for the rendering of image data that results in the pixel data that is stored in the frame buffer 202 and the transformation of image coordinates resulting in the processor element addresses stored in rendering mesh map 203. Storage locations in the frame buffer 202 and rendering mesh map 203 are paired so that a pixel value in the frame buffer 202 is paired with a corresponding address from the rendering mesh map 203. It should be noted that the use of the rendering mesh map 203 is not needed for rendering or manipulating all images. Some images may be rendered and placed in the frame buffer and transferred directly to the display without the display processing that is described below. Further coupled to the bus 205 is a disk drive 206, a keyboard 207, a cursor control device 208 and a display unit 209. Such components are typical for an interactive image generation system. The display unit 209 is comprised of a substrate comprising a plurality of pixels and a mesh of processing elements 210. The logical relationship between pixels and the mesh of processing elements is illustrated in Figure 3. Referring to Figure 3, an array of pixels 301 is comprised of a plurality of pixels. The mesh of processing elements 302 illustrated in Figure 3 are grouped so that a 3 x 3 array of processing elements correspond to each pixel. The processing elements will communicate locally in a square (or alternatively hexagonal) mesh, and each processing element will have at least one writable register. A subset of the processing elements (i.e. one of the processing elements in a group) will have the extra capability to drive the pixels of the display. Further, the processing mesh may also include the capability to control pixels through analog processing techniques. The display of the currently preferred embodiment is implemented using liquid crystal cell technology. Such a display will typically be constructed using polysilicon Very Large Scale Integration (VLSI) fabrication techniques. The design of liquid crystal displays is described in "Liquid Crystal TV Displays: Principles and Applications Of Liquid Crystal Displays", E. Kaneko, KTK Scientific Publishers, 1987. For current polysilicon active matrix liquid crystal displays, each pixel area is comprised of a light valve through which light emanates; and circuitry for controlling the light valve. It is generally acknowledged that device sizes in VLSI technology will continue to shrink. Accordingly, it is anticipated that both the size of the light valve and circuitry will decrease thus enabling the placement of a greater amount of control circuitry on the display substrate. In the currently preferred embodiment, the rendering mesh and the pixel area will reside on the same substrate. Figure 4 illustrates a single pixel area and it's corresponding array of processing elements. Referring to Figure 4, pixel area 401 includes processing elements 402-410. Such processing elements will be enabled to communicate with its horizontal and vertical neighbors. The display characteristics of a pixel (e.g. color or greyscale value) are controlled by a light valve 411. Here, the light valve 411 is controlled by processing element 406. Alternative implementations of the mesh may be used which would time multiplex one processing element per pixel to achieve the effect of the mesh, or, if necessary, a coarser array of processing elements could serve groups (sub-arrays) of pixels. Further, the memory and/or processor elements may also be realized on a separate layer with vias connected to it. Figure 5 is a block diagram illustrating a processing element in greater detail. Referring to Figure 5, a processing element is comprised of a communications controller 501, a register 502, a flooding finite state machine 503 implements and embodies the flooding technique utilized. The state register 504 is used to indicate whether or not the processing element contains a pixel value. The register 502 is coupled to host computer 505 for receiving a seed pixel value. The state register 504 is also coupled to host computer 505 to receive a signal indicating that it has received a seed pixel value. Further illustrated in Figure 5 is additional functionality for the processing elements which generate the final pixel value and control the light valve. When the final pixel value is to be generated, the FSM 503 sends a signal to Pixel Combining FSM 507. The Pixel Combining FSM 507 controls the process for the creation of the final pixel value. The digital pixel values from the various associated processor elements are obtained via Communications Controller 501 and converted into an analog signal via Digital to Analog (D/A) converter 508. The various analog signals are then assembled in assembling means 509. Preferably, the assembling means 509 would perform some form of averaging of the received analog signals. Alternatively, the assembling means may effect an analog computation of a convolution with a Gaussian distribution (which is described in greater detail below). The analog signal from assembling means 509 is then captured through analog sample and hold circuitry 510 and is used for controlling light valve 511. As described above, the assembling means 509 may create the final pixel value by effecting an analog computation of a convolution with a Gaussian distribution . Such analog processing is described in US patent 5 567 971. Such analog processing would typically be embodied as a separate layer within the display. It should be further noted that the pixel values from the various processing elements may also be assembled in the digital domain. In this instance, the assembling means 509 would receive the digital signals from communications controller 501 and combine (e.g. average) them. The resulting digital signal would then be converted to analog form by a D/A converter. The analog signal would then be captured by analog sample and hold circuitry for controlling the light valve. In the foregoing description, various references are made to "mesh processing". This is meant to refer to the net effect of the collective processing performed by the processing elements. As will be described in greater detail below, such mesh processing is analogous to processing performed by neural networks or other highly networked computing environments containing discrete processing components. In the currently preferred embodiment of the present invention, the pixel rendering is split between the host computer system and the rendering mesh contained within the display. The computer system may perform initial rendering, while the rendering mesh performs the final rendering. This is advantageous in that it can lead to reductions in bandwidth requirements between the display and the host computer system. For example, certain manipulations of an image can be performed entirely within the mesh such as distortions or other image processing functions such as the introduction of blurring or fades. Figure 6 is a flowchart illustrating the steps for rendering using the system of the present invention. Prior to the steps of Figure 6, it is assumed that an original version of the image has been rendered or otherwise provided and has been stored in the frame buffer. In some instances, this original version will be displayed. In other instances, the original image may not be what is to be displayed. For example, the image may have been previously rendered and saved as a bit mapped file. In any event, referring to Figure 6, processor element addresses are generated for the desired image and stored in the rendering mesh map, step 601. The generation of the process element addresses is performed by the computer system. The addresses generated will depend on the type of transformation being performed on the original image. Next, pixel values and corresponding processor element addresses are transmitted to the display processing mesh, step 602. The pixel values are stored in the processor element specified by the processor element address, step 603. When this step is completed, it is said the display processing mesh has been seeded with pixel values. Pixel values for each of the "unseeded" processor elements are then generated, step 604. This may be accomplished for example by having processor elements taking on the value of neighboring processor elements. From the pixel values contained in each of the processor elements and the type of rendering to be performed the final pixel values are generated, step 605. For example, the ultimate pixel value may be a simple or weighted average of the pixel values of the processing elements corresponding to the pixel. In any event, mesh processing is described in greater detail below. Computer System Processing Interactive graphical systems allow images to be manipulated. This will typically require a re-rendering of a picture. For example, a graphical system may have a function which allows a user to rotate the view of an image. To accomplish this, spatial transformations are performed to create the new view from an image coordinate system to a display coordinate system. The display coordinate system may be represented as a subpixel coordinate system wherein multiple-subpixels correspond to a particular pixel. The subpixel values are then combined to create the resulting pixel value. The combination method may be simple averaging, weighted averaging or some other technique. As described by Figure 6, the computer system is used to generate the processor element addresses that are stored in the frame buffer map. The generation of processor element addresses will depend on the type of manipulation of the image desired. Generally, the processing will involve a simple perspective transformation of the pixel address of the original image stored in the frame buffer. The transformation function will correspond to the desired manipulation. Such a transformation function may be through a direct computation or via the use of a look-up table and interpolation. The approximate center of each pixel in the transformed image is then mapped to a particular processor element address. This is illustrated in Figure 7. Referring to Figure 7, a representation of the transformed image 701 (illustrated as the angled grid with large squares) is shown in relation to a representation of mesh 702 (illustrated as the horizontal grid with small squares). Each square of the transformed image 701 corresponds to a pixel in the transformed image. Each square in the mesh 702 corresponds to a processing element. Pixel A 703 of transformed image 701 is shown to have an approximate center that lies above a processing element X 704 of mesh 702. Thus, the storage location in the frame buffer map corresponding to the pixel A 703 will contain the address for processing element X 704. Mesh Processing As described above, the mesh is a collection of inter-connected processing elements which are used to generate the final rendering value. The processing described herein will typically occur in parallel. As noted above, the processing elements comprising the mesh are grouped. Each group of processing elements contributes to the rendering of an individual pixel. However, this is not to mean that processing elements cannot communicate with other processing elements that are not within their group. In the present invention, for the purposes of rendering an image, each of the processing elements may be conceptually thought of as a subpixel. Accordingly, various rendering techniques which may utilize the notion of subpixels may be performed using the mesh processing capabilities. Generally, each of the processor elements in the mesh operates in the same fashion. However, one of the processor elements in a group will generate the ultimate pixel value for the group and control the corresponding pixel. In the currently preferred embodiment, the processing elements are only able to communicate with horizontal or vertical neighbors. However, it would be apparent to one of skill in the art to include means for certain processing elements to communicate with diagonal neighbors, or to have processing elements communicate in a hexogonal pattern. Figure 8 is a state diagram overviewing the operation of the mesh. The mesh is initially in an idle state 801. When in the idle state 801 no processing is being performed by the mesh. A seed mesh state 802 is entered upon the receipt of a transmit data signal from the host computer system. During this seeding state, a pixel value and processor element pair is received, and the pixel value stored in the memory of the addressed processor element. In any event, once the mesh has been seeded, a flood mesh state 803 is entered. In the flood mesh state, pixel values for the unseeded processing elements are generated. The manner in which the pixel values for the unseeded processing elements is to assume the value of a "neighbor" processing element which includes some conflict resolution mechanism. This process continues until all of the processing elements have a pixel value. Once each of the processing elements has a pixel value (or an acceptable amount of them have a pixel value), the final pixel value is generated in pixel value generation state 804. As noted above various techniques for combining the subpixel values may be utilized. Example The operation of the present invention is further detailed in Figures 9-13. Referring to Figure 9, a portion of a rendered image is represented by Pixel A 901, Pixel B 902, Pixel C 903 and Pixel D 904 as mapped to (X,Y) coordinates on coordinate system 905. The address for any of the pixels on the coordinate system corresponds to its frame buffer address. The pixel values for the rendered image are stored in the frame buffer. In this example, Pixel A has a pixel value PixA stored at address Xa,Ya, Pixel B has a pixel value PixB stored at address Xb,Yb, Pixel C has a pixel value PixC stored at address Xc,Yc, and Pixel D has a pixel value PixD stored at address Xd,Yd. Now, the image is transformed in the desired manner. The transformation may be an introduced distortion, a scaling of the image or a movement of the image. The transformation can be direct and real-time calculations using look-up tables or the like, or alternatively, the distortions may be predetermined so as to enable the use of precalculated addresses. In any event, this manipulation results in placements of the Pixels A-D on a mesh coordinate system as illustrated in Figure 10. Referring to Figure 10, the Pixel A 901 has been mapped to mesh coordinates Ma,Na, the Pixel B 902 has been mapped to mesh coordinates Mb,Nb, the Pixel C 903 has been mapped to mesh coordinates Mc,Nc, and the Pixel D 904 has been mapped to mesh coordinates Md,Nd. Each of the mesh coordinates is the address of an individual processor element in the mesh. Note that these mesh addresses represent the spatial location of the approximate center of the transformed pixels. As noted above, the frame buffer and the rendering map have the same dimensions. Accordingly, the address Xa,Ya of the rendering mesh map will store the mesh address Ma,Na, the address Xb,Yb will store the address Mb,Nb, the address Xc,Yc will store the address Mc,Nc,and the address Xd,Yd will store the address Md,Nd. When the image is to be transmitted to the display, the pairs will consist of the contents of corresponding locations of the frame buffer and the rendering mesh map. Figure 11 illustrates the rendering mesh after it has been seeded with pixel values. Referring to Figure 11, each block represents a discrete processing element and each of the 3 x 3 squares of processing elements corresponds to a pixel on a display, we see that the value PixA has been placed in a processing element 1101, the value PixB has been placed in processing element 1102, the value PixC has been placed in processing element 1103 and the value PixD has been placed in processing element 1104. Figures 12-13 illustrates a nearest neighbor technique for assigning pixel values for the unseeded processing elements. Referring to Figure 12, the horizontal and vertical neighbors which do not have pixel values take on the neighbors pixel value. Note that this "flooding" of pixel values crosses the 3 x 3 squares indicating the processing elements for a pixel. Figure 13 illustrates another iteration of flooding. This continues until all the processor elements have pixel values. It should be noted that ties, i.e. when multiple neighbors of a processing elements have a pixel value, can be resolved in various fashions. First, ties can be broken arbitrarily. Second, ties can be broken consistently based on the flooding direction (e.g. first flood top neighbors, then bottom, then left, then right) with a bias being intentionally made in the seeding process to compensate. Third, the values of the neighbors could be averaged. The choice of technique used for breaking ties will depend on various factors including the resolution of the rendering mesh. Once each processor element has a pixel value a pixel value is determined by combining the pixel values of the corresponding processing elements. It should be noted that other types of image processing may be performed (e.g. anti-aliasing or image smoothing) . Such image processing would be implemented at each of the processing elements of the rendering mesh.

Claims: A graphical display system comprising: a display (209) having a display substrate, said display substrate having defined therein a plurality of pixels (301) and a rendering mesh (302), said rendering mesh (302) comprising a plurality of pixel rendering groups, each of said plurality of pixel rendering groups comprising a plurality of processing elements (PEs) and receiving a pixel value according to a corresponding processing element address, each of said plurality of processing element groups corresponding to one of said plurality of pixels (301) and each of the processing elements (PEs) corresponding to a subpixel, each of said plurality of pixel rendering groups for generating subpixel values for all subpixels corresponding to said pixel rendering group according to the received pixel value; and a host processing system for providing display information to said display (209), said host processing system further comprising: a rendering means (201) for generating a plurality of pixel data (102) for an original image; a frame buffer (202) coupled to said rendering means (201), said frame buffer (202) for storing said plurality of pixel data (102) for said original image; a transformation means coupled to said frame buffer (202), said transformation means for transforming pixel addresses of said original image into processing element addresses based on a manipulation of said original image and thereby transforming said plurality of pixel data (102) into a plurality of subpixel values, said processing element addresses corresponding to an instance of pixel data (102) in said frame buffer (202); a rendering mesh map (203) coupled to said transformation means, said rendering mesh map (203) for storing said processing element addresses generated by said transformation means; and a transmission means coupled to said frame buffer (202) and said rendering mesh map (203), said transmission means for transmitting said display information to said display (209), said display information comprising pairs of an associated one of said plurality of pixel values from said frame buffer (202) and a corresponding one of said processing element addresses from said rendering mesh map (203). A graphical display system as claimed in claim 1, wherein each of said processing elements (PEs) is comprised of: mesh communication means for transferring pixel values to and from neighboring processing elements (PEs); storage means for storing a subpixel value; a state indicator for indicating if said processing element (PE) contains a subpixel value; and a first processing means for controlling the flooding of pixel values in said rendering mesh (302). A graphical display system as claimed in claim 2, wherein one of said processing elements (PEs) in a pixel rendering group is for controlling a corresponding one of said plurality of pixels (301) and is further comprised of: a light valve (411) for controlling the display characteristics of said corresponding one of said plurality of pixels (301); a second processing means for combining subpixel values of corresponding other processing elements (PEs) to create a final pixel value; and means for converting said final pixel value into a signal for controlling said light valve (411). A graphical display system as claimed in any one of claims 1 to 3, wherein said transformation means is comprised of means for transforming pixel addresses of said original image into processing element addresses based on a distortion of said original image. A method of rendering an image on a display (209) by generating pixel values for displaying an image from a plurality of pixel data (102) for an original image stored in a frame buffer (202) of a host processing system, said display (209) comprising a plurality of pixel rendering groups embedded on a substrate with a plurality of pixels (301), each of said plurality of pixel rendering groups comprising a plurality of processing elements (PEs) and receiving a pixel value according to a corresponding processing element address, each of said plurality of processing element groups corresponding to one of said plurality of pixels (301) and each of the processing elementts (PEs) corresponding to a subpixel, said method comprising the steps of: transforming pixel addresses of said original image into said processing element addresses based on a manipulation of said original image in said host processing system, each of said processing element addresses corresponding to an instance of pixel data (102) in said frame buffer (202); storing said processing element addresses in a rendering mesh map (203) in said host processing system; transmitting each of said instance of pixel data (102) from said frame buffer (202) to an associated one of said plurality of pixel rendering groups of said display (209) using a corresponding one of said processing element addresses from said rendering mesh map (203); and generating subpixel values for all subpixels corresponding to said pixel rendering group of said processing element address according to the received pixel value using said plurality of processing elements (PEs) of said pixel rendering group. A method as claimed in claim 5, wherein said step of creating a set of processing element addresses from said original image is further comprised of the step of performing a mapping of an address space of said frame buffer (202) to an address space of said processing elements (PEs) to achieve a desired effect on said original image when displayed. A method as claimed in claim 6, wherein said desired effect is a distortion of said original image. A method as claimed in claim 6, wherein said step of generating subpixel values for all subpixels (301) corresponding to said pixel rendering group of said processing element address is further comprised of the step of processing elements (PEs) having a subpixel value transmitting said pixel value to neighboring processing elements (PEs) not having a subpixel value. A method as claimed in claim 6, wherein said step of generating subpixel values for all subpixels (301) corresponding to said pixel rendering group of said processing element address is further comprised of the step of generating an average pixel value from the values in neighboring pixel rendering groups.

Inventors: GREENE DANIEL H, MUDGE CRAIG J, GREENE, DANIEL H., MUDGE, CRAIG J.
Applicants: XEROX CORP, XEROX CORPORATION
Application year: 1996
Main classification: G06T15
IPC codes: G06T15, G06T11, G06T3