DIGITAL SUPER-REGENERATIVE DETECTOR RF RECEIVER

Abstract: A digital super-regenerative receiver is provided having an analog (RF) detector (500) and a regenerative oscillator (514). The output of the RF detector (500) is used to generate a digital signal (701) from which the oscillator bias is adjusted, in order to maintain the oscillator start-up time at a fixed level. The circuit senses if the start-up time is earlier or later than the predetermined start-up time and produces an output when the majority of the start times are ahead of the expected start time.

Description: DIGITAL SUPER-REGENERATIVE DETECTOR RF RECEIVER BACKGROUND OF THE INVENTION The invention relates in general to a receiver for the control of equipment which allows operation upon the receipt of a properly coded signal. More particularly, the invention relates to a digital super-regenerative receiver for a security system or to a barrier operator system, such as a garage door operator, employing a transmitter and a receiver. It is well-known to provide radio-controlled garage door operators which include a garage door operator unit having a radio receiver and a motor connected to be driven from the radio receiver. The radio receiver is adapted to receive radio frequency signals or other electromagnetic signals having particular signal character¬ istics which, when received, cause the door to be opened. More recently, such transmitter and receiver systems have become relatively more sophisticated in that they use radio transmitters which employ coded transmissions of multiple or three-valued digits, also known as "trinary bits" or other serial coded transmission techniques. Once such signals are received, a microcontroller is generally used to decode the trinary word. Analog super-regenerative receivers have been known for use in such systems. Super-regeneration is a form of regenerative amplification. In a regenerative receiver, a detector is provided having positive or regenerative feedback from the output to the input. The feedback must maintain operation on the verge of oscillation. In a super-regenerative detector, the circuit is switched into and out of oscillation by an oscillator operating at a very low frequency rate, called the "quench" frequency. That is, the oscillator allows oscillations to build up in the regenerative circuit and then causes them to die out. In the absence of an incoming signal, oscillations are initiated by thermal noise, build up to a critical amplitude and die out. An incoming signal larger than the thermal noise advances the build up time. Thus, the peak is reached sooner, and the oscillations die out sooner. The frequency of interruption increases with signal strength. A detector will provide indication of the incoming signal based on the advance of the build up period. Super-regenerative receivers provide greater sensitivity than other types of receivers. However, most analog super-regenerative receivers require a large number of analog components that are not easily integrated or incorporated into an application-specific integrated circuit (ASIC) . As such, manufacturing costs are relatively high. In addition, such super-regenerative receivers require relatively high current to operate. Thus, they consume more power and decrease battery life. In addition, such super-regenerative receivers do not generally decode the trinary word themselves. Rather, a separate microcontroller is used, which must be kept constantly on. Even if the microcontroller is maintained at a lower-running clock speed, it will still draw current and hence decrease battery life. Also, many super- regenerative receivers require an audio amplifier, thereby increasing system complexity, cost and power consumption. Finally, many super-regenerative receivers are sensitive to variations in transistor characteristics. Accordingly, there is a need for a relatively simple super-regenerative receiver that requires relatively low current and hence draws less power than previous receivers. There is a further need for a super- regenerative receiver that tracks the received signal more quickly than other receivers. There is a further need for a super-regenerative receiver which can be integrated into an ASIC. SUMMARY OF THE INVENTION Accordingly, it is an object of the invention to provide a super-regenerative receiver that tracks more quickly than other receivers and that draws less power than other receivers. It is a further object of the present invention to provide a super-regenerative receiver that obviates the need for a microprocessor for signal decoding. It is a still further object of the present invention to provide a super-regenerative receiver that is relatively insensitive to transistor characteristics. It is a still further object of the present invention to provide a super-regenerative receiver that does not require an audio amplifier. In accordance with one embodiment of the invention, a digital super-regenerative receiver is provided having an analog RF detector and a regenerative oscillator. The output of the RF detector is used to generate a digital signal from which the oscillator bias is adjusted, in order to maintain the oscillator start-up time at a fixed level. The circuit senses if the start-up time is earlier or later than the predetermined start-up time and produces an output signal when the majority of the start times are ahead of the expected start time. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view of an apparatus for moving a barrier . or garage door embodying the present invention; FIG. 2 is a block diagram of a transmitter for use with a garage door operator of FIG. 1; FIG. 3 is a block diagram of a receiver posi¬ tioned within a head unit of the garage door operator shown in FIG. 1; FIG. 4A is a schematic diagram of the clock generator and delays of the receiver shown in FIG. 3; FIG. 4B is a schematic of the RF detector for the receiver shown in FIG. 3; FIG. 4C is a schematic of the phase comparator, oscillator bias and majority detector of the receiver shown in FIG. 3; and FIG. 4D is a schematic of the 3V and 5V interfaces of the receiver shown in FIG. 3. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Referring now to the drawings and especially to FIG. 1, more specifically a movable barrier door operator or garage door operator is generally shown therein and includes a head unit 12 mounted within a garage 14. More specifically, the head unit 12 is mounted to the ceiling of the garage 14 and includes a rail 18 extending therefrom with a releasable trolley 20 attached having an arm 22 extending to a multiple paneled garage door 24 positioned for movement along a pair of door rails 26 and 28. The system includes a hand-held transmitter unit 30 adapted to send signals to an antenna 32 positioned on the head unit 12 and coupled to a receiver as will appear hereinafter. An external control pad 34 is positioned on the outside of the garage having a plurality of buttons thereon and communicate via radio frequency transmission with the antenna 32 of the head unit 12. An optical emitter 42 is connected via a power and signal line 44 to the head unit. An optical detector 46 is connected via a wire 48 to the head unit 12. Referring now to FIG. 2, the transmitter 30 is shown therein in general and includes a battery 70 connected by a pushbutton switch 72 to a power supply 74 which is coupled via leads 75 and 76 to a microcontroller 78. The microcontroller 78 is connected by a serial bus 79 to a non-volatile memory 80. An output bus 81 connects the microcontroller to a radio frequency oscillator 82. The microcontroller 78 produces coded signals when the button 72 is pushed causing the output of the RF oscillator 82 to be amplitude modulated to supply a radio frequency signal at an antenna 83 connected thereto. A block diagram of the receiver is shown in FIG. 3. A master clock 600 enables the bias to RF amplifier 508 and regenerative oscillator 514. When the regenerative oscillator builds to saturation, it terminates 804 the bias enable signal 800. The start up time of the oscillator is shorter when there is a signal present than it is in the presence of noise. A phase comparator 540 monitors the start up time of the oscillator and adjusts the gain of the oscillator via oscillator bias level signal 802 such that the nominal start up time is equal to the reference pulse. If the start up time is shorter than nominal it cuts back the bias. If it is longer, it increases the bias. The phase comparator detects whether the oscillator is starting sooner or later than the nominal start up time and feeds this information to the loop filter and the majority detector. The shift register 548 normally clocks in logical zeroes since its clock signal 555 precedes bias enable 800 by 100 nanoseconds. During reception of the carrier signal, the oscillator starts more quickly. Thus, shift register 548 clocks in logical ones when there is a carrier present instead of logical zeroes. The response of the loop filter 541 is slow enough so that it does not lengthen the oscillator start up time during the bit period. The three-of-five majority detector 550 acts as a low pass filter and provides a clean output waveform with up to two corrupted input data samples. This output is the recovered digital signal. A word detector 696 monitors the rising and falling edges of the majority detector output. If it detects valid trinary word timing, it wakes the microcontroller 700 for complete code recognition. Optionally, a framer 698 may be included that reads one to two entire frames before waking the microcontroller. A schematic of the receiver described above is shown in FIGS. 4A-D. A clock generator 600 (FIG. 4A) generates a regenerative clock signal 602 and a system clock signal 604. Regenerative clock signal 602 is also coupled to a 1.4 microsecond delay 554 for producing an offset to clock signal 602 and a 100 nanosecond delay 556 for producing a second offset signal to clock signal 602 (FIG. 4A) . Delay 554 corresponds to a predetermined nominal reference start up time of the oscillator. The oscillator start up time will be shorter than the nominal time if a carrier signal is present. If only a noise signal is present, the oscillator start up time will be longer than the nominal start up time. Delay 556 on the other hand, represents a permitted signal level above noise which still permits the majority detector to filter out false logical-ones. Jitter of the oscillator start up time due to band limited white noise may cause an unacceptable number of false logical-one bit detections. In particular, delay 556 represents a threshold level of one false logical-ones per ten samples. The three-of-five majority detector is able to filter this level of error. It should be noted that the reference delay and the error delay are exemplary only and that use of other such parameters is within the scope of the present invention. The RF detector 500 generates a digital signal along lead 701 responsive to the input digitally coded radio frequency signal. The input 400 of the RF detector 500 (FIG. 4B) is coupled to a network 502 comprised of an inductance 506 and a capacitor 504 which supply the digitally coded RF signal to an analog amplifier 507 having an NPN transistor 508 at its emitter. The buffer amplifier 507 provides a buffered radio frequency output signal to a reactive network comprising an inductance 510 and capacitor 512. NPN transistor 508 is coupled at its base to clock 602 and delay 554 via NAND gates 750 and 751 through lead 702. The buffer amplifier also isolates the antenna from the noise from the super-regenerative receiver. The base of NPN transistor 508 is pulsed by the clock, turning the transistor on and off in order to save power. These form part of the super-regenerative receiver also having an inductance 520 coupled to analog oscillator 516. The amount of feedback is adjusted using variable capacitance 518. Capacitance 518 and inductance 520 form a tuned circuit tuned to the carrier frequency. Current level detector 522 receives the analog oscillator signal. The output of 522 is a digital signal. The digital signal generator 522 generates pulses which, after being inverted by inverter 524, are delivered to the CLEAR lead 532 of D flip-flop 526 (FIG. 4C) . The regenerative clock signal 602 clocks the D flip flop 526, which holds the digital input stable for the sampling period. The Q output 528, the bias enable signal, of D flip flop 526 is connected to the source 529 of field effect transistor (FET) 534. FET 534 acts as a switch to control the bias level of regenerative oscillator 514. The not Q output of D flip flop 526 is connected to the B input of shift register 528. Shift register 548 is clocked by the regenerative clock 602, after a 1.4 microsecond delay offset 554. Offset 554 provides a nominal reference signal from which the incoming signal is detected. The not Q output 530 of D flip flop 526 is also connected to one input of NOR gate 542. The other input 722 of NOR gate 542 is connected to regenerative clock 602, but only after delay 554 and additional 100 nanosecond delay offset 556. Delay 556 is chosen based on the desired error characteristics of the receiver system. The output of NOR gate 542 and the output of AND gate 544 are fed into quad switches 541 and 543, respectively, of phase comparator 540. AND gate 544 has as its inputs the regenerative clock 602 as well as the not Q output of D flip flop 526 and the delayed regenerative clock at the output of delay 556. Thus, phase comparator 540 compares a delayed clock signal (that is a combination of the offset clock signal resulting from both delay offset 554 and delay offset 556) , with the digital signal output from digital signal generator 522, held by D flip flop 526. In a preferred embodiment, phase comparator 540 includes a pair of 74HC4016 quad switches 541 and 543. The output of phase comparator 540 is connected via lead 538 to the gate 539 of FET 534. Phase comparator 540 detects whether the oscillator is starting sooner or later than the nominal start up time. If it is starting sooner, the output of the phase comparator 540 — the bias level signal — will go negative and cause FET 554 to decrease the bias to regenerative oscillator 514 along lead 536. If the oscillator is starting later than the nominal start up time, the output of phase comparator will go high, causing the bias of oscillator 514 to decrease. That is, a combination clocked and analog bias signal is delivered to the oscillator to stabilize the oscillator timing. The output of AND gate 544 is also coupled to NAND gate 707, the output of which is delivered to the 3 volt and 5 volt interfaces (FIG. 4D) and used for tuning. The digital signal along lead 530, connected to the not Q output of D flip flop 526 is connected to the input of shift register 548. In a preferred embodiment, shift register 548 is an 8 output 74HC164. Shift register 548 normally clocks in logical zeroes, since its clock signal precedes the falling edge of bias enable by 100 ns, the error correction delay 556. However, when a carrier is present, the oscillator 514 starts more quickly and the shift register will clock in logical ones. Thus, the shift register 720 compares the offset delay clock signal 720 with the digital signal and generates a detected code. The outputs of shift register 548 are fed into majority detector 550. The first 902 and seventh 904 outputs are not connected. The last output 712 is provided as raw data to the 3V and 5V interfaces (FIG. 4D) . Majority pulse detector 550 receives the coded signals from shift register 548 and produces an accepted code signal as output when the majority of the outputs 906, 908, 910, 912 and 914 of shift register 548 are high. That is, a positive output will result when the majority of oscillator start times is ahead of the nominal start time and thus, a carrier is present. Output 560 of majority detector 550 is input into D flip flop 552, which is clocked by system clock 604. Outputs 708 and 710 of D flip flop 552 are the data that is fed to the rest of the system, including the microcontroller via the 3 volt and 5 volt interfaces (FIG. 3D) . While there has been illustrated and described a particular embodiment of the present invention, it will be appreciated that numerous changes and modifications will occur to those skilled in the art, and it is intended in the appended claims to cover all those changes and modifi¬ cations which fall within the true spirit and scope of the present invention.

Claims: WHAT IS CLAIMED IS: 1. A receiver for receiving a digitally coded radio-frequency signal from a transmitter, comprising: an RF detector for detecting the digitally coded radio-frequency signal and for generating a digital signal responsive to the digitally coded radio-frequency signal, the RF detector comprising an analog oscillator for generating an analog oscillator signal in response to the digitally-coded radio-frequency signal and a digital signal generator responsive to the analog oscillator signal for producing a digital signal; a clock signal generator for producing a clock signal; a delayed clock signal generator for generating a first offset clock signal and a second offset clock signal in response to the clock signal; a first comparator for comparing the combined first and second offset clock signals with the digital signal and producing a combination clocked and analog bias signal and supplying the combination clocked and analog bias signal to the oscillator to stabilize the oscillator timing; and a second comparator for comparing the first offset signal with the digital signal and generating a detected code signal in response thereto. 2. A receiver according to Claim 1, further comprising a majority pulse detector coupled to receive the detected code signal and for producing an accepted code signal in response to receipt of a predetermined number of code signals. 3. A receiver according to claim 1 further comprising a phase comparator coupled to the analog oscillator to receive the analog signal and to compare the analog signal to a nominal start time and generate an oscillator gain signal in response thereto for controlling the gain of the analog oscillator.

Inventors: SCHLEIFER FRED FREYBLER, SCHLEIFER, FRED, FREYBLER
Applicants: CHAMBERLAIN GROUP INC, SCHLEIFER FRED FREYBLER, SCHLEIFER, FRED, FREYBLER, THE CHAMBERLAIN GROUP, INC.
Application year: 1996
Main classification: H04L27
IPC codes: H03D11, H04B1, H04L27