A GMD (generalised minimum distance) decoding apparatus and method therefor

Abstract: A decoding apparatus generates code words by means of syndrome polynomial, erasure location polynomial, and polynomials indicating error location and size thereof in order to materialize a high speed decoding with a smaller size of memory and a smaller amount of calculations. This decoding apparatus comprises an error location polynomial P k (x) using the product of the syndrome polynomial and the erasure location polynomial as an initial value; a memory unit to store the polynomial Q k (x) to obtain an error number and auxiliary polynomials U k (x) and W k (x); a calculation unit to execute a given plurality of calculations with a plurality of polynomials stored in the memory unit as input in order to output a plurality of polynomials, and a control unit to update the polynomials stored in the memory unit by the output of the calculating unit, and to decide on the input and output relations of the calculation unit in accordance with the d-2th coefficients d k and b k of the polynomials Q k (x) and W k (x).

Description: The present invention relates to a decoding apparatus and a method therefor that use error correcting codes on the reception side in order to correct errors generated in the communication path or memory medium of the digital communication system and digital memory system. More particularly, the invention relates to a decoding apparatus and a method therefor that use the information of communication path for transmission code words to approximately perform a maximum likelihood decoding. The decoding method of error correction codes is classified into a hard decision decoding and a soft decision decoding. The hard decision decoding is a method for correcting errors in the digital system that decides on reception signals by "0" or "1". Since the structure of the decoding apparatus can be made simple, this method is widely adopted for use of a CD (Compact Disk) and many others. On the other hand, the soft decision decoding is to acquire the analogue weights that indicate reliability of decisions in addition to the digital system that makes decisions on the reception signals by "0" or "1", and to utilize such weights for correction of errors in accordance with situations. Therefore, although the decoding process of this method is complicated, it is possible to bring a sufficient capability of error correction codes, and to enhance the SN ratio by 2 to 3 dB as compared with the hard decision decoding. The GMD (Generalized Minimum Distance) decoding method given below is one of the soft decision decoding methods. This is known as a decoding method capable of approximately performing the maximum likelihood decoding by use of the analogue weights thereof. [GMD Decoding Method] With respect to each of the symbols of reception system R of a code length n = (R 0 , R 1 , ..., R n-1 ), the analogue weights that indicate reliability are defined as e = ( 0 ,  1 , ...,  n-1 ). However, provided that 0 ≤  i ≤ 1, it is assumed that the symbol R i of the reception system R is more reliable than the symbol R j if the  i >  j . Also, the function X(a, b) is defined as x(a, b) = 1 if a = b x(a, b) = -1 if a ≠ b and then, the inner product of R•C of the reception system R = (R 0 , R 1 , ..., R n-1 ) and the code word C = (c 0 , c 1 ..., c n-1 ) is defined as follows: Here, given the minimum distance as d, the reception system R that satisfies the inequality (3) given below can be corrected: this is established by G.D.Forney, Jr in the "Concatenated Codes", MIT Research Monograph No. 37, MIT Press (1966), and R.E.Blahut in the "Theory and Practice of Error Control Codes", Addison-Wesley Publishing Company,Inc. (1983). R • C > n - d Therefore, if the process formed by the following four steps is repeated finitely, it is possible to find out a reception system R that satisfies the formula (3), and to make decoding correctly: Step 1: In a reception system R, symbols are erased by j symbols (the initial value being 0) in order of those having smaller analogue weights, and a test system R' is generated, where the hard decisions are made on the symbols other than those erased. Step 2: The code word C' whereby the hard decision decoding is executed is obtained with respect to the test system R'. If no correction is possible, the process will proceed to Step 4. Step 3: Whether or not the inner product, R•C', of the reception system R and the code word C' satisfies the inequality (3) is determined. If the inequality is satisfied, the code word C' is output. If not, the process will proceed to the step 4. Step 4: The process goes to the step 1 after j = j + 2. However, if j ≥ d, it indicates a case where an error is caused to exceed the error correcting capability. Therefore, such error is detected. In this way, it is possible to correct the maximum errors of d - 1 by the application of a GMD decoding, and to implement an error correction having its correcting capability two times that of the hard decision recording. Nevertheless, this Forney's GMD decoding requires the hard decision decoding of maximum (d-1) / two times. Therefore, compared to the hard decision decoding that needs decoding only once, the Forney's takes a longer processing time or needs the provision of a decoder having a larger circuitry. As a result, this decoding has not been put in practice very often eventually. Under such circumstances, E.R.Berlekamp has proposed a remainder decoding that uses a remainder polynomial formulated by dividing a reception system by a code generating polynomial. E.R.Berlekamp shows in the "Faster bounded distance decoding" presented at San Diego ISIT' 90 (1990) that if this remainder decoding method is applied to a GMD decoding, there is a possibility that the amount of calculation required therefor is reduced significantly. Furthermore, L.R.Welch and E.R.Berlekamp have proposed the Welch-Berlekamp (WB) algorithm in the specification of "Error correction for algebraic block codes" (U.S.Patent 4,633,470). In accordance with this proposal, it is anticipated that an effective implementation of a GMD decoding is possible by means of WB algorithm performed only once without the repetition of the hard decision decoding of (d-1) / 2 times maximum. However, the GMD decoding method that uses this remainder decoding should adopt the generalized syndrome polynomial S (x) to be defined by the formula (4) given below as its syndrome polynomial. Therefore, as compared to the syndrome polynomial S (x) to be defined by the conventionally known formula (5), there is a disadvantage that the proposed method needs a complicated process in order to obtain its syndrome polynomial. However, b is an arbitrary integer. As against this method, Okawara, Iwamura, and Imai have proposed a decoding method whereby to perform a GMD decoding by means of the conventional syndrome polynomial defined by the formula (5) (Okawara, Iwamura, and Imai: "On the subject of GMD decoding by means of the conventional syndrome", the 16th Symposium on Information Theory and Its Application, W22-1, 1993). However, whereas the calculation of the syndrome polynomial is easier, there is a need for the adoption of an algorithm, which is more complicated than the WB algorithm. Later, Kamiya has proposed an algorithm given below, which uses the conventional syndrome polynomial to be defined by the formula (5), but the amount of its calculation still remains substantially the same as that of the WB algorithm (Kamiya: "On the subject of the composition of a shift register that generates Reed-Solomon codes for a GMD decoding, and a multiple system", Shingaku Technical Report IT93-113, PP. 43-48, 1994/3). Of the conventional GMD recording methods, this Kamiya's GMD decoding is effective because of the smallest amount of calculation required. Now, with reference to Fig. 13, this decoding method will be described. [GMD Method Proposed by Kamiya] Step S101: For the reception system R i (i = 0, ..., n-1), the weights  i (i = 0, ..., n-1) that indicate reliability are provided, and then, in order of lower reliability, the symbols are positioned at h 0 , ..., h d-2 , hence making X j = α hj . Step S102: The ordinary syndrome polynomial is worked out to get S d-2 (x). Further, the next syndrome polynomials S k-1 (x) (k = d-2, ..., 0) are calculated and held. Step S103: The initial value is defined: k = 0, P 0 (x) = 1, U 0 (x) = 0, L 0 = 0, V 0 (x) = 0, T 0 (x) = S -1 (x), (However, if L k = 0, then b k = -1.) Step S104: Steps S105 and S106: if (d k = 0) then L k+1 = L k P k+1 (x) = P k (x) U k+1 (x) = (x - x k ) • U k (x) T k+1 (x) = T k (x) / (x - x k ) V k+1 (x) = V k (x) Step S105, and steps S107 to S109: if (d k ≠ 0) then if (b k ≠ 0and2 • L k ≥ k + 1) then L k+1 = L k P k+1 (x) = P k (x) - (d k /b k ) • U k (x) U k+1 (x) = (x - x k ) • U k (x) T k+1 (x) (T k (x) - (d k /b k ) • V k (x) ) / (x - x k ) V k+1 (x) = V k (x) else L k+1 = L k + 1 P k+1 (x) (x - x k ) • P k (x) U k+1 (x) = U k (x) - (d x /b k ) • P k (x) T k+1 (x) = T k (x) V k+1 (x) = (V k (x) - (d k /b k ) • T k (x) ) / (x - x k ) Steps S110 and S111: k = k + 1; if (k < d-1) then go to Step S104. Step S112: for (k = 0 ··· d - 2) do if (deg P k (x) ≦ k/2) then N k (x) = P k (x) • λ k-1 (x) for (i = 0 ··· n - 1) do if (N k (x) (α i ) =0) then c k,i = R i + T k (x) (α i ) / (α i(d-1) • N k ' (α i )) Steps S113 to S115: Whether or not the inner product R • C k of the reception system R and the code words C k = [c k,0 , ..., c k,n-1 ] (k = 0, ..., d - 2) satisfies the inequality (3) is determined. If the inequality is satisfied, the code word C k is output. If no inequality is satisfied at all, an error that exceeds the error correcting capability occurs. Therefore, the detection of such error is executed. (The end) However, in the step S102, the S d-2 (x) is given as b ± j = d - 2 - j in the formula (5). Also, the P k (x) is an error location polynomial. The T k (x) corresponds to an error number polynomial. The U k (x) and the V k (x) are the auxiliary polynomial thereto. Also, between each of the polynomials, the following relationship is present: T k (x) = P k (x) • S k-1 (x) mod x d-1 V K (x) = U k (x) • S k-1 (x) mod x d-1 Also, the λ k (x) is an erasure location polynomial, which is defined by the following formula: Also, the P k,j , U k,j , and S k,j express the jth coefficients of the P k (x), U k (x), and S k (x), respectively. Nevertheless, the algorithm described above requires d numbers of syndrome polynomials, S d-2 (x) to S -1 (x), which should be calculated and held in the step S102 in advance for the use of the calculation of the formula (7) in the step S104. Therefore, a problem is encountered that as compared to the other GMD decodings, this decoding needs a greater size of memory. Also, for the Kamiya's GMD decoding, d k and b k are required in order to calculate the P k+1 (x), and U k+1 (x), and for the calculation of the d k and b k , it is necessary to prepare all the coefficients, p k,j (j = 0, ..., L k ) of the P k (x) and the U k (x). Therefore, as shown in Fig. 10, the d k and b k are the values obtainable only after the calculations of the P k (x) and U k (x). As a result, it is only when the calculations of the P k (x) and U k (x) are completed that the calculation of the P k+1 (x) and U k+1 (x) begin. Consequently, even if the calculations of P k (x) and U k (x) or d k and b k are executed by one clock, for example, there is a need for a clock of approximately 2 • (d - 1), because these calculations use its result each other. It is impossible to work out the P k+1 (x) and U k+1 (x) and the P k (x) and U k (x) in parallel. The same is applicable to the calculations of T k+1 (x) and V k+1 (x) and T k (x) and V k (x). It is an object of one aspect of the invention to provide a GMD decoding method and an apparatus thereof using the usual syndrome polynomials without calculating and holding meany syndrome polynomials, and capable of calculating them in a smaller amount of calculation than that of the aforesaid Kamiya's decoding method. It is an object of another aspect of the invention to provide a GMD decoding method and an apparatus thereof capable of implementing a parallel processing easily, which is difficult for the conventional GMD methods to attain, and of making a high speed decoding by means of such parallel processing. According to one aspect, the present invention relates to a decoding apparatus comprising: means for generating a syndrome polynomial (S(x)) from a received sequence (R i ); means for generating an erasure location polynomial (λ(x)) in accordance with reliability of each of the symbols of the received sequence; polynomial multiplication means for multiplying the syndrome polynomial and the erasure location polynomial so as to output the result of multiplication as a product polynomial (S 0 (x)); memory means for storing a plurality of polynomials (P i (x), U i (x), Q i (x), W i (x)) including a polynomial (Q i (x)) having the product polynomial as the initial value; calculation means for executing respective one of a plurality of predetermined calculations for the plurality of polynomials stored in said memory means and updating the plurality of polynomials in said memory means by the result of the calculation; control means for deciding the respective one of the plurality of predetermined calculations for each of the plurality of polynomials and controlling said calculation means to execute the decided calculations on the plurality of polynomials; means for sequentially generating code words by use of the received sequence, the plurality of polynomials output from said calculation means, and the erasure location polynomial; and determination means for determining whether or not the generated code words and the received sequence satisfy a given condition, and outputting the word found as satisfying the given condition as the result of decoding, characterised in that, said control means is adapted to fetch coefficients of a predetermined one degree from respective of specific two polynomials (Q i (x), W i (x)) stored in said memory means, check values of the fetched coefficients, and decide the respective one of the plurality of predetermined calculations for each of the plurality of polynomials on the basis of the result of the check. According to another aspect, the present invention relates to a decoding method comprising the following steps of: generating a syndrome polynomial (S(x)) from a received sequence (R i ); generating an erasure location polynomial (λ (x)) in accordance with reliability of each of the symbols of the received sequence; multiplying the syndrome polynomial and the erasure location polynomial so as to output the result of multiplication as a product polynomial (S i (x)); storing in a memory a plurality of polynomials (P i (x), U i (x), Q i (x), W i (x)) including a polynomial (Q i (x)) having the product polynomial as the initial value; deciding a respective one of a plurality of predetermined calculations for each of the plurality of polynomials in said memory; executing the selected respective one of the plurality of predetermined calculations for the plurality of polynomials stored in said memory and updating the plurality of polynomials in said memory by the result of the calculation; sequentially generating code words by use of the received sequence, the plurality of polynomials output from said calculation means, and the erasure location polynomial; and determining whether or not the generated code words and the received sequence satisfy a given condition, and outputting the word found as satisfying the given as the result of decoding, characterized in that, in said decoding step, coefficients of a predetermined one degree are fetched from respective of specific two polynomials (Q i (x), W i (x)) stored in said memory, and the respective one of the plurality of predetermined calculations for each of the plurality of polynomials are decide on the basis of the result of the check. Embodiments of the present invention will now be described with reference to the accompanying drawings. Fig. 1 is a block diagram which shows the structure of a polynomial operation circuit for a decoding apparatus embodying the present invention; Fig. 2 is a block diagram which shows the structure of a polynomial operation circuit embodying the present invention; Fig. 3 is a block diagram which shows a circuit structure of a decoding apparatus embodying the present invention; Fig. 4 is a block diagram which shows another circuit structure of a decoding apparatus embodying the present invention. Fig. 5 is a view which shows the calculation order of polynomials for a decoding apparatus embodying the present invention. Fig. 6 is a view which shows the calculation order of polynomials for a decoding apparatus embodying the present invention. Fig. 7 is a block diagram which shows the structure of a digital communication system. Fig. 8 is a block diagram which shows the structure of a digital memory system. Fig. 9 is a block diagram which shows the structure of an apparatus that executes a decoding method embodying the present invention by means of a software. Fig. 10 is a view which shows the calculation order of polynomials for a decoding apparatus in accordance with the prior art. Fig. 11 is a view which shows the calculation order of polynomials for a decoding apparatus in accordance with the prior art. Fig. 12 is a flowchart which shows the decoding procedures embodying the present invention. Fig. 13 is a flowchart which shows the decoding procedures in accordance with the prior art. At first, the theorems utilized for the present embodiment will be described as given below. Theorem 1: The multiplicative polynomial of the above formula is defined as Q k (x) = S k (x) • P k (x) mod x d-1 . In this case, the coefficient of x d-2 for the Q k (x) is as follows: Verification: The coefficient q k d-2 of the x d-2 for the Q k (x) is i + j = d - 2, that is, the following is obtainable from i = d - 2 - j: Therefore, q k,d-2 = d k (The end of the verification) Theorem 2: If P k+1 (x) = a 0 • P k (x) - a 1 • U k (x), then the Q k+1 (x) = (a 0 • Q k (x) - a 1 • W k (x)) / (x - x k+1 ) However, it is assumed that W k (x) = U k (x) • S k mod x d-1 . Verification: From the formula (6), S k+1 (x) = S k (x) / (x - x k+1 ) Therefore, Q k+1 (x) = P k+1 (x) • S k+1 (x) mod x d-1 = (a 0 • P k (x) - a 1 • U k (x)) • S k (x) / (x - x k+1 ) = (a 0 • Q k (x) - a 1 • W k (x) ) / (x - x k+1 ) (The end of the verification) From the theorem 1, it is equally clear that the d-2th coefficient for the multiplicative polynomial W k (x) of the S k (x) and the U k (x) is b k . Therefore, the d k and b k are the d-2th coefficients of the Q k (x) and W k (x). Also, from the theorem 2, it is anticipated that the calculations of the Q k+1 (x) and W k+1 (x) are possible by use of the Q k (x) and W k (x), together with the calculations of the P k+1 (x) and U k+1 (x) if it is taken into account that the (a 0 , a 1 ) = (x - x k , 0), (a 0 , a 1 ) = (1, d k / b k ). Also, from the formulas (6) to (8), the following relations are clear: T k (x) = Q k (x) • (x - x k ) V k (x) = W k (x) • (x - x k ) Therefore, instead of the T k (x) and V k (x), the Q k (x) and W k (x) is calculated to obtain the d k and b k as the d-2th coefficients of the Q k (x) and W k (x). Hence, it becomes unnecessary to make the calculation in the step S104. The T k (x) and V k (x) are easily obtainable from the Q k (x) and W k (x) by means of the formulas (14) and (15). Each of the coefficients of d numbers of syndrome polynomials, S k (x) (k= -1, ... , d - 2), is used only for the step S104. Consequently, with the omission of the calculation in the step S104, it will suffice if only one syndrome polynomial is calculated in the step S102 in order to obtain the initial value required for the execution of the step S103. There is no need for calculating and holding any other syndrome polynomials. Therefore, a GMD decoding can be executed in accordance with the procedures given below. [Embodiment 1] At first, the algorithm that brings out the P k (x) and Q k (x) from one syndrome polynomial, S 0 (x), will be shown as follows: 1) The initial values are defined: k=0, P 0 (x)=1, U 0 (x)=0, L 0 =0, W 0 (x)=0, Q 0 =S 0 (x) (However if L k = 0, then b k = -1.) 2) The d-2th coefficients of the Q k (x) and W k (x) are defined as d k and b k . 3) if (d k = 0) then L k+1 = L k P k+1 (x) = P k (x) U k+1 (x) = (x - x k ) • U k (x) Q k+1 (x) = Q k (x)/(x - x k+1 ) W k+1 (x) = W k (x)•(x - x k )/(x - x k+1 ) 4) i f (d k ≠ 0) then i f (b k ≠ 0 and 2 • L k ≧ k + 1) then L k+1 = L k P k+1 (x) = P k (x) - (d k /b k ) • U k (x) U k+1 (x) = (x - x k ) • U k (x) Q k+1 (x) = Q k (x) - (d k /b k ) • W k (x)) / (x - x k+1 ) W k+1 (x) = W k (x) • (x - x k )/(x - x k+1 ) else L k+1 = L k + 1 P k+1 (x) = (x - x k ) • P k (x) U k+1 (x) = U k (x) - (d k /b k ) • P k (x) Q k+1 (x) = Q k (x) • (x - x k )/(x - x k+1 ) W k+1 (x) = (W k (x) - (d k /b k ) • Q k (x)) / (x - x k+1 ) 5) k = k + 1 ; if (k < d - 1) then go to 2 (The end) It is clear that this algorithm can be implemented in accordance with hardware whose structure is shown in Fig. 9. In Fig. 9, a reference numeral 91 designates an input unit for inputting data on the target processing and defining the initial values of parameters; 92, a CPU for executing programs; 93, an output unit for outputting the results of processes; 94, a program memory for storing various programs including the algorithm described above; 95, a work memory for storing data and others temporarily; and 96, a bus connecting each of the units. Also, one example of this algorithm implemented by use of hardware is shown below. The following four kinds of calculations are executed for the algorithm described above by the formulas (19) to (22): A k+1 (x) = (x - x k ) • A k (x) A k+1 (x) = A k (x) - (d k /b k ) • B k (x) A k+1 (x) = (A k (x) - (d k /b k ) • B k (x) ) / (x - x k+1 ) A k+1 (x) = A k (x) • (x - x k )/(x - x k+1 ) However, the formula, Q k+1 (x) = Q k (x) / (x - x k+1 ), in the third algorithm described above corresponds to the case where A k (x) = Q k (x) and B k (x) = 0 in the process of the formula (21). Further, in the algorithm described above, the processes of the formulas (19) to (22) are not overlapped in any one of the cases. Therefore, it is possible to arrange this algorithm by means of an apparatus whose structure is as represented in the block diagram 1. Here, a reference numeral 100 designates an operation unit that executes the calculations of the formulas (19) to (22); 110, a memory unit for storing each of the polynomials temporarily; 120, a controller that fetches d k and b k from the memory unit 110, and calculates L k and k to make a decision to prepare an output from the memory unit 110, thus making it an input of the operation unit 100 for arranging a distribution in accordance with the "if statement" in the aforesaid algorithm. However, even when the B k (x) = 0 as described above, this controller 120 distributes it to the operation unit 100 as an input. Here, each of the polynomials and the initial values represented in the algorithm 1) may be provided for the controller 120 in advance, stored in the memory unit 110, kept in the initial state for the operation unit 100, or provided from the outside source. Also, as described later, the algorithm described above can be processed in parallel. Therefore, as shown in Fig. 2, the operation unit is not necessarily limited to only one. It may be possible to arrange a plurality of the same operation units 100. The operation of the circuit shown in Fig. 1 can be performed as given below, for example. The initial value of each of the polynomials is stored in the memory unit 110 in advance. Then, it is assumed that O is given to the controller 120 as the initial values of k and L k . At first, the memory unit 110 outputs each of the polynomials. Then, the controller 120 fetches the d-2nd coefficients d k and b k of the output values, Q k (x) and W k (x), of the memory unit, and make decisions. For example, if d k ≠ 0 and b k ≠ 0, while 2 • L k ≥ k + 1, then the controller controls the output P k (x) from the memory unit so as to be inputted into means for processing the formula (20); U k (x) into the formula (20) and formula (19); Q k (x) into the formula (21); and W k (x) into the formula (22), respectively. As soon as each of the processes thus distributed is completed, the operation unit 100 outputs each result to the memory unit 110. The memory unit 110 again outputs each of the polynomials immediately when the preceding processes are completed in the operation unit 100. At this juncture, the controller 120 increments the k. (In this case, however, the L k+1 = L k . Therefore, the controller 120 does not increment the L k . If the L k+1 = L k +1, then the controller increments L k to make it L k+1 .) Thereafter, the same processes are repeated until k = d - 1. Also, in Fig. 2, as soon as the coefficients corresponding to the d k and b k of the Q k (x) and W k (x) are calculated by and output from one of the operation units 100, for example, the controller 120 uses the other empty operation unit 100 to operate the calculations of the Q k+1 (x), W k+1 (x), and U k+1 (x), and repeats such operations, while incrementing k (and L k if required). This arrangement is to materialize the operation shown in Fig. 5, which will be described later. For the arrangement described above, it is assumed that the operation units 100 make calculations by use of the direct formulas (19) to (22) in order to make the description simpler. However, the arrangement is not necessarily limited to this example. It will suffice if only operation units 100 should be able to apply the formulas (19) to (22) to its calculation ultimately. Also, it is arranged to enable the memory unit 110 to input and output each of the polynomials at the same time, but it may be possible to arrange so that the input and output are made in order per polynomial. In this case, the operation unit 100 may be structured with a general-purpose unit capable of executing calculations by one processing unit by the application of the formulas (19) to (22). Now with reference to a flowchart shown in Fig. 12, the description will be made of a new decoding method that performs a GMD decoding for each reception system R i (i = 0, ..., n-1) by the utilization of the algorithm described above. Step S201: With respect to the reception system R i (i = 0, ..., n-1), the weights  i (i = 0, ..., n-1) that indicate reliability are given. In order of lower reliability, symbols are positioned at h 0 , ..., h d-2 , and then, it is arranged that x k = α hk . Step S202: The following syndrome polynomial, S (x) is calculated, and then, it is made S o (x) by the multiplication of λ 0 (x): S 0 (x) = λ 0 (x) • S (x) Step S203: k = 0, P 0 (x) = 1, U 0 (x) = 0, L 0 = 0, W 0 (x) = 0, Q 0 (x) = S 0 (x), (However, if L k = 0, then b k = -1.) Step S204: It is assumed that the d-2th coefficients of Q k (x) and W k (x) are d k and b k . Steps S205 to S206: if (d k = 0) then L k+1 = L k P k+1 (x) = P k (x) U k+1 (x) = (x - x k ) • U k (x) Q k+1 (x) = Q k (x) / (x - x k+1 ) W k+1 (x) = W k (x) • (x - x k )/(x - x k+1 ) Steps S207 to S209: if (d k ≠ 0) then if (b k ≠ 0 and 2 • L k ≧ k + 1) then L k+1 = L k P k+1 (x) = P k (x) - (d k / b k ) • U k (x) U k+1 (x) = (x - x k ) • U k (x) Q k+1 (x) = (Q k (x) - (d k / b k ) • W k (x) / (x - x k+1 ) W k+1 (x) =W k (x) • (x - x k )/(x - x k+1 ) else L k+1 = L k + 1 P k+1 (x) = (x - x k ) • P k (x) U k+1 (x) = U k (x) - (d k /b k ) • P k (x) Q k+1 (x) = Q k (x) • (x - x k )/(x - x k+1 ) W k+1 (x) = (W k (x) - (d k / b k ) • Q k (x) ) / (x - x k+1 ) Steps S210 and S211: k = k + 1 ; if (k < d - 1) then go to Step S204 Step S212: for (k = 0 ··· d - 2) do i f (deg P k (x) ≦ k/2) then N k (x) = P k (x) • λ k - 1 (x) for (i = 0 ··· n - 1) do if (N k (x) (α i ) = 0) then c k,i = R i + (α i - α hk ) • Q k (x) (α i ) / (α i(d-1) • N k ' (α i )) Steps S213 to S215: Whether or not the inner product R•C k of the reception system R and the code words C k = [c k,0 , ..., c k,n-1 ] (k = 0, ..., d-2) satisfies the inequality (3). If the inequality is satisfied, the code word C k is output. If all the inequalities are not satisfied, an error that exceeds the error correcting capability has taken place. Thus, such error is detected. (The end) As compared with the Kamiya's decoding method, this decoding can omit the second calculation in step 102 (Equation 6 above). As a result there is no need for the storage of each of the syndrome polynomials. The size of memory can be smaller. Further, as its calculation can be omitted, it is clear that the amount of calculations is also smaller. It is also clear that this decoding method can be implemented by use of software. Meanwhile, one example is given below, in which a decoding apparatus capable of implementing this decoding by means of circuitry is described. Here, it is assumed that the reception system R i (i = 0, ..., n-1) and the x k (k = 0, ..., d - 2) corresponding to its reliability are provided in the step 1 of the decoding method described above before the execution of this decoding. Further, in step 2, the circuit 31 for generating the syndrome polynomial S (x), the circuit 32 for generating the error location polynomial λ o (x), and the circuit 33 for generating the syndrome polynomial S 0 (x) arranged by multiplying these polynomials are the circuits for executing the processes by means of the usual erasure correction. Therefore, it is possible to form these circuits with the known structures. Also, in the step S212, the circuit 35 for obtaining the error and erasure locations and error values is of the same structure of the usual error and erasure locations. Therefore, it is also possible to arrange this circuit with the known structure. (However, although the portion where the c k,i are obtained is slightly different from the Kamiya's GMD decoding due to the formula (14), it is possible to make this formation by means of a simple multiplication of a scalar quantity.) Also, the determining circuit 37 in the step S213 is the same as in the conventional GMD decoding. Then, the processes in the steps S203 to S211 can be executed by the circuit 34 for generating the polynomials shown in Fig. 1. As a result, this decoding method is structured by means of the circuit as shown in the block diagram in Fig. 3. However, the delay circuit 36 shown in Fig. 3 is used for causing the reception system to be delayed temporarily for making corrections. This delay circuit can be formed by known structure comprising a RAM or the like, which is performed by FIFO or address controlling. [Embodiment 2] The S (x) includes any one of the cases defined by the formula (5). Therefore, the present invention is not limited to the examples shown in the Embodiment 1 and Embodiment 2. For example, if b ± j = j in the formula (5), the syndrome polynomial is expressed as given below. Also, there is a case where the λ k (x) of the formula (13) is defined as given below. In this case, the S k (x) = S (x) • λ k (x) can be expressed as given below by use of the coefficient S k,j of the S k (x) shown in the Embodiment 1. Also, the P k (x) can be defined as given below. Therefore, the dk becomes the d-2-k+L k th coefficient of the Q k (x) by means of Q k (x) = S k (x) • P k (x)mod x d-1 = ΣΣp k,j • s k,d-2-i • x d-2-k+1+Lk-j . This does not mean that the d k is limited to the d-2th coefficient of the Q k (x) if the definitions of the S k (x) and P k (x) change in the theorem 1, but it means that the d k becomes a certain coefficient of a given degree of the multiplicative polynomial Q k (x) of the S k (x) and P k (x). To the b k , the same is applicable. Therefore, the present invention includes all the cases where each of the polynomials is worked out by certain coefficients of the Q k (x) and W k (x), which become the Q k (x) = S k (x) • P k (x) mod x d-1 and W k (x) = S k (x) • U k (x) mod x d-1 , irrespective of the definitions of the S k (x) and P k (x). Here,however, the theorem 2 does not change. Now, the algorithm of the GMD decoding, which is defined by the formulas (23) to (26), will be described. Step S301: With respect to the reception system R i (i = 0, ..., n - 1), the weights  i (i = 0, ..., n - 1) that indicate reliability are given, and in order of lower reliability, each of the symbols is positioned at h 0 ..., h d-2 to make x k = α hk . Step S302: The syndrome polynomial given below is worked out, and further, multiplied by λ 0 (x). S 0 (x) = λ 0 (x) • S (x) Step S303: k = 0, P 0 (x) = 1, U 0 (x) = 0, L 0 = 0, W 0 (x) = 0, Q 0 (x) = S 0 (X), (However, if L k = 0, the b k = -1.) Step S304: The d-2-k+L k th coefficients of the Q k (x) and W k (x) are defined as d k and b k . Steps S305 and S306: if (d k = 0) then L k+1 = L k P k+1 (x) = P k (x) U k+1 (x) = (x - x k ) • U k (x) Q k+1 (x) = Q k (x) / (x - x k+1 ) W k+1 (x) = W k (x) • (x - x k )/(x - x k+1 ) Steps S307 to S309: if (d k ≠ 0) then if (b k ≠ 0 and 2 • L k ≧ k + 1) then L k+1 = L k P k+1 (x) = P k (x) - (d k /b k ) • U k (x) U k+1 (x) = (x - x k ) • U k (x) Q k+1 (x) = (Q k (x) - (d k /b k ) • W k (x)) / (x - x k+1 ) W k+1 (x) = W k (x) else L k+1 = L k + 1 P k+1 (x) = (x - x k ) • P k (x) U k+1 (x) = U k (x) - (d k /b k ) • P k (x) Q k+1 (x) = Q k (x) • (x - x k )/(x - x k+1 ) W k+1 (x) = (W k (x) - (d k /b k ) • Q k (x) ) / (x - x k+1 ) Steps S310 and S311: k = k+1;if (k<d-1) then go to Step S304. Step S312: for (k = 0, ···, d - 2) do if (deg P k (x) ≦ k/2) then N k (x) = P k (x) • λ k-1 (x) for (i = 0 ··· n - 1) do if (N k (x) (α -i ) = 0) then c k,i = R i + (1 - α hk-i ) • Q k (x) (α -i )/N k ' (α -i ) Steps S313 to S315: Whether or not the inner product R • C k of the reception system R and the code words C k = [c k,0 , ..., c k,n-1 ] (k = 0, ..., d - 2) satisfies the inequality (3) is determined. If the inequality is satisfied, the code word C k is output. If no inequality is satisfied at all, an error that exceeds the error correcting capability has taken place. Therefore, the detection of such error is executed. (The end) As compared with the Kamiya's decoding method, this decoding can omit the calculation in the step S104. As a result, there is no need for the storage of each of the syndrome polynomials. The size of the memory can be smaller. Further, the calculation thereof can be omitted in order to make the calculation in the step S112 simple in the step S312. The amount of calculations can be reduced still more. This decoding differs from the decoding method shown in the Embodiment 1 in the syndrome calculation in the step S302, in the coefficient selection in the step S304, and in the calculation of the c k,i in the step S312. However, since this syndrome polynomial is included in the usual syndrome polynomial (and erasure location polynomial), this decoding can be implemented by the known means as in the step S312. Also, the coefficient selection in the step S304 is made just by changing the controlled coefficient fetching of the controller. Therefore, it is clear that even if the definitions of the polynomials are changed, this decoding can be implemented as in the Embodiment 1 by means of the circuitry structured as in Fig. 2 or 9 under the procedures arranged substantially the same as those shown in Fig. 12. Also, the GMD decoding method described above makes it easier to execute a parallel processing as given below. For example, in Fig. 2, the d k and b k are the coefficients of a certain degree of the Q k (x) and W k (x). Therefore, as shown in Fig. 5, for example, if the Q k (x) and W k (x) are worked out one after another, it becomes possible to calculate the Q k+1 (x) and W k+1 (x) in parallel with the Q k (x) and W k (x) when the coefficients of the d k and b k are calculated for the Q k (x) and W k (x). Also, when the calculations of the Q k (x) and W k (x) are made by one clock, it should be good enough to apply a clock of approximately d - 1 as shown in Fig. 6. Therefore, it is possible to make its speed faster than the Kamiya's GMD decoding at least two times. Here, clearly, the parallel processing is also possible likewise as to the P k (x) and U k (x). [Embodiment 3] It is clear that the decoder for use of the decoding methods represented in the Embodiments 1 and 2 is generally materialized by a structure as shown in Fig. 4. The decoder comprises an operation unit 41 in which four operations are combined, a controller 42 for making decisions and controlling the procedures, and a memory 43 including a provisional storage. [Embodiment 4] The GMD decoders shown in the Embodiments 1 to 3 are used for enhancing the reliability of various digital systems. Fig. 7 is a view which shows an embodiment in which each GMD decoder 71 of the Embodiments 1 to 3 is used for a digital communication system. Conceivably, as examples of digital communication systems, satellite communications, SS (Spread Spectrum) communications, LAN (Local Area Network) can be cited, among others. In this case, the communication path shown in Fig. 7 is a space or fibers, among others. The transceiver 72 is each of the communication terminals or computers, among others. Also, in the example shown in Fig. 7, a GMD decoder 71 is included in the transceivers 72 on both parties. However, since it is known that encoding is possible by the decoding processing if only the location of the detected symbol of the error correction codes is replaced with that of the erasure location, the GMD decoder 71 is used as an encoder on the transmission side. Nevertheless, since the structure of an encoder is simple, it may be possible to provide encoders besides the GMD decoders 71 described above or if the transceiver can be specified as a transmitter or receiver, such transceiver maybe provided with an encoder as a transmitter while being provided with a GMD decoder as a receiver, respectively. [Embodiment 5] Fig. 8 is a view which shows a case where the GMD decoder described above is used for a digital memory system. As digital memory systems, there are conceivably optical disk devices and magneto-optic disk devices, among others. Here, an access device 82 is to read data from and write them on a memory medium 83 through the GMD decoder 81. In accordance with the embodiments described above, the GMD decoders have the following advantages as has been described above: 1) The amount of calculations required for executing the Kamiya's decoding method is the smallest of the conventional GMD decodings. However, the decoding method embodying the present invention finds it unnecessary to work out the d k and b k . Although the quantity of scalar multiplication is increased in the calculations of the c k,i instead, this multiplication is much simpler than the calculations of the d k and b k . Therefore, the amount of calculations of the decoding method embodying the present invention is smaller than any one of the conventional GMD decodings. 2) The most serious problem of the Kamiya's GMD decoding is that it should keep many numbers of syndrome polynomials in storage. However, there is no need for such storage. 3) Unlike the Kamiya's GMD decoding, it is possible to execute a parallel processing. Therefore, the decoding can be easily made faster. 4) It is possible to utilize a usual syndrome as the syndrome required therefor. The present invention described above may be applicable to a system structured by plural computers or to a specific computer within the system. Also, the present invention is applicable to a case where it is attainable when the computer executes a program. The program may be provided from an external memory medium. The memory medium that stores such program is within the scope of the present invention. Although the present invention has been described in its preferred form with a certain degree of particularity, many apparently widely different embodiments of the invention can be made without departing from the scope thereof. It is to be understood that the invention is not limited to the specific embodiments thereof except as defined in the appended claims.

Claims: A decoding apparatus comprising: means (31) for generating a syndrome polynomial (S(x)) from a received sequence (R i ); means (32) for generating an erasure location polynomial (λ(x)) in accordance with reliability of each of the symbols of the received sequence; polynomial multiplication means (33) for multiplying the syndrome polynomial and the erasure location polynomial so as to output the result of multiplication as a product polynomial (S 0 (x)); memory means (110) for storing a plurality of polynomials (P i (x), U i (x), Q i (x), W i (x)) including a polynomial (Q i (x)) having the product polynomial as the initial value; calculation means (100) for executing respective one of a plurality of predetermined calculations for the plurality of polynomials stored in said memory means and updating the plurality of polynomials in said memory means by the result of the calculation; control means (120) for deciding the respective one of the plurality of predetermined calculations for each of the plurality of polynomials and controlling said calculation means to execute the decided calculations on the plurality of polynomials; means (35) for sequentially generating code words by use of the received sequence, the plurality of polynomials output from said calculation means, and the erasure location polynomial; and determination means (37) for determining whether or not the generated code words and the received sequence satisfy a given condition, and outputting the word found as satisfying the given condition as the result of decoding, characterised in that , said control means is adapted to fetch coefficients of a predetermined one degree from respective of specific two polynomials (Q i (x), W i (x)) stored in said memory means, check values of the fetched coefficients, and decide the respective one of the plurality of predetermined calculations for each of the plurality of polynomials on the basis of the result of the check. A decoding apparatus according to claim 1, wherein said calculation means comprises a plurality of calculation units each operable to execute the plurality of predetermined calculations, and each of the calculation units being arranged to calculate coefficients of each of the polynomials in order of degrees thereof, said control means being arranged to control said calculation means to begin the calculation of the next polynomial by another one of the operation units when the coefficients of the predetermined one degree of the respective of specific two polynomials have been calculated by said calculation units. A decoding apparatus according to claim 1, wherein said control means is provided with a data store for storing a variable (L k ) and means for updating a variable stored in said data store, said control means further being arranged to utilize a said variable stored in said data store to decide the respective one of the plurality of predetermined calculations for each of the plurality of polynomials in accordance with the value of the variable in addition to utilizing the coefficients of the predetermined one degree of the specific two polynomials. A decoding apparatus according to claim 3, wherein said updating means is operable to update a said stored variable in accordance with the value of the coefficients of the predetermined one degree of the specific two polynomials. A decoding method comprising the following steps of: generating a syndrome polynomial (S(x)) from - a received sequence (R i ) (S202); generating an erasure location polynomial (λ (x)) in accordance with reliability of each of the symbols of the received sequence (S203); multiplying the syndrome polynomial and the erasure location polynomial so as to output the result of multiplication as a product polynomial (S i (x)) (S203); storing in a memory (110) a plurality of polynomials (P i (x), U i (x), Q i (x), W i (x)) including a polynomial (Q i (x)) having the product polynomial as the initial value; selecting a respective one of a plurality of predetermined calculations for each of the plurality of polynomials in said memory; (S204, S205, 207) executing the selected respective one of the plurality of predetermined calculations for the plurality of polynomials stored in said memory and updating the plurality of polynomials in said memory by the result of the calculation (S206, S208, S209); sequentially generating code words by use of the received sequence, the plurality of polynomials output from said calculation means, and the erasure location polynomial; and determining whether or not the generated code words and the received sequence satisfy a given condition (S213), and outputting the word found as satisfying the given as the result of decoding (S214), characterized in that , in said selecting step, coefficients of a predetermined one degree are fetched from respective of specific two polynomials (Q i (x), W i (x)) stored in said memory (S205, S207), and the respective one of the plurality of predetermined calculations for each of the plurality of polynomials are selected and performed on the basis of the result of the check. A decoding method according to claim 5, wherein in said executing step, the calculations are performed by a plurality of calculation units each can execute the plurality of predetermined calculations, coefficients of each of the polynomials are calculated in order of degrees thereof, and the calculation of the next polynomial is begun by another one of the operation units when the coefficients of the predetermined one degree of the respective of specific two polynomials are calculated by one of the calculation units. A decoding method according to claim 5, wherein in said selection step, a variable (L i ) stored in a second memory is updated, and the respective one of the plurality of predetermined calculations for each of the plurality of polynomials are performed in accordance with the value of the variable in addition to the coefficients of the predetermined one degree of the specific two polynomials. A decoding method according to claim 7, wherein in said selection step, the variable stored in said second memory is updated in accordance with the value of the coefficients of the predetermined one degree of the specific two polynomials. A storage device storing computer executable instructions for carrying out the method of any one of claims 5 to 8.

Inventors: IWAMURA KEIICHI, IWAMURA, KEIICHI
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1996
Main classification: H03M13
IPC codes: H03M13, G06F11