Semiconductor integrated circuit device with electrostatic protective function

Abstract: An input terminal and an input protective resistor of an N-type diffusion layer connected thereto are provided on a P-type semiconductor substrate. First and second N-type MOS transistors for internal circuit are connected to a grounding wiring at respective source diffusion layers. The first MOS transistor is located at closer distance from the input protective resister than the second MOS transistor. The source diffusion layer of the first MOS transistor and the grounding wiring are connected via a high melting point metal layer wiring, such as a tungsten silicide or so forth to increase a resistance to improve electrostatic breakdown potential. Accordingly, the distance between the input protective resistor and the first MOS transistor can be made smaller to eliminate dead space around the input protective resistor to enable reduction of a chip area.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a semiconductor integrated citrcuit device having an electrostatic protective function. Description of the Related Art Conventional electrostatic protection for a semiconductor integrated circuit will be discussed with taking the technology disclosed in Japanese Unexamined Patent Publication (Kokai) No. Showa 59-87873 (JP-A-59 087 873) as example. Fig. 10 shows a layout in the vicinity of an input terminal of a MOSLSI formed on a P-type semiconductor substrate. An input terminal 1 is connected to an input protective resistor 4 formed with an N-type diffusion layer via a contact 7. The input terminal 1 thus feeds a signal into the inside of the MOSLSI via the input protective resistor 4. At a position spaced from the N-type diffusion layer 4 in a magnitude of a distance d, an N-type MOSFET (MOS field effect transistor) 10 for an internal circuit having an N-type source diffusion layer 5 connected to a grounding wiring 3 is formed. A drain diffusion layer 8 of this MOSFET 10 is often connected to other MOSFET. For instance, in case of CMOSLSI, the drain diffusion layer 8 of the MOSFET 10 is connected to P-type MOSFET (not shown). It should be noted that the reference numeral 9 denotes a gate electrode of the MOSFET 10, and 2 denotes a grounding terminal, 3 denotes a grounding wiring, and 71 denotes a contact. In case of the conventional MOSLSI constructed as set forth above, a problem is encounted in that the distance d has to be 100 µm to 300 µm for obtaining sufficiently high electrostatic protection potential. Namely, when a negative electrostatic pulse is applied to the input terminal 1 with respect to the potential of the grounding terminal 2, electrons are injected to the P-type semiconductor substrate from the N-type diffusion layer 4 and reach to the source diffusion layer 5 of the N-type MOSFET 10 by diffusion. Here, due to high electric field generated at the junction of the source diffusion layer, the electrons become high energy to cause breakdown in the diffusion layer or the gate oxide layer. Accordingly, no internal elements can be arranged in a region of several hundreds µm in the vicinity of the input terminal to cause wasting of the area. This clearly borders reduction of a chip area. Particularly, under the current trend where number of demanded terminals is progressively increasing, presence of the dead space as set forth above is quite disadvantages in down-sizing of the chip area. Fig. 11 shows an example of one solution for the problem set forth above, in which an N-type well 6 of the grounding potential is provided for absorbing the electrons injected from the N-type diffusion layer 4. Even in this case, satisfactory effect may not be expected since large amounts of electrons reach the source diffusion layer 5 of the N-type MOSFET 10 via a deeper region than the well 6 in the P-type semiconductor substrate. Since the N-well 6 occupies a certain area, a dead space is inherently present around the input terminal. Fig. 12 is an explanatory illustration for explaining the presence of the dead spaces not only in the vicinity of the input terminals but also within the MOSFET. Namely, a source diffusion layer 51 of a MOSFET 101 is connected to a grounding wiring 31, and a source diffusion layer 52 of a MOSFET 102 is connected to a grounding wiring 32. The grounding wirings 31 and 32 are respectively connected to independent grounding terminals 21 and 22. The reference numerals 81 and 82 are drain diffusion layers, 91 and 92 are gate electrodes, of MOSFETs 101 and 102 respectively. When an electrostatic pulse in negative potential is applied to the grounding terminal 21 with respect to the grounding terminal 22, similarly to the discussion set forth above, electrons are injected into the semiconductor substrate from a source diffusion layer 51 of the MOSFET 101 connected to the grounding wiring 31, and then the electrons diffuse to a source diffusion layer 52 of the MOSFET 102 connected to the grounding wiring 32 to cause breakdown of the diffusion layers and/or the gate oxide layers. Therefore, the distance d is inherently set to be sufficiently large, e.g. 100 µm to 300 µm. Accordingly, a large number of dead spaces are present even in the internal circuit to be a cause of bordering for reduction of the chip area. Separating of the grounding wiring as in the foregoing example is necessary for avoiding malfunction of the circuit block due to noise generated in certain circuit block. Especially, according to increasing of complicatedness of functions of LSI, the grounding wiring and the power source wiring have to be divided into greater numbers. On the other hand, another example in avoidance of electrostatic breakdown has been disclosed in Japanese Unexamined Patent Publication No. Heisei 4-62838. The example takes a construction, in which a high melting point conductive material is inserted between an aluminum wiring and a diffusion layer. By this, reaction to a lower diffusion layer by melting of aluminum of an upper portion of the diffusion layer of an input protective resistance is prevented. However, the shown construction is not intended to protect the diffusion layer in the internal circuit located in the vicinity of the diffusion layer of the input protective resistor from breakdown by injected electron. From JP-A-3073569 a semiconductor integrated circuit device is known, wherein the margin between the gate contact and drain contact for connecting an input line to the high density drain region of a transistor is set larger than the margin between gate and source contact. Since a resistor is inserted between a low density drain region and the input line the breakdown strength and the gate protective effect for inner circuitry of the gate protective circuit is improved. From JP-A-4062838 a semiconductor device is known having a two-layer interconnection with polysilicon in the lower layer and a high melting point metal such as tungsten silicide in the upper layer. The interconnection is connected to an N-type diffusion layer through lower contact windows while it is connected to an aluminium interconnection through upper contact windows. The interconnection is provided for increasing a surge resistance for an input protection network. In EP-A-109070 a MOS type semiconductor device with a gate protecting circuit for protecting an internal circuit is disclosed. Distances between the diffusion layer in the gate protecting circuit and the diffusion layers in the internal circuit are selected at such values that minority carriers derived from the diffusion layer in the internal circuit are prevented from reaching a depletion layer in the gate protecting circuit, which is caused by the impression thereto of a surge voltage, and that is at least ten times a predetermined minimum distance each separating the adjacent diffusion layers of those. From EP-A-0371663 an integrated circuit output buffer is known comprising a p-channel pull-up transistor and an n-channel pull-down transistor connected to an output bond pad. A protective resistor is connected between the drain of the n-channel transistor and the output node since the n-channel transistor is more suseptible to electrostatic discharge damage than the p-channel transistor. SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device for achieving high package density enabling prevention of electrostatic breakdown even when dead space is eliminated. Another object of the present invention is to provide a semiconductor integrated circuit device which can effectively prevent breakdown of diffusion layer of an internal circuit in the vicinity of diffusion layer of an input protective resistor. According to the invention, a semiconductor device as defined in claim 1 is provided. BRIEF DESCRIPTION OF THE DRAWINGS The present invention will be understood more fully from the detailed description given herebelow and from the accompanying drawings of the preferred embodiment of the invention, which, however, should not be taken to be limitative to the present invention, but are for explanation and understanding only. In the drawings: Fig. 1 is an illustration of a layout of one embodiment of a semiconductor integrated circuit device according to the present invention; Fig. 2 is a section taken along line A - A of Fig. 1; Fig. 3 is a section taken along line B - B of Fig. 1; Fig. 4 is an illustration of a layout of another embodiment of a semiconductor integrated circuit device according to the present invention; Fig. 5 is a section taken along line C - C of Fig. 4; Fig. 6 is an illustration of a layout of a further embodiment of a semiconductor integrated circuit device according to the present invention; Fig. 7 is a section taken along line D - D of Fig. 6; Fig. 8 is an illustration of a layout of a still further embodiment of a semiconductor integrated circuit device according to the present invention; Fig. 9 is a section taken along line E - E of Fig. 8; Fig. 10 is an illustration of a layout of the conventional of a semiconductor integrated circuit; Fig. 11 is an illustration of a layout of another conventional of a semiconductor integrated circuit; and Fig. 12 is an illustration of a layout of a further conventional of a semiconductor integrated circuit. DESCRIPTION OF THE PREFERRED EMBODIMENT The preferred embodiments of a semiconductor integrated circuit device according to the present invention will be discussed hereinafter with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be obvious, however, to those skilled in the art that the present invention may be practiced without these specific details. In other instance, well-known structures are not shown in detail in order to unnecessary obscure the present invention. Fig. 1 is a plan view showing one embodiment of a semiconductor integrated circuit device according to the invention, and Figs. 2 and 3 are sections along lines A - A and B - B. Fig. 1 shows a layout in the vicinity of an input terminal applied for a MOSLSI formed on one major surface of a P-type semiconductor substrate 20. In Figs. 1 to 3, same portions to those of Figs. 11, 12 are represented by the same reference numerals. An input terminal 1 is connected to an input protective resister 4 which is formed with an N-type diffusion layer. The input signal supplied to the input terminal 1 is fed to an internal circuit via the input protective resister 4. With a distances d1 and d2 from the N-type diffusion layer 4, N-type MOSFETs 101 and 102 having source diffusion layers 51 and 52 connected to the grounding wire 3, for internal circuit, are formed, respectively. The drain diffusion layers 81 and 82 are frequently connected to other MOSFET (not shown). For instance, in case of CMOSLSI, the drain diffusion layers 81 and 82 are connected to P-type MOSFETs. In the shown embodiment, the distance d1 is 20 µm and the distance d2 is 150 µm. Since the distance d2 is greater than a critical distance dcr = 100 µm, in the MOSFET 102, the source diffusion layer 52 is directly connected to the grounding wiring 3. On the other hand, since the distance d1 is smaller than the critical distance dcr = 100 µm, in the MOSFET 101, connection between the grounding wiring 3 and the source diffusion layer 52 is established via a tungsten silicide wiring 11 as high melting metal. This manner is as illustrated in Figs. 2 and 3. Namely, in Figs. 2 and 3 the grounding wire 3 is formed with an aluminum wiring and is connected to the tungsten silicide wiring 11 by the first contact 71, and is connected to the source diffusion layer 51 with a second contact 72 via a resistor of tungsten silicide wiring 11. With taking such constriction, even when the negative electrostatic pulse is applied to the input terminal 1 with respect to the potential of the grounding wiring 3, and electrons are injected into the semiconductor substrate 20 from the N-type diffusion layer 4 and diffused to reach the source diffusion layer, a current can be limited by the resistance of the tungsten silicide wiring 11. Therefore, despite of the fact that the distance d1 in the embodiment of Fig. 1 is short, i.e. 20 µm, breakdown of the source region or breakdown of the gate oxide layer is difficult to be caused. As the wiring 11, any high melting point metal having high resistance can be employed. Furthermore, it is also possible to employ high resistance metal, such as polycrystalline silicon and so forth, can be used. While the critical distance dcr is set at 100 µm in the shown embodiment, the practical value of the critical distance should be normally differentiated depending upon the conditions, such as thickness of the gate oxide layer, depth of the diffusion layer, reference impurity concentration and so forth. Practically, the critical distance dcr is determined in a range to cause no problem in the normal practical use on the basis of the relationship between the withstanding voltage against the electrostatic breakdown and the distance d. Fig. 4 is a plan view of another embodiment of the semiconductor integrated circuit device according to the invention, and Fig. 5 is a section taken along line C - C of Fig. 4. The shown embodiment is directed to an example where the source diffusion layer 51 of the MOSFET is distanced from the N-type diffusion layer 4 in a distance greater than that of the drain diffusion layer 81. Even in this case, the construction is identical to that in the first embodiment of Fig. 1. Namely, since the distance d1 is smaller than the critical distance dcr, the grounding wiring 3 is connected to the source diffusion layer 5 via the high resistance wiring, such as the tungsten silicide 11. On the other hand, since the distance d2 is greater than the critical distance dcr, the grounding wiring 3 is directly connected to the source diffusion layer 52. Fig. 6 is a plan view of a further embodiment of the semiconductor integrated circuit device according to the invention, and Fig. 7 is a section taken along line D - D of Fig. 6. In this embodiment, like elements to the embodiment of Fig. 4 are represented by like reference numerals. Since the distance d1 between MOSFET 101 and the N-type diffusion layer 4 is 20 µm which is smaller than the critical distance of 100 µm, the distance a1 from the contact portion 71 between the grounding wiring 3 and the source diffusion layer 51 to the end of the source diffusion layer at the side of a gate electrode 91 is set to be 3 µm. On the other hand, a distance a2 from the contact portion 72 to the end of the source diffusion layer of the side of the gate electrode 92 in the MOSFET 102 is set at the minimum design dimension, i.e. 0.5 µm since d2 is 150 µm which is greater than the critical distance. As set forth above, with respect to the transistor where the distance to the N-type diffusion layer 4 is smaller than the critical distance dcr, the distance a1 from the contact portion between the source diffusion layer and the grounding wiring to the end portion of the source diffusion layer of the gate electrode side is set greater than a2 to increase the parasitic resistance r1 to be greater than that of the parasitic resistance r2 of the diffusion layer of the transistor having greater distance to the N-type diffusion layer 4 to limit the electrostatic discharge current to increase the withstanding voltage against the breakdown potential. Fig. 8 is a plan view of a still further embodiment of the semiconductor integrated circuit device according to the invention, and Fig. 9 is a section taken along line E - E of Fig. 8. The shown embodiment is direct to an application of the present invention for improvement of the conventional semiconductor integrated circuit device shown in Fig. 12. The source diffusion layer 51 of MOSFET 101 is connected to the grounding wiring 31, and the source diffusion layer 52 of MOSFET 102 is connected to the grounding wiring 32. The grounding wirings 31 and 32 are respectively connected to independent grounding terminals 21 and 22. Since a distance d between MOSFETs 101 and 102 is smaller than the predetermined critical distance dcr, respective grounding wirings 31 and 32 and the diffusion layers 51 and 52 of MOSFETs 101, 102 are connected via tungsten silicide wirings 11. The sectional structure along line A - A is the same as that along line A - A of Fig. 1 and as illustrated in Fig. 2. With such constriction, even when either positive polarity or negative polarity of electrostatic pulse is applied between the grounding terminals 21 and 22, the current is limited by the wiring 11 of the resistance of the high resistance and high melting point conducive material, such as the tungsten silicide wiring. Therefore, even when the sufficient distance is not provided, sufficiently high electrostatic breakdown potential can be obtained. It should be noted that while Fig. 8 illustrates the relationship between the internal circuit elements of the MOSFETs 101 and 102, it is equally applicable for the relationship between the input protective resistor element and the MOSFET elements as the internal circuit elements, similarly to the embodiments of Figs. 1 and 4. While the respective of the foregoing embodiments are directed to the case where the source diffusion layer of MOSFET is connected to the grounding wiring, the present invention is equally applicable for the source portion in the case where source diffusion layer is connected to the power source wiring. On the other hand, it is also possible to apply the present invention for the drain portion when the drain diffusion layer is connected to the power source wiring or the grounding wiring. It should be noted that the grounding terminals can be either positive power source terminal or negative power source terminal. Also, the semiconductor substrate is not limited to the P- type, but can be N-type. As set forth above, while the dead space where no element is arranged is provided in the region in the vicinity of the terminal or within the region of the internal circuit for lowering of the electrostatic breakdown potential in the prior art, the present invention may avoid such requirement for the dead space to reduction of the chip size in the extent corresponding to the dead space. Although the invention has been illustrated and described with respect to exemplary embodiment thereof, it should be understood by those skilled in the art that the foregoing and various other changes, omissions and additions may be made therein and thereto, without departing from the spirit and scope of the present invention. Therefore, the present invention should not be understood as limited to the specific embodiment set out above but to include all possible embodiments which can be embodies within a scope encompassed and equivalents thereof with respect to the feature set out in the appended claims.

Claims: A semiconductor device comprising: a semiconductor substrate (20) of a first conductive type; first (1) and second (3) terminals formed on one major surface of said semiconductor substrate; (20) the second terminal being a power source terminal or a grounding terminal first and second wiring layers (12,3) respectively connected to said first and second terminals; a first diffusion layer (4) of a second conductive type selectively formed at one major surface of said semiconductor substrate (20) and connected to said first wiring layer (12); a first field effect transistor (101) located in said semiconductor substrate (20) within a predetermined distance relative to said first diffusion layer (4) and having drain or source diffusion layer (51) connected to said second wiring (3); a second field effect transistor (102) located in said semiconductor substrate (20) in a distance greater than said predetermined distance from said first diffusion layer (4) and having drain or source diffusion layer (52) connected to said second wiring (3), the first and second field effect transistors being internal circuit elements to be protected from breakdown characterized by a first connection wiring (11) for connection between said second wiring layer (3) and said drain or source diffusion layer (51) in said first field effect transistor (101), and a second connection wiring for connection between said second wiring layer (3) and said drain or source diffusion layer (52) in said second field effect transistor (102), wherein said first connection wiring (11) has a higher resistance than said second connection wiring. A semiconductor device as set forth in claim 1, wherein said first diffusion layer (4) is an input protective resistor. A semiconductor device as set forth in claim 1, wherein said first connection coining (11) is formed of a high melting point metal layer. A semiconductor device as set forth in claim 1, wherein said first connection coining (11) is formed of a polycrystalline silicon layer. A semiconductor device as set forth in claim 1, wherein a distance from a connecting portion between the drain or source diffusion layer (51) and said second wiring layer (3) to said gate electrode, in said first field effect transistor (101), is greater than that of said second field effect transistor (102). A semiconductor device as set forth in claim 1, wherein said first terminal (1) is a signal input terminal of a semiconductor integrated circuit device and said second terminal is one of a power source terminal and a grounding terminal, and said first diffusion layer (4) is an input protective resistor.

Inventors: NARITA KAORU, NARITA, KAORU
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1996
Main classification: H01L27
IPC codes: H01L21, H01L27