Trenched field effect transistor with PN depletion barrier

Abstract: A trenched MOSFET in its on-state conducts current through an accumulation region and through an inverted depletion barrier layer located along the trench sidewalls. Blocking is achieved by gate control depletion of the adjacent region and by the depletion barrier layer (having the appearance of "ears" in a cross sectional view and being of opposite doping type to the adjacent region) which extends laterally from the trench sidewalls into the drift region. This MOSFET has superior on-state specific resistance to that of prior art trenched MOSFETs and also has good performance in terms of on state resistance, while having superior blocking characteristics to those of prior art trenched MOSFETs. The improvement in the blocking characteristic is provided by the depletion barrier layer which is a semiconductor doped region. In the blocking state, the depletion barrier layer is fully or almost fully depleted to prevent parasitic bipolar conduction. The shape and extent of the depletion barrier layer may be varied and more than one depletion barrier layer may be present.

Description: This invention pertains to transistors, and more specifically to a field effect transistor having its gate electrode located in a trench and being suitable for use in integrated circuits or as a discrete component, especially for use as a power transistor. Field effect transistors (FETs) are well known, as are power MOS (metal oxide semiconductor) field effect transistors (MOSFETs); such transistors are often used for power applications, i.e. where high voltage is applied. There is a need for power MOSFET transistors with very low on-state resistance (R DS(on) ) for applications where high voltage must be switched. For instance, for a power supply for an integrated circuit, an output rectifier supports 20 volts for a 3.3 volt output and 10 volts for a 1.5 volt output. Typically, Schottky rectifiers are used but these disadvantageously have forward voltage drops of about 0.5 volts, which degrades the efficiency of the power supply. A power MOSFET should have the lowest possible on-state specific resistance to minimize conduction losses. On-state resistance is a well known parameter of the efficiency of a power switching transistor and is a ratio of drain to source voltage to drain current when the device is fully turned on. On-state specific resistance refers to resistance times cross sectional area of the substrate carrying the drain current. A typical prior art N-channel trenched MOSFET is shown in Figure 1a, having conductive gate electrode 10 typically being N doped polycrystalline silicon (N type polysilicon) which is doped to be conductive serving as a gate electrode and located in a trench 12, the floor and sidewalls of which are insulated by a layer of gate oxide 16. Oxide layer 18 insulates the upper portion of gate electrode 10. The metallized source contact 20 contacts both the N+ doped source region 24 formed in the upper portion of the device and the P doped body region 38. The drain electrode 28 is a metallized contact to the N+ drain region 30 at the bottom surface of the device. Formed overlying the N+ drain region 30 is an N-doped drift region 34 typically formed by epitaxy (hence an epitaxial layer) and being the drift region. The upper portion of the epitaxial layer is P doped to form the body region 38 and the very upper portion of the epitaxial layer is N+ doped to form the source region 24. It is to be understood that this transistor is typically formed in a silicon wafer and moreover there are a number of gate trenches 12 arranged (in a plan view) in rectangles, circles, hexagons, or linear structures, each defining a cell and all cells typically having a common source contact and a common gate contact. In this case, to achieve high blocking capability, the trench 12 extends only partly through the N- doped drift region 34 and does not extend into the N+ doped drain region 30. The blocking state (off-state) is ordinarily the state when the transistor is off, i.e. not conducting current, and a measure of blocking capability is leakage current. Ideally, leakage current is zero. This transistor has an inferior on-state specific resistance to the ideal due to the substantial resistance of the N-doped drift region 34 below the trench. An improvement over the prior art MOSFET of Figure 1a is shown in Figure 1b, which shows an N-channel device called the ACCUFET as described in "The Accumulation Mode Field Effect Transistor: A New UltraLow On-Resistance MOSFET" by Baliga et al., IEEE ELECTRON DEVICE LETTERS, Vol. 13, No. 8, August 1992. The ACCUFET is an ultra-low on-state specific resistance vertical channel power MOSFET structure which uses current conduction via an accumulation layer formed on the surface of the trench gate structure. The ACCUFET does not contain a P body region 38, unlike the transistor of Figure 1a, and the gate trench 42 extends all the way into the highly doped drain region 30. To achieve blocking the polysilicon is P doped and the N-region 34 is very lightly doped. For instance, the optimum N- drift region doping for a conventional MOSFET of Figure 1a is typically 2 x 10 16 /cm 3 , while in the ACCUFET the N- region doping is typically below 10 14 /cm 3 . The doping type of the conventional MOSFET polysilicon gate electrode is typically N-type, and not P-type. The ACCUFET on-state specific resistance is 105 micro-ohm cm 2 at a gate bias of 15 volts. Thus the ACCUFET is described as having a on-state specific resistance which is the lowest attainable for any known MOS gate-control device. Moreover, the ACCUFET is bidirectional, i.e. reversal of the source and drain contacts in use is available. However, the ACCUFET blocking characteristics are less than might be desired, and negative gate voltages are required to reduce leakage current to acceptable levels. Thus, it would be desirable to improve performance over both the prior art MOSFET of Figure la and the ACCUFET of Figure 1b in terms of the combined parameters of on-state specific resistance and blocking characteristics. US Patent 4,791,462 discloses doped regions extending laterally from the sidewalls of the trenched gate electrodes. These laterally extending regions include a central N+ doped region which is electrically in contact with the gates. This N+ region is in contact with a surrounding P+ doped region. These reversed bias junctions prevent a significant current from flowing between the gates and prevent conductivity modulation of the channels. US Patent 3,350,934 discloses trench bottom implants located at the bottom of the trenched gate electrodes. According to one aspect of the present invention there is provided a field effect transistor formed in a semiconductor material having a first conductivity type and having a principal surface, and comprising: at least two trenches, spaced apart from one another, each trench extending into the semiconductor material from the principal surface; a conductive gate electrode of a second conductivity type in each trench; a source region of the first conductivity type and extending into the semiconductor material from the principal surface, between the two trenches; and a barrier region associated with each of the trenches and being of the second conductivity type, and in contact with the semiconductor material and underlying the source region and wherein each barrier region extends from a sidewall of the associated trench towards the barrier region associated with the other trench, there being a portion of the semiconductor material of the first conductivity type laterally spacing apart the barrier regions and wherein each barrier region is located intermediate a floor of the associated trench and the principal surface, wherein each barrier region is insulated from the gate electrode and is spaced apart from the source region. According to another aspect of the present invention there is provided a method of forming a field effect transistor having a barrier region, the transistor being formed in a semiconductor material of a first conductivity type and having a principal surface, comprising the steps of: etching two spaced apart trenches extending into the semiconductor material from the principal surface, thereby defining a mesa between the two trenches; implanting a doped barrier region of a second conductivity type into the semiconductor material through the principal surface and the bottom of each of the trenches; driving in the implanted barrier regions; etching the trenches deeper, through a portion of the respective barrier regions; insulating the floors and sidewalls of the trenches; forming a conductive gate electrode structure of the second conductivity type in each insulated trench; and forming a source region of the first conductivity type in the semiconductor material at the principal surface and lying between the trenches; wherein the barrier region is in contact with the semiconductor material and extends form a sidewall of the associated trench towards the barrier region associated with the other trench, wherein each barrier region is insulated from the gate electrode and is spaced apart from the source region. The invention will now be described by way of example with reference to the accompanying drawings, in which: Figure 1a shows a prior art N-channel MOSFET. Figure 1b shows a prior art ACCUFET. Figure 2 shows in cross section an N-channel MOSFET in accordance with the present invention. Figure 3 shows current conduction in the MOSFET of Figure 2. Figure 4 shows a depletion profile of the MOSFET of Figure 2. Figure 5 shows a conduction band barrier profile of the MOSFET of Figure 2. Figure 6 shows dimensions of the MOSFET of Figure 2. Figure 7 shows a P-channel MOSFET complementary to that of Figure 2. Figure 8 shows a MOSFET having multiple depletion barrier regions in accordance with the present invention. Figure 9 shows another MOSFET in accordance with the present invention having a Schottky contact to the source regions. Figure 10 shows another MOSFET in accordance with the present invention illustrating an epitaxial layer/substrate interface. Figure 11 shows another MOSFET in accordance with the present invention illustrating the trench penetrating into the lower portion of the substrate. Figures 12a-12c show steps in fabrication of a MOSFET in accordance with the present invention. Figure 13 shows another MOSFET in accordance with the present invention with the barrier layer immediately under the source region. Figure 14 shows another MOSFET in accordance with the present invention with the barrier layer located immediately under the source region. Similar reference numbers in various figures refer to identical or similar structures. Figure 2 shows a cross-section of a trenched N-channel MOSFET in accordance with the present invention. It is to be understood that Figure 2, like the other figures herein, is not to scale and that furthermore the various doped semiconductor regions shown herein, which are shown as precisely defined regions delineated by lines, are conventional representations of doped regions having gradient dopant levels at their edges. Moreover, as is well known in the art and described above, typically power MOSFETs include a large number of cells, the cells having various shapes such as square, circular, hexagonal, linear or others. These cells are evident in a top side view (not provided here); in terms of cell layout, the present MOSFETs are conventional and may be fabricated in any one of a number of well known cell structures. The present depictions are therefore typically of only one cell or a portion of two cells as delineated by the gate trenches, and are not intended to illustrate an entire power transistor which would typically include hundreds or thousands of such cells. Moreover, certain well known elements of such trenched MOSFETs are not shown herein. For instance, the metallization which connects to the gate electrodes is typically not shown as being outside the plane of the present cross sectional drawings. Also the termination portions of the transistors are also not shown as being outside the area depicted in the drawings; these terminations are conventional (ACCUFET-type) except as described below. The N-channel MOSFET of Figure 2 is in most respects similar to that of the N-channel ACCUFET of Figure 1b (and referred to by identical reference numbers) with the important addition of the P doped depletion barrier layer regions extending from the sidewalls of the trenches into the drift region and having a P-doped polysilicon gate electrode. In this case, the depletion barrier layer for each trench 42a,42b is in two portions respectively 50-1, 50-2 and 50-3, 50-4 which appear in cross section to be "ears" extending from the trench sidewalls. This barrier layer 50-1, 50-2, 50-3, 50-4 is a major distinction between the MOSFET of Figure 2 and the prior art ACCUFET. This barrier layer provides the advantage of surface conduction as depicted in the Figure 3, which is depicted along the Figure 2 MOSFET trench sidewall and shows current flow for the on-state conduction path from the N+ doped drain region 30 through the accumulation region, through the inversion region (formed within the depletion barrier layer) layer 50-2 through the upper accumulation region, through the upper portion of the lightly doped drift region 34 through the N+ source region 24 to the N+ source region contact 20. Operation of the device of Figure 2 in the blocking state, i.e., where V GS is equal to zero, is depicted in Figure 4, showing the depletion region in the P depletion barrier layer (negative charge) and in the N- region (positive charge). A corresponding conduction band barrier profile with V DS greater than zero and V GS equal to zero is shown in Figure 5, where the vertical axis is the energy E C and the horizontal axis is the linear dimension along line XX in Figure 4. The various semiconductor regions along line XX are labeled on the horizontal axis in Figure 5. As can be seen, the PN depletion barrier layer (designated "PN-barrier") provides a conduction band energy "hump" in the blocking state, hence advantageously reducing leakage current and improving (increasing) blocking voltage. The indication "qV DS " of the right hand side of Figure 5 indicates the total energy is a function of charge (q) multiplied by V DS . In this case the depletion barrier layer is totally depleted. Thus the typical undesirable parasitic NPN transistor which appears in a prior art MOSFET as in Figure 1a is not present here, due to depletion. It has been found that advantageously a MOSFET including the present depletion barrier layer and gate electrode doping type exhibits significant improvement in blocking voltage capability compared to the ACCUFET for instance. An ACCUFET has been compared to the present MOSFET, at a blocking voltage of 15 volts. The leakage current for the ACCUFET was found to be approximately 10 times greater than that for the present MOSFET. To put this another way, for the ACCUFET there is significant leakage current in the offstate, i.e., V GS is equal to zero, at a blocking voltage of as little as 8 volts, whereas a similar leakage current would only occur for the present MOSFET at a blocking voltage of 15 volts. Thus the present device is clearly superior to the ACCUFET in this regard. Also it has been found that on-state resistance for the present MOSFET is approximately the same as for comparable ACCUFETS. Hence, a superior blocking capability is achieved at no disadvantage in terms of specific on resistance compared to the ACCUFET. As will be explained further below with reference to other embodiments, the particular shape of the depletion barrier layer as shown in Figure 2 is not critical to the present invention, nor is its extent. That is, the depletion barrier layer may be located anywhere along the sidewalls of the gate trenches and may extend all the way from the sidewall of one trench to the sidewall of the adjacent trench, and need not extend exactly to the sidewall but may be spaced slightly apart therefrom, so long as the depletion improvement is still present. Moreover, the height (vertical extent) of the depletion barrier layer need not be any particular amount so long as it is adequate to provide the desired blocking capability. A wide range of doping levels of the depletion barrier layer also provides the desired depletion effect. Figure 6 shows a somewhat schematic depiction of the structure of Figure 2 with some structures eliminated or redrawn for simplicity, so as to depict relevant illustrative dimensions and doping (concentration) levels. The dimension L, which is the trench depth, is in the range of 0.2 to 10 microns (µm). The dimension W, which is the spacing between adjacent trenches, is also in the range of 0.2 to 10 microns. Similarly the width of the trenches, which is dimension D, is in the range of 0.2 to 10 microns. Dimension Y, which is the height of the depletion barrier layer 50-1, 50-2, 50-3, 50-4 may be any dimension greater than zero and less than L and typically is in the range of 0.2 to 2 microns. The dimension X, which is the spacing between adjacent portions of the depletion barrier layer, is in the range zero (indicating that the depletion barrier layer extends from trench to trench) to slightly less than dimension W, in which case the width of the depletion barrier layer portions is minimal. A minimal width of each "ear" is e.g. 0.1 micron. Dimension Z, which is the depth of the depletion barrier layer relative to the principal surface of the substrate, is in the range of zero (immediately below the source region) to L, in which case the barrier layer is located adjacent the floors of the trenches. The dopant concentration levels of portions of the present device may vary, as is typical of MOSFETs and well understood to one in the art. In typical embodiments, the doping level N S of the N+ source region 24 is in the range of 10 17 to 10 22 /cm 3 . The doping level N C of the N- lightly doped drift region 34 is in the range of 10 13 to 10 16 /cm 3 . The doping level of the P depletion barrier layer 50-1, etc. is in the range of 10 13 to 10 18 /cm 3 . The usual P type dopant is boron, but this is not limiting; neither are the abovementioned concentration levels. Figure 7 shows a P-channel MOSFET complementary in conductivity types to that of Figure 2. This device would have the same benefits as those of Figure 2 and would operate similarly. In this case the substrate 60 is P+ doped while the lightly doped region 62 is P- doped and the source regions 66 are P+ doped. The depletion barrier layer 68-1, 68-2, 68-3, is N doped. Also the polysilicon gate electrodes 64a, 64b are N doped, in contrast to the P doping of the polysilicon gate electrode in the N-channel device of Figure 2. Figure 8 shows (somewhat schematically) a cross section of a MOSFET in accordance with the present invention having a plurality of depletion barrier layers in substrate 80. These are designated as barrier layers NB 1 , NB 2 , NB 3 which are at varying depths respectively z 1 , z 2 and z 3 . In this case there are three barrier layers NB 1 , NB 2 , NB 3 , each potentially varying in height, respectively heights y 1 , y 2 and y 3 , and each having a spacing between the two opposing "ears", in respectively spacings x 1 , x 2 and x 3 . This illustrates that it is possible to use multiple barrier layers to increase the depletion effect, and each barrier layer may have its own dimensions. Use of multiple depletion barrier layer would include in one version one depletion barrier layer near the top of the trench and one near the bottom of the trench, to provide symmetry for bidirectional characteristics. Such a device would be fabricated e.g. by multiple ion implants at different energies. Figure 9 shows another embodiment in accordance with the present invention otherwise similar to that of Figure 2, except that the N+ doped source region is modified so that it is formed in two portions 84-1, 84-2, separated by a portion of the N- region 34. A Schottky contact 88 is made ohmically to the source regions 84-1, 84-2 and drift region 34. Such a Schottky contact is well known in the art and in this application improves the barrier at the surface of the device. The advantage of this is to extend the barrier into the portion of the N- region 34 between the N+ source regions 84-1, 84-2. Figure 10 shows somewhat schematically yet another embodiment in accordance with the present invention. Here the depletion barrier layer 50-1, 50-2, 50-3 is as in Figure 2; however, in this case the trenches 90a, 90b do not penetrate all the way down to the upper portion of the N+ drain region 30, but instead only extend down partly through the N- region 34 (which is in this case an epitaxial layer). The dimension t between the floor of the trenches 90a, 90b and the upper portion of the N+ drain region 30 may be any dimension, as determined by process or other limitations. This structure allows the depletion barrier to extend down further below the trench floors into the lower portion of the region 34. The advantage of this is increased blocking capability, at the expense of on-state specific resistance. Figure 11 shows yet another embodiment in accordance with the present invention. In this case the trenches 92a, 92b extend down into the lower portion of the device, i.e. into the N+ drain region 30 by a depth t which may be any dimension as determined by the maximum trench depth. The advantage of this is to guarantee extension of the trench into the drain region. Figures 12a through 12c show process steps to fabricate the MOSFET of Figure 2 (and with readily apparent modifications the MOSFETs of Figures 7, 8, 9, 10, and 11). These steps individually are conventional. Figure 12a begins with an N+ doped substrate 30, on which is grown an N- doped epitaxial layer 34 having a thickness of 2 microns. Then a "hard" mask (for instance oxide) is formed over the principal surface of layer 34 and patterned into portions 98a, 98b, 98c to define the trench openings. Then the trenches are anisotropically etched to form the straight sided trenches 42a, 42b shown. Then in Figure 12b after an additional layer of silicon dioxide ("oxide"0 is grown lining the trenches 42a,42b, boron is implanted at an energy level in the range of 30 to 80 KEV and driven in to form the P doped depletion barrier layer 50 having a doping concentration in the range of 10 13 to 10 18 /cm 3 , as described above. In this case the hard mask 98a, 98b, 98c extending between each two adjacent trenches prevents the boron atoms from being implanted immediately below the mask 98a, 98b, 98c; however, the drive in step drives the boron atoms so that they extend laterally beyond the trench sidewalls. The extent to which the boron atoms extend laterally is determined by the implant energy and the drive in step parameters, thus determining how close the two adjacent portions of the depletion barrier layer approach one another after drive in. Next as shown in Figure 12c, a second etch step is performed using the same hard mask as before to extend the trenches 42a, 42b downward further through the implanted P depletion barrier layer 50, thus eliminating a substantial part of P layer 50 but leaving the characteristic "ears" 50-1, 50-2, 50-3, 50-4 extending from the sidewalls of each trench. Thus this structure can be identified with that of Figure 2. The transistor is then completed conventionally (not shown) by stripping off the hard mask 98a, 98b, 98c, growing the gate oxide, filling the trenches with polysilicon, doping the polysilicon, patterning the polysilicon to form the gate electrodes, and then using a mask to form the N+ source regions (not shown). The passivation is formed, and then the metallization is formed to contact the source region and the drain region as shown in Figure 2. Figure 13 shows yet another embodiment fabricated by a process different from that shown in Figure 12a to 12c but similar in structure to that of Figure 2, except that the depletion barrier layer 50-1, 50-2, 50-3, 50-4 is not formed midway on the sidewalls of the trenches 42a, 42b, but instead is formed adjacent the upper portion of the trench sidewalls and immediately below the N+ source regions 24. It has been found that this structure provides the benefits of the depletion barrier layer without the need for the double trench etch steps of Figure 12. A variant of the MOSFET of Figure 13 is shown in Figure 14. In this case, in addition to the P depletion barrier layer 50-1, 50-2, 50-3, 50-4 formed adjacent the upper portions of the trench sidewalls, there is also a P+ region 100-1, 100-2 adjacent the principal surface of the substrate and located between each two portions of the source region. This P+ region, in combination with the adjacent source region, forms a PN diode and increases the barrier laterally and vertically. For the MOSFETs of Figures 13 and 14, the depletion barrier layer is formed by a high energy implant so as to be located immediately below the N+ doped source regions 24 and has a typical doping level of 10 16 /cm 3 or less. The N- region 34 has a typical doping level of 10 14 /cm 3 . In this case the trenches are formed by a conventional single trench etch process. The P depletion barrier layer 50-1, 50-2, 50-3, 50-4 is implanted (using a suitable separate mask) prior to etching the trenches. The trenches are then etched through the P depletion barrier layer. It is to be understood that while conventional ACCUFET termination structures (not shown) may be used in accordance with the present invention, other termination structures may be used to isolate the active portion of the MOSFET. The termination isolation prevents drain to source shorting. In one embodiment, an isolation structure (for a closed cell MOSFET) is formed in the perimeter of the transistor and surrounding the transistor; the termination includes dummy cells (having no source contact). Alternatively or additionally, the polysilicon gate structures in the dummy cells are isolated from the active cell gate structures. For a linear (interdigitated) MOSFET cell structure, termination isolation moats are provided to close off the ends of the cells. This disclosure is illustrative and not limiting; further modifications will be apparent to one of ordinary skill in the art in light of this disclosure and are intended to fall within the scope of the appended claims.

Claims: A field effect transistor formed in a semiconductor material (34) having a first conductivity type and having a principal surface, and comprising: at least two trenches (42a, 42b), spaced apart from one another, each trench extending into the semiconductor material from the principal surface; a conductive gate electrode (10a, 10b) of a second conductivity type in each trench; a source region (24) of the first conductivity type and extending into the semiconductor material from the principal surface, between the two trenches; and a barrier region (50-2, 50-3) associated with each of the trenches and being of the second conductivity type, and in contact with the semiconductor material and underlying the source region and wherein each barrier region extends from a sidewall of the associated trench towards the barrier region associated with the other trench, there being a portion of the semiconductor material of the first conductivity type laterally spacing apart the barrier regions and wherein each barrier region is located intermediate a floor of the associated trench and the principal surface, wherein each barrier region is insulated from the gate electrode and is spaced apart from the source region. The field effect transistor of Claim 1, wherein the first barrier region is in two portions (50-1, 50-2), each portion extending form a sidewall of one of the trenches. The field effect transistor of Claim 1, wherein each barrier region extends only part way between the source region and a floor of the associated trench. The field effect transistor of Claim 1, each barrier region having a doping concentration in a range of 10 13 to 10 18 /cm 3 . The transistor of Claim 1, further comprising a second barrier region of the second conductivity type in the semiconductor material below the source region and between the two trenches, and spaced apart from the first barrier region. The transistor of Claim 1, wherein the first barrier region extends from a sidewall of a first of the two trenches to a sidewall of a second of the two trenches. The transistor of Claim 1, wherein the first barrier region is in two portions, a first portion adjacent a sidewall of a first of the two trenches and the second portion adjacent a sidewall of the second of the two trenches. The transistor of Claim 1, wherein the source region is in two spaced apart portions (84-1, 84-2), and further comprising: a region of the second conductivity type lying between the two portions of the source region, and a region of the second conductivity type lying between the two portions of the first barrier region. The transistor of Claim 1, wherein the source region is in two spaced apart portions (84-1, 84-2). The transistor of Claim 1, wherein the semiconductor material comprises a lower portion (30) and an upper portion (34), the lower portion being more heavily doped than the upper portion and the trenches extending to and not into the lower portion. The transistor of Claim 1, wherein the semiconductor material comprises a lower portion (30) and an upper portion (34), the lower portion being more heavily doped than the upper portion, the trenches extending into the upper portion and being spaced apart from the lower portion. The transistor of Claim 1, wherein the semiconductor material comprises a lower portion (30) and an upper portion (34), the lower portion being more heavily doped than the upper portion, the trenches extending into the lower portion. The transistor of Claim 1, further comprising a termination (100-2) laterally surrounding an active portion of the transistor at the principal surface, the termination isolating the active portion of the transistor. A method of forming a field effect transistor having a barrier region, the transistor being formed in a semiconductor material (34) of a first conductivity type and having a principal surface, comprising the steps of: etching two spaced apart trenches (42a, 42b) extending into the semiconductor material from the principal surface, thereby defining a mesa between the two trenches; implanting a doped barrier region (50-2, 50-3) of a second conductivity type into the semiconductor material through the principal surface and the bottom of each of the trenches; driving in the implanted barrier regions; etching the trenches deeper, through a portion of the respective barrier regions; insulating the floors and sidewalls of the trenches; forming a conductive gate electrode structure (10a, 10b) of the second conductivity type in each insulated trench; and forming a source region (24) of the first conductivity type in the semiconductor material at the principal surface and lying between the trenches; wherein the barrier region is in contact with the semiconductor material and extends form a sidewall of the associated trench towards the barrier region associated with the other trench, wherein each barrier region is insulated from the gate electrode and is spaced apart from the source region. The method of claim 14, wherein the step of etching the material includes forming a mask layer on a portion of the principal surface defining the mesa; and the mask layer remains during the step of implanting. The method of claim 17 or 18, wherein after the step of driving in, the barrier regions are laterally spaced apart. The method of any of claims 14 to 16, wherein after the step of etching the trenches, the barrier regions are located midway between the principal surface and the floors of the deeper trenches. The method of any of claims 14 to 16, wherein after the step of driving in, the doping concentration of the barrier regions is in a range of 10 13 to 10 18 /cm 3 . The method of any of claims 14 to 18, further comprising the steps of: implanting additional barrier regions of the second conductivity type underlying and vertically spaced apart from the barrier regions; and driving in the additional barrier regions.

Inventors: CHANG MIKE F, FLOYD BRIAN H, HSHEIEH FWU-IUAN, PITZER DORMAN C, CHANG, MIKE F., FLOYD, BRIAN H., HSHEIEH, FWU-IUAN, PITZER, DORMAN C.
Applicants: SILICONIX INC, SILICONIX INCORPORATED
Application year: 1996
Main classification: H01L29
IPC codes: H01L29