ANALOG-TO-DIGITAL CONVERTER FOR GENERATING A DIGITAL N-BIT GRAY-CODE

Abstract: A full-flash N-bit analog-to-digital converter with Gray-code digital output (Vout) comprises only N current sources (CS1, CS2, CS3) to power the 2<N>-1 differential amplifiers connected to the reference ladder RL and only N latches (L1, L2, L3) which directly furnish an N-bit Gray-code at their outputs (LO). For this purpose the differential amplifiers are grouped and stacked in a special manner and the output signals of the individual differential amplifiers (Di) are cross-coupled to the inputs (LI1, LI2) of the latch associated with the group.

Description: Analog-to-digital converter for generating a digital N-bit Gray code The invention relates to an analog-to-digital converter for converting an analog input signal into an N-bit digital output signal, N being an integer greater than 0, comprising: an input terminal for receiving the analog input signal; - a series arrangement of a multiplicity of resistors which are connected to one another at 2 N -1 tapping points, numbered in ascending order with sequence numbers 1 through 2 N -1, to supply 2 N -1 different reference voltages derived from a voltage source which is connectable to the series arrangement; a plurality of 2 N -1 differential pairs, numbered in ascending order with sequence numbers 1 through 2 N -1, each differential pair comprising a common terminal, a first transistor having a first main electrode connected to the common terminal, a second main electrode, and a control electrode coupled to the input terminal, a second transistor having a first main electrode connected to the common terminal, a second main electrode, and a control electrode coupled to a tapping point having the same sequence number as the relevant differential pair; a plurality of current sources coupled to the common terminal of a number of differential pairs; a plurality of latches each having a first latch input terminal and a second latch input terminal coupled to the second main electrodes of the first and the second transistor of the differential pairs. Such an analog-to-digital converter (ADC) is also referred to as a full- parallel flash converter and is known from, inter alia, IEEE Journal of Solid-State Circuits, Vol. 23, No. 6, December 1988, pp. 1334-1344, Van de Plassche et al. , "An 8-bit 100-MHz Full-Nyquist Analog-to-Digital Converter" , page 1336, Fig. 1. The circuit diagram of such an ADC is shown in Fig. 1. This Figure relates to a 3-bit ADC, i.e. N=3. By means of 2 N - 1 =7 differential amplifiers D 1 (i= 1..2 N -l) the input signal V ιn is compared with 2 N -1 =7 reference voltages appearing at a corresponding number of tapping points N, of a reference ladder RL. Each differential amplifier D, comprises two transistors T, , T 2 arranged as a differential pair. Each differential pair D, is coupled to a current source CS,, whose current is divided between the two transistors in dependence upon the voltage difference between the input voltage V in and the reference voltage at the relevant tapping point N-. By means of 2 N - 1 =7 latches the individual difference signals from the differential amplifiers D* are converted into output signals VL* which indicate whether the input voltage V in is greater or smaller than the relevant reference voltage at the reference ladder. As the input signal V in increases the signals VL* changes in accordance with a thermometer-like code, which code is subsequently converted into the desired N-bit digital output signal V out by means of a code converter CCNV and three additional latches L A , L B and L c . In principle, the code of the N-bit output signal is arbitrary but a frequently used code is the Gray code, in which for the least change in input voltage V in which leads to a change of the N-bit output signal V out the output signal V out changes by only one bit at a time. In this known full-parallel flash ADC the number of current sources CS* and the number of latches L* is equal to the number of tapping points N* of the reference ladder. The number of parts and the resulting chip area and current consumption increase considerably when the number of bits is increased. Inter alia in said article a folding and inteφolation architecture is proposed by means of which the number of latches can be reduced considerably. However, the number of current sources remains the same and a code converter remains necessary to convert the thermometer code into a Gray code. It is an object of the invention to provide a simplified analog-to-digital converter for converting an analog input signal into a Gray-coded digital signal. To achieve this, according to the invention, the analog-to-digital converter of the type defined in the opening paragraph is characterised in that the plurality of 2 N -1 differential pairs is divided into N groups having a group number G, G being an integer from N through N, the group having the group number G comprising 2 G_1 differential pairs; the control electrode of the second transistor of the group having the group number G= 1 is connected to the central tapping point of the 2 N -1 tapping points, leaving residual groups of residual tapping points at either side of the central tapping point; the control electrodes of the second transistors of the group having the group number G =2 through N are connected to different central tapping points of the residual groups of residual tapping points left by the preceding group having the group number G-l ; for each group: the common terminal of the differential amplifier having the lowest sequence number within the relevant group is coupled to a respective current source of the plurality of current sources; the common terminal of a differential amplifier having a higher sequence number in the relevant group is coupled to the second main electrode of the first transistor of the differential amplifier having the next lower sequence number in the relevant group; the second main electrode of the first transistor of the differential amplifier having the highest sequence number within the relevant group is coupled to the first latch input terminal of a respective latch of the plurality of latches; and the second main electrodes of the second transistors of the differential amplifiers within the relevant group are coupled alternately, in accordance with descending sequence numbers, to the second latch input terminal and the first latch input terminal of the respective latch; the respective latch having a latch output terminal to supply a respective bit of the N-bit digital output signal in response to a difference signal between the first latch input terminal and the second latch input terminal of the relevant latch. The analog-to-digital converter in accordance with the invention comprises only N current sources instead of 2 N -1 +N. Moreover, the desired Gray code is directly available at the outputs of the latches, so that no longer a code converter is needed. The ADC in accordance with the invention therefore requires less parts with a smaller current consumption and a smaller chip area. The smaller number of latches also reduces the noise level. These and other aspects of the invention will be described and elucidated with reference to the accompanying drawings, in which Figure 1 shows a prior-art 3-bit Gray code analog-to-digital converter; Figure 2 shows a 3-bit Gray code analog-to-digital converter in accordance with the invention; and Figure 3 is a Table of digital signals for a 3-bit Gray code analog-to- digital converter. Figure 1 shows a known Gray code analog-to-digital converter (ADC). This Figure relates to a 3-bit ADC, i.e. N=3. By means of 2 N -1 =7 differential amplifiers D-(i = 1..2 N -l) the input signal V in at an input terminal IT is compared with 2 N -1 =7 reference voltages appearing at a corresponding number of tapping points N- of a reference ladder RL, which tapping points have been numbered consecutively starting from an end RT j of the reference ladder RL. The reference ladder RL comprises a series arrangement of resistors connected to one another in the tapping points N-. A positive reference voltage is applied to the ends RT j and RT 2 of the series arrangement and is divided into steps by the reference ladder RL. Each differential amplifier D* comprises two PMOS transistors T, , T 2 arranged as a differential pair. The control electrode or gate of the first transistor T j of each differential pair D j is connected to the input terminal IT to receive the input signal V in . The gate of the second transistor T 2 of a differential pair D j is connected to a tapping point N j having the same sequence number i, so that in the case of a progressively decreasing input voltage an increasing number of individual transistors T j of differential amplifiers D ; having increasing sequence numbers i are turned on. The first main electrodes or sources of the transistors T l and T 2 of each differential pair D j are commoned at a respective common terminal CN j , which is coupled to a respective current source CS j , to receive a current which is divided between the two transistors T j and T 2 of the relevant differential pair D* in dependence upon the voltage difference between the input voltage V in and the reference voltage at the relevant tapping point N;. The second main electrode or drain of the first transistor T, of each differential amplifier D ; is connected to a first latch input terminal LI j of a respective latch L j , which has a second latch input terminal LI 2 connected to the drain of the second transistor T 2 of the relevant differential amplifier D j . The latches L ; are clocked by a clock signal generator CLK and are responsive to the difference current of the relevant differential amplifier D j . However, voltage-responsive latches are also possible by arranging resistors between the latch input terminals and a suitable supply voltage. By means of 2 N - 1 =7 latches the individual difference signals from the differential amplifiers D ; are converted into output signals VL ; which indicate whether the input voltage V in is greater or smaller than the relevant reference voltage at the reference ladder. When the input signal V in increases progressively the signals VL j changes in accordance with a thermometer-like code, which code is subsequently converted into the desired 3-bit digital output signal V out by means of a code converter CCNV and three additional latches L A , L B and L c . In principle, the code of the N-bit output signal is arbitrary but a frequently used code is the Gray code, in accordance with which the 3-bit output signal V out changes by only one bit at a time for each smallest change of the input voltage V in which causes the output signal V out to change. Figure 3 gives the thermometer code of VL j and the Gray code of V out for consecutive values of V in , which for the sake of simplicity are represented by the values 0 to 7. In this known full-parallel flash ADC the number of current sources CS; and the number of latches L ; is equal to the number of tapping points N j of the reference ladder. Figure 2 shows a full-parallel Gray code ADC in accordance with the invention. This is again a 3-bit version with PMOS transistors. By means of 2 N -1 =7 differential amplifiers D j (i = 1..2 N -l) the input signal V in at an input terminal IT is compared with 2 N -1 =7 reference voltages appearing at a corresponding number of tapping points N j of a reference ladder RL, which tapping points have been numbered consecutively starting from an end RT-, of the reference ladder RL. In the same way as in Fig. 1, the reference ladder RL comprises a series arrangement of resistors connected to one another in the tapping points N j . A positive reference voltage is applied to the ends RT t and RT 2 of the series arrangement and is divided into steps by the reference ladder RL. Each differential amplifier D j comprises two PMOS transistors T, , T 2 arranged as a differential pair. The control electrode or gate of the first transistor T of each differential pair D ; is connected to the input terminal IT to receive the input signal V in . The gate of the second transistor T 2 of a differential pair D- is connected to a tapping point N j having the same sequence number i, so that in the. case of a progressively decreasing input voltage an increasing number of individual transistors T j of differential amplifiers D ; having increasing sequence numbers i are turned on. The differential amplifiers D ; are divided into N=3 groups having group numbers G = l , 2 and 3. Each group comprises 2 G_1 differential pairs. Group 1 comprises one differential pair, i.e. D 4 , group 2 comprises two differential pairs, i.e. D 2 and D 6 , and group 3 comprises four differential pairs, i.e. D- , D 3 , D 5 and D 7 . In the case of an extension to 4 bits, i.e. if N=4, the fourth group will comprise 8 differential pairs. The gate of the second transistor T 2 of the group bearing the lowest group number 1 is connected to the central tapping point N 4 of the reference ladder. Since the sequence number of the differential pair is equal to the sequence number of the tapping point, this will be the differential pair D 4 . Two residual groups of residual tapping points, i.e. tapping points which are not yet used, are left at either side of the tapping point D 4 . Each of these residual groups again has a central point, i.e. the tapping point N 2 and the tapping point N 6 . These tapping points are connected to the gates of the second transistors T 2 of the two differential amplifiers of group 2, i.e. the differential amplifiers having the sequence numbers 2 and 6. Again residual groups of unused tapping points remain at either side of the tapping points N 2 and N 6 , i.e. N j and N 3 at either side of N 2 and N 5 and N 7 at either side of N 6 . These residual groups comprise only one tapping point. These four tapping points are connected to the gates of the second transistors T 2 of the four differential amplifiers of group 3, i.e. the differential amplifiers with the sequence numbers 1 , 3, 5 and 7. For N=4 there are four groups G = l , 2, 3 and 4 of 1, 2, 4 and 8 differential amplifiers, respectively, of which the gates of the second transistors should be connected to 15 tapping points. The gate of group G = l is then connected to the tapping point N 8 ; the gates of group G=2 to the tapping points N 4 and N 12 ; the gates of group G=3 to the tapping points N 2 , N 6 , N 10 and N 14 ; and the gates of group G =4 to the tapping points N, , N 3 , N 5 , N 7 , N 9 , Each group has one current source, i.e. a current source CS, for group 1, a current source CS 2 for group 2 and a current source CS 3 for group 3. Consequently, there are only N=3 current sources instead of 2 N -1 =7 current sources in Fig. 1. Each of the current sources is connected to a common terminal CN of the differential pair having the smallest sequence number within the relevant group, i.e. the current source CS j is connected to the common terminal CN 4 of the differential pair D 4 of group 1 ; the current source CS2 2 is connected to the common terminal CN 2 of the differential pair D 2 of group 2; and the current source CS 3 is connected to the common terminal CN j of the differential pair D j of group 3. Within each group of more than one differential amplifier the differential amplifiers are stacked in such a manner that the common terminal CN ; of a differential amplifier D ; having a higher sequence number i within this group is coupled to the drain of the first transistor T ] of the differential amplifier having the next lower sequence number within the relevant group. Thus, in group 2 the common terminal CN 6 is connected to the drain of the first transistor T* of the differential amplifier D 2 of group 2. In group 3 the common terminal CN 7 is connected to the drain of the first transistor T j of the differential amplifier D 5 , the common terminal CN 5 to the drain of the first transistor T, of the differential amplifier D 3 , and the common terminal CN 3 to the drain of the first transistor T* of the differential amplifier D* . Each group includes one latch, i.e. the latch L j for group 1 , the latch L-*. for group 2 and the latch L 3 for group 3. This means that there are only N=3 latches instead of the 2 N -1 =7 latches in Fig. 1. Each of the latches has a first latch input terminal LI, , a second latch input terminal LI 2 and a latch output terminal LO, which supplies one bit of the Gray-code output signal V out . The latches are clocked in a manner similar to that shown in Fig. 1. The drain of the first transistor T* of the differential amplifier having the highest sequence number within a group is coupled to the first latch input terminal LI, of the latch belonging to that group. Consequently, the drain of the first transistor T- of the differential pair D 4 of group 1 is coupled to the first latch input LIj of the latch L- ; the drain of the first transistor T j of the differential pair D 6 of group 2 is coupled to the first latch input LI j of the latch L- ; and the drain of the first transistor T j of the differential pair D 7 of group 3 is coupled to the first latch input LI j of the latch L 3 . The drains of the second transistors T 2 of the differential pairs of descending sequence number within a group are alternately coupled to the second latch input terminal LI 2 and the first latch input terminal LI, of the latch belonging to that group. This means that the drain of the second transistor T 2 of the differential pair D 4 of group 1 is coupled to the second latch input terminal LI 2 of the latch L,. The drain of the second transistor T 2 of the differential pair D 6 of group 2 is coupled to the second latch input terminal LI 2 of the latch 1^, and the drain of the second transistor T 2 of the differential pair D 2 of group 2 is coupled to the first latch input terminal LI, of the latch 1^. In the third group the drains of the second transistors T 2 of the differential pairs D 7 and D 3 are coupled to the second latch input LI 2 of the latch j and the drains of the second transistors T 2 of the differential pairs D 5 and D* are coupled to the first latch input LI*, of the latch j . The latches L j , 1^ and j directly produce a Gray-coded 3-bit digital signal at their outputs LO. Consequently, in contradistinction to the known analog-to-digital converter shown in Fig. 1 , no code converter is required. Moreover, a smaller number of current sources CS, and a smaller number of latches L j are needed, which results in a substantial reduction in current consumption and chip area. Owing to the smaller number of latches the resulting noise level is also smaller, which is favourable in the case of a combination with analog functions on one chip, or one module or one printed circuit board. The invention has been described for N=3 bits but an extension to a more bits is possible when the indications given for the 3-bit version are observed. The PMOS transistors may be replaced by NMOS transistors. Implementation by means of vacuum tubes (triodes) or bipolar transistors is not excluded. In the case of bipolar transistors the first main electrode, the second main electrode and the control electrode correspond to the emitter, the collector and the base, respectively.

Claims: Claim: An analog-to-digital converter for converting an analog input signal (V in ) into an N-bit digital output signal (V out ), N being an integer greater than 0, comprising: an input terminal (IT) for receiving the analog input signal; a series arrangement (RL) of a multiplicity of resistors which are connected to one another at 2 N -1 tapping points (N j ), numbered in ascending order with sequence numbers 1 through 2 N -1, to supply 2 N -1 different reference voltages derived from a voltage source which is connectable to the series arrangement; a plurality of 2 N -1 differential pairs (D j ), numbered in ascending order with sequence numbers 1 through 2 N -1, each differential pair (D ; ) comprising a common terminal (CN j ), a first transistor (T j ) having a first main electrode connected to the common terminal (CN j ), a second main electrode, and a control electrode coupled to the input terminal (IT), a second transistor (T 2 ) having a first main electrode connected to the common terminal (CN j ), a second main electrode, and a control electrode coupled to a tapping point (N j ) having the same sequence number as the relevant differential pair (D j ); - a plurality of current sources (CS;) coupled to the common terminal (CNj) of a number of differential pairs (D ; ); a plurality of latches (L j ) each having a first latch input terminal (LI,) and a second latch input terminal (LI 2 ) coupled to the second main electrodes of the first (T j ) and the second (T 2 ) transistor of the differential pairs (Dj), characterised in that the plurality of 2 N -1 differential pairs (D j ) is divided into N groups having a group number G, G being an integer from N through N, the group having the group number G comprising 2 G" ' differential pairs; the control electrode of the second transistor (T 2 ) of the group having the group number G = 1 is connected to the central tapping point (N 4 ) of the 2 N -1 tapping points (N j ), leaving residual groups of residual tapping points at either side of the central tapping point (N 4 ); the control electrodes of the second transistors (T 2 ) of the group having the group number G =2 through N are connected to different central tapping points of the residual groups of residual tapping points left by the preceding group having the group number G-l; for each group: the common terminal (CN;) of the differential amplifier (D j ) having the lowest sequence number within the relevant group is coupled to a respective current source (CSl, CS2, CS3) of the plurality of current sources; the common terminal (CN j ) of a differential amplifier having a higher sequence number in the relevant group is coupled to the second main electrode of the first transistor (T j ) of the differential amplifier having the next lower sequence number in the relevant group; the second main electrode of the first transistor (T j ) of the differential amplifier having the highest sequence number within the relevant group is coupled to the first latch input terminal (Lit) of a respective latch (L j , 1^, 3 ) of the plurality of latches; and the second main electrodes of the second transistors (T 2 ) of the differential amplifiers within the relevant group are coupled alternately, in accordance with descending sequence numbers, to the second latch input terminal (Ll 2 ) and the first latch input terminal (LI,) of the respective latch (L,, L- , L 3 ); the respective latch having a latch output terminal (LO) to supply a respective bit of the N-bit digital output signal (V out ) in response to a difference signal between the first latch input terminal (Ll,) and the second latch input terminal (Ll 2 ) of the relevant latch.

Inventors: MES JOHANNES ANTONIUS MARIA, MES, JOHANNES, ANTONIUS, MARIA
Applicants: PHILIPS ELECTRONICS NV, PHILIPS NORDEN AB, PHILIPS ELECTRONICS N.V.
Application year: 1996
Main classification: H03M1
IPC codes: H03M1, H03M7