Emulation system having multiple emulated clock cycles per emulator clock cycle and improved signal routing

Abstract: A logic emulation system for emulating the operation of a circuit. A uniform routing architecture is provided where a first set of selectors (multiplexers) is coupled to a set of shift registers that are in turn coupled to a second set of selectors. The outputs of the second set of selectors are coupled to the inputs of the logic processors. The arrangement of first selectors coupled to shift registers coupled to second selectors coupled to logic processors ensures that uniform routing exists among all of the logic processors in the emulation system. This, in turn, provides a flat programming model so that compilation steps including technology mapping and scheduling are independent of each other, resulting in faster compile times.

Description: This invention relates generally to digital emulation systems and specifically to a digital emulation system using multiple logic processors with improved signal routing. As electronic circuit designs continue to increase in speed and complexity, it becomes ever more critical to test the developing circuit designs at various stages of development. Hardware emulators provide a means to test complex circuit designs as the designs are being developed. Such emulators typically provide configurable hardware that is controlled by software to perform the functions of a circuit being designed. The circuit design is specified by a set of data which defines the circuit structure and behavior. Emulators operate under software control. The circuit design is "compiled" to produce the program that controls the emulator. The process of compiling the design to produce the program for the emulator is a critical and lengthy process. A lengthy compile time is due, in part, to the goal of producing a program that emulates the circuit design as fast as possible. Speed is of the essence in emulators because inevitably the emulator cannot perform the functions of the circuit being emulated as quickly as the actual circuit, itself. It is desirable to operate the emulator at speeds as close as possible to the target operating speed of the emulated circuit for purposes of accurately interfacing the design to external circuits or other devices and to test the circuit for timing problems. Another reason why the compilation step is complex and time consuming is that constraints in the hardware of the emulator make it difficult to optimize the program for speed without making many computations during compilation. Since an emulator must perform the functionality of a wide range of circuit designs, it should be as flexible as possible. This means the emulation system must contain logic processing hardware that is reusable for different designs. Such an emulation system would contain a large number of general purpose processing elements that are used to indirectly perform the function of the circuit being emulated. For example, a general purpose emulator would process multiple boolean logic equations to emulate a multiplier circuit rather than use a dedicated hardware multiplier for the same purpose which would then become unusable in the emulation of circuit designs which do not contain any multiplier functions. In order to solve these equations, many gates, or other devices, in the emulator must be provided with signals. Further, the outputs of the gates or other components must be routed efficiently among the various components of the emulator. Even though the compilation step is complicated and lengthy, it is necessary to make this step as brief as possible so that a human designer does not have to wait a long time before emulating the latest design change. This is especially important where emulators are used in the design and development of integrated circuits. Many incremental changes are made, each of which requires a compilation step before emulation can proceed. This implies that the time of the compilation step should be shortened in order to increase the utility of the emulator. Document US-A-4 306 286 discloses a simulation machine having an array of specially designed parallel processors, which can be assembled into an array without a limit to the number of processors. Document EP-A-0 336 243 discloses a simulation machine for simulating a logic network in several levels of hierarchy, having a plurality of logic units, which are connected to a plurality of switch units via a cable network. In document EP-A-0 449 579, a logic simulation machine is described including a host interface which comprises a FIFO-buffer which is located between the logic simulation machine and the host computer to buffer data until a receiver is ready to receive data. In view of the above mentioned drawbacks, it is desirable to produce an emulator that provides for short compilation times and that produces an emulation program capable of emulating a circuit design at a high speed. SUMMARY OF THE INVENTION The present invention uses an improved routing and processing architecture to allow signals to be exchanged between multiple processors within an integrated circuit or between integrated circuits. The use of selectors coupled to shift registers that, in turn, feed additional selectors that output to logic units, or logic processors, provides a flexible architecture while also providing a uniform programming model that results in fast compile times. In a preferred embodiment, an emulation system for emulating a circuit design is fabricated on a chip and includes first selectors coupled to a plurality of input signals. Some of the input signals to the first selectors include outputs from the logic processors on the same chip as the first selectors while other input signals are from logic processors in other integrated circuits. Shift registers, or "pipes," are provided whose inputs are the outputs of the first selectors. The shift registers provide for storing the signals from the first selectors in accordance with the program steps of a program that is used to control the emulation system. Second selectors coupled to the outputs of the pipes are used to further select the signals to be applied to an individual logic processor. The outputs of the second selectors are fed to the inputs of the logic processors. This arrangement of selectors, shift registers and logic processors provides a uniform routing scheme with resulting advantages in both speed of compilation before the emulation phase and speed of execution during the emulation phase. BRIEF DESCRIPTION OF THE DRAWINGS Fig.1 is a system level block diagram of a single integrated circuit in the emulator of the present invention.; Fig. 2 shows an expanded diagram of the routing of some functional blocks in Fig. 1; Fig. 3 shows more details of the circuitry of first functional blocks in Fig. 1; Fig. 4 shows an expanded diagram of the logic in the logic unit block of Fig. 1; Fig. 5 shows more detail relating to the input wand circuitry of Fig. 4; Fig. 6 shows more detail in the emulation memory block of Fig. 1; Fig. 7 shows a board level configuration of 12 logic unit chips of the present invention; Fig. 8A shows an example of a circuit to be emulated; Fig. 8B shows the timing diagram for the circuit of Fig. 8A; Fig. 9 is an illustration of a computer system suitable for use with the emulation system compiler of the present invention; Fig. 10 is an illustration of basic subsystems in the computer system of Fig. 9; Fig. 11 shows a technology mapping of the circuit of Fig. 8A; Fig. 12 shows assignments of logic functions to logic processors; Fig. 13 shows assignments of logic processors to timeslices and bus wires; Fig. 14 shows the assignment of inputs to bus wires; Fig. 15 is an input/output mapping for processors in timeslice 1; Fig. 16 is an input/output mapping for processors in timeslice 2; Fig. 17 shows the mux settings for the 1K:1 selectors in timeslice 1; Fig. 18 shows the mux settings for the 1K:1 selectors in timeslice 2; Fig. 19 shows the settings for the 48:1 multiplexers in timeslice 0; Fig. 20 shows the settings for the 48:1 multiplexers in timeslice 1; and Fig. 21 shows the settings for the 48:1 multiplexers in timeslice 2. DESCRIPTION OF THE PREFERRED EMBODIMENT Fig. 1 is a system level block diagram of a single "chip" in a preferred embodiment of the emulator of the present invention. The design shown at the system level as chip 100 in Fig. 1 is fabricated on a single integrated circuit (IC) package referred to as the Hydra Chip. Additional Figs. 2-7 show board-level and block-level details of the logic emulator system. Although a specific embodiment of an emulator is discussed for illustrative purposes, the scope of the invention is not limited to this specific embodiment. In Fig. 1, chip 100 includes various subcircuits for performing specific functions. The subcircuits are shown as blocks in Fig. 1, such as control data 102. In discussing the emulation system the architecture of the logic emulation system is presented in the section immediately below. Next, a detailed discussion of selected subcircuits in the logic emulation system is presented with a focus on subcircuits 106112 which concern the selector and shift register routing of data to the Hydra logic units ("HLUs") that give the logic emulation system a special advantage in its ability to universally and uniformly route variable data among the HLUs. In a subsequent text section an example of compiling a circuit for execution in the emulation system is provided. I. Logic Emulation system Architecture In Fig. 1, control data 102 is used to store the microcode control words that direct the operation of the Hydra Chip ("chip") . In the preferred embodiment, control data 102 provides for 64 control wards, each of approximately 10,000 bits in width. Various numbers of bits in each control word are routed, by means of control lines, to other functional blocks on the chip to control, e.g., n:1 selectors, shift registers, pass gates, signal inversion, as discussed below. For ease of illustration the control lines are omitted from Fig. 1. However, it will be apparent that the control words may be used in manners well-known in the art to control the various devices and functional blocks. Control data 102 is loaded with up to 64 control words of the control program generated by a compiler. The compiler is software that receives, as input, a specification of a circuit to be emulated and outputs a control program in the form of equations and control logic to cause the chip to emulate the desired circuit. The words of the control program are executed each emulation cycle, where an emulation cycle is one cycle of the emulated circuit. That is, if a circuit being emulated runs at 1 MHz the emulation cycle is 1.0 uS. This means that all of the steps in the program must complete within 1.0 uS. Since there are a maximum of 64 program steps allowed, the emulator clock would run at 64 MHz maximum. If there are less than 64 program steps, the emulator clock speed can be slowed down accordingly. The emulator includes the ability to lengthen any of the program steps by up to three additional emulator clock cycles. This is useful for interfacing the emulator to target hardware requiring longer access times. When program steps are lengthened this naturally extends the overall program cycle accordingly. Programmable outputs RAM 104 is a 16 x 256 bit random access memory (RAM) to provide the chip with a way to send predefined output values to external circuitry. As shown in Fig. 1, 12 bits exit from the chip to the outside world for use in interfacing to external circuits. The other four bits of each word are "internal use" bits used to control chip functions. Programmable outputs RAM 104 allows the compiler to define "canned" output values for output at specified times within an emulated clock cycle. There are 256 addresses that are sequenced in order according to the emulator clock. There are four times as many word locations in RAM 104 as there are control data word locations in control data 102 because the chip allows for control data cycles to be extended by up to three additional cycles. Thus, each of the 64 control words can be maintained on the output lines of control data 102 for up to four cycles. Meanwhile, the address locations of RAM 104 are still incremented. This allows values from RAM 104 to be output within a control word cycle when the control word is being extended. The rate at which RAM 104 is sequenced, using the present example, is 64 MHz. Functional blocks 106-112 form the heart of the routing and processing ability of the chip. These blocks are discussed in detail, below. Essentially, blocks 106-110 provide multiplexing and shift register/storing ability for variable values that are fed to HLUs 112 for processing. Functional block 112 includes 8 logic units, each consisting of four Hydra Logic Processors ("processor") with four outputs, for a total of 32 outputs. These outputs from the 8 internal logic units are included as inputs to 3:1 Selector 114. 3:1 Selector 114's other inputs include signals from the backplane (designated as BPlane in) via 32:1 Selectors 112. This allows any of the 32 backplane signals to be routed to any of the inputs of 3:1 selector 114. The backplane signals are inter-board signals. The board-level design of the logic emulation system is discussed below in connection with Fig. 7. The third set of inputs to 3:1 Selector 114 is from Memory 124. Memory 124 is connected to the output of 3:1 selector 114 to allow the emulation system to emulate a RAM, or multiple RAMs, in the user's circuit design. The outputs of 3:1 Selector 114 are provided to 2:1 Selector 120 and to pin pads in the chip. 2:1 Selector 120 acts to return the signals back to the inputs of the HLUs via the routing arrangement of blocks 106-110. Thus, 3:1 Selector 114 allows the system to select from among three separate signal sources to output to processors both within, and external to, the chip on which the processor function of the emulation system of the present invention is fabricated. In the preferred embodiment, Memory 124 is a 4K x 32 bit RAM. The RAM is addressed from signals generated by the HLUs local to the chip, and external to the chip, via the backplane. One or more bits of the address may be obtained, and stored for use each emulator cycle. The address is built and latched piecemeal over one or more cycles so that the system has wide flexibility in emulating the address logic in the circuit design being emulated. The structures for latching and applying the address are not shown in Fig. 1. Data values for the RAM are obtained from the outputs of the HLUs, from the backplane, or from the RAM, itself. Register 116 provides for storing the output values from the HLUs so that they may be delayed by one emulator cycle or more. Whether the current variable values, or the stored variable values from register 116, are output is determined by single mode bit 118 attached to the control line of 2:1 selector 120. Single mode bit 118 is obtained from one of the four "internal use" bits of RAM 104 discussed above, thus it is changeable each emulator clock cycle. 32:1 selectors 126, AND gates 128 and RAM 130 allow signals from the HLUs to be selectively output onto the backplane for use by processors on other boards. The signals are placed onto the backplane bus by using open-collector drivers so that the signals from each chip are effectively "wire ORed" onto the backplane. RAM 130 is loaded by the compiler and is used to enable specific signals onto the backplane each emulated clock cycle since one of each of the used control words in RAM 130 is addressed consecutively once each emulated clock cycle. 32:1 selectors 132 are used along with drivers 134 and RAM 136 to output breakpoint control signals. RAM 136 functions similarly to RAM 130 in that it is loaded by the compiler as part of the emulator program and its address is incremented once each emulator clock cycle. Breakpoints are implemented by having the HLUs evaluate equations to check for signal (i.e., variable) states and, upon detecting the desired combination, outputting a high signal that is selected by 32:1 selector 132. 32:1 selector 132 is controlled, as are the other selectors of Fig. 1 except for selector 120, by control signals from control data 102. The routing and processing of blocks 106-112 will next be discussed in detail. A. Routing Functional blocks 106-112 are the core of Hydra Chip 100's routing and processing. Since the chip relies on multiple emulator cycles per emulated cycle it is crucial that data can be quickly and easily routed between the various local and remote (i.e., on-chip and off-chip) processors so that several iterations of processing data with the same logic units (discussed below) can be efficiently achieved. In Fig. 1, 256 48:1 selectors are used to choose from among 32 internal signal lines and 352 external signal lines. The 32 internal signal lines are fed back from the outputs of the 8 HLUs 112 while the external signal lines are from 11 external processors, each identical to the diagram of Fig. 1, to provide 11 x 32 = 352 signals. Thus, the total number of signals entering the 256 48:1 selectors 106 is 352 + 32 = 384. Each of the 384 signals is distributed to 32 inputs in the 256 48:1 selectors. Thus, the total number of inputs in the 48:1 selector group is 32 x 384 = 12,288. The 48:1 selectors output 256 signals to 256 shift registers 108. The routing is one-to-one with each 48:1 selector output feeding a single 64 stage, or 64 bit, shift register input. The combination of 48:1 selector and shift register is referred to as a "pipe." Each stage of each shift register is output so that the number of outputs from the shift register group is 64 x 256 = 16,384 outputs. The 16,384 outputs are provided to the 128 1K:1 selectors. The outputs of the 1K: I selectors are sent to 8 HLUs 112. Each HLU receives the outputs from 16 1K:1 selectors. Fig. 2 shows an expanded diagram of the routing of blocks 106-112. In Fig. 2, 384 signals at 150 are provided to pipes at 154. The interconnections between the 384 signals and the pipes is at 152. A preferred interconnection scheme distributes each of the 384 signals to 32 different inputs of the 48:1 selectors. The preferred interconnection allows for routing each signal to 16 pairs of 64 bit shift registers. The pairs are separated so that the input signal fanouts have the smallest overlap possible. Connections between pipes at 154 and selectors at 158 are such that consecutive groups of 8 1K:1 selectors receive the same 1024 outputs from a group of 16 shift registers. For example, in the first group of 8 1K:1 selectors (selectors 0-7), each selector receives the same 1024 outputs from shift registers 0-15. In the next group of 8 1K:1 selectors (selectors 8-15), each selector receives the same 1024 outputs from the next 16 shift registers (shift register numbers 16-31) and so on. Connections at 160 between 1K:1 selectors at 158 and HLUs at 162 are assigned by taking sixteen of the 1K:1 selectors modulo 16. For example, HLU 0 is connected to 1K:1 selectors 0, 16, 32, 48, . . ., 112. HLU 1 is connected to 1K:1 selectors 1, 17, 33, 49, . . ., 113. Fig. 3 shows more details of the circuitry of functional blocks 106 and 108 of Fig. 1. Specifically, Fig. 3 shows the inclusion of a "shadow" shift register 180, 64:1 selector 182 and 2:1 selector 184. 48:1 selector 186 and shift register 188 are the same components discussed above and shown in Fig. 1 as 106 and 108, respectively. The use of shadow shift register 180 provides distinct advantages in the ability of the emulation system of the present invention to handle logic elements such as flipflops where the state of the logic element which was computed during the current emulated clock cycle is not required as an input to other logic elements until the next emulated clock cycle. Shift register 188 is used to store results of computations in each of the 64 (maximum) steps in the emulation program. However, a special case occurs where, for example, a flip flop output, or any other "registered" signal, is not required until the next cycle. These registered signals must not be updated for use until the end of the current emulated clock cycle. Thus, the shadow register is used to store the values of these types of registered variables from the time they were generated until the time they are required as inputs to logic functions. At the end of the program cycle, i.e., after all program steps have been executed for the current cycle, the values from shadow shift register 180 are copied into shift register 188 so that the new values for these registered variables are available for use as inputs to the next program cycle. The copying is performed by loading shift register 188 with the parallel outputs of shadow shift register 180. This allows for time-independent routing of all "registered" signals through the emulator since the signals are not required until the following program cycle. As can be seen from Fig. 3, values from 48:1 selector 186 are routed both to shadow shift register 180 and, selectively, to shift register 188 via 2:1 selector 184. Where the value from 48:1 selector 186 is a registered variable, the registered variable is copied to shadow shift register 180, only, and not to shift register 188. Instead, shift register 188 receives a value from 64:1 selector 182 which is generated during the previous program cycle so that any registered variables that change during the current program cycle are not updated until the next program cycle. 64:1 selector 182 allows values from anywhere within shift register 188 to be routed back to stage 0 of the shift register. This allows flexible access to variable values that are computed within a program cycle. The selection of variable through 64:1 selector 182 is by the six control lines shown connected to 64:1 selector 182 and which are controlled from the control data. Other control signals such as the five input multiplexer (MUX) lines to 48: 1 selector 186 and single control line to 2:1 selector 184 also issue from the control data. B. Processing Next, Figs. 4 and 5 are discussed to illustrate details of the Hydra logic units used for processing in the emulation system of the present invention. Fig. 4 shows an expanded diagram of the logic in block 112 of Fig. 1. In Fig. 4 j one or 8 HLUs on the chip is shown. Sixteen inputs from 16 of the 1K:1 selectors enter the HLU at 202. The inverted signals are also provided so that a total of 32 signals is represented by the dark shaded line. The 16 signals are coupled through inverters and pass gates, also called input "wands, 11 shown in larger scale and more detail in Fig. 5, to the OR gates 206-212. Each of the 16 signals can be passed through each of the input wands so that any of the signals can be applied to any of the inputs of the OR gates 206-212. Note that each of the lines to the OR gates is provided with a NOR gate such as NOR gate 214 so that each input to the NOR gates can be selectively disabled with the application of a zero, or low, signal. OR gates 206-212 are used to compute sum-of-products terms to solve boolean equations that emulate the functions of the user's circuit design. The compiler converts the user circuit design into boolean equations which are then converted into multiple program steps. The program steps are loaded into the emulation architecture in the form of microcode words in control data 102 of Fig. 1 and control signals in various select RAM throughout the system. Returning to Fig. 4, register emulation logic 220 is provided at the output of each of the OR gates. Register emulation logic 220 provides specialized control signals to allow the emulator to handle sequential element emulation, such as registers and latches, in an efficient manner. Signals such as "Reset," "Preset, 11 "Clock" and 'IQ-111 represent signals of their well-known counterparts in standard sequential devices. These signals are obtained from the 16 input signals and their inverted signals by using 34:1 selectors as shown, for example, at 222. Note that the 34:1 selectors allow a high or low signal to be selected in addition to the 16 input signals and their inversions. Signal "Q-1" is normally the previous value of what was stored in a register being emulated. The invert control bit of register emulation logic 220 allows inversion of the data signal according to control data. The P/R control signals determine whether a preset or reset will be controlling when both a preset and reset occur at the same time. The P/R control lines are coupled to control RAM, as are the two control bits to the 2:1 selector of register emulation logic 220. The 2:1 selector provides for a bypass of the register emulation logic when it is not needed. Fig. 6 shows more detail in functional block 124, the emulation memory, of Fig. 1. The emulation memory circuitry provides an efficient way for the values generated from the HLUs to be stored and used in addressing the emulation memory. Fig. 7 shows a board level configuration of 12 Hydra chips. Fig. 7 includes backplane 250 that can accommodate additional similar boards. Devices (16646) are register transceivers while devices (74FB2033) are backplane interface transceivers. II. Logic Emulation System Compiler Operation . Fig. 8A shows a circuit 300 as an example of a circuit that a user wishes to emulate. Circuit 300 is a 4-bit binary counter with outputs QO-3, termination count inputs CO-3, RESET and CLOCK signals. Termination count inputs CO-3 are used to specify when the counter resets. When the count on QO-3 matches the value specified on CO-3 the counter resets to 0 and resumes counting up. Fig. 8B shows the timing diagram for the circuit of Fig. 8A. In Fig. 8B, outputs QO-3 are shown to output different values (0, 1, 2 and 3) at different points in time according to the other signals CLOCK, RESET and terminal count bits CO-3. For example, at 302 outputs QO-3 output the value 0. At 304, outputs QO-3 output the value 1. At 306, outputs QO-3 are reset to the value 0 since terminal count bits CO-3 specify a terminal count of 1 at 308. Similarly, QO-3 are shown incrementing up to the terminal count currently specified for subsequent portions of the timing diagram. Note that the count changes on the leading edge of CLOCK and that whenever RESET is high the count becomes 0. Fig. 9 is an illustration of a computer system suitable for use with the emulation system compiler of the present invention. Fig. 9 depicts but one example of many possible computer types or configurations capable of being used with the present invention. Fig. 9 shows computer system I including display device 3, display screen 5, cabinet 7, keyboard 9 and mouse 11. Mouse 11 and keyboard 9 are "user input devices." Other examples of user input devices are a touch screen, light pen, track ball, data glove, etc. Fig. 10 is an illustration of basic subsystems in computer system 1 of Fig. 9. In Fig. 10, subsystems are represented by blocks such as central processor 52, system memory 54, etc. The subsystems are interconnected via a system bus 50. Additional subsystems such as a printer, keyboard, fixed disk and others are shown. Other arrangements of subsystems and interconnections are possible. The compiler accepts an electronic description of circuit 300 as input. In the preferred embodiment, many formats for the electronic description of a circuit are accepted such as the Verilog hardware description language. The compiler performs steps of "technology mapping" the circuit to map operations of the circuit to processors within the emulation system. The operations are converted to equations that one or more processors can solve within one cycle of the emulated circuit. The compiler also performs the step of "scheduling" the solution of the equations to insure that the results of equations that are needed as inputs to other equations are obtained before the other equations are executed. The steps of technology mapping and scheduling are performed advantageously in the present invention by making use of the uniform logic units and routing architecture described in section I, above. The compiler uses the results of the technology mapping and scheduling steps to output an emulation program that is loaded into the control store, multiplexer select RAM and other portions of the emulation system to control the emulation system to solve the equations. Note that the solution of the equations is performed by executing up to 64 program steps within a single emulated clock period (i.e., the period of CLOCK in Fig. 8B). The compilation procedure is made more efficient due to the uniform connectivity of signals in the emulation system resulting in a "flat" programming model. This insures that, after technology mapping, subsequent scheduling steps will not affect the routability of the design being emulated. In other words, the technology mapping and scheduling steps are completely independent of the routing phase of the compilation and of each other. Fig. 11 shows a technology mapping of the circuit of Fig. 8A. In Fig. 11, the circuit has been divided into 7 logic functions labeled A-G. Note that each logic function is a sub-function in the operation of the circuit of Fig. 11, and each logic function can be realized by one logic processor. Each sub-function has clearly defined inputs and outputs and can be computed within each emulation clock cycle, or program step. At most, there are three logic "stages," or dependencies on signals that could arrive at different times in an emulation cycle. The circuit of Fig. 8A is simple enough that the technology mapping and scheduling can be accomplished manually as in the diagram of Fig. 11. For purposes of illustration, seven logic functions are chosen in this example. Note that logic functions F and G include functionality that has been added to the circuit. This functionality accurately accounts for edge transitions in the clock signal, CLOCK. Since the registers which generate QO-3 are positive edge sensitive, logic functions F and G include an emulated delay element coupled to emulated positive edge detection logic to generate a signal indicating a positive CLOCK edge transition. Fig. 12 shows assignments of the logic functions to logic processors (there are 32 logic processors, or 8 logic units, per chip, as discussed above in connection with the architecture of Figs. 1-7), the inputs to each logic function, the earliest time that an input is needed (given in program steps), the output of the logic function and the latest time at which the logic function's output must be available. For the present example, each logic function in Fig. 11 is assigned to a separate processor. Each HLU has the ability to form four discrete sum-of-product terms and produce four outputs (i.e., four processors). So, for example, a single HLU can be used to handle logic functions A-D while a second HLU can handle logic functions E, F and G. However, as discussed below, the present example allows for a single HLU to handle all of the computations within three program steps. Because of the uniformity of routing in the emulator the assignments of HLUs, and processors within HLUs, are completely arbitrary with respect to routability. Returning to Fig. 12, logic function A includes signals QO, CLEAR and CLOCK_POSEDGE. Signals QO and CLEAR are inputs from the user's external circuitry that are interfaced to the emulation system as they would be with the actual circuit under emulation. Signal CLOCK_POSEDGE is generated as an output from logic function G to indicate the clock rising edge. Note that CLOCK_POSEDGE is generated from the signal CLOCK which is the user's clock from the circuit being emulated. In logic function A, signal QO is needed at program step 0, signal CLEAR is needed at program step 2 while signal CLOCK_POSEDGE is also needed at program step 2. Logic function A's output is QO which must be generated, at the latest, by the next program cycle. In the present example there are only three program steps, occupying "timeslices" 0, 1 and 2. Each program step is performed during one clock period of the emulator clock. The emulator clock is generally operated as fast as possible since, inevitably, an emulated circuit is designed to be operated at a speed greater than the speed of the emulation program cycle. As mentioned, program steps can be extended to up to four emulator clock cycles where, for example, delays in the emulator require that the emulation system remain in a predetermined state, corresponding to a specific program step, for more than one cycle. In Fig. 12, the remaining logic functions B-G are designated similarly to logic function A. Fig. 13 shows assignments of logic processors to timeslices and bus wires. For example, output value QO is assigned to timeslice 2 and bus wire 355. As discussed above, there are 384 bus wires (O through 383) that are inputs to the 48:1 selectors. Bus wires 352 through 383 contain results which originate from logic units 0-7. The present example circuit design uses logic unit 0 exclusively and all of the signals are generated and used within a single chip containing the logic unit. In this case, no inter-chip data exchanges are necessary for the emulation. Note that signals CLEAR, CLOCK_DELAYED and CLOCK_POSEDGE are generated in timeslice while signals QO-3 are generated in timeslice 2. Fig. 14 shows the assignment of inputs to bus wires. The signals CO-3, RESET and CLOCK represent the six external inputs to the emulator. Each of the inputs are assumed available and valid at the beginning of the program cycle, i.e., at program step 0, when they are sampled. Figs. 13 and 14 represent the results of the scheduling step in the compilation process. The scheduling problem is to ensure that output values that are needed for a given calculation are available before the calculation requires the value. In other words, any calculation necessary to generate a value must be performed, or scheduled, ahead of the time that a subsequent calculations can use the value. This is a trivial problem in the present simple example, the solution of which is presented in Figs. 13 and 14, but can be a very time consuming step in the compilation procedure where the circuit being emulated is large. An advantage of the present invention is that, contrary to prior emulation systems and compilers, the scheduling step does not influence the routability of the emulated design. This is due, in part, to the processors being fungible commodities in the emulation system of the present invention because there is no advantage to using a given processor over another in terms of input or output routing capability since all of the routing at the Hydra chip level is uniform among the processors. Figs. 15 and 16 show input and output mappings for the different processors in timeslices 1 and 2, respectively. Thus, it can be seen that, in Fig. 15, the signals CLEAR, CLOCK_DELAYED and CLOCK_POSEDGE are generated from the values CO-3, RESET, QO-3, CLOCK and CLOCK_DELAYED. The output CLOCK_DELAYED is generated by using register emulation logic such as that shown at 220 of Fig. 4. Similarly, Fig. 16 shows the mapping for signals computed in timeslice 2. Figs. 17 and 18 show the mux settings for the 1K:1 selectors that are relevant for the processing of the present example. No settings are shown for timeslice 0 since the signals are not required for logic processing until timeslice 1. Figs. 19-21 show the mux settings for the 48:1 muxes in timeslices 0, 1 and 2. In the foregoing specification, the invention has been described with reference to a specific exemplary embodiment thereof.

Claims: An emulation system for emulating a circuit design, wherein the emulation system includes a logic processor (112) for solving equations to emulate the circuit design, wherein the logic processor (112) includes logic processor inputs and logic processor outputs, the emulation system comprising: a first selector (106) having first selector inputs and first selector outputs, wherein one of more outputs from the logic processor (112) are coupled to the first selector inputs, wherein the first selector (106) selects a subset of signals at the first selector inputs and applies the selected signals to the first selector outputs; a register (108) having register inputs and register outputs, wherein the register inputs are coupled to the outputs of the first selectors (106), wherein the register (108) stores the signals received from the selectors (106); a second selector (110) having second selector inputs and second selector outputs, wherein the second selector inputs are coupled to the register outputs for selectively applying the register outputs to the second selector outputs; and wherein the inputs of the logic processor (112) are coupled to the outputs of the second selectors (110). The emulation system of claim 1, further comprising: wherein the register (108) includes the following: a first shift register (188) having a first shift register input and a first shift register output, wherein the first shift register input is coupled to a first selector output, wherein the first shift register output is coupled to a second selector input. The emulation system of claim 2, further comprising: an emulator clock source outputting an emulator clock signal for synchronizing the operation of the emulation system; a control store coupled to the emulator clock source; wherein the control store stores data defining one or more program steps, wherein the program steps are sequenced according to the emulator clock signal; and wherein the shift register (188) includes a clock input coupled to the emulator clock source so that data in the shift register (188) is shifted in synchronization with the emulator clock signal. The emulation system of claim 2 or 3, further comprising: wherein the first shift register (188) includes first shift register parallel inputs and first shift register parallel outputs; and wherein the register (108) further includes a second shift register (180) having second shift register parallel outputs, a second shift register input and a second shift register output, wherein the second shift register input is coupled to a first selector output, wherein the second shift register output is coupled to a second selector input, wherein the second shift register parallel outputs are coupled to the first shift register parallel inputs. The emulation system of one of the preceding claims, further comprising: wherein the first selector (106), register (108), second selector (110) and logic processor (112) are all fabricated on a single integrated circuit chip (100); and one or more first selector input signals coupled to signal sources external to the single integrated circuit chip (100). The emulation system of one of the preceding claims, further comprising: wherein the first selector (106) includes 256 48:1 multiplexers; wherein the register (108) includes 256 shift registers, each having an input and an output, wherein the outputs from the 48:1 multiplexers in the first selector (106) are coupled to the shift registers one-to-one, wherein the shift registers each have 64 stages and 64 bits of parallel output lines for a total of 64 x 256 = 16,384 shift register parallel output lines; wherein the second selector (110) includes 128 1024:1 multiplexers coupled to the shift register parallel output lines so that groups of 8 1024:1 selectors receive the same 1024 outputs from a group of 16 shift registers; and wherein the logic processor (112) includes 8 processors, wherein each processor includes 16 inputs, wherein the processor inputs are coupled to the outputs of the 128 1024:1 multiplexers to that the 128 1024:1 multiplexers are coupled to processors according to an assignment modulo 16. The emulation system of one of the preceding claims, wherein the circuit design is described by logic equations, wherein the circuit design includes a circuit clock signal having a circuit frequency, the emulator comprising: clock generation means coupled to the circuit clock signal for generating an emulator clock signal that is an integer multiple, n, times faster than the circuit frequency, wherein n is greater than 1; processing means for generating solutions to logic equations that emulate the circuit design; and control means coupled to the processing means for controlling the solution of the logic equations, wherein the control means is further coupled to the emulator clock signal and causes one or more logic equations to be solved each n cycles of the emulator clock.

Inventors: CHILTON JOHN, SARNO TONY, SCHAEFER INGO, CHILTON, JOHN, SARNO, TONY, SCHAEFER, INGO
Applicants: QUICKTURN DESIGN SYSTEMS INC, QUICKTURN DESIGN SYSTEMS, INC.
Application year: 1996
Main classification: G06F17
IPC codes: G06F11, G06F17