Reference system for determining the programmed/non-programmed status of a memory cell, particularly for non-volatile memories

Abstract: A reference system for determining the programmed/non-programmed status of a memory cell, particularly for non-volatile memories, which comprises: a first branch for connecting a first load (1) and a memory cell matrix; a second branch for connecting a second load (1') and at least one virgin reference memory cell (4'); means (YM, YN) for selecting a memory cell (4) of the memory matrix; and means (YM, YN) for selecting at least one virgin reference cell (4'); each one of the first and second branches having a transistor (2, 2') for enabling the flow of current respectively between the first load (1) and the second load (1') and the memory cell matrix and the at least one reference memory cell (4'); the enabling transistors (2, 2') being controlled, respectively, by a first biasing structure (3) and by a second biasing structure (3'). The reference system has the particularity that it comprises at least one transistor (5) for redistributing the current of the load (1) on the first branch, which is connected in parallel to the enabling transistor (2), and a first equalization transistor (6) that is controlled by a precharge signal (PC) for the equalization of opposite nodes of the first and second branches; the at least one current redistribution transistor (5) provides a current imbalance in the first load (1) and in the second load (1') to sense the difference in conductivity between a memory cell (4) of the memory matrix and the at least one reference cell (4'), in order to determine the programmed or non-programmed status of the memory cell (4) of the memory matrix.

Description: The present invention relates to a reference system for determining the programmed/non-programmed status of a memory cell, particularly for non-volatile memories. In non-volatile memories, such as for example EPROMs, EEPROMs, and FLASH memories, the memory cells can be exclusively in two possible conditions: programmed or non-programmed (virgin). The conductivity characteristics of the cells are therefore related to these two statuses. There are no intermediate conditions of the cells with conductivity characteristics interpolated assuredly between the two conductivity levels of a programmed cell and of a non-programmed cell, so as to be able to use this intermediate conductivity as reference to determine whether the memory cells belong to one status or the other (programmed or non-programmed). Therefore, it is necessary to plot a curve for distinguishing between the two conductivity levels of the memory cell. Various circuital techniques, developed to provide a reference that allows to determine the status of a memory cell, are commonly known. The two commonest systems are the current mirroring system, with a 2:1 and 3:1 ratio, and the so-called "current offset" system; these systems are shown in figure 1 (with details in figures 2 and 3) and in figure 4. The charts with the conductivity curves related to these systems are shown, for the sake of reference, respectively in figures 25 and 26. Figure 1 illustrates the current mirroring system with 2:1 ratio, characterized by a circuit that comprises a first branch and a second branch; the first branch connects a load 1 to a matrix of memory cells from which, by virtue of the multiplexer selection means YM and YN, a memory cell 4 of a memory matrix is selected, and the second branch connects a load 1' to a matrix of virgin reference cells, from which one cell 4' is selected by virtue of multiplexer selection means YM, YN. Enable transistors 2 and 2' for the flow of current from the loads 1 and 1' to the memory cells 4 and 4' are arranged in the first branch and in the second branch respectively. Biasing structures 3 and 3' are provided to bias the transistors 2 and 2' respectively. Figure 2 shows in detail the loads 1 and 1' in the case of a 2:1 current mirroring ratio, wherein the load 1 is constituted by a single transistor and the load 1' is constituted by two transistors. The current of the cell, designated by Icell, is mirrored in the load transistors and a current equal to Icell/2 flows in the matrix branch. If the memory cell 4 is virgin (like the reference cell 4' in which the current Icell flows), the output node provided on the matrix branch becomes low, since the load does not deliver the current that the memory cell allows to pass, i.e, Icell. The load in fact delivers only the current Icell/2. If instead the memory cell is programmed (i.e., off), the output node of the matrix branch becomes high, since even if the current Icell/2 is weak, it causes the node to become high, since the memory cell 4 is off indeed because it is programmed. This characteristic can be defined by a conductivity curve for the memory cell 4, to be compared with a conductivity curve of the virgin reference cell 4'. In summary, therefore, if the current Im on the matrix branch is Im = 0 (the cell is off and programmed), the current on the reference branch Ir is equal to 1/2 the current Iv of the virgin cell 4' for each mirroring transistor; when balancing occurs, if Im = 1/2Iv and Ir = 1/2Iv, then the state of the cell 4 cannot be determined; finally, if the cell is virgin (Im = Iv), then the current on the reference branch is Ir = Iv/2. Figure 3 instead shows in detail the loads 1 and 1' in the case of a 3:1 mirroring ratio, in which the load 1 is again constituted by a single transistor, whereas the load 1' is constituted by three transistors. The cell current, designated by Icell, is mirrored in the load transistors, and a current equal to Icell/3 flows in the matrix branch. As in the previous case, the following relations occur in the case of a cell when it is programmed, when balancing occurs, and when it is virgin: programmed: Im = 0 Ir = 1/3Iv for each mirroring transistor balanced: Im = 1/3Iv Ir = 1/3Iv for each mirroring transistor virgin: Im = Iv Ir = 1/3Iv for each mirroring transistor The purpose of the circuit shown in figure 1 is to create a curve of the conductivity of a reference cell as a function of the voltage. In this manner it is possible to compare the conductivity curve of the memory cell whose status must be determined with respect to the reference curve. Therefore, if one finds that the examined memory cell allows the same current as a reference cell to pass, then it is a virgin cell; otherwise it is a programmed cell. The reference curve thus created has the drawback that for low voltage values it has very low current difference values with respect to the actual conductivity curves of memory cells and therefore assured determination of their status is difficult. Furthermore, for high voltage values the reference curve and the conductivity curve intersect, causing incorrect cell status determination. The 3:1 mirroring circuit allows to plot another conductivity curve that is lower than the first one and allows to assuredly detect the status of a cell that might be only weakly programmed and cannot be determined with the first above mentioned reference curve. This last curve allows to provide a "margin" for reading during a verify step after programming, in order to ensure the normal reading that is performed with a 2:1 ratio. The chart of the curves of this first reference system is shown in figure 25. Figure 4 shows a so-called "current offset" reference system, in which current mirroring is performed at the level of the bit lines. The drawbacks of these known reference systems are the poor symmetry of the loads, the difficulty in biasing propagation, and higher consumption caused by the current offset. The chart with the curves of this reference system is shown in figure 26. The lack of symmetry at the loads is a problem when using sense amplifiers of the dynamic latch type that require perfect balancing. Furthermore, the vector of the current difference between the matrix current and the current of the reference branch, Im-Ir, in the most favorable conditions, is never higher than Iv/2. Another drawback is given by the fact that both of said reference systems are difficult to implement in architectures in which the roles of the reference and matrix branches swap. The aim of the present invention is therefore to provide a reference system for determining the programmed/non-programmed status of a memory cell, particularly for non-volatile memories, that allows to obtain in output a current variation that is amplified with respect to the current variation of the cell, so as to assuredly detect the status of said cell. Within the scope of this aim, an object of the present invention is to provide a reference system for determining the programmed/non-programmed status of a memory cell that is perfectly balanced as regards the loads, thus providing perfect symmetry. Another object of the present invention is to provide a reference system for discriminating the programmed/non-programmed status of a memory cell that allows to easily swap the side taken as reference with the memory matrix side that contains the cell whose status is to be determined. Another object of the present invention is to provide a reference system for determining the programmed/non-programmed status of a memory cell that allows to obtain a vector, representing the. difference between the matrix current and the reference current, that is approximately twice the vector obtained with conventional solution. Another object of the present invention is to provide a reference system for determining the programmed/non-programmed status of a memory cell that does not have current mirrorings provided in mutually distant locations, which entail propagation problems. Another object of the present invention is to provide a reference system for determining the programmed/non-programmed status of a memory cell that reduces the consumption of current with respect to conventional solution. Another object of the present invention is to provide a reference system that is highly reliable and relatively easy to produce at competitive costs. This aim, these objects, and others which will become apparent hereinafter are achieved by a reference system for determining the programmed/non-programmed status of a memory cell, particularly for non-volatile memories, which comprises: a first branch for connecting a first load and a memory cell matrix; a second branch for connecting a second load and at least one virgin reference memory cell; means for selecting a memory cell of said matrix of memory cells; and means for selecting said at least one virgin reference cell; each one of said first and second branches having a transistor for enabling the flow of current respectively between said first load and said second load and said memory cell matrix and said at least one reference memory cell; said enabling transistors being controlled, respectively, by a first biasing structure and by a second biasing structure; characterized in that it comprises at least one transistor for redistributing the current of the load on said first branch, which is connected in parallel to said first enabling transistor, and a first equalization transistor that is controlled by a precharge signal for the equalization of opposite nodes of said first and second branches, said at least one current redistribution transistor providing a current imbalance in said first and second loads to sense the difference in conductivity between a memory cell of said memory matrix and said at least one reference cell, in order to determine the programmed or non-programmed status of said memory cell of the memory matrix. Further characteristics and advantages of the invention will become apparent from the description of a preferred but not exclusive embodiment of the reference system according to the invention, illustrated only by way of non-limitative example in the accompanying drawings, wherein: figure 1 is a circuit diagram of a first conventional reference system; figure 2 is a circuit diagram of a portion of the first conventional reference system, shown in figure 1; figure 3 is a circuit diagram of the portion of the first reference system shown in figure 2, modified according to a second conventional embodiment; figure 4 is a circuit diagram of a second conventional reference system; figure 5 is a circuit diagram of a first embodiment of the reference system according to the invention; figure 6 is a circuit diagram of a second embodiment of the reference system according to the invention, wherein a double interchangeable reference system is implemented; figure 7 is a circuit diagram of a variation of the first embodiment of the reference system according to the invention, illustrated in figure 5; figure 8 is a circuit diagram of a variation of the second embodiment of the reference system according to the invention, illustrated in figure 6; figure 9 is a circuit diagram of a third embodiment of the reference system according to the invention; figure 10 is a circuit diagram of a fourth embodiment of the reference system according to the invention; figure 11 is a circuit diagram of a variation of the fourth embodiment of the reference system according to the invention, shown in figure 10; figure 12 is a circuit diagram that illustrates in detail a differential amplifier that is applied to the third embodiment of the reference system according to the invention, shown in figure 9; figure 13 is a circuit diagram that illustrates in detail a differential amplifier applied to the fourth embodiment of the reference system according to the invention, shown in figure 10; figure 14 is a circuit diagram of the fourth embodiment of the reference system according to the invention, illustrated in figure 10, in which a difference in currents between the reference and matrix branches is produced; figure 15 is a circuit diagram of one of the possible embodiments of a circuit that is adapted to produce a current difference, as shown schematically in figure 14; figure 16 is a circuit diagram of a possible embodiment of a circuit that is adapted to produce a voltage difference, as shown schematically in figure 13; figure 17 is a chart of the current on the loads, as a function of the current that flows through the memory cell; figure 18 is a chart of the difference between the memory matrix current and the current that flows in the reference branch, as a function of the current that flows in the cell; figure 19 is a chart that plots the various difference currents that can be extracted from the circuit diagram of the first embodiment of the reference system according to the invention, illustrated in figure 5; figure 20 is a chart that plots the various different currents that can be extracted from the circuit diagram of the second embodiment of the reference system according to the invention, shown in figure 6; figure 21 is a chart that plots the various currents that can be extracted from the circuit diagram of the fourth embodiment of the reference system according to the invention, shown in figure 10; figure 22 is a general chart that plots the variation of the current on the loads with respect to the current that flows through the memory cell, for the reference system according to the invention; figure 23 is a chart that plots the variation of the current on the loads with respect to the current that flows in the memory cell, for the reference system according to the invention, illustrating in particular two curves related to two different values of the parameter K; figure 24 is a circuit diagram of a possible embodiment of a biasing structure that can be used in the reference system according to the invention; figure 25 is a chart of the conductivity curves of a cell, obtained with a first conventional reference system; and figure 26 is a chart of the conductivity curves of a cell, obtained with a second conventional reference system. With reference to the above figures, and in particular to figures 5 and 6, said figures show a first embodiment and a second embodiment of the reference system according to the invention. In the various figures, identical elements are designated by identical reference numerals. With reference to figure 5, in a first embodiment the reference system according to the invention comprises two circuit branches, a matrix branch and a reference branch, to which respective loads 1 and 1' are connected. The loads can advantageously be, for example, current sources. The matrix branch comprises: a first transistor 2 for enabling the connection between the load and the memory matrix; a generic biasing structure 3; means for selecting a memory cell of a memory matrix, advantageously provided by a first decoding bus YM and a second decoding bus YN, each having sixteen lines, for decoding the read address of a memory cell; and a plurality of memory cells 4 organized into a matrix. In the various figures, a single memory cell, provided by means of a floating gate transistor, is shown for the sake of simplicity. The size of the transistor 2 is generally referenced by W. Likewise, the reference branch comprises, in addition to the load 1': a first transistor 2' for enabling the connection between the load and the reference matrix; a generic biasing structure 3'; means for selecting at least one virgin reference cell, which are advantageously provided by a first decoding bus YM and a second decoding bus YN, each having sixteen lines, for decoding a read address of a memory cell; and at least one virgin reference memory cell 4'. Each matrix cell is compared with a reference cell: if the two cells being compared are in the same half-matrix, then both are stimulated by a same word line and the reference cells are on a reference bit line. If instead the cells being compared are in two different half-matrices, then the reference cell is stimulated by appropriate reference word lines. In this case, the reference cells are aligned along a reference word line. It is also possible to use a single virgin reference cell to perform the comparison for determining the status of a memory cell of the memory matrix. A single reference memory cell 4', provided by means of a floating gate transistor, is shown in the various figures for the sake of simplicity. The size of the transistor 2' is referenced generically by W. The matrix branch also comprises a second transistor 5 for redistributing the current of the load 1; said transistor is interposed between a node A of said branch and an equalization transistor 6 that is interposed between the matrix branch and the reference branch. The gate terminal of the transistor 5 is biased, like the gate terminal of the transistor 2, by the biasing structure 3. A precharge signal PC is instead sent to the gate terminal of the equalization transistor 6. When the signal PC is high, the nodes B and B' of the matrix branch and of the reference branch, respectively, are equalized. The transistor 5 is of the same type as the transistor 2, and its size is referenced by KW, where K is a parameter that can vary according to the mirroring ratio that one wishes to obtain. For example, if one wishes a 2:1 mirroring ratio, it is necessary to assume K = 0.5. In this case, the size of the transistor 5 is half the size of the transistor 2. Figure 6 illustrates a second embodiment of the reference system according to the invention. The difference with respect to the first embodiment shown in figure 5 is the presence of a second transistor 5' for redistributing the current of the load 1' for the reference branch. This transistor 5' is identical to the transistor 5 of the matrix branch in terms of size and in terms of connection method. Therefore, the biasing structure 3' also biases the gate terminal of the transistor 5'. Furthermore, for the reference branch there is a second equalization transistor 6', whose gate terminal receives the precharge signal PC. The transistor 6' is connected exactly like the transistor 6 and is thus connected between the nodes B and B' of the reference branch. In this manner, the matrix branch and the reference branch are perfectly symmetrical and easily interchangeable. Figure 9 is a view of a third embodiment of the reference system according to the invention. This third embodiment differs from the first one in that it comprises an additional transistor 7, whose size, together with the transistor 5, is KW; said transistor 7 is connected in parallel to the branch that comprises the transistor 5. The transistor 7 is therefore interposed between the node A and the connection between the matrix and reference branches. The gate terminal of the transistor 7 is also biased by the biasing structure 3. Another enabling transistor 8 is connected between the node A and the transistor 7. The enabling transistor 8 receives, at its gate terminal, an enabling signal VERIFY that is adapted to enable the current path from the node A to the memory cell 4 after also passing through the transistor 7. This signal VERIFY, by activating the transistor 8, enables the provision of a 3:1 mirroring ratio. Figure 10 is a view of a fourth embodiment of the reference system according to the invention. This fourth embodiment differs from the second embodiment in that it comprises additional transistors 7' and 8' that are similar to the transistors 7 and 8 described for the third embodiment. Therefore, figure 10 illustrates a double interchangeable reference system, whose reference branch is identical to the matrix branch, already described in figure 9. In this case, therefore, there is another equalization transistor 6', which is similar to the transistor 6 and is driven by a precharge signal PCright (whereas the transistor 6 is driven by a precharge signal PLleft). Depending on the switching-on of the transistor 6 or 6' as a consequence of the high signals PCleft and PCright, the reference branch is swapped with the matrix branch, and vice versa. In particular, if one wishes to swap the reference branch with the matrix branch, it is necessary to switch off the transistor 6' (with a low PCright); the current will flow in the matrix branch, which now becomes the reference branch. In the various figures, the transistors that are present in the circuit are of the N-channel type. In particular, the transistors 2-2', 5-5', 6-6', 7-7', and 8-8' are native transistors with a low threshold. With reference to figure 12, said figure illustrates a reference system according to the invention, similar to the one shown in figure 9, which illustrates a differential amplifier 9 that is adapted to emit an output tension Vout that is the difference of the voltage values Vm and Vr that are present on the matrix branch and on the reference branch respectively. Likewise, figure 13 shows a reference system according to the invention, such as the one shown in figure 10, which illustrates the same differential amplifier 9 of figure 12, which has the same function that has already been described. In figures 12 and 13, the generic biasing structures 3 and 3' are shown explicitly in one of their possible circuital configurations, provided by means of a cascode circuit, which can assume a more complex form that is shown explicitly in its circuital embodiment in figure 24. Figure 14 instead illustrates the fourth embodiment of figure 10, to which a differential current amplifier 10 is applied which is adapted to emit an output voltage that is proportional to the difference between the currents that are present on the matrix branch and on the reference branch. Figure 15 is a view of the reference system according to the invention, which illustrates a possible embodiment of a differential current amplifier of the latch type 15 that is shown schematically in figure 14. Figure 16 is a view of a possible embodiment of a differential voltage amplifier 9, shown in figure 13. The charts of figures 17, 18, 19, 20, 21, 22, and 23 will be explained during the description of the operation of the reference device according to the invention. Finally, figure 24 shows in detail a possible biasing structure 3, 3' of the dynamic cascode type, which has the advantage of providing a much faster precharging step than the one provided by a constant-type bias BIAS. The cascode structure 3, 3' is described in detail in patent application no. 95830357 in the name of the same Applicant and is assumed included herein as reference. Figure 24 shows, with the reference numeral 3, the cascode structure that can be used in the reference system according to the invention, wherein the reference numeral 20 designates a conventional NOR structure. The cascode structure 3 (or 3') is thus provided by adding appropriate native transistors 21, 22, and 23. The transistor 21 is of the N type, the transistor 22 is of the P type, and the transistor 23 is of the N type. With reference to the above figures, and particularly to the fourth embodiment shown in figure 10, which is the most complete, the operation of the reference system according to the invention is as follows. During the precharging step, the lines PC (PCleft, PCright) are kept at the high logic level, allowing a perfectly balanced precharging for the two branches. In this manner, the transistors 6 and 6' are on and provide equalization of the nodes A and A'. The precharging step ends with the drop to the logic level "0" of the precharging signal PC of the precharging line connected to the matrix line. This event modifies the current paths, altering the initial symmetry of the currents in the two branches, set by the equalization provided by the transistors 6 and 6'; the currents redistribute, complying with various relations that will be described hereinafter. The matrix branch is required to provide part of the current of the reference cell, reducing by the same amount the current that is drawn to the load 1' of the reference side. The symbols adopted to reference the various currents that are present in the reference system according to the invention are now described. Im: matrix current, provided by the sum of the currents that flow in the matrix branch; Ic: cell current, which indicates the current that flows in the memory cell 4; Iv: current of a virgin cell, i.e., the maximum current that can flow in a generic cell that has not yet been programmed, when a full stimulus signal is applied to its gate terminal; Ir: current that flows in the reference cell connected to the reference branch. Assume, for the sake of simplicity, that only the transistors 5 and 5' are activated, without the further activation of the configuration VERIFY, and assume KW as the size of said transistors 5 and 5'. Therefore, the matrix current Im, i.e., the current that must be delivered by the load 1, is the sum of the currents that branch off from the node A to flow in the transistors 2, 5, and optionally 7 if the signal VERIFY is high. In this case, the relation that the matrix current must comply with is the following: Im = Ic(1+K) where Ic is the current that flows in the transistor 2 and KIc is the current that flows in the redistribution transistor or transistors 5 and 7. In the same manner, the current in the reference branch is: Ir = Iv - KIc In the case of figure 10, the reference branch has two paths, each of which is affected by the following current flows: (Iv - KIc)K/(K + 1) in the path that leads to the transistors 5' and 7' (Iv - KIc)/(K + 1) in the path that leads to the transistor 2'. The above relations (1) and (2) apply if there is a so-called linearity condition, in which Ic < 1v/K holds. In other words, the maximum condition is Ic = Iv: the mirroring current in fact cannot exceed the current Iv required by the reference cell. If instead the relation Ic > Iv/K holds, i.e., if a so-called saturation condition occurs (the saturation condition can be viewed as the condition in which full delivery of the current is performed by the matrix side), therefore the following relations hold: Im = Ic + Iv and Ir = 0 From these relations it is possible to deduce the following conditions: (a) if the cell 4 is programmed, then the matrix current Im and therefore the current Ic are zero, i.e., Im, Ic = 0. Then one also has Ir = Iv. If instead the cell 4 is not programmed, i.e., the following relation holds: Im = (1+k) Iv then Ir = (1-K)Iv also holds. (b) finally, there is a case in which the cell 4 is in a balanced condition, in which the currents of the matrix side and of the reference side become equal. In this case one has: Im = Iv/ (1+2K) Ir = Iv/ (1+2K) Im = Ir → Ic(1+K) = Iv - KIc → Ic = Iv(1+K) / (1+2K) (c) since the saturation condition entails that: Ir = 0 KIc = Iv and therefore Ic = Iv/K (d) then, on the basis of the above relations, the value of the current at the loads 1 and 1' in the saturation point is: Im = (1+K)Ic → Im = (1+1/K)Iv Ir = Iv -KIc → Ir = 0 (e) the maximum current vector of the load 1 of the matrix side is: Ic = Iv KIc = Iv Im = Ic + KIc → Im = 2Iv (f) the vector of the current difference at the loads 1 and 1' will be: Im - Ir = (Ic+KIc) - (Iv-KIc) Im - Ir = (1+2K)Ic - Iv (g) finally, the derivative with respect to the cell current Ic of the current difference vector provides the following result: d[Im - Ir]/Ic → d[(1+2K)dIc - Iv]/dIc → d(Im - Ir)/dIc = (1+2K) The last relation leads to the observation that since (1 + 2K) > 1, the variation of the current at the loads is greater than the variation of the current of the cell. Therefore, there is a cell current variation gain effect, introduced by the particular redistribution of the currents of the system. This gain effect can be described and quantified as follows: gain = (1+2K). With reference to the above relations, the values of the equations at two particular values of the parameter K, namely K = 0.5 and K = 1, are now given explicitly. If K = 0.5, only the transistors 5 and 5' are active, whereas if K = 1 (and VERIFY is high), both transistors 5-5' and 7-7' are active. Therefore, if one considers, for the two values of K, the above described cases (a)-(g), one obtains the following table: K = 0.5 K = 1 (a) Ic = 0 Ir = Iv Ic = 0 Ir = Iv (b) Im = Ir = (3/4)Iv Im = Ir = (2/3)Iv (c) unaffected by saturation Ic = Iv (d) unaffected by saturation Im = 2Iv Ir = 0 (e) Im = (3/2)Iv Im = 2Iv (f) -Iv (Ic=0); Iv (Ic=Iv) -Iv (Ic=0); 2Iv (Ic=Iv) (g) gain = 2 gain = 3 It should be noted that in the balanced condition, the matrix current Im is equal to the current of the reference branch; i.e., the cell current Ic is equal to half of the value of the maximum current of a virgin cell (Iv), if one uses a 2:1 ratio, with K = 0.5. With reference to figure 6, for example, the balanced condition with K = 0.5 given by Im = Iv/(1+2K) and Ir = Iv/(1+2K) therefore leads to Im = (3/4)Iv and Ir = (3/4)Iv. The comparison of the reference system according to the invention with a conventional reference system, for example the one shown in figure 7 (2:1 imbalance), can be performed by creating relations similar to those mentioned above. In this case, therefore, every unitary transistor is affected by a maximum matrix current vector given by Ium = 1/2Iv. With reference to said unitary vector, one can write: Ium = Ic (Ic equal to, or smaller than, (1/2)Iv) Iur = (1/2)Iv where Iur is the unitary current vector of the reference. The balanced condition is obtained from the following equality: Ium = Iur Ic = (1/2)Iv Between the matrix branch and the reference branch there is a current difference given by: ¦Ium - 2Iur¦ ¦Ic - 2*(1/2)Iv¦ The maximum current signal conditions are obtained when: The maximum current difference vector is Iv in the case of a programmed cell and is instead (1/2)Iv in the case of a cell with a conductivity greater than, or equal to, (1/2)Iv. In this manner there is no "gain" effect as seen in the reference system according to the invention, since a variation in the cell current equal to (1/2)Iv is matched by an equal variation of the current at the loads. The case of a 3:1 ratio described in figure 3 (similar to the case of K = 1 of the system according to the invention) is now analyzed. Each unitary transistor is affected by a current vector: Ium = 1/3Iv By referring to said unitary vector, one can write: Ium = Ic (Ic smaller than, or equal to, (1/3)Iv) Iur = (1/3)Iv The balanced condition is obtained from the following equality: Ium = Iur from which Ic = (1/3)Iv Between the two branches there is therefore a current difference: ¦Im - Ir¦ ¦Ic - 3*(1/3)Iv¦ The maximum signal conditions are obtained when: The current difference vector is asymmetrical and equal to Iv in the case of a programmed cell and is instead (2/3)Iv in cells with a conductivity that is greater than, or equal to, (1/3)Iv. In this configuration, too, for the same reasons as in the preceding case, there is no current "gain" effect. It is possible to plot charts to compare the characteristics of the two described reference systems so as to visually appreciate their differences. The explanatory charts are those of figures 17-23. The chart of figure 17 plots the curves of the matrix current Im = (1+K)Ic and of the reference current Ir = Iv - KIc. The axes of the chart plot the current Ic on the abscissae and the current at the loads, Iload, on the ordinates. The intersection point of the two curves is the balancing point. The chart of figure 18 instead plots the curve of the current difference vector (Im - Ir) as a function of the cell current Ic. In this case, the balancing point occurs when the cell current cancels out the difference (Im - Ir). The chart of figure 19 plots the curves of the various currents in the reference system according to the invention, illustrated for example in figure 5 for the sake of simplicity. The curve indicated by Im = (1+KIc) is the sum of the two curves referenced by Im(pass) = Ic, i.e., the current that flows through the transistor 2, and Im(unbal) = KIc, i.e., the current that flows through the transistor 5. K = 0.5 is assumed in figure 19. The balancing point is given by the intersection of the curve Ir and of the curve Im. For values to the left of the balancing point, one has a programmed cell 4, whereas for values to the right one has a virgin cell 4. Figure 20 is a chart that is similar to the one shown in figure 19 but applies only to the double symmetrical reference system according to the invention, illustrated in figure 10, when K = 0.5. In this chart, Imat(load) designates the matrix current, Imat(pass) designates the current that flows in the transistor 2, Imat(unbal) indicates the current that flows through the transistor 5, Iref(load) designates the current that flows through the reference branch, Iref(unbal) references the current that flows through the transistor 5', and Iref(pass) indicates the current that passes through the transistor 2'. The chart of figure 21 plots the reference system according to the invention, shown in figure 10, when K = 1. The curves plotted here have the same meaning as those described above, with the addition of the curve Iunbal(total), which represents the total current that flows through the two transistors 5 and 7. Finally, the charts of figures 22 and 23 plot, with the general formula and when K = 0.5, 1, respectively, the variation of the current at the loads with respect to the variation of the cell current. The curve 25 plots the current variation at the loads, whereas the curve 30 plots the current variation at the cell. In the chart of figure 23, the curve 25' plots the current variation at the loads for K = 1 (ratio 3), whereas the curve 25" plots the current variation at the loads for K = 0.5 (ratio 2). In practice, it has been observed that the reference system according to the invention fully achieves the intended aim, since it allows to sense, with much greater certainty than conventional systems, the conductivity value of a memory cell, thus allowing to determine its status (programmed or virgin). This is achieved by virtue of a current imbalance at the loads of the matrix branch and of the reference branch, achieved by virtue of a redistribution of the currents in the region of the transistors that are present on the matrix branch and the reference branch driven by the biasing structures. It should be noted that in the reference system according to the invention, no additional currents have been introduced to provide discrimination of the status of a memory cell, but only currents that are normally present have been used. The current imbalance is provided with a 2:1 or 3:1 ratio, depending on whether only the transistor 5 (5') is active or the transistor 7 (7') is also active. Other ratios are of course also possible, according to the number of transistors 5 and 7 that are added in parallel to the transistor 2. The overall size of these transistors must always be K times that of the transistor 2. In this manner, if there are three transistors in parallel to the transistor 2, the size of each transistor is equal to one third of the size of the transistor 2 and the current KIc that is distributed in the three branches formed by the three transistors in parallel to the branch that contains the transistor 2 is distributed in these three branches. The reference system thus provided is perfectly symmetrical and circuitally balanced, there are no current mirrorings provided far from the memory cell, with consequent propagation problems, and current consumption is reduced. The current imbalance at the loads occurs with a gain of the current at the loads in response co a variation in the current of the memory cell; this makes the reference system according to the invention particularly adapted with current differentials, although it can be used perfectly with voltage differentials as well. The symmetry of the two matrix and reference branches, provided in the second embodiment of the invention, allows to swap the reference branch with the matrix branch without any circuital complication. In this manner, it is possible to sense the status of a memory cell in a memory half-matrix by taking as reference a cell that belongs to the domain of the other half-matrix, and vice versa. Finally, the current difference vector provided by the difference between the matrix current and the reference current is twice that of the above described conventional solutions, when only the transistor 5 (and/or 5') is activated. The reference system thus conceived is susceptible of numerous modifications and variations, all of which are within the scope of the inventive concept. Thus, for example, the biasing structures 3 and 3' shown in the various figures can be replaced with a fixed bias value, designated by BIAS in figures 7 and 8, which respectively show the first embodiment and the second embodiment of the reference system according to the invention. Likewise, a fixed bias BIAS can be applied, as shown in figure 11, to the fourth embodiment shown in figure 10. In the same way, of course, a fixed bias BIAS can also be applied to the third embodiment: this last case is not shown in the figures, since it can be easily deduced from the figures that have already been described. Furthermore, the transistors 2-2', 5-5', 6-6', 7-7', and 8-8', advantageously shown in the various figures as native transistors with a low threshold, can be replaced with high-threshold transistors without altering the inventive concept. Finally, all the details may be replaced with other technically equivalent elements. In practice, the materials employed, so long as they are compatible with the specific use, as well as the dimensions, may be any according to the requirements and the state of the art. Where technical features mentioned in any claim are followed by reference signs, those reference signs have been included for the sole purpose of increasing the intelligibility of the claims and accordingly such reference signs do not have any limiting effect on the interpretation of each element identified by way of example by such reference signs.

Claims: Reference system for determining the programmed/non-programmed status of a memory cell (4), particularly for non-volatile memories, which comprises: a first branch for connecting a first load (1) and a memory cell matrix; a second branch for connecting a second load (1') and at least one virgin reference memory cell (4'); means (YM, YN) for selecting a memory cell of said matrix of memory cells; and means (YM, YN) for selecting said at least one virgin reference cell; each one of said first and second branches having a transistor (2, 2') for enabling the flow of current respectively between said first load and said second load and said memory cell matrix and said at least one reference memory cell; said enabling transistors (2, 2') being controlled, respectively, by a first biasing structure (3) and by a second biasing structure (3'); characterized in that it comprises at least one transistor (5) for redistributing the current of the load on said first branch, which is connected in parallel to said first enabling transistor (2), and a first equalization transistor (6) that is controlled by a precharge signal (PCleft) for the equalization of opposite nodes of said first and second branches, said at least one current redistribution transistor (5) providing a current imbalance in said first (1) and second (1') loads to sense the difference in conductivity between a memory cell (4) of said memory matrix and said at least one reference cell (4'), in order to determine the programmed or non-programmed status of said memory cell (4) of the memory matrix. Reference system according to claim 1, characterized in that said at least one current redistribution transistor (5) has a size that is K times the size of said enabling transistors (2), where K is a positive variable parameter. Reference system according to claim 1, characterized in that said current imbalance at the loads (1, 1'), provided by said at least one current redistribution transistor (5), occurs with a gain of current at said loads in response to a variation in the current of said memory cell (4). Reference system according to claim 1, characterized in that it comprises a first current redistribution transistor (5) and a second current redistribution transistor (7) that have the same size and are in parallel to said current flow enabling transistor of said first branch. Reference system according to claim 4, characterized in that it comprises an additional control transistor (8) that is adapted to control the activation of said second current redistribution transistor of said first branch. Reference system according to claim 4, characterized in that said first and second current redistribution transistors (5, 7) of said first branch have, as a whole, a size that is equal to K times the size of said enabling transistor (2) of said first branch, where K is a variable parameter. Reference system according to claim 1, characterized in that it comprises at least one transistor (5') for redistributing the current of the load of said second branch that is connected in parallel to said enabling transistor (2') of said second branch. Reference system according to claim 7, characterized in that it comprises a second equalization transistor (6') that is controlled by said precharge signal (PCright) for the equalization of opposite nodes of said first and second branches, said second equalization transistor (6') being connected between a bit line of said reference matrix and the first equalization transistor (6), said first and second equalization transistors allowing to swap the reference between the first branch and the second branch. System according to claim 7, characterized in that the size of said redistribution transistor (5') of said second branch is equal to K times the size of the enabling transistor (2') of said second branch, where K is a positive variable parameter. Reference system according to claim 7, characterized in that it comprises a first current redistribution transistor (5') and a second current redistribution transistor (7'), having the same size, in parallel to the enabling transistor (2') of said second branch. Reference system according to claim 10, characterized in that it comprises an additional control transistor (8') that is adapted to control the activation of said second current redistribution transistor (7') of said second branch. Reference system according to claim 10, characterized in that said first current redistribution transistor (5, 5') and said second current redistribution transistor (7, 7') have, on the whole, a size that is K times the size of the enabling transistors (2, 2') of said first and second branches, where K is a positive variable parameter. Reference system according to claim 1, characterized in that said first and second biasing structures (3, 3') comprise a cascode structure each. Reference system according to claim 1, characterized in that said first and second biasing structures (3, 3') comprise a constant bias. Reference system according to claim 1, characterized in that it comprises means (5) that provide a current differential between the currents of said first and second branches. Reference system according to claim 1, characterized in that it comprises means (1, 1') that provide a voltage differential between the voltage values of said first and second branches.

Inventors: PASCUCCI LUIGI, PASCUCCI, LUIGI
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1996
Main classification: G11C16
IPC codes: G11C16