SELF-ALIGNED CONTACT TRENCH DMOS TRANSISTOR STRUCTURE AND METHODS OF FABRICATING SAME

Abstract: A trench DMOS transistor structure includes a contact to the transistor's source and body that is self-aligned to the trench. With a self-aligned contact, the distance from the edge of the source and body contact to the edge of the trench can be minimized. Thus, the distance between the trench edges can be reduced. As a result, the packing density of the transistor is increased dramatically. This gives rise to much improved performance in terms of low m-resistance and higher current drive capability. Alternate process modules are provided for fabricating the self-aligned contact structure.

Description: SELF-ALIGNED CONTACT TRENCH DMOS TRANSISTOR STRUCTURE AND METHODS OF FABRICATING SAME BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to metal oxide semiconductor (MOS) devices and, in particular, to a trench, double diffused MOS (DMOS) transistor structure wherein the contact to the transistor's source and body is self-aligned to the trench. The self-aligned contact reduces the distance between trench edges with a resulting increase in packing density and current driving capability and decrease in on-resistance. Alternate methods of fabricating the self-aligned contact structure are also provided. 2. Discussion of the Relevant Art For power trench DMOS transistors, the on-resistance is minimized if the source and body region can be made the same size as the trench width. While the trench width can be made as small as 1 micron or less with current integrated circuit fabrication technology, the dimension of the source and body region is governed by the size of the source and body contact opening, typically from 2 to 5 microns, and the alignment tolerance, typically larger than 1 micron, from the edge of the contact to the edge of the trench. U.S. Patent No. 5,316,959, issued to Kwan, et al. on May 31, 1994, discloses a trench DMOS transistor which utilizes conventional lithographic technology for fabricating a contact to the source and body of a trench DMOS device. Specifically, the Kwan et al patent discloses a process flow that requires six masking steps for fabricating a trench DMOS device structure. These masking steps include a contact hole masking step in which portions of a boro-phosphosilicate glass (BPSG) layer overlying the trench structure are removed to form contact openings to the p+ regions and to the trench polysilicon. Thus, the Kwan et al approach suffers from the same mask alignment tolerance problems common to the prior art. US. Patent No. 5,171,705, issued to Choy on December 15, 1992, discloses a high density DMOS transistor that utilizes a self-aligned structure in combination with a body contact region which overdopes the source region to minimize the number of required masking steps. The Choy structure uses dielectric spacers to eliminate the need for the contact masking step. While eliminating the contact mask, the Choy technique is not directed to a trench DMOS device. It would be desirable to have available structure and fabrication methods for providing a self-aligned contact trench DMOS transistor. SUMMARY OF THE INVENTION The present invention provides a trench DMOS transistor structure with the contact to the transistor's source and body self-aligned to the trench and alternate methods for fabricating the structure. With a self-aligned contact, the distance from the edge of the source and body contact to the edge of the trench can be minimized to between 0.1 to 0.3 microns using conventional integrated circuit fabrication processes. Therefore, the distance between the trench edges, which is the source and body region, can be reduced. As a result, the packing density of the transistor is increased dramatically. This gives rise to much improved device performance in terms of low on-resistance and higher current driving capability. A better understanding of the features and advantages of the present invention will be obtained by reference to the following detailed description and accompanying drawings which set forth an illustrative embodiment in which the principles of the invention are utilized. BRIEF DESCRIPTION OF THE DRAWINGS Figs. 1A-1F are cross-sectional drawings illustrating the sequential steps of a process for fabricating a self-aligned contact, trench DMOS transistor structure in accordance with the present invention. Figs. 2A-2F are cross-sectional drawings illustrating the sequential steps of an alternate technique for forming oxide spacers in a process for fabricating self-aligned contact, trench DMOS transistor structures in accordance with the present invention. Figs. 3A-3C are cross-sectional drawings illustrating another alternate technique for fabricating self-aligned contact, trench DMOS transistor structures in accordance with the present invention. Figs. 4A-4D are cross-sectional drawings illustrating yet another alternate technique for forming oxide spacers in a process for fabricating self-aligned contact, trench DMOS transistors. DETAILED DESCRIPTION OF THE INVENTION A basic process flow for fabricating an N-channel, self-aligned contact, trench DMOS transistor in accordance with the present invention is described in conjunction with Figs. 1A-1F. First, using a starting material of N- epitaxial silicon 10 on a N+ silicon substrate, a layer of stress relief oxide 12 approximately 500 A thick is thermally grown. A layer of low pressure chemical vapor deposition (LPCVD) nitride 14 approximately 2000 A thick and a layer of plasma enhanced chemical vapor deposition (PECVD) low temperature oxide (LTO) 16 approximately 5000 A thick are then deposited on the stress relief oxide 12, resulting in an oxide-nitride-oxide (ONO) sandwich. The resulting structure is shown in Fig. 1A. Next, in a first masking step (trench mask), trench areas are defined by conventional photolithographic techniques and the underlying ONO is etched to expose surface areas of the N- epi 10 under which the trenches are to be formed. After removal of the photoresist trench mask, the N- epi silicon 10 is etched to define trenches 18. This is followed by the removal of the 5000 A LTO oxide 16, trench cleaning, and sacrificial oxide growth and removal, all in accordance with well-known, conventional fabrication techniques. Gate oxide 20 is then grown on the sidewalls of the trenches 18 followed by deposition of a layer of polysilicon 22 to fill the trenches 18 to provide for the gates of the trench DMOS transistors. The resulting structure is shown in Fig. IB. Next, in a second masking step (poly mask), the polysilicon 22 is doped and the poly mask is used to define the gate fingers or runners connecting the trench gate to the gate pad. The poly etch step delineates these gate fingers and gate runners only, while the polysilicon inside the trenches 18 is self- aligned to the trench edge and planarized to the nitride surface. Then, a polyoxide 24 is thermally grown over the poly gates 22 and the nitride 14 is removed. The resulting structure is shown in Fig. lC. The P-body 26 of the DMOS transistor is then formed by blanket implanting boron and performing a drive-in diffusion. In a third masking step (N+ source mask), a photoresist implant mask is used to define the N+ source region 28 by arsenic or phosphorous implant and subsequent drive-in diffusion. The resulting structure is shown in Fig. ID. Next, oxide spacers 30 are formed to self-align the source and body contacts to the trenches 18. First, PECVD LTO oxide approximately 5000 A thick is deposited and blanket dry-etched to form the oxide spacer 30 defining the separation between the source and body contact to the trench edge. Thus, in accordance with the invention, the source and body contact is self-aligned to the trench edge and no photolithographic masking and aligning are required. A blanket P+ implant of boron and an anneal step are then used to form the P+ body ohmic contact 32. The resulting structure is shown in Fig. IE. Next, a layer of aluminum is deposited to form the top layer metal 34. The resulting structure is shown is shown in Fig. IF. In a fourth masking step (metal mask), a photoresist mask is used to delineate the top layer metal 34 for the source and gate area. A passivation layer, typically nitride or phosphosilicate glass (PSG), is then deposited. In a fifth masking step (pad mask), a photoresist mask is used to delineate the bonding pad areas for the source and gate. An alloy step is then used to improve the metal to silicon contact resistance. The substrate is then thinned down to the required thickness and the backside is metallized to form the backside drain contact. The above process flow employs only five photolithographic masking steps. In situations where the design of the termination area might require thick field oxide, an active mask layer can be added prior to- the trench mask. An alternate process module for forming the oxide spacers 30 is illustrated in Figs. 2A-2F. According to this alternate technique, after deposition of polysilicon 22 as shown in Fig. IB of the above-described process flow, the polysilicon 22 is etched to the surface of the epitaxial layer 10 with the nitride 14 in place. The resulting structure is shown in Fig. 2 A. Next, a PECVD LTO oxide layer approximately 5000 A thick is deposited. The resulting structure is shown in Fig. 2B. The LTO oxide is then etched back to the nitride surface as shown in Fig. 2C. This is followed by a nitride strip utilizing hot phosphoric acid, which will not affect the remaining LTO or the underlying gate oxide. The resulting structure, shown in Fig. 2D, provides a well-defined step height on the LTO for formation of the spacers 30. A second layer of LTO is then deposited, as shown in Fig. 2E, and etched to define the LTO spacers 30, resulting in the structure shown in Fig. 2F. The process then proceeds to completion as described above. In a second alternate process module, no spacers are utilized. Referring to Fig. 3A, the process proceeds in accordance with the just-described alternative module until the structure shown in Fig. 2D is realized. Note that Figs. 3A and 2D are identical. The process then proceeds without the formation of oxide spacers with metal deposition as shown in Fig. 3B, relying on the step height of the etched PECVD LTO to insulate the poly gates 22 from the top layer metal 34. The process then continues to completion as described above. Figs. 4A-4D show an alternate process module for fabricating the self-aligned contact structure. When this module is used, the process begins with the formation of the ONO sandwich, as shown in Fig. 1A. The trench mask is then used to define the trench areas on the upper surface of the N-epi layer 10. The trenches are then etched, lined with oxide and filled with polysilicon, all as described above. Next, however, rather than removing the 5000 A LTO oxide 16, the LTO oxide 16 is left in place during the etchback of the polysilicon gate material 22, thereby providing proper poly step height to insure against undercutting the polysilicon surface to a level lower than that of the surface of nitride layer 14. The LTO oxide 16 (Fig. 4B) and the nitride 14 are then removed, leaving maximized step height for formation of the polyoxide spacers (Fig. 4C). The process then proceeds in the manner described above. Optionally, as shown in Fig. 4D, the contact regions may be suicided prior to formation of the final metal layer to improve the resistivity of the contact. That is, a layer of metal (e.g. Co, T, Ti) suicide can be formed, in accordance with techniques well known in the art, on the surface of the ohmic contact regions prior to deposition of the final aluminum contact layer. The above device structure and various processes use an N- channel device for illustration. Those skilled in the art will appreciate that P-channel devices can also be constructed similarly by adopting the opposite material and dopant types. It should be understood that various alternatives to the embodiments of the invention described herein may be employed in practicing the invention. It is intended that the following claims define the scope of the invention and that methods and structures within the scope of these claims and their equivalents be covered thereby.

Claims: What is claimed is: 1. A trench DMOS transistor structure having a contact to the source and body of the transistor that is self-aligned to the trench, the trench DMOS transistor structure comprising: first and second trenches formed in a layer of epitaxial silicon having a first conductivity type to define an active device region th-srebetween; a layer of silicon dioxide formed over the active device region and to cover the sidewalls and bottom of the first and second trenches; first and second gate polysilicon regions formed over the silicon dioxide in the first and second trenches, respectively; a first region of a second conductivity type opposite to the first conductivity type formed in the active device region to extend between the first and second trenches; first and second spaced-apart source regions of the first conductivity type formed in the first region of the second conductivity type adjacent to the first and second trenches, respectively; a contact region of the second conductivity type formed in the active device region betw-sen the first and source regions; first and second oxide pads formed over the first and second gate polysilicon regions, respectively; first and second oxide spacers formed on the sidewalls of the first and second oxide pads, respectively, to extend over the first and second source regions, respectively; and a conductive layer formed over the oxide pads and the oxide spacers for contact with the contact region. 2. A trench DMOS transistor structure as in claim 1 wherein the first conductivity type is N and the second conductivity type is P. 3. A method of fabricating a trench DMOS transistor structure wherein the contact to the source and body of the transistor is self-aligned to the trench, the method comprising: forming a layer of silicon dioxide on an underlying layer of N-type epitaxial silicon; forming a layer of nitride over the silicon dioxide layer; forming a low temperature oxide (LTO) layer over the nitride layer to define an oxide/nitride/oxide (ONO) sandwich; defining a trench mask over the LTO layer to expose pre-selected surface regions of the LTO layer; etching the ONO sandwich to expose surface regions of the N- epitaxial layer underlying the exposed LTO surface regions; etching the exposed surface regions of the N- epitaxial layer to define trenches in the N- epitaxial layer; removing the LTO layer; forming silicon dioxide on exposed surfaces of the trenches; depositing a layer of polysilicon to fill the trenches; etching the polysilicon layer to define polysilicon gate regions in the trenches; growing a polyoxide pad on the exposed upper surface of each polysilicon gate region; implanting P-dopant in the active device regions to form a region of P-type conductivity between the trenches; defining an N+ source mask and using the N+ source mask mask to introduce N-dopant to define N+ source regions adjacent to the trenches; oxidizing the polyoxide pads to form oxide spacers that extend over the source regions; implanting P-dopant into the active device regions to form a P+ body ohmic contact region between the source regions in the active region; and forming a conductive layer over the oxide pads and the oxide spacers for contact with the ohmic contact region. 4. A method of fabricating a trench DMOS transistor structure wherein the contact to the source and body of the transistor is self-aligned to the trench, the method comprising: forming a layer of silicon dioxide on an underlying layer of N-type epitaxial silicon; forming a layer of nitride over the silicon dioxide layer; forming a low temperature oxide (LTO) layer over the nitride layer to define an oxide\nitride\oxide (ONO) sandwich; defining a trench mask over the LTO layer to expose pre-selected surface regions of the LTO layer; etching the ONO sandwich to expose surface regions of the N- epitaxial layer underlying the exposed LTO surface regions; etching the exposed surface regions of the N- epitaxial layer to define trenches in the N- epitaxial layer; removing the LTO layer; forming silicon dioxide on exposed surfaces of the trenches; depositing a layer of polysilicon to fill the trenches; etching the polysilicon layer to define polysilicon gate regions in the trenches; forming a second LTO layer; etching the second LTO layer to define oxide pads on the upper surface of each polysilicon gate region; implanting P-dopant in the active device regions to form a region of P-type conductivity between the trenches; defining an N+ source mask and using the N+ source mask to introduce N-dopant to define N+ source regions adjacent to the trenches; forming a third LTO layer; etching the third LTO layer to determine oxide spacers on the sidewalls of the oxide pads such that the oxide spacers extend over the source regions; implanting P-dopant into the active device regions to form a P+ body ohmic content region between the source regions in the active region; and forming a conductive layer over the oxide pads and the oxide spacers for contract with the ohmic contact region. 5. A method of fabricating a trench DMOS transistor structure wherein the contact to the source and body of the transistor is self-aligned to the trench, the method comprising: forming a layer of silicon dioxide on an underlying layer of N-type epitaxial silicon; forming a layer of nitride over the silicon dioxide layer; forming a low temperature oxide (LTO) layer over the nitride layer to define an (ONO) sandwich; defining a trench mask over the LTO layer to expose pre-selected surface regions of the LTO layer; etching the ONO sandwich to expose surface regions of the N- epitaxial layer underlying the exposed LTO surface regions; etching the exposed surface regions of the N- epitaxial layer to define trenches in the N- epitaxial layer; removing the LTO layer; forming silicon dioxide on exposed surfaces of the trenches; depositing a layer of polysilicon to fill the trenches; etching the polysilicon layer to define polysilicon gate regions in the trenches; forming a second LTO layer; etching the second LTO layer to define oxide pads on the upper surface of each polysilicon gate region; implanting P-dopant in the active device regions to form a region of P-type conductivity between the trenches; defining an N+ source mask and using the N+ source mask to introduce N-dopant to define N+ source regions adjacent to the trenches; implanting P-dopant into the active device regions to form a P+ body ohmic content region between the source regions in the active region; and forming a conductive layer over the oxide pads and the oxide spacers for contract with the ohmic contact region.

Inventors: BENCUYA IZAK, KWAN SZEHON, BENCUYA, IZAK, KWAN, SZEHON
Applicants: NAT SEMICONDUCTOR CORP, NATIONAL SEMICONDUCTOR CORPORATION
Application year: 1996
Main classification: H01L21
IPC codes: H01L21, H01L29