Nonvolatile memory and method of programming the same

Abstract: A nonvolatile memory cell includes a floating gate (31); a programming region (32) having a first current path to the floating gate (31) for programming by providing charge carriers to the floating gate (31) through the first current path or extracting charge carriers stored in the floating gate (31); and a verification region (34 to 37) having a second current path separated from the first current path, for verifying the charge amount of the floating gate (31) through the second current path.

Description: BACKGROUND OF THE INVENTION Field of the Invention The present invention relates to a nonvolatile memory and a method of programming the nonvolatile memory. Discussion of the Related Art Generally, for nonvolatile semiconductor memory devices for mass storage media such as EEPROM and flash EEPROM, the drawback that is the most difficult to overcome is the high cost-per-bit of the memories. In order to solve such a problem, studies on multibit cell have been recently proposed. The packing density of a conventional nonvolatile memory corresponds in a one to one fashion to the number of memory cells. A multibit cell stores data of over two bits in one memory cell, thus enhancing the density of data on the same chip area without reducing the size of the memory cell. For the multibit cell, more than three threshold voltage levels should be programmed on respective memory cells. For instance, in order to store data of two bits for every cell, the respective cells must be programmed in 2 2 , that is, four, threshold levels. Here, the four threshold levels correspond to logic states 00, 01, 10, and 11, respectively. In the multi-level program, the most critical problem is that the respective threshold voltage levels have a statistical distribution. The distribution value is about 0.5V. As distribution is reduced by precisely adjusting the respective threshold levels, more levels can be programmed, which in turn increases the number of bits for every cell. To reduce the voltage distribution, there exists a method of programming using repeated programming and verification. According to this method, a series of voltage pulses are applied to the cells in order to program the nonvolatile memory cell at intended threshold levels. To verify whether a cell reaches an intended threshold level, a read operation is performed between the respective programming voltage pulses. During verification, when the verified threshold level reaches the intended threshold level, programming stops. For this method of repeated programming and verification, it is hard to reduce the error distribution of the threshold level due to the limited pulse width of a program voltage. In addition, the algorithm of repeated programming and verification is implemented with an additional circuit, which increases the area of peripheral circuits of the chip. Furthermore, the repetitive method prolongs the programming time. In order to solve such a drawback, R. Cernea of SunDisk Co., Ltd. suggested a method of simultaneous programming and verification. Fig. 1A illustrates the symbol and circuit diagram of the nonvolatile memory proposed by Cernea. As shown in Fig. 1A, the nonvolatile memory cell is composed of a control gate 1, floating gate 2, source 3, channel area 4, and drain 5. When voltages sufficient to cause programming are applied to control gate 1 and drain 5, a current flows between drain 5 and source 3. This current is compared to a reference current and when the current reaches a value equal to or smaller than the reference current, a programming completion signal is produced. The above-mentioned procedure is illustrated in Fig. 1B. According to this prior art, verification is automatically performed at the same time as programming, which compensates for the drawbacks of the repetitive method in which programming and verification are repeated in succession. However, in Cernea's method, a program gate for programming is not used separately. Further, this method does not use a structure in which a programming current path and sensing (or verifying) current path are completely separated. For this reason, in Cernea's method, programming and sensing are difficult to optimize individually. The programming current and monitoring current are not separated so that the cell's threshold voltages are difficult to control and adjust directly. Conventionally, however, multi-level programming has been performed in such a manner that the voltages applied to the respective parts of a memory cell are fixed, and reference currents corresponding to the respective levels are varied. In this method, as shown in Fig. 1B, reference currents for detection have no explicit relation with the cell threshold voltages, and are not linear with them. The cell structure of an EEPROM or a flash EEPROM is roughly divided into two parts, depending upon where the floating gate is placed on the channel area. The first structure is a simple-stacked gate structure in which the floating gate completely covers the cell channel area. The second one is a split-channel structure in which the floating gate covers only part of the channel area between the source and drain. In the channel area, a portion where the floating gate is not present is called a transfer transistor, which is introduced to eliminate over-erasure problem. The split-channel cell is undesirably larger than the simple-stacked gate structure. Another classification type of flash EEPROM depends on whether a double polysilicon gate or triple polysilicon gate is used. The double polysilicon gate is usually employed in the simple-stacked structure. The triple polysilicon gate is used in the split-channel cell. The EEPROM or flash EEPROM memory cells are disclosed in detail in United States Patent No. 5,268,318. Conventionally, the third gate in the triple polysilicon gate is an erasing gate used merely for data erasure. In the flash EEPROM, erasure is performed in units of blocks made up of a plurality of cells. Fig. 2A is a diagram of a conventional nonvolatile memory cell having a simple-stacked gate. Fig. 2B is a diagram of a conventional nonvolatile memory cell having a split-channel structure. Figs. 2A and 2B show programming and erasing processes as well as the structure of the conventional nonvolatile memory cells. As shown in Fig. 2A, the conventional stacked gate memory cell includes a control gate 6, a floating gate 7, a source 8, a drain 9, a channel area 10, and an erasing gate 11. As shown in Fig. 2B, the conventional split channel memory cell includes a control gate 13, a floating gate 14, a source 15, a drain 16, a channel area 17, and an erasing gate 18. In Figs. 2A and 2B, erasing gates 11 and 18 are not required for programming. Therefore, during programming, the conventional cells of Figs. 2A and 2B have substantially the same structure as the double polysilicon gate. In the prior art, programming is carried out only with the control gate, source and/or drain electrodes so that it is difficult to separate the program current path and verification (sensing) current path within the memory cell for programming and verification. Accordingly, it is difficult to control the multi-levels directly and effectively. Further, US 5,386,132 discloses a multimedia storage system with a highly compact memory device having non-volatile memory cells each of which comprises a floating gate, a programming region having a program gate for providing charge carriers to the floating gate, and a control gate for controlling the amount of charge carriers provided to the floating gate, and a verification region having a field effect transistor having the floating gate, a source, a drain, and a channel region there between. Thus, the known non-volatile memory cell includes a first current path for programming and second current path for verifying the charge amount of the floating gate. SUMMARY OF THE INVENTION The object underlying the present invention is to provide a non-volatile memory and a method of programming the non-volatile memory, in which verification and programming can be carried out more directly and effectively. This object is achieved by the memory device according to claim 1 and by the method according to claims 47 and 51. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and constitute a part of this specification illustrate embodiments of the invention and, together with the description, serve to explain the objects, advantages, and principles of the invention. In the drawings: Fig. 1A is a circuit diagram of a conventional nonvolatile memory cell; Fig. 1B is a graph for explaining the automatic verification/programming principle of the conventional nonvolatile memory of Fig. 1A; Fig. 2A is a circuit diagram of a conventional nonvolatile memory having a simple-stacked gate; Fig. 2B is a circuit diagram of a conventional nonvolatile memory having a split-channel structure; Fig. 3A is a block diagram of a nonvolatile memory cell of the present invention; Fig. 3B is a circuit diagram of a first embodiment of nonvolatile memory of the present invention; Fig. 4 is a diagram explaining a programming method using current detection according to the first embodiment of the present invention; Figs. 5A-5I are diagrams of waveforms present at the respective nodes of Fig. 4; Fig. 6 is a flowchart of showing double or multi-level programming according to the first embodiment of the present invention; Fig. 7A is an equivalent circuit diagram of the capacitances of the nonvolatile memory of Fig. 3B; Fig. 7B is a graph showing the relationship between the threshold levels to be programmed and the correspondingly applied voltages of the control gate; Fig. 8A is a diagram explaining a programming procedure of the present invention, using voltage detection according to the first embodiment of the present invention; Fig. 8B is a circuit diagram of another embodiment of the voltage detecting portion of Fig. 8A; Fig. 9A is a layout of the first structure of the nonvolatile memory according to the first embodiment of the present invention; Fig. 9B is a cross-sectional view of the first structure of the nonvolatile memory cut along line A-A' of Fig. 9A; Fig. 10A is a layout of the second structure of the nonvolatile memory according to the first embodiment of the present invention; Fig. 10B is a cross-sectional view of the second structure of the nonvolatile memory cut along line B-B' of Fig. 10A; Fig. 11A is a layout of the third structure of the nonvolatile memory according to the first embodiment of the present invention; Fig. 11B is a cross-sectional view of the third structure of the nonvolatile memory cut along line C-C' of Fig. 11A; Fig. 12A is a layout of the fourth structure of the nonvolatile memory according to the first embodiment of the present invention; Fig. 12B is a cross-sectional view of the fourth structure of the nonvolatile memory cut along line D-D' of Fig. 12A; Fig. 13A is a circuit diagram of a nonvolatile memory device using the nonvolatile memory cell of Fig. 3B; Fig. 13B is a table showing voltages supplied to the respective lines of Fig. 13A during operation; Fig. 14 is a circuit diagram of a second embodiment of the nonvolatile memory of the present invention; Fig. 15A is a diagram for explaining a programming method according to the second embodiment of the present invention; Fig. 15B is a diagram of a voltage detector used instead of the current detector of Fig. 15A; Fig. 16A is a layout of one structure of the nonvolatile memory according to the second embodiment of the present invention; Fig. 16B is a cross-sectional view of one structure of the nonvolatile memory cut along line E-E' of Fig. 16A; Fig. 17A is a circuit diagram of a nonvolatile memory device using the nonvolatile memory cell of Fig. 14; and Fig. 17B is a table showing voltages supplied to the respective lines of Fig. 17A during operation. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment Referring to Fig. 3A, a nonvolatile memory cell comprises a floating gate, a programming region, having a first current path to the floating gate, for programming by providing charge carriers to the floating gate through the first current path or extracting charge carriers stored in the floating gate, and a verification region, having a second current path separated from the first current path for verifying the charge amount of the floating gate through the second current path during programming. Turning to Fig. 3B, a nonvolatile memory cell comprises a floating gate 31, a program gate 32 for providing negative charges (electrons) or positive charges (holes) to floating gate 31 for the purpose of double or multi-level programming, a control gate 33 for providing voltage to floating gate 31 by capacitive coupling between the control gate and floating gate and controlling the amount of charges provided to floating gate 31 from program gate 32 for the purpose of programming, and a transistor 34 for verifying (or sensing) charges provided to floating gate 31 during double or multi-level programming. In Fig. 3B, transistor 34 includes floating gate 31, a source 35, a drain 36, and a channel area 37 between source 35 and drain 36. As shown in Fig. 3B, the nonvolatile memory of the present invention is constructed to perform double or multi-level programming, using a third program gate 32, and to verify whether the programming is completed or not by checking the amount of charges supplied to floating gate 31 during the double or multi-level programming. Control gate 33, floating gate 31, and program gate 32 may perform only double or multi-level programming. Conversely, transistor 34 may merely perform monitoring of the amount of charges of floating gate 31 in order to verify whether programming is completed or proceeding. The programming region is separated completely from the verifying region. These two regions are connected through floating gate 31. Floating gate 31 and program gate 32 corresponding to the programming region can be regarded as forming a tunnel diode. Programming is performed by a tunnelling mechanism through the tunnel diode. As discussed above, the prior art does not use program gate 32, and performs both programming and verification through drain 36 and channel area 37 of transistor 34. In that respect, the present invention is distinctive from the prior art. Hereinafter, a double or multi-level programming method using the nonvolatile memory of Figs. 3A and 3B will be described. The programming method of the present invention includes voltage detection and current detection. First, the current detection will be explained. Fig. 4 includes a first voltage source 38, second voltage source 39, third voltage source 40, fourth voltage source 41, current detector 42, and nonvolatile memory 100 such as that shown in Fig. 3. Reference character P S indicates an externally supplied programming start signal. Reference character V ST indicates a programming stop signal. First voltage source 38 supplies a voltage V C,i (i=0, 1, 2,....n-1) to control gate 33 of nonvolatile memory 100 for the purpose of programming an ith threshold level during multi-level programming. Voltage V C,i has values that vary with the respective programming levels. Second voltage source 39 applies a voltage V P to program gate 32 for the double or multi-level programming. Voltage V P always has a fixed negative value. Third voltage source 40 induces a voltage V D to drain 36 in order to monitor the state of programming, that is, drain current I D,i (t), during the double or multi-level programming. Fourth voltage source 41 supplies a voltage V S to source 35. For example, voltage V S may be ground. I D,i (t) indicates the current flowing through drain 36 at time (t). Current detector 42 has a threshold current value Ith, and produces a programming stop signal V ST when current I D,i (t) flowing through drain 36 reaches the threshold current Ith during an ith threshold level programming. In other words, programming stop signal V ST is generated when I D,i (t) ≤ Ith (at t=t tp,i ). Time t p,i refers to the time when the ith threshold programming is completed. Here, threshold current Ith of current detector 42 can be defined by a value near the threshold region of the transistor, which can be greater than or equal to zero. An arbitrary reference current I REF greater than the threshold current can also be used for describing the present invention, resulting in the same conclusion. However, if reference current I REF is large, the initial voltage at floating gate 31 V F , i (0) should be large as well, so as to satisfy I D,i (0) >I REF at the initial stage of the multi-level programming. In addition, in order to increase the initial voltage V F,i (0), voltage V c,i must also be increased. Current I D,i (t) indicates the current value of drain 36 triggered by voltage V F,i (t) at floating gate 31 during the ith level programming. The current value has the largest value at the initial stage of programming, and is reduced as programming proceeds. When the reduced value reaches threshold current Ith of current detector 42, the current detector produces program stop signal V ST . In accordance with the above-stated condition, double or multi-level programming using the detection of drain current will be described with reference to Figs. 4, 5A-5I and 6. Figs. 5A-5I show waveforms at the respective locations of Fig. 4. Fig. 6 is a flowchart illustrating double or multi-level programming of the present invention. Presume that a corresponding cell is in the state of erasure. Here, the state of erasure means level zero, that is, the lowest level. This embodiment is described assuming that the floating gate field effect transistor has an n-type channel formed on a p-type substrate. Of course, a floating gate field effect transistor in which a p-type channel is formed on a n-type substrate can be also employed. In this case, if the applied voltages are set to opposite polarities, and the signs of corresponding voltages and threshold voltages are reversed, the same operations can be performed as in the former case. First, when programming start signal P S is externally applied as shown in Fig. 5A for the purpose of double or multi-level programming, positive voltage V C,i is set for programming the ith level. When programming start signal P S of Fig. 5A is applied, positive voltage V C,i of Fig. 5B and negative voltage V P of Fig. 5C are supplied to control gate 33 and program gate 32, respectively, from first and second voltage sources 38 and 39. Then, tunnelling voltage V tun,i (t) of Fig. 5G is applied between program gate 32 and floating gate 31 so that charges for the ith threshold level programming are supplied to floating gate 31 from program gate 32. After V c,i and V p is applied, current detector 42 is turned-on in order to verify the charge variation at floating gate 31. As shown in Fig. 5D, voltage V F,i (t) for the ith threshold level programming is applied to floating gate 31, and an inversion layer is formed in channel area 37 of field effect transistor 34. Because source 35, drain 36, and channel area 37 are located within a semiconductor substrate, when the inversion layer is formed, currents flow from drain 36 to source 35 through channel area 37. Voltages are supplied from third and fourth voltage sources 40 and 41 so that drain voltage V D and source voltage V S are induced to drain 36 and source 35, respectively. Here, current I D,i (t) flows through drain 36. As shown in Fig. 5E, current I D,i (t) has its largest value at an initial stage, and decreases as programming proceeds because the electrons are injected to the floating gate to reduce the floating gate voltage. During the ith threshold level programming, current detector 42 monitors drain current I D,i (t). When this value reaches threshold current Ith, as shown in Fig. 5E, the ith threshold level programming is completed and programming stop signal V ST is output, as shown in Fig. 5F. Here, it was explained that current detector 42 monitors current I D,i (t) at drain 36. However, it is also possible to say that the current detector 42 monitors the variation of the amount of voltage and charge at floating gate 31 during programming of Fig. 5D. Monitoring of current I D,i (t) can be regarded as monitoring the conductivity of the inversion layer formed in channel area 37. In Fig. 4, programming stop signal V ST is applied to first and second voltage sources 38 and 39. First and/or second voltage sources 38 and 39 stop supplying positive voltage V C,i and negative voltage V P to control gate 33 and program gate 32 in response to programming stop signal V ST , as shown in Figs. 5B and 5C. When current I D,i (t) is detected to become below threshold current Ith at a point where t=t p,i , the ith threshold level programming is completed. Time t p,i indicates when the ith threshold level is programmed. Here, threshold current Ith is previously set as a value substantially corresponding to threshold voltage V F TH at floating gate 31. Threshold voltage V F TH at the floating gate is determined when the nonvolatile memory is fabricated, and can be defined at an arbitrary value of the threshold current Ith. In other words, in Fig. 3, because field effect transistor 34 is formed with floating gate 31, source 35, and drain 36, threshold voltage V F TH substantially corresponds to the threshold voltage of channel area 37. Here, it must be noted that the programming of any threshold level is completed when the floating gate voltage reaches threshold voltage V F TH . This is one feature that distinguishes the present invention from conventional technologies. Fig. 5H is a graph showing threshold voltages V C TH,1 and V C TH,2 at control gate 33, corresponding to the first and second threshold levels, respectively. In Fig. 5H, threshold voltage V C TH,1 at control gate 33 increases as the programming level increases during the multi-level programming. This is performed by increasing voltage V C,i during programming. Here, program times t P,1 and t P,2 of the first and second levels are different because the control gate voltage and threshold voltage shift of the respective levels are different. Meanwhile, Fig. 5I is a graph showing the amount of charge variation at floating gate 31 from the initial charge amount Q F,0 (0) to the charge amount Q F,1 (t P,1 ) when the first threshold level programming is completed and to the charge amount Q F,2 (t P,2 ) when the second threshold level programming is completed, in the case where the ith threshold levels corresponds to the first and second levels. In Fig. 5I, it is noted that when voltages V F,1 (t) and V F,2 (t) at floating gate 31 reach threshold voltage V F TH (t=t P,1 , t=t P,2 ), the charge amount at floating gate 31 is increased from the initial amount Q F,0 (0) to amount Q F,1 (t P,1 ) and to amount Q F,2 (t P,2 ). Referring to Fig. 7A, the relationship between voltage V C,i applied to control gate 32 from first voltage source 38 and the threshold voltage at a corresponding level, which is a significant result of the present invention, will be explained. In Fig. 7A, C C represents the capacitance between control gate 32 and floating gate 31, C P represents the capacitance between program gate 32 and floating gate 31, C D represents the capacitance between drain 36 and floating gate 31, and C S represents the capacitance between source 35 (including the substrate) and floating gate 31. Sum C T of those capacitances can be expressed by the following equation (1): C T = C C + C P + C D + C S The coupling coefficients of the respective capacitances are defined by the following equations (2): α C = C C /C T , α P = C P /C T , and α D = C D /C T In Fig. 7A, voltage at floating gate 31 during programming can be expressed by the following equation (3): V F (t) = α C V C + α P V P + α D V D (t) + Q F (t)/C T = α C [V C -V C TH (t)] + α P V P + α D V D (t) where Q F (t) indicates the charge amount at floating gate 31. In the equation(3), it is assumed that the source and substrate are grounded. In programming, threshold voltage V C TH (t) at control gate 33 is defined by the following equation (4): V C TH (t) = Q F (t) C c In other words, in equation (4), V C TH (t) indicates a threshold voltage shift measured at control gate 33 at time t. The threshold voltage shift refers to a threshold voltage measured at the control gate and caused by the charges accumulated at the floating gate. Threshold voltage V C TH (t) measured at control gate 33 is defined as the voltage of control gate 33 when drain current I D (t) reaches threshold current Ith of current detector 42. Threshold current Ith can be defined arbitrarily as mentioned above. For instance, Ith can equal 1 µ A. Threshold voltage V F TH at floating gate 31 is an inherent threshold voltage of the field effect transistor consisting of floating gate 31, source 35, and drain 36 of Fig. 3, which is determined by manufacturing conditions such as channel ion implantation and the thickness of a gate insulator in fabricating nonvolatile memory 100 of Fig. 3. Therefore, threshold voltage V F TH of floating gate 31 is always constant. Threshold voltage V C TH of control gate 33 is determined by the amount of charge Q F at floating gate 31. As described above, programming at respective levels is stopped when voltage V F (t) at floating gate 31 is decreased until threshold voltage V F TH is reached. This time point corresponds to when current I D (t) of drain 36 reaches threshold current Ith and time t P when programming is completed. During the respective threshold level programmings, voltage V F (t P ) of floating gate 31 when programming is finished can be expressed by the following equation (5): V F (t P ) = V F TH = α C [V C - V C TH (t P )] + α P V P + α D V D (t P ) To rearrange equation (5) according to voltage V C applied to control gate 33 from first voltage source 38, the following equation (6) is given: V C =V C TH (t P ) + V F TH - α P V P - α D V D (t P ) α C =V C TH (t P ) + V 1 where V 1 is defined: V 1 = V F TH - α P V P -α D V D (t P ) α C Here, it is important that value V 1 , when detection time point t= t P , is a constant with respect to control gate voltage V C,i at the respective levels. Value V 1 is determined by drain voltage V D (t P ) when t = t P , voltage V P applied to program gate 32, and parameters such as V F TH , α C , α D and α P which are determined during the manufacturing process. The circuit can be constructed so that drain voltage V D becomes a constant value. Values α D and V D are relatively very small with respect to the other two terms. In the respective threshold level programming, V D (t P ) at the completion of programming (when t = t P ) is constant. Using equation (6), voltage V C,i of control gate 33 required for the ith threshold level programming can be expressed as the following equation (7): V C,i = V C TH,i + V 1 where i = 0, 1, 2, 3, ..., n-1. From this equation, it is found that threshold levels to be programmed and correspondingly applied control gate voltages are linear with a slope of 1. Fig. 7B shows this result. Here, likewise, according to equation (4), the charge amount of the floating gate is linear with the control gate voltages. Because value V 1 is constant as mentioned above, the ith shift ΔV C,i of the voltage applied to control gate 33 during the multi-level programming can be given as the following equation (8) : ΔV C,i = ΔV C TH.i From equations (7) and (8), when shift ΔV C TH,i from the state of erasure (i.e., the lowest level) to one of the respective threshold levels is determined during the double or multi-level programming, a corresponding level programming can be performed by applying to the control gate a voltage corresponding to the intended threshold level shift ΔV C TH,i added to the already known value V C,0 of the lowest level programming, and then waiting for the automatic completion of programming. As shown in Fig. 5G, during the respective level programming, tunnelling voltage V tun,i applied between floating gate 31 and program gate 32 for tunnelling is largest initially and smallest at a time point when voltage V F,i (t) reaches a given threshold voltage V F TH at floating gate 31, that is, when programming is completed. The maximum V max tun,i of the tunnelling voltage can be given as the following equation (9) by the difference between initial voltage V F,i (0) of floating gate 31 and voltage V P applied to program gate 32: V max tun,i =V F ,i(0) - V P (actually negative value) =α C V C ,i+(α p -1)V P +α D V D (0)+ Q F (0) C T In equation (9), if the initial charge amount Q F (0) of floating gate 31 is zero, equation (9) can be re-defined as the following equation (10): V max tun,i = α C V C,i + (α P - 1) V P + α D V D (0) Hereinbefore, multi-level programming has been described. An erasing process using the nonvolatile memory of Fig. 3 will be explained below. The erasing process is very simple to describe. Erasure is performed in such a manner that voltages are applied to the respective parts to form, between the floating gate and source, drain, or channel area, electric fields strong enough to erase charge carriers accumulated at the floating gate. By doing so, the charge carriers are erased to the source, drain, or channel area through tunnelling. In the present invention, the erased state means the lowest threshold level, that is, V C TH,0 . In other words, all the nonvolatile memory cells within a given erasure block are programmed at the lowest level. Erasure is performed according to the following steps. First, threshold levels of the overall cells of a selected block are erased to become below level zero, that is, V C TH,0 . Sequentially, with the level zero in which the voltage of control gate 33 is V C,0 , the overall selected cells are programmed. Here, value V C,0 can be fixed arbitrarily. Erasure is performed substantially according to the programming method, thereby eliminating over-erasure problem. Finally, the requirements of voltage V C,i of control gate 33 and voltage V P of program gate 32 necessary for the ith threshold level programming are as follows. In order to monitor the charge variation of the floating gate during programming, voltage V C,i must be applied so that at the initial stage of programming, the channel of transistor shown in Fig. 4 is inverted to make the drain current flow, and during the programming, the conductivity of the inversion layer is reduced. For this purpose, the following equation (11) must be satisfied. V F,i (0) > V F TH , I D,i (0) > Ith Values V C,i and V P must be determined so that a tunnel electric field formed between program gate 32 and floating gate 31 to create tunnelling therebetween is strong enough for programming. Value V P is a fixed negative value so that the strength of the tunnel electric field increases as value V C,i becomes high. The speed of programming also increases as threshold voltage shift ΔV C TH of control gate 33 becomes large. Thus, a programming method in accordance with current detection has been described. Hereinafter, a programming method in accordance with voltage detection will be explained with reference to Fig. 8. The programming method in accordance with voltage detection is substantially the same as the programming in accordance with current detection. Fig. 8 is a diagram for explaining the programming of the present invention using voltage detection. Fig. 8 is substantially the same as Fig. 4, aside from voltage detector 43 used instead of current detector 42 of Fig. 4. Voltage detector 43 can be made with a reference voltage source 44 and a resistor 45 connected between reference voltage source 44 and drain 36. The resistor 45 may be replace by a diode to form the voltage detector 43. This is the most simple configuration. Voltage detector 43 monitors the voltage of drain 36 during programming. During monitoring, when voltage V F,i of floating gate 31 reaches a threshold voltage V F TH , and if drain voltage V D,TH is detected, then a programming stop signal V ST is output. Value V D,TH is constant with respect to the overall programming level. Like the current detection method, programming is completed when, in response to programming stop signal V ST , first and/or second voltage sources 38 and 39 cut off control gate voltage V C,i and program gate voltage V P . Other parts are also substantially the same as the current detection, and their description will be omitted. Referring to Figs. 9A and 9B, a first structure of a nonvolatile memory of the present invention comprises a first conductivity-type semiconductor substrate 50 having a channel area on its surface, floating gate 51 formed on the channel area, control gate 52 formed above floating gate 51, program gate 53 formed adjacent to floating gate 51, and an insulating layer 54 formed between program gate 53, floating gate 51, and control gate 52. The insulating layer 54 is sufficiently thin between floating gate 51 and program gate 53 to enable tunnelling therebetween. Referring to Figs. 9A and 9B again, a field insulating layer 55 is formed on the surface of substrate 50 surrounding the channel area. Part of floating gate 51 extends to the surface of field insulating layer 55. In Fig. 9B, program gate 53 is placed adjacent to one side of control gate 52. A gate insulating layer 56 is formed sufficiently thin to enable tunnelling between the channel area and floating gate 51. Turning to Figs. 10A and 10B, a second structure of the present invention is similar to that of the first structure. In this embodiment, part of program gate 53 is placed adjacent to the bottom of floating gate 51. Referring to Figs. 11A and 11B, a third structure of the present invention again is similar to that of the first structure. In this third embodiment, program gate 53 is placed adjacent to the top of floating gate 51. Referring to Figs. 12A and 12B, a fourth structure of nonvolatile memory of the present invention comprises a first conductivity-type semiconductor substrate 50 having a channel area on its surface, floating gate 51 formed on the channel area, two second conductivity-type impurity areas 57 and 58 formed on either side of the channel area within the surface of the semiconductor substrate, control gate 52 formed above floating gate 51, program gate 53 formed adjacent to floating gate 51, and an insulating layer 54 formed between program gate 53, floating gate 51, and control gate 52. The insulating layer 54 is sufficiently thin between floating gate 51 and program gate 53 to enable tunnelling therebetween. A field insulating layer 55 surrounds the channel region. A gate insulating film 56 is formed sufficiently thin to enable tunnelling between the channel area and the floating gate 51. Referring to Fig. 13A, the nonvolatile memory device of the present invention comprises a semiconductor substrate 60, a plurality of word lines 61 spaced apart by a predetermined distance on substrate 60, a plurality of bit lines 62 perpendicular to the word lines to form a plurality of squares or rectangles spaced apart by a predetermined distance, a plurality of program lines 63 disposed in the same direction as the respective bit lines, and a plurality of nonvolatile memory cells 64 disposed in each of the respective squares or rectangles. In Fig. 13A, as shown in Fig. 3, nonvolatile memory cells 64 each comprise a floating gate 65, program gate 66 for supplying charges to floating gate 65 for the purpose of programming, control gate 67 for controlling the amount of charges supplied to floating gate 65 for the purpose of programming, and field effect transistor 68 for reading (or verifying) the amount of charge carriers supplied to floating gate 65 during programming. Field effect transistor 68 is composed of floating gate 65, source 69, drain 70, and channel area 71 between source 69 and drain 70. Control gate 67 of the respective memory cells is connected to nearby word line 61 and program gate 66 is connected to nearby program line 63. Source 69 of nonvolatile memory cell 64 is commonly connected to nearby bit line 62 along with drain 70 of nonvolatile memory cell 64 placed in a nearby or adjacent square. As shown in Fig. 13B, when the nonvolatile memory device operates in a program mode, - 8- - 15V is applied to a selected program line 63, 0V to unselected program lines 63, 3-12V to a selected word line 61, 0- - 10V to unselected word lines 61, 0.5-2V to a selected bit line 62, 0V to unselected bit lines 62 placed to the left, for example, of a selected cell, 0.5-2V to more than one bit line placed to the right, for example, of the selected cell, and 0V to substrate 60. When the nonvolatile memory device operates in the erase mode, there are two ways to apply voltages. First, to erase through bit lines 62, 0- - 12V is applied to the overall program lines 63 of a selected erasure block, - 7- - 12V to the overall word lines 61 of the selected erasure block, 0-6V to the overall bit lines 61 of the selected erasure block, and 0V to substrate 60. To erase through substrate 60, 0- - 12V is applied to the overall program lines 63 of a selected erasure block, - 7- - 12V to the overall word lines 61 of the selected erasure block. Bit lines 62 of the selected block are floated. 0-6V is applied to substrate 60. When the nonvolatile memory device operates in a read mode, 0V is applied to program lines 63, Power supply voltage Vcc to a selected word line 61, 0V to unselected word lines 61, 0.5-2V to a selected bit line 62, 0V to unselected bit lines 62 placed to the left, for example, 0.5-2V to bit lines 62 placed right, for example, of the selected cell, and 0V to substrate 60. The voltages of Fig. 13B can be varied with structural characteristics or electrical parameters of the memory cells, for instance, the coupling coefficient or the thickness of tunnel insulator. Second Embodiment Hereinafter, there will be described the second embodiment of nonvolatile memory cell and device of the present invention, and a method of programming, with reference to Figs. 14, 15A, 15B, 16A, 16B, 17A, and 17B. Referring to Fig. 14, the nonvolatile memory comprises a floating gate 81 divided into a first area 81a and a second area 81b; a programming field effect transistor including first area 81a of floating gate 81, first drain 82, and common source 83, channel region between the first drain 82 and the common source 83 and having a first threshold voltage V F TH1 for supplying charge carriers to floating gate 81 for the purpose of programming; a control gate 84 for providing voltage to floating gate by capacitive coupling between floating gate and control gate and controlling the amount of charge carriers supplied to floating gate 81 for programming; and a monitoring field effect transistor including second area 81b of floating gate 81 (excluding first area 81a), second drain 85, and common source 83, channel region between the second drain 85 and the common source 83 and having a second threshold voltage V F TH2 for verifying the amount of charge carriers supplied to floating gate 81 during programming. In the circuit of Fig. 14, second threshold voltage V F TH2 must be greater than first threshold voltage V F TH1 . As shown in Fig. 14, unlike the first embodiment, the second embodiment of nonvolatile memory cell of the present invention does not have a program gate, and instead has three impurity areas (the drain of the monitoring transistor, common source, and the drain of the programming transistor) on the surface of the substrate. Besides the components of Fig. 14, the memory of Fig. 15A further comprises a first voltage source 88 for supplying a voltage to control gate 84, a second voltage source 89 for supplying a voltage V P D to first drain 82 of the programming field effect transistor for programming, a third voltage source 90 for supplying to common source 83 a voltage V S lower than or equal to voltage V P D supplied to first drain 82, and a current detector 91A for detecting current I D,i (t) flowing through second drain 85 of the monitoring field effect transistor during programming and supplying programming stop signal V ST to respective voltage sources 88, 89 and 90 when the detected current reaches a set threshold current Ith to cut off voltages V C,i , V P D , and V S . In Fig. 15A, common source 83 is grounded with the substrate (not shown). In Fig. 15A, voltage V C,i supplied to control gate 84 from first voltage source 88 is a positive voltage varying in correspondence with the respective threshold level programming of the multi-level programming. Voltage V P D supplied to the programming field effect transistor from second voltage source 89 is a positive voltage. Current detector 91A of Fig. 15A can be replaced with voltage detector 91B of Fig. 15B. Referring to Fig. 15B, besides the components of Fig. 14, the nonvolatile memory cell further comprises a first voltage source 88 for supplying a voltage V C,i to control gate 84, a second voltage source 89 for supplying a voltage V P D to first drain 82 of the programming field effect transistor for programming, a third voltage source 90 for supplying to common source 83 a voltage V S lower than or equal to voltage V P D supplied to first drain 82, and a voltage detector 91B for monitoring voltage V M D,i (t) during programming and supplying programming stop signal V ST to the first and second voltage sources 88 and 89 when the monitored voltage V M D,i (t) of second drain 85 reaches a set reference voltage V D,TH to cut off voltages V C,i and V P D . Even when voltage detector 91B of Fig. 15B is used instead of current detector 91A of Fig. 15A, voltage V C,i supplied to control gate 84 from first voltage source 88 is a positive voltage varying in correspondence with the respective threshold level programming of the multi-level programming. Voltage V P D supplied to first drain 82 of the programming field effect transistor from second voltage source 89 is a positive voltage in case of programming using hot carrier injection mechanism. As shown in Fig. 15B, voltage detector 91B can be configured with a voltage source V DD for inducing a voltage at second drain 85, and a resistor connected between voltage source V DD and second drain 85 of the monitoring field effect transistor. Voltage V P is set to be less than or equal to zero (≤0) and is supplied to the program gate of the first embodiment shown in Figs. 3B and 4. However, the cell of the second embodiment shown in Figs. 15A and 15B uses a programming field effect transistor instead of the program gate. In a nonvolatile memory cell comprising a control gate 84, a floating gate divided into first and second areas 81a and 81b, a programming field effect transistor having a first threshold voltage V F TH1 and including first area 81a of floating gate 81, first drain 82, common source 83, and a first channel area 86 located between first drain 82 and common source 83, and a monitoring field effect transistor having a second threshold voltage V F TH2 and including second area 81b of floating gate 81, second drain 85, common source 83, and a second channel area 87 placed between second drain 85 and common source 83, a method of programming the second embodiment of the nonvolatile memory cell of the present invention includes the steps of: supplying first voltage V C,i to control gate 84 and second voltage V P D to first drain 82 so that charge carriers are fed to floating gate 81 through first channel area 86 for programming and an inversion layer is formed in second channel area 87; and monitoring the conductivity of the inversion layer during programming and cutting off the supply of first voltage V C,i to control gate 84 and/or second voltage V P D to first drain 82 when the monitored conductivity reaches a reference value. In Figs. 14, 15A and 15B, supplying charge carriers to floating gate 81 from first channel area 86 for programming can be performed through hot carrier injection or Fowler-Norheim (FN) tunnelling. In case of programming using the tunnelling mechanism, the voltage applied to the first drain is less than or equal to zero, and the voltage applied to the common source is equal to that or the first drain. Referring to Figs. 16A and 16B, the nonvolatile memory cell comprises a first conductivity-type (P type) semiconductor substrate 92, a second conductivity-type (n+) first impurity area 93, second impurity area 94, and third impurity area 95 sequentially formed on the surface of substrate 92 while spaced apart by a predetermined distance, a first gate insulating layer 98 formed over first and second impurity areas 93 and 94 on substrate 92, a second gate insulating layer 99 formed over second impurity area 94 and third impurity area 95 and having a different thickness from that of first gate insulating layer 98, a first channel area 100 defined as a region between first and second impurity areas 93 and 94 on the surface of substrate 92, a second channel area 101 defined as a region between second and third impurity areas 94 and 95 on the surface of substrate 92, a floating gate 96 formed over first and third impurity areas 93 and 95 on first and second gate insulating layers 98 and 99, a control gate 97 formed above floating gate 96, and an insulating layer 102 formed to insulate floating gate 96 from control gate 97. Here, as shown in Fig. 16B, second gate insulating layer 99 is thicker than first gate insulating layer 98. First gate insulating layer 98 is determined to be sufficiently thin so that charge carriers are erased to first channel area 100 from floating gate 96 through tunnelling. While not described in detail in Figs. 16A and 16B, a field insulating layer 103 is further formed on the surface of substrate 92 excluding first gate insulating layer 98 and second gate insulating layer 99. In Figs. 16A and 16B, floating gate 96 is formed over first and second channel areas 100 and 101. Part of floating gate 96 extends to the surface of field insulating layer 103. Referring to Fig. 17A, the nonvolatile memory device of the present invention comprises a plurality of word lines 104 disposed to be spaced apart by a predetermined distance, a plurality of second conductivity-type bit lines 105 disposed to be perpendicular to word lines 104 to form a plurality of squares or rectangles spaced apart by a predetermined distance, common source lines 106 formed to divide the respective squares or rectangles in the same direction as bit lines 105 into the left and right areas between bit lines 105, and a plurality of nonvolatile memory cells having a control gate 84, a floating gate 81 divided into, first and second areas 81a and 81b, a programming field effect transistor placed to the right of the squares, for example, and for supplying charge carriers to floating gate 81 for programming, and a monitoring field effect transistor placed to the left of the squares, for example, and for verifying the amount of charge carriers of floating gate 81 during programming. The programming field effect transistor includes first area 81a of floating gate 81, a first drain 82, and common source 83, and a first channel area 86 placed between first drain 82 and common source 83. The monitoring field effect transistor includes second area 81b of floating gate 81, a second drain 85, and common source 83, and a second channel area 87 placed between second drain 85 and common source 83. The control gate 84 is connected to nearby word line 104, and the common source 83 is connected to common source line 106. The first drain 82 is connected to nearby bit line 105 together with second drain 85 of the nonvolatile memory located in a square to the right of the first drain, for example, and the second drain 85 is connected to first drain 82 of the nonvolatile memory located in a square to the left of the second drain 85, for example. When the nonvolatile memory device of Fig. 17A operates in the program mode using the hot carrier injection mechanism. As shown in Fig. 17B, 6-13V can be applied to a selected word line, 0V to unselected word line, 5-9V to a selected n th bit line, 0.5-2V to a selected (n-1) th bit lines, 0V to other bit lines, 0V to a selected n th source line, an unselected (n+1) th source line is floated, an unselected (n-1) th source line is equal to a selected (n-1) th bit line, and 0V to the substrate. When the nonvolatile memory device operates in a program mode using tunneling mechanism, 10-20V is applied to a selected word line, 0V to an unselected word line, 0V to a selected n th bit line, 5-10V to other bit lines, 0V to a selected n th source line, 5-10V to other source lines, and 0V to substrate. When the nonvolatile memory device of Fig. 17A operates in the erasure mode, -7 to -12V can be applied to a selected word line and an unselected word line, all bit lines are floated, Vcc is applied to all source lines, and 0V to the substrate. When the nonvolatile memory device of Fig. 17A operates in the read mode, Vcc can be applied to a selected word line, 0V to an unselected word line, 0.5 to 2V to a selected n th bit line, 0V to other bit lines, 0V to all source lines, and 0V to the substrate. The voltages of Fig. 17B can be varied with structural characteristics or electrical parameters of the memory cells, for instance, the coupling coefficient or the thickness of tunnel insulator. As described above, the present invention is advantageous in the following respects. First, respective threshold level programming is accomplished merely by changing the voltage of the control gate thereby, facilitating multi-level programming. Second, the respective threshold voltage levels and corresponding control gate voltages are linear, and the shift of the threshold voltage coincides with the shift of the control gate voltage, precisely adjusting the shift of the respective level threshold voltages. Third, the state of erasure is controlled by the lowest level programming at an arbitrary control gate voltage, thereby eliminating over-erasure problem. Fourth, programming and verifying are performed simultaneously in the nonvolatile memory cell itself, requiring no separate circuit for verifying programmed contents and making the speed of programming faster. Fifth, pre-programming is not necessary prior to erasure. Sixth, a small voltage below ±12V is required for operation. Seventh, only a small current below several or tens of µ A is merely required for verification. Eighth, the nonvolatile memory cell is constructed as a simple-stacked gate, not a split-channel, making it compact. Ninth, the accuracy of multi-level programming, that is, the error distribution of programmed threshold voltages is precisely determined only by parameters fixed at the time of fabrication of the nonvolatile memory and by applied bias voltages. For this reason, the error distribution of the respective levels of the nonvolatile memory of the present invention is not dependent on the large number of program/erase cycles. Even during programming, the memory is not dependent on the trap of charges to the oxide layer, channel mobility, bit line resistance, and unstable or unpredictable electric elements. Tenth, the programming method of the nonvolatile memory of the present invention is voltage-controlled, performing easier and more precise multi-level programming than the currentcontrolled method. Eleventh, the nonvolatile memory device of the present invention accomplishes a contactless virtual ground array with a simple stacked-gate structure not an asymmetric cell like the split-channel structure, sharply reducing the size of chip. Twelfth, the source and drain of the nonvolatile memory of the present invention are used only in reading, applying a low voltage required only for reading to the source and drain. This optimizes the diffusion area of the source and drain. The foregoing description of preferred embodiment(s) of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and modifications and variations are possible in light of the above teachings or may be acquired from practice of the invention. The embodiments were chosen and described in order to explain the principles of the invention and its practical application to enable one skilled in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto, and their equivalents.

Claims: A memory device having at least one nonvolatile memory cell comprising: a floating gate (31; 81); a programming region having a program gate (32) for providing charge carriers to said floating gate (31) for the purpose of programming; and a control gate (33) for controlling the amount of charge carriers provided to said floating gate (31) for programming; so as to provide a first current path to said floating gate (31; 81) for programming by providing charge carriers to said floating gate (31; 81) through said first current path or extracting charge carriers stored in said floating gate (31; 81); and a verification region, having a field effect transistor (34) comprising -- said floating gate (31), -- a source (35), -- a drain (36), and -- a channel region (37) between said source (35) and said drain (36), so as to provide a second current path separated from said first current path, for verifying the charge amount of said floating gate (31; 81) through said second path; characterized in that the first current path is controlled by voltages applied to said program gate (32) and said control gate (33); the second current path is controlled by voltages applied to said source (35) and drain (36), such that the programming process and the verifying process can be carried out simultaneously. The memory device as claimed in claim 1, wherein said programming region includes a tunneling diode formed by said floating gate (31) and said program gate (32). The memory device as claimed in claim 1, wherein means are provided for verifying the charge amount of said floating gate (31; 81) through the second path during programming. The memory device as claimed in claim 1, further comprising: a first voltage source (38) for supplying a voltage to said control gate (33); a second voltage source (39) for supplying a voltage to said program gate (32); a third voltage source (40) for supplying a voltage to said drain (36); a fourth voltage source (41) for supplying to said source a voltage lower than the voltage supplied to said drain (36), and a current detector (42) for detecting the current of said drain (36) during programming and supplying a programming stop signal to one of said first and second voltage sources (38, 39) when the detected drain current reaches a set reference current so that at least one of said voltages therefrom is cut off. The memory device as claimed in claim 4, wherein the set reference current is the threshold current of the field effect transistor. The memory device as claimed in claim 4 or 5, wherein said voltage supplied from said fourth voltage source (41) to said source (35) is a ground voltage. The memory device as claimed in claim 4, 5, or 6, wherein said voltage supplied to said control gate (33) from said first voltage source (38) is a positive value varying in correspondence with a respective threshold level programming of a multi-level programming, and said voltage supplied to said program gate (32) from said second voltage source (39) is a fixed value below zero. The memory device as claimed in claim 1, further comprising: a first voltage source (38) for supplying a voltage to said control gate (33); a second voltage source (39) for supplying a voltage to said program gate (32); and a voltage detector (43) for monitoring a voltage of said drain (36) during programming and supplying a programming stop signal to one of said first and second voltage sources (38, 39) when the detected drain voltage reaches a reference voltage so that at least one of said voltages from said first and second voltage sources (38, 39) is cut off. The memory device as claimed in claim 8, wherein the reference voltage is the threshold voltage of the field effect transistor. The memory device as claimed in claim 8 or 9, wherein said voltage supplied to said control gate (33) from said first voltage source (38) is a positive value varying in correspondence with a respective threshold level programming of a multi-level programming, and said voltage supplied to said program gate (32) from said second voltage source (39) is a fixed value below zero. The memory device as claimed in claim 8, 9 or 10, wherein said voltage detector (43) comprises a voltage source (44) for inducing a voltage at said drain (36), and a resistor (45A) connected between said voltage source (44) and said drain (36). The memory device as claimed in claim 8, 9 or 10, wherein said voltage detector (43) comprises a voltage source (44) for inducing a voltage at said drain (36), and a diode (45B) connected between said voltage source (44) and said drain (36). The memory device as claimed in one of the claims 1 to 12, wherein the floating gate (51) is formed on a channel region located in the surface of a first conductivity-type semiconductor substrate (50), said semiconductor substrate (50) comprising: two impurity regions of a second conductivity type formed on either side of said channel region within its surface; said control gate (52) is formed above said floating gate (51); said program gate (53) is formed adjacent to said floating gate (51) for supplying charge carriers to said floating gate (51) during programming; and an insulating layer (54) is formed between said program gate (53), said floating gate (51) and said control gate (52), said insulating layer (54) being sufficiently thin between said floating gate (51) and said program gate (53) to enable tunnelling therebetween. The memory device as claimed in claim 13, further comprising a field insulating layer (55) formed on a surface of said substrate (50) surrounding said channel region. The memory device as claimed in claim 14 or 15 wherein a portion of said floating gate (51) extends to a surface of said field insulating layer (55). The memory device as claimed in one of the claims 13 to 15, wherein said program gate (53) is formed adjacent to a side of said floating gate (51). The memory device as claimed in one of the claims 14 to 16, wherein said program gate (53) is formed above said floating gate (51). The memory device as claimed in one of the claims 14 to 16, wherein said program gate (53) is formed adjacent to a bottom portion of said floating gate (51). The memory device as claimed in one of the claims 13 to 18, further comprising a gate insulating layer (56) formed between said channel region and said floating gate (51), and which is sufficiently thin to enable tunnelling therebetween. The memory device as claimed in one of the claims 1 to 19, further comprising: a plurality of word lines (61) spaced apart by a predetermined distance; a plurality of bit lines (62) of a second conductivity-type formed perpendicular to said word lines (61) and spaced apart by a predetermined distance to form a plurality of rectangles; a plurality of program lines (63) disposed parallel to the respective bit lines (62); and a plurality of said nonvolatile memory cells, each disposed in a respective rectangle, from which memory cells each program gate (66) is connected to one of said plurality of program lines (63) for supplying charge carriers to said floating gate (65) for the purpose of programming; each control gate (67) is connected to one of said plurality of word lines (61) for controlling the amount of charge carriers supplied to said floating gate (65) for the purpose of programming; and each source being connected to one of said plurality of bit lines (62) together with a drain of a nonvolatile memory cell located in a rectangle adjacent said source, and each drain being connected to one of said plurality of bit lines (62) together with a source of a nonvolatile memory cell located in a rectangle adjacent said drain. The memory device as claimed in claim 20, wherein, when said nonvolatile memory device operates in a program mode, -8 to -15V is applied to a selected program line (63), 0V to an unselected program line (63) 3 to 12V to a selected word line (61), 0 to -10V to an unselected word line (61), 0.5 to 2V to a selected bit line (62), 0V to unselected bit lines (62) located on a first side of a selected cell, 0.5 to 2V to more than one bit lines (62) located on a second side of the selected cell opposite said first side, and 0V to substrate (60). The memory device as claimed in claim 20, wherein when said nonvolatile memory device operates in an erase mode through said bit lines (62), 0 to -12V is applied to selected program lines (63), -7 to -12V to selected word lines (61), 0 to 6V to selected bit lines (62) and 0V to said substrate (60). The memory device as claimed in claim 20, wherein when said nonvolatile memory device operates in an erase mode through said substrate (60), 0 to -12V is applied to selected program lines (63), and -7 to -12V to a selected word line (61), selected bit lines (62) are floated, and 0 to -6V is applied to said substrate (60). The memory device as claimed in claim 20, wherein, when said nonvolatile memory device operates in a read mode, 0V is applied to program lines (63), 1 to 6V to a selected word line (61), 0V to unselected word lines (61), 0.5 to 2V to a selected bit line (62), 0V to unselected bit lines (62) located on a first side of a selected cell, 0.5 to 2V to more than one bit lines (62) located on a second side of the selected cell opposite said first side, and 0V to substrate (60). The memory device as claimed in claim 1, wherein said programming region includes a first field effect transistor and said verification region includes a second field effect transistor. The memory device as claimed in claim 25, wherein the floating gate (81) is divided into first and second regions (81a, 81b); said first field effect transistor is a programming field effect transistor including said first region(81a) of said floating gate (81), a first drain (82), a common source (83) and a first channel region (86) disposed between the first drain (82) and the common source (83), and having a first threshold voltage for supplying charge carriers to said floating gate (81) for the purpose of programming; a control gate (84) is provided for controlling the amount of charge carriers supplied to said floating gate (81) for programming; and said second field effect transistor is a monitoring field effect transistor including said second region (81b) of said floating gate (81), a second drain (85), said common source (83), and a second channel region (87) disposed between the second drain (85) and the common source (83), and having a second threshold voltage for verifying the amount of charge carriers supplied to said floating gate (81). The memory device as claimed in clailm 26, wherein said second threshold voltage is greater than said first threshold voltage. The memory device as claimed in claim 26 or 27, further comprising: a first voltage source (88) for supplying a voltage to said control gate (84); a second voltage source (89) for supplying a voltage to the first drain (82) of said programming field effect transistor for programming; a third voltage source (90) for supplying to said common source (83) a voltage less than or equal to said voltage supplied to said first drain (82); and a current detector (91A) for detecting a current flowing through the second drain (85) of said monitoring field effect transistor during programming and supplying a programming stop signal to said first, second and third voltage sources (88, 89, 90) when the detected current reaches a set reference current so that said voltages supplied from said first, second and third voltage sources (88, 89, 90) are cut off. The memory device as claimed in claim 28, wherein the set reference current is the threshold current of the monitoring field effect transistor. The memory device as claimed in claim 28 or 29, wherein said common source (83) is grounded. The memory device as claimed in claim 28, 29 or 30, wherein said voltage supplied to said control gate (84) from said first voltage source (88) is a positive value varying in correspondence with a respective threshold level programming of a multi-level programming, and said voltage supplied to said programming field effect transistor from said second voltage source (89) is a positive value. The memory device as claimed in claim 28, 29 or 30, wherein said voltage supplied to said control gate (84) from said first voltage source (88) is a positive value varying in correspondence with a respective threshold level programming of a multi-level programming, and said voltage supplied to said programming field effect transistor from said second voltage source (89) is a value that is less than or equal to zero. The memory device as claimed in claim 26 or 27, further comprising: a first voltage source (88) for supplying a voltage to said control gate (84); a second voltage source (89) for supplying a voltage to the first drain (82) of the programming field effect transistor for programming; a third voltage source (90) for supplying to said common source (83) a voltage lower than or equal to said voltage supplied to said first drain (82); and a voltage detector (91B) for monitoring a voltage of the second drain (85) during programming and for supplying a programming stop signal to said first and second voltage sources (88, 89) when the monitored voltage of said second drain (85) reaches a set reference voltage so that said voltages from said first and second voltage sources (88, 89) are cut off. The memory device as claimed in claim 33, wherein said voltage supplied to said control gate (84) from said first voltage source (88) is a positive value varying in correspondence with a respective threshold level programming of a multi-level programming, and said voltage supplied to the first drain (82) of said programming field effect transistor from said second voltage source (89) is a positive value. The memory device as claimed in claim 33, wherein said voltage supplied to said control gate (84) from said first voltage source (88) is a positive value varying in correspondence with a respective threshold level programming of a multi-level programming, and said voltage supplied to the first drain (82) of said programming field effect transistor from said second voltage source (89) is a value that is less than or equal to zero. The memory device as claimed in claim 33, 34 or 35, wherein said voltage detector (91B) comprises a voltage source for inducing a voltage at said second drain (85), and a resistor connected between said voltage source and said second drain (85) of said monitoring field effect transistor. The memory device as claimed in one of the claims 26 to 36, comprising: a first conductivity-type semiconductor substrate (92); a first impurity region (93), a second impurity region (94), and a third impurity region (95) formed on the surface of said substrate (92) and spaced apart by a predetermined distance, each of said first impurity region(93), said second impurity region (94), and said third impurity region (95) being of a second conductivity-type; a first gate insulating layer (98) formed over said first and second impurity regions (93, 94) on said substrate (92); and a second gate insulating layer (99) formed over said second and third impurity regions (94, 95) and having a different thickness from that of said first gate insulating layer (98); wherein said first channel region(100) is defined as a region between said first and second impurity regions (93, 94) on the surface of said substrate (92); said second channel region (101) is defined as a region between said second and third impurity regions (94, 95) on the surface of said substrate (92); said floating gate (96) is formed over said first to third impurity regions (93 to 95) on said first and second gate insulating layers (98, 99); said control gate (97) is formed over said floating gate (96); and wherein an insulating layer (102) is formed between said floating gate (96) and said control gate (97). The memory device as claimed in claim 37, wherein said second gate insulating layer (99) is thicker than said first gate insulating layer (98). The memory device as claimed in claim 37, wherein said first gate insulating layer (98) is sufficiently thin to enable tunnelling for programming and erasure. The memory device as claimed in claim 37, wherein a field insulating layer (103) is further formed on the surface of said substrate (92) surrounding said first and second gate insulating layer (98, 99). The memory device as claimed in claim 40, wherein a part of said floating gate (96) extends to the surface of said field insulating layer (103). The memory device as claimed in one of the claims 26 to 41, further comprising: a plurality of word lines (104) spaced apart by a predetermined distance; a plurality of second conductivity-type bit lines (105) disposed perpendicular to said word lines (104) and spaced apart by a predetermined distance to form a plurality of rectangles; common source lines (106) formed to divide the respective rectangles in the same direction as said bit lines (105) into first and second regions between said bit lines (105); and a plurality of said nonvolatile memory cells, each of which having the floating gate (81) located in the first and second regions, the control gate (84) connected to one of said plurality of word lines (104), the programming field effect transistor located on a first side of the rectangles and the monitoring field effect transistor located on a second side of the rectangles opposite said first side; said programming field effect transistor and said monitoring field effect transistor of each rectangle are connected with its common source (83) to one of said common source lines (106); said first drain (82) being connected to one of said plurality of bit lines (105) together with a second drain of a nonvolatile memory cell located in a rectangle adjacent said first drain; and said second drain (85) being connected to a first drain of the nonvolatile memory cell located in a rectangle adjacent said second drain. The memory device as claimed in claim 42, wherein, when said nonvolatile memory device operates in a program mode using hot carrier injection mechanism, 6 to 13V is applied to a selected word line (104), 0V to an unselected word line (104), 5 to 9V to a selected n th bit line (105), 0.5 - 2V to a selected (n-1) th bit line (105), 0V to other bit lines (105), 0V to a selected n th source line (106), an unselected (n+1) th source line (106) is floated, an unselected (n-1) th source line (106) is equal to a selected (n-1) th bit line and 0V to substrate. The memory device as claimed in claim 42, wherein, when said nonvolatile memory device operates in a program mode using tunnelling mechanism, 10 - 20V is applied to a selected word line (104), 0V to an unselected word line (104), 0V to a selected n th bit line (105), 5 - 10V to other bit lines (105), 0V to a selected n th source line (106), 5-10V to other source lines (106), and 0V to substrate. The memory device as claimed in claim 42, wherein, when said nonvolatile memory device operates in an erase mode, -7 to -12V is applied to a selected word line (104) and an unselected word line (104), all bit lines (105) are floated, Vcc is applied to all source lines (106), and 0V is applied to said substrate. The memory device as claimed in claim 42, wherein, when said nonvolatile memory device operates in a read mode, Vcc is applied to a selected word line (104), 0V is applied to an unselected word line (104), 0.5 to 2V is applied to a selected n th bit line (105), 0V is applied to other bit lines (105), 0V is applied to all source lines (106), and 0V is applied to said substrate. A method of programming in a memory device a non-volatile memory cell comprising a control gate (33), a floating gate (31), a program gate (32) and a transistor (34) having a threshold voltage and including said floating gate (31), a source (35), a drain (36) and a channel region (37) between said drain (36) and said source (35); comprising the steps of: supplying a first voltage to said control gate (33) and a second voltage to said program gate (32) to control a first current path so that charge carriers for programming are fed to said floating gate (31) from said program gate (32) and an inversion layer is formed in said channel region (37); and monitoring the conductivity of said inversion layer through a second current path separated from said first current path and controlled by voltages applied to said source (35) and drain (36), and stopping the supply of at least one of said first voltage to said control gate (33) and said second voltage to said program gate (32) when the monitored conductivity reaches a reference value. The method as claimed in claim 47, wherein the reference value is the threshold value of the transistor. The method as claimed in claim 47 or 48, wherein said first voltage is a positive value varying in correspondence with a respective threshold level programming of a multi-level programming, and said second voltage is a fixed negative value. The method as claimed in claim 47, 48 or 49, wherein the conductivity of said inversion layer is monitored during programming. A method of programming in a memory device a non-volatile memory cell comprising a control gate (84); a floating gate (81) divided in two first and second regions (81a; 81b); a programming field effect transistor including said first region (81a) of said floating gate (81), first drain (82), a common source (83), and a first channel region (86) between said first drain (82) and said common source (83), and having a first threshold voltage; and a monitoring field effect transistor including said second region (81b) of said floating gate (81), a second drain (85), a common source (83), and a second channel region (87) between said second drain (85) and said common source (83), and having a second threshold voltage, comprising the steps of: supplying a first voltage to said control gate (81) and a second voltage to said first drain (82) to control a first current path so that charge carriers for programming are fed to said floating gate (81) through said first channel region (86) for programming and an inversion layer is formed in said second channel region (87); and monitoring the conductivity of said inversion layer in said second channel region (87) through a second current path separated from said first current path and controlled by voltages applied to said common source (83) and said second drain (85), and stopping the supply of at least one of said first voltage to said control gate (84) and said second voltage to said first drain (82) when the monitored conductivity reaches a reference value. The method as claimed in claim 51, wherein the reference value is the threshold value of the monitoring field effect transistor. The method as claimed in claim 51 or 52, wherein said step of supplying charge carriers to said floating gate (81) from said first channel region (86) for programming is performed through one of hot carrier injection and Fowler-Nordheim tunnelling. The method as claimed in claim 51, 52 or 53, wherein said first voltage is a positive value varying in correspondence with a respective threshold level programming of a multi-level programming, and said second voltage is a positive value. The method as claimed in claim 51, 52 or 53, wherein said first voltage is a positive value varying in correspondence with a respective threshold level programming of a multi-level programming, and said second voltage is a value that is less than or equal to zero. The method as claimed in one of the claims 51 to 55, wherein the conductivity of said inversion layer in said second channel region (87) is monitored during programming.

Inventors: CHOI WOONG-LIM, CHOI, WOONG-LIM
Applicants: LG SEMICON CO LTD, LG SEMICON CO., LTD.
Application year: 1996
Main classification: G11C16
IPC codes: G11C17, G11C11, G11C16, H01L27, H01L29, H01L21