Method for detecting and correcting transmission errors of a digital signal

Abstract: A method of detecting and correcting errors that occurs while digital signals are transmitted in series. In this method, in a processing unit of a transmitter, n addresses (ad) are allocated to respective n digital signals. Using these addresses (ad), bits of the digital signals are picked out, a plurality of bit strings (g) are created by combining information bits and check bits of the selected bits, and the plurality of bit strings (g) thus created are subjected to parity checks to determine the value of the check bits of the digital signals. A transmission code (1) thus created are transmitted to a receiver. In the processing unit of the receiver, the plurality of bit strings (g) are created from the signal received. The plurality of bit strings (g) thus created are subjected to parity checks to detect and correct errors in the transmission code (1).

Description: This invention relates to a method for detecting transmission errors that may occur during serial transmission of digital signals and correcting the detected transmission errors. Binary digital signals transmitted through a transmission line suffer bit reversal at a certain rate that depends upon the characteristics of the transmission line. In order to detect and correct transmission errors due to bit reversal, redundant characters or check bits are added to information bits that represent information to be transmitted. A hamming code V shown in Fig. 38 has its respective characters spaced a predetermined distance not less than three (hamming distance) from adjacent ones. If there is an error in one bit or character, such an error can be easily detected because in such a case, the hamming distance between the bit in error and the original bit changes from zero to one and the hamming distance between the bit in error and any adjacent bit changes from three to two. Specifically, in the transmitter (see Fig. 38A), data a (k = 1, 2 ...) and redundant bits c 1 (1 = 1, 2 ...) are mixed together using a coding matrix B to create e.g. a hamming code "c 1 c 2 a 1 c 3 a 2 a 3 ". Upon receiving the hamming code, the receiver checks it by multiplying the code by a check matrix M as shown in Fig. 38B. If an error E=[1000000] occurs during transmission, results of check operations will be (100) as shown in Fig. 38C. Thus, it is possible to detect and specify the bit in error. Fig. 38D show the results of operations on bits in error. One problem with such a hamming code is that such a code needs a relatively large number of redundant bits c k (in the above example, the ratio of information bits to the entire transmission bits is 4/7 = 57.2%), and thus the transmission efficiency is low. Also, in this arrangement, only one error can be detected and corrected at one time. That is, if errors occur in two bits, it is impossible to detect and correct such errors. Now therefore, it is the object of this invention to provide a method for detecting multiple transmission errors with high reliability while maintaining high transmission efficiency. In order achieve the object, there is provided, according to this invention, a method for detecting errors in transmission of n (in number) digital signals which are a mixture of k (in number) information bits (a k ) and n-k check bits (c (n-k) ), the method comprising, in a processing unit of a transmitter: attaching n addresses (ad) which are h-digit numbers expressed in a number system having integer q as its base (n = q h ) to the respective n digital signals, allocating the check bits (c (n-k) ) to respective addresses (ad) each including h-r (1 ≦ r ≦ h) integers q-1 or 0's, and allocating the information bits (a k ) to the remaining ones of the addresses, selecting h-r digits from the h digits of each of the addresses (ad) without duplication, creating h C h-r · q h-r bit strings (g) each comprising q r bits having the same integers for the selected h-r digits, determining the value of the check bits (c (n-k) ) in each bit string (g) to which the largest address (ad) is attached by subjecting the respective bit strings (g) to parity checks, thus producing a transmission code (1), and in a processing unit of a receiver: attaching n addresses (ad) which are h-digit numbers expressed in a number system having integer q as its base ( n = q h ) to the respective n digital signals of the transmission code (1) received from the transmitter, selecting h-r digits from the h digits of each of the addresses (ad) without duplication, creating h C h-r ·q h-r bit strings (g) each comprising q r bits having the same integers for the selected h-r digits, and detecting errors in transmission by subjecting the respective bit strings (g) to parity checks. In this method, in the transmitter, n addresses (ad) which are h-digit numbers expressed in a number system having integer q as its base are attached to the respective n digital signals. Check bits (c (n-k) ) are allocated to respective addresses (ad) each including h-r (1 ≦ r ≦ h) integers q-1 or 0's, information bits (a k ) are allocated to the remaining ones of the addresses. Transmission data are allocated to the information bits (a k ). h-r digits are selected from the h digits of each of the addresses (ad) without duplication to create h C h-r ·q h-r bit strings (g) each comprising q r bits having the same integers for the selected h-r digits. Each bit includes at least one address corresponding to a check bit (c (n-k) ). The q r-1 bits corresponding to the remaining addresses (ad) may be all information bits (a k ), a mixture of information bits (a k ) and check bits (c (n-k) ), or all check bits (c (n-k) ). In any case, it is possible to select a check bit (c (n-k) ) corresponding to the largest one of the selected q r addresses (ad), and thus to determine the value of the check bits (c (n-k) ) in each bit string (g) to which the largest address (ad) is attached by subjecting the q r bits to even parity checks. This process is carried out for all the h C h-r · q h-r bit strings (g) to create the transmission code (1). In the receiver, addresses (ad) are attached to the transmission code (1) received, h C h-r · q h-r bit strings (g) are created, and the bit strings (g) thus created are subjected to parity checks, in the same manner as in the transmitter. Any transmission error in the code can be easily detected, because such error appears in the form of parity break during parity checks. (Claim 1) All or part of the h digits of each address (ad) may be expressed in different number systems having different integers as their bases. With this arrangement, it is possible to handle any number of signals without increasing the number of digits of each address (ad). (Claim 2) In order to achieve the second object in a different way, this invention provides a method for correcting errors in transmission of n (in number) digital signals which are a mixture of k (in number) information bits (a k ) and n-k check bits (c (n-k) ), the method comprising, the steps carried out in the processing unit of the transmitter in the above-described manner, and in a processing unit of a receiver: attaching n addresses (ad) which are h-digit numbers expressed in a number system having integer q as its base ( n = q h ) to the respective n digital signals of the transmission code (1) received from the transmitter, selecting h-r digits from the h digits of each of the addresses (ad) without duplication, creating a group (G) of check formulas for each of the h C h-r combinations of h-r bits, the check formulas in each group (G) being all the possible combinations of the integers of the selected h-r digits, creating q h-r bit strings (g) for each group (G), each of the bit strings comprising q r bits to which are attached addresses (ad) having the same integers at the selected h-r digits, allocating each check formula to a respective bit string (g), wherein only the h-r digits of the each check formula used to select the respective bit string (g) are effective digits and the remaining digits are indefinite, and correcting any bit in error by repeatedly subjecting the bit strings (g) to parity checks to calculate any parity break, collecting r+1 bit strings (g) in which parity break has been detected for each check formula group (G) and subjecting the thus collected r+1 bit strings to logic operations to find out the address of any bit in error. In this arrangement, h-r digits are selected from the h digits of each of the addresses (ad) without duplication to create a group (G) of check formulas for each of the h C h-r combinations of h-r digits, the check formulas in each group (G) being all the possible combinations of the integers of the selected h-r digits. Check formulas in different groups (G) has no common digits. The bit strings (g) to which the respective check formulas are allocated include address information. Thus, by carrying out logic operations on the components of the check formulas attached to bit strings (g) in which parity break is found for each check formula group (G), it is possible to detect bits in error. The logic operations are carried out by collecting r+1 check formula groups (G), so that the maximum number of operations will be PCr+1 q (h-r)(r+1 ) (where P = h C h-r ). It is thus possible to reduce the number of operations. (Claim 3) The logic operations may be carried out for check formulas based on correction equations (Hn) for calculating effective digit components by performing logic operations between the check formula groups (G). With this arrangement, logic operations for check formulas are carried out based on correction equations (Hn) that makes the digit components of addresses (ad) effective, so that it is possible to reduce unnecessary operations. That is, it is possible to combine digits of addresses (ad) by subjecting the components of the check formula groups (G) to logic operations. The number of such combinations will be h C h-r-1 ·q (h-r)(r+1) . It is thus possible to considerably reduce the number of operations. (Claim 4) Only logic operations that give effective results may be carried out between the check formulas. With this arrangement, it is possible to reduce the number of operations ( h C h-r-1 ·q h ) and thus to reduce the cost, increase the processing speed and reduce the size of the device and energy consumption. (Claim 5) The step of correcting transmission errors may be repeated N times. In this arrangement, even if there are many transmission errors and a long time is needed to correct these errors, the error correction process is terminated and a request for retransmission is issued when the error correction process has been repeated N times. It is thus possible to keep high transmission efficiency. (Claim 6) The step of correcting transmission errors may be carried out by comparing the operation results calculated from the check formulas and pointed to an identical address (ad) with a predetermined number A. In this arrangement, for any address (ad) to which A or more operation results are pointed, error corrections are made unlimitedly. For example, if all the operation results are pointed to a certain address, the bit at this address is almost 100% in error. Thus, by carrying out error corrections only for addresses to which A (1 ≦ A ≦ h C h-r-1 ) or more operation results are pointed, it is possible to freely determine the reliability of error corrections. For addresses to which less than A operation results are pointed, no error corrections are made to improve error correction capacity. (Claim 7) A predetermined number L of bits may be corrected at one time. The value L may be equal to or smaller than q h-r-1 . L bits counted downward from the maximum number ( h C h-r-1 ) of the numbers of logic operations that are pointed to a single address (ad) are corrected. It is thus possible to freely determine the reliability of correction. No unreliable corrections are made, so that it is possible to improve error correction capacity with high efficiency. (Claim 8) All or part of the h digits of each address (ad) may be expressed in different number systems having different integers as their bases. With this arrangement, it is possible to process any number of signals without increasing the digits of each address (ad). (Claim 9) In another arrangement, a plurality of bits are be combined into a transmission signal (1) in the processing unit of the transmitter and are transmitted to the receiver in a serial order, and the processing unit of the receiver separates the bits of the signal received, creates the original transmission signal (1) from the separated bits, and corrects any error present in the transmission signal (1) thus created. With this arrangement, it is possible to eliminate any burst errors that may occur during transmission by separating bits of the signal received. The transmission capacity thus improves. Fig. 1 is a schematic view of the transmission cede according to this invention. Fig. 2 is a schematic view of the memory according to this invention. Fig. 3 is a flowchart showing a first embodiment of this invention. Fig. 4 is a schematic view illustrating the transmission code of the first embodiment of this invention. Fig. 5 is a schematic view of the transmission code of the first embodiment of this invention. Fig. 6 is a view illustrating the encoding method of the first embodiment of this invention. Fig. 7 is a view illustrating the encoding method of the first embodiment of this invention. Fig. 8 is a view illustrating the detecting method of the first embodiment of this invention. Fig. 9 is a flowchart showing the detecting method of the first embodiment of this invention. Fig. 10 is a view illustrating the detecting method of the first embodiment of this invention. Fig. 11 is a view illustrating the detecting method of the first embodiment of this invention. Fig. 12 is a view of another embodiment of the transmission code of this invention. Fig. 13 is a flowchart showing a second embodiment of this invention. Fig. 14 is a view illustrating the correcting method of the second embodiment of this invention. Fig. 15 is a view illustrating the correcting method of the second embodiment of this invention. Fig. 16 is a view illustrating the correcting method of the second embodiment of this invention. Fig. 17 is a view illustrating the correcting method of the second embodiment of this invention. Fig. 18 is a view illustrating the correcting method of the second embodiment of this invention. Fig. 19 is a view illustrating the correcting method of the second embodiment of this invention. Fig. 20 is a view illustrating the correcting method of the second embodiment of this invention. Fig. 21 is a view illustrating the correcting method of the second embodiment of this invention. Fig. 22 is a view illustrating the correcting method of the second embodiment of this invention. Fig. 23 is a table showing solutions for correction equations of the second embodiment of this invention. Fig. 24 is a table showing solutions for correction equations of the second embodiment of this invention. Fig. 25 is a table showing solutions for correction equations of the second embodiment of this invention. Fig. 26 is a table showing solutions for correction equations of the second embodiment of this invention. Fig. 27 is a table showing solutions for correction equations of the second embodiment of this invention. Fig. 28 is a flowchart showing a modified embodiment of the second embodiment of this invention. Fig. 29 is a view of a third embodiment of this invention. Fig. 30 is a table showing solutions for correction equations of the second embodiment. Fig. 31 is a table showing solutions for correction equations of the second embodiment. Fig. 32 is a table showing solutions for correction equations of the second embodiment. Fig. 33 is a table showing solutions for correction equations of the second embodiment. Fig. 34 is a table showing solutions for correction equations of the second embodiment. Fig. 35 is a table showing solutions for correction equations of the second embodiment. Fig. 36 is a table showing solutions for correction equations of the second embodiment. Fig. 37 is a table showing solutions for correction equations of the second embodiment. Fig. 38 shows a conventional arrangement. Fig. 1 shows a data block according to the present invention. The data block comprises a row of n bits. Of the n bits, k bits are information bits a k (k = 1, 2, ... k), and the remaining n-k bits are check bits c (n-k) . The information bits a k and check bits c (n-k) are mixed together to form a transmission code 1. The transmission code 1 is created by a processor, such as a computer or a dedicated LSI, of a transmitter, and sent to a processor of a receiver. For this purpose, bit columns g are generated in a working area of a memory 2 in the processor of the transmitter, as shown in Fig. 2. The bit columns g are subjected to a parity check to produce (encode) check bits c (n-k) . The transmission code 1 thus created is sent to the receiver. The processor of the receiver detects and corrects any error in the transmission code 1 transmitted from the transmitter by creating bit columns g based on the information bits a k and check bits c (n-k) of the transmission code 1. The method of detecting and correcting transmission errors according to the invention is now described step by step with reference to the flowchart of Fig. 3. The transmission code 1 shown has a length n of 32 bits, of which 16 bits are information bits ak. In the processor of the transmitter, upon start of the process (Step 100), a working space corresponding to the length n of the transmission code 1 is created in the memory 2. Data are allocated to each of the n bits of the transmission code 1 (110). Addresses ad are attached to the respective n bits of the transmission code 1. The addresses ad are h-figure numbers represented by a number system having integer q as its base and different from one another. That is, the addresses ad, which are h-figure numbers represented by a number system having q as its base, are allocated to the respective n bits, which are numbered by decimal notation, and comprise information bits a k and check bits c (n-k) , based on the following formula: Bn =  (Nn) =  (Mg · Eg) where Thus, there is a one-to-one relationship between Nn, which represents the addresses ad, and M g ·E g . That is, the relationship between Nn and M g E g is given by the formula: Nn = Mg · Eg By determining the number represented by the number system having q as its base, E g will be constant. Thus, there is the following relationship between Bn and M g : Nn = π(Mg) which leads to: Bn = (Nn) = [π(Mg)] = [π(Mg)] Thus, Bn and M g can be combined in a one-to-one relation to each other. Each row of M g serves as an address ad for each bit. In the above formulas, Bn is a vector having as its components n bits numbered by decimal notation; Nn is a vector having as its components decimal numbers 0 - n which are attached to the respective components of BN; M g is a matrix having h columns by q h rows; E g is a vector having as its components q 0 - q h-1 ;  is a function that establishes a one-to-one relation between the components of Bn and Nn; π is a function that establishes a one-to-one relation between the components of Nn and M g ; and M g ·E gg is the product of the matrix and the vector. In this embodiment, the addresses ad are binaries (q = 2), and there are 32 (n = 2 5 ) bits counted in decimal notation. Thus, the binary addresses ad are attached to the 32 bits as shown in Fig. 4. That is, if the transmission data are (1010101010101010), the first bit is given the address (00000), the second bit is given the address (00001), and then (00010), ..... (11111), as shown in Fig. 5. Data are allocated to the respective bits, which correspond to q h addresses, using r (1 ≦ r ≦ h) digit determined by Formula (3). Since the addresses ad are binaries (q = 2) in this embodiment, the information bits a k are allocated to all the bits to which are attached addresses ad each including h-r or more integers 1's (maximum number q-1 or 2-1) or 0's. In this embodiment, transmission data are allocated to 16 bits to which are attached addressees ad including three or more 0's. (1) or (0) is allocated to each of the remaining bits, i.e. the check bits C (n-k) . (1) or (0) is allocated to each of the check bits C (n-k) , using the addresses ad attached to the bits that represent transmission data 1. That is, address codes ad are used to create bit strings g, which are all the possible combinations of information bits a k and check bits c (n-k) in the manner shown by Formula (3). where k is the number of information bits, n-k is the number of check bits, n is the number of transmission bits, and r is an arbitrarily determined number of figures. Then, h-r of the h figures of the addresses ad are selected without duplication, and the bits to which are attached addresses ad whose components of the selected h-r figures are the same are selected as bit strings g, the number of such bit strings g being h c h-r · q h-r (step 120). In this embodiment, the number h-r being 2, all the rows g of bits which are the same in integers of the two selected figures of their addresses ad are selected, as shown in Fig. 6. In such bit strings g are included those to which are attached addresses ad whose two right figures are (00) and (01), respectively. All the possible bit strings g are shown in Fig. 7. That is, each column of the characters * indicate a bit string whose addresses are the same in the integers of the two selected figures. In this embodiment, there are 10 ( 5 C 2 ) combinations in which two figures are selected from the five figures of the addresses ad. Of any combination, integers 1 and 0 can be combined in 4 (2 2 ) different ways. In Fig. 7, the 10 combinations or check formula groups are represented by G 1 - G 10 , each being subdivided into four bit strings g. Each bit string g in each check formula group G includes at least one address ad corresponding to a check bit c (n-k) . The bits in the bit string g corresponding to the remaining addresses ad (q r -1 in number) may consist essentially of information bits a k , may be a combination of information bits a k and check bits c (n-k) , or may consist essentially of check bits c (n-k) . In any case, one check bit c (n-k) corresponding to the largest address of the q r addresses ad in the bit string g can be selected. Then, the value of the check bits c (n-k) is determined by subjecting the q r bits to parity check as shown by Formula (4). (Step. 130) c (n-k) =a1+ a2 + ·· (mod. 2) If two or more check bits c (n-k) are included in each bit string g, the bit having the larger address ad is changed. When one check formula groups G has been processed in the above manner (Step 140), the other groups G are processed one after another. This process is repeated until all the check formula groups G are processed (Step 150.) In these processes, the same check bits c (n-k) will be selected many times. Their values are renewed every time they are selected. The values of some check bits c (n-k) may be changed by repeated parity checks. But by the time all the groups G are processed, the parity of the check bits c (n-k) will have been determined without contradiction. When all the groups G have been processed, the transmission code 1 is read from the memory 2 (Step 160). The whole process thus ends (Step 170). In this embodiment, the encoded transmission code 1 is represented b (2 h , k) h-r to clarify the fact that h-r of the h figures of each address are invalid. When such transmission code 1 is received by the receiver, its processing unit carries out the steps in the transmitter in the reverse direction to create bit strings g and subject the bit strings to parity checks to detect any transmission error, as shown by flowchart of Fig. 9. Specifically, when the receiver receives the transmission code 1, its processing unit is activated (Step 200). The transmission code 1 is temporarily stored in the memory 2 with addresses ad attached (Step 210). Then, as shown in Fig. 10, the same bit strings g created in the transmitter are created using the same addresses used in the transmitter (Step 215). The respective bit strings g thus created are subjected to parity checks (Step 220). The results are written in the memory 2. When all the bits g in one check formula group G have been processed (Step 230), the other check formula groups G are processed one after another (Step 250). When all the groups G have been processed, judgment is made whether of not there is a parity break based on the previous parity checks (Step 270). If there is a parity break, which indicates the existence of transmission errors, the receiver sends a request for retransmission to the transmitter (Step 355). If no parity break is found, information bits a k are separated and outputted (Step 290) and the receiver is deactivated (Step 300). Suppose now the four bits represented by the addresses (01011), (01100), (01111) and (10000) suffer bit reversals simultaneously as shown in Fig. 11. Although the number of 1's in the entire transmission code 1 remains unchanged, parity breaks will be observed in a plurality of bit strings g as shown in Fig. 11. Thus, it is possible to detect transmission errors. In this embodiment, in order to detect transmission errors, a plurality of bit strings g are created by combining information bits a k and check bits C (n-k) and the bit strings g thus created are subjected to parity checks. With this arrangement, it is possible to detect even bursting errors in which four bits, two of them being in succession, suffer bit reversals simultaneously. In this embodiment, all the h figures of the addresses ad are expressed by binary codes. But instead, all or part of the h figures of the addresses ad may be expressed in different number systems based on different bases. For example, as shown in Fig. 12, the respective figures are expressed in number systems based on 5, 4, 3 and 2, respectively. With this arrangement, it is possible to change the length n of the transmission code 1 without changing the number of figures of the addresses. In this embodiment, the addresses ad are allocated to the respective bits so as to increase from the first bit al to the last bit ak. But they may be attached to the respective bits so as to increase from the last bit a k to the first bit al. In the latter case, contrary to the abovementioned arrangement, the information bits a k are allocated to the addresses ad having 1's by a predetermined number or less, and the value of the check bit c (n-k) to which the smallest address ad is attached is changed for each bit string g based on parity. Other processes are carried out in the same way as above. Their description is thus omitted. Description is now made of the second embodiment of the method for detecting errors in transmission of digital signals. In this method, the steps carried out in the processing unit of the transmitter are the same as in the first embodiment. As shown in Fig. 3, information bits a k and check bits c (n-k) are selected, the selected information bits a k and check bits c (n-k) are combined to create bit strings g, the bit strings g thus created are subjected to parity checks to determine the value of the check bits c (n-k) , and the transmission code 1 thus produced are transmitted. When the transmission code 1 is received by the receiver, its processing unit creates bit strings g from the transmission code 1 received from the transmitter by carrying out the steps of the first embodiment in the reverse direction, as shown at A of the flowchart of Fig. 13. Specifically, when the receiver receives the transmission code 1, its processing unit is activated (Step 200). The transmission code 1 is temporarily stored in the memory 2 with addresses ad expressed in the number system having q as its base ( n = q h ) attached thereto (Step 210). Then, h-r digits are selected from the h digits of each address ad without duplication, and for each of the h C h-r combinations of h-r digits, a group G of check formulas are created, the check formulas being all the possible combinations of the integers of the selected h-r digits. Further, the bits to which the addresses belonging to the respective check formulas in each group G are attached are selected to create q h-r bit strings g for each group G. In the particular embodiment, h is 5 and r is 3 as in the first embodiment. Thus, two digits are selected from the five digits of each address ad. There are 10 such combinations. For each combination, a group G of check formulas are created, the check formulas being all the possible combinations of 1 and 0 in the two selected digits. Then, the same bit strings g created in the transmitter are created using the addresses ad (Step 215). Each bit string g is subjected to parity checks. The results are written in the memory 2 (Step 220). When all the bit strings g of one check formula group G have been checked for parity (Step 230), the other groups G are also subjected to parity checks one after another (Step 250). If parity break is detected, the processing unit carries out combination correction operations (Step 310) as shown at B in the flowchart of Fig. 13. More specifically, as shown in Fig. 14, the check formulas used to create the bit strings, in which the selected two digits are definite, while the remaining digits are indefinite, are attached to the respective bit strings g. Then, logic operations are carried out on the following principles. (1) While errors can be detected in a maximum of q h-r bit strings g in the h C h-r check formula groups, no operations are carried out between check formulas in the same one check group G. (2) Operations are always carried out for r+1 check formulas, and not for other combinations. That is, check formula groups G in which parity break has been detected are picked out, and the following logic operations are carried out between arbitrarily picked out r+1 check formula groups G. Thus, it is possible to point out bits in error because each check formula group G has address components. Maximum possible number of times such operations are carried out is p C r+1 ·q (h-r)(r+1) (where P = h C h-r ). As shown in Fig. 15A, Each check formula group G includes e.g. two effective digits f h . In the embodiment, two (h-r) of the five digits of the check formulas in each group G are effective. Thus, by combining any four check formula groups G, it is possible to cover all the digits f h of the check formulas as shown in Fig. 15B. By using check formula groups G, correction equations Hn which can specify any address ad are obtainable (Fig. 15B). In this embodiment, each correction equation Hn selects one digit from the five digits. Thus, as shown in Figs. 16A-16E, by collecting any 4 (r+1) check groups G, which all cover the same one digit, it is possible to specify an address ad. In the figures, f h 4 indicates the digit f h which is covered by all the four groups G. There are h C h-r-1 · q (h-r)(r+1) combinations of such groups G. It is thus possible to greatly reduce the number of operations. Logic operations are carried out between the same digits of the selected check formulas according to the following truth value table. 0 1 2 * * * 1-1 · 0 0 · · · · · · 0 1 · 1 · · · · · 1 2 · · 2 · · · · 2 * · · · * · · · * * · · · · * · · * q-1 · · · · · * q-1 q-1 · 0 1 2 * * * 1-1 · ┌ · ┘ : indefinite ┌*┘ : number in number system having q as its base For example, operations are carried out between check formulas as follows: (···01) × (··00·) × (·0·0·) × (0··0·) = (00001) (···01) × (··00·) × (·0·0·) × (0··0·) = ( ····· ) => indefinite Suppose now the bit at the address (00001) is in error as shown in Fig. 14, then parity break will be detected at (···01) in G 1 , (·· 0·1) in G 2 , (·0··1) in G 3 , (0···1) in G 4 , (··00·) in G 5 , (·0·0·) in G 6 , (0··0·) in G 7 , (·00··) in G 8 , (0·0··) in G 9 , and (00···) in G 10 . Thus, the correction equations H n shown in Fig. 16 will be as follows: H 1 = G 1 × G 2 × G 3 × G 4 = (···01) × (··0·1) × (·0··1) × (0···1) = (00001) H 2 = G 1 × G 5 × G 6 × G 7 = (···01 ) × (··00·) × (·0·0·) × (0··0·) = (00001) H 3 = G 3 × G 5 × G 8 × G 9 = (··0·1) × (··00·) × (·00··) × (00···) = (00001) H 4 = G 3 × G 5 × G 8 × G 10 = (·0··1) × (·0·0·) × (·00··) × (00···) = (00001) H 5 = G 4 × G 7 × G 9 × G 10 = (0···1) × (0··0·) × (0·0··) × (00···) = (00001) That is, the solutions of the above equations H 1 -H 5 are all (00001). The bit at this address is thus corrected (Step 320). When all the equations Hn have been solved and the bit in error has been corrected (Step 330), bit strings g are created from the corrected transmission code 1, and subjected to parity checks to detect transmission errors if any (Steps 220-270). In this case, since only one bit, at (00001), was in error, no parity break will occur again. Thus, data are outputted (Step 290) and the error detection/correction process is terminated (Step 300). Even if errors are detected at a plurality of addresses at the same time, it is possible to detect and correct such errors by using the above equations in the following manner. Suppose the bits at (00001) and (11001) are in error, as shown in Fig. 17 . Then, parity break will be detected at (·0··1) and (·1··1) in G 3 , (0···1) and (1···1) in G 4 , (·0·0·) and (·1·1·) in G 6 , (0··0·) and (1··1·) in G 7 , (·00··) in G 8 , (0· 0··) and (1·0··) in G 9 , and (00···) and (11···) in G 10 . The first round of correction operations using the correction equations Hn as shown in Figs. 18 and 19 will specify the addresses (00001) and (01001). The bits at these addresses are thus altered. Since the originally correct bit at (01001) is altered, parity break will now be detected at (0···0), (0···1) and (1···1) in G4, (·0·0·) and (·1·0·) in G 6 , (0··0·) and (1··0·) in G 7 , (·10··) in G 8 , (0·0··) and (0·1··) in G 9 , and (01···) and (11···) in G 10 , as shown in Fig. 20. Correction operations are thus carried out again. This time, as shown in Figs. 21 and 22, the bits at (01001) and (11001) will be specified. These bits are thus altered. The altered bits coincide with the original ones. Thus, no parity break will be detected in the bit strings g created from the transmission code 1 thus corrected. That is, the transmission code 1 has now been restored. In this method, bit strings g are created by combining information bits a k and check bits c (n-k) of the transmission code 1. The code 1 are then corrected by attaching check formulas to the plurality of bit strings g thus created. It is thus possible to correct even multiple errors with high reliability. In the particular embodiment, bit strings are created based on addresses ad expressed in binary notation. That is, the following relations are met: Its limit formula is: The limit formula of hamming of a conventional code is: Thus, there is a correction between M1 (present invention) and M (prior art): M>M1 This means that in the arrangement of the present invention, it is possible to use a greater M than in the conventional arrangement, provided the code lengths are the same. It is thus possible not only to transmit data with high efficiency but to correct even multiple errors with high reliability. In the arrangement of the present invention, since h-digit addresses ad are expressed in binary notation, there is the following relation between the number of effective digits in each check formula group G and the number of indefinite digits: detection capacity: 2 h-r+1 - 1 + α bits correction capacity: 2 h-r - 1 + β bits α and β will be explained in the following comparison examples. In the specific embodiment, h is 5 and r is 3. Thus, the following equations are met: detection capacity: 2 5-3+1 - 1 = 7 bits correction capacity: 2 5-3 - 1 = 3 bits To deepen understanding, solutions for part (H 1 ) of the correction equations H n for (2 5 , 16) 2 used in the description of the embodiment are shown in Figs. 30-37. Solutions for H 2 -H 5 are omitted because they are easily inferable from the solutions for H 1 . The numbers at the right end of the equations are the decimal notations of the binary numbers. In the embodiment, the addresses ad are attached from al toward a k , but may be attached in the reverse order. In the latter case, the information bits a k are allocated to the addresses ad having 1's by a predetermined number or less, and the value of the check bit c (n-k) to which the smallest address ad is attached is changed for each bit string g based on even parity. Other processes are carried out in the same way as above. Their description is thus omitted. In the second embodiment, many useless operations that produce indefinite results are carried out using the correction equations H n , as shown in Figs. 18 and 19. In an arrangement shown in Figs. 23 through 27, in order to eliminate such useless operations, only the correction equations H n that produce effective results, and the data obtained are prepared in the processing unit of the receiver in the form of a data table. By using this table, it is possible to carry out only the effective operations and thus to increase the processing speed. Since useless operations are eliminated, the number of operations carried out decreases dramatically to h C h-r-1 ·q h . In an alternate embodiment of the second embodiment, it is possible to set a correction coefficient A, the number of checks N and the number of corrected bits L. As shown in Fig. 28, the method of this embodiment includes, besides the steps of the second embodiment, shown in the flowchart of Fig. 9, the step of setting the number of checks, the correction coefficient and the number of corrected bits (205), the step of determining the number of checks (305), the step of determining the level of the result of correction operations (315), the step of determining the number of bits to be corrected (317), and the step of setting the number of bits (318). The number of checks is set in Step 205 to set the number of times error corrections are made. In Step 305, when the number of times error corrections are made reaches the preset number N, the process is terminated and a request for retransmission is issued. It is thus possible to eliminate the necessity of repeatedly making corrections due to many errors when the data are transmitted, and thus to maintain high efficiency of transmission even if a long time is needed for error corrections. The correction coefficient is set in Step 205 to set the level of capacity to correct errors in bit strings g detected in the receiver. That is, during corrections, the address ad attached to each bit can appear once to h C h-r-1 times. For example, in level A, if h C h-r-1 = 5 C 1 = 5 , the number of equations H n is five. Thus, the address (00000) can appear once to five times. Since the bit at any address that has appeared five times has the highest possibility that it is in error, corrections are made only if an address ad attached to any bit to be corrected appears A (1 ≦ A ≦ 5) times. That is, in this arrangement, the number of error bit detection/correction operations are set in Step 205, and the memory 2 is not corrected in Step 315 if the number of appearances of a certain address ad is less than A. Further, the number of bits corrected at one time in Step 205 is limited to a predetermined value to improve the processing capacity while keeping high reliability. In this case, the number L of bits corrected at one time is set at: L ≦ q h-r-1 or less The number L is determined so that the number of addresses that can be corrected, i.e. h C h-r-1 , will be maximum. Corrections are made only for q h-r-1 or less addresses ad counted from h C h-r-1 downward. For example, if h C h-r-1 is 5 C 5-3-1 = 5, the same address can appear once to five times. If there are a plurality of such addresses ad, q h-r-1 = 2 5-3-1 = 2 1 or less addresses, i.e. two or one address is corrected. For example, only the addresses that appeared five times and four times are corrected, while the remaining addresses, i.e. addresses that appeared three times, twice and once are not. It is thus possible to improve processing capacity without impairing reliability. For this purpose, the number of bits to be corrected are determined in Step 317, and if this number is L or less, corrections are made as it is. If over L, only L addresses ad as counted from the largest one downward are corrected in Step 318. With this arrangement, errors can be corrected most efficiently. This embodiment is otherwise the same as the embodiment of Fig. 9. Next, description is made of the third embodiment, which is a method of correcting transmission errors of digital signals which can reduce burst errors. In this method, as shown in Fig. 29A, a transmission code 1 is created by combining a plurality of transmission signals d n , D n that have been produced separately by the processing unit of the transmitter, and sent to the receiver. Upon receiving the code 1, as shown in Fig. 29B, the processing unit of the receiver detects and corrects transmission errors by splitting the transmission code 1 received. When the transmission code 1 combined in the transmitter is split in the receiver, bursts are cut, so that errors decrease and the correction capacity improves. In this embodiment, transmission signals d n and D n are combined alternately with each other. But they may be combined in any other way depending upon the way burst occur, which is determined e.g. by experiments. In the above-described embodiments, address codes ad are expressed in binary notation. But they may be expressed in any other number system having a base of N (N = 2, 3 ... ), as in the first embodiment. In this embodiment, two digits of each address ad was used to select bit strings g. But the number of digits used for this purpose is not limited to two. In order to evaluate the error detection/correction capacity of the method according to the present invention, comparison was made with the coding rate and error detection/correction capacity in a source BHC code. The results are shown below. (Comparison Example) 1. Coding rate Coding rates are compared under the following conditions: Code length: 7-64 bits i. source BHC code Errors in 3 bits are corrected, and errors i four bits are detected.Present Invention (2 h , k) 2 code ii. errors in (3 + α) are corrected, and errors in (7 + β) bits are detected. α and β are expected values. a) Source BHC code (n,k) (7,1) 15,5) (31,16) (63,45) code length n 7 15 31 63 check bit 1 5 16 45 coding rate 14.3 % 33.8 % 51.6 % 71.4 % b) Present Invention (2 h , k) 2 code (2 h ,k) 2 (2 3 ,1) 2 (2 4 ,5) 2 (2 5 ,16) 2 (2 6 ,42) 2 code length n 8 16 32 64 check bit 1 5 16 42 coding rate 12.5 % 31.3 % 50.0 % 65.6 % Thus, (2 h , k) 2 code according to the invention is at least as high in coding rate as the source BHC code. 2. Error detection/correction capacity When α , β are added as expected values, the code according to the invention is at least as high in error correction capacity as the source BHC. If other factors, such as higher coding rate, higher error detection capacity, and the ability to exclude any wrong corrections, are taken into consideration, the code according to the present invention can be said to be superior to the conventional code. Description of the expected value β Up to 2 h-r+1 -1 bits are detectable. All the other bits, except part of the bits in which β is 2 h-r+1 multiplied by (n/2 h-r+1 ), are also detectable. That is, all the bits are detectable except that part of the bits are not detectable if the number of bits in error is 8, 16, 24 or 32. The error detection rates when there are 8, 16 and 24 error bits. 8 error patterns: Only ten of 10,518,300 bits are not detectable. 5 C 3 / 32 C 8 = 10/10, 518, 300 ≒ 1 × 10 -5 16 error patterns: Only five of 601,080,390 bits are not detectable. 5 C 4 / 32 C 16 = 5/601, 080, 390 ≒ 0.8 × 10 -5 24 error patterns: Only 15 of 10,518,300 bits are not detectable. ( 5 C 3 + 5 C 4 )/ 32 C 24 = 15/10, 518, 300 = 1.4 × 10 -6 Description of the expected value α Up to (2 h-r -1) bits are all correctable. For α : (2 h-r - 2 h-r+1 - 1), part of the bits are not correctable. Correction capacity is calculated for 1-7 bits in error. For 1, 2 and 3 error patterns, all the bits are correctable. For 4 error patterns, 700 of 35,960 are not correctable though detectable. 5 C 3 × 8 C 4 / 32 C 4 = 10 × 70/35, 960 ≒ 2 × 10 -2 For 5 error patterns, 560 of 201,376 are not correctable, though detectable. 5 C 3 × 8 C 5 / 32 C 5 = 10 × 56/201, 376 ≒ 2. 8 × 10 -3 For 6 error patterns, 280 of 906,192 are not correctable, though detectable. 5 C 3 × 8 C 6 / 32 C 6 = 10 × 28/906, 192 ≒ 3.1 × 10 -4 For 7 error patterns, 80 of 3,365,856 are not correctable, though detectable. 5 C 3 × 8 C 7 / 32 C 7 = 10 × 8/3, 365, 856 ≒ 2.4 × 10 -6 From the expected value calculated from the above results, one can see that seven bits can be corrected almost perfectly. That is, theoretically, detection capacity is nearly perfect for 1-31 bits, and correction capacity is nearly perfect for 1-7 bits, though such expected values may vary depending upon pseudo-random error generating characteristics. The code according to the invention is thus superior both in error detection and correction capacities to expanded BHC codes. 3. Algorithm In computer software, many useless operations are carried out to correct errors. By eliminating such useless operations, it is possible to reduce the number of operations to 1/8 in the case of 2 5 (h=2, r=3), as is apparent from the formula EXP 2 [h-(h-r)(r+1)] The error detection and correction capacities vary widely depending not on the error pattern but on whether the number of error bits is even or odd. Industrial Application According to this invention, a plurality of bit strings created by combining information bits and check bits in the transmission code are used to detect and correct transmission errors. It is thus possible to detect and correct even multiple errors with high reliability. This method can be used not only in the communications field but for data transmission between computer drives and CPU's.

Claims: A method for detecting errors in transmission of n (in number) digital signals which are a mixture of k (in number) information bits (a k ) and n-k check bits (c (n-k) ), said method comprising, in a processing unit of a transmistter: attaching n addresses (ad) which are h-digit numbers expressed in a number system having integer q as its base ( n = q h ) to said respective n digital signals, allocating said check bits (c (n-k) ) to respective addresses (ad) each including h-r (1 ≦ r ≦ h) integers q-1 or 0's, and allocating said information bits (a k ) to the remaining ones of said addresses, selecting h-r digits from the h digits of each of said addresses (ad) without duplication, creating h C h-r ·q h-r bit strings (g) each comprising q r bits having the same integers for the selected h-r digits, determining the value of the check bits (c (n-k) ) in each bit string (g) to which the largest address (ad) is attached by subjecting the respective bit strings (g) to parity checks, thus producing a transmission code (1), and in a processing unit of a receiver: attaching n addresses (ad) which are h-digit numbers expressed in a number system having integer g as its base ( n = q h ) to said respective n digital signals of said transmission code (1) received from said transmitter, selecting h-r digits from the h digits of each of said addresses (ad) without duplication, creating h C h-r ·q h-r bit strings (g) each comprising q r bits having the same integers for the selected h-r digits, and detecting errors in transmission by subjecting the respective bit strings (g) to parity checks. A method as claimed in claim 1 wherein all or part of the h digits of each address (ad) are expressed in different number systems having different integers as their bases. A method for correcting errors in transmission of n (in number) digital signals which are a mixture of k (in number) information bits (a k ) and n-k check bits (c (n-k) ), said method comprising, the steps carried out in the processing unit of the transmitter as claimed in claim 1 or 2, and in a processing unit of a receiver: attaching n addresses (ad) which are h-digit numbers expressed in a number system having integer q as its base ( n = q h ) to said respective n digital signals of said transmission code (1) received from said transmitter, selecting h-r digits from the h digits of each of said addresses (ad) without duplication, creating a group (G) of check formulas for each of the h C h-r combinations of h-r bits, said check formulas in each group (G) being all the possible combinations of the integers of the selected h-r digits, creating q h-r bit strings (g) for each group (G), each of said bit strings comprising q r bits to which are attached addresses (ad) having the same integers at the selected h-r digits, allocating each check formula to a respective bit string (g), wherein only the h-r digits of said each check formula used to select said respective bit string (g) are effective digits and the retaining digits are indefinite, and correcting any bit in error by repeatedly subjecting said bit strings (g) to parity checks to calculate any parity break, collecting r+1 bit strings (g) in which parity break has been detected for each check formula group (G) and subjecting the thus collected r+1 bit strings to logic operations to find out the address of any bit in error. A method as claimed in claim 3 wherein said logic operations are carried out for check formulas based on correction equations (H n ) for calculating effective digit components by performing logic operations between said check formula groups (G). A method as claimed in claim 3 or 4 wherein only logic operations that give effective results are carried out between the check formulas. A method as claimed in any of claims 3-5 wherein the step of correcting transmission errors is repeated N times. A method as claimed in any of claims 3-6 wherein the step of correcting transmission errors is carried out by comparing the operation results calculated from the check formulas and pointed to an identical address (ad) with a predetermined number A. A method as claimed in any of claims 3-7 wherein a predetermined number L of bits are corrected at one time. A method as claimed in any of claims 3-8 wherein all or part of the h digits of each address (ad) are expressed in different number systems having different integers as their bases. A method as claimed in any of claims 3-9 wherein a plurality of bits are combined into a transmission signal (1) in the processing unit of said transmitter and are transmitted to the receiver in a serial order, and the processing unit of the receiver separates the bits of the signal received, creates the original transmission signal (1) from the separated bits, and corrects any error present in the transmission signal (1) thus created.

Inventors: IMAZU RYUZO, IMAZU, RYUZO
Applicants: IMAZU RYUZO, IMAZU, RYUZO
Application year: 1996
Main classification: H03M13
IPC codes: H04L1, H03M13