BIPOLAR SILICON-ON-INSULATOR TRANSISTOR WITH INCREASED BREAKDOWN VOLTAGE

Abstract: In a bipolar silicon-on-insulator transistor comprising a substrate (1) having a major surface, an oxide layer (2) on said major surface, a silicon layer (3) of a first conductivity type on said oxide layer (2), a base region (4) of a second conductivity type extending into said silicon layer (3), an emitter region (5) of said first conductivity type extending into said base region (4), and a collector region (6) of said first conductivity type extending into said silicon layer (3) at a lateral distance from said base region (4), a plug region (8) of said second conductivity type extends into said silicon layer (3) up to said oxide layer (2) on the opposite side of said emitter region (5) relative to said collector region (6), a portion (8') of said plug region (8) extends laterally along the surface of said oxide layer (2) under at least part of the emitter region (5) towards the collector region (6) at a distance from said base region (4), and said plug region is electrically connected to said base region (4).

Description: Bipolar silicon-on-insulator transistor with increased breakdown voltage TECHNICAL FIELD The invention relates to a bipolar silicon-on-insulator transistor comprising a substrate having a major surface, an oxide layer on said major surface, a silicon layer of a first conductivity type on said oxide layer, a base region of a second conductivity type extending into said silicon layer, an emitter region of said first conductivity type extending into said base region, and a collector region of said first conductivity type extending into said silicon layer at a lateral distance from said base region. BACKGROUND OF THE INVENTION Such a transistor is known e.g. from the paper "Analysis of New High-Voltage Bipolar Silicon-on-insulator Transistor with Fully Depleted Collector" by Torkel Arnborg and Andrej Litwin in IEEE Transactions on Electron Devices, Vol. 42, No. 1, January 1995. In the known transistor, the breakdown voltage drops very sharply while increasing the substrate voltage in comparison to the emitter voltage for npn transistors and the opposite for pnp transistors. That is due to the fact that an accumu¬ lation layer is created under the emitter of the transistor, which accumulation layer for a certain substrate voltage value makes it impossible to fully deplete the collector under the emitter and lock the potential. The breakdown voltage is thus the same as it would be for a vertical transistor with buried layer and an epitaxial layer over it with similar epitaxial layer thickness and doping as the silicon-on-insulator layer, which breakdown is quite low. Having the same requirements on the breakdown voltage for both npn and pnp transistors implies that the substrate voltage needs to be close to the middle of the applied operational voltage span. That further lowers the highest possible breakdown voltage for the transistor. Also, a soft collector breakdown or punch through may in some cases start just before the potential lock occurs for increasing collec¬ tor bias. BRIEF DESCRIPTION OF THE INVENTION The object of this invention is to prevent this type of breakdown by changing the electric field to reduce or prevent the creation of the accumulation layer on the collector-oxide interface under the emitter. This is attained in the transistor according to the invention in that a plug region of said second conductivity type extends into said silicon layer up to said oxide layer on the opposite side of said emitter region relative to said collector region, that a portion of said plug region extends laterally along the surface of said oxide layer under at least part of the emitter region towards the collector region at a distance from said base region, and that said plug region is electrically connected to said base region. Hereby, the voltage operating area will increase before breakdown occurs for the transistor with fully depleted collector. BRIEF DESCRIPTION OF THE DRAWING The invention will be described more in detail below with reference to the appended drawing on which Fig. 1 is a schematic cross-sectional view of a first em¬ bodiment of a transistor according to the invention, Fig. 2 is a schematic cross-sectional view of a second embodiment of the transistor according to the invention, and Fig. 3 is a schematic cross-sectional view of a third em¬ bodiment of the transistor according to the invention. DETAILED DESCRIPTION OF THE INVENTION Fig. 1 shows a first embodiment of a bipolar silicon-on- insulator (SOI) npn transistor according to the invention. With reverse doping polarities, the invention applies as well to pnp transistors. The transistor comprises a silicon substrate 1, on a major surface of which an insulating layer 2 of silicon dioxide, is provided. A silicon layer 3 which is weakly doped with impurities of conductivity type N, is provided on the insulating oxide layer 2. A base region 4 which is doped with impurities of con¬ ductivity type P, extends into the silicon layer 3 from the free surface thereof. An emitter region 5 which is heavily doped with impuri- ties of conductivity type N, extends into the base region 4 from its free surface. At a lateral distance from the base region 4, a collector region 6 which is heavily doped with impurities of conduc¬ tivity type N, extends into the silicon layer 3 from the free surface thereof. To reduce or prevent the creation of an accumulation layer on the interface between the silicon layer 3 and the oxide layer 2 under the emitter region 5, a plug region 7 which is doped with impurities of conductivity type P, i.e. the same conductivity type as the base region, extends into the silicon layer 3 down to the oxide layer 2 on the opposite side of the emitter region 5 relative to the collector region 6. In the embodiment shown in Fig. 1, the plug region 7 extends completely through the base region 4 and is in elec¬ trical contact with that base region 4. Fig. 2 shows a second embodiment of the bipolar SOI tran¬ sistor according to the invention. The general design of the transistor according to Fig. 2, is the same as that of the transistor according to Fig. 1, and identical elements are provided with identical reference numerals. The design of the plug region 8 of the transistor accor¬ ding to Fig. 2, differs however from that of the transistor according to Fig. 1 in that it comprises a portion 8' which extends laterally along the surface of the oxide layer 2 towards the collector region 6 at a distance from the bottom surface of the base region 4. According to the invention, the plug region portion 8' extends laterally along the surface of the oxide layer 2 under at least part of the emitter region 5. The lateral portion 8' of the plug region 8 should at the most extend laterally up to the edge of the base region 5, facing the collector region 6. Fig. 3 shows a third embodiment of the bipolar SOI transistor according to the invention. The general design of the transistor according to Fig. 3 does not differ from that of the transistors according to Figs. 1 and 2, and, consequently, identical elements are provided with the same reference numerals as the elements of the transistors according to Figs. 1 and 2. The transistor according to Fig. 3 comprises a plug region 9 which extends down to the oxide layer 2 at a lateral distance from the base region 4. However, according to the invention, the plug region 9 and the base region 4 are electrically interconnected by an external conductor 10. The plug region 9 according to Fig. 3, may also be provided with a lateral portion (not shown) similar to the lateral portion 8' of the plug region 8 in Fig. 2. According to a further embodiment (not shown) , the plug region may extend partially through the base region 4 and partially outside the base region 4. When, in the embodiments according to Figs. 1, 2 and 3, a voltage is applied between the collector 6 and the base 4, a lateral depletion of the collector region close to the plug region is started, whereby the accumulation layer at the interface between the collector and the oxide layer is reduced. When a breakdown is caused by base punch through, the lateral field from the base region will increase the space charge layer between the base and the collector and thus delay punch through. Also, when the breakdown is caused by impact ionization, the field redistribution from the base region will result in a lower field strength and a delay of the avalanche break¬ through. The delay in breakdown with increasing collector voltage will be sufficient for the later occurring potential lock to protect the transistor. The plug region 8, 8' according to Fig. 2, is more difficult to manufacture than the plug regions 7 and 9 according to Figs, l and 3, respectively, but all plug region embodiments contribute towards increasing the voltage operat¬ ing area before breakdown for transistors with fully depleted collector.

Claims: CLAIMS 1. A bipolar silicon-on-insulator transistor comprising - a substrate (1) having a major surface, - an oxide layer (2) on said major surface, - a silicon layer (3) of a first conductivity type on said oxide layer (2) , - a base region (4) of a second conductivity type extending into said silicon layer (3) , - an emitter region (5) of said first conductivity type extending into said base region (4) , and - a collector region (6) of said first conductivity type ex¬ tending into said silicon layer (3) at a lateral distance from said base region (4) , characterized in that a plug region (8) of said second conductivity type extends into said silicon layer (3) up to said oxide layer (2) on the opposite side of said emitter region (5) relative to said collector region (6), that a portion (8') of said plug region (8) extends laterally along the surface of said oxide layer (2) under at least part of the emitter region (5) towards the collector region (6) at a distance from said base region (4) , and that said plug region is electrically connected to said base region (4) . 2. A transistor as claimed in claim 1, characterized in that said plug region (8) extends, at least partially, through said base region (4) . 3. A transistor as claimed in claim 2, characterized in that said plug region (8) extends completely through said base region (4) . 4. A transistor as claimed in claim 1, characterized in that said plug region extends at a lateral distance from said base region (4) . 5. A transistor as claimed in claim 4, characterized in that said plug region is externally connected to said base region (4). 6. A transistor as claimed in any of claims 1 - 6, charac¬ terized in that said portion (8') of the plug region (8) extends laterally up to the edge of the base region (4) .

Inventors: ARNBORG TORKEL, LITWIN ANDREJ, ARNBORG, TORKEL, LITWIN, ANDREJ
Applicants: ARNBORG TORKEL, ERICSSON TELEFON AB L M, LITWIN ANDREJ, ARNBORG, TORKEL, LITWIN, ANDREJ, TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
Application year: 1996
Main classification: H01L29
IPC codes: H01L21, H01L29