Method of fabricating a bipolar transistor

Abstract: There is provided a method of fabricating a semiconductor device having a base region and an emitter region both of which are formed in self-aligned fashion with a base opening at which a base region is to be formed, comprising, at least, the steps of (a) forming a collector region (6) in a semiconductor substrate (14) prior to depositing an insulating film (4) over the semiconductor substrate (14), and (b) forming a region at which a collector electrode (10b) is to be formed simultaneously with a region at which an emitter electrode (10a) is to be formed. The method makes it possible decrease the number of photolithography steps by two relative to a conventional method.

Description: The invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a bipolar transistor to be fabricated in self-aligned fashion. With LSI having been improved to have a higher performance recently, a bipolar transistor is requested to have a higher performance. In particular, a bipolar transistor is requested to have a higher operation rate. To accomplish such a request, it is material to reduce parasitic capacity and/or parasitic resistance in a bipolar transistor. Various self-align techniques have been proposed to do so, but simultaneously cause a method of fabricating a bipolar transistor to be more complicated and also cause the number of fabrication steps to increase. Hereinbelow is explained a conventional method of fabricating a bipolar transistor in a self-aligned fashion, with reference to Figs. 1A to 1F. As illustrated in Fig. 1A, an n-type buried layer 2 is formed in a desired region in a p-type semiconductor substrate 14. An n-type epitaxial layer 1 is made grown over the semiconductor substrate 14, and then, there are formed trench-type isolation regions 3 defining a region therebetween in which a semiconductor device is to be formed. Then, there is deposited a silicon dioxide film 4 over a resultant, and an opening BE is formed in the silicon dioxide film 4 by means of photolithography at a region where base and emitter are to be formed. Then, a silicon dioxide film 4a is formed within the opening BE. The silicon dioxide film 4a is thinner than the first formed silicon dioxide film 4. Then, an opening C is formed by means of photolithography at a region where a collector electrode is to be formed, as illustrated in Fig. 1B. Then, a polysilicon film 5 is deposited all over a resultant by means of chemical vapor deposition (CVD), as illustrated in Fig. 1C. Then, ion implantation is carried out in selected regions by means of photolithography. Specifically, boron (B), one of p-type impurities, is implanted into a region where a base is to be formed, and phosphorus (P), one of n-type impurities, is implanted into a region where a collector electrode is to be formed, as illustrated in Fig. 1C. Then, photolithography and etching are carried out to thereby remove the polysilicon film 5 at regions other than regions where a base/emitter and a collector electrode are to be formed. Namely, the polysilicon film 5 is now existent only at regions where a base/emitter and a collector electrode are to be formed. Then, the semiconductor substrate is thermally annealed to thereby make phosphorus contained in the polysilicon layer 5 diffuse into the n-type buried layer 2 in a region where a collector electrode is to be formed. Thus, a collector region 6 is formed, as illustrated in Fig. 1D. Then, a silicon nitride film 7 is deposited over a resultant by means of CVD, and there is formed an opening 7a so that the thin silicon dioxide film 4a is exposed in a region where a base is to be formed, as illustrated in Fig. 1E. Then, an exposed portion of the thin silicon dioxide film 4a and a portion of the silicon dioxide film 4a located just below ends of the polysilicon film 5 are etched for removal with weak hydrofluoric acid to thereby form undercut hollow portions below the polysilicon film 5. Then, a polysilicon film 8 is deposited in the opening 7a by CVD so that the undercut hollow portions are filled therewith. Then, the thus deposited polysilicon film 8 is etched out so that the polysilicon film 8 is existent only in the undercut hollow portions. Then, boron ions are implanted into the epitaxial layer 1 through the opening 7a, followed by thermal annealing, to thereby form a base region 11 in the epitaxial layer 1. Then, an insulating film 9 is deposited over a resultant, and is anisotropically etched so that the insulating film 9 is existent only on an inner sidewall of the opening 7a. Then, an n-type polysilicon film 10 is formed over a resultant, and is patterned to cover the opening 7a, as illustrated in Fig. 1F. Then, the semiconductor substrate is thermally annealed to thereby make impurities contained in the n-type polysilicon film 10 diffuse into the base region 11 to thereby form an emitter region 13. The above mentioned thermal annealing carried out for the formation of the base region 11 makes p-type impurities contained in the polysilicon film 5 diffuse into the n-type epitaxial layer 1 through the polysilicon film 8 to thereby form external base regions 12. The above mentioned conventional method needs seven photolithography steps to be carried out after the formation of the device isolation regions 3 in order to fabricate a bipolar transistor: (1) first for forming the opening BE in the silicon dioxide film 4 at a region where base/emitter are to be formed; (2) second for forming the opening C in the silicon dioxide film 4 at a region where a collector electrode is to be formed; (3) third for carrying out p-type impurities ion implantation into the polysilicon film 5 at a region where a base electrode is to be formed; (4) fourth for carrying out n-type impurities ion implantation into the polysilicon film 5 at a region where the collector region 6 is to be formed; (5) fifth for patterning the polysilicon film 5; (6) sixth for forming the base opening 7a through the silicon nitride film 7 and the polysilicon film 5; and (7) seventh for patterning the polysilicon film 10. As mentioned above, the conventional method of fabricating a bipolar transistor in self-aligned fashion needs a lot of photolithography steps to be carried out, which increases the number of fabrication steps and lengthens the term for fabrication of a bipolar transistor. In addition, the increased number of fabrication steps is accompanied with problems of reduction in fabrication yield and increased fabrication cost. EP-A-0 425 242 describes a method of fabricating a semiconductor device comprising the steps of, in sequence: partially forming a first conductivity type buried layer in a semiconductor substrate and also forming a first conductivity type epitaxial layer in the buried layer, forming a collector region in the epitaxial layer by selectively introducing first conductivity type impurities into the epitaxial layer so that the collector region reaches the buried layer, forming an insulating film on the epitaxial layer, forming a second conductivity type impurities doped polysilicon film on the insulating film, patterning the polysilicon film to form a base electrode, forming an interlayer insulating film over the base electrode and the insulating film, forming a base region in the epitaxial layer by introducing second conductivity type impurities into the epitaxial layer to the base opening, and forming a second conductivity type impurities doped polysilicon film over the structure. However, in this method first and second impurities are implanted into a non-doped polysilicon film through first and second masks, such that two masking steps are necessary. EP-A-0 297 335 shows method features such as patterning both an interlayer insulating film and a base electrode to form a base opening at a region at which a base region is to be formed and a collector opening above the collector region, an insulating sidewall formed on an inner wall of the first collector opening and patterning second conductivity type impurities doped polysilicon film to form both an emitter electrode and a collector electrode. Furthermore, DE-A-39 40 394 discloses the steps of first forming an insulating side wall on inner walls of first and second base openings and then a first conductivity type emitter region in a surface of the base region. It is an object of the present invention to provide a method of fabricating a semiconductor device which is capable of decreasing the number of photolitographic steps without sacrifying high performance given to a bipolar transistor by a self-align process to thereby decrease the number of fabrication steps and enhance fabrication yield. This object is achieved by a method as defined in claim 1; the dependent claims are related to further developments of the invention. In accordance with the above mentioned present invention, it is possible to fabricate a bipolar transistor in a self-aligned fashion with a smaller number of photolithography steps than with the conventional method. Accordingly, the present invention makes it possible to fabricate a bipolar transistor in the less number of fabrication steps with a higher fabrication yield and smaller cost than with the conventional method. Figs. 1A to 1F are cross-sectional views of a bipolar transistor, each drawing showing respective step of a conventional method of fabricating a bipolar transistor. Figs. 2A to 2F are cross-sectional views of a bipolar transistor, each drawing showing respective step of a method of fabricating a bipolar transistor to be carried out in accordance with the first embodiment of the present invention. Figs. 3A to 3C are cross-sectional views of a bipolar transistor, each drawing showing respective step of a method of fabricating a bipolar transistor to be carried out in accordance with the second embodiment of the present invention. [First Embodiment] As illustrated in Fig. 2A, an n-type buried layer 2 is formed in a desired region in a p-type semiconductor substrate 14. After an n-type epitaxial layer 1 has been grown over the semiconductor substrate 14, there are formed trench-type isolation regions 3 defining a region therebetween in which a semiconductor device is to be formed. Then, a first photolithography step is carried out. That is, phosphorus (P) ion implantation is carried out in the first lithography step into a selected region in the n-type epitaxial layer 1, for instance, at a dose of 5 × 10 15 cm -2 at 70 KeV to thereby form a collector region 6 in the n-type epitaxial layer 1. Then, a silicon dioxide film 4 is formed all over a resultant by means of thermal oxidation or chemical vapor deposition (CVD). Then, a second photolithography step is carried out for forming a base/emitter opening BE at a region where base and emitter are to be formed and a collector opening C at a region where a collector electrode is to be formed. Then, the semiconductor substrate 14 is thermally annealed to thereby form thinner silicon dioxide films 4a than the first formed silicon dioxide film 4 within the base/emitter opening BE and collector opening C, as illustrated in Fig. 2B. Then, as illustrated in Fig. 2C, a polysilicon film 5 is formed all over the silicon dioxide films 4 and 4a by means of CVD, followed by boron (B) ion implantation into the polysilicon film 5. Then, a third photolithography step is carried out. Specifically, the polysilicon film 5 is patterned by the third photolithography and further by etching to thereby form a base electrode 5a and a dummy electrode 5b both on the thinner silicon dioxide film 4a, each covering the base/emitter opening BE and collector opening C, respectively, as illustrated in Fig. 2D. Then, a silicon nitride film 7 is deposited over a resultant by CVD. Then, a fourth photolithography step is carried out. That is, the silicon nitride film 7 and the polysilicon films 5a and 5b in regions where a base and a collector electrode are to be formed, respectively, are patterned in the fourth photolithography step and successively etched for removal to thereby form a base opening 7B and a collector opening 7C through which the thinner silicon dioxide films 4a are exposed, as illustrated in Fig. 2E. Then, exposed portions of the thinner silicon dioxide films 4a and portions of the silicon dioxide film 4a located just below ends of the polysilicon films 5a and 5b are etched for removal with weak hydrofluoric acid to thereby form undercut hollow portions below the polysilicon films 5a and 5b. Then, a polysilicon film 8 is deposited in the base and collector openings 7B and 7C by CVD so that the undercut hollow portions are filled therewith. Then, the thus deposited polysilicon film 8 is etched out so that the polysilicon film 8 is existent only in the undercut hollow portions. Then, boron ions are implanted into the epitaxial layer 1 at a dose of 2 × 10 13 cm -2 at 10 KeV through the base and collector openings 7B and 7C, followed by thermal annealing to thereby form a base region 11 in the epitaxial layer 1 just below the base opening 7B. It should be noted that the collector region 6 has a high phosphorus concentration, and hence the collector region 6 is not inverted to p-type in spite of the above mentioned boron ion implantation. Then, an insulating film 9 is deposited over a resultant, and is anisotropically etched so that the insulating film 9 is existent only on inner sidewalls of the base and collector openings 7B and 7C. Then, an n-type polysilicon film is formed over a resultant, and is patterned to form an emitter electrode 10a covering the base opening 7B and a collector electrode 10b covering the collector opening 7C by means of a fifth photolithography step, as illustrated in Fig. 2F. Then, the semiconductor substrate is thermally annealed to thereby make impurities contained in the n-type polysilicon film 10a diffuse into the base region 11 to thereby form an emitter region 13 therein. The above mentioned thermal annealing carried out after the formation of the polysilicon film 8, in particular, the thermal annealing carried out for the formation of the base region 11 makes p-type impurities contained in the polysilicon film 5a diffuse into the n-type epitaxial layer 1 through the polysilicon film 8 to thereby form external base regions 12 around the base region 11, as illustrated in Fig. 2F. Since the collector region 6 is designed to have a phosphorus concentration higher than a boron concentration, the above mentioned p-type impurities diffusion does not cause the collector region 6 to be inverted to a p-type one. As is obvious in view of the foregoing description, the photolithography steps are carried out five times in order to fabricate a transistor after the formation of the device isolation regions 3. That is, the above mentioned first embodiment makes it possible to fabricate a transistor with the two smaller number of photolithography steps than the conventional method. [Second Embodiment] The method in accordance with the second embodiment has the same steps as those of the first embodiment having been explained with reference to Figs. 2A to 2C. Accordingly, first and second photolithography steps have been already carried out in the second embodiment which is explained hereinbelow. A polysilicon film is formed all over the silicon dioxide films 4 and 4a by means of CVD, followed by boron (B) ion implantation into the polysilicon film. Then, a third photolithography step is carried out. Specifically, the polysilicon film is patterned by the third photolithography and further by etching to thereby form a base electrode 5a on the thinner silicon dioxide film 4a, covering the base/emitter opening BE, as illustrated in Fig. 3A. Then, a silicon nitride film 7 is deposited over a resultant by CVD. Then, a fourth photolithography step is carried out. That is, the silicon nitride film 7 and the polysilicon film 5a in regions where a base and a collector electrode are to be formed, respectively, are patterned in the fourth photolithography step and successively etched for removal to thereby form a base opening 7B and a collector opening 7C through which the thinner silicon dioxide films 4a are exposed, as illustrated in Fig. 3B. Then, exposed portions of the thinner silicon dioxide films 4a and portions of the silicon dioxide film 4a located just below ends of the polysilicon film 5a are etched for removal with weak hydrofluoric acid to thereby form undercut hollow portions below the polysilicon film 5a. Then, a polysilicon film 8 is deposited in the base and collector openings 7B and 7C by CVD so that the undercut hollow portions are filled therewith. Then, boron ions are implanted into the epitaxial layer 1 at a dose of 2 × 10 13 cm -2 at 10 KeV through the base and collector openings 7B and 7C, followed by thermal annealing to thereby form a base region 11 in the epitaxial layer 1 just below the base opening 7B. Then, an insulating film 9 is deposited over a resultant, and is anisotropically etched so that the insulating film 9 is existent only on inner sidewalls of the base and collector openings 7B and 7C. Then, an n-type polysilicon film is formed over a resultant, and is implanted with phosphorus. Then, the n-type polysilicon film is patterned to form an emitter electrode 10a covering the base opening 7B and a collector electrode 10b covering the collector opening 7C by means of a fifth photolithography step and etching, as illustrated in Fig. 3C. Then, the semiconductor substrate is thermally annealed to thereby make impurities contained in the n-type polysilicon film 10a diffuse into the base region 11 to thereby form an emitter region 13 therein. Since boron contained in the polysilicon film 5 is not diffused into the collector region 6 in the above mentioned second embodiment, it is possible to make collector resistivity in a transistor smaller than that of the first embodiment. It should be noted that the thinner portion 4a of the silicon dioxide film 4 located just above the collector region 6 may be formed also in the collector opening 7C in both the above mentioned first and second embodiments.

Claims: A method of fabricating a semiconductor device, comprising the steps of, in sequence: (a) forming a first conductivity type buried layer (2) in a predetermined region of a semiconductor substrate (14) and also forming a first conductivity type epitaxial layer (1) on the buried layer (2); (b) forming a collector region (6) in the epitaxial layer (1) by selectively introducing first conductivity type impurities into the epitaxial layer (1) so that the collector region (6) reaches the buried layer (2); (c) forming an insulating film (4) on the epitaxial layer (1); (d) forming a polysilicon film (5) on the insulating film (4); (e) implanting a second conductivity type impurity into the polysilicon film (5) to thereby form a second conductivity type impurities doped polysilicon film (5); (f) patterning the polysilicon film (5) to form both a base electrode (5a) and a dummy electrode (5b) above the collector region (6) on the insulating film (4); (g) forming an interlayer insulating film (7) over the base electrode (5a) and the insulating film (4); (h) patterning both the interlayer insulating film (7) and the base electrode (5a) to form a base opening (7B) at a region at which a base region is to be formed and a collector opening (7C) above the collector region (6); (i) removing portions of the insulating film (4) located in both the base opening (7B) and the collector opening (7C) and side-etching portions of the insulating film (4) located below the base electrode (5a) to form undercut hollow portions in the insulating film (4); (j) filling the undercut hollow portions with polysilicon (8) ; (k) forming a base region (11) in the epitaxial layer (1) by introducing second conductivity type impurities into the epitaxial layer (1) through the base opening (7B); (l) forming insulating sidewalls (9) on inner walls of the base and collector openings (7B, 7C); (m) forming a first conductivity type impurities doped polysilicon film over a resultant; and (n) patterning the first conductivity type impurities doped polysilicon film to form both an emitter electrode (10a) and a collector electrode (10b). The method as set forth in claim 1, wherein the insulating film (4) is formed in the step (c) so that the insulating film (4) has thinner portions (4a) in regions at which the base electrodes and collector electrodes are to be formed than in the remaining portions. The method as set forth in claim 2, wherein one of the thinner portions (4a) of the insulating film (4) located above the collector region (6) are situated within the collector opening (7C).

Inventors: WATANABE TAKESHI, WATANABE, TAKESHI
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1996
Main classification: H01L29
IPC codes: H01L29, H01L21