Fully digital drive system for brushless motor with voltage/current profiles read from a digital memory

Abstract: Pre-defined driving profiles for the distinct phase-windings of an electronically controlled brushless motor, are continuously reconstructed for each switching phase and forced in the form of a drive current or voltage on the respective windings, in synchronism with a signal indicative of the rotor position, from just a first complete sequence and at least a first sample of the successive sequence of a number of sequences, each of N samples, equal to number of switching phases of the motor, in which is divided a complete digital pre-defined profile. The digital samples are stored in a nonvolatile memory (M1) and are scanned at a continuously regulated clock frequency and with varying order and direction of scan for reconstructing the instantaneous driving profiles for all the windings.

Description: The present invention relates to driving techniques for an electronically switched DC motor, commonly referred to as "brushless". The document US-A-4,409,534, discloses a digital drive system for an electronically switched synchronous machine. The windings are driven with a sinusoidal waveform in an open loop mode, by reading amplitude values of the sinusoidal vaweform. The read values correspond to sample values of a digitized quarter (90°) of the sinusoidal vaweform, and they are permanently stored in a memory or look-up table. Distinct and mutually outphased profiles are reconstructed by logic means by scanning the stored digital samples of a quarter of the sinusoidal profile. European Patent EP-A-0 800 263 in the name of the same applicant describes a driving technique, according to which through the motor's phase windings are forced excitation currents (or voltages) which, rather than having a certain pre-established and substantially constant level during each switching phase, possess a certain profile (not of a constant value) that may be preventively defined, digitized and stored in a nonvolatile static memory such as an EPROM or an EEPROM. The pre-defined profile (obviously cyclic or alternate) may be a sinusoid or more generally the resulting waveform of a sum of Fourier harmonics of a fundamental frequency. In practice, this technique allows for the optimization of the torque characteristics of the motor, allowing for the pre-definition of a more adequate cyclic form of the excitation current or of the voltage to be forced or applied on the phase windings of the motor. The current (or the voltage) forced during each switching phase does not correspond to a certain constant value as it is the usual case in known driving systems, but rather to a certain profile congruent with the whole pre-defined cyclic or alternate waveform. A second patent application EP-A-0 800 262 in the name of the same applicant discloses a particularly suited synchronization technique of the different excitation phases in respect to the real rotor's position in order to optimize the torque characteristic, in relation to a driving system as that illustrated in the previously cited patent application EP-A-0 800 262. The driving system described in the above-identified patent applications envisages the storage in different buffers of the driving current or voltage profiles for the different motor's windings. This entails a certain costly requirement of nonvolatile memory capacity. The present invention aims to reduce this requirement by providing for a reconstruction logic circuitry of current or the voltage profiles of phase excitation for the corresponding motor's windings during all the switching phases, in order allow for permanently storing in a nonvolatile manner only a significant part of an entire excitation profile (waveform) of a motor's phase winding. This important result is obtained by assuming (as in the above mentioned prior patent applications) the subdivision in a given number of sequences, each of N samples, and equal in number to the motor's switching phases, of a whole driving profile. The system permanently stores in a nonvolatile memory a first whole sequence of N samples of the six sequences into which is subdivided an entire cycle or profile for 360 electric degrees and only a half of the N samples of the successive sequence, in practice a total number of samples equal to N+1/2N. As a whole, these digitized and stored samples correspond to a quarter of the entire periodic driving profile of a phase winding, typically having an almost sinusoidal form or being the result of a sum of harmonics. In accordance with the invention, it is possible to further reduce the nonvolatile memory requisite by just the N samples of the first sequence and only the first sample of the following sequence, that is one sample more than the N samples that pertain to just 60 electric degrees of an entire excitation profile or waveform of 360 electric degrees, as will be shown in details further on in this description. Another important aspect of the invention consists in that the entire driving system can be implemented in digital form using configurable logic devices like PLA or similar programmable devices. The various aspects and advantages of the invention will become even dearer through the following description of some important embodiments and by referring to the attached drawings, wherein Figure 1 shows the meaning of the notation used in the present context; Figure 2 is a prior art scheme of a transconductance control loop of the current forced through a motor's winding; Figure 3 shows a sinusoidal current profile divided in six sequences of N samples each; Figure 4 shows a block diagram of the system of the invention; Figure 5 illustrates the power-up and reset conditions of the counters that generate the addresses; Figures 6 and 7 respectively show the block diagram and the I/O signals of the PWM CONVx (x=1,2,3) converters; Figure 8 shows a scheme of the SCANGEN block used as a digital frequency multiplier; Figure 9 shows a block diagram of an alternative embodiment of the system of the invention; Figure 10 is a block diagram of a further alternative embodiment of the system of the invention; Figure 1 depicts the classical scheme of a DC motor having three phase windings connected in a star configuration. The standard notation is that of indicating each excitation phase by two capital letters, the first capital letter (for example A, B, C) defines the winding through which the current conventionally flows from the respective supply terminal towards the star center (CT) and the second capital letter, preceded by the sign (!), designates the winding through which the current, conventionally coming from the star center, flows towards the supply terminal of the relative winding. The currents scheme for the six different switching phases (A!B, A!C, B!C, B!A, C!A, C!B), referred to the case of a three winding motor is illustrated in Figure 1. These brushless motors are commonly driven by an integrated circuit whose output stage is represented by a multiphase full-wave bridge circuit, which in the case of a three-phase motor may employ six bipolar (BJT) or field effect (MOS) power transistors. The motor's current may be linearly controlled by a transconductance loop, as disclosed in Figure 2, for the case of a current mode control. As an alternative, it is also possible to implement a voltage mode control. During a certain switching phase of the motor, the "sourcing" power transistor is forced into full conduction (that is to saturation in case of an MOS device) whereas the "sinking" power transistor operates as an element of transconductance, according to the scheme of Figure 2, which refers to the use of power MOS devices. With reference to Figure 2, the motor's current may be expressed as follows: Imotor = Vref Gv*Rs where Vref is the control voltage, generated by a phase-locked speed regulation loop (PLL), Gv is the voltage gain of the sensing amplifier while Rs is the current sensing resistor. In the prior art, the voltage Vref is set to a certain value by a dedicated phase locked regulating loop (PLL), in order to regulate the current absorbed by the motor and thus maintain a given rotational speed under varying load conditions. Of course, the regulation PLL loop acts upon the Vref value by varying its instantaneous value about its regulating value, in order to compensate for instantaneous load-torque variations. In line with the technique described in the prior European Patent application 0 800 263 and also with the synchronization system disclosed in the prior patent application EP-A-0 800 262, through the motor's windings a certain current or voltage periodic profile is forced through the succession of switching phases. The period of the driving signal profile for each winding is equivalent to the time taken by the rotor to complete an entire electric turn and this entire periodic profile is divided into the same number of sequences of N samples each of the switching phases of the motor, when driven as illustrated in the diagram of Figure 3. As described in the application EP-A-0 800 262, the system requires the generation of a synchronization pulse ZC (or RZC), congruent with the instantaneous position of the rotor and which is asserted at the instant of synchronization of the scanning of the sequence of samples. By defining Tc to represent the time interval between two consecutive assertions of the ZC pulse, each of the six sequences of N samples that made up the entire driving signal profile for winding must be scanned in an interval of time corresponding to the last measured value of the time interval Tc or in other words the system must force ideally the xN th (x=1,6) in the coincidence with the last instant of a Tc interval. The system of the invention may utilize the same scheme of synchronization described in the patent application EP-A-0 800 262 or even an equivalent scheme, however rather than storing a complete series of sequences of N samples, it only stores one significant portion of the totality of said samples. According to a first embodiment the system stores just a first quarter of the whole series of samples, that is only the samples of the first sequence and the first sample of the following sequence of N samples belonging to the successive sequence. In practice, the system allows for storing the samples of the driving profile or waveform relative to the first 90 electric degrees of the whole profile (rotor's rotation). The entirely digital system may be considered as consisting of two main parts or portions. A first part defines the logic circuitry capable of reconstructing a whole driving profile from the N plus a number of samples of the next sequence less than the first N/2 samples thereof permanently stored samples, as well as reconstructing the other two similar profiles, out-of-phase by 120 and 240 electric degrees, respectively, from the first profile, relative to the three phase windings of the motor shown in Figure 1. The other functional part or portion, which may also be realized entirely in digital form, modulates the amplitude of the three reconstructed driving profiles in function of the content of a dedicated register AMPCONTROL of K bits. As a whole, the block diagram of the system of the invention, according to the embodiment, is shown in Figure 4. The nonvolatile memory M1 contains the values relative to digital samples of the first quadrant of the pre-defined driving profile (as current or voltage samples), that is the N samples of the first of the six sample sequences and the first sample of the second sequence of the sequences into which is divided the whole period of the driving profile. On the assumption of digitizing each sample in form of a word made up of an X number of bits, then, the permanently (nonvolatily) samples stored in the memory M1 will have a value between 0 and 2 x -1. Because M1 must be capable of storing over N samples, its address bus must then have a number of AD bits, where AD is the lowest integer number equal or greater than the maximum number of stored samples. The whole pre-defined driving profile is divided into four zones or quadrants, respectively I, II, III, and IV and only a limited number of samples belonging to the quadrant I of the profile is sampled, digitized and stored in a nonvolatile manner. The remaining zones of the first quadrant as well as the other quadrants of the profile are reconstructed every time by the system. To attain this, the system recognizes to which zone or quadrant the digital value of the sample read from the memory must be attributed in order to properly reconstruct the profile. If the value to be read from the memory must be attributed to a sample of the quadrant I, then this is read and stored in the dedicated latch. The address of the memory is then incremented because in this zone I the profile or the sequence of stored digital values is scanned from left to right. Thereafter the sample is modulated by the digital multiplier MULx (x=1,2,3), divided by 2 k and subsequently complemented by 2 x by the block WOx (x=1,2,3). In this way it assumes a full dynamic amplitude as permitted by the X+1 number of bits into which each sample of the three output sequences or profiles is digitized. If the sample or digital value read from M1 must be attributed to the zone or quadrant II, after being stored in the dedicated latch, the address of the digital memory is decremented because in zone II the profile is scanned from right to left. Also in this case the sample is modulated by the digital multiplier MULx (x=1,2,3), divided by 2 k and afterwards complemented by 2 x by the WOx (x=1,2,3) block, in order to assume a full dynamic amplitude, as permitted by the X+1 number of bits into which each sample of the three output sequences or profiles is digitized. If attributed to zone III, the sample is read and stored into the dedicated latch and the address of the digital memory is incremented because in zone III the profile is again scanned from left to right. The sample is thereafter modulated by the digital multiplier MULx (x=1,2,3), divided by 2 k and is then complemented by the module 2 x by the block WOx (x=1,2,3) to attain the full dynamic of amplitude allowed by the X+1 number of bits into which each sample of the three output sequences is digitized. If the sample read from the memory belongs to zone IV, after being stored into the dedicated latch, the address of the digital memory is decremented because in zone IV the profile is scanned from right to left. The sample is then modulated by the digital multiplier MULx (x=1,2,3) divided by the module 2 k and thereafter is complemented by 2 x by the block Wox (x= 1, 2, 3) to attain the full dynamic of amplitude permitted by the X+1 number of bits into which each sample of the three output sequences is digitized. Since the motor requires three similar driving signals out-of-phase by 120 electric degrees among each other, the system has three address counters of the up/down type AC1, AC2, and AC3, which point the correct datum in the common memory M1, whose addresses bus has a number AD of bits The ACx (x=1,2,3) counters are synchronized by the clock signal FSCAN generated by the SCANGEN block which multiplies by a factor N the frequency of the synchronization signal ZC. In this way, each sequence of N samples fits within the time interval Tc (equivalent to the interval between two consecutive assertions of the synchronism pulse ZC). At the power-on instant, the three address generators are pre-set with the first three correct values (RESET1, RESET2, RESET3), out-of-phase by 120° among each other, as shown in Figure 7, wherein the first counter is pre-set so to address the first sample of the entire series of samples, whereas the remaining two are pre-set as pointing the N th sample. The Sx blocks supervise the preleading of the addresses at power-on or resynchronization of the addresses with the ZC signal. These S1, S2, S3 blocks are described in details in the cited prior European patent application EP-A-0 800 263. The state of the two bits counters C1, C2 and C3 defines one of the four zones or quadrants and by calling Q0x and Q1x the two output bits of the respective Cx(x=1,2,3), the following relationships may be established: Q0x Q1x Addressed zone 0 0 I 1 0 II 0 1 III 1 1 IV At power-on, the counters Cx (x=1,2,3) are pre-set in a proper state, as shown in Figure 7, whereby C1 is forced to state I, C2 is forced to state II and C3 is forced to state III. A new configuration of the Cx (x=1,2,3) counters is forced every 3/2 N samples addressed and "buffered" by acting upon the NSx (x=1,2,3) signals originating from the respective address generators. When Q0x (x=1,2,3) is low, it forces the respective address generator to count upward, while forcing the same generator to count downward when Q0 is high. The Q1x signal forces the respective offsetting block of the Wox (x=1,2,3) waveform to add 2 x to the input datum, if Q1x is low, or to complement the input datum with the 2 x module, if Q1 x is high. AM is an address multiplexer that, functioning collectively with the two bit counter, the module three block AMC, to the demultiplexer of 1-to-3 lines DMX and the three synchronization blocks SINCx (x=1,2,3), permits to "bufferize" the subsequent data of the profile in the latches Lx (x=1,2,3). The process of addressing through the multiplexer employs the fastest clock available, using for example the system's frequency FSYS. At each leading front of the system's clock signal FSYS, the AMC counter forces AM to address M1 on the proper datum and forces the DMX to address the appropriate "buffer". At each trailing front of the system's clock signal FSYS, the datum at the M1 output is stored in the so selected latch (buffer). The SINCx (x=1,2,3) blocks prevent a simultaneous updating of the AC1, AC2 and AC3 counters upon a reading of the AM block. Thereafter, the reconstructed portions of the profile are then amplitude modulated and employed in reconstructing the actual drive signals of the motor's windings. The profiles at the output of the latches have a normalized amplitude of 2 x -1. The three multiplier blocks MULx (x=1,2,3) have the task of digitally multiplying the data present at the outputs of the respective Lx latches by an updatable value contained in the K-bit register AMPCONTROL. The multiplier should have an output capacity capable of supporting the required number of bits to express the result of the multiplication: for instance, if X=7 and k=8, the multiplier should have a digital output of at least 15 bits. The KVAL value in the AMPCONTROL register modulates the amplitude of the reconstructed drive profiles and this value may be continuously updated through a control routine of the motor's speed performed by the PLLSPEED block. The datum at the multiplier output is divided by 2 k , where K is the number of bits of the AMPCONTROL register, because the output samples are correlated to the input samples by way of the following equations: OUTx = INx*KVAL 2 K x=1,2,3 if K=8, then OUTx = INx*KVAL 256 x=1,2,3 where INx are the input samples of the multiplier and OUTx are the output data of the multiplier after amplitude modulation. Finally, the sample value is translated by the WOx (x=1,2,3) block so to properly reconstruct the whole profile with the maximum possible amplitude dynamics. The state signal Q11, Q12 and Q13 originating from the state counters C1, C2 and C3 are input to the WOx (x=1,2,3) blocks. The following table illustrates the action of the WOx blocks on the input signals. Q1x (x=1,2,3) effect of the WOx block 0 adds 2 x to the input datum 1 complements the input datum with the module 2 x The Dx (x=1,2,3) data of the respective WOx blocks output define the properly reconstructed and modulated sequences of the predefined current or voltage profile. The CONVx blocks (x=1,2,3) convert the Dx (x=1,2,3) sequences of input samples of X+1 bits into three PWM signals. The CONVx blocks carry out the following conversion (assuming X+1=8): INPUT BYTE PWM% OUTPUT 0 0 127 50 255 100 An embodiment of one of these converting blocks for X+1=8 is shown in Figure 9. The INPUT sample is transferred through the synchronizing latch SL to the B input of the 8-bit comparator (COMP) whereas at the A input of the same is fed the output of the CNT counter synchronized with the clock FSYS. PWMOUT represents the alternating output of the FF2 latch which may be either set or reset (depending on whether a direct PWM signal or an inverted signal is required) at power-on commanded by the INITIALIZE block. The "Toggle" FF1 latch, at power-on, forces the CNT counter to count up. When the counter CNT reaches a value equal to that at the input B of COMP, the latter sets the signal A=B which switches FF2 so that PWMOUT goes high (if the value at the input B is equal to A when EOC is reached, then FF2 will not switch because the EN signal of CNT is forced low). When the counter CNT reaches the top counting limit, it switches FF1 via EOC, thus forcing the CNT counter to count down. When the counter CNT reaches again the value equal to that present at the input B of COMP, the latter sets again the signal A=B, the latch FF2 is reset and thus PWMOUT goes low again. When the counter CNT reaches the bottom counting limit, the latch FF1 switches and forces CNT to count up again and the process is repeated. Therefore, the frequency of the PWMOUT signal is given by: Fpwmout = FSYS 2 X+2 Figure 10 depicts the signals involved in the above described data/PWM conversion for the case of X+1=8. The PWMOUTx (x=1,2,3) signals may directly drive three half-bridge power stages, functioning in a PWM mode or may be filtered through a simple RC network so to reconstruct three analog drive profiles. Figure 11 shows an embodiment of the SCANGEN block representing a digital PLL block used by the system to generate the FSCAN frequency that times the address generators ACx (x=1,2,3). As stated above, FSCAN must be N times higher than the frequency of the synchronism signal ZC. The assertion of the synchronism signal ZC resets the counter CNTUP which is timed with a frequency equal to FSYS/2N and loads the CNTDOWN counter with the last value present at the outputs of CNTUP before it is reset. Because the CNTDOWN is directly timed by FSYS and because the FF3 latch is switched at each EOC of the CNTDOWN counter, the outcome is that the frequency of the FSCAN signal at the FF3 output is exactly N times the frequency of the ZC signal. Figure 12 shows another embodiment of the system in which the third profile is reconstructed as the sum of the remaining two profiles. In this instance all the blocks of the scheme of Figure 4 relating to the third profile (x=3) may be eliminated whereas the SUM and NEG blocks must be added to reconstruct the third profile from the other two. The SUM block adds the X+1 bit data to the outputs of the WO1 and WO2 blocks and the corresponding results are truncated at the least significative X+1 bits. Of course the sum is synchronized so to be enabled when the two input data are stable. The NEG block inverts the least significative X bits of the sample at the output of the SUM blocks and the resultant signals are thereafter loaded into the CONV3 block. The most significative bit (MSB) is not inverted and is loaded directly into the CONV3 block as MSB. According to this embodiment, the DMX block is a demultiplexer of 1-to-2 lines while the AMC block may be replaced by a simple TFF latch. According to the invention in M1 only N+1 samples, equivalent to just one sample more than those pertaining to the first 60 electric degrees of a whole profile are stored. By observing the scheme of Figure 4, at each instant the sample stored in the M1 portion between N+1 and 3/2N is read. As already described and illustrated in Figure 12, given two profiles it is possible to reconstruct the third by means of simple operations in a way that is feasible to obtain a wave profile derivable from the set of samples N+1..3/2N thanks to the fact that the other two waves in any case exploit samples stored in the cells 0 to N of M1. Considering the reset situation of Figure 7 and referring to the scheme of Figure 4, it may be noted that in the first 60 degree, the profiles 1 and 2 point the memory in the set 0..N so that the third profile 3 must be reconstructed from the first two. 60 degrees after the initial reset signal, the profile 1 is pointing to the N-1 cell in the memory, the profile 2 will be pointing the cell 1 of the memory, whereas the third profile will be pointing the N+1 sample, with the substantial difference that the profile 1 is about to exit the zone 0..N while the profile 3 will be entering it. Thus it will become necessary to reconstruct the profile 1 by exploiting the data of the other profiles 2 and 3. After further 60 degrees, the profile 1 will be pointing the N+1 cell of the memory, the profile 2 will be pointing the N-1 cell of the memory while the third profile will be pointing sample 1, the difference being that now the profile 2 is about to exit the zone 0..N while the profile 1 is about to enter it. Thus it will become necessary to reconstruct the profile 2 exploiting the data of the other profiles 1 and 3. The following table illustrates the method for an entire electric revolution from the moment of the initial reset. DEGREES 0..60 60..120 120..180 180..240 240..300 300..360 PROFILE BEING RECONSTRUCTED 3 1 2 3 1 2 By referring to Figure 13, the final stages that comprise the SUM, NEG, MULx, DIVx, WOx (x=1,2) and CONVx (x=1,2,3) block remain unchanged as compared to Figure 12. The modifications concern only the other blocks and in particular the way of accessing M1 has been modified by the addition of the SH block. The block SH is synchronized at each end of sequence and, by drawing the PWMx (x=1,2,3) signals from the output of the respective CONVx stages, it distributes them to the relative motor's winding through the PWMOUTx signals, according to the table shown above and more in particular, according to the following scheme: DEGREES 0..60 60..120 120..180 180..240 240..300 300..360 PWMOUT1 PWM1 PWM3 PWM2 PWM1 PWM3 PWM2 PWMOUT2 PWM2 PWM1 PWM3 PWM2 PWM1 PWM3 PWMOUT3 PWM3 PWM2 PWM1 PWM3 PWM2 PWM1 With regard to the addressing of the memory, AD must be the least integer greater or equal to log2(N+1) whereas the address counter (AC) may simply be an increment N-module counter. Indeed, the countdown from N to 0 is only necessary to obtain PWM2 and may be replaced by a (COMP) block capable of complementing to N the value coming from AC. The memory is alternatively addressed with the addresses relative to the PWM1 and PWM2 signals (synchronism managed by TFF); in particular COMP addresses the memory with the value coming from AC (properly synchronized by SYNC1), if at its F input the value is 0, otherwise the memory will be addressed by the value from AC, complemented to N. By doing so, in the LATCHx (x=1,2) buffers is stored the appropriate value because they are alternatively enabled by the signal coming from TFF. In particular, the LATCH 2 is directly enabled by the TFF output while the LATCH1 is enabled by the inverted signal of this output signal through INV2. A further modification of the scheme of Figure 12, consists in utilizing only one TFF2 rather than C1 and C2 to determine the value to be introduced at the SIGN input of the WOx (x=1,2) blocks because it is sufficient to alternatively force the signals 0 and 1 at the end of each scanning cycle of the memory. Indeed Q1x (x=1,2,3) of Figure 4 assume the following values: DEGREES 0..60 60..120 120..180 180..240 240..300 300..360 Q11 0 0 0 1 1 1 Q12 0 1 1 1 0 0 Q13 1 1 0 0 0 1 RECONSTRUCTED PROFILE 3 1 2 3 1 2 From these analysis can be gathered that in each zone, the Q1x relative to the reconstructed profile assumes a value different from the other two and in particular that the Qx relative to the "original" profiles assume the value 0, from 0 to 60 degrees, the value 1, from 60 to 120 and so forth alternately in the successive zones.

Claims: A method of driving a threephase brushless motor consisting in defining a current or voltage alternate profile for each phase winding of the motor so that the sum of the instantaneous values of said profiles is constant and forcing a current or a voltage according to said pre-defined profiles through the corresponding phase windings of the motor synchronously with a signal representative of the rotor's position by reading nonvolatily stored digitized samples of said pre-defined profiles pertaining to a portion of one entire profile according to a direction of scan, attributed sign and phase of the samples, coordinated to reconstruct whole alternate profiles, mutually outphased, for driving the respective phase windings, characterized in that it comprises defining, by subdivision of said profile, six sequences corresponding to six switching phases of a complete periodic driving cycle, each of 60 electric degrees and consisting of N samples; nonvolatily storing only a first complete sequence of N samples and the first sample of the following sequence of N samples corresponding to the next 60 electric degrees; reconstructing during each synchronized switching phase alternate profiles, mutually outphased among each other for the respective windings, by reading the stored N samples of said first sequence and at least a first sample of said maximum number of stored samples of the following sequence of N samples, according to a given order of scan, direction of scan, attribution of sign and phase of the samples. The method according to claim 1, characterized in that each sample is stored and read from a read only memory in the form of a word of an X number of bits. The method according to claim 2, characterized in that the N samples of said first sequence and said other sample belonging to the first half of the successive sequence of N samples in which is divided said alternate current or voltage profile are stored in said memory with an amplitude dynamics equivalent to a half of the dynamic of 2 X+1 allowed by the final stage of the driving system; the minimum sample value being stored as zero and the maximum value of said samples being stored as 2 x -1. The method according to any of the preceding claims, in which said memory is read alternatively with an address whose value increases from zero to N-1 and with its complement to N. The method according to any of the preceding claims, in which the motor has three phase windings connected in a star configuration and three identical reconstructed profiles out-of-phase by 120° from one another, are reconstructed from said N samples of said first sequence and from said first sample of the next sequence by alternating the calculation of the third, of the first and of the second profile operating on the first and second profile, on the second and third profile and on the first and third profile, respectively. A driving system of an electronically switched threephase brushless motor comprising a plurality of power stages driving as many phase windings of the motor, nonvolatile storing means (M1) of a pre-defined driving current or voltage alternate profile for said phase windings, a plurality of digital/analog converters (CONV1, CONV2, CONV3) converting the digital value of each sample into which is digitized a current profile in an analog driving signal (PWMOUT1, PWMOUT2, PWMOUT3), means (SYNC1, SYNC2, SYNC3) synchronizing the conversion of said samples read from said storing means (M1) with a signal (Z.C.) representative of the rotor's position, characterised in that only a first full sequence of N samples and the first sample of the successive sequence of N samples of the six sequences of N samples into which is equally divided a complete periodic cycle of 360 electric degrees of said current or voltage profile, are stored in said nonvolatile storing means (M1), and in that it comprises pointing means (AC1, AC2, AC3), in function of an address value (AD), of an individual sample belonging to said first complete sequence of N samples and to said first sample or samples belonging to said number of stored samples of the next sequence, during each reading phase of said nonvolatile storing means, logic circuit means (ACx) of reconstruction of complete alternate profiles, mutually outphased among each other, from said limited number of stored samples (N+1, 3/2N), multiplier means (MULx) multiplying the digital data of all the reconstructed profiles by a gain factor (KVAL) recorded in an updatable manner in a register (AMPCONTROL) by a speed control block (PLLSPEED). The system of claim 6, further including means (SUM, NEG), for reconstructing profile as a complement of profiles being reconstructed by reading the stored samples according to respective order of scan, direction of scan, attribution of sign and phase of the stored samples during each switching phase.

Inventors: MAIOCCHI GIUSEPPE, VITI MARCO, MAIOCCHI, GIUSEPPE, VITI, MARCO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1996
Main classification: H02P6
IPC codes: H02P6, H03B28, G06F1, H02P23