Manufacture method of a DRAM capacitor storage electrode with textured surface

Abstract: A capacitor of a highly integrated semiconductor device and a manufacturing method therefor are provided. In the highly integrated semiconductor device, an HSG polysilicon layer pattern (46a) is formed having a multitude of hemispherical grains (50a) (HSG) on the top and side surfaces of the storage electrode. Electrode separation is performed by selectively removing a silicide layer (52) that has been formed of a sacrificial metal layer (38) after the HSG step. The HSG polysilicon layer pattern does not have to be etched so that HSG polysilicon layer pattern (50a) on the top and side surfaces of conductive layer pattern (46a) remains intact.

Description: The present invention relates to a manufacturing method of a capacitor of a highly integrated semiconductor device, and more particularly, to a manufacturing method of a dynamic random-access memory (DRAM) cell capacitor provided with a stable storage electrode which increases capacitance by the formation of a multitude of hemispherical grains on a surface of the storage electrode. In order to keep pace with recent improvements in integration density, various methods for multiplying the storage electrode surface area of a DRAM cell capacitor have received much attention. One such method is the formation of a hemispherical-grain (HSG) polysilicon layer on the outer surface of the storage electrode in order to increase the surface area. FIGS. 1A-1E are sectional views for explaining a conventional method of manufacturing the capacitor. FIG. 1A shows a step of forming a spacer 20. In detail, first to third insulation layers such as an oxide layer, a silicon nitride layer and another oxide layer are successively deposited on a semiconductor substrate 10. A contact hole 18 for exposing a predetermined region of the semiconductor substrate is then formed by patterning the first to third insulation layers via photolithography, and concurrently forming first to third insulation layer patterns 12, 14 and 16. After this, spacer 20, formed of the nitride silicon layer, is formed on the sidewalls of contact hole 18. FIG. 1B shows a step of forming a photoresist layer pattern 24. A polysilicon layer 22 is deposited on the whole surface of the resultant structure of FIG. 1A, completely filling contact hole 18. A photoresist pattern 24 is then formed on polysilicon layer 22 above contact hole 18 by use of a storage electrode mask. FIG. 1C shows a step of patterning a polysilicon layer pattern 22a. That is, polysilicon layer pattern 22a covering contact hole 18 is formed by etching polysilicon layer 22 using photoresist pattern 24 as a mask. FIG. 1D shows a step of depositing an HSG polysilicon layer 26. After photoresist pattern 24 is removed, HSG polysilicon layer 26 is deposited on the whole surface of the resulting structure. FIG. 1E shows a step of completing the capacitor. In detail, HSG polysilicon layer 26 is anisotropically etched to electrically isolate polysilicon layer pattern 22a from the adjacent polysilicon layer pattern. As a result, HSG polysilicon layer 26 formed on third insulation layer pattern 16 between the adjacent polysilicon layer patterns and on the upper surface of polysilicon layer pattern 22a is etched away and is thus removed. Here, as shown in the drawing, etching of the upper surface of polysilicon layer pattern 22a is influenced by the uneven surface of HSG polysilicon layer 26, resulting in the formation of a polysilicon layer pattern 22b having very irregular surface protrusions. Here, portions (A) on the upper portions of the sidewalls of the polysilicon layer pattern 22b are also etched together with HSG polysilicon layer 26, thus exposing deformed polysilicon layer pattern 22b. Consequently, HSG polysilicon layer pattern 26a is formed only on the lower portions of the sidewalls of deformed polysilicon layer pattern 22b. After this, the capacitor is completed by depositing successively a dielectric layer (not shown) and a conductive layer for a plate electrode (not shown), using a common method, on the whole surface of the semiconductor device where the storage electrode, comprising deformed polysilicon layer pattern 22b and HSG polysilicon layer pattern 26a, is formed. As described above, the HSG polysilicon layer is anisotropically etched to isolate adjoining storage electrodes from each other electrically. In this case, not only the HSG polysilicon layers on the upper surface of the polysilicon layer pattern and the third insulation layer pattern, but also the HSG polysilicon layer formed on the upper portions of the sidewalls of the polysilicon layer pattern are etched. Since the polysilicon layer pattern has very irregular surface protrusions and a damaged surface, excessive leakage current occurs. In addition, the surface area of the storage electrode becomes smaller than desired, since the upper portions of the sidewalls of the polysilicon layer pattern are exposed. EP 448 374 describes a process for fabricating polycrystalline silicon with micro-roughness on its surface. US 5,278,091 describes a capacitor formed with a hemispherical grained conductive structure. To solve the above problems, it is an object of the present invention to provide a method according to claim 1. Accordingly there is provided a method for manufacturing a capacitor of a highly integrated semiconductor device, comprising the steps of: successfully forming on a semiconductor substrate first to third insulation layer patterns, a metal layer pattern and a fourth insulation layer and forming a contract hole for exposing a predetermined region of the semiconductor substrate therein; forming a spacer on the sidewalls of the contact hole; forming a conductive layer on the whole surface of the resultant structure completely filling the contact hole; forming a photoresist pattern on the conductive layer over the contact hole; forming a conductive layer pattern and a fourth insulation layer pattern for exposing the metal layer pattern around the contact hole and by sequentially etching the conductive layer and the fourth insulation layer using the photoresist pattern as an etching mask; removing the photoresist pattern; depositing an HSG (hemispherical grain) polysilicon layer on the whole surface of the resultant structure from removing the photoresist pattern; forming a metal silicide layer between the fourth insulation layer pattern by reacting the exposed metal layer with the HSG polysilicon layer thereon; and removing the metal silicide layer with a chemical solution. Thus, a storage electrode consisting of the conductive layer pattern and the HSG polysilicon layer formed on the top and side surfaces of the conductive pattern is formed. Specific embodiments of the present invention are described in detail below, by way of example, with reference to the attached drawings, in which: FIGS. 1A-1E are section views for explaining a manufacturing method of a capacitor according to a conventional technology; FIG. 2 is a section view illustrating a structure of a capacitor according to an embodiment of the present invention; and FIGS. 3A-3F are section views for explaining a manufacturing method of the capacitor according to an embodiment of the present invention. In FIG. 2, which illustrates the structure of a capacitor according to an embodiment of the present invention, reference numeral 30 denotes a semiconductor substrate; reference numeral 32 denotes a first insulation layer pattern being formed on semiconductor substrate 30 and including a contact hole for exposing a predetermined portion thereof; reference numeral 34 denotes a second insulation layer pattern being formed on first insulation layer pattern 32; reference numeral 36 denotes a third insulation layer pattern formed on second insulation layer pattern 34; reference numeral 40a denotes a fourth insulation layer pattern formed with a space above third insulation layer pattern 36 around the contact hole; reference numeral 44 denotes a spacer formed on the sidewalls of the contact hole formed through first, second and third insulation layer patterns 32, 34 and 36 and connected with fourth insulation layer pattern 40a; reference numeral 46a denotes a conductive layer pattern being formed on fourth insulation layer pattern 40a and filling the contact hole enclosed by spacer 44; and a reference numeral 50a denotes an HSG polysilicon layer pattern formed on surfaces of conductive layer pattern 46a. In this case, conductive layer pattern 46a and HSG polysilicon layer pattern 50a formed thereon constitute a storage electrode of the capacitor. As shown in FIG. 2, in accordance with the present invention, since a non-etched or undamaged HSG polysilicon layer pattern can be formed on the top and side surfaces of the conductive layer pattern 46a, a surface area of the storage electrode can be maximized. FIGS. 3A-3F are section views by process step for explaining a method of manufacturing the capacitor of the present invention shown in FIG. 2. FIG. 3A shows a step of forming a spacer 44. First, second and third insulation layers, e.g., an oxide layer, a silicon nitride layer and another oxide layer, are successively deposited on top of semiconductor substrate 30. After this, a metal layer, which may be any one selected from a group consisting of a tungsten layer, a tungsten nitride layer and a tungsten-rich tungsten nitride layer, is deposited on the third insulation layer. Subsequently, a fourth insulation layer, e.g., either a silicon nitride layer or an oxide layer, is deposited on the metal layer as a silicidation preventing layer. A contact hole 42 for exposing a predetermined region of semiconductor substrate 30 is formed by patterning the first to third insulation layers, the metal layer and the fourth insulation layer, and, concurrently, first to third insulation layer patterns 32, 34 and 36, a metal layer pattern 38 and a fourth insulation layer pattern 40 are formed. Next, after the silicon nitride layer is formed on the whole surface of the semiconductor substrate where contact hole 42 is formed, a spacer 44 formed of the silicon nitride layer is formed on the sidewalls of contact hole 42 by anisotropically etching the silicon nitride layer formed on the whole surface of the semiconductor substrate. In this arrangement, fourth insulation pattern 40 and spacer 44 will serve as a silicidation preventing layer when metal layer pattern 38 is reacted to become a silicide layer in a subsequent process. FIG. 3B shows a step of forming a photoresist layer pattern 48. A conductive layer 46 such as a polysilicon layer is formed on fourth insulation layer pattern 40, completely filling contact hole 42. A photoresist pattern 48 is formed on conductive layer 46 over contact hole 42 by using a mask for a storage electrode. FIG. 3C shows a step of forming a conductive pattern 46a and a fourth insulation layer pattern 40a. By using photoresist pattern 48 as an etching mask, conductive layer 46 and fourth insulation layer pattern 40 are anisotropically etched away to thereby form conductive layer pattern 46a and fourth insulation layer pattern 40a. Metal layer 38 around contact hole 42 is thus exposed. FIG. 3D shows a step of forming an HSG polysilicon layer 50. Initially, photoresist pattern 48 is removed. Then, by employing a common method, HSG polysilicon layer 50 is deposited on the whole surface of the semiconductor substrate from which photoresist pattern 48 has been removed. FIG. 3E shows a step of forming a metal silicide layer 52 characteristic of the present invention. In detail, in this embodiment of the present invention, the semiconductor substrate where HSG polysilicon layer 50 has been deposited is heat-treated at a temperature of 550~700°C. A metal silicide layer 52, such as a tungsten silicide layer, is formed by chemically reacting HSG polysilicon layer 50 formed in a region between fourth insulation layer pattern 40a, indicated by a "B" with the metal layer pattern 38 underneath it. While this occurs, HSG polysilicon layer pattern 50a on the top and side surfaces of conductive layer pattern 46a remains intact. In this case, the above heat-treatment is performed either by a rapid thermal processing method or by a method utilizing a furnace. FIG. 3F shows a completion step of the storage electrode. Metal silicide layer 52 is removed by using a chemical solution of NH 4 OH, H 2 O 2 and deionized water. The storage electrode made of conductive layer pattern 46a and HSG polysilicon layer pattern 50a is thus completed by removing metal silicide layer 52. At this point, the storage electrode is electrically isolated from the adjacent storage electrode, and HSG polysilicon layer pattern 50a, which is physically undamaged, is formed on the top and side surfaces of the conductive layer pattern 46a. Finally, the capacitor of the present invention is completed by successively depositing a dielectric layer (not shown) , and a conductive layer (not shown), on the whole surface of the resultant structure. As described above, according to the preferred embodiment of the present invention, the metal silicide layer is formed by reacting chemically the HSG polysilicon layer formed between the fourth insulation layer patterns and the metal layer pattern underneath it. The metal silicide layer is then removed by employing a wetetching process to isolate the storage electrode from the adjacent storage electrode. Accordingly, the HSG polysilicon layer pattern formed on the top and side surfaces of the conductive layer pattern can be prevented from undergoing etching and damage. Accordingly, capacitance of the capacitor can be increased by maximization of the surface area of the storage electrode consisting of the conductive layer pattern and the HSG polysilicon layer pattern. The leakage current can also be greatly reduced. It should be noted that the present invention is not limited to the preferred embodiment described above, and it is apparent that variations and modifications by those skilled in the art can be effected within the scope of the present invention as defined in the appended claims.

Claims: A method for manufacturing a capacitor of a highly integrated semiconductor device, comprising the steps of: (a) successively forming on a semiconductor substrate (30) first to third stacked insulation layer patterns (32, 34, 36), a metal layer pattern (38) and a fourth insulation layer (40) thereon, and forming a contact hole (42) for exposing a predetermined region of said semiconductor substrate (30) therethrough; (b) forming a spacer (44) on the sidewalls of the contact hole (42); (c) forming a conductive layer (46) for completely filling said contact hole (42) on the whole surface of the structure resultant from said step (b); (d) forming a photoresist pattern (48) on the conductive layer (46) over the contact hole (42); (e) forming a conductive layer pattern (46a) exposing the metal layer pattern (38) around the contact hole (42) and forming a fourth insulation layer pattern (40a) by sequentially etching the conductive layer (46) and the fourth insulation layer (40) using the photoresist pattern (48) as an etching mask; (f) removing the photoresist pattern (48); (g) depositing an (HSG) hemispherical grain polysilicon layer (50) on the whole surface of the structure resultant from said step (f); (h) forming a metal silicide layer (52) between fourth insulation layer patterns (40a) by reacting the exposed metal layer (38) with the HSG polysilicon layer (50) thereon; and (i) removing the metal silicide layer (52) with a chemical solution, thereby forming a storage electrode consisting of the conductive layer pattern (46a) and the HSG polysilicon layer (50a) formed on the top and side surfaces of the conductive layer pattern (46a). A method for manufacturing a capacitor of a highly integrated semiconductor device according to claim 1, wherein said conductive layer (46) is formed of a polysilicon layer. A method for manufacturing a capacitor of a highly integrated semiconductor device according to claim 1 or claim 2, wherein said metal layer (38) is formed of any one selected from the group consisting of a tungsten layer, a tungsten nitride layer, and a tungsten-rich tungsten nitride layer. A method for manufacturing a capacitor of a highly integrated semiconductor device according to any of claims 1 to 3, wherein said fourth insulation layer is formed of a silicon nitride layer. A method for manufacturing a capacitor of a highly integrated semiconductor device according to any of claims 1 to 4, wherein said fourth insulation layer pattern is formed of an oxide layer. A method for manufacturing a capacitor of a highly integrated semiconductor device according to any of claims 1 to 5, wherein said chemical solution is a mixture of NH 4 OH, H 2 O 2 and deionized water. A method for manufacturing a capacitor of a highly integrated semiconductor device according to any of claims 1 to 6, wherein said chemical reaction is performed through heat-treatment at a temperature of 550-700°C. A method for manufacturing a capacitor of a highly integrated semiconductor device according to claim 7, wherein said heat-treatment is performed by a rapid thermal process. A method for manufacturing a capacitor of a highly integrated semiconductor device according to claim 7, wherein said heat-treatment is performed by a method utilizing a furnace. A method according to any preceding claim including completing the capacitor by depositing a dielectric layer and a conductive layer on the whole surface of the structure.

Inventors: KIM KYUNG-HOON, PARK YOUNG-WOOK, YOO CHA-YOUNG, KIM, KYUNG-HOON, PARK, YOUNG-WOOK, YOO, CHA-YOUNG
Applicants: SAMSUNG ELECTRONICS CO LTD, SAMSUNG ELECTRONICS CO., LTD.
Application year: 1996
Main classification: H01L21
IPC codes: H01L21, H01L27