Read method and circuit for nonvolatile memory cells with an equalizing structure

Abstract: The read circuit presents a current mirror circuit (9) including a first and second load transistor (12, 13) interposed between the supply line (15) and a respective first and second output node (16, 17); the first output node (16) is connected to a cell (4) to be read; the second output node (17) is connected to a generating stage (20, 51) generating a reference current (I R1 ) having a predetermined characteristic; and the size of the second load transistor (13) is N times greater than the first load transistor (12). To permit rapid cell reading even in the presence of low supply voltage and with no initial uncertainty, an equalizing circuit (55) presents a current balancing branch (75) connected between the first output node (16) and ground for generating an equalizing current (I B ) presenting a ratio of 1/N with the reference current to balance the circuit before commencing the reading.

Description: The present invention relates to a read method and circuit for nonvolatile memory cells with an equalizing structure. As is known, to read the cells of nonvolatile, particularly flash, memories, the row and column to which the cell to be read is connected are appropriately biased and the current flow through the cell is detected. If the cell is written, its threshold voltage is higher than the read voltage and the cell conducts no current; if the cell is erased, its threshold voltage is lower than the read voltage, and the cell conducts current; and written and erased cells are discriminated by comparing the current flow in the cell with a reference current generated by a reference cell. The comparison is made by a read circuit comprising a current/voltage converter for converting the current of the cell to be read and the reference cell into corresponding voltages; and a sense amplifier for comparing the two voltages and generating a logic output signal, the state of which depends on the outcome of the comparison. To ensure correct read operation and reliable cycling (multiple cycle operation) of the memory array, certain limits must be posed to the distribution of the threshold voltages of the cells. More specifically, currently used technologies require that the threshold voltage of the most erased cells be above zero, and the threshold voltage of the worst erased cells be about 2.5 V. The lower limit substantially arises from the need to ensure against read errors caused by depleted cells (cells with a threshold voltage below zero); while the upper limit is due to the intrinsic distribution of the cell threshold voltages according to the fabrication technology used. Since the read voltage normally coincides with the supply voltage, read problems arise in the case of a low supply voltage (about 2.5 V), due to the poorly erased cells, which conduct a very low current, being considered written and so resulting in read errors. In view of the current demand for memories capable of operating within a wide range in relation to the supply voltage (typically, with supply voltages of 2.5 to 4 V) and with fast access times (<100 ns), a sense amplifier is required, which is capable of fast, correct reading within the full range of supply voltages involved. To solve the problem of achieving a reasonable read time of poorly erased cells, a first co-pending patent application (EP 0814480 A), entitled "Method and circuit for reading low-supply-voltage memory array cells", filed concurrently by the present Applicant, relates to a solution in which the current/voltage converter operates in the opposite way as compared with standard converters, to enable even poorly erased array cells to be read rapidly in the presence of low supply voltage (when the memory cells conduct a low current). For the written cells to be determined correctly, however, the above solution poses limits as regards the maximum permissible supply voltage. In this connection, Figures 1 and 2 show the solution proposed in the aforementioned first co-pending patent application entitled "Method and circuit for reading low-supply-voltage memory array cells". In Figure 1, the read circuit is indicated by 1, and comprises an array branch 2 and a reference branch 3; array branch 2 comprises an array cell 4 to be read, forming part of a memory array 5 and connected to an array bit line 6; reference branch 3 comprises a reference cell 7 connected to a reference bit line 8; array bit line 6 (together with other array bit lines not shown and forming part of memory array 5) and reference bit line 8 are connected to a current/voltage converter 9 via a known decoding, biasing and equalizing circuit 10 not essential to the description and therefore not shown in detail; and circuit 10 provides for selecting the array bit line 6 of the cell 4 to be read, appropriately biasing it (and reference bit line 8) to prevent spurious read phenomena such as soft writing, and possibly also equalizing lines 6 and 8 before the cell is actually read. Converter 9 comprises an array load 12 and reference load 13 forming a current mirror circuit and connected to array and reference bit lines 6 and 8 via circuit 10. More specifically, and according to the teachings of the above first co-pending patent application, array load 12 comprises a diode-connected PMOS transistor, and reference load 13 a PMOS transistor; array load transistor 12 has the source terminal connected to a supply line 15 at V CC , the drain terminal connected to circuit 10 at a node 16, the gate terminal connected to the gate terminal of reference load transistor 13, and a width/length ratio W/L = K; and reference load transistor 13 has the source terminal connected to supply line 15, the drain terminal connected to circuit 10 at a node 17, and a width/length ratio W/L = N*K, where N is a multiplication constant. Nodes 16, 17 are connected to the inputs of sense amplifier 18. In the Figure 1 circuit, since the diode (low-impedance) element is connected to array bit line 6 instead of reference bit line 8, and in view of the width/length ratio of transistors 12 and 13, the current in I/V converter 9 is imposed by memory cell 4, and is supplied, amplified by N, to reference branch 3 where it is compared with the current flowing in reference cell 7. This therefore provides for rapidly reading the array cell, even when it is poorly erased and conducts only a small amount of current due to the low supply voltage. Figure 2 shows the current/voltage characteristics obtainable from the Figure 1 circuit by biasing the drain terminal of the cells (both array and reference cells) at about 1 V (linear operating region) and assuming a boost voltage V B is used to increase the voltage V GS between the gate and source terminals of cell 4 with respect to supply voltage V CC . In Figure 2, I R indicates the I/V characteristic of the reference cell with a fixed, known threshold voltage V TR ; I TC indicates the characteristic of the worst erased array cell with the maximum permissible threshold voltage V TC (2.5 V with the above specifications); I TCN indicates characteristic I TC amplified by the Figure 1 configuration; I TCNB indicates characteristic I TCN in the presence of bootstrap voltage V B - by which it is shifted by V B towards the origin - and therefore presenting a threshold voltage of (V TC - V B ); I TW indicates the characteristic of the worst written array cell with the minimum permissible threshold voltage V TW ; I TWN indicates characteristic I TW amplified by the Figure 1 configuration; and I TWNB indicates characteristic I TWN in the presence of bootstrap voltage and with a threshold voltage of (V TW - V B ). As shown clearly in Figure 2, the intersection of characteristics I R and I TCNB determines the minimum supply voltage V 1 , and that of characteristics I R and I TWNB the maximum supply voltage V 2 , i.e. the voltages below and above which reading (recognition of erased and written cells respectively) is not possible. Voltages V 1 and V 2 may be determined analytically, bearing in mind that: I R = G*(V-V TR ) I TC = G*(V-V TC ) I TCN = N*I TC = N*G*(V-V TC ) I TW = G*(V-V TW ) I TWN = N*I TW = N*G*(V-V TW ) I TCNB = N*G*(V-V TC +V B ) I TWNB = N*G*(V-V TW +V B ) where G is the slope of the nonamplified characteristics. By equaling relation (1) to (2) and relation (1) to (3), the following voltages are obtained: V 1 = (N*V TC -N*V B -V TR )/(N-1) V 2 = (N*V TW -N*V B -V TR )/(N-1) For example, if V TC = 2.5 V, V TW = 4.5 V, V TR = 1.25 V, V B = 0.8 V and N = 8, then V 1 = 1.76 V and V 2 = 4 V. As such, though the above solution provides for reading memory cells even when the minimum supply voltage is low, the maximum permissible supply voltage is also low. For also reading memory cells with a high maximum supply voltage, but without at the same time increasing the minimum supply voltage, according to a further co-pending patent application (EP-0814482 A) entitled "Method and circuit for generating a read reference signal for nonvolatile memory cells" and incorporated herein by way of reference, the reference characteristic comprises two segments with different slopes. In read circuits of the type considered, to speed up reading in the presence of a low supply voltage, an equalizing network is used to connect nodes 16 and 17 and bring them to the same voltage before they are read. Since it depends, however, on various parameters, and in view of the unbalanced loads involved, the actual voltage level reached by nodes 16 and 17 cannot be established accurately beforehand, and, in the event of an unbalanced voltage level, reading may be commenced erroneously before eventually reaching the correct value, thus resulting in such a time loss as to at least partly reduce the theoretic advantage of the equalizing function. IEEE INTERNATIONAL SOLID STATE CIRCUITS CONFERENCE, vol. 24, February 1991, NEW YORK US, pages 264-265, XP000238333 SWEHA ET AL: "A 29ns 8Mb EPROM with dual reference-column ATD sensing" describes an EPROM having a differential amplifier, the complementary inputs whereof are precharged using identical biasing currents. US-A-4 725 984 describes another known EPROM sensing device. It is an object of the present invention to provide a method and an equalizing circuit designed to solve the above problem and permit rapid reading even at low supply voltage. According to the present invention, there are provided a read method and circuit for non volatile memory cells, with an equalizing structure, as claimed respectively in Claims 1 and 3. A preferred, non-limiting embodiment of the present invention will be described by way of example with reference to the accompanying drawings, in which: Figure 1 shows an electric diagram of a read circuit as described in the aforementioned first co-pending patent application; Figure 2 shows the characteristics obtainable from the Figure 1 circuit; Figure 3 shows the characteristics obtainable from the aforementioned second co-pending patent application; Figures 4a, 4b and 4c show how to obtain the reference characteristic in Figure 3; Figure 5 shows an electric diagram of the circuit for generating the reference characteristic in Figure 3; Figure 6 shows an equivalent diagram of a variation of a detail in Figure 5; Figure 7 shows an electric diagram of a known equalizing circuit as applied to the Figure 1 circuit; Figure 8 shows an electric diagram of one embodiment of the equalizing circuit according to the present invention; Figure 9 shows a comparative graph of a number of electric quantities in the Figure 7 and 8 diagrams. For a clearer understanding of the present invention, a description will first be given of the reference signal generating circuit according to the aforementioned second co-pending patent application. In Figure 3, characteristics I TCNB , I TWNB , I R and threshold voltages V TR , (V TC - V B ), (V TW - V B ) have the same meaning as in Figure 2, whereas the reference characteristic is indicated I R1 . As can be seen, the reference characteristic, generated by the reference branch of the array, comprises two segments: a first segment coinciding with the first portion of characteristic I R in Figure 2 up to a trigger voltage V S ; and a second segment coinciding with a characteristic I SN presenting a threshold voltage V A between (V TC - V B ) and (V TW - V B ) and a slope N*G. The fact that the first part of characteristic I R1 coincides with I R permits the same minimum value V 1 of supply voltage V CC to be maintained, while at the same time ensuring a high current difference between the array and reference branches and enhancing dynamic performance. The second segment with a steeper slope parallel to that of the amplified array characteristic, on the other hand, provides for eliminating the maximum limit posed on the supply voltage. In selecting value V S marking the change in the slope of characteristic I R1 , a trade-off must be made between the minimum permissible threshold value for the written cells and the current value required at low supply voltage to conform with the specified access time (since a low supply voltage corresponds with a low current value and hence slow charging and discharging of capacitive nodes). With the threshold voltages indicated above, for example, a V S value of 3 V may be selected. Characteristic I R1 may be obtained as shown in Figures 4a, 4b and 4c from characteristic I R with threshold voltage V TR and from characteristic I S with threshold voltage V S and the same slope as characteristic I R ; and characteristic I S may be obtained either by appropriately regulating the threshold voltage of a special reference cell appropriately located in the memory device (outside array 5), or by adding two thresholds as explained in detail later on. To obtain characteristic I R1 , first of all a difference characteristic I D = I R - I S equal to the difference between characteristics I S and I R is obtained; a characteristic I SN (Figure 4b) is obtained by amplifying characteristic I S with a current mirror similar to that forming I/V converter 9; and, finally, characteristics I D and I SN are added to give characteristic I R1 as shown in Figure 4c. A generating circuit capable of generating the above characteristic I R1 is shown in Figure 5 and described below. The generating circuit, indicated by 20 in Figure 5, comprises two floating-gate type (e.g. flash) memory cells 21, 22, both with threshold voltage V TR . More specifically, cell 21 has the source terminal and bulk region grounded, the gate terminal connected to a node 24, and the drain terminal connected to a node 26 via a protection circuit 25 (to prevent phenomena such as soft writing); node 24 is grounded via a diode-connected NMOS transistor 28 (drain and gate terminals shorted and connected to node 24) and is connected to supply line 15 via two PMOS transistors 29, 30; transistor 29 is also diode-connected (drain and gate terminals shorted and connected to node 24); transistor 30 has the source terminal and bulk region connected to supply line 15, and the gate terminal connected to an input 31 supplied with an active-when-low inverted enabling signal ENN; and an NMOS transistor 32 has the drain terminal connected to node 24, the source terminal grounded, and the gate terminal connected to input 31 to ground node 24 in standby mode and so avoid consumption. Protection circuit 25 comprises an NMOS transistor 33 interposed between the drain terminal of cell 21 and node 26; and a NOR gate 34 having a first input connected to the drain terminal of cell 21, a second input connected to input 31, and the output connected to the gate terminal of transistor 33, so that, when signal ENN is low, NOR gate 34 controls the power-on level of transistor 33 in known manner, and (by means of a negative feedback) maintains the drain terminal of cell 21 at the desired biasing voltage (typically 1 V). Conversely, when high, signal ENN forces the output of NOR gate 34 to switch to low, thus turning off transistor 33 and cutting off the connection between node 26 and cell 21. A diode-connected PMOS load transistor 35 has the source terminal connected to supply line 15, the gate and drain terminals connected to node 26, and a width/length ratio W/L = K, and is so connected as to form a current mirror with a PMOS load transistor 36 and with a PMOS transistor 37; transistor 36 has the source terminal connected to supply line 15, the gate terminal connected to node 26, the drain terminal connected to a node 38, and a width/length ratio W/L = K equal to that of load transistor 35; and, via a protection circuit 39 identical to circuit 25 and therefore not described in detail, node 38 is connected to the drain terminal of cell 22, which has the gate terminal connected to supply line 15, and the source terminal and bulk region grounded. Node 38 is also connected to the drain terminal of a diode-connected PMOS transistor 40, which has the gate terminal also connected to node 38, the source terminal connected to supply line 15, a width/length ratio W/L = K equal to that of load transistors 35 and 36, and forms a current mirror circuit with a PMOS transistor 44 also presenting a width/length ratio W/L = K. Transistors 37 and 44, the gate terminals of which are connected respectively to nodes 26 and 38, have the source terminals connected to supply line 15, and the drain terminals connected to a node 45; transistor 37 presents a width/length ratio W/L = N*K N times greater than that of transistor 35 with which it is connected to form a current mirror; transistor 44 presents a width/length ratio W/L = K equal to that of transistor 40 with which it is connected to form a current mirror; and, via a protection circuit 46 identical to circuit 25 and therefore not described in detail, node 45 is connected to the drain terminal of a diode-connected native NMOS transistor 48 (i.e. with a low threshold voltage unaltered during fabrication). More specifically, native transistor 48 has the source terminal grounded, and the gate terminal forming a node 50 and connected to the drain terminal. Transistor 48 forms a 1:1 current mirror circuit with one or more native NMOS transistors (one indicated by 51 in Figure 5) connected to reference bit lines 8 of the various read circuits of the memory; and K1 in Figure 5 indicates the width/length ratio of transistors 48 and 51, which is identical for both. For a clearer understanding of the connection of generating circuit 20 to read circuit 1, Figure 5 also shows current/voltage converter 9, decoding, biasing and equalizing circuit 10, and memory cell 4 of Figure 1. The Figure 5 circuit operates as follows. When signal ENN is low (circuit 20 enabled), transistor 30 is turned on and connects diode-connected transistor 29 to supply line 15; transistor 32 is turned off; and the outputs of the NOR gates of protection circuits 25, 39 and 44 are not forced to zero, so that the voltage at node 24 is somewhere between supply voltage V CC and ground, depending on the sizing of diode-connected transistors 28, 29. More specifically, if V P is the threshold voltage of diode-connected transistor 29, equal to the minimum source-gate voltage drop for transistor 29 to be turned on, and by so sizing transistors 28, 29 that transistor 28 is much more resistive than transistor 29 and, hence, the difference between supply voltage V CC and threshold voltage V P of transistor 29 falls entirely on diode-connected transistor 28, then cell 21 has a gate-soource voltage drop V GS of V CC - V P . In which case, and bearing in mind that cell 21 presents a threshold voltage of V TR , cell 21 remains off as long as supply voltage V CC is less than the sum of threshold voltage V TR of cell 21 and voltage drop V P . Above this supply voltage value, cell 21 starts conducting current, controlled by voltage V GS , and therefore functions as a cell with a threshold voltage V S of V TR + V P . From the above, it is clear that the current controlled by cell 21 and flowing in load transistor 35 equals current I S in Figure 4a. Since transistor 36 forms a 1:1 mirror with transistor 35, the current flowing through transistor 36 is equal to I S ; the current in transistor 37 equals N*I S , due to the width/length ratio of transistor 37 being N times greater than that of load transistor 35, and therefore corresponds to current I SN in Figure 4b. Due to the gate terminal of cell 22 being connected directly to the supply line, the current flowing in cell 22 equals I R , so that the current flowing in transistor 40, equal to the difference between current I R imposed by cell 22 and current I S supplied by transistor 36, equals current I D in Figure 4b; current I D is mirrored by transistor 44 and supplied to node 45 together with current I SN supplied by transistor 37; and native transistor 48 therefore receives and transfers current I R1 in Figure 4c to reference bit line 5 via transistor(s) 51. Current I R1 so generated may therefore be transferred easily to the rest of the memory device using only one reference circuit 20 for all the device outputs. As an alternative to the Figure 5 arrangement, memory cells 21 and 22 may be located outside memory array 5. More specifically, in the Figure 6 example, a small, e.g. 8x8, cell array 53 is formed, and cells 21, 22 are selected from among the innermost cells to reduce the edge effects, and may therefore be written or erased in known manner during final EWS (Electrical Wafer Sort) testing of the device. Being able to adjust the threshold voltage of cells 21, 22 in an independent way to the most appropriate value, the gate terminal of cell 21 may be connected directly to the supply line like cell 22, thus eliminating transistors 28-30 and directly setting the threshold voltage of cell 21 to the desired V S value. The advantage of this solution lies in the threshold voltage of characteristic I S (which, as is known, varies with temperature) depending solely on the variations of one component (cell 21 itself) instead of those of two components (cell 21 and transistor 29 in the Figure 5 embodiment), so that the temperature performance of current I S is substantially the same as that of the other quantities generated by the other components of the device (cell 22 included). Moreover, the above solution also provides for using only two reference cells for the whole memory device. Circuit 20 therefore permits read circuit 1 in Figure 1 to be operated at both low and high supply voltage V CC (the maximum supply voltage is theoretically infinite) without penalizing either limit. Moreover, it is simple, reliable, and presents zero consumption in standby mode. When read circuit 1 operates at low supply voltage, current flow in the circuit is low, but, on the other hand, the time taken to charge and discharge the capacitive nodes is increased, thus slowing down the read operation. One known solution to speed up reading of the cell is to use an equalizing network to connect nodes 16 and 17 and bring them to the same voltage at the ATD (Address Transition Detection) step, in which the addresses of the memory cells switch (high ATD pulse signal) before they are read. More specifically, in Figure 7, circuit 10 in Figure 1 is shown divided into a known equalizing circuit 55 and a known decoding and biasing circuit 56 (not shown in detail). Equalizing circuit 55 substantially comprises a pair of transistors 60, 61 connected between supply line 15 and respective nodes 16, 17; and a connecting transistor 62 connected between nodes 16 and 17. More specifically, transistors 60-62 are native (low-threshold) NMOS transistors; PMOS protection transistors 64 and 65 are located between supply line 15 and respective transistors 60 and 61; and both transistors 64, 65 have the gate terminals grounded so that they are always turned on, and provide for protecting respective native transistors 60, 61 from voltage peaks on supply line 15. The gate terminals of transistors 60, 61, 62 are all supplied with signal ATD so that, in the time interval in which signal ATD is high, they are turned on and bring nodes 16 and 17 to a voltage substantially equal to the high voltage of signal ATD (e.g. 3 V) less a threshold voltage (voltage drop V GS between the gate and source terminals). At the end of the ATD pulse, therefore, nodes 16 and 17 are at the same voltage, so that they are brought more rapidly to the voltage compatible with the erased or written state of the array cell to be read. The actual (equalizing) voltage reached by nodes 16 and 17 at the equalizing step, however, depends on various parameters, such as temperature and current flow in the two branches, and, there being no possibility of establishing it accurately beforehand, may be too low or too high, thus impairing the effect of the equalizing function on read time. If the equalizing voltage is too high (high voltage at nodes 16, 17), erased cell reading is slow. More specifically, with too high an equalizing voltage, load transistors 12, 13 forming I/V converter 9 may be turned off (insufficient source-gate voltage drop), so that, when equalizing transistors 60-62 are turned off at the end of the equalizing step, there is no current flow in load transistor 13 (which is still turned off), whereas reference cell 7 is turned on and drawing current. As such, nodes 16 and 17 function as if the array cell 4 to be read were written, even when in actual fact it is erased, so that, when reading an erased cell, the sense amplifier first supplies a wrong reading, which, though later corrected when converter 9 is turned on, results in a certain loss of time and hence an increase in read time. Conversely, if the set equalizing voltage is too low, nodes 16 and 17 are brought to too low a voltage, so that written cell reading is slow. That is, the control voltage (source-gate voltage drop) of load transistors 12, 13 is so high as to bring nodes 16 and 17 to a voltage corresponding to an erased cell 4, even when in actual fact it is written. In the case of a written memory cell 4, a wrong initial setting of this sort is further compounded initially by the parasitic capacitances associated with bit line 6 (which must rise from the previous excessively low voltage to the correct level) absorbing current, which, albeit small, is amplified by converter 9 and interpreted at node 17 as being due to an erased cell. In the case of a written cell and too low an equalizing voltage, before the circuit reaches the correct condition, the above two effects combined cause the sense amplifier to supply a reading corresponding to an erased cell 4 and which, though corrected later, also means the correct reading is only obtained some time after the end of the ATD pulse. For solving this problem, provision is made for an adaptive equalizing network for automatically setting the equalizing voltage of nodes 16 and 17 at an intermediate point corresponding to a balanced condition of the array and reference branches, i.e. the current required by reference bit line 8 equals the current supplied by I/V converter 9. The above condition is balanced in the sense that it is exactly halfway between the written cell read condition (current demand by reference branch 3 greater than that - ideally zero- supplied by array branch 2 via load 13) and the erased cell read condition (current supply by load 13 greater than the current demand of reference branch 3), so that the circuit is in an excellent condition to be unbalanced one way or the other at the end of the ATD pulse, depending on the state of array cell 4. To achieve the above balanced condition, despite the unbalance due to the difference in the sizing of load transistors 12 and 13, provision is made, as shown in Figure 8, for a grounding current path connected to the array branch, which is active at the equalizing step and provides for the same but opposite current unbalance as that produced by I/V converter 9. More specifically, in Figure 8, circuit 10 in Figure 1 is shown divided into its three components: known equalizing circuit 55; biasing circuit 71 (similar to circuits 25, 39, 46 in Figure 5) for preventing soft writing; and decoding circuit 72. A node 74 is provided between biasing circuit 71 and decoding circuit 72; a balancing branch 75 is provided between node 74 and ground to define a grounding path, and comprises an NMOS selection transistor 76 and a native NMOS balancing transistor 77; selection transistor 76 has the drain terminal connected to node 74, the gate terminal supplied with signal ATD, and the source terminal connected to the drain terminal of balancing transistor 77; and balancing transistor 77 has the source terminal grounded, and the gate terminal connected to node 50 of generating circuit 20 in Figure 5. In practice, like transistor 51 connected to reference bit line 8, balancing transistor 77 is connected to form a current mirror with transistor 48 of circuit 20, but presents a width/length ratio N times smaller than transistor 51, i.e. equal to K1/N. At the equalizing step, when signal ATD is high and equalizing network 55 is active, balancing branch 75 is therefore also active, and balancing transistor 77 draws a current I B N times smaller than current I R1 drawn by transistor 51; current I B , supplied by load transistor 12 of I/V converter 9, is mirrored, multiplied N times, by load transistor 13, so that it equals current I R1 drawn by transistor 51; the read circuit is therefore balanced, with nodes 16 and 17 at a voltage halfway between those corresponding to a written and erased cell, so that the load transistors are neither turned on nor off excessively; thus, when, at the end of the ATD pulse, transistors 60, 61, 62 and 76 are turned off (disabling equalizing network 55 and balancing branch 75), the read circuit is ready to detect the actual state of cell 4 to be read, with none of the delays due to spurious initial switching, as described above. To show the read speed obtainable by virtue of balancing branch 75, Figure 9 shows the difference in the voltage behavior at reference node 17 using the Figure 7 and 8 circuits and relative to an erased array cell 4. In Figure 9, V 16 indicates the voltage at node 16; V 17 the voltage at node 17 in both the Figure 7 and 8 circuits; V 17 ' the voltage at node 17 in the Figure 7 circuit; and V 17 " the voltage at node 17 in the Figure 8 circuit. As shown, in the presence of the ATD pulse, voltage V 17 equals V 16 in both circuits. At the end of the ATD pulse, on the other hand, voltage V 17 ' in the Figure 7 circuit falls for a given time below V 16 , thus causing a wrong initial reading, and requires additional read time to reach the correct (high) value; whereas voltage V 17 " in the Figure 8 circuit reaches the correct voltage much more quickly, thus supplying a correct reading immediately and so greatly reducing read time as compared with the Figure 7 circuit. As such, low-voltage dynamic performance of the read circuit is enhanced and comparable with that obtainable at high voltage and hence high current. Clearly, changes may be made to the method and circuit as described and illustrated herein without, however, departing from the scope of the present invention. In particular, the equalizing circuit may also be applied to read circuits with the loads unbalanced in the opposite way to that described and/or featuring single-slope reference signals, and any of the elements may be replaced by technical equivalents.

Claims: In a nonvolatile memory cell read circuit comprising a current mirror circuit (9) in turn comprising a first and second load transistor (12, 13) interposed between a first reference potential line (15) and a respective first (16) and second (17) output node, said first load transistor (12) having a first dimensional parameter, said second load transistor (13) having a second dimensional parameter, said first and second dimensional parameters being the width-to-length ratio of the first and respectively, the second load transistors; said second and first dimensional parameters defining a ratio of N where N is a predetermined number, said second output node (17) being connected to a reference generating circuit (20, 51) generating a reference current (I R1 ) having a predetermined characteristic, and said first output node (16) being connected to at least one memory cell (4) to be read; and an equalizing circuit (55) connected to said first and second output nodes, an equalizing method comprising the step of temporarily biasing said first and second output nodes (16, 17) at an equal voltage value, characterized in that , during said temporary biasing step, an equalizing current (I B ) is generated, flowing between said first output node (16) and a second reference potential line; said equalizing current and said reference current presenting a ratio of 1/N by wirthe of said first and second dimensional parameters being different. A method as claimed in Claim 1, characterized in that N is a number greater than one. A nonvolatile memory device comprising at least one memory cell and a read circuit comprising: a first current mirror circuit (9) comprising a first and second load transistor (12, 13) interposed between a first reference potential line (15) and a respective first (16) and second (17) output node, said first load transistor (12) having a first dimensional parameter, said second load transistor (13) having a second dimensional parameter, said second and first dimensional parameters being the width-to-length ratio of the first and, respectively, the second load transistors, being mutually different and defining a ratio of N where N is a predetermined number; said first output node (16) being connected to at least one memory cell (4) to be read, and said second output node (17) being connected to a reference generating stage (20, 51) generating a reference current (I R1 ) having a predetermined characteristic; and an equalizing circuit (55) connected to said output nodes; characterized in that said equalizing circuit comprises a current balancing branch (75) connected between said first output node (16) and a second reference potential line and generating an equalizing current (I B ); said equalizing current and said reference current presenting a ratio of 1/N. A circuit as claimed in Claim 3, characterized in that said reference generating stage presents a control node (50) connected to control terminals of a first and second transistor element (77, 51); said first transistor element (77) being connected between said first output node (16) and said second reference potential line; and said second transistor element (51) being connected between said second output node (17) and said second reference potential line. A device as claimed in Claim 4, characterized in that said first and second transistor elements (77, 51) comprise a native MOS transistor. A device as claimed in Claim 4 or 5, characterized by a controlled switching element (76) interposed between said first transistor element (77) and said first output node (16) and having a control terminal receiving an equalization enabling signal (ATD). A device as claimed in one of the foregoing Claims from 4 to 6, characterized in that said reference generating stage (20, 51) comprises at least one reference memory cell (22) generating a reference cell signal (I R ) having a predetermined characteristic, and a connecting circuit (40, 37, 48, 51, 77) comprising at least one second current mirror circuit (40, 37) having a first and second reference node (38, 45) connected respectively to said reference memory cell (22) and to a third transistor element (48) forming a fourth current mirror circuit with said first and second transistor elements (77, 51). A device as claimed in any one of Claims 4 to 7, characterized in that said first and second load transistors (12, 13) are MOS transistors of a first channel type; in that said dimensional parameter comprises the channel width/length ratio; and in that said first and second transistor elements (77, 51) each comprise a MOS transistor of a second channel type; said second transistor element (51) having a dimensional ratio equal to a predetermined number K1; and said first transistor element (77) presenting a dimensional ratio of K1/N. A device as claimed in Claim 8, characterized in that said first load transistor (12) is diode-connected, and said number N is a number greater than one.

Inventors: CAMPARDO GIOVANNI, MACCARRONE MARCO, MICHELONI RINO, CAMPARDO, GIOVANNI, MACCARRONE, MARCO, MICHELONI, RINO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1996
Main classification: G11C16
IPC codes: G11C16