Digital signal processing circuit for a television receiver

Abstract: Digital signal processing circuit for a television receiver comprising: a first field memory for storing input data representative of the chrominance or luminance portion of one field; first interpolation means for generating interpolated line data based on line data received from said first field memory; zooming and up-conversion control means for controlling the read-out of line data from said first field memory and the interpolation performed by said interpolation means based on a zoom factor input to said zooming and up-conversion control means.

Description: The present invention relates to a digital signal processing circuit for a television receiver, which circuit supports up-conversion and digital zooming. Zooming in this context means to expand a picture, or a portion of a picture, by adding additional lines to the picture, said lines being generated according to interpolation techniques. Zooming may, in particular, be used to convert a picture transmitted in the letterbox format, into a picture covering the whole screen. In regard to up-conversion there are currently two, common, approaches. One is the so-called 100/120 Hz interlaced scanning approach, the other is the so-called 50/60 Hz progressive scan conversion approach. Figures 1b and 1c illustrate the principle of these two techniques, whereas Figure 1a illustrates traditional 50/60 Hz interlaced scanning. According to traditional 50/60 Hz interlaced scanning, every picture (frame) is divided into two fields, one field comprising the odd lines of the complete frame, the other field comprising even lines of the complete frame. The two fields A and B, forming together a full frame, are displayed at successive times, which is illustrated in Figure 1 by the field sequence A,B,A,.... The 100/120 Hz interlaced scanning technique differs from the traditional 50/60 Hz interlaced scanning in that four timely successive fields are displayed during one frame period. In the simplest form, this can be achieved by field repetition leading to field sequence of A,A,B,B,.... Such simple repetition of the fields reduces only the large area flicker, the line flicker is the same or even increased compared with a normal 50/60 Hz interlaced display. A second form is achieved by frame repetition leading to field sequence A,B,A,B,.... This method leads to acceptable results in case of pictures that are practically without motion (still picture). In order to enhance the picture quality achievable with 100/120 Hz interlaced scanning, it is proposed that motion adaptive filtering is used, in that generation of additional fields is performed, dependent on the amount of motion contained in the picture. This is illustrated in Figure 1b, by the sequence AA*,BB*....If motion is existent, fields A and B are not merely repeated, but the additional fields A*, B* are generated, dependent on the amount of motion present in the picture. Figure 1c illustrates the 50/60 Hz progressive scanning technique. According to this technique, to each field A,B, the respective missing odd or even lines are added, so that two interlaced fields, A/A*, B*/B, are simultaneously displayed. From EP-A2-0 514 819 a television receiver is known which has mode setting means for setting a display mode and further aspect ratio converting means. The aspect ratio converting means is set to one of a plurality of conversion modes or display magnification modes in accordance with the output signal from said mode setting means. Said aspect ratio converting means converts a video signal of a non-wide aspect ratio into a signal of a wide aspect ratio suitable for being displayed on a wide aspect ratio screen. The interpolation is carried out using a field memory and a line memory, two coefficient multipliers and an adder. The field memory receives a video signal and puts out the delayed video signal. The line memory receives and delays the video signal outputted by said field memory. The video signals outputted by said field memory and said line memory are weighted by said coefficient multipliers according to predetermined coefficients, respectively. Finally, both weighted signals are added in order to provide an interpolated video signal. It is the object of the present invention to provide a digital signal processing circuit for a television receiver, which circuit combines up-conversion processing with zooming processing, whereby the circuit may be realised using relatively simple hardware. This object is solved by the subject matter of present claim 1. Preferred embodiments of the present invention are the subject matter of the dependent claims to claim 1. In the following a preferred embodiment of the present invention is described in detail, in connection with the accompanying drawings, which show: Fig. 1a-c illustrations for describing traditional 50/60 Hz interlaced scanning, 100/120 Hz interlaced scanning and 50/60 Hz progressive scanning, Fig. 2 a schematic diagram of a circuit combining up-conversion-, zooming- and panning-capabilities, Fig. 3 a schematic diagram of a circuit combining motion dependent up-conversion-, zooming- and panning-capabilities, and Figs 4 & 5 diagrams for illustrating the operation of the phase accumulation means. The circuit according to Figure 2 basically comprises three main units, namely a field memory 1, a filter unit 2 and a control unit 3. Field memory 1, which is preferably a field RAM, stores one field of an incoming video signal, whereby the video signal comprises only luminance or chrominance signals of the incoming video signal, or both. Filter unit 2 is preferably a so-called FIR-filter and most preferably a 2-tap FIR-filter. The filter unit comprises a line memory 4, adder means 5 and 6, and a multiplier 7. As will be understood by those skilled in the art, if filter unit 2 is a 2-tap-filter, as illustrated in Figure 2, the filter operation may be mathematically expressed as follows: Y = kX o +(1-k)X -1 , whereby X 0 represents a current line, X -1 represents a line succeeding the current line and y represents the output of the filter unit. Factor k is applied by control unit 3 and, as is apparent from the above formula, determines the ratio by which a current line and the adjacent succeeding line are mixed to provide an interpolated line. If there is no zooming, no additional lines to the lines already stored in field memory have to be generated, and so factor k can be selected with a value of 0 in order not to change the lines provided by field memory 1. If there is zooming the generation of additional lines is necessary. For example, to expand a picture received in the letterbox format, to a format matching the full size of the screen, it is necessary to generate additional lines by interpolating lines adjacent to the active part of the picture. Control unit 3 is preferably a so-called phase accumulator unit, basically comprising a line address counter 8, an adder means 9 and a delay or register means 10. Since control unit 3 addresses, via line address counter 8, field memory 1, and simultaneously supplies factor k to multiplier 7 of filter unit 2, it controls which of the lines stored in field memory 1 are interpolated with each other, and according to which ratio. As shown in Figure 2, controller unit 3 preferably comprises adder means 9 receiving at a first input an initial value or a zoom factor and, at a second input, the low 6 bits (0..5) output of register means 10. Register means 10 coupled to the output of the adder means 9 delays the input from adder means 9 by a time period corresponding to one line. Adder means 9 is preferably a seven bit adder and thus provides a seven bit word to register means 10. The seven bit output from register means 10 is split, in that the most significant bit is applied to line address counter 8, and the lower 6 bits (0..5) are applied to multiplier 7, of filter unit 2. These lower 6 bits are also applied to one of the inputs of the adder. The phase accumulation means 3 is executed every output line. The physical distance between two lines of the input field is divided into 64 steps. Theoretically it is possible to generate at every step position an output line by interpolation. If a zooming factor from one to two is realised then, at maximum, two of these new interpolated output lines are required. Therefore, there is no need to generate a line at all 64 steps. The output of control unit means 3 can be described by the following mathematical formulae: k 0 = INIT mod 64 k n = (k n-1 + comp) mod 64 (n = 1,2,3,...) la 0 = INIT div 64 la n = la n + (k n-1 + comp) div 64 (n = 1,2,3,...) where: INIT = initial value, which depends on the field (A1,A1*,B1* or B1) generated k = value given to multiplier means 7 (bit 0..5) k 0 = k-factor for the first output line (line No. 0) la = output of line address counter n = output line number to be generated (n = 1,2...) comp = compression factor (32...64) mod = modulo operation (rest of division) div = division operation (integer result of division) The following example illustrates the above given formulae: The output field is A1 and the compression factor is 50. This means that only 78% of the incoming picture is displayed (50/64 = 0.78; with an initial value for A1=64). In Figure 4, the generation of output field A1 with n=0 and n=1 is shown. The output field is A1* and the compression factor is 50. For output field A1* the initial value is (64 + comp/2) = 89. Figure 3 geometrically indicates a preferred embodiment of a circuit according to the present invention, combining motion adaptive up-conversion-, zooming- and panning-capabilities. The circuit shown in Figure 3 comprises a field memory 1' and a filter unit 2', which basically provide the same function as units 1 and 2 of Figure 2. Unit 2 is preferably the 2-tap FIR-filter for intra-field interpolation, which result is used in case of motion. The circuit of Figure 3 further comprises a control unit 11 controlling the addressing of field memory 1' and filter unit 2', similar to control unit 3 in Figure 2. The circuit of Figure 3 additionally comprises a further field memory 12 and a further filter unit 13. Unit 13 is preferably a 3-tap FIR-filter for intra-frame interpolation, which is used in case of no motion or slow motion. Preferably one coefficient of the 3-tap filter is always set to zero. Therefore, the 3-tap filter can be realised by a 2-tap FIR-filter with multiplexers means 17 and 18, which are described below. Briefly explained, filter unit 13 performs a similar filter operation to that of filter unit 2' based however, on different input signals. Control unit 11 controls both, filter unit 2' and filter unit 13. Mixer unit 14 combines the output of filter unit 2' and the output of filter unit 13 and outputs, through normalisation unit 19, the resultant video signal. The operation of mixer unit 14 is controlled by a motion signal supplied from a motion detection unit (not shown). Basically, mixer 14 passes the output from filter unit 13 to its output if there is no motion, and passes the output signal from filter unit 2' to its output if there is maximum motion. In the case of intermediate motion values, mixer 14 combines the outputs of filter units 2' and 13. As shown in Figure 3, control unit 11 applies a control signal to filter unit 2' and filter unit 13. These control signals are preferably supplied to multiplier 15 and multiplier 16 respectively. The phase accumulation means 11 is executed for every output line. The physical distance between two lines of the output field is divided into 128 steps. Theoretically, it is possible to generate at every step position an output line by interpolation. If a zooming factor from one to two is realised then, at maximum, in 100/120 Hz mode two, and in 50/60 Hz mode, four of these new interpolated output lines are required. Therefore, there is no need to generate a line at all 128 steps. The output of control unit means 11 can be described by the following mathematical formulae: 6 Bit Adder and Reg: km 0 = INIT/2 mod 64 km n = (k n-1 + comp/2)mod 64 (n = 1,2,3,...) 8 Bit Adder and Reg: temp 0 = INIT mod 128 temp n = (temp n-1 + comp)mod 128 (n = 1,2,3,...) knm n = temp n mod 64 (n = 0,1,2,3,...) mux n = temp n div 64 (n = 0,1,2,3,...) la 0 = INIT div 128 la n = la n-1 + (k n-1 + comp) div 128 (n = 1,2,3,..) where: INIT = initial value, which depends on the field to be generated (A1,A1*,B1* or B1) km = value given to multiplier means 15 (bit 0..5) km 0 = k-factor for multiplier means 15 of the first output line temp = temporal variable knm = value given to multiplier means 16 (bit 0..5) mux = mux_ctrl, signal to control multiplexers means 17 and 18 la = output of line address counter n = output line number to be generated (n=0,1,2..) comp = compression factor (64,68,72...128) mod = modulo operation (rest of division) div = division operation (integer result of division) The output of the line address counter is given to the field memory means 1. The address, which is given to field memory means 12 can differ by one line, dependent of the field (A1,A1*,B1* or B1) to be generated. The two multiplexers (17, 18) are controlled by a mux_ctrl signal. If the mux_ctrl signal is "0" then the output of the line memory means 2 and the output of the field memory means 12 is applied to the filter means 13. If the mux_ctrl signal is "1" then the output of the field memory means 1 and the output of the line memory means 2 is applied to the filter means 13. The following example may illustrate the above given formulae. If output field is A1 and the compression factor is 100, only 78% of the incoming picture is displayed (since 100/64 = 0.78 with an initial value for A1 = 128) The output field is A1* and the compression factor is 100. For output field A1* the initial value is (128+comp/2)=178. Figure 5 illustrates the generation of output field A1 with n=0 and n=1. In the second column the output of the 2-tap filter means is shown and in the third column the output of the 3-tap filter means 13 is shown. As mentioned, the circuit according to Figure 3 combines up-conversion capabilities with zooming and panning capabilities. Thereby the circuit according to Fig. 3 is able to perform interlaced scan conversion and progressive scan conversion. The principle operation of the circuit shown in Figure 3 for different situations, i.e. as interlaced scanning or progressive scanning, zooming or no zooming, motion or no motion (still), will be explained in connection with the following Tables 1 and 2. Table 1 concerns the operation of the circuit with regard to interlaced scanning and in particular for 100/120 Hz interlaced scan conversion. As mentioned above, in the case of interlace scanning, the amount of fields is doubled, in that during the time period of a field A1 of an incoming video signal, two fields A1, A1* are generated and displayed. In the case of no zooming and no motion (still) in the picture, sub-field A1 is identical to incoming field A1 and sub-field A1* is identical to the previous incoming field BO (situation 2). In the case of no zooming, but with motion, sub-field A1 is identical to incoming field A1, the lines of sub-field A1* are however, generated by interpolating adjacent lines of incoming field A1. This is indicated in Table 1 by the expression A1,A1LD, whereby LD designates "line delay" (situation 1). In the case of zooming and motion, the lines of both sub-fields A1 and A1* are generated by interpolating respective adjacent lines of incoming field A1 (situation 3). In the final case of Table 1, a situation with zooming and no motion (still) (situation 4), lines of sub-fields A1 and A1* are generated by interpolating adjacent lines of incoming field A1 and lines of previous field B0. Although explained in more detail herein below, it should be mentioned that interpolation between lines of adjacent incoming fields A1 and B0 is achieved by the operation of multiplexer 17 and 18 of filter unit 13. Table 2 illustrates the situation in the case of progressive scan conversion. As mentioned above, in the case of progressive scan conversion, each incoming field is, by interpolation, expanded into a frame whereby all lines of the resultant frame are displayed during the same field period. Table 2 shows the manner in which individual lines of frames A1/A1* and B1*/B1 are generated for the mentioned four different situations. In case of 100/120 Hz interlaced scan conversion and output field A1 and A1*, the output data of field memory means 1 is data of input field A1 and the output data of the line memory means 2 is input field A1 one line delayed. The output of field memory means 12 is the input field B0. Thus, the input of the 2-tap filter means 2 is input field A1 and input field A1 one line delayed (A1LD). One coefficient of the 3-tap filter is preferably always set to zero, in that it can be realised by a 2-tap filter with multiplexers. In case of output field B1* and B1, the output data of field memory means 1 is data of input field B1 and the output data of the line memory means 2 is input field B1 one line delayed. The output of field memory means 12 is input field A1. Thus, the input of the 2-tap filter means 2 is input field B1 and input field B1 one line delayed (B1LD). The input of the 3-tap filter means 13 is input field B1 and B1LD and the input field A1. One coefficient of the 3-tap filter is preferably always set to zero, in that it can be realised by a 2-tap filter with multiplexers.

Claims: Digital signal processing circuit for a television receiver comprising: a first field memory (1') for storing input data representative of the chrominance or luminance portion of one field, first interpolation means (2') for generating interpolated line data based on line data received from said first field memory (1'), zooming and up-conversion control means (11) for controlling the read-out of line data from said first field memory (1') and the interpolation performed by said interpolation means based on a zoom factor input to said zooming and up-conversion control means (11), characterised in that said digital signal processing circuit further comprises: a second field memory (12), a second interpolation means (13) and a mixer means (14), wherein, said second field memory (12) is coupled to the output of the first field memory (1'), said second interpolation means (13) receives as a first input the output of the second field memory (12), as a second input the output of the first field memory (1') and as a third input a one-line delayed version of the output of the first field memory and generates, based on either the first and second or the first and third inputs, interpolated line data, said mixer means (14) receives the output data from the first and the second interpolation means (2', 13) and generates output data based on the two inputs and based on a motion signal supplied by a motion detection unit. Digital signal processing circuit according to claim 1, wherein said first interpolation means (2') is a FIR-filter, preferably a 2-tap FIR-filter. Digital signal processing circuit according to claim 1 or 2, wherein said second interpolation means (13) is a FIR-filter and preferably a 2-tap FIR-filter. Digital signal processing circuit according to claim 2 or 3, wherein said FIR-filter comprises weighting means (7, 16) which are controlled by said zooming and up-conversion control means (11). Digital signal processing circuit according to claim 3 or 4 wherein said FIR-filter of said second interpolation means (13) comprises multiplexer means (17, 18) for passing either the first and second or first and third input to the FIR-filter. Digital signal processing circuit according to one of the claims 1 to 5, wherein said zooming and up-conversion means (11) controls the weighting operation performed within the first interpolation means (2') and the weighting operation performed by the second interpolation means (13) and further controls the switching of the multiplexer (17, 18) contained in the second interpolation means (13). Digital signal processing circuit according to one of the preceding claims, wherein said interpolation means (2') comprises at least one line memory for outputting a one-line delayed version of the current line data output from the first field memory (1'). Digital signal processing circuit according to one of the claims 1 to 7, wherein the third input to the second interpolation means (13) is provided by a line delay means comprised in the first interpolation means (2'). Digital signal processing circuit according to one of the preceding claims, wherein said zooming and up-conversion control means (11) determines the first line data to be read out from the first field memory (1') in accordance with a received active area signal so that only relevant line data is supplied to the interpolation means (2'). Digital signal processing circuit according to one of the preceding claims, wherein said zooming and up-conversion control means (11) comprises adder means (9), line delay means (10) and line address counter means (8), wherein said adder means (9) receives said zoom factor as a first input and provides output data to said line delay means (10), said line delay means (10) provides output data to said interpolation means (2'), 13) and to said adder means (9) as a second input thereof, said line address counter (8) receives the MSB from the output of the line delay means (10) and controls by its output the read-out of the first field memory (1'). Digital signal processing circuit according to claim 10, wherein said adder means (9) is a 7-bit adder and said line delay means (10) provides the six lower bits of its output to the second input of the adder means (9) and to the interpolation means (2', 13) and provides the most significant bit of its output to said line address counter means (8).

Inventors: GEISSEL MICHAEL, HINRICHS TIMM, SCHU MARKUS, SINGER ROLF, GEISSEL, MICHAEL, HINRICHS, TIMM, SCHU, MARKUS, SINGER, ROLF
Applicants: MATSUSHITA ELECTRIC IND CO LTD, MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Application year: 1996
Main classification: H04N5
IPC codes: H04N5