Self-aligned etching process to realize word lines of semiconductor integrated memory devices

Abstract: The process proposed allows provision of a matrix topography for electronic memory devices using self-alignment etchings capable of removing those spurious electrical contacts between adjacent memory cells. The self-aligned etching process proposed for providing a plurality of mutually parallel word lines in a first conducting layer (11,12) deposited over a planarized architecture (9) obtained starting from a semiconductor substrate (1) on which is provided a plurality of active elements extending along separate parallel lines e.g. memory cell bit lines (13) and comprising gate regions formed by a first conducting layer (4), a dielectric interpoly layer (5) and a second conducting layer (6) with said regions being insulated from each other by dielectric insulation films(7,8) to form said architecture (9) with said word lines being defined photolithographically by protective strips is implemented by means of: a vertical profile etching for complete removal from the unprotected areas respectively of the first conducting layer (11,12), of the second conducting layer (6) of the gate region, a successive etching of the dielectric interpoly layer (5) accompanied by a considerable erosion of the dielectric film (8) of the insulation region so as to totally uncover the first conducting layer (4), and a concluding etching of the first conducting layer (4).

Description: Field of application The present invention relates to a self-aligned etching process for providing word lines and improving the reliability of electronic memory devices integrated on semiconductor substrates displaying a topography of the matrix type comprising word lines and bit lines. Specifically the present invention relates to a self-aligned etching process for providing a plurality of parallel word lines in a conducting layer deposited over a planarized architecture obtained starting from a semiconductor substrate on which a plurality of active elements is provided extending along separate parallel lines e.g. bit lines including memory cell comprising gate regions formed by a first conducting layer, an interpoly dielectric layer and a second conducting layer, said regions being insulated from each other by at least one insulation region to form this architecture including said word lines being defined photolithographically by protective strips. The present invention also relates to a memory device with matrix configuration of the cross-point type and comprising bit lines and word lines. The present invention concerns specifically but not exclusively a self-aligned etching process for providing word lines in memories integrated on contactless semiconductor and with virtual ground circuitry. The following description is given with reference to this specific field of application with the only purpose of simplifying its explanation. Prior art As is well known, EPROM or FLASH-EPROM electronic memory devices require the provision on a semiconductor substrate of a matrix-type topography in which a plurality of bit lines having a floating gate region is intersected above by a plurality of conducting strips properly called word lines. A topography of this type is shown in the photograph of FIG 1 obtained by electronic microscopy techniques. The practical provision of this matrix-type topography is not entirely without problems and shortcomings because it was verified experimentally that it is possible that the floating gate regions find themselves contacted by spurious residues of conducting materials not entirely removed during manufacturing. In the following description given by way of example there are again proposed the process steps necessary for defining on a semiconductor substrate a matrix-type topography of an EPROM memory device comprising word lines, bit lines and floating gate regions to better clarify those aspects necessary for defining the technical problem. Starting from a semiconductor substrate 1, e.g. like that shown in FIG 2 in which there is already a division into active areas with the possible presence of a field oxide dividing layer 2, multiple depositions are made over the entire surface of the substrate. First a thin gate oxide layer 3 is deposited. Then a deposition of a first polysilicon layer 4, identified by the name POLY1, is provided followed by the deposition of a second dielectric interpoly layer 5, e.g. ONO, which is encapsulated above by another deposition of a third, polysilicon, layer 6 which is identified by the name POLYCAP. At this point a masked photolithography step which for convenience is identified by the name 'POLY1 mask' defines the topography of the gate regions and related bit lines. A cascade self-aligned etching allows removal of parallel strips of multiply layers until reaching the active areas of the substrate 1. This cascade etching removes from the unprotected areas of the photolithography the POLYCAP layer 6, the ONO layer 5, the POLY1 layer 4, the gate oxide layer 3 and the field oxide 2 if necessary where present. This defines a spatial geometry on the semiconductor substrate 1 in which it is possible to recognize a plurality of active elements extending along separate parallel lines, e.g. memory cell bit lines 13 and corresponding gate regions. The gate regions 13 are formed as shown in FIG 2 by the stratified structure of POLYCAP - ONO - POLY1 - gate oxide and possibly field oxide, as shown in figure 2. During performance of this self-aligned etching, removal of the POLYCAP layer 6 causes deposition of polymers which create a pair of steps or ribs 10 on the underlying POLY1 layer 4 which thus projects laterally with respect to the layers deposited above as shown in FIGS 2 and 4. Another cause which could be at the origin of the formation of this pair of steps 10 is generally an additional oxidation step usually used for sealing the bit lines 13. During this oxidation step the POLYCAP layer 6 can reoxidize more than the POLY1 layer 4 (depending on the type of doping of the POLY1) as shown in FIG 2. The above mentioned step 10 made up of the POLY1 layer 4 projecting laterally can originate a short circuit between adjacent floating gate regions once a self-aligned etching has been completed to define word lines and hence individual memory cells. FIG 3 shows an electronic microscope photograph of a semiconductor substrate having a matrix-type topography after performance of a self-aligned etching to define the word lines, which can be identified in the high-luminosity areas which are united by thin white strips revealing the presence of the steps 10. The successive process steps for the provision of an EPROM memory device call for the use of a planarization method in which a first insulating dielectric film 8 and a second planarizing dielectric film 7 deposited in the interstitial regions included between the gate regions 13 allow obtaining a planarized architecture 9 as shown in FIG 2. It is important to note that the above described process causes the first insulating dielectric film 8 to act as a protective micromask for the step 10 created previously. Provision of the plurality of word lines intersecting the gate regions 13 calls for deposition of a conducting layer entirely covering the planarized architecture 9 as shown in FIG 4. This conducting layer can be obtained by means of successive deposition of a protective layer 12, e.g. of polysilicon and indicated for convenience by the name POLY2, and a final layer 11 of silicide, e.g. tungsten silicide. To define the spatial geometry of the word lines again use has been made of a conventional photolithography step with an appropriate mask usually indicated as a POLY2 mask designating unprotected areas in which a self-aligned etching can be performed even for the word lines. Another objective of this etching is to mutually insulate the individual memory cells by removing material from the floating gate regions not protected by the photolithography step. Those skilled in the art usually perform this self-aligned etching in two successive steps and with a vertical profile. The first step calls for removal of the conducting layer 11, 12 and the underlying POLYCAP layer 6 while the second step calls for removal of the ONO layer 5 and POLY1 layer 4. FIG 5 shows a vertical cross section of an electronic memory devices comprising gate regions 13 planarized by means of insulation regions 7 and 8 after performance of the first self-aligned etching step for definition of the word lines and memory cells. This cross section was taken in a region included between two consecutive word lines in which erosion takes place due to the first self-aligned etching step. In this figure it can readily be seen that the insulation regions 7 and 8 are only partially etched because the dielectric layer 5 at the end of this etching is still protected by the insulating dielectric film 8. It is accordingly clear that the step zone 10 is still present. The second self-aligned etching step, which is diagrammed in the cross section of FIG 6A only for removal of the dielectric layer 5, is insufficient to eliminate the steps 10 if done with a vertical profile. The final removal of the POLY1 layer 4 with a vertical profile etching is insufficient to remove the step zone 10 because of the persistence of the micromask. The prior art process described up to this point has provided on the semiconductor substrate 1 a matrix topography comprising gate regions, corresponding bit lines 13 and word lines orthogonal thereto. This topography is widely used in EPROM or E 2 PROM memory devices and in particular in EPROM, Flash EPROM and EEPROM memory devices having a cross-point and virtual ground structure as described e.g. in European Patent no. 0 573 728. Although meeting the purpose, there are some critical aspects of the above described process which require a remedy. In particular it is desired to place the accent on the existence of the pair of steps 10 present in the floating gate regions associated with each bit line 13 between the POLYCAP layer 6 and the underlying layers. As mentioned, these steps can originate undesired contacts which can affect the reliability of the memory device. In addition, the usual self-aligned etchings having a vertical profile for definition of the word lines as well as for insulation of the individual memory cells are quite inadequate for removing said steps 10 as may be seen in FIGS 3, 5 and 6A. Indeed, it happens that, after removal of the ONO layer 5 and POLY1 layer 4 the pairs of steps 10 still remain present because protected by the micromask created by the first dielectric insulation film 8 used for planarization of the architecture 9. In this manner the floating gate regions of adjacent memory cells made by means of self-aligned etching of the word lines come into mutual electrical contact. The technical problem underlying the present invention is to conceive a self-aligned etching process for definition of geometry associated with word lines which would allow overcoming the above mentioned shortcomings which still limit the reliability of the memory devices provided in accordance with the prior art. European Patent no. 0 677 869 discloses a planarized architecture including memory cells, but does not mention the problem of stringers or remnants of POLY1 between adjacent cells when forming the word lines. Another prior art document, U.S. Patent no. 5,342,801, deals with stepped structures and eliminates the stringers with an etching process different from the one of the present invention. Summary of the invention The solution idea underlying the present invention is that of using for definition of the word lines and individual memory cells a self-aligned etching with a vertical profile limited to removal of the conducting layer 11, 12 and the underlying POLYCAP layer 6. Advantageously the present invention provides that removal of the ONO dielectric layer 5 be accompanied by a considerable erosion of the insulating dielectric film 8 so as to eliminate the protective micromask of the steps 10. Subsequent removal of the POLY1 layer 4 then permits mutual insulation of the individual memory cells to avoid that the steps 10 not be removed because protected by the micromask. On the basis of this solution idea the technical problem is solved by a process of the type indicated above and defined in claim 1. The characteristics and advantages of the process in accordance with the present invention are set forth in the description of an embodiment thereof given below by way of non-limiting example with reference to the annexed drawings. Brief description of the drawings FIG 1 shows an electronic microscope photograph of a plurality of Flash EPROM memory cells having a matrix-type topography of which can be seen only the bit lines before deposition of a dielectric layer, FIG 2 shows diagrammatically and in enlarged scale a vertical cross section of a semiconductor electronic device with a planarized architecture comprising gate regions conformed as a stratified POLYCAP - ONO - POLY1 - gate oxide structure, FIG 3 shows an electronic microscope photograph of a semiconductor substrate having a matrix-type topography and taken after performance of a self-aligned etching for definition of the word lines, FIG 4 shows schematically and in enlarged scale a vertical cross section of a semiconductor electronic device with a planarized architecture covered above by a conducting layer provided in accordance with the prior art, FIG 5 shows schematically and in enlarged scale a vertical cross section of a semiconductor electronic device comprising gate regions conformed as a stratified ONO - POLY1 structure and insulation regions after provision of a first self-aligned etching step for definition of the word lines in accordance with the prior art, FIG 6A shows schematically and in enlarged scale a vertical cross section of a semiconductor electronic device comprising gate regions conformed as a stratified POLY1 field oxide structure and insulation regions after provision of a second self-aligned etching step for removal of the ONO layer and definition of the word lines in accordance with the prior art, and FIG 6B shows schematically and in enlarged scale a vertical cross section of a semiconductor electronic device comprising gate regions conformed as a stratified POLY1 field oxide structure and insulation regions after provision of a second step of self-aligned etching for removal of the ONO layer and definition of the word lines in accordance with the present invention. Detailed description With reference to FIGS 4, 5, 6A and 6B there is now described a self-aligned etching process for providing a plurality of mutually parallel word lines in a first conducting layer formed by a pair of superimposed layers 11, 12. FIG 4 shows the layers 11, 12 deposited over a planarized architecture 9 obtained starting from a semiconductor substrate 1 on which a plurality of active elements is provided extending along separated parallel lines, e.g. bit lines of memory cells. This figure is an enlarged vertical cross section of the above described device having planarized architecture 9 obtained in a region delimited by two word lines in which is performed the self-aligned etching. In this region are present an optional field oxide layer 2, a thin gate oxide layer 3, a first conducting layer 4, a dielectric interpoly layer 5, e.g. ONO, and a second conducting layer 6. The gate regions are mutually insulated by an insulating dielectric film 8 and by a planarized dielectric film 7 forming said planarized architecture 9. The word lines are defined photolithographically by protective strips orthogonal to the bit lines. Advantageously in accordance with the present invention the etching for definition of the word line geometry and insulation of the individual memory cells is provided in two successive steps. In a first step there is provided the action of a self-aligned etching starting from the exposed surface of the additional conducting layer 11, 12. This etching proceeds with a vertical profile for removal of the conducting layer 11, 12 and of the underlying second conducting layer 6 from the gate regions 13 not protected by the photolithographic process. As mentioned above, a POLY2 mask is used for definition of the word lines in the photolithography step. FIG 5 shows an enlarged vertical cross section of the self-aligned etching region after removal of the conducting layers 11, 12 and the second conducting layer 6. This first etching step does not include elimination of the pairs of steps 10 because the dielectric films 7,8 used for the insulation region are only partially removed after the etching. Indeed, it can be seen that the dielectric interpoly layer 5 and the underlying first conducting layer 4 are still protected by the micromask of the dielectric film 8. Advantageously the present invention as shown in FIG 6B requires that the removal of the dielectric interpoly layer 5 is accompanied by a considerable erosion of the dielectric film 8 of the insulation region so as to eliminate the protective micromask of the steps 10. FIG 6B clearly shows how after the above described etching step the dielectric film 8 has a lower profile with respect to the first conducting layer 4. This is possible if an etching much longer than that normally used to remove e.g. 30 nm (300 Å) of oxide is used. An etching of this type allows removal of an oxide layer of a thickness comparable to the thickness of the POLY1. In addition this etching allows the removal of an oxide thickness over the POLY1 of approximately 80 nm (800 Å) For a complete definition of the word lines and individual memory cells one proceeds with a final etching step to eliminate the first POLY1 conducting layer 4. This final etching step is free to act over the entire surface of the layer 4 without any longer leaving the undesired steps 10 which were the cause of the spurious contacts between the gate regions of adjacent cells once the cells are defined with the self-aligned etching in accordance with the prior art. One of ordinary skill in the art will surely recognize in the process proposed here a solution to all those technical problems in which there is conducting material previously not removed because protected by undesired micromasks which can cause spurious contacts. It is noted in particular that the technical problem set forth above and concerning the possibility of spurious contacts between the floating gate regions associated with adjacent memory cells remains even when the profile of the vertical cross section of the gate regions 13 is the trapezoid type and not only in the presence of a step as described. In conclusion the self-aligned etching proposed by the present invention is capable of ensuring good reliability of the memory devices with matrix configuration if provided in accordance with the process steps described here.

Claims: Process for providing a plurality of mutually parallel word lines comprising the steps of: providing a plurality of memory cells on a semiconductor substrate (1), these cells extending along separate parallel bit lines and comprising gate regions formed by a first conducting layer (4), a dielectric interpoly layer (5) and a second conducting layer (6), said gate regions being insulated from each other by at least one dielectric insulation film (7,8) to form a planarized architecture (9); depositing a third conducting layer (11,12) over said planarized architecture (9); providing a plurality of mutually parallel word lines in said third conducting layer (11,12), wherein said word lines are defined photolithographically by protective strips; this process further comprising the following self-aligned etching steps: an etching with vertical profile for complete removal from the unprotected areas respectively of the third conducting layer (11,12), of the second conducting layer (6) of the gate region , and thereafter, an etching of the dielectric interpoly layer (5) and of the dielectric film (7, 8) of the insulation region in such a manner as to fully expose the upper surface and the sidewalls of the first conducting layer (4) of the gate region, and a final etching of the first conducting layer (4). Process in accordance with claim 1, characterized in that said third conducting layer (11,12) can be provided by means of successive deposition of a first (12) and a second (11) layer having different chemical composition. Process in accordance with claim 2, characterized in that said first layer (12) is made of polysilicon. Process in accordance with claim 2, characterized in that the second layer (11) is made of silicide. Process in accordance with claim 4, characterized in that the second layer (11) is made of tungsten silicide (WSi 2 ). Process in accordance with claim 1, characterized in that said first conducting layer (4) and said second conducting layer (6) making up the gate regions are made of polysilicon. Process in accordance with claim 1 and characterized in that said dielectric interpoly made of layer (5) is ONO.

Inventors: COLABELLA ELIO, PIVIDORI LUCA, REBORA ADRIANA, COLABELLA, ELIO, PIVIDORI, LUCA, REBORA, ADRIANA, Rebora, Adriana, SGS-Thomson Microelectronics Srl
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1996
Main classification: H01L21
IPC codes: H01L21, H01L29, H01L27