CELL DRIVING CIRCUIT FOR USE IN FIELD EMISSION DISPLAY

Abstract: A cell driving circuit of an FED, including: an electrode plate (10) connected to ground potential, for installing a plurality of cathodes (C11 to C44) which serve to emit electrons; two or more gate electrodes (G1 to G4) disposed in the upper portion of the cathodes (C11 to C44); two or more switching units (T1 to T4) for switching voltages to be applied to the two or more gate electrodes (G1 to G4); and a control unit (20) for driving the number of the two or more switching units (T1 to T4) corresponding to size of a video signal (VS) in accordance with the size of the video signal (VS).

Description: CELL DRIVING CIRCUIT FOR USE IN FIELD EMISSION DISPLAY TECHNICAL FIELD The present invention relates to a cathode ray tube (CRT) , and more particularly, to a cell driving circuit of a field emission display (hereinafter referred to as "FED") which can provide multi-level gradation to a picture element within a simplified circuit construction and can embody a simple manufacturing procesε. BACKGROUND ART Generally, cell driving circuits in FEDs have realized multi-level gradation by adjusting an amount of current flowing to cathodes of a plurality of field emission devices or by dividing driving time periods of the plurality of field emission devices. The cell driving circuit in the FED using the method of adjusting the amount of current should require a large number of transistors which serve to substantially adjust the amount of current, so that the circuit construction becomes very complicated. In addition, both a high voltage applied to gate electrodes and a low voltage needed to drive the transistors are used, so that the manufacturing process is more complex. On the other hand, the cell driving circuit in the FED using the method of dividing the driving time periods is disclosed in U.S. Patent No. 5,135,483, issued to Kishino. This patent teaches the cell driving circuit in the FED wherein time periods during current paths of cathodes are formed are adjusted by means of capacitors, thereby adjusting the amount of electrons emitted from the cathodes. The time taken during the charge, which is charged to the capacitors, is adjusted according to the size of the video signal. However, there is a problem in that the cell driving circuit using this method can not divide the cell driving time periods over a predetermined limit due to a restricted driving time period of a picture element. Accordingly, the cell driving circuit in the FED as disclosed in the U.S. Patent Publication No. 5,135,483 can not achieve a multi¬ level gradation over the predetermined limit. DISCLOSURE OF INVENTION Therefore, it is an object of the present invention to provide a cell driving circuit of an FED which can provide a multi-level gradation to a picture element within a simplified circuit construction and can embody a simple manufacturing process . To accomplish the object of the present invention, a cell driving circuit of an FED includes : an electrode plate connected to ground potential, for installing a plurality of cathodes which serve to emit electrons; two or more gate electrodes disposed in the upper portion of the cathodes; two or more switching units for switching voltages to be applied to the two or more gate electrodes; and a control unit for driving the number of the two or more switching units corresponding to size of a video signal in accordance with the size of the video signal. BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a circuit diagram illustrating a cell driving circuit of an FED constructed according to the principles of the present invention; and FIG. 2 is a graph illustrating the size of the amount of electrons emitted according to an operational signal outputted upon switching of transistors in FIG. 1. BEST MODE FOR CARRYING OUT THE INVENTION Referring to FIG. 1, a circuit diagram illustrating a cell driving circuit of an FED constr' ted according to the present invention is shown. In the nstruction, the cell driving circuit in the FED includes: 16 cathodes Cll to C44 installed in a rectangular direction on the upper surface of an electrode plate 10; a resistor Rl connected between the electrode plate 10 and ground potential GND; first to fourth gate electrodes GI to G4 arranged in a horizontal direction on the upper portion of the cathodes Cll to C44. The resistor Rl serves to limit the amount of current flowing into the cathodes Cll to C44. Each of the first to fourth gate electrodes GI to G4 includes gate holes . In more detail, the first gate electrode GI has the gate holes which expose a first row of cathodes Cll to C14 and in the case where a voltage is applied, connects the electrons emitted from the first row of cathodes Cll to C14. In a similar manner to the above, the second to fourth gate electrodes G2 to G4 respectively include gate holes which expose second to fourth cathodes C21 to C24, C31 to C34 and C41 to C44 and in the case where voltages are respectively applied, connect the electrons emitted from the second to fourth rows of cathodes C21 to C24, C31 to C34 and C41 to C44. Preferably, the cell driving circuit in the FED further includes: first to fourth NMOS transistors Tl to T4 for switching first to fourth voltages Vddl to Vdd4 to be supplied to the first to fourth gate electrodes GI to G4 ; and a control unit 20 for controlling the first to fourth NMOS transistors Tl to T4. The first to fourth voltages Vddl to Vdd4 may be set to have the same voltage level, but preferably should be set to have different voltage levels from each other so that the amount of electrons emitted from each row of cathodes is increased to 2 n times. The control unit 20 inputs a video signal VS and converts the video signal VS into 4-bit digital logic signals DO to D3 to provide the 4-bit digital logic signals DO to D3 as a valve control signal to gates of the first to fourth NMOS transistors Tl to T4 , respectively. The control unit 20 is comprised of an analog-digital converter or an encoder. The 4-bit digital logic signals DO to D3 have logic values "0 (0 0 0 0) " to "15 (1 1 1 1) " in accordance with the size of the video signal VS. Also, the 4-bit digital logic signals DO to D3 have logic values "0 (0 0 0 0) " to "4 (0 0 1 0) " in accordance with the size of video signal VS. However, to accomplish a high level of gradation, it is desirable to use the logic values "0 (0 0 0 0) " to "15 (1 1 1 1)". In the case that each of the 4-bit digital logic signals DO to D3 has a logic "high" level, it means it has data "1". Therefore, some or all of the 4-bit digital logic signals DO to D3 have the logic value of data "1", or all the 4-bit digital logic signals DO to D3 have the logic value of data "0" The first to fourth transistors Tl to T4 are selectively driven in accordance with logic values of the 4- bit digital logic signals DO to D3 applied to their gates. The first to fourth NMOS transistors Tl to T4 selectively drive the first to fourth gate electrodes GI to G4 , to linearly vary the amount of electrons emitted in accordance with the size of video signal VS, as shown in FIG. 2. FIG. 2 is a graph illustrating sizes of the amount of electrons emitted according to an operation signal outputted upon switching of the transistors in FIG 1. For instance, when the logic value of the 4-bit digital logic signals DO to D3 is "1 (DO Dl D2 D3. 1 0 0 0) " , only the first NMOS transistor Tl is turned on and thus the first voltage Vddl is supplied only to the first gate electrode GI . As a result, an amount of electrons I 1 is emitted from the first row of cathodes Cll to C14. Meanwhile, when the logic value of the 4-bit digital logic signals DO to D3 is "2 (DO Dl D2 D3 0 1 0 0) ", only the second NMOS transistor T2 is turned on and thus the second voltage Vdd2 is supplied only to the second gate electrode G2. As a result, an amount of electrons I ≥ is emitted from the second row of cathodes C21 to C24. Further, when the logic value of the 4-bit digital logic signals DO to D3 is "4 (DO Dl D2 D3 • 0 0 1 0) " , only the third NMOS transistor T3 is turned on and thus the third voltage Vdd3 is supplied only to the third gate electrode G3. As a result, an amount of electrons I 4 is emitted from the third row of cathodes C31 to C34. When the logic value of the 4-bit digital logic signals DO to D3 is "8 (DO Dl D2 D3. 0 0 0 1) ", only the fourth NMOS transistor T4 is turned on and thus the fourth voltage Vdd4 is supplied only to the fourth gate electrode G4 As a result, an amount of electrons I 8 is emitted from the fourth row of cathodes C41 to C44 Finally, when the logic value of the -bit digital logic signals DO to D3 is "15 (DO Dl D2 D3 : l l l l) ", all the first to fourth NMOS transistors Tl to T4 are turned on and thus the first to fourth voltage Vddl to Vdd4 are supplied to all the first to fourth gate electrodes GI to G4. As a result, an amount of electrons I 15 is emitted from the first to fourth rows of cathodes Cll to C44. As is apparent from the above, the present invention provides a cell driving circuit m an FED wherein a plurality of cathodes are connected to ground potential through an electrode plate, and two or more gate electrodes are selectively driven to provide a multi-level gradation to picture elements, thereby achieving a simplified circuit construction. Furthermore, the present invention provides a cell driving circuit in an FED having an advantage in that since transistors being driven by a single voltage to be applied to the gate electrodes are used, the manufacturing process is simple. Meanwhile, in the preferred embodiment of the present invention, four gate electrodes, as shown m FIG. 1, provide 16 grading levels of luminance, but it is obvious to those skilled m the art that a plurality of gate electrodes may provide several hundreds of grading levels of luminance for a picture element. Therefore, it should be understood that the present invention is not limited to the particular embodiment disclosed herein as the best mode contemplated for carrying out the present invention, but rather that the present invention is not limited to the specific embodiments described m this specification except as defined m the appended claims.

Claims: WHAT IS CLAIMED IS: 1. A cell driving circuit of a field emission display, comprising : an electrode plate connected to ground potential, for installing a plurality of cathodes which serve to emit electrons; two or more gate electrodes disposed in the upper portion of said cathodes; two or more switching units for switching voltages to be applied to said two or more gate electrodes; and a control unit for driving the number of said two or more switching units corresponding to size of a video signal in accordance with the size of said video signal. 2. The cell driving circuit as claimed in claim 1, wherein said two or more gate electrodes are set to be supplied with different voltage levels from each other, so that a grading level of 2 n times can be achieved. 3. The cell driving circuit as claimed in claim 1, further comprising a resistor connected between said electrode plate and said ground potential to thereby limit an amount of current flowing into said cathodes. 4. The cell driving circuit as claimed in claim 3, wherein said control unit is comprised of an encoder for generating a logic signal of at least two bits or more, said logic signal having a logic value sequentially increasing by one in accordance with the size of said video signal. 5. The cell driving circuit as claimed in claim 3 , wherein said control unit is comprised of an analog-digital converter for converting said video signal into a digital logic signal of at least two bits or more.

Inventors: HYUN CHANG HO, KWON OH KYONG, HYUN, CHANG, HO, KWON, OH, KYONG
Applicants: HYUN CHANG HO, KWON OH KYONG, ORION ELECTRIC CO LTD, HYUN, CHANG, HO, KWON, OH, KYONG, ORION ELECTRIC CO. LTD.
Application year: 1996
Main classification: H01J1
IPC codes: G09G3, H04N5