Digital phase-locked loop

Abstract: Using positive-phase or negative-phase clocks of phase count clock Pf 0 , a number M of multilevel quantized phase comparators output as values quantized in multiple levels the phase differences of output signals outputted from first and second N-stage frequency dividers wherein input clocks and output clocks, respectively, of a digital PLL have been N-stage frequency divided and moreover, divided into M groups. An adder adds this phase difference information and outputs advanced pulses or delayed pulses. An N1 counter counts up in response to advanced pulses and both outputs an increment pulse and undergoes setting to initial value N1 upon counting up to 2N1. In response to delayed pulses, the N1 counter counts down, and upon counting down to "0" both outputs a decrement pulse and undergoes setting to initial value N1.

Description: The present invention relates to a digital phase-locked loop (PLL) used in a cell decomposition circuit in an ATM or stuffing synchronization device. In a previously proposed digital PLL in which two N-stage frequency dividers are added to the first stage of a digital PLL, an input signal is inputted to an input of one N-stage frequency divider and the output signal of the digital PLL is inputted to an input of the other N-stage frequency divider, and following N-stage frequency division of each of the signals, the signals are inputted to a multilevel quantized phase comparator. Fig. 1 of the accompanying drawings is a block schematic diagram illustrating a previously proposed digital PLL. In the digital PLL shown in Fig. 1 an input clock F in and an output clock f out are inputted to first and second N-stage frequency dividers 11 and 12, respectively, and subjected to N-stage frequency division. Multilevel quantized phase comparator 13, which is driven by phase comparator clock Pf 0 , inputs the output clocks of N-stage frequency dividers 11 and 12 and outputs output phase error information (advanced pulses or delayed pulses) indicating the phase advance/phase delay of both output clocks. N1 counter 14 is a competitive counter which inputs the advanced pulses or delayed pulses, counts up in response to advanced pulses, and upon counting up to count value 2N 1 , both outputs an increment pulse and undergoes setting to initial value N 1 . N1 counter 14 counts down in response to delayed pulses, and upon counting down to "0," both outputs a decrement pulse and undergoes setting to initial value N 1 . Frequency regulator 15 is driven by the standard drive clock Rf 0 of the digital PLL, and clears one pulse from the pulse train of standard drive clock Rf 0 when one increment pulse is generated from N1 counter 14 and adds one pulse to the pulse train of standard drive clock Rf 0 when one decrement pulse is generated from N1 counter 14. R-stage frequency divider 16 effects R-stage frequency division upon the output of frequency regulator 15 and outputs the output clock f out of the digital PLL. In the above-described previously proposed digital PLL, however, because the input to multilevel quantized phase comparators is N-stage frequency divided by N-stage frequency dividers, phase comparison is effected 1/N times that of a case in which N-stage frequency dividers are not employed. In other words, the gain of the switching network is reduced to 1/N, phase error information obtained per second drops to an insufficient level, and unwanted jitter (variations in phase) is generated. Furthermore, if half-clock control is selected for controlling the frequency regulator of the digital PLL, there is the further drawback that half-clock phase error cannot be detected in the phase comparator because the sampling interval of phase error detection in the phase comparator is 1 clock. Features of a digital PLL to be described below as an example are that half-clock phase control carried out in a frequency regulator can be detected in a phase comparator, the gain of a switching network can be maintained and the occurrence of unwanted jitter can be minimised. In a particular arrangement to be described below, as an example, a digital PLL includes first N-stage frequency dividing means that N-stage frequency divides input clocks of a digital PLL and generates N clocks of a first phase, a second phase, ..., and an Nth phase synchronized to a first input clock, a second input clock, ..., and an Nth input clock, respectively, divides these N clocks into M groups (N>M), and outputs the result; second N-stage frequency dividing means that N-stage frequency divides output clocks of a digital PLL, generates N clocks of a first phase, a second phase, ..., and an Nth phase synchronized to a first output clock, a second output clock, ..., and an Nth output clock, respectively, divides these N clocks into M groups (N>M), and outputs the result; first multilevel quantized phase comparison means that inputs an arbitrary output signal of the first group of first N-stage frequency dividing means and an arbitrary output signal of the first group of second N-stage frequency dividing means and outputs the phase difference between the two signals as a value quantized in multiple levels; second multilevel quantized phase comparison means that inputs an arbitrary output signal of the second group of first N-stage frequency dividing means and an arbitrary output signal of the second group of second N-stage frequency dividing means and outputs the phase difference between the two signals as a value quantized in multiple levels; ...; and Mth multilevel quantized phase comparison means that inputs an arbitrary output signal of the Mth group of first N-stage frequency dividing means and an arbitrary output signal of the Mth group of second N-stage frequency dividing means and outputs the phase difference between the two signals as a value quantized in multiple levels; adding means that adds phase difference information outputted from the M multilevel quantized phase comparison means and outputs advanced pulses indicating phase advance or delayed pulses indicating phase delay; N1 counting means that is a competitive counter that inputs the advanced pulses or the delayed pulses, counts up in response to the advanced pulses and, upon counting up to count value 2N1, both outputs an increment pulse and undergoes setting to initial value N1; and that counts down in response to the delayed pulses, and, upon counting down to "0," both outputs a decrement pulse and undergoes setting to initial value N1; frequency regulating means that is driven by a standard drive clock of the digital PLL, eliminates one pulse from the pulse train of the standard drive clock when one increment pulse is generated from the N1 counting means, and adds one pulse to the pulse train of the standard drive clock when one decrement pulse is generated from the N1 counting means; and R-stage frequency dividing means that R-stage frequency divides the output of the frequency regulating means and outputs an output clock of the digital PLL; wherein, of the M multilevel quantized phase comparison means, multilevel quantized phase comparison means of odd ordinal numbers are driven by a phase count clock of positive phase and multilevel quantized phase comparison means of even ordinal numbers are driven by a phase count clock of negative phase. An N-order digital PLL within the scope of the appended claims includes the above-described digital PLL. Another digital PLL to be described below, as an example, includes first N-stage frequency dividing means that N-stage frequency divides input clocks of a digital PLL, generates N clocks of a first phase, a second phase, ..., and an Nth phase synchronized to a first input clock, a second input clock, ..., and an Nth input clock, respectively, divides these N clocks into M groups (N>M), and outputs the result; second N-stage frequency dividing means that N-stage frequency divides output clocks of a digital PLL, generates N clocks of a first phase, a second phase, ... and an Nth phase synchronized to a first output clock, a second output clock, ... and an Nth output clock, respectively, divides these N clocks into M groups (N>M), and outputs the result; first multilevel quantized phase comparison means that inputs an arbitrary output signal of the first group of first N-stage frequency dividing means and an arbitrary output signal of the first group of the second N-stage frequency dividing means and outputs the phase difference between the two signals in the form of advanced pulses indicating phase advance or delayed pulses indicating phase delay as a value quantized in multiple levels; second multilevel quantized phase comparison means that inputs an arbitrary output signal of the second group of first N-stage frequency dividing means and an arbitrary output signal of the second group of second N-stage frequency dividing means and outputs the phase difference between the two signals as a value quantized in multiple levels; ...; and Mth multilevel quantized phase comparison means that inputs an arbitrary output signal of the Mth group of first N-stage frequency dividing means and an arbitrary output signal of the Mth group of second N-stage frequency dividing means and outputs the phase difference between the two signals as a value quantized in multiple levels; N1 counting means which are competitive counters provided corresponding to each of the M multilevel quantized phase comparison means and which input the advanced pulses indicating phase advance or the delayed pulses indicating phase delay outputted by the respective multilevel quantized phase comparison means, count up in response to the advanced pulses and, upon counting up to count value 2N1, both output an increment pulse and undergo setting to initial value N1; and that count down in response to the delayed pulses, and, upon counting down to "0," both output a decrement pulse and undergo setting to initial value N1; adding means that adds increment pulses or decrement pulses of the M N1 counting means and outputs pulses of advanced phase or delayed phase; frequency regulating means that is driven by a standard drive clock of the digital PLL, eliminates one pulse from the pulse train of the standard drive clock when. one pulse of advanced phase is generated from the adding means, and adds one pulse to the pulse train of the standard drive clock when one pulse of delayed phase is generated from the adding means; and R-stage frequency dividing means that R-stage frequency divides the output of the frequency regulating means and outputs an output clock of the digital PLL; wherein, of the M multilevel quantized phase comparison means, multilevel quantized phase comparison means of odd ordinal numbers are driven by a phase count clock of positive phase and multilevel quantized phase comparison means of even ordinal numbers are driven by a phase count clock of negative phase. An N-order digital PLL within the scope of the appended claims includes the above described another digital PLL. By employing multiple multilevel quantized phase comparison means, the phase error information obtained in one second can be increased M-fold and the system gain can be increased M-fold. Moreover, generated phase jitter can be reduced because accurate phase error information can be obtained. The following description and drawings disclose, by means of examples, the invention which is characterised in the appended claims, whose terms determine the extent of the protection conferred hereby. In the drawings:- Fig. 2 is a block schematic diagram of one embodiment of a digital PLL, Fig. 3 is a waveform chart illustrating the operation of the one embodiment of a digital PLL, Fig. 4 is a block schematic diagram showing an N-order digital PLL including the one embodiment of a digital PLL, Fig. 5 is a block schematic diagram showing a second embodiment of a digital PLL, and Fig. 6 is a block schematic diagram showing an N-order digital PLL including the second embodiment of a digital PLL. Referring to Fig. 2, there is shown a digital PLL which includes a first N-stage frequency divider 1, a second N-stage frequency divider 2, M multilevel quantized phase comparators 3-1 to 3-M, an adder 4, an N1 counter 5, a frequency regulator 6, and an R-stage frequency divider 7. First N-stage frequency divider 1 N-stage frequency divides input clock f in of the digital PLL, generates first phase, second phase, ..., and Nth phase clocks synchronized with the first input clock, the second input clock, ..., and the Nth input clock, respectively, divides these N clocks into M groups (N>M), and outputs the result. Second N-stage frequency divider 2 N-stage frequency divides output clock f out of the digital PLL, generates first phase, second phase, ..., and Nth phase clocks synchronized with the first output clock, the second output clock, ..., and the Nth output clock, respectively, divides these N clocks into M groups (N>M), and outputs the result. Multilevel quantized phase comparator 3-1 inputs an arbitrary output signal of the first group of first N-stage frequency divider 1 and an arbitrary output signal of the first group of second N-stage frequency divider 2 and outputs the phase difference between the two output signals as a value quantized in multiple levels. Multilevel quantized phase comparator 3-2 inputs an arbitrary output signal of the second group of first N-stage frequency divider 1 and an arbitrary output signal of the second group of second N-stage frequency divider 2 and outputs the phase difference between the two output signals as a value quantized in multiple levels. Multilevel quantized phase comparator 3-M inputs an arbitrary output signal of the Mth group of first N-stage frequency divider 1 and an arbitrary output signal of the Mth group of second N-stage frequency divider 2 and outputs the phase difference between the two output signals as a value quantized in multiple levels. Here, multilevel quantized phase comparators of odd ordinal numbers count input phase differences at the rising edge of phase comparison (sampling) clock Pf 0 , and multilevel quantized phase comparators of even ordinal numbers count input phase difference at the rising edge of sampling clock Pf 0 of negative phase. By using sampling clocks of both positive phase and negative phase in this way, sampling accuracy can be doubled as compared with using only a positive-phase sampling clock, and half-clock phase difference can be detected. Adder 4 adds the phase difference information outputted from the M multilevel quantized phase comparators 3-1 to 3-M and outputs advanced pulses indicating phase advance and delayed pulses indicating phase delay. When input is of differing phase (increment and decrement), a value for the difference can be obtained. N1 counter 5 is a competitive counter that inputs advanced pulses or delayed pulses, counts up in response to advanced pulses, and upon counting up to a count value 2N1 (a positive integer), both outputs an increment pulse and undergoes setting to initial value N1. In response to delayed pulses, N1 counter 5 counts down, and upon counting down to "0," both outputs a decrement pulse and undergoes setting to initial value N1. Frequency regulator 6 is driven by standard drive clocks Rf 0 of the digital PLL, eliminates one pulse from the pulse train of standard drive clock Rf 0 when one increment pulse is generated from N1 counter 5, and adds one pulse to the pulse train of standard drive clocks Rf 0 when one decrement pulse is generated from N1 counter 5. R-stage frequency divider 7 R-stage frequency divides the output of frequency regulator 6, and outputs an output clock f out of the digital PLL. Here, R is a positive integer, any value being selectable. When the value of R is small, the phase jitter generated by addition and elimination of pulses increases, and when R is set to a large value, jitter can be decreased. In addition, the values of R, N, and N 1 are each independent. Fig. 3 is a waveform chart illustrating the operation of the digital PLL of Fig. 2. Fig. 3A shows the output waveform after dividing the waveform of standard drive clock Rf 0 in a case where no control is performed. Fig. 3B shows the addition of 1 pulse to R-stage frequency dividing standard drive clock Rf 0 in a case where pulse addition is effected, and the output waveform after R-stage frequency division. By adding pulses in this way, output frequency following R-stage frequency dividing can be set to a high level. Fig. 3C shows the elimination of 1 pulse from R-stage frequency dividing standard drive clock Rf 0 in a case where pulse elimination is performed, and the output waveform after R-stage frequency division. By eliminating pulses in this way, output frequency following R-stage frequency division can be set to a low level. As described hereinabove, phase can be pulled in by adding or eliminating pulses in frequency regulator 6. The generation of this addition and elimination of pulses is performed as the automatic control loop of the overall system. In other words, a phase locked loop is formed. Fig. 4 is a block schematic diagram of an N-order digital PLL including the digital PLL of Fig. 2. This N-order digital PLL is made up of first N-stage frequency divider 1, second N-stage frequency divider 2, multilevel quantized phase comparators 3-1, 3-2, ..., and 3-M, N1 counter 5, N2 counter 10-1, N3 counter 10-2, ..., and NN counter 10-(N-1), frequency regulator 6, R-stage frequency divider 7, Q 1 counter 8-1, Q 2 counter 8-2, ..., and Q N-1 counter 8-(N-1) that store the center frequencies of N2 counter 10-1, N3 counter 10-2, ..., and NN counter 10-(N-1), respectively, and rate multiplier 9-1, rate multiplier 9-2, ..., and rate multiplier 9-(N-1) that generate increment pulses or decrement pulses appropriate to the center frequency of the system. A complete second-order digital PLL construction is described in Electronic Information Communications Conference Papers (B-I, Vol. J73-B-I No. 8 pp. 650-659. August 1990) also published as "A Digital Phase-Locked Loop for Stuffing Synchronization Systems" in "Electronics and Communications in Japan", Part I - Communications, vol. 75, no. 4, 1 April 1992, New York, US, and as the operation of the N-order digital PLL of the present invention can be easily inferred from this publication, further explanation will be omitted here. Referring to Fig. 5, there is shown a digital PLL which includes the provision, in the embodiment of Fig. 2, of N1 counters 5-1, 5-2, ..., and 5-M immediately after counters 5-1, 5-2, ..., and 5-M immediately after multilevel quantized phase comparators 3-1, 3-2, ..., and 3-M, respectively, and providing adder 4' immediately after N1 counter 5-1, 5-2, ..., and 5-M. N1 counters 5-1, 5-2, ..., and 5-M are competitive counters that input either advanced pulses indicating phase advance or delayed pulses indicating phase delay which are outputted by the corresponding multilevel quantized phase comparators 3-1, 3-2, ..., and 3-M, count up in response to the advanced pulses, and upon counting up to 2N1, both output an increment pulse and undergo setting to initial value N1. In response to the delayed pulses, the N1 counters 5-1, 5-2, ..., and 5-M count down, and upon counting down to "0," both output a decrement pulse and undergo setting to initial value N1. Adder 4 adds the increment pulses or decrement pulses of the M N1 counters 5-1 to 5-M and output pulses of an advanced phase or a delayed phase. The operation of this embodiment is otherwise similar to that of Fig. 2. Fig. 6 is a block schematic diagram showing an N-order digital PLL that includes the digital PLL of Fig. 5.

Claims: A digital Phase-Locked Loop (PLL) including first N-stage frequency dividing means (1) that N-stage frequency divides input clocks of a digital PLL and generates N clocks of a first phase, a second phase, ..., and an Nth phase synchronized to a first input clock, a second input clock, ..., and an Nth input clock, respectively, divides these N clocks into M groups (N>M), and outputs the result; second N-stage frequency dividing means (2) that N-stage frequency divides output clocks of a digital PLL, generates N clocks of a first phase, a second phase, ..., and an Nth phase synchronized to a first output clock, a second output clock, ..., and an Nth output clock, respectively, divides these N clocks into M groups (N>M), and outputs the result; first multilevel quantized phase comparison means (3-1) that inputs an arbitrary output signal of a first group of first N-stage frequency dividing means (1) and an arbitrary output signal of a first group of second N-stage frequency dividing means (2) and outputs the phase difference between the two signals as a value quantized in multiple levels, second multilevel quantized phase comparison means (3-2) that inputs an arbitrary output signal of a second group of first N-stage frequency dividing means (1) and an arbitrary output signal of a second group of second N-stage frequency dividing means (2) and outputs phase difference between the two signals as value quantized in multiple levels, ..., and Mth multilevel quantized phase comparison means that inputs an arbitrary output signal of an Mth group of first N-stage frequency dividing means (1) and an arbitrary output signal of an Mth group of second N-stage frequency dividing means (2) and outputs phase difference between the two signals as a value quantized in multiple levels; adding means (4) that adds phase difference information outputted from the M multilevel quantized phase comparison means (3-1...3-M) and outputs advanced pulses indicating phase advance or delayed pulses indicating phase delay; N1 counting means (5) that is a competitive counter that inputs said advanced pulses or said delayed pulses, counts up in response to said advanced pulses and, upon counting up to count value 2N1, both outputs an increment pulse and undergoes setting to initial value N1; and that counts down in response to said delayed pulses, and, upon counting down to "0," both outputs a decrement pulse and undergoes setting to initial value N1; frequency regulating means (6) that is driven by a standard drive clock (Rfo) of the digital PLL, eliminates one pulse from the pulse train of said standard drive clock (Rfo) when one increment pulse is generated from said N1 counting means (5), and adds one pulse to the pulse train of said standard drive clock (Rfo) when one decrement pulse is generated from said N1 counting means (5); and R-stage frequency dividing means (7) that R-stage frequency divides output of said frequency regulating means (6) and outputs an output clock of the digital PLL; wherein, of said M multilevel quantized phase comparison means (3-1...3-M), multilevel quantized phase comparison means of odd ordinal numbers are driven by a phase count clock of positive phase and multilevel quantized phase comparison means of even ordinal numbers are driven by a phase count clock of negative phase. An N-order digital PLL including a digital PLL according to claim 1. A digital PLL including first N-stage frequency dividing means (1) that N-stage frequency divides input clocks of a digital PLL, generates N clocks of a first phase, a second phase, ..., and an Nth phase synchronized to a first input clock, a second input clock, ..., and an Nth input clock, respectively, divides these N clocks into M groups (N>M), and outputs the result; second N-stage frequency dividing means (2) that N-stage frequency divides output clocks of a digital PLL, generates N clocks of a first phase, a second phase, ..., and an Nth phase synchronized to a first output clock, a second output clock, ..., and an Nth output clock, respectively, divides these N clocks into M groups (N>M), and outputs the result; first multilevel quantized phase comparison means (3-1) that inputs an arbitrary output signal of a first group of first N-stage frequency dividing means (1) and an arbitrary output signal of a first group of the second N-stage frequency dividing means (2) and outputs phase difference between the two signals in the form of advanced pulses indicating phase advance or delayed pulses indicating phase delay as a value quantized in multiple levels; second multilevel quantized phase comparison means (3-2) that inputs an arbitrary output signal of a second group of first N-stage frequency dividing means (1) and an arbitrary output signal of a second group of first N-stage frequency dividing means (2) and output phase difference between the two signals as a value quantized in multiple levels; ...; and Mth multilevel quantized phase comparison means (3M) that inputs an arbitrary output signal of an Mth group of first N-stage frequency dividing means (1) and an arbitrary output signal of an Mth group of second group of second N-stage frequency dividing means (2) and outputs phase difference between the two signals as a value quantized in multiple levels; N1 counting means (5-1, 5-2 ... 5-M) which are competitive counters provided corresponding to each of said M multilevel quantized phase comparison means (3-1, 3-2 ... 3-M) and which input the advanced pulses indicating phase advance or the delayed pulses indicating phase delay outputted by the respective multilevel quantized phase comparison means (3-1, 3-2 ...3-M), count up in response to said advanced pulses and, upon counting up to count value 2N1, both output an increment pulse and undergo setting to initial value N1; and that count down in response to said delayed pulses, and, upon counting down to "0," both output a decrement pulse and undergo setting to initial value N1; adding means (4) that adds increment pulses or decrement pulses of said M N1 counting means (5-1, 5-2 ... 5-M), and outputs pulses of advanced phase or delayed phase; frequency regulating means (6) that is driven by a standard drive clock (Rfo) of the digital PLL, eliminates one pulse from the pulse train of said standard drive clock when one pulse of advanced phase is generated from said adding means (4), and adds one pulse to the pulse train of said standard drive clock when one pulse of delayed phase is generated from said adding means; and R-stage frequency dividing means (7) that R-stage frequency divides the output of said frequency regulating means (6) and outputs an output clock of the digital PLL; wherein, of said M multilevel quantized phase comparison means (3-1, 3-2 ... 3-M), multilevel quantized phase comparison means of odd ordinal numbers are driven by a phase count clock of positive phase and multilevel quantized phase comparison means of even ordinal numbers are driven by a phase count clock of negative phase. An N-order digital PLL including a digital PLL according to claim 3.

Inventors: ROKUGO YOSHINORI, ROKUGO, YOSHINORI
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1996
Main classification: H03L7
IPC codes: H03L7, H04J3