HALF-BRIDGE DRIVER CIRCUIT

Abstract: An integrated half-bridge driver circuit for driving a half-bridge output stage having high-side and low-side power transistors coupled together at a high-voltage output terminal includes a low-voltage control circuit and a floating well within the integrated circuit which has a timing circuit for controlling the activation of the high-side power transistor. The driver circuit further includes a high-voltage interface circuit for coupling a control signal from the low-voltage control circuit to the timing circuit within the floating well. In this manner, an integrated half-bridge driver circuit is obtained which is capable of operating at high frequencies due to the relatively low power dissipation in the control and timing circuitry.

Description: Half-bridge driver circuit. The invention relates to a half-bridge driver circuit for driving a half- bridge output stage having high-side and low-side power transistors coupled together at a high-voltage output terminal, which comprises: a low-voltage control circuit having a low-voltage input terminal and a control output coupled to a control terminal of said low-side power transistor, and a floating well, a floating ground node of said floating well being coupled to said high-voltage output terminal. Half-bridge driver circuits are presently used to drive power transistors in such applications as power converters in electronic ballasts for high intensity discharge lamps and induction lamps. Although present electronic ballast circuits operate at relatively low frequencies, typically up to several hundred kHz, electronic ballasts currently under development for high intensity discharge lamps will be required to operate at frequencies of over 700 kHz, with electronic ballasts for induction lamps requiring operation at frequencies up to several MHz. For such applications, the use of existing half-bridge driver circuits in the power converters of the electronic ballasts is impractical, because present integrated circuit designs generate high losses and excessive heat at high frequencies, which in practice limits high-voltage high-frequency operation. A representative prior-art integrated driver circuit is the IR2110, manufactured by International Rectifier. This high-voltage integrated circuit uses a bootstrap capacitor to power the high-side gate drive circuit, which is fabricated in a floating well within the IC. Timing information from a low-voltage control circuit is communicated to the circuitry within the floating well by a level-shifting stage that operates off the high voltage and sends pulses of current to a latch circuit in the floating well. The state of the latch circuit then determines when the high-side power transistor is turned on and off. However, the use of a level shifting stage operating off the high voltage, while effective to transmit timing information to the high-side switch, is a major source of power loss at high frequencies, and in practice limits the frequency of operation of such circuits to about 100 kHz. The invention aims to provide a half-bridge driver circuit in which power losses due to dissipation in the level shifting circuitry are minimized or eliminated. Additionally, the invention aims to provide a half-bridge driver circuit capable of operating at frequencies substantially higher than the maximum operating frequency of presently-available integrated driver circuits. A half-bridge driver circuit as mentioned in the opening paragraph is therefore according to the invention characterized in that the floating well comprises a timing circuit for controlling the activation of said high-side power transistor and in that the half- bridge driver circuit comprises a high-voltage interface circuit for coupling said control output of said low-voltage control circuit to said timing circuit. It was found that power losses due to dissipation in a half-bridge driver circuit according to the invention were relatively small and also that a half-bridge driver circuit according to the invention could be operated at a relatively high frequency. In a preferred embodiment of a half-bridge driver circuit according to the invention, the timing circuit comprises an RC network for generating a decaying voltage signal referenced to the floating ground node from a signal provided from said control output. The timing circuit in the preferred embodiment is realized in a simple and dependable way. Preferably said floating well further comprises means for generating first and second reference voltages referenced to said floating ground node, said first reference voltage being less than an initial value of said decaying voltage signal and said second reference voltage being less than said first reference voltage, said high-side power transistor being activated when said decaying voltage signal reaches the value of said first reference voltage and being deactivated when said decaying voltage signal reaches the value of said second reference voltage. Activation and deactivation of said high-side power transistor at the indicated moments in time can relatively easily and dependably be realized this way. In addition good results were obtained in case said floating well further comprises a first comparator for comparing said decaying voltage signal to said first reference voltage to control the activation of said high-side power transistor and a second comparator for comparing said decaying voltage signal to said second reference voltage to control the deactivation of said high-side power transistor. Preferably said means for generating said first and second reference voltages comprises first and second capacitors, a first terminal of each of said first and second capacitors being coupled to said floating ground node. In that case first and second substantially constant voltages are preferably generated in said low- voltage control circuit, and said high-voltage interface circuit preferably comprises first and second diodes for coupling said first and second substantially constant voltages, respectively, to second terminals of said first and second capacitors to generate said first and second reference voltages in said floating well. Similarly in that case said high-voltage interface circuit preferably further comprises a third diode for coupling said control output to said RC network in the timing circuit. Preferably at least part of the half-bridge driver is an integrated circuit. An embodiment of the invention will be further explained with reference to a drawing, in which: Fig. 1 shows a block diagram of an integrated half-bridge driver circuit in accordance with the invention; Fig. 2 shows a simplified schematic diagram of the integrated half-bridge driver circuit of Fig. 1 , and Figs. 3a, 3b and 3c show selected voltage waveforms generated during operation of the circuit shown in Fig. 2. An integrated half-bridge driver circuit 10 in accordance with the invention is shown in block-diagram form in Fig. 1. This circuit is used for driving a half- bridge output stage 12 having high-side and low-side power transistors 14 and 16, respectively, coupled together between a high-voltage terminal 18 and a common or ground node 20 at a high-voltage output terminal 22. The driver circuit 10 further includes a low-voltage control circuit 24 having a low-voltage input terminal 26 and a control output which is coupled through a driver 28 to the gate of low-side power transistor 16, shown here as an MOS power transistor. The control output of low-voltage control circuit 24 is additionally coupled, via a high-voltage interface circuit 30, to a timing circuit 32 in a floating well 34 of the integrated driver circuit 10. It should be understood that the term "floating well", as used herein, designates a portion of an integrated circuit which is electrically "floating" with respect to other portions of the same integrated circuit, so that both its voltage supply and common or ground connections can "float" or vary with respect to the voltage supply and ground connections for the remainder of the integrated circuit, in a manner well known to those of ordinary skill in this art. Thus, circuits such as timing circuit 32 in the floating well 34 are coupled between a voltage supply line 36 and a floating ground node 38 which is connected to high-voltage output terminal 22. Circuits such as timing circuit 32 in the floating well are powered by a floating voltage supply shown schematically in Fig. 1 by block 40, which is coupled between supply line 36 and floating ground node 38. The output of timing circuit 32 is coupled to a voltage comparison circuit 42, the output of which is coupled in turn to a latch circuit 44. The output of the latch circuit 44 is provided, through a driver 46, to the gate of high-side power transistor 14 to control the activation and deactivation of MOS transistor 14 in accordance with timing signals generated in the timing circuit 32. Thus, the integrated half-bridge driver circuit of Fig. 1 eliminates the level-shifting circuitry of prior-art driver circuits, and the attendant disadvantages associated with such level-shifting circuits, by using high-voltage interface circuit 30 and timing circuit 32, which together couple signals from the low-voltage control circuit 24 up to the floating well 34, and then generating appropriate timing information from these signals within the floating well 34. Further details of the integrated half-bridge driver circuit 10 are shown in the simplified schematic diagram of Fig. 2. In Fig. 2, for simplicity, like reference numerals have been used to identify like components illustrated in Fig. 1 and previously described, with additional detail being shown in the timing and control portion of the circuit relevant to the present invention. It should be understood that the particular circuit configuration shown in Fig. 2 represents a preferred embodiment, and that various alternative circuit configurations can be used for the various blocks shown in Fig. 1 within the scope of the invention. In Fig. 2, the low-voltage control circuit 24 includes a control circuit 48 and driver 50 for providing the various control and reference voltage signals used by the remainder of the driver circuit. More particularly, control output voltage V L is coupled from the low-voltage control circuit 24 through driver 28 to the gate of low-side MOS power transistor 16 and, through a driver 50, to high-voltage interface circuit 30. In the embodiment shown in Fig. 2, the high-voltage interface circuit 30 is composed of diodes 52, 54 and 56, although other high-voltage coupling components, such as MOS transistors, may alternatively be used. High-voltage interface circuit 30 is coupled by coupling diode 52 to an RC network composed of capacitor 58 and resistor 60, with diode 54 being coupled to capacitor 62 and diode 56 being coupled to capacitor 64. Resistor 60, and capacitors 58, 62 and 64 are all referenced to the floating ground node 38. The floating voltage supply 40 in this embodiment is composed of a bootstrap capacitor 66 coupled to low- voltage control circuit 24 by a diode 68, with a DC voltage from control circuit 48 within the low-voltage control circuit 24 being provided through diode 68 to charge bootstrap capacitor 66 to a voltage above that of floating ground node 38 when this node is at a low voltage. In this manner, a voltage is generated across bootstrap capacitor 66 to provide a power supply voltage to the circuitry within floating well 34, with diode 68 becoming reverse-biased when the voltage on voltage supply line 36 within the floating well rises to a high voltage value with reference to the common or ground node 20 of the driver circuit. Within the timing circuit 32, reference voltages V, and V 2 are generated across capacitors 64 and 62, respectively, from substantially constant voltages generated in control circuit 48 and coupled to the capacitors 64 and 62 by diodes 56 and 54, respectively. Similarly, control output voltage V L is coupled through driver 50 and diode 52 to the RC network 58,60 to generate a decaying voltage signal V 0 , with voltages V 0 , V, and V 2 all referenced to the floating ground node 38. Reference voltages V, and V 2 , and decaying voltage signal V 0 , are coupled to comparators 70 and 72 within voltage comparison circuit 42, with the output of these two comparators being coupled to latch circuit 44. The remainder of the circuit shown in Fig. 2 is the same as shown and described in connection with Fig. 1 , and accordingly will not be described in further detail here. The operation of the circuit of Fig. 2 may be more easily understood with reference to the timing diagrams of Figs. 3a, 3b and 3c, which show the voltage levels of the waveforms V L , V 0 , and V H along the vertical axis, as a function of time along the horizontal axis, with five specific points in time being labelled 1 through 5 for reference. At time point 1 , the control output voltage V L goes high and is coupled through driver 28 to the gate of low-side power MOS transistor 16 to turn that transistor on and cause the high-voltage output terminal 22 to go low. At the same time, voltage V L is coupled through driver 50 and diode 52 to charge capacitor 58 in timing circuit 32 to a high initial voltage with reference to floating ground node 38 which, since it is connected directly to output node 22, is at this point in time at a low voltage. At the same time, capacitors 64 and 62 are similarly charged to voltage levels V, and V 2 from substantially constant voltages provided from control circuit 48 through diodes 56 and 54, respectively. The relationship between the initial value of these voltages is such that V 0 > V, > V 2 , as shown in Fig. 3b. Then, at time point 2, voltage V L goes low, and voltage V 0 begins to decay as capacitor 58 discharges through resistor 60, since voltage V 0 is no longer held at its substantially constant initial value by the voltage provided through diode 52. During the time period between points 2 and 3, the value of voltage V 0 provided to the voltage comparison circuit 42 is greater than both V, and V 2 and the latch circuit 44 and driver circuit 46 accordingly provide a low initial value for voltage V H at the gate of high-side MOS power transistor 14, thus ensuring that this transistor is off while low-side MOS power transistor 16 is on and for a short interval thereafter. When the voltage V 0 decays sufficiently such that its value drops below reference voltage level V,, as shown at time point 3 in Fig. 3b, this change in voltage levels will be detected by comparator 70, which will activate latch circuit 44 and driver 46 to cause voltage V H to go high, thus activating high-side power transistor 14. It should be noied that while high-side transistor 14 is not activated until time point 3, low-side power transistor 16 is deactivated at earlier time point 2, thus avoiding any overlap in activation of the two power transistors, which would result in an undesirable and possibly damaging current surge between the high voltage terminal 18 and ground terminal 20. Subsequently, at time point 4, the voltage V 0 has further decayed and passes below the value of reference voltage V 2 , and this change in voltage levels will be detected by comparator 72, which will cause latch circuit 44 and driver 46 to return voltage V H to its low level, thereby turning high-side power transistor 14 off. Finally, at time point 5, V L will again go high, activating low-side power transistor 16 through driver 28, and the cycle will repeat. It is important to note that the voltage V H returns to its low level at time point 4, thus deactivating high-side power transistor 14, before voltage V L goes high at time point 5 to activate low-side power transistor 16, again avoiding an undesirable and potentially damaging situation involving the simultaneous conduction of both power transistors. Additionally, it should be noted that all of the timing information is generated from low-voltage signals V 0 , V, and V 2 provided from the low-voltage control circuit 24 while the floating ground node 38 is at its low level, thus avoiding the necessity for high-voltage level-shifting circuits to convey this information to the floating well as in the prior art. Furthermore, since all of the relevant parameters (the voltages V 0 , V, and V 2 and the values of capacitor 58 and resistor 60) are determined by easily-controlled low voltages and easily-calculated component values, both the "dead-time" (the time between time points 2 and 3, and between time points 4 and 5) and the high-side pulse width (the time between time points 3 and 4) can be easily and accurately determined by the appropriate selection of low-voltage levels and component values. The integrated half-bridge driver circuit described above is capable of efficiently driving a half-bridge output stage without the need for a level-shifting circuit operating off the high voltage as is required in comparable prior-art circuits. This substantially reduces unwanted power losses in the driver circuit and permits operation at substantially higher frequencies than the prior-art circuits.

Claims: o CLAIMS: 1. A half-bridge driver circuit for driving a half-bridge output stage having high-side and low-side power transistors coupled together at a high-voltage output terminal, which comprises: a low-voltage control circuit having a low-voltage input terminal and a control output coupled to a control terminal of said low-side power transistor, and a floating well, a floating ground node of said floating well being coupled to said high-voltage output terminal, characterized in that the floating well comprises a timing circuit for controlling the activation of said high-side power transistor and in that the half-bridge driver circuit comprises a high- voltage interface circuit for coupling said control output of said low-voltage control circuit to said timing circuit. 2. A half-bridge driver circuit as in Claim 1, wherein said timing circuit comprises an RC network for generating a decaying voltage signal referenced to said floating ground node from a signal provided from said control output. 3. A half-bridge driver circuit as in Claim 2, wherein said floating well further comprises means for generating first and second reference voltages referenced to said floating ground node, said first reference voltage being less than an initial value of said decaying voltage signal and said second reference voltage being less than said first reference voltage, said high-side power transistor being activated when said decaying voltage signal reaches the value of said first reference voltage and being deactivated when said decaying voltage signal reaches the value of said second reference voltage. 4. An integrated half-bridge driver circuit as in Claim 3, wherein said floating well further comprises a first comparator for comparing said decaying voltage signal to said first reference voltage to control the activation of said high-side power transistor and a second comparator for comparing said decaying voltage signal to said second reference voltage to control the deactivation of said high-side power transistor. 5. A half-bridge driver circuit as in Claim 3, wherein said means for generating said first and second reference voltages comprises first and second capacitors, a first terminal of each of said first and second capacitors being coupled to said floating ground node. 6. A half-bridge driver circuit as in Claim 5, wherein first and second substantially constant voltages are generated in said low-voltage control circuit, and said high-voltage interface circuit comprises first and second diodes for coupling said first and second substantially constant voltages, respectively, to second terminals of said first and second capacitors to generate said first and second reference voltages in said floating well. 7. A half-bridge driver circuit as in Claim 6, wherein said high-voltage interface circuit further comprises a third diode for coupling said control output to said RC network in the timing circuit. 8. A half-bridge driver circuit according to one or more of the previous claims, wherein at least part of the half-bridge driver is an integrated circuit.

Inventors: WONG STEPHEN L, WONG, STEPHEN, L.
Applicants: PHILIPS ELECTRONICS NV, PHILIPS NORDEN AB, PHILIPS ELECTRONICS N.V.
Application year: 1996
Main classification: H02M7
IPC codes: H02M1, H02M7, H03K17