Application of thin crystalline Si3N4 liners in shallow trench isolation (STI) structures

Abstract: Silicon integrated circuits use a crystalline layer of silicon nitride (Si 3 N 4 ) in shallow trench isolation (STI) structures as an O 2 -barrier film. The crystalline Si 3 N 4 lowers the density of electron traps as compared with as-deposited, amorphous Si 3 N 4 . Further, a larger range of low-pressure chemical-vapor deposited (LPCVD) Si 3 N 4 films can be deposited, providing a larger processing window for thickness controllability. An LPCVD-Si 3 N 4 film is deposited at temperatures of 720°C to 780°C. The deposited film is in an amorphous state. Subsequently, a high-temperatures rapid-thermal anneal in pure nitrogen or ammonia is conducted at 1050°C to 1100°C for 60 seconds.

Description: Field of the Invention The present invention generally relates to the manufacture of submicron integrated circuits and, more particularly, to the application of thin silicon nitride (Si 3 N 4 ) films in shallow trench (STI) structures as O 2 -barrier films. Background Description One of the most critical parameters affecting silicon integrated circuit functionality and yield is the amount of stress that is developed within the silicon substrate during device processing. Stresses, exceeding the mechanical yield strength of silicon (Si), will form Si crystal defects (e.g., dislocations and stacking faults), adversely affecting device performance and yield. A prominent source of stress occurs during the isolation process of electrical devices. Shallow trench isolation (STI) is used for features designed a 0.5 µm or less. This process includes etching a "shallow" trench (i.e., 0.5 µm or less), growing a thin oxide immediately after etch, filling the trench with a dielectric (i.e., deposited oxide), "densifying" the dielectric, either by oxidizing the dielectric or using a high-temperature anneal in an inert ambient, and planarization of the dielectric. As device geometries continue to shrink in size, and since stress is inversely proportional to area, it is of paramount importance to minimize stress during isolation processes as much as possible. A 256 megabyte (MB) dynamic random access memory (DRAM) chip uses a "deep" trench array (as the capacitors) and STI to isolate the various transistors within the capacitor array. It has been determined that limiting the amount of oxide grown in the substrate is necessary to eliminate Si crystal defects in the trench-capacitor array. The method currently employed to "block-out" oxygen (O 2 ) in the Si substrate is the use of a thin (<5 nm) silicon nitride (Si 3 N 4 ) film deposited by low-pressure chemical-vapor deposition (LPCVD) immediately after a thin oxide is grown in the STI. The thickness of the Si 3 N 4 film is specified as being 5 nm or less. The reason for this thickness limitation is that this film has been found to be etch-resistant in hot phosphoric acid baths (e.g. to remove pad Si 3 N 4 ) as well as in hydrofluoric acid baths (to remove thermally grown oxides). Thicker LPCVD-Si 3 N 4 films used as Si 3 N 4 liners in STI trenches have shown to etch readily in hot phosphoric acids. One problem associated with the thin Si 3 N 4 liner has been its propensity to trap electrical charge. The charge-trapping behavior (interface and bulk) of the Si 3 N 4 liner has been observed to enhance STI-bounding leakage (N well to N well) in the sense amplifiers (i.e. "support circuitry" of the DRAMSs, thus causing high standby currents. Recent data clearly shows that the Si3N4 liner lowers the threshold voltages (Vt) and enhances junction leakage by several orders of magnitude. To ascertain the amount of charge that is trapped by the Si 3 N 4 liner, blanket wafer experimental lots were processed consisting of (1) thermally-grown oxide (SiO 2 - 10 nm), (2) LPCVD-Si 3 N 4 (4 nm), and (3) 10 nm SiO 2 /4 nm LPCVD-Si 3 N 4 . Simple metal-insulator-semiconductor (MIS) structures were fabricated by depositing aluminium through a dot mask onto the insulating film(s). C-V measurements (low- and high-frequency) were conducted and result indicated that (1) the thin Si3N4 film alone contains approximately two orders of magnitude more charge-trapping states than the oxide (i.e. 10 12 versus 10 10 ), and (2) the combination of the oxide and Si 3 N 4 decreases the density of charge-trapping states only marginally (eg. ~5×10 11 versus 10 10 ). Ideally, it would be best to develop or deposit a thin Si 3 N 4 film that would not trap charge and still be resistant to hot phosphoric acid and hydrofluoric acid. US 5472904 discloses a process for isolating active areas of semiconductor devices in which an oxide layer is formed by oxidising the exposed substrate following selective etching of a thin nitride layer. Summary of the Invention It is therefore an object of the present invention to provide a thin Si 3 N 4 film which has a lower density of trapping centers than as-deposited LPCVD-Si 3 N 4 and is an extremely effective as an O 2 -barrier film yet is resistant to hot phosphoric acid and hydrofluoric acid. According to the invention, thin crystalline Si 3 N 4 films are applied in STI structures as O 2 -barrier films. The crystalline Si 3 N 4 contains a lower density of trapping centers, is more resistant to hot phosphoric acid etches and hydrofluoric acid etches than as-deposited LPCVD-Si 3 N 4 , and is extremely effective as an O 2 -barrier film. The fact that crystalline Si 3 N 4 has a lower density of trapping centers lowers, and in some cases prevents altogether, the parasitic transistor caused by the as-deposited LPCVD-Si 3 N 4 film used in current STI technology. Furthermore, unlike the restrictive thicknesses that are specified in the current technology, this invention permits a larger range of crystalline Si 3 N 4 thicknesses (e.g., 5 nm to 10 nm) to be used as O 2 -barrier films in STI trenches. This allows a larger processing window for thickness controllability in manufacturing. Brief Description of the Drawings The foregoing and other objects, aspects and advantages will be better understood from the following detailed description of a preferred embodiment of the invention with reference to the drawings, in which: Figures 1A, 1B and 1C illustrate the process of forming thin crystalline Si 3 N 4 films in STI structures; and Figures 2A and 2B are, respectively, a bright-field transmission electron micrograph (TEM) of crystalline Si 3 N 4 and an electron diffraction pattern of the TEM. DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION Referring now to the drawings, and more particularly to Figures 1A, 1B and 1C, there is shown the process of forming crystallized Si 3 N 4 films in STI trenches according to the invention. In Figure 1A, after a shallow trench has been etched, a thin thermal oxide (typically 10 nm thick) is grown to remove etch damage. Next, in Figure 1B, a thin Si 3 N 4 film (5 to 10 nm) is deposited on top of the thermally-grown oxide layer in the STI trench. Then, in Figure 1C, this Si 3 N 4 film (LPCVD- Si 3 N 4 ) is typically deposited at temperatures of 720°C to 780°C, and as such, is generally deposited in an amorphous state. Immediately after deposition, a high temperature, rapid thermal anneal in pure nitrogen (RTN) or ammonia (NH 4 ) is conducted. Crystallization of LPCVD-Si 3 N 4 begins at 1050°C and for anneal times of the order of 60 seconds. Temperatures greater than 1050°C and/or anneal times greater than 60 seconds will induce further crystallization and grain growth of the LPCVD-Si 3 N 4 film. In addition, thicker LCPVD-Si 3 N 4 films (up to 10 nm) can be crystallized at temperatures less than 1100°C. This can be critically important in terms of limiting wafer warpage and slip line information along wafer edges during the RTN process. The typical morphology of crystalline Si 3 N 4 is shown in Figures 2A and 2B. Figures 2A and 2B are bright-field transmission electron micrograph (TEM) and corresponding electron diffraction pattern, respectively, of a 10 nm SiO 2 /4 nm Si 3 N 4 insulator-couple that has been annealed at 1100°C. At 1100°C, the Si 3 N 4 film is found to be largely crystalline. At 1050°C, the majority of the film is found to be amorphous; however, small crystallites of Si 3 N 4 are observed. Electron diffraction analysis of samples annealed at 1050°C and 1100°C shows that crystalline Si 3 N 4 film is the low-temperature, hexagonal (α) Si 3 N 4 phase. Crystallized films of LPCVD-Si3N4 have much lower trap densities as compared to as-deposited LPCVD-Si 3 N 4 films. Results of C-V measurements of 10 nm SiO 2 /4 nm Si 3 N 4 insulator-couples which have been crystallized by high temperature RTN anneals (1050°C to 1150°C) show that the trap density, at a minimum, has decreased by an order of magnitude. In addition, crystallized LPCVD-Si 3 N 4 films show a heartier etch resistance to hot phosphoric acid and hydrofluoric acids. Etch rate studies show that crystallized LPCVD-Si 3 N 4 films have, at a minimum, a 45% lower etch rate in hot phosphoric acid than as-deposited Si 3 N 4 and as much as a 30% lower etch rate in pure hydrofluoric acid.

Claims: A process of forming a thin film of crystalline silicon nitride (Si 3 N 4 ) film in a shallow trench isolation (STI) structure in an integrated circuit device comprising the steps of: depositing by low-pressure chemical-vapor deposition (LPCVD) a Si 3 N 4 film 5 to 10 nm thick within an STI structure at a temperature between 720°C and 780°C; and immediately after deposition of the Si 3 N 4 film, conducting a rapid-thermal anneal between 1050°C and 1150°C for approximately 60 seconds to convert the Si 3 N 4 film from an amorphous state to a crystalline state. The process recited in claim 1 wherein the STI structure is formed comprising the steps of: etching a shallow trench of 0.5µm or less in a silicon substrate; and growing a thin thermal oxide in the etched trench to a thickness of approximately 10 nm to remove etch damage. The process recited in claim 1 wherein the anneal temperature is 1100°C or less. The process recited in claim 1 wherein the rapid-thermal anneal is done in pure nitrogen. The process recited in claim 1 wherein the rapid-thermal anneal is done in ammonia.

Inventors: AJMERA ATUL, DOBUZINSKY DAVID M, FUGARDI STEPHEN, HAMMERL ERWIN, HO HERBERT, MOSEMAN JAMES E, PALM J HERBERT, RAMAC SAMUEL C, AJMERA, ATUL, DOBUZINSKY, DAVID M., FUGARDI, STEPHEN, HAMMERL, ERWIN, HO, HERBERT, MOSEMAN, JAMES E., PALM, J. HERBERT, RAMAC, SAMUEL C.
Applicants: IBM, INFINEON TECHNOLOGIES AG, INTERNATIONAL BUSINESS MACHINES CORPORATION
Application year: 1996
Main classification: H01L21
IPC codes: H01L21