LOGIC CIRCUITS

Abstract: A logic circuit having at least a first input terminal and at least a first output terminal, comprises at least a first and a second electron-wave Y-branch switch (2, 3), each having a source (S2, S3), a first drain (D2', D3'), a second drain (D2", D3"), and at least a first gate (G2, G3) for switching a source current (IDD) between the first and the second drain (D2', D3'; D2", D3"). The sources (S2, S3) of said first and said second Y-branch switches (2, 3) are adapted to be connected to a high voltage supply and a low voltage supply, respectively. The first gates (G2, G3) of said first and said second Y-branch switches (2, 3) are interconnected, and the interconnection point between said first gates (G2, G3) constitutes said first input terminal. The first drain (D2') of the first Y-branch switch (2) is connected to the second drain (D3") of the second Y-branch switch (3), and the second drain (D2") of the first Y-branch switch (2) is connected to the first drain (D3") of the second Y-branch switch (3). The interconnection point between said second drain (D2") of the first Y-branch switch (2) and said first drain (D3') of the second Y-branch switch (3) constitutes said first output terminal.

Description: LOGIC CIRCUITS TECHNICAL FIELD The invention relates to a logic circuit having at least one input terminal and at least one output terminal. BACKGROUND OF THE INVENTION For a long time, transistors have dominated digital elect¬ ronics. Mainly by reducing device size, it has been possible to increase packing density and speed by several orders of magnitude. Nevertheless, by reducing the device size, new phenomena become important which may cause problems for the transistors but which also may open up possibilities for new devices. When device sizes are reduced to below the inelastic and elastic scattering length, the ballistic region is entered, where the common drift/diffusion model fails. Instead, electrons travel in straight lines and are reflected and refracted like lightwaves. Thus, when the width of an electric wire approaches that of the electron wavelength (tens of nm in semiconductors) the wire should be treated as a waveguide analogous to an optical fibre. From i.a. "Analy¬ sis of an electron-wave Y-branch switch" by Thomas Palm and Lars Thylen in Appl. Phys. Lett. 60 (2), 13 January 1992, pages 237-239, and US-A-5,367,274, a so called electron-wave Y-branch switch built of electron waveguides, is known. As apparent from these publications, the Y-branch switch is based on modal evolution and has a monotonic response to a changed gate voltage. By creating an electric field perpen¬ dicular to a branching waveguide, electrons can be forced to enter the branch with the highest electrostatic potential. An advantage of the Y-branch switch over a field effect tran- sistor (FET) is that it has added functionality in that it switches current between two outputs rather than turning a current on or off. An additional advantage is the potential for low voltage operation. Unlike the FET, the Y-branch does not require a switching voltage larger than the thermally limited voltage k B T/e, where B is Boltzmann's constant. (See "Quantum interference devices and field-effect transistors: A switch energy comparison" by T. Palm, L. Thylen, O. Nilsson, and C. Svensson in J. Appl. Phys., Vol. 74, No. 1, pp. 687-694, 1993.) BRIEF DISCLOSURE OF THE INVENTION The object of the invention is to design logic circuits using electron-wave Y-branch switches. According to the invention, this is attained by the logic circuits set forth in the claims. BRIEF DESCRIPTION OF THE DRAWING The logic circuits according to the invention will be described more in detail below with reference to the appended drawing on which Fig. 1 shows a first embodiment of an inverter, Fig. 2a shows a second embodiment of an inverter, Fig. 2b shows a first embodiment of a logical implication gate. Fig. 2c shows first embodiment of a NAND gate. Fig. 2d shows a first embodiment of a NOR gate, Fig. 3 shows a third embodiment of an inverter. Fig. 4 shows a second embodiment of a NAND-gate, Fig. 5 shows a second embodiment of a NOR-gate, and Fig. 6 shows a second embodiment of a gate implementing a logical implication function. PREFERRED EMBODIMENTS Fig. 1 shows a first embodiment of an inverter according to the invention. The inverter in Fig. 1 comprises an electron-wave Y-branch switch 1 having a source SI which is adapted to be connected to a high supply voltage V DD , a first drain Dl', a second drain Dl'', and a gate Gl. The gate Gl constitutes the input terminal of the inverter and is adapted, depending on its input signal V G , to switch a source current I DD between the first drain Dl' and the second drain Dl''. The first drain Dl' is series-connected with a resistor Rl' to a low supply voltage which in the embodiment shown is equal to ground. The second drain Dl'' is series-connected with a resistor Rl'' to the same low supply voltage, i.e. ground, as the resistor Rl'. In the embodiment shown, the output terminal of the inverter is the interconnection point between the second drain Dl'' and the resistor Rl''. When the input signal V G on the gate Gl is low, the source SI will be connected to the drain Dl'' pulling up the output voltage V QUt to the high supply voltage DD . When the input signal V G is high, the source SI will be connected to ground via the resistor Rl', while the resistor Rl'' will ensure that the output voltage V out is pulled down to a low voltage. Another embodiment of an inverter according to the invention ' is shown in Fig. 3. The inverter according to Fig. 3 comprises a first electron- wave Y-branch switch 2 and a second electron-wave Y-branch switch 3 which are of the same type as the Y-branch switch 1 in Fig. 1. Thus, each of the Y-branch switches 2 and 3 in Fig. 3 comprises a source S2 and S3, respectively, a first drain D2' and D3', respectively, a second drain D2'' and D3'', respectively, and a gate G2 and G3, respectively. The sources S2 and S3 of the Y-branch switches 2 and 3, respectively, are connected to a high supply voltage V DD and a low supply voltage, e.g. ground, respectively. In accordance with the invention, the gate G2 of the switch 2 and the gate G3 of the switch 3 are interconnected and the interconnection point constitutes the input terminal of the inverter according to Fig. 3, which is supplied with an input signal V G . The drain D2' of the switch 2 is connected to the drain D3' ' of the switch 3 while the drain D2'' of the switch 2 is connected to the drain D3' of the switch 3. The interconnection point between the drains D2" and D3' constitutes the output terminal of the inverter as indicated *>y v out - In the inverter according to Fig. 3, when the input signal V G is high, the switch 3 connects the output terminal V ou ^. to ground, while the switch 2 connects the interconnection point V a between the drains D2' and D3" to V DD - When the input signal V G goes low, V out will instead be connected to V DD and V a will be connected to ground. Thus, current will flow through the gate only during switching, which is analogous to the behaviour of complementary metal-oxide semiconductors (CMOSs) . The inverter according to Fig. 1 is analogous to NMOS, while the inverter in Fig. 3 is analogous to CMOS. In connection with FETs, NMOS has largely been replaced by CMOS, and for the same reasons, the inverter according to Fig. 3 is more preferred than the inverter according to Fig. 1. Fig. 4 shows an embodiment of a NAND gate which comprises two inverters of the type shown in Fig. 3. As in Fig. 3, each inverter in Fig. 4 comprises two Y-branch switches 4 and 5, and 6 and 7, respectively. Each of the switches 4, 5, 6, and 7 comprises a source S4, S5, S6 and S7, respectively, a first drain D4', D5', D6' and D7', respectively, a second drain D4", D5", D6" and D7", respectively, and a gate G4, G5, G6 and G7, respectively. With reference to Fig. 4, the interconnection point between the drain D4' ' of the switch 4 and the drain D5' of the switch 5 is connected to the source S7 of the switch 7. The interconnection point between the drain D6'' of the switch 6 and the drain D7' of the switch 7 constitutes the output of the embodiment of the NAND gate in Fig. 4. The sources S4 and S6 of the switches 4 and 6, respectively, are both connected to a high supply voltage V DD , while the source of the switch 5 is connected to ground as in Fig. 3. The left inverter comprising the switches 4 and 5, is controlled by an input gate voltage V G1 connected to gates G4 and G5, and supplies the voltage V b to the source S7 of the switch 7 of the right inverter. In this right inverter, an input gate voltage V G2 controls whether the output voltage v out ^ s V D D or v b * 0nl Y i f both gate voltages V G1 and V G2 are logic ones, the output will be connected to ground. Fig. 5 shows an embodiment of a NOR gate also comprising two inverters of the type shown in Fig.3. As in Fig. 3, each inverter in Fig. 4 comprises two Y-branch switches 8 and 9, and 10 and 11, respectively. Each of the switches 8, 9, 10, and 11 comprises a source S8, S9, S10 and Sll, respectively, a first drain D8', D9', D10' and Dil', respectively, a second drain D8'', D9'', D10" and Dil'', respectively, and a gate G8, G9, G10 and Gil, respectively. The only difference between the NOR gate in Fig. 5 and the NAND gate in Fig. 4 is that the source S10 of the switch 10 is connected to the interconnection point between the second drain D8'' of the switch 8 and the first drain D9' of the switch 9, while the source Sll of the switch 11 is connected to ground. Fig. 6 shows an embodiment of a gate, implementing a logical implication function, based on the inverter in Fig. 3, i.e. with two Y-branch switches 12 and 13 comprising a source S12 and S13, respectively, a first drain D12' and D13', respectively, a second drain D12'' and D13'', respectively, and two gates G12'and G12'', and G13'and G13'', respectively. The interconnection point between the gates G12' and G13' constitues a first input terminal for a gate voltage V G1 , while the interconnection point between the gates G12'' and G13'' constitutes a second input terminal for a gate voltage V G2 « The logical implication gate in Fig. 6 produces the outputs V a = V G1 AND NOT V G2 and V Qut = V G2 OR NOT V G1 , i.e. both complementary outputs are generated. This provides a factor of two size reduction compared to the NAND gate in Fig. 5 at the price of an unconventional logic basis function. The logical implication gate in Fig. 6 requires that the two Y-branch switches 12 and 13 are asymmetric as indicated by a thicker line for the drains D12'' and D13'', respectively. The thick line symbolizes that the current will flow in the "thicker line" drain when the gate voltages V G1 and V G2 are equal on the two gates. Thus, if V G2 > v c i ' tne Y-branch switch 12 will connect source S12 to drain D12'' and the Y- branch switch 13 will connect source S13 to drain D13''. If V G 2 < V G1 ' source S12 will be connected to drain D12' and source S13 will be connected to drain D13'. A smaller version of an inverter can be built using a single Y-branch switch 14 with a gate G14 which is used as an input terminal as shown in Fig. 2a. The two drains D14' and D14'' of the Y-branch switch 14 are connected to a low and a high voltage supply, respectively, while the source S14 is used as an output terminal. For phase-coherent transport, no current flows between the branches D14' and D14'' when the Y-branch switch 14 is biased, i.e. when V G1 = 0 or 1. There is a direct current between V DD and ground only for values inbetween, i.e. during switching. The inverter according to Fig. 2a will be more sensitive to inelastic scattering than the inverters in Figs. 1 and 3 since scattering may cause a leakage current between the two drains D14' and D14''. In the inverter in Fig. 2a this will lead to a larger increase in power dissipation. Based on the inverter in Fig. 2a, Fig. 2b shows an embodiment of a gate which implements a logical implication, and which requires only a single Y-branch switch 15. The two drains D15' and D15" of the Y-branch switch 15 are coupled to a low supply voltage, ground, and a high supply voltage V DD , respectively, while the source S15 is used as an output terminal. Two gates G15' and G15'' are provided in this embodiment, and the gates G15' and G15'' are supplied with gate voltages V G1 and V G2 , respectively. The output V out = V G1 OR NOT V G2 is then produced. The Y-branch switch 15 in Fig.2b is asymmetric as the logical implication gate in Fig. 6, i.e. the source S15 is connected to drain D15' if V G1 > V G2 and to drain D15" if V G1 < V G2 . Fig. 2c shows an embodiment of a NAND gate based on a combination of the inverter in Fig. 2a, and the logical implication gate in Fig. 2b. As apparent from Fig. 2c, the NAND gate comprises an electron-wave Y-branch switch 16 having a source S16, a first drain D16', a second drain D16'', and a gate G16 which constitutes a first input terminal of the NAND. The first drain D16' and the second drain D16'' are adapted to be connected to a low voltage supply and a high voltage supply, respectively, while the source S16 is connected to the second gate G17'' of a second electron-wave Y-branch switch 17, the first gate G17' of which constitutes a second input terminal of the NAND gate. The first drain D17' and the second drain D17'' of that second electron-wave Y-branch switch 17 are adapted to be connected to a low voltage supply and a high voltage supply, respectively, while the source S17 of the electron-wave Y-branch switch 17 constitutes the output terminal of the NAND gate. Fig. 2d shows an embodiment of a NOR gate also based on a combination of the inverter in Fig. 2a, and the logical implication gate in Fig. 2b. As apparent from Fig. 2d, the NOR gate comprises an electron- wave Y-branch switch 18 having a source S18, a first drain D18', a second drain D18'', and a gate G18 which constitutes a first input terminal of the NOR gate. The first drain D18' and the second drain D18'' are adapted to be connected to a low voltage supply and a high voltage supply, respectively, while the source S18 is connected to the first gate G19' of an electron-wave Y-branch switch 19, the second gate G19'' of which constitutes a second input of the NOR gate. The first drain D19' and the second drain D19'' of the electron-wave Y- branch switch 19 are adapted to be connected to a high voltage supply and a low voltage supply, respectively, while the source S19 of the electron-wave Y-branch switch 19 constitutes the output terminal of the NOR gate. In all of the gates described above, phase-coherent transport is required within the Y-branch to ensure proper operation. This requirement is clearly apparent from the above mentioned US-A-5,367,274. In addition, whenever a closed loop of conductors is formed, such as between the two Y-branch switches 2 and 3 in Fig. 3 (and also in Figs. 4-6) , it is essential that phase coherence is broken somewhere in this loop. With phase-coherent transport, the loop may act as an Aharonov-Bohm interferometer ("Proposed structure for large quantum interference effects", S. Datta, M.R. Melloch, S. Bandyopadhyay, and M.S. Lundstrom, Appl. Phys. Lett., Vol. 48, No. 7, p. 487, 1986.), which is not the intended behaviour in this connection. This interferometer would add oscillations of an uncontrollable nature in response to changed gate voltages. Using current fabrication technologies, the path-length aorund the loop, e.g. in Fig. 3, is much longer than the inelastic mean free path of an electron ensuring that no Aharonov-Bohm oscillations will occur. If better fabrication technology allows the mean free path of the electrons to become comparable to the path-length of the loop, a special structure must be inserted somewhere in the loop. This structure, which has the purpose of producing inelastic scattering, may consist simply of a piece of a lower quality semiconductor. The logic circuits according to the invention allow a higher degree of integration than current devices. The lower operating voltages will also reduce energy dissipation which often is a limiting factor in integrated electronics.

Claims: CLAIMS 1. A logic circuit having at least a first input terminal and at least a first output terminal, characterized in - that it comprises at least a first and a second electron- wave Y-branch switch (2, 3), each having a source (S2, S3), a first drain (D2', D3'), a second drain (D2", D3"), and at least a first gate (G2, G3) for switching a source current (I DD ) between the first and the second drain (D2', D3'; D2", D3"), - that the sources (S2, S3) of said first and said second Y- branch switches (2, 3) are adapted to be connected to a high voltage supply and a low voltage supply, respectively, - that the first gates (G2, G3) of said first and said second Y-branch switches (2, 3) are interconnected, the interconnection point between said first gates (G2, G3) constituting said first input terminal, - that the first drain (D2') of the first Y-branch switch (2) is connected to the second drain (D3 , ) of the second Y- branch switch (3) , and - that the second drain (D2") of the first Y-branch switch (2) is connected to the first drain (D3') of the second Y- branch switch (3) , the interconnection point between said second drain (D2'') of the first Y-branch switch (2) and said first drain (D3') of the second Y-branch switch (3) constituting said first output terminal. 2. A logic circuit according to claim 1, characterized in - that said first output terminal is connected to the source (S7) of a third electron-wave Y-branch switch (7) , - that the first drain (D7') of the third Y-branch switch (7) is connected to the second drain (D6'') of a fourth electron- wave Y-branch switch (6) , the interconnection point between said first drain (D7') of the third Y-branch switch (7) and said second drain (D6'') of the fourth Y-branch switch (6) constituting a second output terminal, - that the second drain (D7") of the third Y-branch switch (7) is connected to the first drain (D6') of the fourth Y- branch switch (6) , - that the first gates (G7, G6) of said third and fourth Y- branch switches (7, 6) are interconnected, the interconnection point between said first gates (G7, G6) constituting a second input terminal, and - that the source (S6) of said fourth Y-branch switch (6) is adapted to be connected to said high voltage supply. 3. A logic circuit according to claim 1, characterized in - that said first output terminal is connected to the source (S10) of a fifth electron-wave Y-branch switch (10) , - that the second drain (D10'') of the fifth Y-branch switch (10) is connected to the first drain (Dil') of a sixth electron-wave Y-branch switch (11) , the interconnection point between said second drain (D10'') of the fifth Y-branch switch (10) and said first drain (Dil') of the sixth Y-branch switch (11) constituting a second output terminal, - that the first drain (D10') of the fifth Y-branch switch (10) is connected to the second drain (Dil") of the sixth Y- branch switch (11) , - that the first gates (G10, Gil) of said fifth and sixth Y- branch switches (10, 11) are interconnected, the interconnection point between said first gates (G10, Gil) constituting a second input terminal, and - that the source (Sll) of said sixth Y-branch switch (11) is adapted to be connected to said low supply voltage. 4. A logic circuit according to claim 1, characterized in - that each of said first and said second electron-wave Y- branch switches (12, 13) have a second gate (G12", G13''), and - that said second gates (G12'', G13") are interconnected, the interconnection point between said second gates (G12", G13' ') constituting a second input terminal. 5. A logic circuit having at least one input terminal and one output terminal, characterized in - that it comprises an electron-wave Y-branch switch (14) having a source (S14) , a first drain (D14'), a second drain (D14''), and a gate (G14) constituting a first input terminal, - that the first drain (D14') and the second drain (D14") are adapted to be connected to a low voltage supply and a high voltage supply, respectively, and - that the source (S14) constitutes said output terminal. 6. A logic circuit according to claim 5, characterized in that it comprises a second gate (G15") constituting a second input terminal. 7. A logic circuit according to claim 5, characterized in - that the source (S16) is connected to the second gate (G17'') of a second electron-wave Y-branch switch (17), the first gate (G17') of which constitutes a second input terminal, - that the first drain (D17') and the second drain (D17") of said second electron-wave Y-branch switch (17) are adapted to be connected to a low voltage supply and a high voltage supply, respectively, and - that the source (S17) of said second electron-wave Y-branch switch (17) constitutes the output terminal. 8. A logic circuit according to claim 5, characterized in - that the source (S18) is connected to the first gate (G19') of a third electron-wave Y-branch switch (19) , the second gate (G19'') of which constitutes a second input, - that the first drain (D19') and the second drain (D19'') of said third electron-wave Y-branch switch (19) are adapted to be connected to a high voltage supply and a low voltage supply, respectively, and - that the source (S19) of said third electron-wave Y-branch switch (19) constitutes the output terminal. 9. A logic circuit having an input terminal and an output terminal, characterized in - that it comprises an electron-wave Y-branch switch (1) having a source (SI), a first drain (Dl'), a second drain (Dl"), and a gate (Gl) constituting said input terminal for switching a source current (IDJJ) between the first and the second drain (Dl', Dl"), - that the source (SI) is adapted to be connected to a high supply voltage (V DD ) , and - that the first drain (Dl') in series with a first resistor (Rl') and the second drain (Dl") in series with a second resistor (Rl'') are adapted to be connected to a low supply voltage, the interconnection point between the second drain (Dl") and the second resistor (Rl") constituting said output terminal.

Inventors: PALM THOMAS, THYLEN LARS, PALM, THOMAS, THYLEN, LARS
Applicants: ERICSSON TELEFON AB L M, PALM THOMAS, THYLEN LARS, PALM, THOMAS, TELEFONAKTIEBOLAGET L M ERICSSON (PUBL), THYLEN, LARS
Application year: 1996
Main classification: H03K19
IPC codes: H03K19