CLOCK SIGNAL CLEANING CIRCUIT

Abstract: A device which reduces jitter and narrows the frequency spectrum of a jitter-ridden clock signal includes a basic unit having a plurality of series connected delay elements outputs from each delay element are all connected to an AND/NAND gate. A front end of the device locates missing clock pulses and ensures regular clock pulses are relayed to the remainder of the device. A succeeding section including plural basic units hones the signal such that jitter elements are removed. By the output of this section time duty cycles are uneven, a positive edge triggered flip-flop is then used to obtain 50 % duty cycles at the expense of halving the clock signal's frequency. Optionally a frequency doubler can be employed to regain the clock signal's original frequency.

Description: Clock Signal Cleaning Circuit Background of the Invention Field of the Invention This invention relates to jitter removing circuits, clock averagers and other clock signal correction devices. Description of Related Art At present jitter is controlled by prevention rather than cure. By the use of good design technique the effects of factors such as current surges, temperature, EM interference etc, are minimised. However there are many instances where despite such measures jitter is introduced into the system via transmission, mechanical devices and the like. Clock recovery systems, which recover clock signals distorted by transmission usually incorporate a high quality crystal which is used as a reference and as a source if a clock pulse is missing. Summary of the Invention An object of the present invention is to provide an improved clock signal cleaning circuit. Presented is a device which removes jitter from a clock signal. The device is based upon a basic unit which is repeated throughout the device. The behaviour of this basic unit determines its jitter removal capabilities. In its present embodiment the invention can be considered passive, however it is possible to include feedback loops connected to the oscillator to compensate for environmental conditions including aging. The basic unit comprises a number of delay elements connected in series. The output of each delay is connected to the input of a multi-input AND gate. The output from the basic unit exhibits a narrower spectrum than the original spectrum. This statement must be qualified in that the actual signal emerges with an uneven duty cycle. By feeding the output from any of the basic units to a flip-flop a clock signal of half the original frequency is created with a 50% duty cycle because the times between positive to negative transitions is constant. After being passed through a frequency doubler the resulting spectrum of this signal is narrower than the original. In an embodiment of the present invention a 'front end' includes a circuit which compensates for missing pulses. Conveniently, any number of basic units can be connected in series. Each of their outputs are fed into a respective flip-flop and to a respective AND gate. There are one less AND gates connected such that the output from only one basic unit is let through to an EXOR gate. The output from there is presented to various basic units of different size, all connected in series. The output from there is fed to a flip-flop which corrects the uneven duty cycle but produces a signal whose frequency is half that input. Either this signal can be used, or the signal can be applied to a frequency doubler to create a clock signal at the original frequency. Brief Description of Drawings The present invention will be further understood from the following description with reference to the drawings in which: Figure 1 schematically illustrates a basic unit in accordance with an embodiment of the present invention; Figure 2 illustrates a block representation of the basic unit of Figure l; Figure 3 illustrates a front end in accordance with an embodiment of the present invention. Figure 4 illustrates an embodiment of the present invention for the middle section following the front end; and Figure 5 illustrates an embodiment of the present invention for the band end. Detailed Description The present invention aims to eliminate jitter and compensate for the occasional missing pulse from clock signals. The key element of an embodiment of the invention is a basic unit shown in Figure 1. It is passive in the sense that no feedback loops are employed. This does not mean that none can be; for example if there is no output it implies that the clock signal's frequency is outside the circuit's range and a feedback loop can be employed to control the crystal oscillator or clock source to bring the input frequency back within its range. It is to be understood that the present invention is not limited to work within the confines of electricity, indeed the topologies described work equally well, theoretically if the medium is light or sound as well as electrons. The practicalities of implementing the design fall within those of good design practice. For example delay lines of considerable length might be employed. In this circumstance stable voltage and current sources must be used to reduce jitter caused by the simultaneous switching of all these jitter caused by the simultaneous switching of all these gates. In fact delay elements can be formed from complementary pairs to eliminate current surges. Referred to Figure 1, there is schematically illustrated a basic unit in accordance with an embodiment of the present invention. This basic unit 14 consists of a number of delay elements 1-8 in series each having its output fed into a multi-input NAND/ AND gate 9. The number of delay elements is arbitrary however the greater the number the narrower the range of frequencies from which the unit can accept an input. In general given a imperfect signal as input the basic unit will give out a signal whose duty cycle is uneven. This is corrected later. Input 10 receives a signal direct from a crystal oscillator, other clock source or the output of another basic element. The signal propagates through the delay elements 1-8, the output at each element controls the output of the NAND/ AND gate 9 which forms part of the basic unit. The output 11 outputs the signal as it enters from the input 10. The output (changed) 12 gives the basic unit's output and output (changed) 13 gives the inverse of 12. A positive level from output (changed) 12 is only possible if all the levels presented at the inputs of the multi-input NAND/ AND gate 9 are positive. The delay of each element 1-8 must be identical and determines the 'ideal' frequency of the basic unit 14. Given a delay of x seconds then the ' ideal' or central frequency is 2π÷x Hz. In other words the delay introduced by each element must equal the period of the input frequency. It is difficult to analyze the circuit in the time domain, it is instructive to see its behaviour in the frequency domain by studying its effect on certain types of signals presented to it. When presented with a jitter-free, stable clock signal whose frequency is off from the ideal the basic unit 14 has no effect on the signal. The range of clock signal periods which are allowed through unaffected is given approximately by 2π Hz, x± x 2*n t where n, is the number of delay elements 1-8 in the basic unit 14 and x is the delay introduced by each delay element 1-8. When presented with a signal containing a range of frequencies (introduced by jitter or other factors) the basic unit 14 narrows the range significantly. An interesting feature is that irrespective of whether or not the signal's frequencies are centred around the 'ideal' frequency the basic unit 14 narrows the frequency range and moves the spectrum's peak towards the ideal frequency. However the closer the original signal's central frequency is to the basic unit's 14 the narrower the output spectrum. In Figure 2, a block representation of the basic unit of Figure 1 is shown. Referring to Figure 3, there is illustrated a front end in accordance with an embodiment of the present invention. The front end of the embodiment of the present invention is concerned with recognising the absence of clock pulses and compensating for them. If a clock pulse is missed then the logic is arranged so that the output from the basic unit 15-19 containing the absence is blocked (e.g. 19) and the signal from the basic unit preceding it (e.g. 18) takes over and is routed through to the following sections. The flip-flops 20-23 ensure that the output from only one basic until 15-19 reaches the EXOR gate 37. The delay elements 44, 25, 27, 29, 31 provide a delay equal to that of the flip-flops the signal paths too the AND gate have the same propagation delay. The delay elements 24, 26, 28, 30 at the enable/disable input of the flip-flops 20, 21, 22, 23 are adjusted so that the flip-flop can identify an absent clock pulse and an actual clock pulse. It also serves to reset the device. Referring to Figure 4, there is shown a middle section in accordance with an embodiment of the present invention. Following the front end of Figure 3, the signal then goes to a section including four basic units 38-41 each having an increasing number of delay elements. The actual topology of this section can be anything that works; experimentation will reveal the best ways of connecting basic elements 38-41 of any size and number for the particular application. By using increasingly larger numbers of delay elements the resulting signal will have a much narrower frequency spectrum. Referring to Figure 5, there is illustrated the back end in accordance with an embodiment of the present invention. Following the middle section, the signal is then presented to flip-flop 42 and optionally a frequency doubler 43. By the time the signal reaches this stage it may generally consist of a very short positive cycle and a very long negative half-cycle. The times between negative to positive transactions are constant. Small deviations may occur periodically which are caused by the signal going out of phase with the delay elements 1-8. Thus by using a positive edge triggered flip-flop 42 a signal with a 50% duty cycle, at the expense of halving the signal's frequency, is produced. If desired, a frequency doubler 43 can be employed to regain regenerate a clock signal of the original frequency. Numerous other modifications, variations and adaptions may be made to the particular embodiment of the invention described above without departing from the scope of the invention as defined in the claims:

Claims: What is claimed is: 1. A clock signal cleaning circuit comprising: an input and an output; and a plurality of delay elements, serially connected between the input and the output; an AND gate having a plurality of inputs and inverting and noninverting outputs; an output of each delay element being connected to a respective input of the AND gate. 2. A clock signal cleaning circuit comprising: a basic unit including a plurality of delay elements, serially connected between the input and the output; and an AND gate having a plurality of inputs and inverting and noninverting outputs; an output of each delay element being connected to a respective input of the AND gate; and a duty cycle recovery module. 3. A clock signal cleaning circuit as claimed in claim 2, wherein the duty cycle recovery module includes an end triggered flip-flop coupled to the output of the basic unit. 4. A clock signal cleaning circuit as claimed in claim 3, further comprising a frequency doubler coupled to the output of the flip-flop. 5. A clock signal cleaning circuit as claimed in claim 2, further comprising a missing clock pulse detection and substitution module coupled to the input of the basic unit. 6. A clock signal cleaning circuit as claimed in claim 5, wherein the missing clock pulse detection and substitution module includes a plurality of second basic units, serially connected via respective noninverting outputs; a plurality of flip-flips connected to respective inverting outputs of a plurality of second basic units; a plurality of AND gates having a plurality of inputs; and an XOR gate connected to the outputs of the AND gates. 7. A method of cleaning a clock signal comprising the steps of: successively delaying a jittery clock signal to generate a plurality of delayed clock signals; and gating the plurality of delayed clock signals together to derive a clean clock signal. 8. A method of cleaning a clock signal as claimed in claim 7, further comprising successively delaying the cleaned clock signal to provide a plurality of delayed clean clock signals, detecting a missing clock pulse in the one of the plurality of delayed clean clock signals, and substituting another of the clock pulses and one of the plurality delayed clean clock signals, and outputting a single clean clock signal without missing clock pulses. 9. A method of cleaning a clock signal as claimed in claim 8, further comprising deriving from the single clean clock signal, a third clock signal having a 50% duty cycle and a frequency of one-half that of the single clean clock signal. 10. A method of cleaning a clock signal as claimed in claim 9, further comprising doubling the third clock signal to generate a fourth clock signal having a frequency equal to that of the single clean clock signal.

Inventors: ARKAS EVAN, ARKAS NICHOLAS, ARKAS, EVAN, ARKAS, NICHOLAS
Applicants: ADVANCED INTELLIGENCE INC, ARKAS EVAN, ARKAS NICHOLAS, ADVANCED INTELLIGENCE INC., ARKAS, EVAN, ARKAS, NICHOLAS
Application year: 1996
Main classification: H04L7
IPC codes: H03K5, H04L7