INTEGRATED SEMICONDUCTOR WAFER PROCESSING SYSTEM

Abstract: An improved apparatus (16, 18, 20, 22, 24, 25) and method which offers an integral pre-strip rinse operation between etching operation and stripping operation. The present invention is designed to allow a semiconductor wafer (A) to undergo sequential processing of dry etching, wet pre-strip rinsing, dry photoresist stripping, and wet final rinsing in a single system.

Description: INTEGRATED SEMICONDUCTOR WAFER PROCESSING SYSTEM Field of the Invention: The present invention relates to a semiconductor wafer processing system and, more particularly, to an improved wafer processing apparatus and method which offers an integral post-etch pre-strip rinse operation. Background of the Invention: Fabrication of integrated circuits requires the formation of conductive paths interconnecting various semiconductor devices in a microchip. These conductive paths may be composed of pure metals, metal alloys, metal composites, or silicon films such as aluminum, polysilicon or tungsten suicide. In a typical process, a layer to be patterned is first deposited on a semiconductor wafer and a layer of photoresist is deposited on top of the underlying deposited layer. Patterns are then formed on the photoresist layer exposing and covering certain areas of the underlying deposited layer creating a photoresist mask. The deposited materials exposed by the open areas of the photoresist mask are conventionally removed by dry plasma etch techniques. Such a dry plasma process leaves behind residues on the photoresist mask and on the underlying deposited layer after the plasma etch. If the residues which remain on the photoresist after the metal etch step are not removed, they will cause corrosion of the underlying metal or a variety of device performance problems. Various approaches have been taken to remove residues and to prevent corrosion, none of which have been completely successful. One solution to the corrosion and residue-problems is to remove the photoresist immediately after the plasma etch step. Many wafer processing systems currently available have integrated an etch module with a photoresist strip module so that wafers can be directly transferred to a strip module for photoresist removal after etching to minimize the chance of corrosion. This practice, however, has a significant drawback. Since photoresist removal is conventionally accomplished by using an oxygen plasma, the residues that remain after the etch step, are converted into insoluble oxides in the plasma, resulting in incomplete photoresist strip, incomplete residue removal, or the need of a prolonged strip process, all of which reduce yield or throughput. Another solution to remedy the corrosion and residue problems is to perform a pre-strip rinsing step in a solvent to remove the water soluble residues which can corrode the underlying metals before photoresist stripping and can cause other undesirable effects. However, in order to perform a pre-strip rinsing step, the wafer must be removed from the etch equipment and rinsed using separate equipment. This process of transferring the wafers between separate processing equipment not only increases overall process time, but it also increases handling and thus the chance of contaminating wafers. Furthermore, using separate equipment for the etching, photoresist stripping, and rinsing processes significantly increases the amount of space required in wafer fabrication facilities. Thus, manufacturers of integrated circuits are faced with the dilemma of either not rinsing their wafers and risking corrosion or rinsing them off-line and thus risking potential contamination and lower throughput due to increased wafer handling. Accordingly, there is a need for a wafer processing system that allows for the sequential processing of a wafer from a dry plasma etch step to a wet pre-strip rinse step in a single system for corrosion control and residue removal. Summary of the Invention: Broadly stated, the present invention is directed to a modular, integrated wafer processing system designed to allow a rinse operation between an etching step and a stripping step. In a preferred embodiment, a semiconductor wafer can undergo sequential processing of dry etching, wet pre-strip rinsing, dry photoresist stripping, and wet final rinsing in a single system. The present invention provides a wafer processing system that achieves corrosion control and residue removal after a dry plasma etch by removing residues on the wafer using a rinsing step prior to photoresist stripping. The pre-strip rinsing step not only prevents corrosion, it also avoids the risk of oxidizing the residues into insoluble oxides during photoresist stripping. As a result, the time required for photoresist stripping is decreased. Furthermore, by performing a pre-strip rinsing step in the same system as the etching step, the present invention eliminates the need to bring the wafers off-line to a separate rinsing station and thus increases wafer fabrication productivity. Additionally, it reduces the total amount of wafer handling, which in turn decreases the chances of wafer contamination. The present invention also eliminates the need for having different types of equipment for etch, pre-strip rinse, photoresist strip and post strip rinse. Instead it provides a single compact, small-footprint system which performs multiple processing functions including pre-strip rinsing within a single system and thereby decreases the space needed in wafer fabrication facilities. The advantages and objectives of the present invention will become apparent to those skilled in the art from the following detailed description of the invention, its preferred embodiments, the accompanying drawings, and the appended claims. Brief Description of the Figures: Fig. 1 is a top plan view, partially schematized, of a wafer processing system. Fig. 2 is a simplified top plan view of the wafer processing system of Fig. 1 showing a wafer in the load lock chamber. Fig. 3 is a simplified top plan view of the wafer processing system of Fig. 1 showing a wafer in the load lock chamber and a wafer in the alignment module. Fig. 4 is a simplified top plan view of the wafer processing system of Fig. 1 showing a wafer in the load lock chamber and a wafer in each of the two etch modules. Fig. 5 is a simplified top plan view of the wafer processing system of Fig. 1 wherein a wafer previously in the load lock chamber has been transferred to the alignment module. Fig. 6 is a simplified top plan view of the wafer processing system of Fig. 1 wherein a wafer previously in an etch module has been transferred to the strip module and then to the rinse module. Fig. 7 is a simplified top plan view of the wafer processing system of Fig. 1 wherein a wafer previously in the rinse module has been transferred back to the strip module. Fig. 8 is a simplified top plan view of the wafer processing system of Fig. 1 wherein a wafer previously in the strip module has been transferred to the rinse module. Fig. 9 is a simplified top plan view of the wafer processing system of Fig. 1 wherein a wafer previously in the rinse module has been transferred to an exit wafer cassette. Fig. 10 is a simplified top plan view of the wafer processing system of Fig. 1 wherein a wafer previously in an etch module has been transferred to the strip module and a wafer previously in the alignment module has been transferred to an etch module. Detailed Description of the Preferred Embodiment: Fig. 1 illustrates a preferred embodiment of a system in accordance with the present invention. The system includes a vacuum load lock chamber 16, an alignment module 18, two etch modules 20 and 22, and a strip module 24, all of which are connected to a central vacuum chamber 26 through a closable opening and are operated by a computer process control system (not shown) . Load lock chamber 16 houses an internal cassette elevator for holding a wafer cassette (entry cassette). Vacuum chamber 26 has a robotic wafer handling system 38 for transferring wafers from one chamber or module to another. Strip module 24 is connected to an atmospheric robotic wafer handling system 32 through a closable opening 27, which in turn is connected to rinse module 25 and atmospheric cassette module 34 (exit cassette). An example of a typical rinse module used is the Semitool Equinox rinse system. Atmospheric robotic wafer handling system 32 services the atmospheric cassette module 34 which holds wafers after the completion of processing. In addition, the second robotic wafer handling system 32 transfers wafers between strip module 24 and rinse module 25. During the rinsing process, rinse module 25 and robotic handling system 32 are designed to maintain the degree of wafer alignment required by strip module 24 for stripping. The operation of the present invention is automated and programmable through a computing system. Figs. 2-10 illustrate the general processing steps performed by the preferred embodiment of the invention. Fig. 2 shows a wafer that has been loaded onto a vacuum cassette elevator in load lock chamber 16. Once the load lock chamber 16 has been pumped down to vacuum, gate valve 37, situated between load lock chamber 16 and central vacuum chamber 26 opens and provides access by central robot arm 38 to the wafer cassette in load lock chamber 16. Central robot arm 38 transfers a wafer (A) from load lock chamber 16 into alignment module 18 whereby a theta alignment is performed on the wafer as illustrated in Fig. 3. The wafer is then transferred to a first etch module 20 through closable opening 40 for etching. While the first wafer is being etched in module 20, central robot arm 38 picks up a second wafer (B) from the wafer cassette in load lock chamber 16 and transfers it to alignment module 18 for theta alignment. Once the alignment is completed, wafer B is transferred into a second etch module 22 through closable opening 42 as illustrated in Fig. 4. While wafers A and B are still in the respective etch modules, the central robot arm 38 picks up a third wafer (C) from the wafer cassette in load lock chamber 16 and transfers it into alignment module 18 for theta alignment as illustrated in Fig. 5. When the etch for the first wafer (A) is completed, central robot arm 38 removes the wafer through closable opening 40 and places it in strip module 24 through closable opening 44. No processing is performed in the strip module at this point. Once closable opening 44 is closed and sealed, strip module 24 is vented to atmospheric pressure. While strip module 24 is venting, central robot arm 38 picks up wafer C in alignment module 18 and transfers it to first etch module 20 through closable opening 40. While wafer C is being etched in first etch module 20, central robot arm 38 picks up a fourth wafer (D) from the wafer cassette in the load lock chamber and transfers it to alignment module 18 for theta alignment. Operating in parallel, once strip module 24 has been vented to atmosphere, closable opening 27 situated between atmospheric robot arm 32 and strip module 24 opens, allowing atmospheric robot arm 32 to transfer wafer A from strip module 24 to rinse module 25 as shown in Fig. 6. Wafer A then undergoes a pre-strip rinse step and a spin-dry step in rinse module 25. Once rinsing and drying is completed, atmospheric robot arm 32 transfers wafer A from rinse module 25 back to strip module 24 through closable opening 27 as illustrated in Fig. 7. After opening 27 is closed, strip module 24 is pumped down to vacuum and an oxygen plasma is used to strip the photoresist on the wafer. Once photoresist stripping is completed, strip module 24 is again vented to atmosphere. When venting is completed, atmospheric robot arm 32 transfers the wafer from strip module 24 to rinse module 25 for a final rinse and dry step through closable opening 27 as illustrated in Fig. B. After the wafer is rinsed and dried, atmospheric robot arm 32 transfers it to exit wafer cassette 34 as illustrated by Fig. 9. This sequence of processing steps encompassing pre-strip rinse, strip, and rinse, then repeats for wafer B in second etch module 22 which is transported by central robot arm 38 through closable opening 42 and placed in strip module 24 through closable opening 44 as in Fig. 10. While the present invention has been described in connection with specific embodiments, ' the present invention is not limited to such embodiments and encompasses modifications and equivalent arrangements within the scope of the appended claims. For example, while the preferred embodiment contemplates two etch modules, the benefits are obtained irrespective to the number of etch modules.

Claims: WHAT IS CLAIMED IS: 1 . A semiconductor processing system comprising: a. a central vacuum chamber; b. a vacuum load lock chamber, having at least one closable opening, connected to said central vacuum chamber; c. an etch module, including a reaction chamber and at least one closable opening, connected to said central vacuum chamber; d. a strip module, including a reaction chamber and at least one closable opening, connected to said central vacuum chamber; e. a rinse module, accessible to said strip module; and f . transfer means for transporting a semiconductor wafer from said rinse module to said strip module. 2. The semiconductor processing system of claim 1 further comprising second transfer means for transporting said semiconductor wafer between said load lock chamber, said etch module, and said strip module. 3. The semiconductor processing system of claim 1 wherein said transfer means operates at atmospheric pressure. 4. The semiconductor processing system of claim 1 wherein said strip module further comprising a resistively heated wafer chuck. 5. The semiconductor processing system of claim 1 wherein said rinse module comprising means of spraying liquids. 6. The semiconductor processing system of claim 1 wherein said rinse module comprising means for drying said semiconductor wafer. 7. A method for treating a semiconductor wafer in a wafer processing apparatus comprising the steps of: a. removing a material on said semiconductor wafer in an etch module of said apparatus; b. rinsing said semiconductor wafer in a rinse module of said apparatus subsequent to said removing step; and c. removing a mask material on said semiconductor wafer in a strip module of said apparatus. 8. The method of treating a semiconductor wafer of claim 7 further comprising a step of rinsing said semiconductor wafer in said rinse module subsequent to said mask removal step. 9. The method for treating a semiconductor wafer of claim 7 wherein said material removal step, said rinsing step, and said mask removal step are automated by a user-programmable computing means. 10. A method for treating a semiconductor wafer in a wafer processing apparatus comprising the steps of: a. rinsing said semiconductor wafer in a rinse module of said apparatus prior to a mask removal step; b. transferring said wafer from said rinse module to a strip module by a transfer means; and c. removing a photoresist layer on said semiconductor wafer in said strip module of said apparatus. 1 1 . The method for treating semiconductor wafer of claim 10 further comprising a step of rinsing said semiconductor wafer in said rinse module of said apparatus subsequent to said photoresist removing step. 12. The method for treating a semiconductor wafer of claim 10 wherein said transfer means is adapted for transporting said semiconductor wafer from said strip module to said rinse module. 13. The method for treating a semiconductor wafer of claim 10 wherein said transfer means is adapted for transporting said semiconductor wafer from said rinse module to said strip module. 14. The method for treating semiconductor wafer of claim 10 wherein said transfer means is adapted for operating at atmospheric pressure. 1 5. The method for treating semiconductor wafer of claim 7 or claim 10 wherein said rinse module comprising means of treating said wafer with various solutions. 16. The method for treating semiconductor wafer of claim 7 or claim 10 wherein said rinse module comprising means of drying said semiconductor wafer. 1 7. The method for treating semiconductor wafer of claim 7 or claim 10 wherein said rinsing step, said transferring step, and said removing step are automated by a user-programmable computing means. 18. A semiconductor etch processing system comprising: a. a vacuum chamber; b. an etch module selectively communicable with said vacuum chamber; c. a strip module selectively communicable with said vacuum chamber; and d. a rinse module, accessible to said strip module. 19. The system of claim 18 adapted for handling a semiconductor wafer, said system including: a transfer device that can sequentially transfer a wafer (1 ) from the strip module to the rinse module so that the wafer can be rinsed, and (2) from the rinse module back to the strip module so that a photoresist layer can be removed. 20. The system of claim 19 wherein: said transfer device can further sequentially transfer a wafer from the strip module after a photoresist layer has been removed to the rinse module where the wafer can again be rinsed. 21 . The system of claim 18 wherein: said system is comprised of an integrated modular semiconductor etch processing system. 22. A method for treating a semiconductor wafer in wafer etch processing apparatus comprising the steps of: a. rinsing said semiconductor wafer prior to a photoresist layer removal step; b. removing a photoresist layer on said semiconductor wafer. 23. The method for treating semiconductor wafer of claim 22 further comprising a step of: c. rinsing said semiconductor wafer subsequent to said photoresist removing step. 24. The method of claim 22 including: performing steps (a) and (b) in an integrated wafer etch processing apparatus. 25. The method of claim 22 including: performing steps (a) and (b) in a modular wafer etch processing apparatus. 26. The method of claim 23 including: performing steps (a), (b), and (c) in an integrated wafer etch processing apparatus. 27. The method of claim 23 including: performing steps (a), (b), and (c) in a modular wafer etch processing apparatus. 28. The method of claim 23 wherein steps (a) and (c) are performed in the same rinse chamber.

Inventors: DEORNELLAS STEPHEN PAUL, DEORNELLAS, STEPHEN, PAUL
Applicants: TEGAL CORP, TEGAL CORPORATION
Application year: 1996
Main classification: H01L21
IPC codes: H01L21