ARRANGEMENT AND METHOD RELATING TO DIGITAL INFORMATION

Abstract: The present invention relates to a logic circuit arrangement comprising signal input means and signal output means (1, 2) (respectively) and a number of SFQ circuits comprising Josephson junctions wherein carrier means are used for carrying digital information. SFQ circuits comprising Josephson junctions are sampled at the input/output for producing DC voltages and a train comprising at least two single flux quanta is used as carrier means for information and phase locking between at least two Josephson junctions is used to provide at least two different dynamic states of which at least one provides an output signal.

Description: TITLE ARRANGEMENT AND METHOD RELATING TO DIGITAL INFORMATION. TECHNICAL FIELD The present invention relates to a logic circuit arrangement which comprises signal input means and signal output means and flux quanta circuits comprising Josephson junctions. The flux quanta are used for carrying digital information. The invention also relates to an arrangement for processing digital information comprising a number of logic elements, for example one or more of any combination of AND elements, OR elements and NOT elements each of which comprises input and output means and wherein single flux quanta are used as carriers of digital information. Still further the invention relates to a method for stabilizing a logic circuit arrangement comprising a number of logic elements using flux quanta as information carriers. STATE OF THE ART Most common today are semiconductor-transistor-based integrated circuits. In semi-conductor logic, digital information is represented as voltage levels wherein the voltage level differences are determined by the electronic band gap. However, circuits based on semiconductor logic have a limited frequency of operation, i.e. it is not as high as could be desired for a number of applications and moreover the power dissipation is not as low as sometimes wanted or needed. This means that for a number of applications these values are not satisfactory. Therefore a considerable amount of research within superconducting electronics has been done and among others a Rapid Single Flux Quantum (RSFQ) circuit family has been developed. This is based on superconductor integrated circuits and use Josephson junctions. Josephson junction technologies as such have been found advantageous for digital applications among others since the intrinsic switching speed of Josephson junctions is very high, such as around a few picoseconds. Moreover the power dissipation is low and the fabrication technologies are simple as compared to semiconductor transistors for corresponding devices. In "RSFQ Logic/Memory Family: A New Josephson-Junction Technology for Sub-Teraherz-Clock-Frequency Digital Systems" by K.K. Likharev and V.K. Semenov in IEEE Transactions on Applied Superconductivity, Vol 1, No 1, March 1991 a rapid single flux quantum (RSFQ) circuit family is presented where the logic is based on processing of single flux quanta wherein each digital information bit is represented by a single flux quantum or a fluxon. Therefore it is, particularly at higher frequencies, easily subjected to bit errors and SFQ-to-DC converters are required as input/output interfaces of an RSFQ chip. These converters serve the purpose of converting digital voltage levels to SFQ pulses and vice versa. The circuit is fully superconducting and the RSFQ logic requires a better magnetic field shielding the larger the circuit is in order to provide shielding from external magnetic fields. In "SAIL High Temperature Superconductor Digital LOGIC: Improvements and Analyses" by S.M. Schwarzbek et al in IEEE Transactions on Applied Superconductivity, Vol. 3 No 1, March 1993, another SQUID based scheme, a so called Series Array Interferometer Logic, (SAIL) is provided. This logic has similarities with CMOS but it suffers from not being fast enough to compete with the fastest (at room temperature) semiconductor logic circuits. Moreover flux flow transistor based logic (SFFT) is attractive in so far as it is dual to Field Effect Transistor (FET) logic, but it is inherently slow compared with the RSFQ logic and moreover the power dissipation is several orders of magnitude higher. Moreover single flux quanta (SFQ) based circuits are known wherein the SFQs are used as digital carriers. However, then resistors are used for the interconnection of active elements. The circuit parameters of these devices have very small margins. The above mentioned RSFQ logic, although being comparatively fast and having a comparatively low power dissipation, still leaves a lot to desire among others as far as speed and power dissipation is concerned. Moreover, elements based on this logic require additional equipment in order to interface with for example semiconductor circuits since digital voltage levels have to be converted to SFQ pulses and vice versa. SUMMARY OF THE INVENTION Therefore a logic circuit arrangement is needed through which a still higher frequency of operation is enabled. Further still a logic circuit arrangement is needed wherein the power dissipation can be still further reduced. Moreover a logic circuit arrangement is needed which can be easily interfaced with for example logic semiconductor circuits, particularly without requiring any additional components. Generally a logical circuit arrangement is needed which is fast, easy and cheap to fabricate and which can easily be combined with other circuits or circuit arrangements of the same or different kinds. Therefore a logic circuit arrangement as initially referred to is provided which comprises a number of Josephson junctions which are so arranged that mutual phase locking between the Josephson junctions is used for providing an output signal wherein a train of single flux quanta are used as digital information carriers. The logic digital information is represented as voltage levels (like in semiconductor logic) which facilitates interfacing with semiconductor circuits. The voltage level difference is here determined by the superconducting pairing energy which is given b the I^-product of the employed Josephson junctions which are shunted or unlatching, i.e. overdamped unlike in semiconducto logic wherein the voltage level differences are determined by th electronic band gap. This makes the arrangements according to the present invention easy to interface with semiconductor circuits. Particularly, in order to provide a still faster operation of the logic circuit arrangement, the Josephson junctions may be directl connected, i.e. without requiring any converting arrangements etc. Particularly voltage supply means may be provided (connected), which advantageously are superconducting, to the circuit arrangement or particularly to every logic element of the circuit arrangement in order to provide a standard voltage output. According to various advantageous embodiments, the logic circuit element may comprise an AND element, an OR element and an NOT element respectively or any combination thereof. Advantageousl superconducting signal input/output means are used which even more particularly may be high temperature superconducting. Further advantageous embodiment are given by the appended subclaims. Moreover an arrangement for processing of digital information as initially referred to is provided. The input/output means comprises superconductors, in a most advantageous embodiment high temperature superconductors, and to each logic element a voltage supplying means is connected for supplying every circuit or logic element with substantially the same voltage and wherein each logic element or circuit comprises a number of Josephson junctions which are so arranged that via phase locking of flux quanta between two or mor Josephson junctions, the output signals are provided, the type of the signal being given by the particular Josephson junctions involved in the phase locking. The Josephson junctions are shunted and a train of fluxons (at least two) acts as digital carrier. The effect of mutual phas locking between Josephson junctions is used, this is furthe described in A.K. Jaine, K.K. Likharev, J.E. Lukens et al, in "Mutual Phase-Locking in Josephson Junction Arrays", Phys. Report., 109, 1984, pp 309-426 which is incorporated herein by reference. Mutual phase locking intrinsically requires more than one SFQ pulse and therefore a train of fluxons is used, the minimum being two fluxons. Physically each Josephson junction can be seen as a frequenc . oscillator and when two or more of said oscillators interact, this leads to a mutually phase locked state. Digital information is presented as one of a number of different dynamic states (particularly two) characteristic for the given kind of information. In order to use the phase locking more than one fluxon is required as discussed above. Phase locking as such represents a complicated dynamic state and in order to provide a standard voltage output, advantageously (superconducting) voltage supply means are used. According to the present invention, different dynamical states are thus used to present different kinds of digital information. Advantageously the invention relates to a logical circuit arrangement comprising a high number of logical elements in any desired combination and particularly it relates to large scale (LSI) or very large scale integrated circuits (VLSI). Actually the invention provides for an entirely new superconducting logic family through which substantially any logic element can be built or provided as well as any combination of logical elements. It is an advantage of the invention that the arrangements are easy to interface with among others semiconductor circuits since logic, digital information in both cases is represented as voltage levels. It is also an advantage of the present invention that it enables a high maximum operation frequency which for example may be about 200 GHz or even more. Another advantage of the invention is that the power dissipation per logic element is very low such as for example of the order of magnitude of about 10 ~6 J. Another advantage is that the logic is less sensitive to external magnetic fields than for example RSFQ circuit. Thus the logic circuit arrangements according to the invention are simpler and require less complicated magnetic shielding than hitherto known circuit arrangements which is particularly advantageous for large circuits or even very large circuits (LSI and VLSI respectively). BRIEF DESCRIPTION OF THE DRAWINGS The invention will in the following be further described in a non¬ limiting way under reference to the accompanying drawings in which: FIG 1 schematically illustrates a logical NOT element, FIG 2 illustrates a diagram on simulation results of a N O element illustrating input and output voltage versus switching time, FIG 3a illustrates simulation results of input voltage versus time, FIG 3b illustrates the output voltage corresponding to the input voltage of Fig 3a and FIG 4 schematically illustrates an equivalent circuit of an OR/AND element. DETAILED DESCRIPTION OF THE INVENTION The logic family as suggested by the present invention comprises logical circuit arrangements which may comprise different logic elements such as so called NOT elements, OR elements and AND elements as well as any combination thereof. Such logical elements or logical circuit arrangements comprise single flux quanta hereinafter referred to as SFQ circuits. These are sampled at the input/output in order to produce DC voltages. Generally these logical circuit arrangements or logical elements have the advantages (at least) as far as speed and low power dissipation of RSFQ circuits as referred to above are concerned and moreover they have the advantages of Josephson transmission lines, at least in the cases when input/output means comprises superconductors as far as SFQ energy amplification and noise discrimination is concerned. For comparatively low frequency applications, alternatively to Josephson transmission lines superconducting microstrip lines can be used as will be discussed below. The sampling of a sufficiently high number of SFQ pulses (the number will be further discussed below) makes the arrangements robust, i.e. they have a low bit error rate (BER), as compared to that of semiconductor voltage stage logic and they are also easily interfaceable with semiconductor circuits as discussed above. The speed of the logic is defined by the minimum number of fluxons needed, for example two or three (n=2-3) to be sampled by an element to attain (or switch to) a stable voltage level. Furthermore the critical current of the Josephson junctions can be reduced since the information is stored in form of a voltage. Sometimes there is a contradiction between a low bit error rate (BER) and speed but since for the superconducting junctions, or in particularly advantageous embodiments high temperature superconducting Josephson junctions, the I c R n value is high, it does not matter that the speed is somewhat lowered for the provision of a still lower BER. The I c R n value or product is the critical current times the normal resistivity which means the resistivity under normal conditions. The operational frequency of a logic element or a logic circuit arrangement may be about I c R n Φ 0 "1 /n or approximately 200 GHz or even more, particularly for HTS based circuits. This is for example much higher than that of the SAIL logic referred to above and the fact that advantageously direct connections are used, which means that no transformers are used between Josephson junctions in the SFQ logic elements, also contributes in providing high speed. Thus a voltage state logic is provided which is based on sampling of single flux quanta or fluxons which are phase locked between the signal input and output means of the SFQ circuits. Fig. 1 illustrates an equivalent circuit of a logical circuit arrangement according to the invention which comprises a NOT element. The NOT element comprises signal input means 1 and signal output means 2. Advantageously the input and output means 1,2 respectively comprise Josephson transmission lines although for relatively low frequencies they may e.g. be exchanged through superconducting microstrip lines. In a most advantageous embodiment the Josephson transmission lines comprise a high temperature superconducting material although this is not necessary. 3 l r J 4 indicate Josephson junctions connected to the signal input and output means 1,2 respectively. A separate superconducting voltage supply means 3 supplies a standard voltage to the Josephson junction J 5 and causes it to generate the corresponding Josephson frequency which is an essential feature. The voltage supply means (connected to a voltage source) comprises e.g. a conventional superconducting wiring with one Josephson junction e.g. at the end thereof. The fact that no complicated design is actually needed is a further advantage of the present invention. An active circuit means forming an interferometer comprises a.o. the Josephson junctions J 2 ,J 3 and the inductor ^ which prevents penetrations of the fluxons from the signal output voltage means 2 to the signal input voltage means. Advantageously all the Josephson junctions as indicated in the figure are biased with DC currents (in a manner known per se) which however are not illustrated in the figure. Also the inductor L x is biased with a DC current. If the needed frequencies are particularly high or the highest available frequencies, the Josephson junctions J l f J 4 can be seen as a continuation of the input/output means or particularly the Josephson transmission lines (JTL) if such are used which in practice means that they simply can be seen as parts of the Josephson transmission lines 1,2. However, generally the NOT element according to the invention works as follows: The bias current I 3 (which means the bias current for the Josephson junction J 3 ; generally the same numbers are used for a Josephson junction and its biasing current) is large enough to generate a voltage at the output of the logic circuit arrangement, here particularly the NOT element, in the absence of any input voltage which corresponds to a logic "0". The voltage supply means 3 supplies a standard voltage to the Josephson junction J 5 and causes it to generate the corresponding Josephson frequency as mentioned above. Mutual phase locking (as described in the reference referred to above "Mutual Phase Locking in Josephson Junction Arrays") between oscillations in the Josephson junction J 5 and the oscillations in the output junctions J 2 and J 3 is provided by the resistor R 2 connected between the voltage supplying means 3 and the output means 2. This is sampled or read as the standard voltage corresponding to logic "1" on the output of the NOT element. The inductor L 1 prevents a penetration of the fluxons from the output to the input as also discussed above. An input voltage (logic "1") through the link R^L., ^ produces a phase shift in the interferometer formed by a J 2 ,J 3 and ^ and switches it to the zero voltage state giving a logic zero "0" at the output. The fast switching is provided by the SFQ interaction through the inductor L x and the resistor R x . For illustrative purposes some examples on values will be given (for one particular embodiment) for the resistors, inductors etc. The resistor R 2 may for example have a resistance of 10Ω and the inductors L x and L 2 may have inductances of 3.9pH. As referred to above all Josephson junctions are biased with DC currents which for example may take the following values I 1 =0.2mA, I 3 =0,462mA, I 4 =0.2mA and the inductance of the inductor L x may be biased with the current I L =0, 177mA. These examples are of course merely given as examples and should in no way be interpreted as limitative on the scope of the present invention. Figs. 2,3a and 3b show simulation results of a NOT element according to the invention. The Josephson junction parameters that are used are the following: V c =lmV, R n =4Ω, I c =0,25mA, β c =0 for all the junctions. The digital voltage unit is 0,375mV. Fig 2 indicates that in fact only two fluxons are needed for switching and that the time delay is about lOps corresponding to approximately 100GHz. In case high temperature superconducting materials are used for the Josephson junctions V c could be increased to about lOmV which might reduce the time scale more or less by a factor 10 which means that the operational frequency could be increased to ITHz. In Fig. 2 a dashed line indicate output whereas a continuous line . indicate input voltage. Instantaneous voltages of the Josephson junction on input/output are shown. Each pass means a fluxon through the junction. The average voltage can be measured and is used for storing digital information. A stream of single flux quanta produces an average voltage across the Josephson junctions. Fig. 4 illustrates an equivalent circuit for a combined OR and AND element. Of course these elements are provided separately. In this case β c =0 wherein βc = Ic R " c β c being the McCumber parameter, I c the critical current of the junction, R n the normal resistance, C the capacitance, e the charge of the electron and h the Plank constant and V c =lmV (=I c R n ). This circuit operates in a way which is quite similar to that of the RSFQ circuit as described in the reference by Likharev as discussed above. One important difference is that a loss (or gain) of one single fluxon in this case is not important since the minimal duration for a voltage pulse is two or more fluxons. Depending on the values of the critical currents and the bias currents (which are not indicated in the figure) of the junctions, the herein illustrated circuit can operate both as an OR element and as an AND element. The circuit comprises first signal input means la and second signal input means lb. Furthermore it comprises signal output means 2. As discussed above under reference to the NOT element, these input and output means respectively may comprise a superconducting material or particularly a high temperature superconducting material. Advantageously they comprise Josephson transmission lines JTL. The logic circuit arrangement operates as follows: If there is a voltage ("1") on but one of the input means la or lb and the corresponding train of fluxons can switch the Josephson junction J 3 thus giving a voltage on the output, it constitutes an OR element. If on the other hand, a voltage ("1") is needed from both inputs means la,lb in order to switch the Josephson junction J 3 , it constitutes an AND element. In Fig. 4 no voltage supply means corresponding to the ones of Fig. 1 are indicated. These are not necessary, but on the other hand it can be useful to supply a voltage via voltage supply means also in this case, among others in order to increase the stability of the elements and the above discussion relating to the voltage supply means (3) is relevant also here. Josephson junctions Jι,J 6 ar e connected to the first and the second input means whereas the Josephson junction J 5 is connected to the output means. If the arrangement operates as an OR element, there is a voltage input on the first la or the second input lb, and the corresponding Josephson junction provides a phase locking to Josephson junction J 5 . If it operates as an AND element and there are input signals both on the first and the second input means la, lb, Josephson junctions Jχ,j 6 and J 3 provide a phase locking to J 5 . With the above mentioned elements (AND, OR, NOT) practically every logic element circuit can be built. According to the invention a logical circuit arrangement or an arrangement for processing digital information may comprise a large circuit comprising various combinations of the above mentioned elements. Then advantageously all parts the of the circuit operate on one and the same frequency and this is particularly provided through supplying every circuit or logic element with a standard supply voltage as discussed above. Thus, using the logical family of the present invention considerably facilitates the fabrication of large circuits. With the use of voltage supply means (superconducting) and via using the phase locking, is possible to stabilize such large circuits. Also in a number of other aspects the invention can be varied without departing from the scope thereof.

Claims: CLAIMS 1. Logic circuit arrangement comprising signal input means (l;la,lb) and signal output means (2) and a number of single flux quantum circuits comprising Josephson junctions wherein carrier means are used for carrying digital information c h a r a c t e r i z e d i n , that single flux quantum circuits comprising Josephson junctions are sampled at the input/output for producing DC voltages and in that a train comprising at least two single flux quanta is used as carrier means for carrying information and in that via phase locking between at least two Josephson junctions at least two different dynamic states are available of which at least one provides an output signal. 2. Logic circuit arrangement according to claim 1, c h a r a c t e r i z e d i n , that the Josephson junctions of the single flux quantum circuits are so arranged that at least two dynamic states are available and in that the provision of an output signal is given/decided by the phase locking between the Josephson junctions of the different single flux quantum circuits. 3. Logic circuit arrangement according to claim 1 or 2, c h a r a c t e r i z e d i n , that input digital information is stored as a voltage. 4. Logic circuit arrangement according to anyone of the preceding claims, c h a r a c t e r i z e d i n , that at least one Josephson junction is arranged connecting to each of the input/output means respectively, between which a circuit means comprising a number of Josephson junctions is arranged. 5. Logic circuit arrangement according to claim 4, c h a r a c t e r i z e d i n , that voltage supplying means (3) is connected to the active circuit means, to which means (3) a further Josephson junction (J 5 ) is connected. 6. Logic circuit arrangement according to anyone of the preceding means, c h a r a c t e r i z e d i n , that the input/output means (1; la, lb;2) comprises a superconductor. 7. Logic circuit arrangement according to claim 6, c h a r a c t e r i z e d i n , that the superconductor is a High Temperature Superconductor (HTS). 8. Arrangement according to anyone of claims 6-7, c h a r a c t e r i z e d i n , that the input/output means (1;la,lb;2) comprise Josephson Transmission Lines (JTL). 9. Logic circuit arrangement according to claim 5, c h a r a c t e r i z e d i n , that the voltage supplying means (3) comprises a conventional superconducting wiring. 10. Logic circuit arrangement according to anyone of claims 6-8, c h a r a c t e r i z e d i n , that the input/output means (1;la, lb;2) and/or the voltage supplying means (3) comprise(s) a microstrip line. 11. Logic circuit arrangement according to anyone of the preceding claims, c h a r a c t e r i z e d i n , that it comprises at least one OR element. 12. Logic circuit arrangement according to anyone of claims 1-10, c h a r a c t e r i z e d i n , that it comprises an AND element. 13. Logic circuit arrangement according to anyone of the preceding claims, c h a r a c t e r i z e d i n , that it comprises an element which can be used as an AND element or an OR element wherein the requirements for producing an output signal gives whether it operates as an AND element or an OR element. 14. Logic circuit arrangement according to anyone of claims 11-13, c h a r a c t e r i z e d i n , that it comprises at least first and second signal input means (la, lb). 15. Logic circuit arrangement according to claim 14, c h a r a c t e r i z e d i n , that in order to provide an output voltage over the output means (2) a voltage input only on one of the input means (la, lb) which is represented by a train of single flux quanta which are able to switch a Josephson junction (J 3 ) of the active circuit means, is required to provide an output voltage signal, and in that it operates as an OR element. 16. Logic circuit arrangement according to claim 14, c h a r a c t e r i z e d i n , that in order to provide an output signal, input signals on both input means (la,lb) are required and in that it operates as an AND element. 17. Arrangement according to anyone of claims 11-16, c h a r a c t e r i z e d i n , that at least one voltage supplying means (3) to which a Josephson junction (J 5 ) is connected, is connected to at least a number of logic elements (AND,OR,NOT) comprised by the circuit. 18. Logic circuit arrangement according to claim 17, c h a r a c t e r i z e d i n , that a voltage applied via a first input means (la) or second input means (lb) or via a first and a second input means (la,lb) locks the quantum mechanical phase difference across the Josephson junction (J 5 ) of the output means. 19. Logic circuit arrangement according to anyone of claims 1-10, c h a r a c t e r i z e d i n , that a Josephson junction (J lr J 4 ) is connected to the input and output means (1;2) respectively between which an active circuit means comprising at least one Josephson junction is arranged and to which a voltage supplying means (3) is connected over a resistor (R 2 ) and to which at least one Josephson junction (J 2 ,J 3 ) is connected and in that it comprises a NOT element. 20. Logic circuit arrangement according to claim 19, c h a r a c t e r i z e d i n , that the circuit means comprises a highly non-linear means (J 2 ,J 3 ,L 1 ) and in that in the absence of any input signal representing a first dynamical state, an output signal is provided whereas through the active highly non-linear circuit means all single flux quanta are eliminated in case of an input voltage signal thus representing a second dynamical state. 21. Logic circuit arrangement according to claim 20, c h a r a c t e r i z e d i n , that the circuit means comprises an interferometer comprising two Josephson junctions (J 2 , J 3 ) and an inductor (L x ) . 22. Logic circuit arrangement according to anyone of claims 20-22, c h a r a c t e r i z e d i n , that via the resistor (R 2 ) between the voltage supply means (3) and the circuit means and a set standard voltage on the output means is provided for mutual phase locking between the Josephson junction (J 5 ) connected to the supply voltage means (3 ) and the Josephson junctions (J 2 , J 3 ) of the circuit means. 23. Logic circuit arrangement according to claim 22, c h a r a c t e r i z e d i n , that the circuit means comprises an inductor ( L-. ) for preventing penetration of single flux quanta from the output means (2) to the input means (1) . 24. Logic circuit arrangement according to anyone of claims 22-23, c h a r a c t e r i z e d i n , that an input voltage through a first resistor (R-.) and an inductor (L- L ) of the interferometer produces a phase shift of the interferometer (J 2 , J 3 , L x ) and switches it to a zero voltage state giving a logical zero output signal. 25. Logic circuit arrangement according to anyone of the preceding claims, c h a r a c t e r i z e d i n , that at least a number or preferably all Josephson junctions are shunted (overdamped) . 26. Logic circuit arrangement according to anyone of the preceding claims, c h a r a c t e r i z e d i n , that at least some of the Josephson junctions are directly connected, i.e. without any transformers or similar. 27. Arrangement for processing digital information comprising a number circuits or logic elements such as one or more of AND and/or OR and/or NOT elements of which each comprises input (l;la,lb) and output means (2) , c h a r a c t e r i z e d i n , that the input/output means comprise superconductors wherein to each element a superconducting voltage supplying means is connected for supplying every circuit or logic element with substantially the same voltage wherein each circuit or logical element further comprises a number of Josephson junctions which are so arranged that phase locking conditions of single flux quanta between the Josephson junctions provide/prevent the output signals of the logic elements/circuits. 28. Arrangement according to claim 26 or 27, c h a r a c t e r i z e d i n , that phase locking between different Josephson junctions provide different dynamic states. 29. Arrangement according to anyone of claims 23-28, c h a r a c t e r i z e d i n , that as carrier for digital information a train of fluxons is required. 30. Arrangement according to anyone of claims 26-29, c h a r a c t e r i z e d i n , that digital information is represented as voltage levels wherein the difference between voltage level is given by the I c R n -product of involved Josephson junctions. 31. Method for stabilising large digital logic circuits comprising a number of logic elements each comprising a number of Josephson junctions comprising the steps of supplying to each logic element substantially the same voltage and using phase locking between Josephson junctions of each respective element to provide the relevant output signal of the respective logic element. 32. Method according to claim 31, wherein the digital information is represented as voltage levels and where input voltage is converted into a train of single flux quanta at least comprising two single flux quanta by a Josephson junction.

Inventors: KAPLUNENKO VSEVOLOD, WIKBORG ERLAND, KAPLUNENKO, VSEVOLOD, WIKBORG, ERLAND
Applicants: ERICSSON TELEFON AB L M, KAPLUNENKO VSEVOLOD, WIKBORG ERLAND, KAPLUNENKO, VSEVOLOD, TELEFONAKTIEBOLAGET LM ERICSSON (PUBL), WIKBORG, ERLAND
Application year: 1996
Main classification: H03K19
IPC codes: H03K19