Vertical bipolar power transistor with an integrated sensing resistor

Abstract: A vertical structure, integrated bipolar transistor incorporating a current sensing resistor, comprises a collector region (1), a base region (3) overlying the collector region, and an emitter region over the base region. The emitter region comprises a buried region (5), a surface region (7), and a first vertical diffusion region (6) connecting the buried layer (5) to the surface region (7). A second vertical diffusion region (8) connects the buried emitter layer (5) periphery to a first surface contact (11), while the surface emitter region (7) is contacted, along three peripheral sides thereof, by a second surface contact (10). The transistor current flows from the substrate (1), through the base (3) to the buried emitter region (5). It is then conveyed into the vertical region (6), which represents a resistive path (R1), and on reaching the surface region (7) splits between two resistive paths (R2) included between the vertical region (6) and the surface contacts (10). These resistive paths form in combination the current sensing resistor incorporated to the transistor, whose terminals are led to the first (11) and second (10) surface contacts, respectively.

Description: Field of the Invention This invention relates to a vertical structure, bipolar power transistor integrated on a semiconductor material substrate and incorporating an emitter current sensing resistor. Background Art A vertical structure, bipolar power transistor comprises a substrate of the N+ type overlaid by an N- epitaxial layer wherein an isolation well of the P type is formed whose ends are flush with the device surface. The substrate provides the transistor collector, while the isolation well, contacted at the device surface, provides the transistor base. The emitter region usually consists of one or more regions of the N+ type formed within the well P and being contacted at the surface by conduction paths referred to as the metallizations, or briefly the "metals". The current through a power transistor is sensed by measuring the voltage drop across a resistor, generally provided in series with the emitter terminal, the voltage drop being due to the current flowing through the transistor. This resistor, known as the "sensing" resistor, is usually integrated to the device in an area close to that of the power transistor, or alternatively, formed by modifying somewhat the transistor structure, as shown in Figures 1, 2 and 3. Figure 1 is a plan view of a prior power transistor incorporating a sensing resistor. Also shown in the figure are the base and emitter metallizations 10 and 11, respectively, in contact with corresponding buried regions, not illustrated in the figure. A sensing resistor 12 is formed from a metallization section placed in series with the emitter contact 13. A current is caused to flow through the metallization section 12 which is proportional to the total emitter current and produces a voltage drop that can be easily sensed, e.g. by means of two contacts 14 and 15 as shown in the figure. Figure 2 is a plan view of another prior power transistor, also incorporating a sensing resistor. A base metallization 20 and emitter metallization 21 contact here corresponding buried base and emitter regions, not illustrated in the Figure. The emitter region is split into plural zones, referred to as the emitter "fingers" on account of their peculiar shape and which are connected together by the emitter metal 21. The emitter current is measured here by measuring, through contacts 24 and 25, the difference of potential across the metallization of an emitter finger 22. Figure 3 is a plan view of a further prior power transistor to which a surface diffused sensing resistor Rs has been incorporated. In particular, in order to take a measurement of emitter current, the difference of potential across a diffused resistor Rs, being placed in series with an emitter portion and similarly doped, is measured. Two base metallizations 30 and an emitter metallization 31 contact respective base and emitter regions. The active region 32 of the emitter is contacted by means of a first contact C1 and a metallization 34, while the resistor Rs is contacted by means of a second contact C2 and a metallization 35. The difference of potential across the resistor Rs, as due to the current flowing from the emitter active region to the emitter contact C2, is measured between the ends of said metallizations 34 and 35. Thus, in prior integrated structures, the sensing resistor has been formed at the surface by having metallization or diffusion areas modified in or added to the structure of the power transistor. These techniques invariably result in an increase of the area occupied by the power transistor. A known vertical bipolar power transistor with buried base and a buried emitted with elongated portions or fingers is described in the EP application No. 0 632 505 in the name of Co.Ri.M.Me.. In particular, this application describes a vertical transistor which comprises a screening region which lies below an interconnection region and is couple to N+ contact regions by a metal strip thus creating a parasitic diode with the contact and screening regions behaving as an anode while the interconnection region operates as a cathode. The EP application No. 0 544 364 in the name of Co.Ri.M.Me. also describes a monolithic semiconductor device having a vertical structure and comprising a deep-base and finger-emitter power transistor. Also known from the US Patent No. 5,281,872 to Mori is a current detectable transistor having a sense resistor. The underlying technical problem of this invention is to provide a vertical structure, integrated bipolar transistor incorporating a current sensing resistor which involves no increase of the total area occupied by the transistor, or at least for an increase of trivial significance in occupied area. This technical problem is solved by a vertical structure, integrated bipolar transistor incorporating a current-sensing resistor, as indicated above and defined in the characterizing portions of Claims 1 to 7. The features of this invention can be better appreciated by having reference to the following detailed description of some embodiments thereof illustrated, by way of example and not of limitation, in the accompanying drawings. Brief Description of the Drawings Figure 1 is a plan view of a first power transistor incorporating a sensing resistor, according to the prior art. Figure 2 is a plan view of a second power transistor, also incorporating a sensing resistor and according to the prior art. Figure 3 is a plan view of a third power transistor incorporating a sensing resistor, according to the prior art. Figure 4 is a sectional view taken through the structure of a bipolar power transistor incorporating a sensing resistor, according to this invention. Figure 5 is a plan view of the power transistor shown in Figure 4 and embodying this invention. Detailed Description Figures 4 and 5 show a vertical structure, bipolar power transistor of the NPN type, Figure 4 being a sectional view and Figure 5 a plan view of the transistor structure. The structure shown in Figure 4 includes, from bottom to top, a substrate 1 of an N+ doped semiconductor material. The substrate is overlaid by an N- doped epitaxial layer 2, grown with epitaxial techniques known per se. The substrate 1 forms, jointly with the epitaxial layer 2, the collector of the transistor. A base region, with P conductivity, comprises a buried region 3 in the epitaxial layer 2 and is connected to a surface base contact (15) by vertical diffusion regions 4 having the same type of conductivity. Formed over the base region is an emitter region 5 with N+ conductivity, also buried in the epitaxial layer 2. A vertical diffusion region 6, of the N+ type, is then formed to contact the buried emitter 5 and bring it to the surface, where it is further contacted by a surface region 7 having the same type of conductivity. A contact 10, from which an emitter current is taken via a metallization line 12, is formed at the edge of the region 7. A region 8 of the N+ type brings to the surface the edge of the buried emitter region 5 and is then contacted by a contact 11 and a metallization 13. The transistor current will flow from the substrate 1, through the base 3, to the emitter 5. It is then forced to go through the region 6, representing a resistive path designated R1 in the figure, and on reaching the region 7 splits between two resistive paths R2 included between the region 6 and the emitter contacts 10. Thus, the resistance met by the emitter curent will be the combined resistance of the resistor R1 and the two resistors R2 in parallel, i.e.: Rs = R1 + R2/2. This resistance is put to use as a sense resistor for sensing the emitter current, by contacting it, at one end, through the contact 11 and vertical region 8, and at the other end, through the emitter contact 10 located at the edge of the region 7. The current flowed through the transistor will, in fact, be proportional to the voltage drop across the sensing resistor RS, and this difference of potential can be easily sensed on the metallization lines 12 and 13. Figure 5 is a plan view of the bipolar power transistor shown, in section, in Figure 4, which highlights the epitaxial layer 2 overlying the substrate 1, part of the buried regions, and some of the metallization lines. In particular, the buried emitter region 5 is noticeable, overlaid by the surface emitter region 7. The vertical region 8 connects, along three sides, the buried region 5 to the device surface, whereat this region is connected to the metallization line 13 by the contact 11. The contact 10 can be seen at the edge of the region 7 from which the emitter current is taken through the metallization line 12; another metallization line 14 used for sensing the drop of potential across the sensing resistor extends from line 12. Thus, the sensing resistor RS = R1 + R2/2 is contacted by the two metallization lines 13 and 14. Line 14 in this figure branches off the emitter metal 12 and is expediently utilized for sensing the voltage on the resistor RS. As can be appreciated from Figure 4, as well as from Figure 5, this invention provides for the formation of a sensing resistor which can be integrated to the structure of a bipolar power transistor without involving increased area occupation. In fact, whereas in prior devices, as shown in Figures 1, 2 and 3, the sensing resistor is formed at the surface, thus using up a significant area, in this invention it is formed part vertically (R1) and part horizontally (R2) over the emitter region 5.

Claims: A vertical structure, integrated bipolar transistor incorporating a resistor suitable for current sensing integrated on a substrate (1) with conductivity of a first type on which an epitaxial layer (2) with the same type of conductivity has been grown, comprising: a collector region (1) provided by the substrate (1); a base region (3) with conductivity of a second type, opposite to the first type, being buried in the epitaxial layer (2) and connected to a surface base contact (15) through at least a first vertical diffusion region (4); and an emitter region with conductivity of the first type, comprising a buried layer (5) in the epitaxial layer (2) over the base region (3), a surface region (7), and at least a second vertical diffusion region (6) connecting the buried layer (5) to the surface region (7); characterized in that at least a third vertical diffusion region (8) is provided to connect the buried emitter layer (5) to a first surface emitter contact (11), and that the surface emitter region (7) is contacted, along at least two peripheral sides thereof, by a second surface emitter contact (10), the first and second surface emitter contacts contacting only regions of the first conductivity type. A transistor according to Claim 1, characterized in that the surface emitter region (7) is contacted by the second surface emitter contact (10) along three peripheral sides thereof. A transistor according to Claim 1, characterized in that the resistor suitable for current sensing comprises regions contacted by said first (11) and second (10) surface contacts. A transistor according to Claim 3, characterized in that it further comprises a metallization (12) in electric contact with the second surface emitter contact (10) and suitable to take an emitter current. A transistor according to Claim 3, characterized in that the third vertical diffusion region (8) extends along at least two sides of the buried emitter layer (5).

Inventors: PALARA SERGIO, PALARA, SERGIO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1996
Main classification: H01L29
IPC codes: H01L29, H01L21