METHOD FOR MANUFACTURING A MICROWAVE VERTICAL BIPOLAR TRANSISTOR ON AN SOI WITH BURIED BASE METAL CONDUCTOR

Abstract: The present invention is directed to a method of manufacturing a microwave vertical bipolar transistor on an SOI device in which oxide spacers are used to make the structure without using multiple deposition layers. Buried oxide regions are used to form base regions and the emitters are formed on the base regions followed by provision of the oxide spacers about the emitters. The oxide spacers prevent electrical contact between the base contact regions and the emitter. Useful for manufacturing MMIC devices.

Description: Method for manufacturing a microwave vertical bipolar transistor on an SOI with buried base metal conductor. The present invention is directed to a method of making a microwave, vertical bipolar transistor on an SOI where there is a buried metal conductor. In particular, the method of the present invention uses oxide spacer widths and diffusion to provide critical dimension in the device without using lithography. Attention is directed to applicants' related application by the same inventor, Serial No. 08/579,703 (PHA 23,083) filed on the same day as this application. In communication systems operating at less than 10 Ghz, silicon bipolar transistors are used. The making of such devices for microwave applications has been expensive, such as in the making of bipolar MMIC devices using conventional bulk silicon technology. Problems occur in the prior art because of the process complexity associated with buried collectors and isolation of the parts. The making of such devices with SOI technology reduces the complexity of the process with the added advantage of low capacitances. But while a lateral bipolar transistor can be made for use at microwave frequencies, high power has not achieved in such devices. The present invention offers a method of making vertical bipolar transistors on an SOI in which critical dimensions in the device can be controlled by a different technique. Namely, the use of oxide spacers and controlled diffusion enables the formation of such devices without using lithographic techniques, such as used in applicant's corresponding application (see Serial No. 08/579,703), filed on the same date as this application. The device is made according to the present invention by the steps of forming an SOI wafer of n and n-l- layers of silicon on an insulating layer on a substrate, implanting an n-l- collector through the n layer of silicon into the n+ layer of silicon, forming a p type base within an active region at the surface of the n layer, forming an n + polysilicon emitter on the p type base within the active region, providing oxide spacers about the emitter for a distance, forming p+ base contacts and contact metalization to the base spaced from the emitter by the oxide spacers, depositing a planar dielectric layer over the formed structure, and providing conductive contacts to the collector and the emitter through the planar dielectric layer. In a particularly beneficial embodiment of the present invention, suicide contacts are formed over the emitter and the p+ base contacts before the contact metalization is made. This improves conductivity of the emitter and the base, and may be formed by any metal suicide. Such metal suicide may be formed by a metal film deposition followed by a subsequent sintering. Cobalt suicide is preferred since it has a high conductivity and a low probability of forming a bridge across the oxide spacer. Also in a preferred embodiment, the contact metalization is provided by using a double layer refractory metal. Such a double layer would preferably include a TiW layer with a stacked layer of Mo thereover. The TiW layer provides a good adhesion with the oxide spacers, and forms a good ohmic contact with the p+ base contact layer or the suicide. The high conductivity molybdenum provides a stable contact with the TiW layer at high temperatures. The features and technique of the present invention may be seen by way of example with respect to the drawing figures, in which distances and sizes have been changed in order to more clearly show the features of the present invention, and where: Figure 1 shows the vertical bipolar SOI device according to the present invention, and Figures 2, 3, 4, 5, 6, 7, 8, 9, 10, 11 and 12 show in sequence the process for making the device of Figure 1. The self-aligned vertical bipolar transistor on an SOI wafer, according to the present invention, is shown in Figure 1. The SOI wafer is formed by the substrate 1 on which an isolation or buried oxide 2 is disposed. Over this oxide 2 is a semiconductor layer, being in this case an n+ layer 3 provided on the oxide layer 2 and an n layer 4. The n+ layer 3 under the n layer 4 has a high conductivity so that it will provide a low loss collector. The substrate 1 may be a silicon layer and the layers 3 and 4 may also be silicon, while the oxide layer may be SiO 2 . On this SOI wafer, an n-l- collector region 6 is provided through the n layer 4 between oxide regions 5 which are buried into the n layer 4. Beside this collector region is provided a base region and emitter region between one of the buried oxide regions 5 and a further buried oxide region 5, according to the present invention. The base region includes a base 7, base contact regions 9 and base contact metalization 15 provided in contact with a silicide 10. The emitter region 8 is provided over the base region 8 with an n type emitter junction 12. A silicide layer 10 is also disposed on the emitter 8 which is surrounded by oxide spacers 11 which are given dimensions to control the distance between the emitter 8 and the base contact regions 9. Over this structure is provided a planar oxide layer 16 of a low temperature oxide (LTO) in which openings are provided to provide the emitter and collector metalizations 17. The contact metalization 15 to the base runs beneath the surface of the device to an edge of the device to make electrical connection. In the formation of this vertical bipolar device, the SOI wafer is formed, as shown in Figure 2, with the n+ layer 3 provided on the isolated oxide layer 2 on the substrate 1 of silicon, for example. The epitaxial layers 3 and 4 silicon films where the n-f- layer 3 has a high conductivity in order to be used as a low loss collector since it will be in contact with the collector 6. Next, as may be seen in Figure 3, before LOCOS oxidation is carried out, the silicon layer 4 is etched to eventually provide recessed oxide layers 5 which will define an active area 30, and a second area 31 in which a collector will be formed. In the LOCOS, an oxide pad of about 500A is first grown and then a nitride, such as silicon nitride, is deposited to about 1000A by a LPCVD technique. While the active area is covered with a photoresist, the nitride and oxide are etched away by a reactive ion etch (RIE). While normally the etch stops at the surface of the silicon layer 4, etching in this case is carried on to below the silicon surface by using a different RIE chemistry. The depth of the recessed etching is about half of the silicon thickness, which generates a smooth surface, as shown in Figure 3. Alternatively, an oxide planarization, instead of the recessed LOCOS could also produce a similar result. The n+ collector 6 is produced in Figure 4 by a selective implantation to drive dopant down to the n+ layer 3. As an example, phosphorus is used for a fast diffusion to save thermal effort. Some of the dopant laterally diffuses under the recessed LOCOS oxide 5. Then, as shown in Figure 5, p type dopant is selectively implanted into the active area 30 to form the p type base 7. This implantation is carried out with a doping concentration for the p type base that is higher than the doping for the n+ collector 6. But the doping concentration should be low enough for high injection efficiency. Alternatively, the p dopant can be diffused into or just activated to eliminate defects generated by implantation that would cause a subsequent abnormal diffusion during emitter formation from a n-f- type poly emitter layer. A heavily doped n-t- poly semiconductive layer is deposited and an emitter 8 is patterned, as seen in Figure 6, by a sequential process of poly deposition, photoresist patterning and plasma etching. Either arsenic or phosphorous may be used as the poly layer dopant, depending upon a desired depth of the emitter junction with the base 7. Oxide spacers 11 are formed at the steps of the emitter 8 from the base, as seen in Figure 7. This may be achieved by a deposition of LTO followed by an anisotropic RIE etching. The width of the spacers 1 1 are determined by the oxide thickness. Next, as seen in Figure 8, according to the present invention, a self- aligned implantation is carried out to form p+ type conductivity base contacts 9. The most critical dimension, which is the distance between the emitter 8 and the p+ base contacts 9, is not determined by a photolithographic technique, but by the width of the spacers 1 1. According to this process of the present invention, the recessed oxide layers 5, the poly emitter 8 and the spacers 1 1 form a mask for implanting ions into the p+ base contact areas, so that a photoresist mask is not needed according to the present invention. During diffusion into the p+ base contact areas, the n type dopant in the n-t- poly doped emitter 8 is also diffused into the p base 8 to form a buried emitter junction 12. A silicide 10 is formed over the p-f- base contact 9 and the n-f poly emitter 8, as seen in Figure 9, to improve the conductivity of the poly emitter and the base. Any metal silicide may be formed with a first metal film deposition and subsequent sintering. A metal silicide of cobalt is preferred because of its high conductivity and low probability for forming a bridge across the spacers 1 1. The formation of this metal silicide may be an option in the process of the present invention. Metalization to the base contacts 9 is preferably provided by a double layer refractory metal. A thin layer 13 of TiW is first deposited and a layer of molybdenum 14 is formed thereon, as may be seen in Figure 10. The layer 13 may be about lOOOA thick and have about 10 to 20 weight percent of Ti in tungsten. The molybdenum layer 14 may be about 2000A to 5000A in thickness. This metalization 13, 14 may be partially formed by lithographic and RIE etching processes over the exposed p+ base contacts 9 The TiW metalization not only provides a good adhesion to the buried oxide regions 5 but also forms a good ohmic contact with the p+ base contact 9 or silicide 10. The high conductivity refractory molybdenum region 14 and the TiW region 13 provides a stable contact at a high temperature without causing electric spiking in operation. A thick mterlevel dielectric layer 16 is deposited and pianaπzed, as seen in Figure 1 1 , to produce a smooth surface. A LTO may be used and planaπzed by using a photoresist of a low viscosity mateπal and/or reflowmg it over the surface. By selecting a RIE chemistry of an equal etch rate for both the resist and the LTO, the LTO hills may be leveled. Then, as seen in Figure 12, the emitter and collector contacts 17 are formed by opening areas 20 and 21, respectively, over the emitter 8 and collector 6. This may be done by conventional lithography. A disadvantage of the planaπzation step is a reduction of the LTO thickness on top of the emitter, leading to a variation in the contact depth. However, the planaπzed surface may be produced by a high resolution lithography so that it is possible to align the contact to the emitter which acts as an etch stop. In the fmal structure produced by the present invention, as seen in Figure 1 , the metalization areas 17 may be formed by aluminum and alloyed to form ohmic contacts to the emitter and collector. The base contact metalization 15 may be extended to the edge or end of the device where a highly conductive metal contact may be provided. Such device isolation is not shown but may be easily formed by a trench etching through the thin SOI film.

Claims: Claims: 1. A method of manufacturing vertical bipolar transistors on an SOI device comprising the steps of (a) forming an SOI wafer of n and n+ layers of silicon on an insulating layer on a substrate, (b) implanting an n-l- collector through the n layer of silicon into the n+ layer of silicon, (c) forming a p type base within an active region at the surface of the n layer, (d) forming an n+ polysilicon emitter on the p type base within the active region, (e) providing oxide spacers about the emitter for a distance, (f) forming p+ base contacts and contact metalization to the base spaced from the emitter by the oxide spacers, (g) depositing a planar dielectric layer over the formed structure, and (h) providing conductive contacts to the collector and the emitter through the planar dielectric layer. 2. A method according to Claim 1 , wherein silicide contacts are formed over said emitter and said p+ base contacts before forming said metalization. 3. A method according to Claim 2, wherein said silicide contacts are metallic and formed by depositing metal followed by sintering. 4. A method according to Claim 1 , wherein said contact metalization is formed by forming a first layer of TiW partially over said p+ base contact and then forming a second layer of Molybdenum over said first layer.

Inventors: KIM MANJIN J, KIM, MANJIN, J.
Applicants: PHILIPS ELECTRONICS NV, PHILIPS NORDEN AB, PHILIPS ELECTRONICS N.V.
Application year: 1996
Main classification: H01L21
IPC codes: H01L21, H01L29