Wiring board for electronic devices with high-density terminals and method for producing same

Abstract: A lattice of a wiring or terminal pattern is varied at areas on a wiring board. The spacing of the wiring lattice is reduced only in a predetermined area for a device having many terminals. An alignment pattern is provided in the predetermined area. The spacing of the wiring lattice in the central portion of the wiring board may be the finest and may get gradually coarser toward the peripheral portion of the wiring lattice.

Description: The present invention relates to a wiring board used in electronic equipment and a method of producing the wiring board, and more particularly to a wiring board for mounting electronic devices with high-density terminals and a method of production thereof. In a conventional thick-film wiring board fabrication method, inter-layer insulation materials and wiring materials are alternately stacked, and are baked at the same time. For example, a green sheet is used as the inter-layer insulation material and a conductive paste is used as the wiring material. In a conventional thick-film wiring board, wiring patterns and electrodes cover the entire area of the wiring board according to the same basic wiring lattices. In the conventional thick-film wiring board, the inter-layer insulation material contracts during baking. With such contraction, the wiring material also contracts. Under the current technology, controlling this contraction during fabrication is limited (e.g., to an error of approximately 0.2% of the target size). Because of this error during fabrication, the terminal density of devices to be mounted on the wiring board or the terminal density for connection between the wiring board and an external circuit (i.e., a reduction in the terminal pattern size) is limited. For example, in a square-shaped thick-film wiring board having a side length of 100 mm, if it is assumed that the wiring pattern contains a fabrication error of 0.2% with respect to an expected size, the spacing between a pad provided on one end of the board and a pad provided on a second end will be dislocated (i.e., deviated) from a designed value by up to 0.2 mm. Therefore, when pads for external circuits are arranged on outer regions of a wiring board, the spacing between the pads must be great enough to absorb the fabrication error (e.g., on the order of approximately 0.4 mm for a fabrication error of 0.2 mm). Similarly, when pads for a square device having a side length of 10 mm are arranged on the wiring board, the terminal spacing likewise contains a fabrication error of up to 0.02 mm and therefore the terminal spacing must be designed to absorb the fabrication error. As described above, because of the fabrication error caused by contraction during baking, in a large-size board (e.g., a board having a length of 100 mm), the board wiring lattice must be large (e.g., approximately a 0.4 mm pitch), although the basic wiring lattice is small (e.g., approximately a 0.1 mm pitch). Consequently, in the conventional wiring board, high density wiring patterns (e.g., less than about 0.4 mm) or pads (e.g., more than 200) cannot be obtained. Some conventional wiring boards are referred to in United States patent no. 5,034,802 and European patent no. 0 602 257. US 5,034,802 discloses a method and structure for aligning SMDs to a substrate. EP 0 602 257 describes a manufacturing method and wiring board designed for high-density wiring. In view of the foregoing problem of the conventional wiring board, an object of the present invention is to provide a wiring board and method for forming high-density pads and wiring patterns taking into consideration the dispersion in the baking-time contraction coefficient of the fabrication process of a multi-layer wiring board. Another object of the present invention is to provide a wiring board for mounting high-density and multi-terminal devices and a method for producing the wiring board. The aforementioned objects are realized by the wiring board and the method of fabricating a wiring board as disclosed in the claims. In a wiring board according to an aspect of the present invention, a first area mounts a first device which has an alignment pattern in the center of the first area. A second area, devoid of the alignment pattern, mounts a second device. With the unique and unobvious structure of the present invention, high-density pads are formed and the wiring board reliably mounts high-density and multi-terminal devices. The above-mentioned and other objects, features and advantages of this invention will become more apparent by reference to the following detailed description of the invention taken in conjunction with the accompanying drawings in which: FIG. 1 is a sectional view of a wiring board according to a first comparative example; FIG. 2 is a plan view of the wiring board according to the first comparative example; FIG. 3 is a side view of the wiring board according to the first comparative example; FIG. 4 is a sectional view of the wiring board according to a variation of the first comparative example; FIG. 5 is a side view of the wiring board according to the variation of the first comparative example; FIG. 6 is a plan view of the wiring board according to the variation of the first comparative example; FIG. 7 is a plan view of a wiring board according to a second comparative example; and FIG. 8 is a plan view of a wiring board according to an embodiment of the present invention. A wiring board in accordance with a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. Referring to FIG. 1, a wiring board has an inter-insulation layer 11 having a device mounting surface, an inter-insulation layer 21 having a wiring area and forming signal wiring, an inter-insulation layer 31 having a wiring area and forming signal wiring, and an inter-insulation layer 41 having a wiring area and forming ground wiring. Wiring patterns 13, 23, 33, and 43 are formed on the inter-insulation layers 11, 21, 31, and 41, respectively. The inter-insulation layers 11, 21, 31, and 41 and the wiring patterns 13, 23, 33, and 43 are alternately stacked, and are baked at the same time. For example, a green sheet is used as the inter-layer insulation material and a conductive paste (e.g., a silver paste) is used as the wiring material. In this comparative example, it is assumed that the contraction of the wiring board is about 17% after baking with respect to the size before baking (e.g., the size of the wiring area, which was approximately 120 mm before baking, is reduced to approximately 100 mm). Similarly, wiring patterns 13, 23, 33, and 43 are also reduced by about 17%. Via-holes 12, 22, 32, and 42 are provided for connecting the wiring layers formed on the different inter-insulation layers. The spacing between these via-holes is also reduced by about 17% after baking compared with the spacing therebetween before baking. Pads 14 are provided for mounting devices on the inter-insulation layer 11. In this comparative example, the contraction coefficient after baking is about 17% as described above. However, the contraction of ceramic material after baking is generally difficult to strictly control. In general, a dispersion (i.e., difference) in contraction between two arbitrary points of a wiring board depends on the manufacturing lots (e.g., generally having an error rate of between 0.2% and 0.5%). Therefore, even if the contraction coefficient is carefully controlled, a difference usually occurs with respect to the expected sizes. Referring to FIG. 2, the thick-film board 10 has an area-A and an area-B. Each of the area-A and area-B comprises a square (e.g., each side having about a 24 mm length before baking, and about a 20 mm length after baking), and has printed patterns (e.g., a 96 µm width at positions according to a basic wiring lattice having a spacing of 240 µm before baking). In an area 60 outside the area-A and area-B, printed patterns are coarser (i.e., have a wider spacing) than those of area-A and the area-B. For example, the printed patterns have about a 96 µm width at points according to a basic wiring lattice having a spacing of 480 µm before baking. The via-holes are formed at lattice points according to the basic wiring lattice. Each via-hole is filled with a conductive paste (e.g., a silver paste). Substantially in the center of the area-A and area-B, alignment patterns 15 are formed for aligning the device during mounting. The pads 14 are arranged at a predetermined interval and width. In the area-A and area-B, the interval of the pads is assumed to be about 240 µm before baking and about 200 µm after baking, and the width is assumed to be about 120 µm before baking and about 100 µm after baking. On the other hand, in the other area outside of the area-A and area-B, the interval of the pads is assumed to be about 480 µm before baking and about 400 µm after baking, and the width is assumed to be about 240 µm before baking and about 200 µm after baking. Devices 50 and 51 mounted on the areas A and B have a large number of terminals (e.g., at least 240 terminals). The terminals of the devices are aligned with the pads 14 by the alignment pattern 15 and then the terminals are soldered. In this example, assuming a length of 20 mm, since the alignment pattern 15 is substantially in the center of the area-A and area-B, the maximum distance between each terminal and the alignment pattern 15 will be: 10.0 mm × 2 ½ = 14.1 mm. Assuming the deflection (i.e., deviation) of the contraction coefficient to be about 0.2%, the maximum distance error will be: 14.1 mm × 0.2% = 28.2 µm. Therefore, since the error is sufficiently small as compared with the interval of the pads (e.g., about 200 µm), a mounting operation can be reliably performed. Next, referring to FIG. 3, contraction of a ceramic thick-film layer-in a fabrication process is described. Referring to FIG. 3, the device 50 is mounted on the area-A. A pitch 57 of the terminals is assumed to be about 200 µm, and a number of terminals is assumed to be about 60 on one side, although some of the terminals are omitted in FIG. 3. The device 50 maintains its size during the fabrication process. On the other hand, the size 56 and position of the pads on the ceramic multi-layer wiring board changes according to the contraction of the ceramic thick-film layer during the fabrication process. The device 50 has an alignment mark 55. During a mounting operation of the device 50, the alignment mark 55 is aligned with the alignment pattern 15 on the wiring board 10. In the alignment operation described above, assuming the number of terminals to be 60, the pitch 57 of the terminals to be about 200 µm, and the deflection of the contraction coefficient to be about 0.2%, the maximum positional dislocation between the terminals of the device and the pad on the wiring board will be: (60 - 1) / 2 × 200 µm × 2 ½ × 0.2% = 16.6 µm. Next, a variation of the first comparative example will be described in detail with reference to FIG. 4. Referring to FIG. 4, a variation of the first comparative example includes polyimide wiring layers 18 each having thin-film patterns 16 and pads 17 being added to the area-A and area-B of the first comparative example shown in FIG. 2. Each of the pads 14 in the first comparative example forms a connection terminal that is connected to the lowermost layer of the polyimide thin-film wiring layer. The wiring of the ceramic multi-layer wiring board and the wiring of the thin-film wiring layer are connected by the connection between the connection terminal 14 of the ceramic multi-layer wiring board and the pad 17 of the thin-film wiring layer. The area shown as area-Z in FIG. 4 represents a portion other than the area-A and area-B. Next, an exposure method, which is used when forming the thin-film wiring layer of the variation of the first comparative example shown in FIG. 4, will be described with reference to FIG. 5. Referring to FIG. 5, the area-A and area-B are exposed using the alignment patterns 74 and 78 located in the centers of the area-A and area-B. An exposure mask 72 for the area-A and an exposure mask 76 for the area-B have alignment marks 73 and 77, respectively. Therefore, even if a position of the pad on the ceramic multi-layer wiring board is dislocated due to contraction deflection by baking, dislocation between the connection terminal 14 on the ceramic multi-layer wiring board and the pad on the thin-film wiring layer is decreased. An exposure mask for the area-Z covers substantially the entire area of the wiring board 10, and alignment with the ceramic multi-layer wiring board is performed at one location. Thus, in the area-Z, the dislocation between the connection terminal 14 on the ceramic multi-layer wiring board and the pad 17 on the thin-film wiring layer is larger than that of the area-A and area-B. In the first comparative example and the variation of the first comparative example, the devices 50 and 51 with a large number of terminals have been disposed in the area-A and area-B. When a large number (e.g., 9) of such devices with a large number of terminals are arrayed, the devices are arrayed in a lattice and, at the same time, the areas where the basic wiring lattice is fine (e.g., an approximately 0.1 mm spacing) are arranged in correspondence with the devices arrayed in the lattice, as shown in FIG. 6. Next, a second comparative example will be described in detail with reference to FIG. 7. Referring to FIG. 7, a feature of the second comparative example includes portions requiring relatively fine wiring being positioned at a single place (e.g., "area-C") substantially in the vicinity of the center of the wiring board. In this example, an alignment pattern is disposed at the center of the limited area-C and alignment is performed thereat. By such positioning of the devices requiring fine wiring, a fine wiring connection, which is not affected easily by the contraction deviation, becomes possible substantially in the vicinity of the center of the area-C. The sectional structure of the thick-film wiring board in this second comparative example is identical to that of the variation of the first comparative example shown in FIG. 4. In addition, as with the first comparative example, the contraction coefficient is not strictly controllable. In this thick-film board, the area-C comprises a square (e.g., having a substantially 60 mm length side before baking, and about a 50 mm length side after baking), and has printed patterns (e.g., a substantially 96 µm width at positions according to a basic wiring lattice having a spacing of about 360 µm before baking). In an area outside the area-C, printed patterns are coarser than in the area-C (e.g., a 96 µm width at points according to a basic wiring lattice having a spacing of 480 µm before baking). In the second comparative example, a thin-film wiring layer (unreferenced in FIG. 7) is formed on the upper layer of the thick-film wiring board 10. In the thin-film wiring layer, printed patterns are defined according to a basic wiring lattice (e.g., a substantially 40 µm width, and about a 100 µm pitch, while the pitch of the connection terminals to the thick-film wiring board 10 is about 300 µm in the area-C and about 400 µm in areas other than the area-C). Assuming the length of one side of the area-C to be 60 mm and the deviation of the contraction coefficient to be 0.2%, the maximum dislocation of the distance from the center of the board in the area-C will be about: 30 mm × 2 ½ × 0.2% = 84.8 µm. On the other hand, in the thin-film wiring layer 18, a wiring pattern 16 is formed as designed, because the deviation of the contraction coefficient does not occur. Therefore, in the area-C the maximum dislocation (e.g., about 84.8 µm) occurs between pads 14 on the thick-film wiring board and pads 17 on the thin-film wiring layer, but the positional dislocation is small compared to the pitch of the connection terminals (i.e., about 300 µm). If the connection terminal is formed into a circular cone having a diameter of about 150 µm, for example, the positional dislocation can be absorbed. Assuming the length of one side of the wiring board to be about 120 mm, in the outside of the area-C, a distance from the center of the board has a maximum dislocation of: 60 mm × 2 ½ × 0.2% = 169.7 µm. This dislocation can be absorbed, for example, by setting the pitch of the connection terminals to about 400 µm and forming the connection terminal to have a circular diameter of 250 µm. In the formation of the wiring board of the second comparative example, an exposure mask is sized so that it can cover substantially the entire board, patterns of not only the area-C but also the area outside the area-C are drawn on the exposure mask, and substantially the entire area is exposed by using the alignment pattern located in the central portion of the area-C. With this method, the patterns of the entire area can be formed with a single exposure process simultaneously with the area-C. In this case, the alignment accuracy between the connection terminal of the ceramic multi-layer wiring board and the via-hole of the thin-film wiring layer decreases in the area outside the area-C than in the area-C. Next, a preferred embodiment of the present invention will be described in detail in reference to FIG. 8. A feature of the preferred embodiment of the present invention is that the spacing of the wiring lattice in the central portion of the wiring board is narrowest and is gradually widened toward the peripheral portion. Referring to FIG. 8, the thick-film wiring board 10 has an area-D, an area-E, and an area-F. Each of the areas comprises a square (e.g., having a substantially 60 mm length side for the area-D, a 120 mm length side for the area-E, and a 180 mm length side for the area-F, before baking). The area-E is disposed outside the area-D, and the area-F is disposed outside the area-E. The area-D has printed patterns according to a basic wiring lattice having a predetermined spacing (e.g., about 360 µm before baking, and about 300 µm after baking). The area-E has printed patterns according to a basic wiring lattice having a predetermined spacing (e.g., about 480 µm before baking, and about 400 µm after baking). The area-F has printed patterns according to a basic wiring lattice having a predetermined spacing (e.g., about 600 µm before baking, and about 500 µm after baking). Thus, the spacing of the wiring lattice in the central portion (i.e., area-D) of the wiring board is narrowest and gradually increases outwardly toward the periphery (i.e., to area-E and area-F). The advantage of such a structure is that devices having highest-density pads are mounted in the central portion and other devices are mounted toward periphery depending on the density of the pads. As is apparent from the above description, according to the present invention, since the wiring board has the alignment pattern, pads can be formed with high density, and the wiring board can mount high-density and multi-terminal devices, while considering the contraction dispersion of a ceramic multi-layer wiring board. If the thick-film wiring board of the present invention is used as a base board for a thin-film wiring, a thick-film and thin-film mixed wiring board can be obtained with density higher than that of a conventional mixed wiring board. In addition, the thick-film wiring board of the present invention can mount a multi-terminal device having higher density than a conventional device. While the invention has been described in terms of a preferred embodiment, those skilled in the art will recognize that the invention can be practiced with modification within the scope of the appended claims.

Claims: A wiring board (10), comprising: a first area (D) for mounting a first device, said first area (D) having an alignment pattern substantially in the center of said first area (D) for aligning said first device, said first area (D) having a first wiring lattice having a first pattern spacing for mounting said first device; and a second area (E), co-planar with and substantially concentric with said first area (D), having a second wiring lattice having a second pattern spacing for mounting a second device, said second pattern spacing being greater than said first pattern spacing and getting greater with the increase of the distance from said alignment pattern, wherein said first area (D) comprises an area substantially in the center of the wiring board. A wiring board according to claim 1, comprising: at least one inter-insulation layer; a wiring pattern on said at least one inter-insulation layer; and a pad connected to said wiring pattern on an uppermost layer of said at least one inter-insulation layer. The wiring board (10) according to claim 2, further comprising: a via-hole for connecting adjacent layers of said at least one inter-insulation layer. The wiring board (10) according to claim 2 or 3, wherein said at least one inter-insulation layer comprises a ceramic sheet. The wiring board (10) according to claim 2, 3 or 4, wherein said wiring pattern comprises a conductive paste. The wiring board(10) according to any of claims 2 to 5, further comprising: a thin-film wiring layer on an uppermost layer of said at least one inter-insulation layer. The wiring board (10) according to claim 6, wherein said thin-film wiring layer comprises a polyimide sheet. The wiring board (10) according to any of claims 2 to 7, further comprising, a third area (F), co-planar with and substantially concentric with said second area (E), having a third wiring lattice having a third pattern spacing for mounting a third device, said third pattern spacing being greater than said second pattern spacing and getting greater with the increase of the distance from said alignment pattern. A method of fabricating a wiring board (10), comprising: preparing an inter-insulation layer; stacking a wiring pattern on said inter-insulation layer; forming an alignment pattern substantially in the center of a first area (D) on said inter-insulation layer; and baking said inter-insulation layer, said first area (D) including a first wiring lattice having a first pattern spacing for mounting a first device, said alignment pattern for aligning said first device, said wiring board further including a second area (E), co-planar with and substantially concentric with said first area (D), having a second wiring lattice having a second pattern spacing for mounting a second device, said second pattern spacing being greater than said first pattern spacing and getting greater with an increase of distance from said alignment pattern; wherein said first area (D) comprises an area substantially in the center of the wiring board.

Inventors: INOUE TATSUO, INOUE, TATSUO, Inoue, Tatsuo, c/o NEC Corp.
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1996
Main classification: H01L23
IPC codes: H01L23, H05K1, H05K3