METHOD AND APPARATUS FOR DETERMINING BURST ERRORS IN AN ERROR PATTERN

Abstract: A burst error counting system determines, for each sector long error pattern, a minimum number of burst errors by: specifying, based on the statistical operation of the system a maximum burst length, L; determining the location in the error pattern of a first erroneous bit b(first) (104); associating the the next L-1 bits with b(first) (106); incrementing a burst counter; searching for a next b(first) and repeating the steps (116). The system also stores the position (bit count) of all b(first) occurrences. By associating with each b(first) the next L-1 bits, each burst error can be associated with a number of non-erroneous bits that follow. The count of the burst errors in the error pattern is not altered. The burst error count is compared to a burst error threshold which is equal to or less than the maximum number of errors expected in a sector.

Description: METHOD AND APPARATUS FOR DETERMINING BURST ERRORS IN AN ERROR PATTERN FIELD OF THE INVENTION This invention relates generally to error correction systems that correct errors in data encoded using an error correction code and, more particularly, to a system for counting burst errors in the decoded data. BACKGROUND OF THE INVENTION Data to be stored for later retrieval are typically stored in encoded form. Prior to their storage, the data symbols are encoded using an error correction code (ECC). Encoding the data avoids the loss of information through misinterpretation of the retrieved data, should one or more of the data symbols become corrupted due, for example, to a defect in the recording medium, such as a disk, or to noise signals in associated read or write channels. The result of rnisinterpreting the retrieved data symbols is erroneous data, and the error correction code is employed to, as the name implies, correct the erroneous data. Specifically, before a string of data symbols is recorded, it is mathematically encoded to form ECC symbols. The ECC symbols are then appended to the data string to form data code words - data symbols plus ECC symbols - and the data code words are written to, or stored on, the disk after appropriate encoding with a modulation code. As recording densities increase, "N" code words are typically interleaved before they are recorded in a sector. When data are read from the disk, the interleaved code words are retrieved and mathematically decoded. During decoding, errors in the data are detected and, if possible, corrected through manipulation of the associated ECC symbols [For a detailed description of decoding see Peterson and Weldon, Error Correction Codes. 2d Edition, MIT Press, 1972]. When the data recorded in a sector are retrieved from storage, they are manipulated in a conventional manner to de-interleave the N code words and determine the locations of errors and the associated error values. The system then corrects the errors by combining the error values with the associated erroneous bits or symbols. There are essentially two ways to classify errors - as random errors or as burst errors. A random error is an independent error that occurs in a code word symbol. A burst error is a sequence of contiguous bits or symbols in which at least the first bit or symbol and the last bit or symbol are erroneous, and the bits or symbols between the first and last may but need not be erroneous. Burst errors result from, for example, a storage medium defect that adversely affects a portion of a sector, and thus, affects a number of the interleaved code words. As data are stored more densely, defects in the storage medium tend to involve more and more bits, and thus, produce more and more burst errors. Systems are more often using maximum likelihood demodulators to demodulate the retrieved data. These demodulators tend to correct random errors in the retrieved data by selecting "legitimate" sequences of bits, based on a sequence of retrieved bits that may contain one or more erroneous bits. The demodulator uses information about the modulation code to select, as the most likely recorded bits, a sequence of bits that is closest to the retrieved bits and meets the constraints of the modulation code. The maximum likelihood demodulators may actually introduce bursty errors into the demodulation, by selecting as most likely the wrong sequence of bits. The demodulator is more apt to make such a selection if the retrieved data are corrupted. The sequences selected by the maximum likelihood demodulator are legitimate sequences of bits, even if they are the wrong sequences, that is, even if they are not the sequences that were recorded. These sequences are then de-interleaved and decoded to reproduce the N code words. If the retrieved data contains too many errors the data may be mistakenly demodulated, and then interpreted as different (but legitimate) code words. This is the worst type of decoding mistake, since the system "corrects" these code words, as necessary, using the ECC, and then treats the data symbols as error-free. Accordingly, as recording density increases, it is becoming more and more important to count the number of burst errors in the N retrieved code words, so that this decoding problem can be avoided by limiting error correction to those sectors that contain a relatively small number of burst errors. A burst error occurs as a number of bits or symbols. Since all the bits or symbols in a burst need not be erroneous, there is an ambiguity in determining the start and length of each burst. There is thus a problem in determining if a retrieved sector of data contains a number of burst errors that exceeds the predetermined error correcting limit. To count the number of burst errors in the retrieved data, the system examines the error pattern for the entire sector of data. The error pattern is determined from the error locations and the error values for the N code words. These are provided by the ECC during decoding. A zero in the pattem represents a correct bit and a one in the pattem represents an erroneous bit. The pattern includes the same number of bits as those recorded the sector. Consider an error pattem: 0010001100000000001010000000000001 1100000... The number of burst errors in this segment of the pattem can be counted as: eight 1 -bit bursts; three 1-bit bursts, one 2-bit burst and one 3-bit burst; one 1-bit burst, one 2-bit burst and two 3-bit bursts; one 6-bit burst, and two 3-bit bursts; and so forth. There is thus a need for a system to determine, for an error pattem, a unique number of burst errors. Once the number of error bursts is known, such a system can restrict, or limit, its error correcting to sectors that contain up to or less than the number of burst errors that are encountered during normal operations of the system. SUMMARY OF THE INVENTION The invention is a burst error counting system that determines for each error pattem a unique, minimum number of burst errors by (i) specifying, based on the statistical operation of the system, a maximum burst length, L, which, as discussed below, is the longest burst that the system "generates;" (ii) determining the location in the error pattem of a first erroneous bit; (iii) associating the next L-1 bits with the erroneous bit; (iv) incrementing a burst counter; (v) searching for the first bit of a next burst error in the remaining bits of the error pattem; and (vi) repeating iii-v. The system may also store the positions of these first erroneous bits for later use. More specifically, the system associates with each burst error at least the bits included in that burst and may associate with it a number of non-erroneous bits that follow the burst. Assume, for example, that the maximum burst length is 6, i.e., L= 6, and the first erroneous bit of a burst error, bpr o c T , and the succeeding L-1, or 5, bits are 110100. The system associates with bpmς T both the sequence of bits included in the actual burst error (i.e., 1101) and the two non-erroneous bits that follow the burst. If, for example, the last bit were instead erroneous, both of the bits would be included in the actual burst error. However, since they are non-erroneous and any succeeding erroneous bit is beyond the maximum length, they are not part of this actual burst error or a next actual burst error. Accordingly, associating them with this burst error does not alter the count of the burst errors in the code word error pattem. Each time the burst error count is incremented, the system compares the count to a predetermined burst error threshold, which is less than or equal to the number of burst errors that the system can expect in a sector of data. If the number of burst errors exceeds the threshold, the system may characterize the code words as uncorrectable. As discussed in more detail below, the threshold is based on the performance statistics of the system. In an alternative embodiment, the system counts the burst errors simultaneously from both ends of the error pattem. It thus determines the positions in the pattem of a first erroneous bit, bpmr r and a last erroneous bit, b^ AST . Next, it associates with these bits the succeeding or proceeding L-1 bits, as appropriate. If the bit position of the L- 1 st bit associated with the first burst error is the same as or beyond the position of bγ . < ,-, the system determines that the two erroneous bits bprnc- j - and br * ~ are within the same burst error, and thus, that the error pattem contains a single burst error. Otherwise, the system determines that there are at least two burst errors. It then increments its burst count by two and continues searching through the remaining error pattem for additional burst errors. If additional erroneous bits bp j nc j and . * Q J. are found in the error pattem, the system associates with them the appropriate succeeding and preceding L-1 bits and again checks if they should be treated as a single burst error. If so, the system has found all of the burst errors. Accordingly, it increments its burst count by one and stops its burst counting operations. Otherwise, the system increments the burst count by two and continues searching for additional burst errors, as long as the burst count is below the burst error threshold. If the burst error threshold is two, the system locates bp rDSτ . and by A <- τ and sets to all zeros bpyogy. and the succeeding L-1 bits and b j » C T nd preceding L-1 bits. It can then readily determine from the altered error pattem whether or not there are additional burst errors, by searching for any l's in the pattem. The system may reduce the length of the error pattem, and free buffer space, by limiting to L-1 the number of zeros between consecutive l's. The system then counts the burst errors by searching through the reduced number of bits. The system in all of its embodiments determines for an error pattem a unique, minimum count of the burst errors. The particular burst error patterns and locations may differ, depending on whether the system searches the error pattem from one end or both ends. However, the count of the burst errors remains the same. BRIEF DESCRIPTION OF THE DRAWINGS The above and further advantages of the invention may be better understood by referring to the following description in conjunction with the accompanying drawings, in which: Fig. 1 is a functional block diagram of a system constructed in accordance with the invention; Fig. 2 is a flow chart of the operations of a decoder that is included in the system of Fig. 1; Fig. 3 depicts the decoder of Fig. 2 with increased storage capabilities; Fig. 4 depicts an alternative decoder; and Fig. 5 is a flow chart of the operations of the decoder of Fig. 4. DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS Fig. 1 depicts a system 10 in which an encoder 12 encodes data symbols in a conventional manner to produce error correction code (ECC) symbols. The encoder 12 concatenates the ECC symbols to the data symbols to form a code word. It then interleaves N code words and sends them to a storage device 14 for storage in a sector on a recording medium, such as a magnetic disk (not shown). Referring also to Fig. 2, when the sector of data is retrieved from storage, the decoder 16 demodulates, de-interleaves and decodes the data in a conventional manner in processor 17. The decoding produces a sector-long error pattem that consists of a sequence of zeros and ones, with ones representing erroneous bits and zeros representing non-erroneous bits. It then stores the error pattem in a buffer 18 (step 100). As an example assume the error pattem is: 00100001011100010000000000000000000010100000000111110000000000... The decoder 16 sets its burst counter 20 to c=0 and a "1" detector 22 searches the contents of the error pattem buffer 18 for a first one bit, b ττ, Qj (steps 102-104). The position of this bit in the error pattem is the start of a first burst error. In the example, the detector 22 stops its search at the third bit. The decoder 16 then determines a first potential burst error, e . , by associating with bit bpm„ τ the next L-1 bits, where L is the maximum burst length associated with the system (step 106). The maximum burst length, L, is an error statistic that is specific to the system. It is based, for example, on the type of system, i.e., optical, tape, magnetic disk; the density of recording; and so forth, and is determined experimentally. In the example, L=6 and the system associates with bit bppn ς the next 5 bits. Accordingly, the first potential burst error, e , , is thus 100001. If the system is only counting the burst errors and does not at this time require that the starting location of the errors or the actual burst error patterns be saved, the system increments the burst error counter 20 to c=l and sets the corresponding L bits in the code word error pattem to all zeros (steps 108-110). The code word error pattem is now: 0000000001110()010(X)0000000000000000010100000000111110000000000... The decoder also compares its burst count to a predetermined burst error threshold, which is equal to or less than the maximum number of burst errors that the system "expects" in an error pattem that corresponds to a sector of data that is not so corrupted that the ECC may inaccurately "correct" the data (step 112). This burst error threshold is also determined experimentally for a particular system. For example, the system may occasionally encounter error patterns with at most two burst errors and encounter significantly more burst errors only when a sector is corrupted beyond the point at which the error correction system always correctly reproduces the recorded data. Such a system would have its threshold set to two or perhaps three, to avoid labeling good sectors as uncorrectable. If the burst count is greater than the burst error threshold, the system stops its burst counting operation (steps 112-113). Otherwise, the system searches for the next 1 in the remaining bits in the error pattem (steps 114- 116) . Assuming the threshold has not been reached, the decoder 16 again begins its searches for a first 1 bit in the pattem and ends this search at the ninth bit, which becomes the next bp jj -.ςr . The decoder next associates the succeeding L-1, or 5, bits with bp ,ς T , to produce the second potential burst error, e « > of 111000. The decoder increments its burst count to c=2 and sets these L bits to all zeros. It then compares the burst count to the burst error threshold and determines if the count exceeds the threshold. If so, the system ends its burst error counting operation. Otherwise, it repeats its burst counting operations until either the burst error threshold is exceeded or it reaches the last bit in the error pattem. To save the information relating to the burst error locations, the detector 22 enables an address memory 24. This memory stores, in a memory location addressed by the count of burst counter 20, a bit count from an address counter 26, which counts the bits in the error pattem as these bits are searched. The detector 22 operates in a conventional manner to detect l's in the error pattem. In an exemplary system, the detector 22 retrieves the error pattem from the error pattem buffer 18 (Fig. 1) as a serial stream of bits, and "tests" each bit to find the first 1 bit. The address counter 26 thus counts the bits as they are applied to the detector. As is well known to those skilled in the art, the detector 22 could instead retrieve the error pattem in parallel from the buffer 18, and use a combinational search and counting mechanism to determine the position of a first 1 in the pattem. When the detector 22 detects the first 1 in the error pattem, it asserts a signal on line 23. The asserted signal increments the count of the burst counter 20 and enables a burst error address memory 24. The memory 24 stores the count of the address counter 26 in the memory location addressed by the burst count, to indicate the first bit position of the first burst error. The detector then leaves asserted the signal on line 25 for the next L-1 bits. Thereafter, the detector de-asserts the signal on line 25 until a next 1 is detected in the code word error pattem. Each time the burst counter 20 is incremented, its count is compared to a predetermined error threshold by comparator 28. The burst error threshold is equal to or less than the maximum number of burst errors that are expected in a sector that is not corrupted to the point that the error correction performed by the system is questionable. If the sector includes too many burst errors, it is at least somewhat likely that the corrected data are not the data that were recorded on the disk, but instead other data that were produced through a combination of inaccurate demodulation and error correction of the resulting data. If the burst count exceeds the burst error threshold, the comparator asserts a signal on line 29 and the system 10 (Fig. 1) responds appropriately by. for example, labeling the code word as uncorrectable. It thus rejects the corrected data as inaccurate. In an alternative embodiment, the decoder 16 counts burst errors simultaneously from both ends of the error pattem. The decoder 16 thus includes two detectors 22-1 and 22-2 and two address counters 26-1 and 26-2, as depicted in Fig. 3. Referring also to Fig. 4, the detector 22-1 determines the first position of a 1 in the error pattem by examining succeeding bits of the error pattem, starting from the end of the pattem that corresponds to the start of the error pattem (step 202). The associated address counter 26-1, which is initially set to zero, increments its count for each bit examined by the detector 22-1 (steps 200, 204). At the same time, the detector 22-2 starts searching for 1 's from the end of the pattem that corresponds to the end of the date (step 302). The associated address counter 26-2 starts its count at the total bit count of the error pattem, and decrements its count for each bit examined by the detector 22- 2 (steps 300, 304). Once the detectors 22-1 and 22-2 each detect a 1, respectively, bpyy-. ^ — and b A ς T , the decoder 16 determines if the two l's should be included in the same or different burst errors. The decoder 16 first stores the address count of bpy j ^c in the address memory, since it is the first bit of at least the first burst error in the pattem. (step 206). The decoder next associates L-1 bits with bpyy^ T and determines from the count of address counter 26-1 the position of the L-1 st bit (step 208). If this bit position is beyond the position of by . sτ , that is, if processor 27 determines that the count of address counter 26-1 is greater than the count of address counter 26-2, the system includes bpyy, ^ T and by . ςy in the same burst error. The burst counter is then incremented by one and the decoder stops its burst counting operations (steps 210, 212). If the position of the last of the L-1 bits is not beyond by * c the system increments the burst counter 20 by two, associates the preceding L-1 bits with by . „-, and stores the count of the address counter 26-2 in the burst error address memory 24 as the location of a second burst error (steps 211, 214, 215). The decoder next sets to all zeros y ^ and the associated succeeding L-1 bits, and by A r T and the associated preceding L- 1 bits. If the burst count does not exceed the burst error threshold, the system searches the remaining bits of the code word error pattem from both ends and determines the positions of any additional burst errors (steps 216-218). If the burst error threshold is two, the system may use a simplified operation to determine if the number of burst errors exceeds the threshold. Referring now to Fig. 5, the decoder 16 searches the error pattem from both ends for b τn jT , the first 1 in the error pattem, and by AST , the last 1 in the error pattem (step 400). It then sets to all zeros the bits ^FIRST tnrou gh b τ RS' τ , T ι and bits by A T through by . ~ _,, .. (steps 401-402). Next, it determines if any l's remain in the error pattem (step 403). If so, the system determines that the pattem contains three or more burst errors, and thus, that the error threshold is exceeded (step 404). Otherwise, the system determines that there are at most two burst errors, and thus, that the error correction operations accurately reproduced the recorded data (step 405). To free buffer space, the system may limit to L-1 the number of consecutive zeros between any two l's in the error pattem. Consider the exemplary error pattem: 00100001011100010000000000000000000010100000000111110000000000... By limiting the number of consecutive zeros to L-1 , the error pattem becomes: 10000101110001000001010000011111... The length of the pattem is thus reduced, without altering the burst error count, which remains at 5. If the burst errors are spread out in the error pattem, a significant amount of buffer space can be freed by limiting the included sequences of consecutive zeros. Another way to free buffer space is to separate the error pattem into segments. The segments begin and end with l's and their boundaries are determined by strings of L-1 or more zeros. The error pattem thus becomes 100001 1110001 101 11 1110 and the burst errors are determined by associating up to L- 1 bits with the first bit in each segment and any remaining l's in a segment with subsequent burst errors. As illustrated by the underlined portions: 100001 111000 1 101 11111 the burst error count remains at 5, with the second segment containing two burst errors. If the number of symbols in the burst errors, rather than the number of bits, is important, the decoder 16 counts "symbol burst errors" by first mapping the symbols that represent the error pattem to a binary sequence in which the l's represent erroneous symbols and the 0's represent error-free symbols. Thus, the bits in the error pattem are first mapped to symbols and the symbols, in turn, are mapped to the binary sequence. The decoder then counts the bursts in the binary sequence as described above and compares the count to an associated symbol burst error threshold. As an example, consider the sequence: ooooooooos 1 s 2 ooooooooooos 3 s 4 s 5 s 6 s 7 oooooooooooos 8 s 9 s 10 ooooooooooo... in which the S.'s represent erroneous symbols. This sequence is mapped to the binary sequence ooooo ooπoo ()oθ{χx)oιιιιιo{χκx)oo()(κ)()θi ιιθ(κ)(κ)oooooo ... The decoder 16 counts the bursts of symbols by detecting the first 1 in the sequence and associating with it the appropriate L-1 bits. It then increments its burst count and searches for a next 1 in the remaining sequence. If L=6, the system counts 3 symbol burst errors. As discussed above, the decoder 16 determines for each error pattem a unique. minimum number of burst errors of less than or equal to a predetermined size. The decoder determines burst errors based either on a number of bits or a number of symbols, as appropriate. Further, the system limits the data sectors it treats as accurately corrected to those sectors that contain fewer than a predetermined number of burst errors. In this way, the system avoids potentially misinterpreting one or more of the code words contained in the sector. The foregoing description has been limited to a specific embodiment of this invention. It will be apparent, however, that variations and modifications may be made to the invention, with the attainment of some or all of its advantages. Therefore, it is the object of the appended claims to cover all such variations and modifications as come within the true spirit and scope of the invention.

Claims: CLAIMS What is claimed is: 1. A system for counting burst errors, the system including: A. means for producing an error pattem consisting of ones representing erroneous bits and zeros representing non-erroneous bits of N code words that are recorded together; B. a burst counter for counting burst errors, the counter being initially set to zero; C. burst detecting means for determining the position of a next one bit, error pattem; D. means for associating with bpyr j oy the next L-1 bits in the error pattem, where L is a maximum burst length associated with the system; and E. means for incrementing the burst count for each by-ro e -r located by with the burst detecting means, the burst detecting means determining the position of a next one bit in the bits of the error pattem following the L-1 bits associated with bpyy, y and the burst counter counting the number of burst errors in the error pattem. 2. The system of claim 1, wherein the system further includes means for comparing the burst count with a predetermined burst error threshold, said means preventing the system from continuing to count burst errors if the burst error count exceeds the threshold. 3. The system of claim 2, wherein the system still further includes a buffer for holding the error pattem, the buffer including means for limiting to L-1 the number of zero bits between consecutive one bits. 4. The system of claim 2, wherein the system still further includes: i. an address counter for determining a bit count for bpy j , ~ -,; and ii. a memory for storing the count of the address counter as an indication of the location of the burst errors. 5. The system of claim 2, wherein the system still further includes: i. a second burst detector means for determining the position in the error pattem of a last one bit, by AST >, the second burst detector means searching preceding bits of the error pattem, starting from an end of the pattem that is associated with the last bit of the code word; ii. means for determining if bpyy j τ and by AST are included in the same burst error, said means determining the bits are in the same burst error if the L- 1 st bit associated with D FIRST * s * n e same P os ^ uon ^ or beyond the position of by A Q T in the error pattem; iii. means for incrementing the burst count by two if bp jϋST and by A τ are not part of the same burst error, said means incrementing the burst count by one if bp m ςr y , and b τ Δ ςτ are part of the same burst error. 6. The system of claim 5, wherein the system still further includes: i. an address counter for determining, respectively, a bit count for by- ™ ςτ and a bit count for the bit that precedes by A<?τ by L-1 bits; and ii. a memory for storing the counts of the address counter as indications of the locations of the two burst errors. 7. A system for determining if a sector of data contains more than two burst errors, the system including: A. means for producing an error pattem consisting of ones representing erroneous bits and zeros representing non-erroneous bits of the sector of data, the error pattem having first and second ends, the first end being associated with the first bit of the sector and the second end being associated with the last bit of the sector; B. first burst detecting means for determining the position of a next one bit, by ™ ™ , in the error pattem, the first burst detecting means starting at the first end of the error pattem; C. second burst detecting means for determining the position of a preceding one bit, D AST ' n ^ error P attern > e second burst detecting means starting at the second end of the error pattem; D. means for setting to all zeros and the next L-1 bits in the error pattem and b y A< - τ the preceding L-1 bits in the error pattem, where L is a maximum burst length associated with the system; and E. means for determining if any one bits remain in the error pattem, said means asserting an error signal if any one bits remain. 8. A system for correcting errors in a sector of N code words, the system including: A. means for producing a sector-long error pattem consisting of ones representing erroneous bits and zeros representing non-erroneous bits; B. a burst counter for counting burst errors, the counter being initially set to zero; C. burst detecting means for determining the position of a next one bit, bpyy-,„ T , in the error pattem; D. means for associating with the next L-1 bits in the error pattem, where L is a maximum burst length associated with the system; and E. means for incrementing the burst count for each located by with the burst detecting means, the burst detecting means determining the position of a next one bit in the bits of the error pattem following the L-1 bits associated with 9. The system for counting burst errors in a sector of N code words of claim 8, the system further including comparing means for comparing the burst count with a predetermined burst error threshold, the comparing means preventing the system from correcting errors in the code word if the burst count exceeds the threshold. 10. The system of claim 9, wherein the system still further includes a buffer for holding the error pattem, the buffer including means for limiting to L-1 the number of zero bits between consecutive one bits. 11. The system of claim 9, wherein the system still further includes: i. an address counter for determining a bit count for b j n o and ii. a memory for storing the count of the address counter as an indication of the location of the burst errors. 12. The system of claim 9, wherein the system still further includes: i. a second burst detector means for determining the position in the error pattem of a last one bit, b τ A ς T , the second burst detector means searching the preceding bits of the error pattem from an end of the pattem associated with the last symbol of the sector; 15 ii. means for and by AST are included in the same burst error, said means determining the bits are in the same burst error if the L-1 st bit associated with ''FIRST * S n me same P os i α o n as or beyond the position of by A ^ T in the error pattem; iii. means for incrementing the burst count by two if bpyy,ς T and by A ς T are not part of the same burst error, said means incrementing the burst count by one if by- ς T and b τ Δ ςτ are part of the same burst error. 13. The system of claim 12, wherein the system still further includes: i. an address counter for determining, respectively, a bit count for by- ™ ς T and a bit count for a bit that precedes by A „ τ by L-1 bits; and ii. a memory for storing the counts of the address counter as indications of the locations of the burst errors. 14. The system of claim 13 wherein the means for producing an error pattem includes means for mapping erroneous symbols to a sequence of bits. 15. A system for determining if a sector contains more than two burst errors, the system including: A. means for producing an error pattem consisting of ones representing erroneous symbols and zeros representing non-erroneous symbols, the error pattem having first and second ends, the first end being associated with the first symbol of the sector and the second end being associated with the last symbol of the sector; B. first burst detecting means for determining the position of a next one bit, by- ™ ^ T , in the code word error pattem, the first burst detecting means starting at the first end of the error pattem; C. second burst detecting means for determining the position of a preceding one bit, by A „ τ , in the error pattem, the second burst detecting means starting at the second end of the error pattem; D. means for setting to all zeros by-™ ςT an d me next L-1 bits in the error pattem, and by Aςτ the preceding L-1 bits in the error pattem, where L is a maximum burst length associated with the system; and E. means for determining if any one bits remain in the error pattem, said means asserting an error signal if any one bits remain. 16. The system of claim 15 wherein the means for producing an error pattem includes means for mapping erroneous symbols to a sequence of bits.

Inventors: HUI PAK NING, KOK AN-LOONG, WENG LIH-JYH, HUI, PAK, NING, KOK, AN-LOONG, WENG, LIH-JYH
Applicants: QUANTUM CORP, QUANTUM CORPORATION
Application year: 1996
Main classification: H03M13
IPC codes: G11B20, H03M13, H04L1