Method and apparatus for decoding RLL modulated data using tables of reduced sizes

Abstract: The invention relates to a method and an apparatus for decoding RLL modulated data using tables of reduced sizes whereby the data are recorded on an optical disk, specifically a digital video disk (DVD). Even if an element such as a ROM is not used, a code reverse conversion can be realized by a sufficiently small scale circuit to be effective for integration. When code data group converted from 8-bit to 15-bit according to a predetermined rule is converted to original 8-bit code data group, an exclusive logic processor 11, a bit shift processor 12, a six-to-four decoder and an eleven-to-eight decoder 14 divides the 15(m) bit code (dividing by m at the maximum) into a plurality of areas, converts "1" (in the case of positive logic) in response to the generated bit position in the respective areas, and the numeric codes obtained by the numeric value converting means are added by an adder 15.

Description: This invention relates to a data decoding apparatus and a method of decoding data that fetches a signal from a recording medium such as an optical disk which records digital data by using specific modulation techniques and converts the modulated data to original digital data. Recently, as digital compression technology advances, digitized video and audio data could have been recorded on storage media such as optical disks. Specifically, a video disk of next generation called a "DVD (Digital Video Disk)" is noticed as for storing sharp video which cannot be found in the conventional video equipment in a small-diameter disk. However, the performance required for the DVD is not only high-efficiency compression technology. From the necessity of recording video and audio for long time up to two hours or more, it is absolutely indispensable factor to enhance the high density of the disk itself. The recording density of the disk is not only the physical surface density by merely shortening a pit length and narrowing a track pitch by considering the limit in the optical properties such as a laser wavelength, the NA of a lens, etc. To increase the density of the disk as much as possible in the present optical system, it is an important subject to improve the modulation techniques at the signal processing field side. In this connection US-A-5 155 485 teaches a code modulating apparatus and a code demodulating apparatus for digital signals such as PCM audio signal, computer data, and so on. An input signal of M bit words is divided into a plurality of data bits and the code conversion is performed for respective data bits, thereby simplifying the circuit arrangement for data conversion. According to the present invention there is obtained a modulation code that is expected for the high density of the disk and also a modulation code that is expected for enhancing the density of a disk recording without largely enlarging the scale of a decoding processor. The object of the present invention is to provide an apparatus for decoding data and a method of decoding data which can easily restore a modulation code having a long bit length to an original source code. To accomplish the foregoing object, according to one preferred aspect of the invention, there is provided an apparatus for decoding data as defined in claim 1. According to another preferred aspect of the invention, there is provided a method for decoding data as defined in claim 6. Accordingly, the modulation code having the long bit length is divided into a plurality of areas and processed. Therefore, circuit scale for decoding the components of the respective area may be small, and the reduction in size of the circuit scale as a whole can be realized. This invention can be more fully understood from the following detailed description when taken in conjunction with the accompanying drawings, in which : FIG. 1A is an explanatory view showing the content of an eight-to-fifteen conversion table A; FIG. 1B is a view showing the continued content of FIG. 1A; FIG. 1C is a view showing the continued content of FIG. 1B; FIG. 1D is a view showing the continued content of FIG. 1C; FIG. 1E is a view showing the continued content of FIG. 1D; FIG. 2A is an explanatory view showing the content of an eight-to-fifteen conversion table B; FIG. 2B is a view showing the continued content of FIG. 2A; FIG. 3A is an explanatory view showing the content of an eight-to-fifteen conversion table C; FIG. 3B is a view showing the continued content of FIG. 3A; FIG. 4 is an explanatory view showing the content of an eight-to-fifteen conversion table D; FIG. 5 is an explanatory view showing the content of an eight-to-fifteen conversion table E; FIG. 6A is an explanatory view showing the content of an eight-to-fifteen conversion table F; FIG. 6B is a view showing the continued content of FIG. 6A; FIG. 6C is a view showing the continued content of FIG. 6B; FIG. 7 is a view showing an example of a fifteen-to-eight decoder; FIG. 8 is a view showing a decoder according to one embodiment of the present invention; FIG. 9 is a view showing a detailed exclusive OR processor of FIG. 8; FIG. 10 is a view showing a detailed shift processor of FIG. 8; FIG. 11A is an explanatory view showing to explain the progress of converting the code converted by the eight-to-fifteen modulation conversion table F into the same content as the code converted by the tables A and B by an exclusive logic processor; FIG. 11B is an explanatory view showing to explain the continuation of FIG. 11A and the progress of converting the code converted by the eight-to-fifteen modulation conversion table F into the same content as the code converted by the tables A and B by an exclusive logic processor and a shift processor; FIG. 12 is a view showing the logic conversion table of a six-to-four decoder; FIG. 13 is a view showing the detailed circuit of the six-to-four decoder; and FIG. 14 is a view showing the logic conversion table of an eleven-to-eight decoder. Hereinafter, embodiments of the present invention will be explained in detail with reference to the accompanying drawings. First, the technology of the premise of the present invention will be explained with reference to FIGS. 1 to 7. To increase the recording density of a disk, modulation techniques for enabling the density to be increased by (2, 7) PLL modulation or an EFM in response to the request for improving the modulation techniques at the signal processing field side are proposed. This is an eight-to-fifteen modulation for converting, for example, an 8-bit digital code into a 15-bit code according to a specific rule. Since at least two bits "0" exist between the bit "1" and the bit "1" in a modulation code row, the minimum inversion interval Tmin of the data after non-return-to-zero NRZI is (3 × (8/15))T = 1.6T (where T is data period before the modulation), a detecting window width Tw is (8/15)T = about 0.53T, and hence the improvement in the recording density is expected. An example of the translation rule of the abovedescribed eight-to-fifteen modulation will be explained. Six types of tables A to F for converting the 8-bit source code into the 15-bit modulation code are prepared. The respective tables will be explained. There are 189 types of the 15-bit codes in which the two bits of the rightmost side becomes ".....00". The table A is produced by preparing 175 types except the following 14 types from the above-mentioned 189 types. The table A is used to convert the 8-bit source code of 0 to 174 represented by decimal. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 The entire codes of the table A are shown in FIGS. 1A to 1E. When the output codes of the table A is observed, the following can be stated. The maximum run in the own code continues eleven "0" as seen in "1 0 0 0 0 0 0 0 0 0 0 1 0 1". The rightmost run continues two "0" at the minimum and eleven "0" at the maximum, and the leftmost run continues zero "0" at the minimum and seven "0" at the maximum. The 59 types of the codes are started from the code of "1". There are 88 types of the 15-bit codes in which the four bits of the rightmost end become "...0 0 1 0". The table B is produced by preparing the 81 types except the following seven types from the above-mentioned 88 types. The table B is used to covert the 8-bit source codes of 175 to 255. 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 The entire codes of the table B are shown in FIGS. 2A and 2B. When the output codes of the table B are observed, the following can be stated. The maximum run in the own code continues eleven "0" as observed in "0 1 0 0 0 0 0 0 0 0 0 1 0". The rightmost run is "1", and the leftmost run continues zero "0" at the minimum and six "0" at the maximum. There are 27 types of the codes in which the leading number is "1". There are 129 types of the 15-bit codes in which the rightmost three bits become "....0 0 1". The tables C, D and E are produced by preparing 115 types by removing the following 14 types from the above-mentioned 129 types. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 1 1 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 When the 115 types of the 15-bit codes are observed, the following can be stated> The maximum run in the own code continues twelve "0" as observed in "0 1 0 0 0 0 0 0 0 0 0 0 0 1". The rightmost run is "0", and the leftmost run continues zero "0" at the minimum and six "0" at the maximum The tables C, D and E are set as follows by using the codes therein. The table C contains 81 types of the above-mentioned 115 types in which the rightmost end is "...0 0 0 1", and coincides at the leftmost run with the table B. The table C is used to convert the source codes of 175 to 255, and its conversion outputs all become "0 0 0 1" at the rightmost four bits. The entire codes of the table C are shown in FIGS. 3A and 3B. The table D contains 34 types of the above-mentioned 115 types in which the rightmost end is "...0 0 1 0 0 1", and coincides at the leftmost run with the table A. The table D is used to convert the source codes of 0 to 33 so that all the rightmost end six bits become "0" when converted by the table A. The right-most end four bits of the converted outputs all become "1 0 0 1". The entire codes of the table D are shown in FIG. 4. The table E contains the codes shown in FIG. 5 arbitrarily selected from the 115 types in which the leftmost run is 2 or more. The table E selects the source codes so that all the rightmost end six bits become "0" when the 86 types of the source codes to be converted in the table F to be explained later (FIGS. 6A to 6C) are converted by the table F. The converted outputs of the table E used to convert the selected source codes contain 17 type codes in which all the rightmost end three bits become "0 0 1" and the leftmost end two bits become "0 0". The table F contains 86 types in which the following two types are removed from the 88 types of the 15-bit codes of "0 0....0 0" (FIGS. 6A to 6C). 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 The maximum run in the own code continues nine "0" as observed in "0 0 1 0 0 0 0 0 0 0 0 0 1 0 0". The rightmost run continues two "0" at the minimum and eleven "0" at the maximum, and the leftmost run continues two "0" at the minimum and twelve "0" at the maximum. The table F is obtained by selecting the source codes in which the leftmost end one bit becomes "1" when the source codes of 0 to 255 are converted by the table A or B. The converted outputs of the table F used to convert the selected source codes contain 86 types in which all the rightmost end two bits are "0 0" and the leftmost end two bits are "0 0". When the types and the features of the contents of the 15-bit codes of the tables A to F described above are summarized, the following is obtained. Table A contains 175 types (tail code:...0 0) Table B contains 81 types (tail code:...0 0 1 0) Table C contains 81 types (tail code:...0 0 0 1) Table D contains 34 types (tail code:...0 0 1 0 0 1) Table E contains 17 types (leading code:0 0.. tail code: ...0 0 1) Table F contains 86 types (leading code:0 0.. tail code: ...0 0) The total sum of the types of the codes are 474. When the relationships between the above tables are summarized, the following is obtained. All the codes of the table B do not exist in the other tables. All the codes in the tables C and D are not duplicate from each other. The leftmost run of the table C coincides with the leftmost run of the table B. The leftmost run of the table D coincides with the leftmost run of the table A. Almost all the codes of the table F exist in the table A. All the codes of the table E exist in the tables C and D. In the foregoing description, only the contents of the converted codes corresponding to the source codes are designated. Then, a method of designing how to allocate the source codes to the respective tables will be explained. (1) Source codes 0 to 174 (175 types) The source codes are allocated to the table A. The 34 types of the source codes in which the rightmost end run becomes 6 or more in the table A are also allocated to the table D for the case that the run at the time of connecting to next code become 13 or more. The 59 types of the source codes in which the leading bit becomes "1" in the table A are also allocated to the 59 types of the 86 types of the table F. The 17 types of the source codes in which the rightmost end run becomes 6 are also allocated to the table E for the case that the run becomes 13 or more at the time of connecting to the next code. (2) Source codes 175 to 255 (81 types) The source codes are allocated to both the tables B and C. The 27 types of the source codes in which the leading bit becomes "1" in the table B are also allocated to the 27 types of the 86 types of the table F. Then, when the tables are produced based on the above-mentioned designing conditions, the converting conditions of the input source codes (table using conditions) become the following algorithm. (1) For source codes 0 to 174 Complete one byte conversion is conducted including the case that the conversion table of the present source codes is determined according to the next source code. Specifically, when 141 types of the source codes except the 34 types allocated to the table D are input, the source codes are converted by the table A despite the next source codes. When the 34 types of the source codes also allocated to the table D are input, in the case that the connecting results of the 15-bit codes converted by the table A and the 15-bit codes converted by the table A or B from the continuous second byte become 13 or more, the source codes are converted by the table D instead of the table A. If not, the source codes are converted by the table A. Specifically, the source codes of 0 to 174 are fundamentally converted by the table A. However, when the source codes in which 13 or more "0" are continued to the connecting result of the case that the source codes continued to the next are converted by the table A or B are input (which might occur in the 34 types of the source codes of 0 to 33) are converted by the table D. (2) For source codes 175 to 255 Any of the 170 types of the source codes in which the leading bit becomes "0" when the next source codes are converted by the table A or B is completely one byte converted by the table B for the present source codes. When the source code of the second byte is converted by the table A or B, any of the 86 types in which the leading bit becomes "1" is perfectly two byte-complete-converted according to the following sequence. First, initial source codes 117 to 255 are converted not by the table B but by the table D and determined. The second byte source code of any of the 86 types of the source codes is converted as follows. The second byte source code of the 69 types except the 17 types allocated also to the table E is converted by the table F despite the third byte source code to complete the second byte source code. However, the second byte source code of the 17 types allocated also to the table E is converted by the table E instead of the table F when the connecting result of the 15-bit code converted by the table F and the 15-bit code converted by the table B becomes run 13 or more, and if not, it is converted by the table F to complete the second byte. Specifically, the source codes of 177 to 255 are fundamentally converted by the table B, but when the source code continued to next is converted by the table A or B, in the case of the source codes of the 86 types in which the leftmost end bit becomes "1", it is converted by the table C. At this time, the next second source code is converted by the table E or F. Specifically, when the conversion using the table C is conducted, the conversion using the table E or F is always executed next. Whether or not the source code is converted by the table F or E is determined according to the content of the third source code further continued. The source code is fundamentally converted by the table F, but 13 or more "0" are continued at the connecting result when the third source code is converted by the table A or B (which might occur in the source codes of the 17 types of the table F), is converted by the table E. The algorithm of the case that the 15-bit codes code-modulated by using the tables A to F as described above is decoded to the source code will be explained. The decoding is handled as the 1-byte or 2-byte complete conversion. The input 15-bit codes are decoded according to any of the tables A, B, C and D. Since the codes are not duplicated from each other, the codes are unitarily correctly decoded. Of course, when the present 15-bit codes are decoded by using the table C, the next input 15-bit code is decoded according to the table E or F. As described above, the modulation from the 8-bit code to 15-bit code and simultaneous decoding from the 15-bit code to the 8-bit source code can be executed. Specifically, when m-bit source code is converted to n-bit conversion code, it can be easily converted directly to (>m)-bit conversion code without using a complicated procedure like the conventional procedure that it is once converted to smaller q-bit intermediate code than n-bit and (n - q) bits are added thereto, and its reverse conversion can be directly executed. The modulation needs to be monitored for the source code in the 3 byte width as the maximum, but the modulation result is completed in the two byte width. The demodulation is simple. The steps of referring to the conversion table at each one modulation code to demodulate it to one byte and simultaneously determining the conversion table used for demodulating the next modulation code are merely repeated. The conversion tables between the 8-bit and 15-bit codes include 6 types, total number of 474 (the details of which fundamentally include 2 types of tables, 256 and 4 types of substitutes, 218). In the converting operation, the data contents of only the connector of 15 bits + 15 bits are not always altered, but the entirety is altered of the complete type in which the leading bit of the 15 bits continued to next is not altered, and all the conversions are conducted according to the respective separate tables based on the divided simple cases. Specifically, the conversion of the different source code 8 bits to the 15 bits of the same conversion code between the different tables is recognized by preparing the separate tables divided to the cases according to the continuous state of the source codes, and hence the conversion codes of less number are peculiarly devised. The decoding algorithm for reversely converting the digital data code-converted as described above to the original code will be simply explained. The 15-bit modulation codes representing at first are converted by any of the tables A, B, C and D, and since the codes are not duplicated, the discrimination of the A, B, C or D is facilitated by the rightmost end 2 - 4 bits. The codes are converted by reverse tables based on the discriminated result to be decoded. If the input data is judged to be converted by the table C, the next modulation code is always converted by the table F or E, and hence the modulation code continued to next is converted by any of the reverse tables of the F or E. FIG. 7 shows the configuration of a decoding apparatus for decoding eight-to-fifteen modulation code. Table reverse converters 1 to 6 from the table A to the table F are connected to 15-bit input data line, and the outputs are sent to a selector 7. A table selector 8 determines which of table reverse converters 1 to 6 is selected according to the rightmost end 4 bits of the input data and the decoding selected result before the previous times (the output of a latched circuit 9). The decoding algorithm and the configuration itself of the decoding apparatus itself described above are simple, but when it is intended to be actually integrated, it has a problem in a scale. Since the contents of the tables are complicated, there are a method of using a ROM, a method of designing a converter with a logical synthesis driven by a computer, but since the types of the tables are many, its efficiency is low, and it results in a gate scale up to several kilo gates to occupy considerable chip area. In the case of a single IC of a decoding circuit, it is facilitated, but when an integration accompanied with other signal processors is considered, an increase in a chip size and hence an increase in its cost occurs, and even if the high density is provided, its effect is reduced by half. Therefore, the present invention contemplates to realize an apparatus for decoding data and a method of decoding data in which a modulation code expected for its high density of disk recording is easily recoverable in a scale without great difference from a decoding processor according to the above-described modulation techniques and a recording medium. Specifically, the present invention fundamentally comprises exclusive logic means for converting an arbitrary bit to "1" or "0" in response to a specific bit pattern generated in m-bit code, bit shift means for shifting the partial or entire bit position of the m-bit code by a predetermined quantity in a rightward or leftward direction, a plurality of numeric value converting means for dividing the m-bit code into a plurality of areas (dividing by m at the maximum) and converting it to a predetermined numeric code in response to the bit position for generating "1" (in the case of positive logic) in the respective areas, and numeral data processing means for adding or subtracting the numeric code obtained by said numeric value converging means. The features of the present invention will be explained with reference to the accompanied drawings. FIG. 8 is an embodiment of the present invention. A 15-bit (HD0 to HD14 sequentially from a right side bit) modulation code introduced to an input unit IN is supplied to an exclusive logic processor 11. The 15-bit data processed by the exclusive logic processor 11 is input to and processed by a shift processor 12. The data (SD0 to SD13) output from the shift processor 12 are distributed to a six-to-four decoder 13 and an eleven-to-eight decoder 14. The 8-bit outputs of the six-to-four decoder 13 and the eleven-to-eight decoder 14 are input to an 8-bit adder 15. The output of the 8-bit adder 15 is input to and latched by a latched circuit 10, and output to an output unit OUT as decoded data. The 15-bit modulation code of the input unit IN is also input to a pattern control circuit 16. The pattern control circuit 16 discriminates which table the 15-bit modulation code is converted by. When the 15-bit modulation code is converted by the table A or B, the exclusive logic processor 11 and the shift processor 12 are so controlled as not to conduct any but output the 15-bit modulation code as it is. The reason why the bit signal of HD14 is not output from the shift processor 12 as the SD14 is because it is invalid bit in which "0" in both the tables A and B. When the input modulation codes (HD0 to HD14) are modulated by the table C or D, the exclusive logic processor 11 is validated. When the input modulation codes are modulated by the table E or F, either the exclusive logic processor 11 or the shift processor 12 is validated in response to the content of the bits of the HD2. Thus, the modulation code modulated by the table C, D, E or F is replaced with the modulation code modulated by basic table A or B. When the modulation of the input modulation codes by the table E or F is determined, it is determined according to the output of the latched circuit 9 for latching whether or not the modulation code input by decoding before the previous time is modulated by the table C. FIG. 9 shows the detailed configuration example of the above-described exclusive logic processor 11. The exclusive logic processor 11 detects the bit in which "1" of the input modulation code is set up, converts the bit "1" to "0" if the rightward third bit from the bit is "1", or converts the bit to "1" if the rightward third bit is "0". The final bit of the conversion is fundamentally obtained by an exclusive OR circuit 17 group. However, when the bit is converted from "0" to "1", whether or not the right adjacent second bit from the bit is "0" is detected by an OR circuit 18 group, it is converted in the case of "0", and limited to only the case that the converted result is not deviated from the translation rule. In the conversion process, an AND circuit 19 group for preferentially outputting to the leftward side are provided, and only one bit is to be its objected within one code. For instance, when the input modulation code is next code determined to be converted by the table F, the source code before the modulation is 40 by decimal number. HD 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 0 0 0 1 0 0 0 1 0 0 1 0 0 0 When this is observed from the leftward direction, "1" is first set up in the HD4. In this case, it tends to convert the bit of the HD 7 to "1", but since the logic OR result of the HD8 and the HD9 are not "0", it cannot be converted. Then, "1" is set up in the HD8. This time, the bit of the HD11 is to be its object, but since its original is "1", it is converted to "0" despite the values of the HD12 and the HD13. The converted results are as follows HD 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 When the bit of the HD0 is forcibly set to "1", its content coincides with the source code 40 of the table A. Thus, the bit processing is executed in the exclusive logic processor 11 under predetermined conditions, it is resultantly returned to the source codes of the table A and B, and prepared for the following decoding process. FIG. 10 is the detailed configuration of the shift processor 12. The shift processor 12 is fundamentally a mere 2-input selector 20 group. The signal is switched from the bit position of right adjacent second bit from the normal bit position to the bit position of the right adjacent second bit. Gate circuits 21 and 22 provided at the route of the SD0, the SD11 and the SD13 forcibly convert the bit to "1" or "0" according to gate signals G0, G11, G13. FIGS. 11A and 11B show the process of converting the eight-to-fifteen-modulated conversion table F to the conversion code of the same content as that converted by the table A or B by the exclusive logic processor 11 and the shift processor 12 as an example. The codes of the range of the source codes 1 to 174 are conducted for exclusive logic processing, and the codes of the range of the source codes 178 to 254 are executed for shift processing. "1 0 0 1" is converted to "1 0 0 0" and "1 0 0 0" is converted to "1 0 0 1" as indicated by an underline in the codes of FIGS. 11A and 11B. Then, the bits indicated by "*" are forcibly converted to "1", and hence converted to the codes of the same content as that of the code converted by the table A or B. With respect to the other tables C, D and E, the same operation is executed, and fundamentally the same except that the bit positions to be forcibly converted to "1" or "0" are slightly different. The six-to-four decoder 13 and the eleven-to-eight decoder 14 will be explained. FIG. 12 shows the logic conversion table of the six-to-four decoder 13 and FIG. 13 shows the detailed circuit example of the six-to-four decoder. The number of the input bits is 14. The fundamental concept is the conversion of six bits to four bits. The translation rule is defined to sum the converted value (decimal converted values 1, 2, 3, 4, 6, 9 shown in FIG. 12) of the bit in which "1" is set up in the SD0 to SD13 to be input and convert it to binary number. For instance, in the case of "0 1 0 0 0 1", "1" is set up in the SD1 and the SD5. When the converted value 2 and the converted value 9 are summed, the total sum becomes 11. When it is converted to a binary number, "1 0 1 1" is obtained. This is used as the decoded output. The example of the circuit for realizing this process is shown in FIG. 13, which contains OR circuits, AND circuits, inverters, NAND circuits, etc. This circuit is merely illustration only, and various embodiments can be provided based on the above-mentioned theory. FIG. 14 shows the logic conversion table of the eleven-to-eight decoder 14. This decoder 14 is provided by the same way of concept as the six-to-four decoder 13. The decoder 14 sums the converted values of the bits in which "1" are set up in the input SD. However, the converted value of "1" set up at the rightmost end and the bits except it are different in the converted values. For instance, in the case of "1 0 0 1 0 0 1 0", "1" is set up in the SD6 and the SD9 and further the SD12. "1" disposed at the rightmost end of the bit row is at the position of the SD12, and when the table under this row is observed, 117 is described. "1" of the SD6 is the converted value 13 when the table under it is observed. "1" of the SD9 is the converted value 39 (since the SD13 is "0") when the table under it is observed. Then, when the 117, the 13 and the 38 are summed, the total sum becomes 169. When the 169 is converted to corresponding binary number by searching it in the column of the decimal display, it becomes "1 0 1 0 1 0 0 1" (169 by the decimal). This is used as the decoded output. The decoded output LBT (LBT4 to LBT7 are fixed to "0 0 0 0") obtained as described above and the HBT are input to the 8bit adder 15 to be added. Thus, the original source code is restored. The present invention is not only applied to the decoding of the above-described eight-to-fifteen modulation code, but also applied to various applications. The method of dividing the modulation code to be varied at its numeric value and adding them can be applied to various tables. For instance, it is not indispensable that the source code "0" started like the table A is "0 0 0 1 0 0 0 0 0 0 0 0 0 0 0" or the conversion bit width is 15 bits, but the source code "0" started as indicated next may be 14-bit conversion table of "1 0 0 0 0 1 0 0 0 0 0 0 0 0". HD Source code 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 2 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 3 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 5 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 6 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 7 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 8 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 9 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 11 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 : : 19 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 20 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 : : In this case, a six-to-eight numeric vale conversion decoder for dividing HD0 to HD5 and HD6 to HD13 so determined that the converted value of the bit position of the HD0 is set to "1", the converted value of the bit position of the HD1 is set to "2", the converted value of the bit position of the HD2 is set to "3", the converted value of the bit value of the HD3 is set to "4", and an eight-to-eight numeric value conversion decoder so determined that the converted value of the bit position of the HD6 is set to "4", the converted value of the bit position of the HD7 is set to "10" are used, and adding to be realized. In summary, there is provided the code group in which the position where "1" is set up is varied along with the rule of "setting up "1" from the leftward or rightward direction and forcing it while satisfying the conditions that determined number of "0" are always existed between the "1" and "1" to match the increase of the source code represented by the decimal number from the output conversion code as described above, the present invention may be applied. Of course, there is no problem even if slight omission occurs on the way of the table. For example, the following table of : n-1 0 1 0 0 0 1 0 0 1 0 0 1 0 0 n 0 0 1 0 0 1 0 0 1 0 0 1 0 0 n+1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 n+2 1 0 0 0 0 0 0 0 1 0 0 0 1 0 may be produced as follows : n-1 0 1 0 0 0 1 0 0 1 0 0 1 0 0 n 0 0 1 0 0 1 0 0 1 0 0 1 0 0 n+1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 n+2 0 1 0 0 0 0 0 0 0 0 0 0 1 0 Accordingly, the present invention may be applied to the case that the minimum number of "0" existing between the "1" and the "1" is 3 or 4 or more. How the converted value to the decimal number to be used in the decoder is set, and the fundamental concept is the same. In the embodiment described above, the modulation code is divided into the two areas. However, according to the present invention, the modulation code may be divided into three or four areas. In this case, the numeric value conversion tables are simplified, but the hardware of the addition side is, contrary, increased. As a result, it is preferable to set the number of divisions by considering the balance of the entirety. According to the present invention as described above, the code reverse conversion (decoding) can be realized by a sufficiently small scale circuit even without using elements such as ROM, etc., and is remarkably effective to integrate the configuration. Thus, the chip size of the IC itself is suppressed, and the high density of the optical disk can be realized without increasing the cost.

Claims: A decoding apparatus for converting an m-bit conversion code into an n-bit source code, comprising: first and second decoding means (13, 14) for dividing an m-bit conversion code into first data and second data, and for decoding the first data and the second data, thereby obtaining a first decode output and a second decode output, respectively; and adding means (15) for adding the first and second decode outputs from said first and second decoding means (13, 14), thereby obtaining data for obtaining an n-bit source code, wherein the n-bit source code is converted into the m-bit conversion code and the m-bit conversion code satisfies the following rules: (i) at least two bits "0" are successively interposed between bit "1" and bit "1" throughout the m-bit conversion code; (ii) at least two bits "0" are successively interposed between bit "1" included in rightmost end bits of the m-bit conversion code and bit "1" included in leftmost end bits of a subsequent m-bit conversion code; (iii) the maximum number of bits "0" successively located in the m-bit conversion code is limited to a predetermined number; characterized in that the n-bit source code is converted into the m-bit conversion code according to one of a plurality of conversion tables, and the m-bit conversion code further satisfies the following rules: (iv) it is determined which one of the conversion tables is used for converting the n-bit source code into the m-bit conversion code, on the basis of leftmost end bits of the m-bit conversion code and rightmost end bits thereof; and (v) even if n-bit source codes have the same bits, when the n-bit source codes are converted into m-bit conversion codes according to different conversion tables included in the conversion tables, bits of the m-bit conversion codes differ from each other; and the decoding apparatus further comprises pre-processing means for fetching the m-bit conversion code, said pre-processing means including: table identifying means (16) for identifying one of the conversion tables which is used for conversion of a presently fetched m-bit conversion code which is presently fetched by said pre-processing means, on the basis of a precedently fetched m-bit conversion code which has been fetched by said pre-processing means, precedent to the presently fetched m-bit conversion code; and arithmetic processing means (11, 12) for determining arithmetic processing to be performed on the presently fetched m-bit conversion code on the basis of an identification result of said table identifying means, for performing the arithmetic processing on the presently fetched m-bit conversion code, thereby to obtain a pre-processed m-bit conversion code, for dividing the pre-processed m-bit conversion code into first and second codes, and for supplying the first and second codes to said first and second decoding means (13, 14), respectively. A decoding apparatus according to claim 1, characterized in that: when said table identifying means (16) identifies said one of the conversion tables which is used for conversion of the presently fetched m-bit conversion code, as a first conversion table, said arithmetic processing means (11, 12) outputs the presently fetched m-bit conversion code as the pre-processed m-bit conversion code; and when said table identifying means (16) identifies said one of the conversion tables which is used for conversion of the presently fetched m-bit conversion code, as a second conversion table, said arithmetic processing means (11, 12) inverses or shifts predetermined bits of the presently fetched m-bit conversion code such that bits of the presently fetched m-bit conversion code are identical to bits of an m-bit conversion code into which an n-bit source code is converted according to the first conversion table, and then outputs the presently fetched m-bit conversion code as the pre-processed m-bit conversion code. A decoding apparatus according to claim 1, characterized in that the m-bit conversion code is included in a signal reproduced from an optical disk. A decoding apparatus according to claim 1, characterized in that: conversion codes for use in converting n-bit source codes into m-bit conversion codes (m>n) are stored in conversion tables A, B, C, D, E and F of the conversion tables; values expressed by n bits are "0" to "N"; each of n-bit source codes which respectively correspond to "0" to "N/2" is a first source code; each of n-bit source codes which respectively correspond to "{(N+1)/2}" to "N" is a second source code; the first source code is converted according to the conversion table A; an n-bit source code is converted according to the conversion table B when the n-bit source code has rightmost end bits including at least six "0" bits successively located; an n-bit source code is converted according to the conversion table F when a lead bit of the n-bit source code iS "1"; an n-bit source code is converted according to the conversion table E when a lead bit of the n-bit source code is "1" and right most end bits of the n-bit source code include at least six "0" bits successively located; and the conversion codes are stored in the conversion tables A, B, C, D, E and F such that the conversion codes satisfy the following conditions: (i) rightmost end two bits of each of the conversion codes stored in the conversion table A are "00"; (ii) rightmost end four bits of each of the conversion codes stored in the conversion table B are "0010"; (iii) rightmost end four bits of each of the conversion codes stored in the conversion table C are "0001"; (iv) rightmost end six bits of each of the conversion codes stored in the conversion table D are "001001"; (v) rightmost end three bits of each of the conversion codes stored in the conversion table E are "001"; (vi) rightmost end two bits of each of the conversion codes stored in the conversion table F are "00"; (vii) at least two bits "0" are successively interposed between bit "1" and bit "1" throughout each of the conversion codes; (viii) the maximum number of bits "0" successively located in each of the conversion codes stored in the conversion table A is eleven; (ix) the maximum number of bits "0" successively located in each of the conversion codes stored in the conversion table B is eleven; (x) the maximum number of bits "0" successively located in each of the conversion codes stored in the conversion tables C, D and E is twelve; (xi) the maximum number of bits "0" successively located in the conversion codes stored in the conversion table F is nine; (xii) the conversion codes stored in the conversion table B are not stored in any of the conversion tables A, C, D, E and F; (xiii) the conversion codes stored in the conversion table C differ from the conversion codes stored in the conversion table B; (xiv) the number of bits "0" successively located in leftmost end bits of each of the conversion codes stored in the conversion table C is equal to the number of bits "0" successively located in leftmost end bits of each of the conversion codes stored in the conversion table B; (xv) when n-bit source codes are converted according to the conversion tables A and D, each of m-bit conversion codes obtained according to the conversion table A has left most end bits which are identical to leftmost end bits of a corresponding one of m-bit conversion codes obtained according to the conversion table D with respect to succession of bits "0"; (xvi) if rightmost end bits of an m-bit conversion code to be obtained when the first source code is converted according to the conversion table A are connected to leftmost end bits of an m-bit conversion code to be obtained when an n-bit source code subsequent to the second n-bit source code is converted according to one of the conversion tables A and B, and at least thirteen bits "0" are successively located in the connected right most end bits and leftmost end bits, the first code is converted according to the conversion table D; (xvii) if a lead bit of m-bit conversion code to be obtained when the n-bit source code subsequent to the second source code is converted according to one of the conversion tables A and B is "1", the second source code is converted according to the conversion table C; (xviii) when the second source code is converted according to the conversion table C, the n-bit source code subsequent to the second source code is converted according to the conversion table F; (xix) if leftmost end bits of an m-bit conversion code to be obtained when the n-bit source code subsequent to the second source code is converted according to the conversion table F are connected to rightmost end bits of an m-bit conversion code to be obtained when an n-bit source code subsequent to the second source code is converted according to one of the conversion tables A and B, and at least thirteen bits "0" are successively located in the connected leftmost end bits and rightmost end bits, the n-bit source code subsequent to the second source code is converted according to the conversion table E. A decoding apparatus according to claim 4, characterized in that in a case where the m-bit conversion code is input, when said table identifying means identifies one of the conversion tables which is used to obtain the input m-bit conversion code, as one of the conversion tables C and D, exclusive logical processing is performed on the input m-bit conversion code such that bits of the input m-bit conversion code are identical to bits of an m-bit conversion code to be obtained when an n-bit source code, which is to be converted into the input m-bit source code according to one of the conversion tables C and D, is converted according to one of the conversion table A and B, and when said table identifying means (16) identifies one of the conversion tables which is used to obtain the input m-bit conversion code, as one of the conversion tables E and F, shift processing is performed on the input m-bit conversion code such that the bits of the input m-bit conversion code are identical to bits of an m-bit conversion code to be obtained when an n-bit source code, which is to be converted into the input m-bit conversion code according to one of the conversion tables E and F, is converted according to one of the conversion tables A and B. Method for converting an m-bit conversion code into an n-bit source code, comprising the steps of: dividing an m-bit conversion code into first data and second data, and decoding the first data and the second data, thereby obtaining a first decode output and a second decode output, respectively; and adding the first and second decode outputs, thereby obtaining data for obtaining an n-bit source code, wherein the n-bit source code is converted into the m-bit conversion code according to one of a plurality of conversion tables, and the m-bit conversion code satisfies the following rules: (i) at least two bits "0" are successively interposed between bit "1" and bit "1" throughout the m-bit conversion code; (ii) at least two bits "0" are successively interposed between bit "1" included in rightmost end bits of the m-bit conversion code and bit "1" included in leftmost end bits of a subsequent m-bit conversion code; (iii) the maximum number of bits "0" successively located in the m-bit conversion code is limited to a predetermined number; (iv) it is determined which one of the conversion tables is used for converting the n-bit source code into the m-bit conversion code, on the basis of leftmost end bits of the m-bit conversion code and rightmost end bits thereof; and (v) even if n-bit source codes have the same bits, when the n-bit source codes are converted into m-bit conversion codes according to different conversion tables included in the conversion tables, bits of the m-bit conversion codes differ from each other; and the method further comprises the steps of fetching the m-bit conversion code identifying one of the conversion tables which is used for conversion of a presently fetched m-bit conversion code on the basis of a precedently fetched m-bit conversion code, precedent to the presently fetched m-bit conversion code; and determining arithmetic processing to be performed on the presently fetched m-bit conversion code on the basis of an identification result, for performing the arithmetic processing on the presently fetched m-bit conversion code, thereby to obtain a pre-processed m-bit conversion code, for dividing the pre-processed m-bit conversion code into first and second codes. Method according to claim 6, characterized by when said one of the conversion tables is identified which is used for conversion of the presently fetched m-bit conversion code, as a first conversion table, outputing the presently fetched m-bit conversion code as the pre-processed m-bit conversion code; and when said one of the conversion tables is identified which is used for conversion of the presently fetched m-bit conversion code, as a second conversion table, inverting or shifting predetermined bits of the presently fetched m-bit conversion code such that bits of the presently fetched m-bit conversion code are identical to bits of an m-bit conversion code into which an n-bit source code is converted according to the first conversion table, and then outputing the presently fetched m-bit conversion code as the pre-processed m-bit conversion code. Method according to claim 6 or 7, characterized in that the m-bit conversion code is included in a signal reproduced from an optical disk. Method according to one of the claims 6 to 8, characterized in that: conversion codes for use in converting n-bit source codes into m-bit conversion codes (m>n) are stored in conversion tables A, B, C, D, E and F of the conversion tables; values expressed by n bits are "0" to "N"; each of n-bit source codes which respectively correspond to "0" to "N/2" is a first source code; each of n-bit source codes which respectively correspond to "{(N+1)/2}" to "N" is a second source code; the first source code is converted according to the conversion table A; an n-bit source code is converted according to the conversion table B when the n-bit source code has rightmost end bits including at least six "0" bits successively located; an n-bit source code is converted according to the conversion table F when a lead bit of the n-bit source code is "1"; an n-bit source code is converted according to the conversion table E when a lead bit of the n-bit source code is "1" and right most end bits of the n-bit source code include at least six "0" bits successively located; and the conversion codes are stored in the conversion tables A, B, C, D, E and F such that the conversion codes satisfy the following conditions: (i) rightmost end two bits of each of the conversion codes stored in the conversion table A are "00"; (ii) rightmost end four bits of each of the conversion codes stored in the conversion table B are "0010"; (iii) rightmost end four bits of each of the conversion codes stored in the conversion table C are "0001"; (iv) rightmost end six bits of each of the conversion codes stored in the conversion table D are "001001"; (v) rightmost end three bits of each of the conversion codes stored in the conversion table E are "001"; (vi) rightmost end two bits of each of the conversion codes stored in the conversion table F are "00"; (vii) at least two bits "0" are successively interposed between bit "1" and bit "1" throughout each of the conversion codes; (viii) the maximum number of bits "0" successively located in each of the conversion codes stored in the conversion table A is eleven; (ix) the maximum number of bits "0" successively located in each of the conversion codes stored in the conversion table B is eleven; (x) the maximum number of bits "0" successively located in each of the conversion codes stored in the conversion tables C, D and E is twelve; (xi) the maximum number of bits "0" successively located in the conversion codes stored in the conversion table F is nine; (xii) the conversion codes stored in the conversion table B are not stored in any of the conversion tables A, C, D, E and F; (xiii) the conversion codes stored in the conversion table C differ from the conversion codes stored in the conversion table B; (xiv) the number of bits "0" successively located in leftmost end bits of each of the conversion codes stored in the conversion table C is equal to the number of bits "0" successively located in leftmost end bits of each of the conversion codes stored in the conversion table B; (xv) when n-bit source codes are converted according to the conversion tables A and D, each of m-bit conversion codes obtained according to the conversion table A has left most end bits which are identical to leftmost end bits of a corresponding one of m-bit conversion codes obtained according to the conversion table D with respect to succession of bits "0"; (xvi) if rightmost end bits of an m-bit conversion code to be obtained when the first source code is converted according to the conversion table A are connected to leftmost end bits of an m-bit conversion code to be obtained when an n-bit source code subsequent to the second n-bit source code is converted according to one of the conversion tables A and B, and at least thirteen bits "0" are successively located in the connected right most end bits and leftmost end bits, the first code is converted according to the conversion table D; (xvii) if a lead bit of m-bit conversion code to be obtained when the n-bit source code subsequent to the second source code is converted according to one of the conversion tables A and B is "1", the second source code is converted according to the conversion table C; (xviii) when the second source code is converted according to the conversion table C, the n-bit source code subsequent to the second source code is converted according to the conversion table F; (xix) if leftmost end bits of an m-bit conversion code to be obtained when the n-bit source code subsequent to the second source code is converted according to the conversion table F are connected to rightmost end bits of an m-bit conversion code to be obtained when an n-bit source code subsequent to the second source code is converted according to one of the conversion tables A and B, and at least thirteen bits "0" are successively located in the connected leftmost end bits and rightmost end bits, the n-bit source code subsequent to the second source code is converted according to the conversion table E. Method according to claim 9, characterized in that in a case where the m-bit conversion code is input, when one of the conversion tables is identified which is used to obtain the input m-bit conversion code, as one of the conversion tables C and D, exclusive logical processing is performed on the input m-bit conversion code such that bits of the input m-bit conversion code are identical to bits of an m-bit conversion code to be obtained when an n-bit source code, which is to be converted into the input m-bit source code according to one of the conversion tables C and D, is converted according to one of the conversion table A and B, and when one of the conversion tables is identified which is used to obtain the input m-bit conversion code, as one of the conversion tables E and F, shift processing is performed on the input m-bit conversion code such that the bits of the input m-bit conversion code are identical to bits of an m-bit conversion code to be obtained when an n-bit source code, which is to be converted into the input m-bit conversion code according to one of the conversion tables E and F, is converted according to one of the conversion tables A and B.

Inventors: ISHIWAZA YOSHIYUKI, ISHIWAZA, YOSHIYUKI
Applicants: TOSHIBA KK, KABUSHIKI KAISHA TOSHIBA
Application year: 1996
Main classification: H03M5
IPC codes: G06T9, G11B20, H03M5, H04L25, G11B7, H03M7