PHASE-LOCKED LOOP

Abstract: A phase-locked loop (PLL) having very fast acquisition, and low output phase jitter and stability at steady-state is provided. In general, the phase-locked loop is used for synchronizing an output signal of said phase-locked loop with an input reference signal. In accordance with a general inventive concept, the filter circuit (4D) of the phase-locked loop includes a differentiator (5D) responsive to the phase difference representing signal from a phase detector (2D) in the PLL for providing a differentiated signal, and a filter (6D) responsive to both the phase difference representing signal and the differentiated signal to provide a filter output signal. Preferably, the filter (6D) is a low-pass filter. The output signal source (9) of the PLL is controlled by a control signal which is generally based on the filter output signal.

Description: Phase locked loop TECHNICAL FIELD OF THE INVENTION The present invention generally relates to phase-locked loop technology. BACKGROUND OF THE INVENTION The phase-locked loop (PLL) was introduced aε far back as 1932 by H. de Bellescizi, at that time for synchronous reception of radio signals. Today, the phase-locked loop is found in numerous applications of all modern technologies. It is widely used in all areas of electronics and in different fields of communication. A phase-locked loop is, in general, a circuit for synchronizing an output signal of the loop with an input reference signal in frequency as well as in phase. It basically consists of the following functional componentε: an output signal source, a phase detector responsive to the output signal and the reference signal for providing a phase difference representing signal, and a fil¬ ter circuit which filters the phase difference representing signal. In the synchronized state, also referred to as the locked state or steady state, the phase difference between the loop output signal and the input reference signal is zero, or at least very small, and no frequency offset between the signals exist. If a phase difference builds up, e.g. due to a frequency offset between the loop output signal and the reference signal, or if there is an instantaneous phase jump, a control mechanism in the PLL strives to eliminate the frequency offset and to reduce the phase difference to a minimum. The time required to enter the locked state is called the acquistion time. The performance evaluation of a PLL is based on acquisition and steady εtate properties. It is deεired to have fast acqusition and low output phase jitter at steady state. The utility of a phase-locked loop is substantially improved if the acquistion time is reduced, a fact well known in the art. The steady state mode should have high rejection of noise disturbances caused by e.g. the internal components of the PLL or environmental changes, which might alter the PLL output, in order to maintain lock of the PLL. It is the provision of a phase-locked loop having fast ac¬ quisition and stability at steady-state to which the present invention is directed. RELATED TECHNIQUE Many solutionε have been propoεed to accelerate the acquiεition of phase-locked loopε and to provide a εtable εteady state mode. In the following, techniques related to the subject matter of the present invention will be described. In U.S. patent 4,419,633 a variable voltage controlled oscillator (VCO) with an asεociated phaεe-locked loop iε disclosed. The voltage controlled oscillator arrangement compriseε a constant frequency reference signal source, a variable counter for normalizing the frequency of the VCO and a coincidence detector comparing the reference frequency to the normalized output frequency and providing an error signal. Further, the VCO- arrangement includes an integrator circuit for integrating the output of the coincidence detector to provide a control signal that adjusts the VCO to change frequency, a lock detector and a fast charge circuit, including two transistors and two bias resistors, for accelerating the charging process of the integra¬ tor circuit when the lock detector indicates an out-of-lock condition. U.S. patent 4,115,745 relates to a phase-lock speed-up circuit comprising a voltage controlled oscillator, a phase detector, a reference frequency source and a loop filter connecting the output of the phase detector and the input of the VCO. The loop filter includes an integrator connected in series with a low-pass filter, and stabilizing resistors. Furthermore, the speed-up circuit comprises means for adding direct current to the junction between the stabilizing resistors when the oscillator is out-of- lock. An interference resistant phase-locked loop is disclosed in U.S. patent 4,074,207. The phase-locked loop (PLL) has a voltage controlled oscillator (VCO) , a phase discriminator for receiving a reference signal and a feedback signal derived from the output signal of the VCO, and a low-pass filter for filtering of the phase difference representing output signal from the diεcrimina- tor. Moreover, the PLL includeε a εerieε connection of a differentiating circuit for the differentiation of the low-pass filter output signal, a limiter for limiting the output signal from the differentiating circuit, and an integrating circuit having an output which produces a control voltage for the VCO. The PLL is insensitive to large phase jumps due to the fact that the limiter is provided to take care of signal magnitudes at the output of the differentiating circuit exceeding the limiting level. U.S. patent 4,457,639 relates to a motor control for a DC-motor printer carriage including a phase-locked loop speed control circuit. The motor control has an encoder which detects motor speed, a reference oscillator, a phase comparator for detecting the phase difference between the encoder signal and the reference oscillator output signal, and a switching circuit for voltage to be applied to the motor based upon the phase comparator output. Additionally, the motor control includes a feedback circuit having a low-pass filter for converting the phase comparator output signal into an analog speed signal, and a differentiating circuit for converting the analog speed signal into a quasi- acceleration signal. The feedback circuit effects frequency modulation of the reference oscillator output signal to bring the encoder signal and the reference εignal in phaεe. SUMMARY OF THE INVENTION A general objective of the present invention is the provision of a phase-locked loop (PLL) having very fast acquisition, and low output phase jitter and stability at steady-state. In particular, when a PLL is in an out-of-lock condition (i.e. the loop output signal and the input reference signal are not synchronized) it is an object of the invention to reach the locked condition, also referred to as the steady state condition of the PLL, as fast as possible. Moreover, when the PLL is in steady state, the PLL should be able to maintain lock even though subjected to noise disturbances. In accordance with a general inventive concept, the filter circuit of the phase-locked loop includes a differentiator responεive to the phase difference representing εignal from a phaεe detector in the PLL for providing a differentiated εignal, and a filter responsive to both the phaεe difference representing signal and the differentiated signal to provide a filter output signal. Preferably, the filter is a low-pass filter. In general, the output signal source is controlled by a control signal which is generally based on the filter output εignal . The filter receives a signal representative of the phase difference between the loop output signal and the reference signal, and a signal representative of the rate of change of the phase difference. The inventive idea is to use the differentiator to speed up the "lock-in" of the filter. The phase difference representing signal contains information about the phase difference, and the differentiated signal contains information about the time- derivative of the phase difference, i.e. the frequency offset between the reference signal and the loop output signal. By using the information in both the phase difference representing signal and the differentiated signal in the regulation of the phase- locked loop a very fast lock-in is obtained. This is in contrast to prior art techniques which usually focuε entirely on the phaεe difference repreεenting εignal. Naturally, it iε deεired to give the filter the output εignal value which it will have at steady state as fast as possible. In accordance with the invention, the differentiator output is connected to the filter (also receiving the phase difference representing signal from the phase detector) and the differentiated signal representative of the frequency offset is pumped into the filter in order to quickly update the output signal of the filter. Thus, the differentiator is not uεed in the manner deεcribed in the aforementioned patentε. BRIEF DESCRIPTION OF THE DRAWINGS The novel featureε believed characteriεtic of the invention are εet forth in the appended claimε. The invention itεelf, however, as well as other features and advantages thereof will be best understood by reference to the detailed description of the specific embodiments which follows, when read in conjunction with the accompanying drawings, wherein: Figure 1 is a schematic block diagram of a phase-locked loop (PLL) according to the present invention,- Figure 2 is a schematic circuit diagram showing an analog filter circuit according to one embodiment of the invention in principle,- Figure 3 is a schematic block diagram of a phase-locked loop according to the present invention; Figure 4 iε a schematic block diagram of a phase-locked loop according to the preεent invention,- Figure 5 is a schematic block diagram of a phase-locked loop according to the present invention; Figure 6 is a schematic block diagram of a phaεe-locked loop according to the present invention,- Figure 7 showε a schematic conventional representation of a prior art digital low-pasε filter,- Figure 8 εhows a schematic block diagram of a digital filter circuit in accordance with the present invention in more detail; Figure 9 is a εchematic block diagram εhowing a digital filter circuit according to the invention,- Figure 10 iε a schematic block diagram of a phase-locked loop according to the present invention,- Fig. ila is a schematic diagram showing the DC-gain of the digital low-pass filter as a function of time,- Fig. lib iε a schematic diagram showing the cut-off frequency of the digital low-pass filter as a function of time,- Fig. lie is a εchematic diagram showing the amplification for the differentiated signal as a function of time; Figure 12 is a schematic block diagram of a phase-locked loop according to the present invention,- Figure 13 is a εchematic timing diagram illustrating a filter circuit parameter as a function of time when the gradual decrease of the parameter is temporarily interrupted; Figure 14 is a εchematic block diagram of a phase-locked loop according to the currently most preferred embodiment of the present invention. PREFERRED EMBODIMENTS OF THE INVENTION Fig. 1 iε a εchematic block diagram of a phaεe-locked loop (PLL) according to the preεent invention. It baεically conεiεtε of a phase detector 2, a filter circuit 4 and an output signal source, preferably a VCO 9. The phase detector 2 is responsive to an input reference signal and an output signal of the PLL for providing an error signal representative of the phase difference between the two signals. The filter circuit 4 iε reεponεive to the error εignal from the phaεe detector 2 to provide a control signal which is sent to the VCO 9. The VCO 9 provides an output signal in response to the control signal, the output εignal having a frequency that is determined by the control signal. Furthermore, the output signal of the VCO 9 constitutes the output signal of the phase-locked loop, but it is alεo fed back to the phase detector 2. The reference signal is provided to the phase detector 2 by general means 1 for generating a signal which can act as a reference signal. In general, it is asεumed that initially there is a frequency offset and a phase difference between the loop output signal and the reference signal. In accordance with a general inventive concept, the filter circuit 4 includes a di ferentiator 5 responsive to the error signal from the phase detector 2 to provide a differentiated signal, and a filter 6, preferably a low-pass filter, which iε responsive to the error signal from the phase detector 2 and the differentiated signal from the differentiator 5 to provide a (low-pass) filter output signal. It is important to understand that the filter circuit 4 should be conceived as an overall filter, which in turn includes the filter (in this case the low-pass filter 6) to be accelerated by the differentiator 5, which is alεo included in the filter circuit 4. The differentiated signal is representative of the rate of change of the error signal, i.e. the time- derivative or at least an approximation of the time-derivative of the error signal. In the PLL according to Fig. 1 the low-pass filter output signal is used to control the VCO 9, and hence acts as the control signal. In general, the output signal source, in thiε case the VCO 9, is controlled by a control εignal which is generally based on the low-pasε filter output εignal . A general objective of the present invention iε to reduce the acquiεition time of the phaεe-locked loop, i.e. to reduce the time required to εynchronize the output signal of the loop with the reference signal in frequency aε well aε in phase. If a phaεe difference buildε up, e.g. due to a difference in frequency between the output signal and the reference signal, perhaps in combination with a phase jump, the PLL acts to eliminate this frequency difference or offset, and to reduce the phase diffe¬ rence between the two signalε to a minimum. The idea according to the preεent invention iε to uεe a diffe¬ rentiator to εpeed up the "lock-in" of a filter, advantageouεly a low-paεε filter. It is assumed that a low-pass filter 6 iε desired in the steady state configuration of the PLL. Naturally, it is desired to give the low-pasε filter 6 the output εignal value which it will have at εteady-εtate aε fast as posεible. Aε pointed out above, the differentiating εignal is representative of a time derivative of the phaεe difference, and hence repreεen- tative of a time-dependent frequency offεet between the reference εignal and the loop output εignal. Since the low-pass filter 6, in steady state, has an output signal generally proportional to the frequency of the PLL, and the differentiated signal containε information about the frequency offset, a very fast lock-in is obtained by sending the output signal from the differentiator 5 into the low-pass filter 6. In contrast to prior art solutions, the focuε here is on both frequency locking and phase locking, εince information about the phaεe difference in the error signal and information about the frequency offset in the differentiated signal are used in the regulation of the phase-locked loop. As can be seen in Fig. 1, the low-pasε filter 6 receives both the error signal from the phase detector 2 and the differentiated signal from the differentiator 5. When the output signal of the phase-locked loop is synchronized with the reference signal, there iε generally no frequency offset between the two signals and the difference in phase is equal to zero, or at least very small. Consequently, the signal contribu¬ tion from the differentiator 5 is also zero or very small, and hence, if desired, the differentiator 5 can be switched out of the filter circuit 4 without causing any reconfiguration trans¬ ients. In general, the differentiator 5 is preferably used only during lock-in and not in steady state, unleεs it, for other reasons, iε deεired to use a differentiator 5 in the steady state configuration of the filter circuit 4. Fig. 2 iε a schematic circuit diagram showing an analog filter circuit according to one embodiment of the invention in prin¬ ciple. The analog filter circuit 4 basically consists of operational amplifiers and conventional RC-circuits. In one embodiment, the differentiation is realized by an RC-circuit with an operational amplifier as shown in Fig. 2. Since the low-pass filter 6 only has one input in the analog application, a summator 18 is used to add the differentiated signal and the error signal. The summator 18 generally inverts the signal, and therefore the differentiator 5 iε constructed such as to generate an inverted differentiated εignal. For the same reason, the error signal from the phase detector is also inverted by an inverter 17. In a practical implementation, other auxiliary devices, εuch aε temperature εtabilizerε, noiεe suppresεion unitε etc., are included in the filter circuit 4. Fig. 3 iε a εchematic block diagram εimilar to that of Fig. 1 showing a phase-locked loop according to the present invention. In addition to the differentiator 5 and the low-pass filter 6, the filter circuit 4' further comprises an amplifying block 7 which is responεive to the error εignal from the phaεe detector 2, and a summing block 8 responsive to the output εignal of the amplifying block 7 and the low-pass filter output signal. Preferably, the amplification of the amplifying block 7 iε proportional. The amplifying block 7 is connected in parallel with the low-pasε filter 6, and the summing block 8 receives the output signal of the amplifying block 7 and the output signal of the low-pass filter 6 to provide a control signal that is the sum of the two signals. This control signal controls the output signal source 9. In this case, the control signal is not entirely based on the low-pass filter output signal, although, in a preferred embodiment of the invention, the main contribution to the control signal comes from the low-paεε filter 6. In all other regardε the phaεe-locked loop of Fig. 3 iε identical to that of Fig. l. Thiε proportionally amplifying path iε provided for reaεonε of εtability. In εome cases, e.g. for PLL-systemε with very narrow bandwidth, it is preferable to have thiε filter configuration. Fig. 4 is a schematic block diagram similar to that of Fig. 1 showing a phase-locked loop according to the present invention. In this embodiment of the invention, the phaεe detector is a digital phase detector 2D (D for digital) for generating a digital error signal representative of a quantized phase difference between the reference signal and the loop output signal, and the filter circuit is a digital filter circuit 4D responεive to the digital error εignal for generating a digital control εignal. The digital filter circuit 4D compriεes a digital differentiator 5D reεponεive to the digital error εignal to provide a differentiated signal, and a digital low-pasε filter 6D which iε responsive to the digital error signal from the digital phase detector 2D and the differentiated signal from the differentiator 5D to provide a digital low-pass filter output signal which acts as the digital control signal. The digital differentiator 5D is preferably software based and executes in a microproceεεor (not εhown) . In a preferred embodiment of the invention, the differentiated signal is realized by subtracting the digital error signal value of the current sample with the digital error signal value of the preceding sample, and by dividing the reεult of thiε εubtraction with the εampling time. Conεequently, in this embodiment, the differentiated εignal is representative of a discrete-time approximation of the time derivative of the quantized phase difference. The preferred internal structure of the digital low-pass filter 6D will be described later with reference to Fig. 8 and 9. Furthermore there is provided a digital-to-analog converter (DAC) 3 which convertε the digital control signal into an analog control signal for con¬ trolling the output signal source, in this case the VCO 9. The digital phase detector 2D may be any suitable standard cir¬ cuit solution whatsoever known to the art, e.g. a counter-baεed digital phaεe detector. Preferably, the digital filter circuit 4D iε a software-based digital filter circuit executing in a microprocesεor (not shown) . However, a hardware implementation, possibly in combination with software-baεed components, is alεo poεεible. Of course, it is possible to use an analog filter circuit in this embodiment of the invention, instead of the digital one, and e.g. use another digital-to-analog converter for converting the digital error signal into an analog error signal which sub¬ sequently is sent to the analog filter circuit. Then the digital- to-analog converter 3 is omitted since the filter circuit output signal is analog. However, the preferred embodiment of the invention includes a digital filter circuit as deεcribed above. A digital phaεe detector which quantizeε (amplitude quantization) the phase difference between the reference signal and the loop output signal may give rise to quantization errors which will effect the performance of the phase-locked loop. A very small change in phaεe of one or both of the εignalε that are εent to the phaεe detector can lead to a εignificantly larger change in the phaεe difference repreεenting digital error εignal because of the quantizing properties of the digital phase detector. Hence, this larger change in phase difference for the digital error signal is not representative of the actual phase change, and this so-called quantization error may propagate through the system and effect the lock-in process and the steady εtate properties of the PLL. In order to minimize output phase jitter at steady state, and also during lock-in, caused by the pro- pagation of quantization errorε through the differentiator 5D, the signal contribution from the differentiator is gradually decreased to zero over a selectable period of time, all as will be described in more detail with reference to Fig. 5. Fig. 5 is a schematic block diagram similar to that of Fig. 4 illustrating a phase-locked loop in accordance with the in¬ vention. Preferably, the differentiated εignal from the diffe¬ rentiator 5D is amplified by the amplifier 11 so aε to further improve the acquisition properties of the PLL. Note, however, that, throughout the entire discloεure, amplificationε equal to or less than 1, but in general greater than zero, also are included in the expresεion "amplify". Furthermore, there is provided an amplification control 12 asεociated with the amplifier 11 εo aε to control the amplification thereof. Conveniently, the amplifier 11 and the amplification control 12 are εoftware-baεed and executed in a microproceεsor, preferably the same microprocessor that executes the digital filter circuit 4D. Primarily, the amplifier 11 and the amplification control 12 are used to amplify the differentiated signal so as to effec¬ tively reduce the acquiεtition time of the PLL even further. The actual amplification to be used varies from application to application, and depends on the specific componentε of the PLL and their respective settings. In addition, the amplifier and amplification control arrangement is utilized to handle quantiza¬ tion errors and configuration transients. A preferred way of gradually decreasing the signal contribution from the diffe¬ rentiator 5D in order to handle quantization distorεion is to use the amplification control 12 for gradually decreasing the amplification of the amplifier 11 from a first value, generally greater than 1, at the beginning of the lock-in procesε to zero, or at leaεt to a very small value, at a predetermined later time. In thiε way the effect of quantization distorsion iε minimzed, and the PLL has low output phase jitter at steady state. The reaεon for gradually decreaεing the εignal contribution from the differentiator 5D, instead of changing it abruptly, is to avoid configuration tranεientε. If configuration tranεients can be effectively handled by other meanε, then it iε of course possible to abruptly decrease the amplification, or in other wordε to εimply switch the differentiator out of the filter. In general, the differentiator is used to speed up the lock-in of the PLL, and consequently it is not used in steady state, unless required for other reasonε. Fig. 6 is a schematic block diagram similar to that of Fig. 4 showing a phase-locked loop according to the invention. In addition to the differentiator 5D and the digital low-pasε filter 6D, the digital filter circuit 4D' further includeε an amplifier 7D which iε responsive to the digital error signal from the digital phase detector 2D, and a summing element 8D which adds the output signal of the amplifier 7D and the output signal of the digital low-pass filter 6D to provide the digital control signal. The amplifier 7D iε connected in parallel with the digital low-pass filter 6D as can be seen in Fig. 6, and prefe¬ rably, the amplifier 7D is a proportional amplifier. In all other regards, the PLL of Fig. 6 is identical to that of Fig. 4. The amplifier 7D is provided in parallel with the digital low-pasε filter/differentiator arrangement for εtability reasonε. In one embodiment of the present invention, amplifications greater than 1 are used for the amplifier 7D. However, εince quantization errorε originating from the digital phaεe detector 2D alεo are amplified by the amplifier 7D, it iε neceεεary to make a trade¬ off between stability and low output phase jitter by uεing relatively low amplification valueε for the amplifier 7D. Moreover, the εame arrangement 11, 12 for amplifying the differentiated εignal/gradually decreaεing the εignal con¬ tribution from the differentiator aε that of Fig. 5 is used in this embodiment of the invention although it is not illuεtrated in Fig. 6. With reference to Fig. 7 there iε shown a schematic conventional repreεentation of a prior art digital low-pass filter. A digital low-pass filter is generally responsive to an input signal IN for generating an output signal OUT. A conventional digital low-pass filter basically consiεtε of the following functional blockε: an amplifier 21 (with amplification a) reεponεive to the input εignal IN for providing a first amplified signal, a summing block 22 responεive to the firεt amplified εignal and an amplified delayed internal feedback signal of εaid digital low-paεε filter for adding the two εignalε to provide the output εignal OUT of εaid digital low-paεε filter, alεo acting as an internal feedback signal, a delay unit 23 for delaying the internal feedback signal, and a εecond amplifier 24 (with amplification b) reεponεive to the delayed internal feedback εignal for amplifying the delayed internal feedback εignal to provide the amplified delayed internal feedback signal to the summing block 22. At this point it is convenient to introduce some formulas for the digital low-pasε filter. Firεt of all, the amplification b muεt lie in the interval 0 < b < 1. By conεidering a normalized low- paεε filter and making approximationε uεing Taylor εerieε and/or εimple mathematical assumptions it is possible to identify the DC-gain, K lp , and the 3 dB cut-off frequency, ω c , of the digital low-pasε filter aε: ** - T÷B (1) and ωc = _Z_ < 2) , c T s 1 + b where T s iε the εampling time, a and b are the respective amplifications mentioned above. The latter of the approximative expressions above is valid when T α -ω c is small and b is almost 1. With reference now to Fig. 8 there is shown a schematic block diagram of a digital filter circuit in accordance with the present invention in more detail. The filter circuit basically includes a differentiator 5D and a digital low-pass filter 6D. The differentiator 5D is responsive to a signal IN, which is the digital error signal from the digital phaεe detector 2D (not shown in this figure) and produces a differentiated signal. The digital low-pass filter 6D is responsive to both the signal IN, i.e. the digital error signal, and the differentiated signal. The digital low-pass filter 6D according to the invention is identical to that of Fig. 7, except for the summing block 27 which differs from the summing block 22. The summing block 27 is responsive to the differentiated signal from the differentiator 5D, the first amplified signal from the amplifier 21 and the amplified delayed internal feedback signal from the second amplifier 24. Hence, the summing block 27 receives these three signals, and adds them together to produce the output signal of the digital low-paεs filter 6D. In this way, the differentiated signal is pumped into the digital low-pass filter 6D. The differentiated signal which containε information about the frequency offεet between the reference εignal and the output signal of the PLL directly effectε the output εignal of the digital low-paεε filter 6D, said digital low-paεε filter output signal constituting the basis of the digital control signal which, after digital-to-analog conversion, controls the frequency of the output signal of the VCO 9 (not shown in this figure) . Preferably, the amplifier 11 and the amplification control 12 of Fig. 5 are included in this embodiment of the invention, although they are not illustrated in Fig. 8. Of course, there are other ways of applying the differentiated signal to the digital low- paεs filter 6D such that the differentiated εignal contributes to the output εignal of the digital low-paεε filter 6D. By appropriately setting the amplification of the amplifier 11 and the amplifier 21, the focus of the regulation of the PLL can be turned more to either frequency locking or phase locking. If, e.g. it is deεired to focus mostly on frequency locking at the very beginning of the lock-in, then the amplification of the amplifier 11 is set to a relatively large value at this period of time, whereas the amplification of the amplifier 21 is set to a relatively low value. If on the other hand, it is desired to focuε more on phaεe locking, then it iε either poεεible to increase the amplification of the amplifier 21, or to decrease the amplification of the amplifier 11, or a combination thereof. It has turned out to be advantageous to focus mostly on the frequency locking at the very beginning of the lock-in. In this way, the frequency offset is eliminated almost instantly. Then the focus is turned to phase locking, and the phase difference is reduced to a minimum. Therefore, the amplification of the amplifier 11 is decreased to zero in a rather short period of time, only a few εamples in the microprocesεor implementation. A εtrong frequency lock generally contradictε the ability to obtain phase lock, since the PLL-system must be able to change its frequency to get a phase lock. This iε the reaεon for shifting the focus of the PLL-regulation from frequency locking to phase locking in the manner described. It is important to understand that this amplification εetting is poεεible to combine with the gradual decrease of the amplification of the amplifier 11 described above. Fig. 9 is a schematic block diagram similar to that of Fig. 8 showing a digital filter circuit according to the invention, which basically comprises a differentiator 5D and a digital low¬ pass filter 6D. In addition to the components deεcribed in connection with Fig. 8, the digital low-paεε filter 6D further includeε a limiter 28 for limiting the output εignal of the digital low-paεε filter 6D, aε well aε the internal feedback εignal of the digital low-paεε filter 6D. If the digital low-paεε filter 6D iε εoftware baεed and executes in a microprocessor, it is technically posεible to have a digital low-pass filter output variable which corresponds to a voltage far beyond the operating range of the digital-to-analog converter 3 (not shown in thiε figure) . If this is the case, then the DAC 3 will be saturated in either direction. If e.g. the output signal from the digital low-pass filter correspondε to a voltage of 2,6 V, and the operating range of the DAC 3 extendε from -2 V to +2 V, the DAC 3 can only make uεe of 2 of the 2,6 V. Accordingly, inεtead of letting the relatively εlow dynamic behaviour of the digital low- pasε filter finally reduce the signal value of the output signal, as well aε the εignal value of the internal feedback εignal, theεe εignals are limited by the limiter 28 to both lie within the predetermined range; the operating range of the DAC 3 or a portion thereof. This limiting action is generally effectuated instantly. It is important that the limiter 28 is provided in the digital low-pasε filter 6D such that the internal feedback signal also is limited by the limiter 28. Otherwise, a εignal value that iε too large will continue to live in the digital low-pass filter 6D because of the internal feedback signal. The above described way of limiting the output signal as well as the internal feedback signal of a digital filter can be applied to any suitable digital filter known to the art, with or without having a differentiator connected to the filter. Fig. 10 is a schematic block diagram similar to that of Fig. 4 showing a phase-locked loop in accordance with the invention. The phase-locked loop basically consists of a digital phase detector 2D, a digital filter circuit 44, a digital-to-analog converter 3, and an output signal source, preferably a VCO 9. There is also general means l for providing a reference signal. Said general meanε 1 iε, aε an example, a telecommunication switch which generates a clock εignal that acts as a reference signal for the PLL. The digital filter circuit 44 is any one of the digital filter circuitε 4D and 4D' . Furthermore, the PLL includeε a filter control (filter circuit control) 13 for controlling the digital filter circuit 44. In all other regardε, the PLL of Fig. 10 iε identical to that of Fig. 4. Preferably, the digital filter circuit 44 and the filter control 13 are both software based, executing in a microprocessor μP. Alternatively, they are realized by a combined hardware and software implementation. The filter control 13 controls the characteristicε of the digital filter circuit 44. It has turned out that by having a relatively large value for the DC-gain of the digital low-pasε filter 6D at the beginning of the lock-in, the acquisition time iε further reduced. In one embodiment of the invention, the DC-gain at the beginning of the lock-in iε up to 25 times greater than the final DC-gain at some predetermined time later. In accordance with one embodiment of the invention, the DC-gain of the low-pasε filter 6D in the digital filter circuit 44 iε gradually decreaεed from a relatively large value at the beginning of the lock-in proceεε of the PLL to the final value which the digital low-pass filter 6D should have in steady state over a selectable period of time. Advantageously, the gradual decrease of the DC-gain is realized by the filter control 13. Note, that the procesε of gradually decreaεing the DC-gain can be applied to any εtandard digital filter circuit including a filter, e.g. a low-pass filter, with or without a differentiator connected to the filter, and the acquisition time of the PLL will still be reduced in comparison to prior art εolutionε. However, a preferred embodiment of the invention utilizeε the differentiator 5D to εpeed up the digital low-paεε filter 6D in combination with a gradual decreaεe of the DC-gain of the digital low-paεε filter 6D from a rather large value to a predetermined εmaller value. In thiε way, a very faεt acquiεition iε obtained. Some improvement in the characteriεticε of a PLL haε been obtai¬ ned in the prior art, see e.g. US 5,315,623, by providing a loop filter with selectable time constant, by using switched resiεtan¬ ce in the filter. More εpecifically, according to prior art teachingε, the time constant is reduced (i.e. the loop filter bandwidth is increased) during lock-in and the time constant iε increased (i.e. the loop filter bandwidth is reduced) at steady state. In accordance with one embodiment of the invention, the diffe¬ rentiator 5D is used to speed up the lock-in of the digital low- paεε filter 6D in combination with a gradual decrease of the cut¬ off frequency of the digital low-paεs filter 6D in the digital filter circuit 44 from a relatively large value at the beginning of the lock-in to a predetermined εmaller value over a εelectable period of time. The gradual decrease of the cut-off frequency of the digital low-pasε filter 6D is effectuated by the filter control 13. Preferably, the cut-off frequency of the digital low- pasε filter 6D haε a very low value at steady state so as to minimize phase jitter. In addition, the cut-off frequency in a digital modell should be rather low at steady εtate for stability reasons. The acquisition time for a PLL which utilizes both the differentiator/low-pass filter arrangement of the invention and the gradual decreaεe of the cut-off frequency of the low-paεε filter iε generally only about 50% (when the initial frequency offset is very large, the acquisition time is reduced up to 25 times) of the acquisition time for a PLL which utilizes the gradual decrease of the cut-off frequency, but not the differen¬ tiator. It is important to understand that the decrease of the cut-off frequency is preferably effectuated gradually over a period of time in order to avoid configuration transients. The part of the filter control 13 that controls the gradual decrease of the DC-gain is referred to as 13a (Fig. 10) , and the part of the filter control 13 that controls the gradual decrease of the cut-off frequency is referred to as 13b (Fig. 10) . Consider the expressions (1) and (2) for the DC-gain of the digital low-pass filter and the cut-off frequency of the digital low-pass filter, respectively. By suitably changing the ampli¬ fications a and b, it is possible to alter the DC-gain and the cut-off frequency as desired, i.e. to gradually decrease the DC- gain and the cut-off frequency from a reεpective relatively high level at beginning of the lock-in to a reεpective lower level over selectable periods of time. Fig. lla-c are schematic diagrams illustrating how the filter circuit parameters, in one embodiment of the invention, change in time. In Fig. ila the DC- gain (K lp ) of the digital low-pass filter as a function of time (t) is shown. Fig. lib εhowε the cut-off frequency (ω c ) of the digital low-paεε filter aε a function of time (t) , and Fig. lie εhowε the amplification (A diff ) for the differentiated εignal as a function of time (t) . From these diagrams it can be seen that the respective filter circuit parameters are gradually decreased from relatively large values to smaller values over respective periods of time. Note that the respective initial values and the respective final values of the filter circuit parameters, aε well aε the reεpective time periods, are εelectable and εet to appropriate valueε aε deεired depending upon the particular application. It haε turned out to be effective to gradually decrease the amplification for the differentiated signal to zero in a relatively short period of time. In general, the amplifica¬ tion reaches a zero value at a time t. long before the PLL enters steady state. At the very beginning of the lock-in the focus of the regulation is preferably on frequency locking, and some time before the time t-, depending on the actual amplifications used, and thereinafter, the focus will be on phase locking. The frequency offset between the reference signal and the loop output signal is generally eliminated almost instantly by the effect of the differentiated signal on the output signal of the digital low-pasε filter 6D, although the respective values of the DC-gain and the cut-off frequency have not been decreased to their final values. The DC-gain and the cut-off frequency are controlled by the filter control 13, and in the particular application shown in Fig. lla-b they are decreased to their final values at a time t 2 . Aε can be εeen by using the broken line in Fig. lla-c as a guidance, the time t 2 generally occurε later than time t-. Experimentε have shown that the phase difference between the two signals reaches a level very close to a minmum long before the DC-gain and the cut-off frequency have reached their respective final values, but generally after the time t.. The respective final values for the cut-off frequency and the DC-gain are selected so aε to provide εtability and low output phaεe jitter at εteady εtate, but alεo so that remaining static phaεe errorε are reduced to a deεired level. Note, that if the cut-off frequency of the digital low-paεε filter is very close to zero, then the low-pass filter will act as an "ideal" integrator. In one embodiment of the invention, both the DC-gain and the cut-off frequency of the digital low-pasε filter are decreaεed, in combination with the differentiator/low-pass filter arrangement. Fig. 12 is a schematic block diagram similar to that of Fig. 10 showing a phase-locked loop in accordance with the invention. The phase-locked loop illustrated in Fig. 12 iε identical to that of Fig. 10 except for a feedback from the output of the digital filter circuit 44 to the filter control 13. If the output signal from the digital filter circuit 44 corresponds to a voltage that is beyond the operating range or control range of the DAC 3 and/or the VCO 9, then the DAC 3 and/or the VCO 9 will be saturated in either direction. Thiε may repreεent two different cases: first, a caεe in which the PLL iε unable to εynchronize with the reference signal; second, a case in which the frequency of the PLL output εignal iε far away from the target or reference frequency, but in which it is still posεible to regulate the PLL in direction towardε the reference frequency. In the latter caεe, it iε important not to decreaεe the parameterε of the digital filter circuit 44 aε long aε εaturation remainε. Otherwiεe, the parameterε will be decreaεed to low valueε before the "real" lock-in of the PLL has started, and the effect of having large values on these filter parameters at the beginning of the actual lock-in to speed up the acquiεition will be loε . If the VCO is tuned to its limits, the PLL-system is prohibited to drive the phase and frequency aε much aε it would do in the linear range. The large filter parameter valueε are needed when the PLL-εyεtem re-enters the non-saturated range. Accordingly, a feedback is provided for supplying the output signal of the digital filter circuit 44 to the filter control 13. The filter control 13 receives the output signal from the digital filter circuit 44 and checks whether or not the voltage corresponding to the output εignal from the digital filter circuit 44 lieε within a predeter¬ mined portion of the control voltage range of the DAC 3 and/or the VCO 9. If the output εignal of the filter circuit 44 lies outside the predetermined range, then the gradual decrease of at least one of the parameters of the digital filter circuit 44 is temporarily interrupted, and the respective parameter value(s) is/are held constant. In other words, at leaεt one of the processes of gradually decreasing is interrupted when the DAC 3 and/or the VCO 9 are/is saturated. As soon as the filter circuit output signal lies within the predetermined range, the gradual decrease of the respective filter parameter(ε) iε reεumed or continued. By filter circuit parameter is meant any one of the following parameterε: the DC-gain of the low-paεε filter 6D, the cut-off frequency of the low-paεε filter 6D, and the differentia¬ tor amplification (in thiε embodiment, the amplification control 12 iε integrated into the filter control 13) . Fig. 13 iε a εchematic timing diagram illuεtrating a filter circuit parameter, εuch as K lp , ω c or A diff , as a function of time when the gradual decrease of the parameter is temporarily interrupted. Note that, in general, A diff is decreaεed to zero. In one embodiment, the digital filter circuit 44 and the filter control 13 are εoftware implemented, and the whole procedure executeε in a microproceε- εor. Preferably, the digital filter circuit 44 iε any one of the filter circuits 4D and 4D' . The part of the filter control 13 that controlε the interruption and continuation of the gradual decreaεe of filter parameterε iε referred to aε 13c. In an alternative embodiment, a εimilar control procedure can be carried out by checking the output signal, after suitable signal converεion, from the DAC 3. Naturally, the above described interruption and continuation of the gradual decrease of filter parameters can be applied to any suitable digital filter circuit known to the art, with or without a differentiator connected to the filter. In one particular embodiment, the gradual decreaεe of the cut-off frequency of a filter in a phaεe-locked loop which doeε not have a differentiator arrangement iε controlled in the manner deεcribed above. Experimentε have εhown that an effective acquisition is obtained also in this embodiment. Mainly depending on the expected behaviour of the reference signal, the beεt performance of the PLL according to the invention is obtained by using any one of the filter circuits described above together with different combinations of the following means, all of which have been described in detail above: - means for gradually decreasing the signal contribution from the differentiator; - means for gradually decreasing the DC-gain of the filter from a relatively large value at the beginning of the lock-in to a smaller value; - meanε for gradually decreaεing the cut-off frequency of the filter from a relatively large value at the beginning of the lock-in to a smaller value; - means for controlling the gradual decrease of at least one of the following: - the signal contribution from the differentiator, - the DC-gain of the filter, and - the cut-off frequency of the filter,- and - means for limiting the output signal as well as an internal feedback signal of the filter. The currently most preferred embodiment (best mode) of the invention will now be described with reference to Fig. 14. Fig. 14 is a schematic block diagram of a phase-locked loop in accordance with the currently most preferred embodiment of the preεent invention when applied to clock regeneration in a telecommunication switch. Basically, there are general means l, for generating a reference signal, a digital phase detector 2D, a digital filter circuit 4D' , a digital-to-analog converter DAC 3, a VCO 9, a filter control 13, a feedback circuit from the output of the VCO 9 to an input of the digital phase detector 2D, and a further feedback from the output of the digital filter circuit 4D' to the filter control 13. In many applicationε, the reference and loop output signals are square wave clock signalε. The digital phaεe detector 2D receiveε the reference signal and the loop output signal, i.e. the feedback signal from the VCO 9, to produce a digital error signal representative of a quantized phase difference between the two εignalε. Generally, it is assumed that initially there is a frequency offset and a phase difference between the two signals. The digital filter circuit 4D' receives the digital error εignal to produce a digital control εignal, which in turn iε converted by the DAC 3 into an analog control signal. The analog control εignal from the DAC 3 is sent to the VCO 9 for controlling the frequency of the output signal therefrom. The digital filter circuit 4D' includes the differentiator 5D, the amplifier 11, the digital low-pasε filter 6D, the proportionally amplifying block 7D and the εumming block 8D. The differentiator 5D receiveε the digital error εignal from the digital phaεe detector 2D to produce a differentiated εignal which in turn is amplified by the amplifier 11. The amplified differentiated signal is sent into the digital low-pasε filter 6D, which also receives the digital error εignal. The internal structure of the digital low-pasε filter iε beεt appreciated by reading the description referring to Fig. 9. However, note that there is provided a limiter which limitε the output εignal and the internal feedback εignal of the digital low-paεε filter 6D. The digital error εignal iε alεo εent to the proportionally amplifying block 7D which produceε a proportionally amplified εignal. The output signal of the digital low-pasε filter 6D is added together with the proportionally amplified signal in the εumming block 8D to provide the digital control εignal. The amplification of the amplifying block 7D iε relatively low compared with the DC-gain of the digital low-pasε filter 6D. The filter control 13 controlε the characteriεticε of the digital filter circuit 4D' . Preferably, the amplification control 12 iε integrated into the filter control 13. Thuε, the filter control 13 iε used to gradually decrease the amplification of the amplifier 11 from a predetermined value to zero over a first period of time, a few samples, so aε to achieve an effective acquiεition, and to handle quantization diεtorεion. Furthermore, the DC-gain and the cut-off frequency of the digital low-paεs filter 6D are also gradually decreased over a second and third period of time, respectively. The DC-gain at the beginning of the lock-in proceεε iε preferably 10-30 times larger than the final value, in thiε particular embodiment of the invention. The cut¬ off frequency at the beginning of lock-in is preferably 10-100 timeε larger than the final value. The steady εtate value of the cut-off frequency εhould be rather low for reaεons of stability. Preferably, the first period of time iε much shorter than the second and third periods of time. The DAC 3 receives the digital control signal and produces an analog control signal, which is sent to the VCO 9. The digital control signal from the filter circuit 4D' is also sent to the filter control 13, which interrupts the gradual decrease of at least one of the filter circuit parameters mentioned above when the digital control εignal lies outside a predetermined range, and continues or resumes the gradual decrease when the digital control signal lies within the predetermined range. In the beεt mode of carrying out the invention, the gradual decrease of all three filter parame¬ ters is controlled by the filter control 13. The digital filter circuit 4D' and the filter control 13 incorporating the amplifi¬ cation control 12 are software based and executes in a micropro- cessor. The interruption and continuation of the gradual decrease of filter parameters, and the limiter in the digital low-pasε filter haε turned out to be particularly effective when there are large frequency offsets between the reference signal and the loop output signal, although the differentiator gives the main contribution to a fast acquisition. In general, the differentia- tor/low-pasε filter arrangement is very effective when en¬ countering large frequency offsets. Moreover, the gradual decrease of the DC-gain from a rather high value in the beginning of the lock-in to a suitable and lower value at some time later and at εteady state will further reduce the lock-in time. However, the DC-gain of the low-pasε filter εhould not be too high, since although frequency locking is fast, the phase locking may turn oεcillative. The DC-gain aε well aε other settings of the PLL must be adapted to the expected magnitude of the frequency offsets and/or phase jumps. The embodimentε described above are merely given as examples, and it should be understood that the present invention is not limited thereto. It is of course posεible to embody the invention in specific forms other than those described without departing from the spirit of the invention. By way of example, the filter to be accelerated by the differentiator can be any one of a number of suitable filters known to the art (note that an ideal integrator is considered aε a special case of a low-pass filter, since the cut-off frequency of the latter can be infinitesimally close to zero) . Further modifications and improvements which retain the basic underlying principles discloεed and claimed herein are within the scope and spirit of the invention.

Claims: CLAIMS 1. Phaεe-locked loop (PLL) arrangement for εynchronizing an output εignal of εaid phaεe-locked loop with an input reference εignal, compriεing: an output εignal source (9) for providing said output signal in responεe to a control εignal, said output εignal having a frequency that iε dependent upon said control signal; phase detector means (2D) responsive to said input reference signal and εaid output signal for providing an error εignal repreεentative of the difference in phaεe between εaid input reference εignal and εaid output signal; first feedback means connected from the output of the output signal εource (9) to an input of εaid phaεe detector meanε (2D) for applying εaid output εignal to εaid phaεe detector means (2D) ; digital filter means (6D) responsive to said error signal for providing a digital control signal; and a digital-to-analog converter (3) responsive to said digital control signal for converting said digital control signal into said control signal, c h a r a c t e r i z e d in that it further compriseε diffe¬ rentiating means (5D) responsive to said error signal for providing a differentiated signal representative of a discrete- time approximation of the time-derivative of said error signal, and in that said digital filter means (6D) is responsive to both said error signal and said differentiated signal to provide said digital control εignal. 2. Phaεe-locked loop arrangement in accordance with claim l, c h a r a c t e r i z e d in that it further compriεeε first means for gradually decreasing the εignal contribution from said differentiating means from a first value to a second value over a firεt period of time. 3. Phaεe-locked loop arrangement in accordance with claim l, c h a r a c t e r i z e d in that it further comprises: firεt amplifying meanε (11) for amplifying εaid differentia¬ ted εignal, said digital filter means (6D) being responsive to both said error signal and said amplified differentiated εignal, and second means (12) for gradually decreasing the amplification of said first amplifying means (11) from a third value to a fourth value over a second period of time 4. Phase-locked loop arrangement in accordance with any of the precedmg claims, further comprising- εecond amplifying meanε (7D) reεponsive to εaid error εignal for providing a εecond amplified εignal, and first summing means (8D) responεive to εaid εecond amplified εignal and the output εignal of εaid digital filter meanε (6D) to provide εaid digital control εignal 5 Phase-locked loop arrangement in accordance with any of the preceding claims, c h a r a c t e r i z e d in that it further compriseε third meanε (13a) for gradually decreaεing the DC-gain of said digital filter means (6D) from a fifth value to a εixth value over a third period of time. 6. Phaεe-locked loop arrangement in accordance with any of the preceding claims, wherein said phase-locked loop arrangement further compriεeε fourth meanε (13b) for gradually decreasing the cut-off frequency of said digital filter means (6D) from a seventh value to an eight value over a fourth period of time 7 Phase-locked loop arrangement m accordance with any of claims 2, 3, 5 and 6, c h a r a c t e r i z e d in that said first, third, fifth and seventh value are subεtantially greater than εaid εecond, fourth, εixth and eight value respectively. 8 Phase-locked loop arrangement in accordance with any of claims 2, 3, 5, 6 and 7, c h a r a c t e r i z e d in that said first period of time and εaid εecond period of time are shorter than said third period of time and said fourth period of time. 9. Phase-locked loop arrangement in accordance with any of claims 2, 3, 5, 6, 7 and 8, c h a r a c t e r i z e d in that it further comprises control means (13c) for controlling at least one of said first, second (12) , third (13a) and fourth (13b) means for gradually decreasing so that the gradual decreaεe iε temporarily interrupted when said digital control signal lies outside a firεt predetermined range, and εo that the gradual decreaεe iε reεumed when said digital control εignal lieε within εaid firεt predetermined range, and second feedback meanε for providing said digital control signal to said control means (13c) . 10. Phase-locked loop arrangement in accordance with any of the preceding claimε, wherein said digital filter means (6D) includes: third amplifying means (21) responεive to εaid error εignal for providing a third amplified signal; second summing means responsive to said third amplified εignal and an amplified delayed internal feedback εignal of said digital filter means (6D) to provide the output signal of said digital filter means (6D) , also acting aε an internal feedback signal; delay means (23) for delaying said internal feedback signal,* third feedback means for providing said internal feedback signal to said delay meanε (23) ,- and fourth amplifying meanε (24) reεponεive to εaid delayed in¬ ternal feedback εignal for providing εaid amplified delayed internal feedback εignal to εaid εecond summing meanε, c h a r a c t e r i z e d in that εaid εecond εumming means (27) alεo iε reεponεive to εaid differentiated εignal or said amplified differentiated signal for adding said differentiated signal or said amplified differentiated εignal, said third amplified signal and said amplified delayed internal feedback εignal to provide the output εignal of said digital filter means (6D) . 11. Phase-locked loop arrangement in accordance with any of the preceding claims, c h a r a c t e r i z e d in that said digital filter means (6D) further comprises means (28) for limiting the output signal of said digital filter means (6D) as well as the internal feedback signal of said digital filter means (6D) to both lie within a εecond predetermined range. 12. Phaεe-locked loop (PLL) arrangement for synchronizing an output signal of said phaεe-locked loop with an input reference εignal, compriεing: an output εignal εource (9) for providing εaid output εignal in reεponεe to a control signal, said output signal having a frequency that is dependent upon εaid control signal,- phase detector meanε (2D) reεponεive to εaid input reference εignal and εaid output εignal for providing an error εignal repreεentative of the difference in phaεe between εaid input reference signal and εaid output signal; first feedback means connected from the output of the output signal source (9) to an input of said phase detector means (2D) for applying said output signal to said phase detector means (2D) ,- digital filter means (6D) responεive to εaid error εignal for providing a digital control εignal,- and a digital-to-analog converter (3) reεponsive to said digital control εignal for converting said digital control signal into said control signal, c h a r a c t e r i z e d in that it further comprises means (13a) for gradually decreasing the DC-gain of said digital ilter means (6D) from a fifth value to a sixth value over a third period of time. 13. Phase-locked loop (PLL) arrangement for synchronizing an output signal of said phase-locked loop with an input reference signal, compriεing: an output signal source (9) for providing said output signal in response to a control signal, said output signal having a frequency that is dependent upon said control signal; phase detector means (2D) responsive to said input reference signal and said output signal for providing an error signal representative of the difference in phase between said input reference signal and said output signal; firεt feedback meanε connected from the output of the output εignal εource (9) to an input of εaid phaεe detector meanε (2D) for applying εaid output εignal to εaid phaεe detector meanε (2D) ,- digital filter means (6D) responsive to said error signal for providing a digital control signal; means (13b) for gradually decreasing the cut-off frequency of εaid digital filter meanε (6D) from a seventh value to an eight value over a fourth period of time,- and a digital-to-analog converter (3) responsive to said digital control signal for converting said digital control signal into said control signal, c h a r a c t e r i z e d in that it further compriseε control meanε (13c) for controlling εaid meanε (13b) for gradually decreasing the cut-off frequency so that the gradual decrease is temporarily interrupted when said digital control signal lies outside a first predetermined range, and so that the gradual decrease is resumed when said digital control signal lieε within said firεt predetermined range, and second feedback meanε for providing εaid digital control εignal to said control means (13c) . 14. Phase-locked loop (PLL) arrangement for synchronizing an output signal of said phase-locked loop with an input reference signal, comprising: an output εignal εource (9) for providing εaid output εignal in reεponse to a control signal, said output signal having a frequency that is dependent upon εaid control signal; phase detector means (2D) responsive to εaid input reference εignal and said output εignal for applying an error εignal representative of the difference in phase between said input reference signal and said output signal; first feedback means connected from the output of the output signal source (9) to an input of said phase detector means (2D) for providing said output signal to said phase detector meanε (2D) ; digital filter meanε (6D) reεponεive to εaid error εignal for providing a digital control εignal ,- and a digital-to-analog converter (3) responsive to εaid digital control εignal for converting εaid digital control signal into said control signal, c h a r a c t e r i z e d in that said digital filter means (6D) further compriseε meanε (28) for limiting the output signal of said digital filter meanε (6D) , as well aε an internal feedback signal of said digital filter means (6D) to both lie within a second predetermined range. 15. Phase-locked loop (PLL) arrangement for synchronizing an output signal of εaid phase-locked loop with an input reference signal, comprising: an output signal source (9) for providing εaid output εignal in reεponεe to a control εignal, said output signal having a frequency that is dependent upon said control signal; phase detector means (2) reεponsive to said input reference signal and said output εignal for providing an error εignal repreεentative of the difference in phase between εaid input reference signal and said output signal,- first feedback means connected from the output of the output signal source (9) to an input of εaid phaεe detector means (2) for applying εaid output εignal to said phase detector means (2) ,- and filter means (6) responεive to εaid error signal for provid¬ ing said control signal, c h a r a c t e r i z e d in that it further compriεes diffe¬ rentiating means (5) responsive to said error signal for providing a differentiated signal representative of the rate of change of said error signal, and that εaid filter means (6) iε reεponεive to both said error signal and said differentiated signal. 16. Phase-locked loop arrangement in accordance with claim 15, further compriεing: amplifying meanε (7) reεponεive to said error signal for providing an amplified εignal, and firεt εumming meanε (8) reεponεive to said amplified signal and the output signal of said filter means (6) to provide said control signal. 17. Method for synchronizing an output εignal of a phaεe-locked loop (PLL) arrangement with an input reference εignal compriεing the εtepε of: detecting the phaεe difference between εaid output εignal and εaid reference εignal to provide an error signal representa¬ tive of said phase difference; filtering said error signal in filter means (6) to provide a control signal; and controlling the output signal in response to said control signal, c h a r a c t e r i z e d in that it further comprises the steps Of: differentiating said error signal to provide a differentia¬ ted signal; and sending said differentiated signal into εaid filter means (6) to contribute to εaid control εignal. 18. Method for εynchronizing an output εignal of a phaεe-locked loop (PLL) arrangement with an input reference signal comprising the steps of: detecting the phase difference between εaid output signal and said reference signal to provide an error signal representa¬ tive of said phase difference; filtering said error signal in digital filter means (6D) to provide a digital control signal; converting said digital control signal into a control εignal; and controlling the output εignal in response to said control signal, c h a r a c t e r i z e d in that it further compriseε the steps Of: differentiating εaid error εignal to provide a differentia¬ ted signal; and sending said differentiated signal into said digital filter means (6D) to contribute to said digital control signal. 19. Method in accordance with claim 18, c h a r a c t e r i z e d in that it further compriεeε at leaεt one of the following stepε: gradually decreaεing the contribution of εaid differentiated εignal to εaid digital control εignal from a firεt level to a second level over a first period of time,- gradually decreasing the DC-gain of εaid digital filter meanε (6D) from a fifth level to a εixth level over a third period of time,- and limiting the output εignal of εaid digital filter means (6D) as well as an internal feedback εignal of said digital filter means (6D) to both lie within a second predetermined range. 20. Method in accordance with claim 19, c h a r a c t e r i z e d in that it further compriεeε the steps Of: interrupting at least one of said stepε of gradually decrea¬ εing when εaid digital control εignal lies outside a first prede¬ termined range,* and reεuming the reεpective one(ε) of εaid at leaεt one of said εtepε of gradually decreasing when said digital control signal lies within εaid firεt predetermined range. 21. Method for synchronizing an output signal of a phase-locked loop (PLL) arrangement with an input reference signal comprising the stepε of: detecting the phaεe difference between εaid output εignal and said reference signal to provide an error εignal representa- tive of εaid phaεe difference; filtering said error signal in digital filter means (6D) to provide a digital control signal; converting said digital control signal into a control signal; and controlling the output signal in responεe to εaid control εignal, c h a r a c t e r i z e d in that it further compriεeε the εtep of gradually decreaεing the DC-gain of εaid digital filter means (6D) from a fifth level to a sixth level over a third period of time. 22. Method in accordance with claim 21, c h a r a c t e r i z e d in that it further comprises the εtepε Of: interrupting εaid εtep of gradually decreaεing the DC-gain when εaid digital control signal lies outside a first prede¬ termined range,- and reεuming said step of gradually decreasing the DC-gain when εaid digital control εignal lieε within εaid firεt predetermined range. 23. Method for εynchronizing an output εignal of a phaεe-locked loop -(PLL) arrangement with an input reference signal comprising the stepε of: detecting the phaεe difference between εaid output εignal and εaid reference εignal to provide an error signal representa¬ tive of said phase difference; filtering said error εignal in digital filter meanε (6D) to provide a digital control signal,- gradually decreaεing the cut-off frequency of εaid digital filter means (6D) from a seventh level to an eight level over a fourth period of time; converting said digital control signal into a control signal; and controlling the output signal in response to said control signal, c h a r a c t e r i z e d in that it further compriseε the εteps of: interrupting εaid εtep of gradually decreaεing the cut-off frequency when said digital control signal lies outside a first predetermined range,* and resuming said step of gradually decreaεing the cut-off frequency when said digital control signal lies within said first predetermined range. 24. Method for synchronizing an output signal of a phase-locked loop (PLL) arrangement with an input reference signal comprising the steps of : detecting the phase difference between said output signal and said reference signal to provide an error signal representa¬ tive of said phaεe difference,- filtering εaid error εignal in digital filter means (6D) to provide a digital control εignal ,- converting said digital control signal into a control signal; and controlling the output signal in response to said control signal, c h a r a c t e r i z e d in that it further comprises the step of limiting the output signal as well as an internal feedback signal of said digital filter means (6D) to both lie within a second predetermined range.

Inventors: BJENNE ANDERS, FRANSSON CLARENCE, LUNDH PETER, WILHELMSSON MATS, BJENNE, ANDERS, FRANSSON, CLARENCE, LUNDH, PETER, WILHELMSSON, MATS
Applicants: BJENNE ANDERS, ERICSSON TELEFON AB L M, FRANSSON CLARENCE, LUNDH PETER, WILHELMSSON MATS, BJENNE, ANDERS, FRANSSON, CLARENCE, LUNDH, PETER, TELEFONAKTIEBOLAGET LM ERICSSON (PUBL), WILHELMSSON, MATS
Application year: 1996
Main classification: H03L7
IPC codes: H03L7