APPARATUS AND METHOD FOR EXECUTING POP INSTRUCTIONS

Abstract: An apparatus and method for implementing a POP instruction to transfer data from the top of the stack to an internal register in a more efficient manner than carried out by current microprocessors. Reduction in the number of clock cycles required to execute a POP instruction is accomplished by a microprocessor architecture which enables the basic operations of the POP instruction to be executed in a single clock cycle. The microprocessor architecture of the present invention uses two arithmetic logic units which function as adders to execute both of the POP operations (a read operation of the memory using the current stack pointer value and stack base address and an incrementing of the stack pointer value) in a single clock cycle. This provides a significant savings in the time required to execute a POP instruction.

Description: APPARATUS AND METHOD FOR EXECUTING POP INSTRUCTIONS TECHNICAL FIELD The present invention relates to a POP instruction used by a microprocessor to transfer the data 5word on the top of the stack to an internal register, and more specifically, to an apparatus and method for computing a POP instruction compatible with an Intel 486™ microprocessor in significantly fewer clock cycles than is currently required by that processor. BACKGROUND OF THE INVENTION Many microprocessors organize the memory in a manner which partitions it into multiple, lQindependent address spaces. Typically, such independent spaces are assigned to store a program's code, data to be used in executing the program, and a stack. The stack is a segment of memory containing a dynamic, sequential list of data and having the capability to be accessed from one end. The stack is used to store return addresses, parameters passed by a calling routine, and temporary variables assigned by a routine. A POP instruction is used by a microprocessor to transfer the word or doubleword located at the 15current top of the stack to the register location indicated by a destination operand provided when executing the instruction. The register which indicates the current top of the stack (the SP or stack pointer register) is then incremented to point to the new memory address corresponding to the top of the stack. The POP instruction thus has the effect of moving the word at the top of the stack to a register or memory. As noted in the 1992 version of the Intel 486™ Microprocessor Family "Programmer's Reference 2CManual" at page 26-230, the POP instruction requires 4 clock cycles in order to transfer the word or doubleword at the top of the stack to a register. As the POP instruction is a commonly used instruction (comprising as much as 4% of the executed instructions according to some estimates), the amount of time spent executing this one instruction can become a significant factor in the speed with which a program can be executed. What is desired is an apparatus and method for implementing a POP instruction in a more efficient 25manner than is currently used for implementing such operations in Intel 486™ compatible microprocessors. SUMMARY OF THE INVENTION The present invention is directed to an apparatus and method for implementing a POP instruction to transfer data from the top of the stack to an internal register in a more efficient manner than carried out by current microprocessors, particularly the Intel 486™. A reduction in the number of clock cycles required to 3Cexecute a POP instruction is achieved by a microprocessor architecture which enables the basic operations of the POP instruction to be executed in a single clock cycle. The POP instruction consists of two basic operations: (1) a read operation of the memory using an address formed from the current stack pointer value and stack base address; and (2) incrementing the stack pointer value by either 2 or 4, depending upon the size of the operand. The microprocessor architecture of the 35present invention uses two arithmetic logic units which function as adders to execute both of the POP operations in a single clock cycle. This provides a significant decrease in the time required to execute a POP instruction in an Intel 486™ compatible microprocessor. Further objects and advantages of the present invention will become apparent from the following detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a block diagram of the architecture of a microprocessor which includes apparatus for efficiently computing a POP instruction according to the method of the present invention. Fig. 2 is a detailed diagram showing the portions of the architecture of the microprocessor of Fig. 1 5which are used in executing a POP instruction according to the method of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT Fig. 1 is a block diagram of the architecture of a microprocessor 1 which includes apparatus for efficiently computing a POP instruction according to the method of the present invention. The microprocessor architecture employs a three stage pipeline using microprogrammed control. The three primary stages of the lCpipeline are the decode, execute and writeback stages. The writeback stage is further divided into two substages. The second writeback substage is used for some of the memory accesses. This architecture has the benefit of needing only three stages for register to register operations. The decode stage contains the decode unit 10, but the stage functions as more than just an instruction decoder. This stage also includes the prefetch buffer 12, the instruction cache 14, and the l≤microsequencer 16. Prefetch buffer 12 is 16 bytes wide and is designed as a two tier unit. Prefetch unit 12 acts to keep instruction decoder 10 fully supplied with all the bytes of the instruction it is currently decoding. Prefetch unit 12 interfaces with instruction cache 14, and is designed to fetch ahead of the decode stage. This look ahead mechanism improves the efficiency with which the processor operates. Instruction cache 14 contains 1 K bytes organized as a direct map with a line size of 8 bytes. 2CCache 14 checks on the bus to avoid stale data due to self modifying code. A 1 K byte size cache provides a significant performance improvement, and is particularly effective for executing small groups of application code. Decoder 10 is capable of decoding simple instructions in a single cycle. Prefixes and complex instructions can take more than one cycle to decode. Microsequencer 16 steps through the decoded microcode for the instructions. Most of the microcode is stepped through in a single cycle except for complex instructions, 25which include the ones needed to support the protection mechanism of the 486™ microprocessor. The execute stage not only fetches operands and executes the instructions, but also completes the memory addresses. As noted, the 486™ architecture has a segmented address space, with many complex addressing modes being used to access this space. A segmented memory space means that to obtain the physical address that actually goes on the bus, at least one addition must be performed, that of the segment base and the 30offset within that segment. This can be further complicated by the computation of the segment offset, which can have up to three parts; a base, an index, and a displacement. Execution unit 18 is capable of performing the entire address computation in a single cycle. As will be discussed later, this is a result of being able to perform two addition operations in a single clock cycle. Segment limit checking is also done at this point to prevent segment overruns. The linear address thus computed 35(which is also the physical address in this case) is sent to bus unit 20 for dispatch to the external world. As will be described in greater detail later, this design allows the single cycle execution of frequently used load, store, push and pop instructions. The execute stage also utilizes the architectural register file 22 and protection logic unit 24. Register file 22 resolves the source and destination information for all the operations in the execute stage. It 40also allows bypassing of results either from the output of the arithmetic and logic unit (ALU), or from a load operation from memory. This helps to reduce pipeline backups due to data dependencies. The writeback stage includes bus interface unit 20, debug logic unit 26 and register writeback logic. In this stage the memory access is initiated and completed. The register file update is also performed. The second writeback substage permits the completion of an independent register operation, out of order, while a memory write access is pending. In this architecture, the memory access is pipelined, which allows a new read/write operation to be initiated every cycle. As indicated in figure 1, the microprocessor core is divided into 11 blocks to reduce the complexity of the design. These blocks are the prefetch unit 12, decoder unit 10, microsequencer 16, register file unit 22, 5execution unit 18, protection logic unit 24, exception logic unit 28, debug logic unit 26, bus unit 20, global control unit 30, and instruction cache 14. Prefetch unit 12 consists of two eight byte registers that are filled in from either instruction cache 14 or directly from memory. Decode unit 10 gets an instruction from prefetch unit 12 and generates the entry microcode address for the instruction, register addresses, immediate values, displacement values and segment lQnformation. Decoder 10 also generates information for some of the exceptions. Microsequencer 16 controls the process of stepping through the instruction microcode. It generates the next microcode address and performs the look ups in the micro(code) ROM. The micro-ROM address can come from decoder 10 if a new instruction is started, from the microcode if the present instruction is not finished, or from exception logic unit 28 in the case of exceptions. 15 Register file unit 22 reads the operands, resolves the bypasses, generates constants, and aligns operands for an instruction. The architecture registers and the selectors (i.e., the segment lookup registers) are implemented in this block. Register file 22 has dual read and write ports. Registers contained in register file unit 22 can be accessed either as a single byte, a word (2 bytes), or a doubleword (4 bytes). This ability is the basis for the use of dual read and write ports. The dual write ports are used to optimize load instructions and for 2Qsimultaneous completion of instructions. Execution unit 18 has two major functions. One is to perform all the arithmetic and logic operations. For this function, execution unit 18 has an arithmetic and logic unit and a barrel shifter. The second function(s) of execution unit 18 are address computation (linear address generation) and limit checking. The design of this unit allows computation of the address offset, linear address, and limit checking in a single clock 25cycle. Bus unit 20 is the interface of the core to the external world. An important feature of this unit is the ability to support pipelined memory access where a memory access is initiated before the previous one has finished. In this mode, the external DRAMs which constitute the memory are divided into pages, typically 4 K bytes long. As long as an access is within one page in the DRAM, single cycle reads and writes to memory can 30be sustained. If a page miss occurs, then it takes 3 cycles to complete that access. DRAM, SRAM and ROM accesses can also be supported with wait states and non-pipelined memory accesses. Global control unit 30 is the supervisor of the entire architecture. This unit controls the stepping of the instruction pipeline. Interlocks, control of the exception handling, and process shutdown are also handled by this unit. Exception logic unit 28 prioritizes and resolves all the exceptions and external interrupts. This 3Sncludes the software interrupts, arithmetic exceptions, protected mode exceptions, and other faults and traps. Protection logic unit 24 is responsible for the protection mechanism defined in the Intel 486™ implementation. This unit is required for the implementation of the segmented memory architecture of the 486™. Debug logic unit 26 includes all the debug registers and implements the instruction and data breakpoints. Debug logic unit 26, along with bus unit 20, also implements the requirements for the external ICE 4C(in circuit emulation) support. Fig. 2 is a detailed diagram showing the portions of the architecture of the microprocessor of figure 1 which are used in executing a POP instruction according to the method of the present invention. As indicated in figure 2, register file 22 provides a stack pointer (SP) value as an input to element 52. The stack pointer is a value corresponding to an offset from a base address in the stack to the top-of-stack 45(TOS) in the currently accessed stack segment. The base address of the first memory location in the currently accessed stack is contained in the stack segment base (SS) in register 46. Thus, the address [SS:SP] describes the location of the top of the stack segment whose starting memory location is identified by the contents of the SS base register. When executing a POP instruction, the data at this location would be retrieved from memory and written to a location in register file 22, or to a destination address provided as an operand when calling the POP instruction. 5 Element 52 is shown as a two-input-single-output logic element or switch. It typically takes the form of a data multiplexer, with control logic selecting which of the two inputs to route out of the element as the output. The control logic for selecting the desired output is typically contained in a register file control unit (not shown). The second input to element 52 is provided along path 60. This signal "bypasses" the return loop to register 22, and is used when executing sequential POP instructions. This aspect of the present invention will be lOdiscussed in greater detail later. The output of element 52 is provided as an input to arithmetic logic unit (ALU) 40. In the preferred embodiment of the present invention, ALU 40 is principally used to implement adding operations. The second input to ALU 40 is provided along the data path which includes element 44. Element 44 is a memory unit hich provides a constant whose value is to be used to increment the stack pointer. The 15value of the constant used in any particular execution cycle depends upon the size of the data words being accessed. In most situations element 44 will provide a value of +2 for word sized operands and +4 for doubleword sized operands. The value provided by element 44 serves as the second input to ALU 40. ALU 40 performs an add operation on its two inputs, with the resulting output serving as the incremented value of the stack pointer (SP). 2CThis incremented value is stored in register 54. As noted, the output of element 52 is provided as an input to ALU 40. It is also provided as an input to arithmetic logic unit (ALU) 42. In the preferred embodiment of the present invention, ALU 42 is principally used to implement adding operations. A second input to ALU 42 is the stack segment base address provided by register 46. 25 ALU 42 performs an add operation on its two inputs, thereby adding the base value and offset to obtain the address in memory 50 of the data located at the top of the stack. The output of ALU 42 is then used to access memory 50. As indicated by the dotted line in figure 2, memory 50 is typically external to the microprocessor elements shown in the figure. As noted, the output value of ALU 42 corresponds to the address [SS:SP] of the top of the stack, and thus is the location of the data to be written to register 22. When executing 30_ POP instruction according to the method of the present invention, the data contained in the memory location described by [SS:SP1 is read. When the memory is accessed, it returns the data value found at that address. In accordance with the present invention, a processing unit constructed as is described with reference to figure 2 is capable of executing a POP instruction in a single clock cycle. This is accomplished by the use of ALUs 40 and 42, which perform the steps of: (1) calculating the address in memory of the top of the 35stack; and (2) incrementing the stack pointer by a desired value in a single clock cycle. Thus, in a single clock cycle, the apparatus of figure 2 produces the outputs of both ALU 40 and ALU 42. As noted, the output of ALU 40 is stored in register 54. This value is the incremented stack pointer which is used to indicate the new location of the data at the top of the stack when executing the next POP instruction. As indicated by figure 2, in the next clock cycle the value stored in register 54 takes each of 40two data paths: (1) the value is sent to register 22 and stored there as the stack pointer (SP); and (2) the value is sent along data path 60 directly to element 52. As shown in figure 2, the data sent along data path 60 forms one input to element 52 with the other input provided from register 22. As previously discussed, control logic determines which of the two inputs to element 52 is passed by that element to ALU 40. The value provided along data path 60 is used as the output of element 52 in the situation where 45two POP instructions are executed sequentially. In such a situation, the control logic recognizes the existence of sequential POP instructions and causes the data along path 60 to be output by element 52. In this case a single clock cycle is all that is necessary for the incremented stack pointer to be passed from register 54 to ALU 40. This permits ALU 40 to be loaded with the (incremented) stack pointer in the clock cycle after the add operation performed by ALU 40, rather than having to wait another clock cycle to have the stack pointer retrieved from register 22. 5 In accordance with the present invention, an apparatus and method of executing a POP instruction in a single clock cycle has been described. This apparatus and method can be used to execute a compatible POP instruction for many types of microprocessors, in particular an Intel 486™ microprocessor. The present invention accomplishes this goal by using two ALUs to calculate the memory address of the top of the stack from the stack pointer and stack segment base and increment the stack pointer during the same clock cycle. The lQresult is an apparatus and method for executing a POP instruction in significantly fewer clock cycles than required by microprocessors such as the Intel 486™. This can speed up the execution of many application programs which frequently utilize POP instructions. The invention embodiments described herein have been implemented in an integrated circuit which includes a number of additional functions and features which are described in the following co-pending, 15commonly assigned patent applications, the disclosure of each of which is incorporated herein by reference: U.S. patent application Serial No. 08/ , entitled "DISPLAY CONTROLLER CAPABLE OF ACCESSING AN EXTERNAL MEMORY FOR GRAY SCALE MODULATION DATA" (atty. docket no. NSC1-62700); U S. patent application Serial No. 08/ , entitled "SERIAL INTERFACE CAPABLE OF OPERATING IN TWO DIFFERENT SERIAL DATA TRANSFER MODES" (atty. docket no. NSC1-62800); U.S. patent 20_pplication Serial No. 08/ , entitled "HIGH PERFORMANCE MULTIFUNCΗON DIRECT MEMORY ACCESS (DMA) CONTROLLER" (atty. docket no. NSC1-62900); U.S. patent application Serial No. 08/ , entitled "OPEN DRAIN MULTI-SOURCE CLOCK GENERATOR HAVING MINIMUM PULSE WIDTH" (atty. docket no. NSC1-63000); U.S. patent application Serial No. 08/ , entitled "INTEGRATED CIRCUIT WITH MULTIPLE FUNCTIONS SHARING MULTIPLE INTERNAL SIGNAL 25BUSES ACCORDING TO DISTRIBUTED BUS ACCESS AND CONTROL ARBITRAΗON" (atty. docket no. NSC1-63100); U.S. patent application Serial No. 08/ , entitled "EXECUTION UNIT ARCHITECTURE TO SUPPORT x86 INSTRUCΗON SET AND x86 SEGMENTED ADDRESSING" (atty. docket no. NSC1-63300); U.S. patent application Serial No. 08/ , entitled "BARREL SHIFTER" (atty. docket no. NSC1-63400); U.S. patent application Serial No. 08/ , entitled "BIT SEARCHING 30IΗROUGH 8, 16, OR 32-BIT OPERANDS USING A 32-BIT DATA PATH" (atty. docket no. NSC 1-63500); U.S. patent application Serial No. 08/ , entitled "DOUBLE PRECISION (64-BIT) SHIFT OPERATIONS USING A 32-BIT DATA PATH" (atty. docket no. NSC1-63600); U.S. patent application Serial No. 08/ , entitled "METHOD FOR PERFORMING SIGNED DIVISION" (atty. docket no. NSC 1-63700); U.S. patent application Serial No. 08/ , entitled "METHOD FOR PERFORMING 35ROTATE THROUGH CARRY USING A 32-BIT BARREL SHIFTER AND COUNTER" (atty. docket no. NSC1-63800); U.S. patent application Serial No. 08/ , entitled "AREA AND TIME EFFICIENT FIELD EXTRACTION CIRCUIT" (atty. docket no. NSCl-63900); U.S. patent application Serial No. 08/ , entitled "NON-ARITHMEΗCAL CIRCULAR BUFFER CELL AVAILABILITY STATUS INDICATOR CIRCUIT" (atty. docket no. NSCl-64000); U.S. patent application Serial No. 08/ , 40entitled "TAGGED PREFETCH AND INSTRUCΗON DECODER FOR VARIABLE LENGTH INSTRUCΗON SET AND METHOD OF OPERATION" (atty. docket no. NSC1-64100); U.S. patent application Serial No. 08/ , entitled "PARTITIONED DECODER CIRCUIT FOR LOW POWER OPERATION" (atty. docket no. NSC1-64200); U.S. patent application Serial No. 08/ , entitled "CIRCUIT FOR DESIGNATING INSTRUCΗON POINTERS FOR USE BY A PROCESSOR DECODER" (atty. docket no. 45NSC1-64300); U.S. patent application Serial No. 08/ , entitled "CIRCUIT FOR GENERATING A DEMAND-BASED GATED CLOCK" (atty. docket no. NSC1-64500); U.S. patent application Serial No. 08/ , entitled "INCREMENTOR DECREMENTOR" (atty. docket no. NSC1-64700); U.S. patent application Serial No. 08/ , entitled "A PIPELINED MICROPROCESSOR THAT PIPELINES MEMORY REQUESTS TO AN EXTERNAL MEMORY" (atty. docket no. NSC1-64800); U.S. patent application Serial No. 08/ , entitled "CODE BREAKPOINT DECODER" (atty. docket no. NSC1-64900); U.S. patent application Serial No. 08/ , entitled "TWO TIER PREFETCH BUFFER STRUCTURE AND METHOD WITH BYPASS" (atty. docket no. NSC1-65000); U.S. patent application Serial No. 08/ , entitled "INSTRUCΗON LIMIT CHECK FOR MICROPROCESSOR" (atty. docket no. NSCl-65100); U.S. patent application Serial No. 08/ , entitled "A PIPELINED MICROPROCESSOR THAT MAKES MEMORY REQUESTS TO A CACHE MEMORY AND AN EXTERNAL MEMORY CONTROLLER DURING THE SAME CLOCK CYCLE" (atty. docket no. NSC1-65200); U.S. patent application Serial No. 08/ , entitled "APPARATUS AND METHOD FOR EFFICIENT COMPUTATION OF A 486™ MICROPROCESSOR COMPATIBLE POP INSTRUCΗON" (atty. docket no. NSCl-65700); U.S. patent application Serial No. 08/ , entitled "APPARATUS AND METHOD FOR EFFICIENTLY DETERMINING ADDRESSES FOR MISALIGNED DATA STORED IN MEMORY" (atty. docket no. NSC1-65800); U.S. patent application Serial No. 08/ , entitled "METHOD OF IMPLEMENTING FAST 486™ MICROPROCESSOR COMPATIBLE STRING OPERAΗON" (atty. docket no. NSC1-65900); U.S. patent application Serial No. 08/ , entitled "A PIPELINED MICROPROCESSOR THAT PREVENTS THE CACHE FROM BEING READ WHEN THE CONTENTS OF THE CACHE ARE INVALID" (atty. docket no. NSCl-66000); U.S. patent application Serial No. 08/ , entitled "DRAM CONTROLLER THAT REDUCES THE TIME REQUIRED TO PROCESS MEMORY REQUESTS" (atty. docket no. NSC1-66300); U.S. patent application Serial No. 08/ , entitled "INTEGRATED PRIMARY BUS AND SECONDARY BUS CONTROLLER WITH REDUCED PIN COUNT" (atty. docket no. NSC1-66400); U.S. patent application Serial No. 08/ , entitled "SUPPLY AND INTERFACE CONFIGURABLE INPUT/OUTPUT BUFFER" (atty. docket no. NSC1-66500); U.S. patent application Serial No. 08/ , entitled "CLOCK GENERATION CIRCUIT FOR A DISPLAY CONTROLLER HAVING A FINE TUNEABLE FRAME RATE" (atty. docket no. NSC1-66600); U.S. patent application Serial No. 08/ , entitled "CONFIGURABLE POWER MANAGEMENT SCHEME" (atty. docket no. NSC1-66700); U.S. patent application Serial No. 08/ , entitled "BIDIRECπONAL PARALLEL SIGNAL INTERFACE" (atty. docket no. NSC1-67000); U.S. patent application Serial No. 08/ , _ntitled "LIQUID CRYSTAL DISPLAY (LCD) PROTECΗON CIRCUIT" (atty. docket no. NSCl-67100); U.S. patent application Serial No. 08/ , entitled "IN-CIRCUTT EMULATOR STATUS INDICATOR CIRCUIT" (atty. docket no. NSC1-67400); U.S. patent application Serial No. 08/ , entitled "DISPLAY CONTROLLER CAPABLE OF ACCESSING GRAPHICS DATA FROM A SHARED SYSTEM MEMORY" (atty. docket no. NSC1-67500); U.S. patent application Serial No. 08/ , entitled "INTEGRATED CIRCUIT WITH TEST SIGNAL BUSES AND TEST CONTROL CIRCUITS" (atty. docket no. NSC1-67600); U.S. patent application Serial no. 08/ , entitled "DECODE BLOCK TEST METHOD AND APPARATUS" (atty. docket no. NSC1-68000). The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention in the use of such terms and expressions of excluding equivalents of the features shown and described, or portions thereof, it being recognized that various modifications are possible within the scope of the invention claimed.

Claims: We claim: 1. An apparatus for executing a POP instruction to transfer data from a top of a stack section in a memory to an internal register in a single clock cycle, comprising: means for inputting a stack segment base address to a first adder means, wherein the stack Ssegment base address corresponds to an address in the memory of a beginning location of the stack; means for inputting a stack pointer value to the first adder means and to a second adder means, wherein the stack pointer value corresponds to an offset of a top of the stack from the stack segment base address; first adder means for adding the stack segment base address and the stack pointer to lOdetermine an address in the memory of the top of the stack; means for providing an incrementing value to be added to the stack pointer value; and second adder means for adding the incrementing value to the stack pointer value to determine an incremented stack pointer value, wherein the first adder means and the second adder means perform their respective add operations during a same clock cycle. 15 2. The apparatus for executing a POP instruction of claim 1, further comprising: means for inputting the incremented stack pointer value instead of the stack pointer value to the second adder means when executing sequential POP instructions. 3. The apparatus for executing a POP instruction of claim 1, wherein die means for inputting a stack segment base address to a first adder means is a register. 20 4. The apparatus for executing a POP instruction of claim 1, wherein the means for inputting a stack pointer value to the first adder means and to a second adder means is a register. 5. The apparatus for executing a POP instruction of claim 1, wherein the first adder means is an arithmetic logic unit. 6. The apparatus for executing a POP instruction of claim 1, wherein the second adder means is 25an arithmetic logic unit. 7. A method for executing a POP instruction to transfer data from a top of a stack section of a memory to an internal register in a single clock cycle, comprising: providing a stack segment base address, wherein the stack segment base address corresponds to an address in a memory of a beginning location of a stack; 30 providing a stack pointer value, wherein the stack pointer value corresponds to an offset of a top of the stack from the stack segment base address; adding the stack segment base address and the stack pointer to determine an address in the memory of the top of the stack; providing an incrementing value to be added to the stack pointer value; and 35 adding the incrementing value to the stack pointer value to determine an incremented stack pointer value, wherein the step of adding the stack segment base address and the stack pointer and the step of adding the incrementing value to the stack pointer value are performed during a same clock cycle.

Inventors: NEMIROVSKY MARIO, PEREZ ALEXANDER, NEMIROVSKY, MARIO, PEREZ, ALEXANDER
Applicants: NAT SEMICONDUCTOR CORP, NATIONAL SEMICONDUCTOR CORPORATION
Application year: 1996
Main classification: G06F9
IPC codes: G06F7, G06F9