Method for rapid validation and coding of cyclic codes

Abstract: A method for rapid validation of cyclic codes, the method including the steps of acquiring (100) a sequence of n bits defining a received vector r=(r 0 ,r 1 ,......,r n-1 ) of length n; calculating (110) a control function (s) for the acquired bits; examining (120) the control function (s) to determine whether the received vector r is an acceptable code word; calculating (160) a pseudo control function (s p ) for a dummy vector r b of length n, the first b bits of the dummy vector being equal to zero, and the next n-b bits of the dummy vector being equal to the corresponding bits of the previously acquired vector r; acquiring (170) b new bits following the last bit used to calculate the current control function; and calculating (180) a new control function value for a new sequence of bits including, in sequence, the last n-b bits of the received vector and the next b new bits.

Description: The present invention relates to a method for rapid validation and coding of cyclic codes. As is known, cyclic codes are a particular class of linear parity check codes, and are of enormous practical use by comprising, not only all the characteristics of parity check codes, but also certain specific characteristics for simplifying decoding using simple mathematical algorithms. The main characteristic of a cyclic code is the following: a linear code is a cyclic code if, and only if, a cyclic shift of a code word produces another code word. Details of cyclic codes are to be found in numerous publications on transmission theory, such as, "DIGITAL TRANSMISSION THEORY" by S. Benedetto, E. Biglieri and V. Castellani, Prentice-Hall International Editions. Decoding of a cyclic code is preceded by determining a sequence of n bits defining a received vector r=(r 0 ,r 1 ,......,r n-1 ), which, due to noise along the transmission channel, may be other than the transmitted cyclic code. When decoding a cyclic code, therefore, a preliminary or validity check is made to determine acceptability of the received vector, e.g. by examining the so-called syndrome s, which is defined as the product of vector r multiplied by the transpose of a parity check matrix H, i.e. s=rH T . If syndrome s equals a zero vector, vector r is an acceptable code word; whereas, if the syndrome equals other than a zero vector, vector r contains transmission errors or, at any rate, is invalid as a code word. For instance EP-A-154 538 discloses a syndrome generator for the detection and/or the correction of errors in a communication system The validity check is followed by the actual decoding step (if necessary) using known mathematical algorithms, and, following or concurrently with this, another sequence of n bits defining a further vector r' for decoding is received. Vector r' may comprise part of the bits of the previously received vector r together with other bits received after the last bit of vector r so as to analyze the data in groups of n in an "observation window" moving over the entire received bit sequence. Since, as stated, any cyclic rotation of a code word of a cyclic code produces another code word, the corresponding syndrome of which is zero, a vector may also be validated by calculating its rotation syndrome as opposed to its syndrome. As another n-bit syndrome is also calculated for vector r', known validation operations therefore involve calculating a number of syndromes, one for each received vector. This is normally done using a dividing circuit comprising a shift register into which all the bits forming the received vector are entered sequentially. For each received vector, therefore, all the bits forming the vector are entered into the shift register, and, between two successive syndrome calculations, the shift register must be reset, thus making calculation of the syndrome fairly complex and enormously time-consuming. Patent US-A-5,131,012 discloses a method of synchronization of cyclic codes which performs an update of a previous validation. It is an object of the present invention to provide a method permitting rapid validation of a cyclic code. In view of the close structural similarity - acknowledged in literature - between validation and coding operations, the method according to the present invention may also be used for accelerating coding of a cyclic code. According to the present invention, there are provided a method for rapid validation of cyclic codes, as claimed in Claim 1, and a method for rapid coding of cyclic codes, as claimed in Claim 17. The invention will now be described with reference to the accompanying drawings, in which: Figure 1 shows a block diagram of the steps in the method according to the present invention, for performing a syndrome-based validity check; Figure 2 shows a block diagram of the steps in the method according to the present invention, for performing a validity check based on calculation of the parity check bits; Figure 3 shows a block diagram of the steps in the method according to the present invention, as applied to parity check coding. The steps in the method according to the present invention will now be described with reference to Figure 1. To begin with, a block 100 reads n bits forming part of a bit sequence supplied over a transmission channel (not shown) by a remote transmission source (not shown) transmitting a cyclic code, and which are acquired sequentially and memorized. Purely by way of a non-limiting example, the transmission source may comprise a transmitter (not shown) located along a railway line (not shown) and for cyclically transmitting a bit sequence to a receiver-demodulator (not shown) on a rail vehicle (not shown) on the line. The n-bit sequence defines a vector r=(r 0 ,r 1 ,......,r n-1 ) of length n. Block 100 is followed by a block 110, which, in known manner, calculates a control function, e.g. the syndrome s function, of the n bits acquired by the previous block 100. Syndrome 2 may be calculated with reference to vector r, by multiplying vector r by the transpose of a parity check matrix H, i.e. s=rH T . More details concerning the syndrome calculation are to be found in "ERROR CORRECTING CODES" by Shu Lin and Daniel Costello, PRENTICE HALL Editions, which also explains how the syndrome is used for correcting errors detected during validation. Syndrome s contains information relative to the presence and location of transmission errors, and is defined by a vector of length n-k, where n is the size of vector r, and k the number of information bits in vector r. An important point to note is that syndrome s may also be calculated using sequential algorithms, e.g. shift registers (not shown) into which the bits forming the vector for examination are entered sequentially. Examples of shift registers are given in "ERROR CONTROL CODING" by Shu Lin and Daniel Costello, PRENTICE HALL Editions. Depending on the properties of the cyclic codes, the syndrome function may also be calculated with reference to any cyclic rotation of vector r, by multiplying the cyclic rotation of the received vector r by the transpose of a parity check matrix H. To calculate the syndrome of a rotation of r, as opposed to rotating r, the columns of matrix H are interchanged or changes made to the shift register (not shown) into which r is entered. In fact, like the syndrome of vector r itself, the syndrome of a cyclic rotation of vector r equals a zero vector if, and only if, vector r is an acceptable code word. Conversely, both syndromes (that of vector r and its rotation) equal other than a zero vector, but may differ from each other. In the following description, however, the s symbol is used for both the syndrome of vector r and that of its rotation. Block 110 is followed by a block 120, which examines the syndrome s calculated in the previous block 110. If syndrome s equals a zero vector, block 120 goes on to a block 130. Conversely (syndrome s equal to other than a zero vector), block 120 goes on to a block 125. Block 130 determines that the previously acquired n-bit sequence (telegram) forms a received message acknowledged as forming part of the code. As is known, if syndrome s equals a zero vector, vector r is an acceptable code word, whereas, if syndrome s equals other than a zero vector, the presence of transmission errors in vector r, or at any rate the invalidity of vector r as a code word, is detected (block 125). Both blocks 125 and 130 are followed by block 140. Block 140 determines whether a sufficient number of bits (e.g. b bits) have been received to permit further processing. If they have not, block 140 goes on to block 150, which terminates the data acquisition and validation operations. If they have, block 140 goes on to block 160. Block 160 calculates the syndrome (referred to, for the sake of simplicity, as the pseudosyndrome) s p of a dummy vector r b of length n, the first b bits of which equal zero, and the next n-b bits of which equal the corresponding bits of vector r, i.e.: s p =r b H T where r b =(0, .. .. ,0,r b , ......, r n-1 ) In other words, vector r b is obtained from vector r by zeroing the first b bits of vector r. The pseudosyndrome is calculated by "subtracting" from the current syndrome s a correction syndrome calculated for a correction vector r*=(r 0 ,r 1 ,......, r b-1 , ,0, ....,0) of length n, the first b bits of which equal the corresponding bits of vector r, and the next n-b bits of which equal zero. Depending on the properties of the cyclic codes, the correction syndrome may be calculated on the basis of a cyclic rotation of vector r*=(r 0 ,r 1 ,......, r b-1 , ,0, ....,0). More specifically, the correction syndrome is calculated on the basis of a cyclic rotation of vector r*=(r 0 ,r 1 ,......, r b-1 , ,0, ....,0) when the calculation in block 110 is also made on the basis of a rotation of r, and with reference to the same rotation as in block. The pseudosyndrome calculation is explained by the linearity of the syndrome (the syndrome of the sum equals the sum of the syndromes) so that syndrome s of vector r=(r 0 ,r 1 ,......,r n-1 ) may be thought of as being the sum of the syndromes of correction vector r*=(r 0 ,r 1 ,......, r b-1 , ,0, ....,0) and of dummy vector r b =(0, .. ..,0,r b ,......,r n-1 ), i.e.: (r 0 ,r 1 ,......,r n-1 ) H T =(r 0 ,r 1 ,......, r b-1 , ,0, ....,0) H T + (0, .. ..,0,r b ,......,r n-1 ) H T so that: (0, .. ..,0,r b ,......,r n-1 ) H T = (r 0 ,r 1 ,......,r n-1 ) H T - (r 0 ,r 1 ,......, r b-1 , ,0, ....,0) H T where the - sign indicates an EXOR logic operation. In other words, block 160 calculates pseudosyndrome s p by performing an EXOR operation of the current syndrome s and the correction syndrome. In the event b < n - k, where k is the number of information bits of received vector r, a highly simplified form of the correction syndrome may be obtained by referring the entire syndrome calculation procedure to a cyclic rotation of the vector in question, as opposed to the vector itself, so that the first n-k bits of the vector become the last; in which case, the correction syndrome comprises a sequence of bits comprising the first b bits (r 0 ,r 1 ,......,r b-1 ) of received vector r, followed by n-k-b zero bits. The same also applies to lesser rotations of vector r, providing they are no less than b. Even in the event n - k < b ≤ n, the correction 20 syndrome need not be calculated for each b-bit "advance," by depending, for a given type of cyclic code, solely on the correction sequence as opposed to the current processing status, and may therefore be calculated once for each sequence (r 0 ,r 1 ,......, r b-1 , ,0, ....,0), memorized in a table, and used for fast table searches. Block 160 is followed by a block 170, which reads b bits following the last bit used to calculate the current syndrome. Block 170 is followed by a block 180, which updates the current syndrome s with the b bits detected in block 170 and as of the current pseudosyndrome s p value. For example, block 180 sequentially enters the b new bits detected in block 170 into the shift register forming the pseudosyndrome to obtain a new current syndrome. A new control function value is thus calculated for a new bit sequence (new vector) comprising, in sequence, the last n-b bits of the received vector and the next b new bits, so as to analyze the data in groups of n in an "observation window" moving over the entire sequence of received bits in steps b (where 1 ≤ b ≤ n). Finally, block 180 goes back to block 120. For the sake of simplicity, the s symbol is also used in block 120 to indicate a new syndrome of a new vector r, which is to be taken as indicating the starting point of any update of the syndrome at any shift of the observation window. The advantages of the method according to the present invention will be clear from the foregoing description. That is, as opposed to calculating a new n-bit syndrome, the operation (syndrome calculation) in block 180 is performed by updating a previously calculated (pseudo) syndrome with b new bits. In other words, as opposed to resetting the shift register and entering n new bits, a new syndrome is calculated by updating the content of the shift register with b new bits (where b ≤ n). Bearing in mind that one bit is entered into the shift register at each CLOCK pulse, calculation of the syndrome according to the above method is decidedly faster as compared with the corresponding known operation. Moreover, in addition to being extremely fast, the above method is also straightforward and may be applied generally to any type of cyclic redundancy code. To further accelerate validation according to the method of the present invention, the operations in block 180 may also be performed, by means of software algorithms or appropriate hardware structures, by performing the operations corresponding to each bit, as well as the operations in blocks 160 and 170, concurrently. The Figure 2 method differs from that in Figure 1 by the control function being calculated by calculating the parity check bits (so-called CRC calculation) as opposed to the syndrome. To begin with, a block 100a reads n bits forming part of a bit sequence supplied over a transmission channel (not shown) by a remote transmission source (not shown) transmitting a cyclic code, and which are acquired sequentially and memorized. The n-bit sequence defines a vector r=(r 0 ,r 1 ,......,r n-1 ) of length n. Block 100a is followed by a block 110a, which examines the first k information bits of received vector r; and the same parity check law as in transmission is applied to the k bits to obtain a bit set (parity or CRC calculation). More details concerning CRC calculation are to be found in "ERROR CORRECTING CODES" by Shu Lin and Daniel Costello, PRENTICE HALL Editions. In the next block 120a, the bit set calculated in block 110a is compared with the last n-k bits of the received vector, which should correspond to the parity check bits. If the bit set calculated in block 110a corresponds to the n-k parity check bits, block 120a goes on to block 130a. Conversely, block 120a goes on to block 125a. Block 130a determines that the previously acquired n-bit sequence (telegram) forms a received message acknowledged as forming part of the code, whereas block 125a determines the presence of transmission errors in vector r, or at any rate the invalidity of vector r as a code word. Both blocks 125a and 130a are followed by block 140a. Block 140a determines whether a sufficient number of bits (e.g. b bits) have been received to permit further processing. If they have not, block 140a goes on to block 150a, which terminates the data acquisition and validation operations. If they have, block 140a goes on to block 160a. Block 160a calculates the parity check (CRC P ) of a dummy vector r b of length k, the first b bits of which equal zero, and the next k-b bits of which equal the corresponding bits of vector r, i.e.: r b =(0, .. ..,0,r b ,......,r k-1 ) The parity check for the dummy vector is calculated by "subtracting" from the current parity check a correction parity check calculated for a correction vector r**=(r 0 ,r 1 , .. . . ,r b-1 ,0......,0) of length k. The subtraction may be made by performing a logic EXOR operation of each bit of the current parity check and the corresponding bit of the correction parity check. Block 160a is followed by block 170a, which reads b bits following the n bits currently being validated; and the position of the n bits currently being validated - vector r - and the "window" of the first k of these bits, i.e. of the bits currently being examined to calculate the CRC, are therefore moved b bits forward. Block 170a is followed by a block 180a in which a new parity check bit value relative to the new position of the k bits under examination is calculated by updating the block 160a calculation with the b new bits of the k new current bits determined in block 170a. For example, block 180a sequentially enters the b new bits detected in block 170a into a shift register forming the parity check (defined previously) for the dummy vector. New parity check bits are thus calculated for a new bit sequence (new vector) - also referred to as a new examination window - comprising, in sequence, the last k-b bits already examined of the received vector, and the next b bits. Unlike the syndrome-based validation procedure, in which no distinction is made between the observation window and the examination window for which the control function is calculated, when validating by calculating the parity check bits, the examination window for calculating the control function only coincides with the first k bits of the observation window. Finally, block 180a goes back to block 120a. The advantages of the above method will be clear from the foregoing description. That is, as opposed to a new k-bit calculation, the operation in block 180a (parity check bit calculation) is performed by updating the block 160a calculation with b new bits. The steps in the coding of a cyclic code according to the method of the present invention will now be described with reference to Figure 3. To begin with, a block 200 reads a sequence of k bits for coding. Block 200 is followed by a block 210, which examines and applies a coding law to the k bits detected in block 200 to obtain a set of parity check bits (CRC calculation). More details concerning the CRC calculation are to be found in "ERROR CORRECTING CODES" by Shu Lin and Daniel Costello, PRENTICE HALL Editions. Block 210 is followed by a block 220, which determines whether a data transmission request is present. If it is, block 220 goes on to block 230. If it is not, block 220 goes on to block 240. Block 230 provides for connecting the set of parity check bits calculated in block 210 to the k bits for transmission, and so forming an n-bit sequence defining a vector r=(r 0 ,r 1 ,......,r n-1 ) of length n, the first k bits of which are information bits, and the last n-k bits of which are the parity check bits calculated for block 210. Block 230 then goes on to block 240. Block 240 determines whether a sufficient number of bits (e.g. b bits) have been detected to permit further coding. If they have not, block 240 goes on to block 250, which terminates the coding procedure. If they have, block 240 goes on to block 260. Block 260 applies the coding law to a dummy vector r b of length k, the first b bits of which equal zero, and the next k-b bits of which equal the corresponding bits in the sequence. Coding is performed by "subtracting" from the current code a correction code calculated for a correction vector r**=(r 0 , r 1 , .. ..,r b-1 ,0,....., 0) of length k; which subtraction is made by performing a logic EXOR operation of each bit of the current code and the corresponding bit of the correction code. Block 260 is followed by block 270, which reads b bits following the last bit used to calculate the parity check bits. Block 270 is followed by block 280 in which the parity check bit calculation performed in block 260 for the dummy vector is updated with the b new bits to calculate a new set of parity check bits for a new bit sequence comprising, in sequence, the last k-b bits of the sequence and the next b new bits. For example, block 280 sequentially enters the b new bits detected in block 270 into a shift register forming the code for the dummy vector. Finally, block 280 goes back to block 220. The advantages of the above method will be clear from the foregoing description. That is, as opposed to a new k-bit calculation, the operation in block 280 (parity check bit calculation) is performed by updating the block 260 calculation with b new bits. For example, the method described may also be used for validating and/or coding codes substantially similar to cyclic codes, e.g. shortened cyclic codes.

Claims: A validation method for the rapid validation of cyclic codes, comprising the following sequence of steps: a) acquiring (100) a sequence of n bits to be validated from an input stream; said sequence of n bits defining a received vector r=(r 0 , r 1 , ...... r n-1 ) of length n; b) calculating (110) a current validation value (s) based on the n bits of the received vector r; c) using (120) the current validation value (s) to determine whether the received vector r is an acceptable codeword, characterized by comprising the steps of: d) calculating (160) a pseudo validation value (s p ) for a dummy vector rb of length n; the first b bits of the dummy vector being equal to zero, and the remaining n-b bits of the dummy vector being equal to the corresponding bits of the vector r, such that r b =(0, ..., 0, r b , ...., r n-1 ), and b being smaller than n; said step of calculating (160) a pseudo validation value (s p ) comprising the steps of: acquiring a correction validation value for a correction vector r'=(r 0 ,r 1 ...., r b-1 , 0, ...., 0) of length n; the first b bits of the correction vector being equal to the corresponding bits of the received vector r, and the next n-b bits of the correction vector being equal to zero; and subtracting said correction validation value from the current validation value (s) to calculate said pseudo validation value (s p ); the validation method further comprising the steps of: e) acquiring (170) b new bits from the input stream following the last acquired bits; and f) calculating (180) a new validation value from the pseudo validation value (s p ) and the b newly acquired bits, the new validation value forming the current validation value for the sequence of n bits comprising, in sequence, the last n-b bits from the previously acquired vector r and the b newly acquired bits, whereby the step of calculating the new validation value is performed by sequentially entering the b newly acquired bits into a shift register type divider forming said pseudo validation value. A method as claimed in Claim 1, characterized in that said step of calculating said validation value (110) based on the n bits of the received vector r comprises the step of calculating the syndrome s. A method as claimed in Claim 2, characterized in that said syndrome s is calculated by multiplying the received vector r by a transpose of a parity check matrix H (s=rH T ). A method as claimed in Claim 2, characterized in that said step of calculating said syndrome s comprises the step of sequentially entering said received n bits into said shift register type divider. A method as claimed in any one of the foregoing Claims from 2 to 4, characterized in that said step of using (120) the validation value (s) to determine whether the received vector r is an acceptable codeword comprises the step of determining whether the syndrome s equals a zero vector. A method as claimed in any one of the foregoing Claims from 2 to 5, characterized in that said step of calculating (160) a pseudo validation value (s p ) comprises the step of calculating the syndrome of said dummy vector r b . A method as claimed in any one of the foregoing claims, characterized in that said step of subtracting said correction validation value from the current validation value (s) comprises the step of performing an EXOR operation of the current validation value (s) and said correction validation value. A method as claimed in Claim 2, characterized in that said step of acquiring a correction validation value comprises the step of calculating a correction syndrome; said correction syndrome comprises a simplified form obtained by referring the entire syndrome calculation procedure to a cyclic rotation of said received vector; said simplified form of said correction syndrome, in the event b < n - k, where k is the number of information bits of said received vector r, comprising a sequence of bits comprising the first b bits (r 0 , r 1 ...., r b-1 ) of the received vector r, followed by n-k-b zero bits. A method as claimed in Claim 2, characterized in that said step of acquiring a correction validation value comprises the step of calculating a correction syndrome; said step of calculating a correction syndrome for a correction vector r'= (r 0 ,r 1 , .... ,r b-1 ,0,...., 0) of length n comprises the step of calculating the syndrome of a cyclic rotation of said correction vector. A method as claimed in Claim 9, characterized in that said syndrome s is calculated by multiplying a cyclic rotation of the received vector r by a transpose of a parity check matrix H. A validation method for the rapid validation of cyclic codes, comprising the following sequence of steps: a) acquiring (100a) a sequence of n bits to be validated from an input stream; said sequence of n bits defining a received vector r=(r 0 , r 1 , ...., r n-1 ) of length n; b) calculating (110a) a current validation value (CRC) based on at least the first k bits of the received vector r, whereby k is smaller or equal to n; c) using (120a) the current validation value (CRC) to determine whether the received vector r is an acceptable codeword, characterized by comprising the steps of: d) calculating (160a) a pseudo validation value (CRC p ) for a dummy vector rb of predetermined length k; the first b bits of the dummy vector being equal to zero, and the remaining k-b bits of the dummy vector being equal to the corresponding bits of the vector r, such that r b =(0, ...., 0,r b , ...., r k-1 ), and b being smaller than k; said step of calculating (160a) a pseudo validation value (CRC p ) comprising the steps of: acquiring a correction validation value for a correction vector r**= (r 0 ,r 1 , .... ,r b-1 /0, ....0) of length k; the first b bits of the correction vector being equal to the corresponding bits of the received vector and the next k-b bits of the correction vector being equal to zero; subtracting said correction validation value from the current validation value to calculate said pseudo validation value (CRC p ); the method further comprising the steps of: e) reading (170a) b new bits from the input stream following the last n acquired bits to be validated thereby moving the position of the n bits to be validated, the vector r, and the first k bits of vector r, in points a) to d) above b bits forward in the input stream; f) calculating (180a) a new validation value for the new position of the k bits under examination by updating the calculation of step d), whereby the calculation of the new validation value is performed by sequentially entering the b new bits of the k new current bits determined in step c) into a shift register type divider forming said pseudo validation value. A validation method as claimed in Claim 11, characterized in that said step of calculating (l10a) a validation value comprises the steps of applying a parity check law to the first k bits of the received vector r to obtain a parity check (CRC); the parity check (CRC) refers to the k bits as to its information bits; said step of calculating a pseudo validation value (CRC p ) comprising the steps of: applying said parity check law (160a) to a dummy vector r b of length k; the first b bits of the dummy vector being equal to zero, and the next k-b bits of the dummy vector being equal to the corresponding bits of the previously acquired vector r; acquiring (170a) b new bits and examining b bits following the last bit used for calculating the current parity; and updating (180a) the parity check bit calculation with the b next bits examined, to calculate a new set of parity check bits for a new sequence of bits comprising, in sequence, the last k-b bits already examined and used in the preceding parity check bit calculation, and the b next bits examined. A method as claimed in Claim 12, characterized in that said step of applying said parity check law (160a) to a dummy vector (r b ) of length k comprises the step of subtracting from the current parity check a correction parity check calculated for a correction vector r**= (r 0 , r 1 , ...., r b-1 , 0,....,0) of length k; the first b bits of the correction vector being equal to the corresponding bits of the received vector r, and the next k-b bits of the correction vector being equal to zero. A method as claimed in Claim 13, characterized in that said subtracting step comprises the step of performing a logic EXOR operation of the current parity check and said correction parity check. A method as claimed in Claim 11, characterized in that said step of using (120a) the validation value (CRC) to determine whether the received vector is an acceptable codeword comprises the step of comparing said parity check with the parity check bits of the received vector. A method as claimed in any one of the foregoing Claims, characterized in that said step of using the validation value (s; CRC) to determine whether the received vector (s) is an acceptable codeword is followed by the step of determining (140; 140a) whether a sufficient number (b) of bits is detected for performing further processing, and by the step of terminating (150; 150a) the data acquisition operations in the event an insufficient number of bits is detected. A method for rapid coding of cyclic codes, comprising the steps of: acquiring (200) a sequence of k bits for coding; applying a coding law to said k bits to calculate (210) a current validation value, characterized by comprising the steps of: applying (260) said coding law to a dummy vector (r b ) of length k to calculate a pseudo validation value; the first b bits of the dummy vector being equal to zero, and the next k-b bits of the dummy vector being equal to the corresponding bits in the sequence; acquiring (270) b new bits following the last bit used for calculating the current validation value; and updating the validation value calculation previously performed (260) by sequentially entering, into a shift register type divider forming the pseudo validation value, the b newly acquired bits to calculate a new validation value for a new sequence of bits comprising, in sequence, the last k-b bits of the sequence and the next b new bits; said method further comprising the steps of acquiring a correction validation value calculated for a correction vector r**= (r 0 , r 1 ...., r b-1 , 0, ...., 0) of length k; the first b bits of the correction vector being equal to the corresponding bits in the sequence, and the next k-b bits of the correction vector being equal to zero; said step of applying (260) said coding law to a dummy vector (rb) comprises the step of subtracting from the current validation value the correction validation value. A method as claimed in Claim 17, characterized in that said subtracting step comprises the step of performing a logic EXOR operation of the current validation value and said correction validation value. A method as claimed in any one of the foregoing Claims, characterized in that said cyclic codes are shortened cyclic codes. A method as claimed in any one of the foregoing claims, characterised by the fact that said step of acquiring a correction validation value comprises the step of searching among pre calculated values of said correction validation value.

Inventors: TAMPONI ALDO, TAMPONI, ALDO
Applicants: ANSALDO TRASPORTI SPA, ANSALDO TRASPORTI S.P.A.
Application year: 1996
Main classification: H03M13
IPC codes: H03M13