Fault tolerant distributed control system

Abstract: A fault tolerant distributed intelligence control system (10) for sensing and control has fault tolerant fibre optic communication media (21,22,23) interconnecting a plurality of intelligent nodes (12,14,16,18,20). Each intelligent node comprises a digital control and communication processor (DCCP) (28) operating autonomously in relation to DCCPs at other nodes, and a transceiver (26) for interfacing with the communication media (21,22,23). The fibre optic communication media comprises bi-directional serial data buses (21,22,23). The combination provides a low cost highly reliable distributed control system particularly applicable to primary and secondary aircraft control systems, as well as to other vehicle and control systems.

Description: This invention relates to a fault-tolerant, distributed-intelligence control system, and to a method of assembling and operating such a system. Typical aircraft today employ hydraulic pumps and actuator systems for the primary and secondary flight controls, plus large amounts of shielded twisted-pair point-to-point cabling and connectors for all of the sensors, controls and environmental equipment throughout the aircraft. Much of this equipment is heavy, costly and labour-intensive, and in many cases is uniquely designed for each customer's equipment configuration. Current large-scale distributed sensor/actuator systems for control, communications and lighting of airplane systems, vehicle control systems, or industrial process control systems are primarily implemented as point-to-point buses with dedicated wiring controls. For example, in aircraft an ARINC 429 or ARINC 629 standard is used which adds over one hundred pounds of wire and connectors to a small commercial aircraft. This interconnect topology consumes significant amounts of time in design and assembly, and results in excess weight, complexity and inflexibility of the configured control system. Fly-by-light for aircraft control has been envisioned and prototype systems have been demonstrated for a number of years, primarily on high-performance NASA and military aircraft. However, fly-by-light has not been broadly incorporated into an aircraft product because the approach has been to use highly centralized control, typical of current fly-by-wire systems, resulting in cumbersome and expensive systems. Centralized flight control fly-by-light systems require substantial bandwidth in the interconnect and large numbers of fibers for aircraft control systems in order to receive sensor data, perform the control laws and supply the centralized control to the actuators distributed around the aircraft. Centralized fly-by-wire or fly-by-light systems also require complex, high-performance multi-tasking processor systems. The cost of such a centralized point-to-point system is substantial; it requires more complex, high-throughput flight control computers coupled with electronics to drive and receive multiple high-data-rate signals. In the prior art, a fly-by-light architecture is described in a paper entitled "A Low Maintenance and Highly Reliable Fly-By-Light architecture" by Dan Palumbo, NASA Langley Research Center. The fly-by-light characteristics of the architecture are a serial fiber optic backplane and redundant fiber optic data bus. A distributed architecture is realized by utilizing several processing clusters on the data bus. A processing cluster is comprised of one or more processing units. However, although this architecture is distributed, it is narrowly distributed with tasks being closely coupled as shown by the number of processing modules which are co-located. In this architecture if one node is destroyed many functions are destroyed; in fact each node performs multiple tasks instead of a node being dedicated to a specific control law or sensor function. This system requires a fibre optic backplane in addition to redundant fibre optic data buses. Further, this architecture requires voting at every network line connection. A simpler approach would have voting only at actuation nodes where consistency checks occur between three autonomous fault tolerant processors. A fibre-optic control system integration (FOCSI) project is described in an article entitled "NASA, Navy to Evaluate Fly-By-Light Sensors in F/A-18" by Stanley W. Kandebo, Aviation Week & Space Technology, August 2, 1993. It describes tests to be performed in a fibre-optic control system. Passive optical sensors and fibre optic data links are employed in that sensing and actuation signals are transmitted optically. However, the architecture used is largely centralised and it is more costly than a distributed architecture such as the present invention. It points out that the fibre optic control system reduces signal transmission harness weight, cuts harness volume, cuts aircraft certification costs by offering greater immunity to electromagnetic effects, and boosts aircraft fire safety by eliminating possible ignition sources. These advantages and others are provided by preferred embodiments of the present invention. In "Autonomous Decentralised Computer Control Systems" at pages 57 to 66 of IEEE Computer, Volume 17, No. 8, August 1984, H. Ihara and K. Mori described an autonomous decentralised loop (ADL) network system in which a plurality of intelligent nodes, each in the form of a host processor and a pair of network control processors, are interconnected in a double-loop structure designed for optical transmission in opposite directions. Each network control processor (NCP) of a node acts as a controller on a respective one of the two optical transmission lines, the two network control processors of the node being fused and connected to the host processor. Software stored in a ROM in an NCP is used for controlling transmission, and the NCP has a built-in tester. The information transmission function of a buffer memory serves as a communication path in the NCP. Each NCP broadcasts a message containing a content code instead of a receiver's address. An NCP decides whether or not to accept a message on the basis of content. Only the originating NCP can remove the message from the respective loop after it returns. The necessary content codes for a host are stored in the connected NCP pair. The host can dynamically change the content codes in the connected NCP pair. Thus each NCP has antonomy in sending and receiving messages. A loop is not occupied by any NCP, since each NCP functions in both the store-and-forward transmission mode and the through transmission mode. When a host generates any new information, the host sends it to the connected NCP pair with the appropriate content code. Each NCP transmits this information to a downstream NCP in a serial message format that includes the content code, the sender's address, and a frame check sequence. In "Autonomous Decentralised Steel Production Process Control System" at pages 1457 to 1460 of the Conference Record of the 1989 IPEE Industry Applications Society Annual Meeting, Part II, San Diego 1-5 October, 1989, K. Mori et al describe the use of an ADL as an optical fibre cable local area network connecting a plurality of HIDIC V90/5 series mini-computers in which the functions of three major software subsystems are distributed, these subsystems being real-time process control of a cold mill section of a steel production process, on-line information management, and software development. The present invention is defined by claim 1 hereinafter, to which reference should now be made. Preferred embodiments of the invention provide: a fault tolerant, distributed low-cost control-by-light™ system having a bi-directional single fibre, serial communication media for enhanced reliability; a combination of distributed intelligence, fibre optic network communications and fault tolerant techniques to produce a low cost aircraft sensor/actuator control system that can withstand a number of failures without impacting overall performance, with local nodes providing distributed intelligence to perform sensor processing or local actuator control; a highly distributed vehicle control network using fibre optics to provide a control system having substantially reduced sensitivity to electromagnetic interference (EMI), lightning, and high intensity radiated field (HIRF) environments; a fault tolerant, distributed control-by-light™ system having fibre optic networks interconnecting fault-tolerant intelligent nodes, which may be applied to many types of critical or trusted control system problems such as aircraft control, ship control, vehicle control, industrial process control, launch and/or fire control, utility switching control, etc. The use of serial messages that contain synchronisation bits is described in "Profibus Contra Interbus-S" by B. Jünger at pages 68 to 79 of Elektronik, Volume 43, No. 21, 18th October 1994. In a preferred embodiment of the control system of the invention, the nodes comprise either a simplex node, a dual control node or a triple or greater control node in accordance with the application-specific predetermined level of the redundancy. The communication media comprises fibre optic bus means (preferred, although other media may be employed depending upon the application platform) for interconnecting the intelligent nodes. The transceiver means and said fibre optic bus means provide for bi-directional communication over the media. The transceiver means and the fibre optic bus means may alternatively provide for unidirectional communication over the media. The plurality of intelligent nodes are arranged in a ring topology. The plurality of intelligent nodes may also be arranged in a point to point topology. The processor means comprises a digital control and communication processor having a local operating network to provide network communications among the distributed intelligence processors. Each of the nodes comprises at least one processing element, and each processing element comprises transceiver means for interfacing the processing element to the interconnecting fibre optic bus means, each of the intelligent nodes being connected via the transceiver means to one or more bi-directional fibre optic buses of the fibre optic bus means in accordance with a predetermined level of redundancy. Each processing element in each of the nodes comprises processor means having a local operating network coupled to the transceiver means for processing messages transmitted or received on the fibre optic bus means and for processing application-specific tasks of the nodes, the processor means operating autonomously in the control system. The nodes are coupled to actuators/sensors or control devices for performing control or data processing tasks. Each of the nodes comprises either one of the processing elements, dual processing elements or triple processing elements (or greater) in accordance with an application-specific predetermined level of redundancy. The bi-directional fibre optic buses transmit messages in two directions around the ring topology for enhanced reliability. Each processing element comprises means for generating and detecting the time beacon for synchronisation of messages being transmitted and received, one of the time beacon generating means being preselected to generate said timing beacon in the control system. The preferred fault tolerant distributed control system is assembled by carrying out the steps of providing a plurality of intelligent nodes, each of the nodes comprising at least one processing element, interconnecting each of the intelligent nodes with at least one bi-directional fibre optic bus in accordance with a predetermined level of redundancy, and interfacing each of the processing elements in each of the nodes to the interconnecting fibre optic bus with transceiver means. The system operates by processing in each element of the nodes messages transmitted or received on the fibre optic bus and processing application-specific tasks of the nodes with the processor means having a local operating network coupled to the transceiver means, the processor means operating autonomously in the control system. The step of interconnecting each of the intelligent nodes comprises the step of arranging the plurality of nodes in a ring topology wherein the bi-directional fibre optic buses transmit messages in two directions around the ring topology for enhanced reliability. One of the processing elements is preselected to generate the time beacon for synchronisation of messages being transmitted and received, each processing element comprising means to generate and detect the time beacon. Brief Description of the Drawings Other and further features and advantages of the invention will become apparent in connection with the accompanying drawings wherein: FIG. 1 is a block diagram of a fault-tolerant distributed control-by-light™ system employing the present invention; FIG. 2 is a block diagram of a transceiver coupled to a digital control and communication processor as shown in FIG. 1; FIG. 3 is an illustration of the time slot arrangement of the deterministic protocol within a beacon signal period; FIG. 4 is a detailed block diagram of the deterministic control portion of the transceiver as shown in FIG. 2; FIG. 5 is a block diagram of the state machine shown in FIG. 3; FIG. 6 is a flow chart of the media access algorithm embodied in the PROM of the DCCP in FIG. 2; FIG. 7 is a schematic diagram of a voter switching circuit employed in the voter node of FIG. 1; and FIG. 8 is a schematic representation of an optically isolated receiver shown in FIG. 7. Description of the Preferred Embodiment Referring to FIG. 1, a block diagram of a distributed intelligence fault tolerant control-by-light™ system 10 is shown comprising a deterministic network protocol for communication with a plurality of intelligent nodes 12, 14, 16, 18, 20. Such nodes 12-20 are connected to one or more bi-directional serial buses 21, 22, 23, each of said buses being a single fiber optic ring in the preferred embodiment. The number of nodes shown in Fig. 1 is only representative of a system and one skilled in the art will recognize that many node configurations are feasible depending on the particular system application. The system 10 is particularly useful for aircraft control by providing a low cost fault-tolerant control-by-light™ distributed intelligence system for sensing and control across fault tolerant fiber optic networks. The system 10 uses the distributed local intelligent nodes 12-20 to sense and/or control physical parameters and actuators with messages being passed across redundant serial buses 21,22,23 whenever sense or control information changes. In order to achieve fault tolerant operation, two, three or four or more redundant data buses are employed depending upon the criticality, and redundancy is also employed in certain intelligent nodes performing critical functions such as sensor/actuator functions in an aircraft control system. The coupling of the nodes 12-20 to the serial data buses is accomplished by transceivers 26 1-N and each transceiver 26 1-N is connected to a digital control and communication processor (DCCP) 28 1-N . Each combination of a transceiver and a DCCP may be referred to as a processing element. This system 10 in an aircraft application replaces mechanical, hydraulic and electrical controls now used by aircraft pilots to control, monitor, and display primary and secondary flight control functions and it provides substantial weight, cost, safety and performance advantages over current techniques. This system 10 is applicable to control of other systems besides aircraft such as ground transportation, surface and submarine ships, spacecraft, utilities and industrial process controls. Although the data bus media in the present preferred embodiment is implemented with fiber optics, the deterministic network protocol is applicable to other medias such as twisted pair wiring and power lines. Node 12 is representative of a simplex control node, node 14 is representative of a dual control node, and node 16 is a triple control node including fault tolerant intelligent voters which are described hereinafter. Node 18 is a fault tolerant, fail fast, triple digital node for interfacing with digital sensors/actuators and node 20 is a fault tolerant, fail fast, triple analog node for interfacing with analog sensors/actuators. The broadcast link shown in node 18 and node 20 is a bi-directional serial bus similar to buses 21,22,23. The preferred embodiment of the broadcast link replaces the bi-directional photo-diodes 68 and 70 and the Single Fiber Analog Interface 66 of Figure 2 with an optically isolated electrical interface. This provides a reduction of node cost, and is appropriate for use within a single equipment enclosure such as would typically be used for a node such as 18 or 20. By distributing the system intelligence to every node, network communications is reduced, autonomy for failure-recovery is enhanced, and reliability is improved. In an aircraft application of the control-by-light™ system 10, information flow between node computers can be minimized by distributing the control algorithms across the aircraft. It becomes possible to design a set of global data messages which pass across the communication network and correspond to aircraft state, physical parameters, and pilot commands. Individual nodes 12-20 may subscribe to a given set of messages depending on the function they perform. For example a thrust reverser control computer would subscribe to messages indicating whether the aircraft is airborne, the state of the engine, the state of the thrust lever, the state of the landing gear, and whether the pilot has commanded thrust reverser deployment. The thrust reverser control computer would publish data messages corresponding to the state of the reverser system. A crew alerting computer or subsystem would then subscribe to the status messages being published by the thrust reverser control computer as well as from other computers and subsystems distributed across the network. For critical control functions, messages must be received and voted upon across redundant networks before actions are taken at the point of actuation. A node computer such as the DCCP 28 1-N may be programmed to provide local loop closure on an actuator. By associating the software required to control the actuator with its actuator, and by standardizing on a network protocol, it becomes much easier to interface components across the aircraft, while also enhancing flexibility and configurability. Partitioning the software also aids in minimizing maintenance and certification costs. The control-by-light™ system 16 uses fiber optic serial data buses 21,22,23 which support multiple message transmitters. The bus network relies on a distributed media access technique to eliminate collisions, while at the same time not introducing any single points of failure. The advantages of a collision free network protocol are well known and are especially desirable for aircraft control systems or other critical control system applications. The bus network covering transceiver 26 1-N and buses 21,22,23 supports bi-directional communications over a single fiber by restricting communications to half duplex. This has the obvious benefit of reducing the cost to interconnect processing nodes to a single fiber. Each fiber optic transceiver 26 has two bi-directional, half duplex ports. This allows large networks to be created by connecting together processing elements into rings. Each node within the network or ring is connected to its neighbors by a bi-directional, half-duplex point to point fiber link. As a message propagates around the network, the message is regenerated at each node 12-20. To prevent a single node or link failure from disabling the network, every message is transmitted across the ring in both directions and is removed from the ring by the node which receives it from both directions. This method of transmission guarantees the delivery of all messages to all operating nodes, in the event of single hardware failures or fiber breaks. The control-by-light™ system uses combinations of traditional fault tolerant techniques including hardware redundancy, software redundancy, temporal redundancy, and information redundancy. Flight critical functions are implemented using nodes composed of multiple processing elements. Hardware and software voters are utilized to ensure the validity of commands. Multiple, independent data buses 21,22,23 are utilized to ensure the validity of data. Asynchronous sampling techniques are used to reduce the effects of transient upsets or disturbances. Software design includes techniques such as recovery blocks and reasonableness checking known to those of ordinary skill in the art of software fault tolerance. The DCCPs 28 1-N in the nodes 12-20 are powered from multiple sources to allow the system 10 to operate while an aircraft or other system is in an emergency reversionary state. Internally, the DCCPs 28 1-N utilize more than one power supply to allow for uninterrupted operation after a single hardware fault. Depending upon the application and the criticality of the function being implemented, multiple actuators and sensors can be used. A control-by-light™ system enforces the partitioning of software across multiple processing elements thereby creating independent software executables which implement an easily definable function. All the independent routines communicate via a well defined interface. The software partitioning allows for exhaustive testing of the software, providing a level of confidence which is often difficult and expensive to achieve on more centralized systems. Referring to Fig. 2 block diagrams of the digital control and communication processor (DCCP) 28 and the transceiver 26 forming a processing element are shown. The DCCP 28 provides the network and applications - specific processing within a node to process inputs from sensors and control devices intelligently and propagate control information across a network such as is shown in Fig. 1. The DCCP 28 comprises a VLSI chip 50 having three controllers 52 which include a media access control (MAC) processor, a network processor and an application processor; all three controllers 52 communicate on common address and data bus 60 to a random access memory (RAM) 56 and non-volatile, programmable read only memory (PROM) 58. The three controllers 52 are coupled to a network communication port 54 which interfaces with the single fiber controller 64 of transceiver 26. The transceiver 26 and in particular the deterministic controller 72 is connected to the bus 60 via a bus extension 62. The RAM 56 provides general purpose storage of network messages and program variables. The PROM 58 stores programs and configuration data for the three controllers 52, including a media access control system routine described hereinafter for initiating a priority or a non-priority message onto the network bus 21,22,23. The operation of the VLSI chip 50 is described in a Neuron® Data Book dated February 1995 for the 3150 chip published by Echelon Corporation of Palo Alto, California which is incorporated herein by reference. The VLSI chip 50 may be embodied by Part No. MC143150 manufactured by Motorola Inc. of Phoenix, Arizona. Other similar microcontrollers with network communication capabilities may also be used to implement the VLSI Chip 50. The RAM may be embodied by Part No. CY7C199 manufactured by Cypress Semiconductor of San Jose, California. The PROM 58 may be embodied by Part No. AT29C256 manufactured by Atmel Corp., San Jose, California and programmed by Raytheon Company of Marlborough, Massachusetts. Referring to Figures 1 and 2, the transceiver 26 receives and transmits data over the bi-directional data bus 21 (and buses 22,23). Data packets from or to the fiber optic data bus 21 are passed through bi-directional photo diodes 68,70 which are coupled to a single fiber analog interface (SFAI) 66 in the preferred embodiment, or in an alternative embodiment through twisted pair or other media transceivers or through separate transmit photo diodes and receive photo diodes or laser diodes which require two fiber optic cables between each node and dual fiber analog interfaces although two fiber optic cables are required. The uni-directional diodes are less costly. The SFAI 66 converts low level analog signals from the bi-directional photo diodes 68,70 to CMOS or TTL levels and vice-versa. The bi-directional diodes 68,70 function in a "ping-pong" mode whereby they operate as either a receiver or a transmitter. The photo-diodes 68,70 may also operate uni-directional whereby the operation is receive only or transmit only. Providing support for two ping-pong diodes allows for data transfers to occur in different communication topologies, e. g. a ring or star configuration. The SFAI 66 provides for rapid packet mode response from a quiet network condition to packet detection and the SFAI 66 provides for minimal turn around time from transmit to receive mode or from receive to transmit mode. The SFAI 66 converts the inputs of the photo diodes 68,70 to digital signals when in the receive mode and it converts digital signals to drive signals required by the bi-directional photo diodes 68,70 in the transmit mode. The SFAI 66 may be embodied by Part No. G641848-1 manufactured by Raytheon Company of Marlborough, Massachusetts. The bi-directional photo diodes 66,70 may be embodied by Model 1A212-SMA2A manufactured by ABB Hafo Inc. of San Diego, California, the fiber optic data buses 21,22,23 may be embodied by fiber optic cable such as Part No. BF04499 manufactured by Spectran Corp. of Avon, CT. The SFAI 66 is connected to a single fiber controller (SFC) 64 which is connected to the deterministic controller (DC) 72. The SFC 64 interfaces with a communication port 54 of the DCCP 28 and the DC 72 interfaces with buses 60,62 of the DCCP 28. The combination of the SFC 64 and DC 72 is referred to as a single fiber controller-deterministic (SFC-D) 74. The SFC-D 74 communicates bi-directionally (half-duplex) via the fiber optic data buses. It provides the control for the operation of the deterministic network protocol including a contention type protocol of the DCCP 28. Since the transceivers 26 1-N are operated in a circular or ring topology as shown in FIG. 1, the SFC 64 provides an anti-recirculation timer to automatically prevent data packets from being recirculated by deleting such data packets from the network once they are received at all nodes 14-20. The SFC 64 restores signal quality at each node 14-20 and provides for pulse width distortion compensation resulting from non-symmetrical high-to-low and low-to-high propagation delays. It also provides optical power monitoring by measuring the magnitude of pulse width distortion which provides a relative implication of optical power strength. The SFC 64 restores the signal pulse width before sending the signal to the DCCP 28 or re-transmitting the signal. Referring now to FIG. 2 and FIG. 3, Fig. 2 shows that the deterministic controller 72 is connected to the single fiber controller 64 and also interfaces with the DCCP 28. The DC 72 provides the control for a network response in a guaranteed time period by the unique combination of time slot and contention based communications. The use of the deterministic network protocol permits multiple nodes 10-20 of Fig. 1 to transmit data without chance of message collisions. Message collisions are undesirable since they result in the failure of the network to deliver these messages in a concisely bounded and predictable manner. Collision detection and/or message acknowledgment protocols could be used to detect failure of message delivery, but these methods do not provide a guarantee of system response time. The deterministic network protocol allows the system designer to place a concise upper bound on message delivery time. Fig. 3 shows a plurality of time slots 82 available for message or data packet communications. A Manchester - encoded data stream is used. Each slot is a multiple of 12.8 microseconds in duration, although this duration will change according to the network transmission specification. The definition of slots 82 for each node 12-20 must be consistent with an overall network time line defined by a system designer. A node may be assigned more than one time slot. Time slots #1 to #N are the priority slots 83 1 -83 N where contention is prevented because of hardware synchronization across the network nodes 12-20, with periodic resynchronization using the beacon signal. The next slot is the non-priority slot 84 where the contention based protocol is allowed to function. In order to provide synchronization, it is necessary to transport a synchronization signal across the network. Each node 12-20 provides for transmitting the synchronization signal, detecting the synchronization signal, and provides management of which node is in charge of originating this signal. The synchronization signal is referred to as the beacon and it may occur at time slots 81 and 86 in Fig. 3. The beacon is transported across the same medium as the subsequent data stream and does not require a separate line. The node that originates the beacon is referred to as the beacon master. The time slots 82 are measured from the time that a beacon is detected on the ring network buses 21, 22, 23. As a result, all nodes 12-20 are synchronized exactly, with the exception of skew caused by propagation delay of the beacon around the network and oscillator accuracy. The guardband time slot 85 allows time for any network message started late in the non-priority time slot 84 to be completed. Following the guardband slot 85 is a beacon slot 86 which is allocated for transmission of the network beacon 80; the beacon slot 86 is implicit and is automatically added by the state machine of the transceiver 26. The network beacon is periodically transmitted by one node to loosely synchronize all nodes 12-20 on the network. The beacon pattern is chosen to satisfy the following requirements: (a) the beacon pattern must be distinct, i.e. it must be a pattern which cannot occur during transmission of a network message; (b) the beacon pattern must not adversely impact the operation of the digital control and communication processor (DCCP); and (c) the beacon pattern should be relatively short so as not to significantly reduce the time available for network messages. For the Manchester line code employed in the present embodiment, the beacon pattern selected to meet these requirements is defined as follows: 1. TTL high (LED on) for 2000 nanoseconds. 2. TTL low (LED off) for 400 nanoseconds. 3. TTL high (LED on) for 400 nanoseconds. 4. TTL low (LED off) for 400 nanoseconds. 5. TTL high (LED on) for 400 nanoseconds. 6. TTL low (LED off) for 400 nanoseconds. 7. TTL high (LED on) for 2400 nanoseconds. This pattern violates the standards for a valid Manchester encoded data stream, and is referred to as the non-valid Manchester sequences. It, therefore, is a sequence which will not be confused with normal message transmission. Since the pattern is non-valid Manchester data, the DCCP 28 will not interpret a beacon as the start of a message, but will ignore it. The 6.4 microsecond duration of the beacon (the time required to establish the above pattern at a 1.25 megabits per second bit rate) is short compared to network messages, representing 8 bit periods on a 1.25 megabit per second network. On different bit rate networks, these times would be scaled accordingly. Referring now to Fig. 4, a block diagram of the deterministic controller 72 portion of the transceiver 26 is shown. A beacon detector 90 monitors incoming network data and generates a beacon detect 91 signal when the incoming data matches the beacon pattern defined hereinbefore. The beacon detector 90 comprises a shift register and comparator known to one of ordinary skill in the art. The beacon detect 91 signal is fed to a state machine 92 which controls the overall operation of the deterministic network protocol. The state machine 92 functions are described hereinafter. When the state machine 92 generates a beacon request 93 signal, a beacon generator 95 generates the defined beacon pattern data on the network or bus 21. The beacon generator 95 comprises a counter and logic gates known to one of ordinary skill in the art. The deterministic controller 72 comprises an application offset timer 94, a beacon watchdog timer 96, a slot counter 98 and a time since beacon counter 100. The application offset timer 94 comprises a 16 bit down counter which is loaded under state machine 92 control each time a beacon is received. The value loaded is supplied by a 16-bit application offset time constant register 110 in the DCCP interface 102. This register is loaded by the DCCP 28 during node initialization. The DCCP interface 102 provides a one -bit application offset status register 112 which permits the DCCP 28 to determine when the application offset timer has expired. This is used in conjunction with DCCP 28 application software to ensure that messages are issued only once per beacon period. Beacon Period is the sum of the duration of all priority slots 83 1 -83 N , plus the non-priority slot 84, the guardband slot 85, and the implicit beacon slot 81 as shown in Fig. 3. The beacon watchdog timer is an 8 bit down counter which is loaded under state machine 92 control each time a beacon is received by the beacon detector 90. The value loaded is supplied by an 8-bit beacon watchdog time constant register 116 in the DCCP interface 102. This register is loaded by the DCCP 28 during node initialization. The DCCP 28 interface 102 provides a one-bit beacon watchdog status register 118 which permits the DCCP to determine when the beacon watchdog timer 96 has expired. This permits the DCCP 28 to detect loss of beacons on the network. Synchronization among nodes and guard-banding of transmit periods is sufficient to allow nodes to remain synchronized for several beacon periods, should the beacon master generation node fail. In this case software in the DCCP 28 elects a new beacon master, which assumes responsibility for beacon generation. The Slot Counter 98 comprises a 5-bit up counter which is reset to zero by the state machine 92 each time a beacon is received. It is used to select one of 32 locations in a slot RAM 106, and is advanced by one when commanded by the state machine 92. The time since beacon counter 100 comprises a 16-bit up counter which is reset to zero by the state machine 92 each time a beacon is received. This counter 100 counts at a 78 Khz (12.8 µsec) rate for the preferred embodiment but one skilled in the art will recognize that this counter rate will vary depending on the data rate employed. The Slot RAM 106 comprises a 32 word x 16 bit static RAM which is used to define the allocation of network slots 82 within a beacon period. This RAM is loaded by the DCCP 28 during node initialization. For most of the entries, the most significant bit indicates whether the slot is allocated to this node or not. The lower 15 bits indicate the end time of the slot, with the least significant bit representing 12.8 microseconds. For the non-priority and guard band slot end times as shown in Fig. 3, all 16 bits are used to represent the slot end time. Entries into the slot RAM are as follows: (1) a series of 16 bit words defining the end times and ownership of all priority slots 83 1 -83 N ; (2) one 16 bit value defining the start time of the non-priority slot 84; this should be identical to the end time of the last priority slot; (3) one 16 bit value defining the end time of the non-priority slot; and (4) one 16 bit value defining the end time of the guard band slot. A multiplexer 104 provides a path by which the DCCP 28 can directly address the slot RAM 106 during initialization. A deterministic mode control register 120 in the DCCP Interface 102 permits the DCCP 28 to command entry into the deterministic mode. When not in the deterministic mode, the DCCP 28 has access to the Slot RAM 106 to perform initialization. A compare 108 function comprises a 16 bit comparator plus gating logic which detects and indicates when the slot end time from the slot RAM 106 matches the time since last beacon. As described above, this is either a 15 or 16 bit comparison, depending on the current slot type. The DCCP Interface 102 provides the DCCP 28 with access to the functional elements of the deterministic controller 72. It includes address decoding and data path logic which permits the DCCP 28 to read and write registers to control and monitor the deterministic network protocol. This includes: the ability to read and write the application offset timer 94 and beacon watchdog timer 96, the ability to command entry into deterministic mode, the ability to read and write the Slot RAM 104 (when not in deterministic mode), and the ability to read status registers which indicate when a timer has expired or what the current slot type is. The deterministic controller 72 located at each node 12-20 is initialized by application code running in the DCCP 28. This code writes into registers which define the application offset timer 94 and beacon watchdog timer 96 intervals. The operating mode and such items as whether the node is beacon master or beacon slave are also written at this time. It then writes a sequence of values into the slot RAM 104 which define the allocation of network slots 82. Once initialization is completed, the DCCP 28 commands entry into deterministic operating mode. While in deterministic operating mode, the DCCP interface 102 can no longer modify the slot RAM 106. The single fiber controller 64 and the deterministic controller 72 may be embodied by a single chip referred to as the single fiber control-deterministic 74, Part No. G649806-1, manufactured by Raytheon Company of Marlborough, Massachusetts. Referring now to Fig. 4 and Fig. 5, Fig. 5 shows a flow chart of the state machine 92 of Fig. 4 with each state identified by a hexadecimal number. The state machine 92 controls the deterministic network protocol operation. When the deterministic mode is entered, the state machine 92 enters state 0 or the entry state. The beacon master moves to state D and issues a beacon request to its beacon generator 95, and then proceeds to state 6. All other nodes (the beacon slaves) go directly from state 0 to state 6. In state 6, all nodes wait for a beacon detect indication. Software handles the case when the beacon master fails to initialize, and a back-up beacon master is turned on to issue beacons. Beacon detection produces the following effects: a) the state machine 92 is forced into state 7 (enter first slot); b) the slot counter 98 is cleared; c) the time since beacon counter 100 is cleared and begins counting up; d) the application offset timer 94 is loaded with its maximum interval and begins counting down; and e) the beacon watchdog timer 96 is loaded with its maximum interval and begins counting down. From state 7, the state machine will proceed to state 9 (enabled priority slot) if the next (first) slot is allocated to this node, and to state A (disabled (locked) priority slot) if it is not allocated to this node. In states 9 and A, the slot type is set to indicate "sync slot" or "sync lock" as appropriate. The state machine 92 then proceeds to state 2 (time delay). In state 2, the state machine 92 waits for a 12.8 microsecond interval to expire in this preferred embodiment. Each time this interval expires, the state machine 92 advances to state 3 (slot end check), where it compares the time since last beacon to the end time of the current slot. If the two do not match, the state machine 92 returns to state 2 and waits another 12.8 microseconds. If the two match, the current slot has ended. From state 3, the state machine 92 will take one of the following paths: a) If the slot which ended was a priority slot and the next slot is also a priority slot, the state machine 92 will pass through state 4 (guardband check) and into state 5, (next slot set up - where the slot counter is incremented), then into state B (non-priority check). Since the new slot RAM 106 location contains a different time value then the prior location, the state machine 92 moves to state F (enter new slot). State F is similar to state 7. From state F, the state machine 92 will move to state 9 or A based on slot ownership, and the process described above will repeat. b) If the slot which ended was a priority slot and the next slot is the non-priority slot, the state machine will pass through state 4 and into state 5 (where the slot counter in incremented) and then into state B. Since the next RAM location has the same time value as the prior location, the state machine 92 moves to state C (enter non-priority slot). In state C, the slot type is set to indicate "sync open." The state machine 92 then moves to state 2 and begins waiting for the end of the non-priority slot. c) If the slot which ended was the non-priority slot, the state machine 92 passes through state 4 and into state 5 (where the slot counter is incremented), and then into state E (enter guardband slot). In state E, a flag is set to indicate that the guardband has been entered, and the slot type is set to indicate "sync lock." The state machine 92 then moves to state 2 and begins waiting for the end of the guardband. d) If the slot which ended was the guardband, the state machine 92 passes through state 4 and into state 1 (beacon slot delay). In state 1, the state machine 92 waits a fixed amount of time. This time is 12.8 microseconds for a slave node, or the full length of the beacon slot. Slave nodes then proceed through state 8 (beacon node check) into state 7, assuming that a beacon arrived when expected. If a beacon arrived early or late, the state machine 92 would be forced into state 7 and resynchronized. A master waits approximately 6.4 microseconds in state 1, and then proceeds through states 8 and D and into state 6, where it waits for the beacon. This accounts for the fact that it takes the master 6.4 microseconds to generate a beacon. If a beacon is generated and seen by all nodes, all are resynchronized into state 7 at the time of beacon detection. Any node which misses the beacon for some reason has made an attempt to synchronize itself, and should be in error by oscillator accuracy differences only. In this way, all nodes enter state 7 at about the same time. As described in the state machine 92 description above, the deterministic controller 72 provides a slot type which is made available to the DCCP 28 through a 3-bit control register located in the DCCP interface 102. This register, called the sync state register 114, is used to ensure that messages are transmitted only in the proper time slots as shown in Fig. 3. Two bits are used to define four slot types as follows: Sync Slot: A deterministic slot allocated to a particular node; one priority message may be transmitted. Sync Lock: A deterministic slot not allocated to a particular node or nodes; transmission is prohibited. Also used during the guardband to prevent all transmissions. Sync Open: This state is for the non-priority slot time; all available non-priority messages may be transmitted. Normal: The network is running in non-deterministic mode. The third bit permits the DCCP 28 to detect consecutive slots of the same type. The reason for this is described hereinafter. The use of the deterministic network protocol assumes that the system designer defines a fixed (or at least bounded) number of message transmissions by each node within a single beacon period, and a maximum execution time for the processing required in a beacon period. Each node is given enough time slots to meet the maximum transmission load. Application code is written for the application control processor of the DCCP 28 to ensure that this limit is not exceeded; the application offset timer 94 is provided for this purpose. This timer is loaded with a time constant upon receipt of a beacon (or when a beacon is expected and not received), and counts down to zero. The DCCP interface 102 provides a register 112 in which the application code can determine when the application offset timer 94 has expired. The preferred implementation is to set the application offset timer 94 to a value which is longer than the maximum processing time and shorter than the beacon period. After completing the processing required during a period, the application code polls the application offset status register 112, waiting for the timer 94 to expire. Once the application offset timer 94 has expired, the application code updates those network variables which it wishes to transmit during the next beacon period. The act of updating the network variables causes them to be placed in application buffers which are serviced by the network processor of the DCCP 28. The network processor is responsible for transmitting these network variables onto the network. The application offset timer 94 status is cleared to ensure that this action takes place only once per beacon period. Ensuring that the application code is aware of its message limits, and causing it to issue a known number of messages once per beacon period prevents the application processor of the DCCP 28 from issuing too many messages, which would eventually overflow the DCCP's 28 application buffers. Application code may send messages either within the priority slot(s) 83 1 -83 N which have been allocated to the node or in the non-priority contention based slot 84 which follows the priority slots. Network messages which are defined as priority messages are sent during priority slots, while others are sent during the non-priority slot. The beacon watchdog timer 96 is provided to detect the loss of the beacons which synchronize the network. This timer is loaded with a time constant upon receipt of a beacon, and counts down to zero. The DCCP interface 102 provides a register 118 in which the application code can determine when the beacon watchdog timer 96 has expired. If beacons continue to arrive as expected, this timer is continually reloaded, and never expires. The preferred implementation is to set the beacon watchdog timer 96 to a value significantly greater than one beacon period. Since nodes attempt to maintain synchronization in the absence of the beacon, some number of missed beacons can be tolerated. The system designer is responsible for defining the number of consecutive missed beacons which can be tolerated. Some of the factors on which this limit is based are as follows: (1) the accuracy of the clock sources on the nodes; (2) the amount of time the system designer wishes to provide within each slot for synchronization drift; (3) the likelihood that a properly transmitted beacon may not be received by all nodes (due to factors such as system environment); and (4) the speed with which the system designer wishes to detect and correct for the failure of the beacon master node by electing a new beacon master. In the preferred embodiment, the application code checks the status of the beacon watchdog timer whenever the application offset timer 94 expires, and if necessary initiates corrective action to select a new beacon master. If the beacon watchdog timer 96 expires, the selection of a new beacon master is accomplished by software. It is important that a beacon master be selected. The method of selection is not critical. Referring now to Fig. 6, a flow chart of the media access control (MAC) software routine 130 for initiating a priority or non-priority message is shown. This MAC routine is located in the PROM 58 of the DCCP 28 shown in Fig. 2. The MAC begins 131 by checking message queues for a priority message 132 or non-priority message 133. When a message is available for transmission, the MAC examines the sync state register 134, 137 and verifies that transmission of the available message is permitted 135, 138. If the transmission is permitted, the message is sent 136, 139. If not permitted, the MAC checks the other queue and returns to this one later. In order to allow the system designer to assign consecutive priority slots to the same node, the least significant bit of the slot counter 98 is also readable in the sync state register 114 to permit the MAC to detect a new slot with the same node allocation. Since the MAC polls the sync state register 114, a variable delay may be incurred from the start of a slot time and the beginning of message transmission. The length of a priority slot must be set to accommodate both the message length and an allowance for this delay. Messages may be transmitted over the network buses 21,22,23 at any time during the non-priority slot. The guardband 85 as shown in Fig. 3 is provided within a beacon period to ensure that a message begun at the very end of the non-priority slot 84 will be completed before the start of the beacon time slot 86. Guardband slot length must accommodate the largest non-priority message in the system. Referring again to Fig. 1, the node 16 comprises three processing elements each consisting of DCCP 28/transceiver 26 elements wherein each transceiver 26 is coupled to one of the data buses 21,22,23. In particular, transceiver 26 2 is coupled to data bus 21, transceiver 26 3 is coupled to data bus 22 and transceiver 26 4 is coupled to data bus 23. Outputs from form the three DCCPs 28 2 , 28 3 , 28 4 are fed to each of three intelligent voters 31,32,33. Each of the voters 31-33 is such that it generates an actuation signal if two of the three inputs to the voter agree. The actuation signal from each voter 31-33 is used to control a respective device 36 1 , 36 2 , 36 3 wherein each of the devices in a preferred application comprises an electrically controlled hydraulic valve to be energized. Referring now to Fig. 1 and Fig. 7, a schematic circuit diagram of a voter is shown in Fig. 7 which comprises three portions 142, 146, and 144. For circuit board commonality, each of three circuit boards comprises a transceiver 26, a DCCP 28, and one of each voter portion 142, 144, 146. Each voter is constructed by taking portion 142 from one circuit board, portion 144 from a second circuit board, and portion 146 from the third circuit board. Three independent voters can be constructed from three circuit boards. Any two of the three DCCPs 28 2 ,28 3 ,28 4 must agree in order for the voter to transfer voltage (V) to the solenoid 154. The voter is implemented using four optically isolated relays 148-151 and a bridging diode 152 arranged as shown in Fig. 7. Diodes 147,153 provide a current path for turn-off transients of inductive loads, ensuring that the voltage at the solenoid 154 does not spike the power supply voltage. If any two of the three portions 142,144,146 close their optically isolated relays 148-151, a connection is made between the voltage (V) and the solenoid 154. The bridging diode 152 provides a connection path for voltage (V) to get to the solenoid 154 when the relays 148 and 151 are closed. The bridging diode 152 prevents completion of a 20 connection path when the relays 149 and 150, which are controlled by a single DCCP 28, are closed. All connections to and from the three portions 142,146 and 144 are made using optically isolated devices. The isolation provided protects each DCCP 28 2 ,28 3 ,28 4 from faults in the voltage (V) being switched by the voter, and protects the DCCPs from each other. In this manner, faults external to a DCCP, even those which damage this voter or render it inoperable, do not damage the DCCP or prevent it from carrying out other functions The isolation further permits this voter to be used as either a "high side" or a "low side" switch. If other considerations require, the voter can be placed either between voltage (V) and the solenoid, or between the solenoid and ground. The optically isolated relays 148-151 may be embodied by part number PVDZ172 manufactured by International Rectifiers of El Segundo, California. Referring now to Fig. 7 and Fig. 8, in addition to the optically isolated relays 148-151 and bridging diode 152 which provide the voting function, the distributed voter includes provisions for performance monitoring and built-in test. This is provided by optically isolated receivers 156 1 -156 6 which monitor the voltage across each solid state optically isolated relay 148-151. They are arranged as shown in Fig. 7. Optically isolated receiver 156 1 is connected across terminals 160 and 161 of optically isolated relay A 148. Optically isolated receiver 156 2 is connected across terminals 168 and 169 of optically isolated relay C 151. Optically isolated receiver 156 3 is connected across terminals 166 and 167 of optically isolated relay B1 149. Optically isolated receiver 156 4 is connected across terminals 162 and 163 of optically isolated relay B2 150. Optically isolated receiver 156 5 is connected across the terminals 168 and 169 of optically isolated relay C 151. Optically isolated receiver 156 6 is connected to the power supply voltage (V) and to the junction of terminal 162 of optically isolated relay B2, terminal 164 of diode 152 and terminal 161 of optically isolated relay A 148. These receivers take advantage of the fact that a significant amount of current is required to activate the solenoid 154. The small currents (on the order of a few milliamperes) required by the optically isolated receivers 156 1 -156 6 may be passed through the solenoid with no effect on the system. A schematic representation of each optically isolated receiver 156 1 -156 6 is shown in Figure 8. The resistor 157 and diode 158 values are chosen such that the leakage current through the receiver is not sufficient to activate the receiver. The receivers 156 1 -156 6 will only be activated if a closed relay 148-151 provides part of the current path. The most common failure mode of the optically isolated relays 148-151 is to fail in a short circuit state. The optically isolated receivers 156 1 -156 6 are configured such that the closure of a relay controlled by one of DCCPs 28 2 , 28 3 , 28 4 can be detected by each of the other two DCCPs using built-in-test software monitoring the receivers 156 1 -156 6 . The receivers 156 1 -156 6 can also be used to perform a test of the relays which is coordinated by any DCCP 28 which has access to all three DCCP 28 2 , 28 3 , 28 4 such as intelligent node 20 of Figure 1. This test may be performed off line or when system requirements permit as an on line background diagnostic test. The Table describes how each of the potential faults in the voter is detected by the monitoring functions of the optically isolated receivers 156 1 -156 6 provided. Those items which are testable "any time" may be tested by checking the monitoring points at a time when all relays are expected to be open. Those items testable during Built-In-Self-Test "BIST" may be tested only when it is safe to close certain relays and monitor the voter as a coordinated activity involving all three portions 142,144,146. This is expected to be performed either as part of pre-flight self test/diagnostics, or in a maintenance mode. FAULT WHEN TESTABLE DETECTION METHOD Relay 148 short circuit Any time Detected by monitors 156 2 ,156 4 ,156 5 Relay 149 or diode 153 short circuit Any time Detected by monitors 156 2 ,156 5 Relay 150 or diode 147 short circuit Any time Detected by monitors 156 1 ,156 6 Relay 151 short circuit Any time Detected by monitors 156 1 ,156 3 156 6 Relay 148 open circuit BIST Attempt to close 148 and use 156 2 ,156 4 156 5 to verify result Relay 149 open circuit BIST Attempt to close 149 and use 156 2 ,156 5 to verify result Relay 150 open circuit BIST Attempt to close 150 and use 156 1 ,156 6 to verify result Relay 151 open circuit BIST Attempt to close 151 and use 156 1 ,156 3 156 6 to verify result Diode 153 open circuit Not detectable This is a protection diode only Diode 152 short circuit BIST Attempt to close 149. Monitors 156 2 and 156 5 should detect a current path and monitor 156 4 should not. If 152 is shorted, monitor 156 4 will detect a current path. Diode 147 open circuit Not detectable This is a protection diode only Diode 152 open circuit BIST Attempt to close 148. Monitors 156 4 , 156 2 and 156 5 should all detect a current path. If diode 152 is open, monitors 156 2 and 156 5 will not detect the current path.

Claims: A fault-tolerant, distributed-intelligence control system comprising a plurality of intelligent nodes (12,14, 16, 18,20) coupled to actuators/sensors or control devices and one or more serial communication media (21,22,23) interconnecting the nodes (12,14,16,18,20), each node including transceiver means (26) for interfacing the node with one or more of the serial communication media (21,22,23) in accordance with a predetermined level of redundancy, and each node including processing means (28) for processing messages transmitted or received on the one or more serial communication media and for processing application-specific tasks of the node, the processor means (28) operating autonomously and being coupled to the respective transceiver means (26), characterised in that each node (12,14,16,18,20) includes means (72) for generating and detecting a time beacon (81,86) for synchronisation of messages being transmitted and received by the nodes (12,14,16,18,20) over the one or more serial communication media (21,22,23), with one of the nodes being, in operation, selected to generate the time beacon (81,86), the nodes being such that the messages conform to a valid Manchester encoded data stream protocol, and the time beacon (81,86) comprises a data stream having a plurality of data bits with a non-valid Manchester sequence. A system according to claim 1, characterised in that each node comprises either a simplex node (12), a dual control node (14) or a triple control node (16) or more in accordance with said application-specific predetermined level of said redundancy. A system according to claim 1, characterised in that the communication media comprises fibre optic bus means (21,22,23). A system according to claim 3, characterised in that each transceiver (26) and said fibre optic bus means (21,22,23) provide for bi-directional communication over said media. A system according to claim 3, characterised in that each transceiver means (26) and said fibre optic bus means (21,22,23) provide for uni-directional communication over said media. A system according to claim 1, characterised in that the plurality of intelligent nodes (12,14,16,18,20) and the one or more serial communication media (21,22,23) comprise a ring topology. A system according to claim 1, characterised in that the plurality of intelligent nodes (12,14,16,18,20) and the one or more serial communication media (21,22,23) comprise point to point topology. A system according to claim 1, characterised in that each processor means comprises a digital control and communication processor (28) having a local operating network. A system according to claim 1, characterised in that the one or more serial communication media comprise fibre optic bus means (21,22,23) for interconnecting each of said intelligent nodes; each of said intelligent nodes is connected via respective transceiver means (26) to one or more bi-directional fibre optic buses (21,22,23) of said fibre optic bus means in accordance with a predetermined level of redundancy; and each processor means (28) has a local operating network. A system according to claim 9, characterised in that each node (12,14,16,18,20) is coupled to an actuator/sensor or control device (26) for performing control or data processing tasks; and the processor means (28) of the node provides local intelligence for sensor information processing or actuator position control and loop closure. A system according to claim 9, characterised in that each of the nodes comprises at least one processing element including processor means (28) and an associated transceiver means (26), in accordance with an application-specific predetermined level of redundancy. A system according to claim 9, characterised in that said plurality of nodes (12,14,16,18,20) and the fibre optic bus means (21,22,23) are arranged to form a ring topology and the bi-directional fibre optic bus means (21,22,23) are arranged to transmit messages in two directions around said ring topology for enhanced reliability. A system according to claim 9, characterised in that said fibre optic bus means (21,22,23) is adapted for non-electro mechanical coupling of signals between said intelligent nodes and said fibre optic bus means (21,22,23) via said transceiver means (26). A system according to claim 9, characterised by a plurality of power sources for eliminating a single point failure, said nodes connected to one of said fibre optic buses being powered by said power sources. A method of assembling and operating a fault tolerant distributed-intelligence control system comprising the steps of: providing a plurality of intelligent nodes (12,14,16,18,20), each of said nodes comprising at least one processing element (26,28); interconnecting each of said intelligent nodes (12,14,16,18,20) with at least one bi-directional fibre optic bus (21,22,23) in accordance with a predetermined level of redundancy; interfacing each processing elements (26,28) in each of said nodes to said at least one interconnecting fibre optic bus (21,22,23) with transceiver means (26); and processing in each processing element (26,28) of said nodes messages transmitted or received on said at least one fibre optic bus (21,22,23) and processing application-specific tasks of said nodes with processor means (28) coupled to said transceiver means (26), said processor means (28) operating autonomously in said control system, characterised by generating at a selected one of the nodes a time beacon (81,86) for synchronisation of messages being transmitted and received by the nodes over the at least one bi-directional fibre optic bus (21,22,23), and detecting at each node the time beacon (81,86), with messages transmitted by the nodes conforming to a valid Manchester encoded data stream protocol, and the time beacon (81,86) comprising a data stream having a plurality of data bits with a non-valid Manchester sequence. A method according to claim 15, characterised in that the step of interconnecting each of said intelligent nodes comprises the step of arranging said plurality of nodes in a ring topology wherein said bi-directional fibre optic buses transmit messages in two directions around said ring topology for enhanced reliability. A method according to claim 15, characterised by the step of preselecting one of said processing elements (26,28) to generate the time beacon (81,86) for synchronisation of messages being transmitted and received, each processing element (26,28) comprising means (72) to generate and detect said time beacon (81,86).

Inventors: BATTEN MARTIN R, MORRISON BRIAN D, ROBILLARD MICHAEL N, WIENKE CREIG E, BATTEN, MARTIN R., MORRISON, BRIAN D., ROBILLARD, MICHAEL N., WIENKE, CREIG E.
Applicants: RAYTHEON CO, RAYTHEON COMPANY
Application year: 1996
Main classification: G05B9
IPC codes: G05B9, H04B10, G05B15, G05D1, G05B19