BiCMOS negative charge pump

Abstract: A charge pump comprises a plurality of stages (S1,S2,S3',S4') connected in series between a reference potential and an output terminal (O) of the charge pump. The plurality of stages comprises a first group of stages (S1,S2), proximate to the reference potential, and a second group of stages (S3',S4') proximate to the output terminal of the charge pump. Each stage of the first group comprising a pass-transistor (M1) with first and second terminals respectively connected to an input and an output of the stage, and a first capacitor (CL) with a first plate connected to the output of the stage and a second plate driven by a digital signal (B,D) switching between the reference voltage and a positive voltage (VDD); each stage of the second group comprising a junction diode (D) having a first electrode connected to an input of the stage and a second electrode connected to an output of the stage, and a second capacitor (CL') having a first plate connected to the output of the stage and a second plate driven by a digital signal (B',D') switching between the reference voltage and the voltage supply.

Description: The present invention relates to a BiCMOS negative charge pump, particularly for the integration in non-volatile memory device chips. Non-volatile memory devices require, for the operation of electrical erasure of the memory cells, the provision of on-chip negative charge pumps capable of generating a negative voltage starting from a voltage comprised between ground and the positive voltage supply (VDD). The known circuit structure of a negative charge pump in CMOS technology is depicted in Figure 1 and e.g. known from JP-A-63 185 054. The circuit comprises a plurality of stages S1-S4 connected in series between ground and an output 0 of the charge pump. Each stage comprises a P-channel pass-transistor M1, a P-channel pre-charge transistor M2 and two capacitors CP and CL; capacitor CP has a plate driven by one of two phase signals A or C, capacitor CL has a plate driven by a respective phase signal B or D; the simplified timing of the phase signals A, B, C and D is depicted in Figure 2; all the phase signals are digital signals varying between ground and a positive voltage supply, typically the voltage supply VDD of the chip wherein the charge pump is integrated; phase signals A and D are substantially in phase with respect to each other and are substantially in phase opposition with respect to signals B and C. When the charge pump is integrated in a non-volatile memory device chip, P-channel transistors M1, M2 are formed inside respective N type wells formed in a P type semiconductor substrate. A positive charge flows from the output terminal 0 of the charge pump toward ground, and nodes P1, P2, P3, P4 acquire negative potentials. Considering one of the stages, for example stage S2, when the respective phase signal C switches from VDD to ground the pass-transistor M1 turns on; at the same time, the pass-transistors M1 in the adjacent stages are turned off by the switching of phase signal A from ground to VDD. A positive charge flows from capacitor CL of stage S2 to capacitor CL of stage S1. In an ideal negative charge pump, the voltage at the output P1-P4 of a given stage is one VDD lower than the voltage at the output of the preceding stage (moving from Left to right in Figure 1); the higher the number of stages, the higher (in absolute value) the voltage at the output node 0. In the practice, however, since the P-channel pass-transistors M1 can have a rather high threshold voltage VTH due to the body effect, the voltage gain of each stage is limited to a value Lower than -VDD. The body effect is especially pronounced in the stages near the output terminal 0 of the charge pump, wherein the drain and the source electrodes of the P-channel pass-transistors M1 can be at potentials of approximately -10 V. In order to eliminate the problems of body effect, it would be necessary to bias the N type well wherein the P-channel pass-transistors M1 are formed at negative voltages. However, this is not possible, because the N type well/P type substrate junction would be forward biased. The provision of the pre-charge transistors M2 and of the capacitors CP partially reduces the body effect problem, because the gate electrodes of the pass-transistors M1 are boosted to obtain gate-to-source drive voltages higher in absolute value; to this purpose, a proper disoverlap between phase signals A, B, C and D is necessary, so that precharging of the gate electrode of the pass transistors M1 takes place at different time intervals with respect to the transfer of charge from one stage to another. However, also the boosting of the gate electrodes of the pass-transistors is not useful after a given number of stages. The reduced efficency of each stage makes it necessary to provide a higher number of stages (which are Less and less efficient), and the occupation of chip area and the power consumtion increase. Additionally, after a given number of stages, the gain of the subsequent stages becomes zero. Another possibility calls for increasing the voltage swing of phase signals A and C (which drive capacitors CP), which instead of varying between ground and VDD should vary between ground and, e.g., 2VDD. This solution complicates the design, because it would be necessary to provide a positive charge pump for generating the phase signals. In view of the state of the art described, it is an object of the present invention to provide a negative charge pump which is capable of eliminating the problems related to the body effect of the pass-transistors. According to the present invention, such an object is achieved by means of a charge pump comprising a plurality of stages connected in series between a reference potential and an output terminal of the charge pump, said plurality of stages comprises a first group of stages proximate to said reference potential, and a second group of stages proximate to said output terminal of the charge pump, each stage of said first group comprising a pass-transistor with first and second terminals respectively connected to an input and an output of the stage, and a first capacitor with a first plate connected to said output of the stage and a second plate driven by a digital signal switching between said reference voltage and a positive voltage, each stage of the second group comprising a junction diode having a first electrode connected to an input of the stage and a second electrode connected to an output of the stage, and a second capacitor having a first plate connected to said output of the stage and a second plate driven by a digital signal switching between said reference voltage and said voltage supply. Thanks to the fact that the junction diodes have a turn-on voltage which, differently from the threshold voltage of transistors, is not affected by body effect problems, the voltage gain of the stages in the second group of stages (proximate to the output of the charge pump, where body effect problems would be more evident) is not reduced. Thanks to this, the charge pump is more efficient, and a Lower number of stages is required compared to a conventional charge pump for generating a given output voltage. The features and advantages of the present invention will be made apparent by the following detailed description of a particular embodiment thereof, described as a non-limiting example in the annexed drawings, wherein: Figure 1 is a circuit diagram of a negative charge pump according to the prior art; Figure 2 is a timing diagram of drive signals of the charge pump of Figure 1; Figure 3 is a circuit diagram of a negative charge pump according to the present invention; and Figure 4 is a cross-sectional view of a diode of the charge pump of Figure 3. With reference to the drawings, figures 1 and 2 respectively show a negative charge pump according to the prior art, and a timing diagram of phase signals driving the negative charge pump. Figure 3 is a circuit diagram of a negative charge pump according to the present invention. The charge pump comprises a plurality of stages serially connected between an input terminal of the charge pump connected to ground and an output terminal 0 (four stages S1, S2, S3', S4' in this example). In a first group of stages, comprising stages which are proximate to the terminal of the charge pump connected to ground (stages S1 and S2 in the shown example), conventional stages identical to those of the charge pump of Figure 1 are used, and said stages are driven by phase signals A, B, C and D having the timing shown in Figure 2. In a second group of stages, comprising the stages which are proximate to the output terminal 0 of the charge pump (stages S3' and S4' in the shown example) the stages are instead different in structure: stages S3' and S4' comprise each a junction diode D with cathode connected to the output of the preceding stage and anode connected to the input of the following stage (i.e., to the cathode of diode D in the following stage), and a capacitor CL' with one plate connected to the anode of diode D and the other plate driven by a respective phase signal B' and D'. Phase signals B' and D' are digital signals periodically switching between ground and a positive voltage supply, for example the voltage supply VDD of the chip wherein the charge pump is integrated; signal D' is in phase opposition with respect to signal B'. Signals B' and D' can be for example respectively identical to signals B and D. With respect to the conventional charge pump shown in Figure 1, the P-channel pass-transistors M1 in the final stages of the charge pump have been replaced by junction diodes D. The voltage gain of one of stages S3', S4' is equal to -VDD+VD, where VD is the turn-on voltage of diodes D. Since the turn-on voltage VD of a junction diode can be made lower than the threshold voltage VTH of the P-channel pass-transistors, and since the turn-on voltage VD of the junction diodes is not affected by problems of body effect, the negative charge pump of Figure 3 is more efficient than the conventional one. Furthermore, it is possible to obtain negative output voltages which, in absolute value, are as high as desired, because for each stage like S3' or S4' added to the charge pump, an increase of |-VDD+VD| in (absolute value of) the output voltage can be achieved. The stages which, like S1 and S2, are proximate to the input terminal of the charge pump coupled to ground are preferably of the type comprising P-channel pass-transistors and precharge transistors M2 instead of the type comprising junction diodes; in fact, in these stages the body effect on the threshold voltage VTH of the pass-transistor M1 is still small, and the boosting of the gate electrode of the pass-transistors by means of M2 and CP is sufficient for obtaining a voltage gain equal to VDD (i.e., higher than that obtainable by means of a stage with a junction diode). Another advantage of the charge pump of Figure 3 resides in that stages S3' and S4' only comprise one capacitor each, i.e. the boosting capacitor CP is absent. In such stages it is not necessary to provide a precharge phase, so that capacitors CL can be driven by phase signals B' and D' with a higher clock rate than that of phase signals B and D driving stages S1 and S2; in this way, it is possible to increase the rate of transfer of charge between the stages, so as to compensate the loss of gain due to the voltage drop across diodes D (diode turn-on voltage VD). Figure 4 shows in cross-section a possible embodiment of the diodes D, particularly suitable in view of the integration of the charge pump in CMOS integrated devices, such as non-volatile memories. In a P type substrate 1 which represents a common substrate of the chip, an N type well 2 is formed. Inside the N type well 2, a P type well 3 is formed, and an N+ doped region 4 is formed inside the P type well 3. Region 4 forms the cathode KA of the diode, while the P type well 3 forms the anode AN. The N type well 2 is kept biased at VDD (i.e., the more positive voltage inside the chip), while the substrate 1 is conventionally kept grounded. In this way, the P type well 3 is isolated from the P type substrate 1. This structure requires for its manufacturing a so-called "triple-well" process. From the structure of Figure 4, it is possible to appreciate that the maximum number of stages of the charge pump, i.e. the maximum negative voltage which can be generated at the output of the charge pump, is limited by the breakdown voltage of the junction between the N region 2 and the P type well 3, which is very high.

Claims: Charge pump comprising a plurality of stages (S1,S2,S3',S4') connected in series between a reference potential and an output terminal (0) of the charge pump, said plurality of stages comprises a first group of stages (S1,S2), proximate to said reference potential, and a second group of stages (S3',S4') proximate to said output terminal of the charge pump, each stage of said first group comprising a pass-transistor (M1) with first and second terminals respectively connected to an input and an output of the stage, and a first capacitor (CL) with a first plate connected to said output of the stage and a second plate driven by a digital signal (B,D) switching between said reference voltage and a positive voltage (VDD), characterized in that each stage of the second group comprising a junction diode (D) having a first electrode connected to an input of the stage and a second electrode connected to an output of the stage, and a second capacitor (CL') having a first plate connected to said output of the stage and a second plate driven by a digital signal (B',D') switching between said reference voltage and said voltage supply. Charge pump according to claim 1, characterized in that each stage of said first group of stages (S1,S2) further comprises a precharge transistor (M2) with a first terminal connected to the input of the stage, a second terminal connected to a control electrode of the pass-transistor (M1) and a control terminal connected to the output of the stage, and a second capacitor (CP) with a first plate connected to the control electrode of the pass-transistor, and a second plate driven by a pre-charge digital signal (A,B) switching between the reference voltage and the voltage supply (VDD). Charge pump according to claim 2, characterized in that each of said junction diodes (D) has a first electrode (KA) formed by a doped region (4) of a first conductivity type and a second electrode (AN) formed by a first well region (3) of a second conductivity type containing said doped region (4), the first well region (3) being in turn formed inside a respective second well region (2) of the first conductivity type formed in a semiconductor substrate of the second conductivity type. Charge pump according to claim 3, characterized in that said first conductivity type is the N type and said second conductivity type is the P type. Charge pump according to claim 4, characterized in that said pass-transistor (M1) and said precharge transistor (M2) are P-channel MOSFETs.

Inventors: BRANCHETTI MAURIZIO, GHILARDELLI ANDREA, MULATTI JACOPO, BRANCHETTI, MAURIZIO, GHILARDELLI, ANDREA, MULATTI, JACOPO
Applicants: ST MICROELECTRONICS SRL, STMICROELECTRONICS S.R.L.
Application year: 1996
Main classification: H02M3
IPC codes: H01L21, H01L27, H01L29, H02M3