Solid-state image sensing device with common output line

Abstract: A solid-state image sensing device has an inverting-amplifier constructed with MOS transistors (3,6), which is provided with electrical power through a common output line (7), and inputs and outputs signals through the common output line. With this configuration, a supply line used exclusively for supplying electrical power does not pass through a pixel (1) of a solid-state image sensing device. The inverting-amplifier of this solid-state image sensing device is reset to the same voltage as that of the common output line, and an offset voltage is read out. Thereafter, the electric charge inputted into the inverting-amplifier from a photo-electric converter is inverted and amplified, and the resultant signal is read out. Finally, a difference between the inverted and amplified signal and the offset voltage is obtained and outputted as an image signal.

Description: BACKGROUND OF THE INVENTION The present invention relates to an inverting-amplification type solid-state image sensing device using MOS transistors. A conventional solid-state image sensing device is used as a line sensor for an image scanner and an area sensor for an 8 mm video camera, for example. As an image processing device improves, a solid-state image sensing device having a sensor cell of higher precision and better sensitivity is demanded. Further, in order to read out electrical signals corresponding to the intensity of incoming light more accurately, it is necessary to remove noises from the signals as they are transmitted. A conventional solid-state image sensing device is mainly configured with a photo-sensing surface constructed by using large numbers of photodiodes, a scanning circuit for scanning an image on the photo-sensing surface to obtain image signals, and a switch for connecting the photo-sensing surface and the scanning circuit. As for a solid-state image sensing device using photodiodes, there are two types, so called a MOS type and a CCD type. Here, a word "MOS" is an abbreviation for "Metal-Oxide-Semiconductor". The both types of solid-state image sensing devices actually use MOS transistors, and the former type is precisely a MOS FET type and the latter type is a MOS CCD type. Photo-electrons stored in a MOS FET photodiode are read out to a scanning circuit by using MOS transistors, then outputted. Eric R. Fossum et al. suggested in 1993 IEDM P. 583 an example of a solid-state image sensing apparatus having a structure such that a photo-electric charge was stored in a gate of a MOS transistor and a signal corresponding to the charge was read out from the MOS transistor which is connected as a source follower. According to Fossum et al., since an offset output read out after resetting each pixel can be subtracted from a signal carrying an image signal which is added to a reset gate, it is possible to obtain an image signal which contains neither fixed-pattern noise which represents unevenness in output from each pixel nor random noise that is a kTC noise generated during resetting of each pixel. However, according to the aforesaid example, a single pixel is configured with a photodiode and four MOS transistors, and a power-supply line and a ground line pass through the pixel. Therefore, there are problems in which, upon manufacturing a high-density pixels, an aperture area must be extremely small to make the size of each pixel small, or it is even impossible to make a pixel of an extremely reduced size by manufacturing it in miniaturization processes. Further, since a gate of a MOS transistor which is connected as a source follower is reset to a voltage of a power supply, the High level of a pulse used for resetting a pixel has to have a higher voltage than that of the power supply. Consequently, a pulse having a large voltage difference between the High level and the Low level is necessary. Furthermore, the ratio of a signal outputted from the source of the source follower to a signal inputted to its gate is not greater than 1 and when a signal stored in a capacitor for storing an offset output and a signal stored in a capacitor for storing a total signal of an image signal plus a reset voltage are transmitted to a differential amplifier where one signal is subtracted from the other, the voltages of the signals drop. Accordingly, there is a problem in which S/N ratio tends to drop because of noises on the output lines and the differential amplifier. Thus, a processing circuit for differentiating signals produces noise. Furthermore, if memory means for storing noise component signal and a signal including an image signal component are used, the memory means also produces noises. The present invention has been made in consideration of the above situation, and has as its object to provide a solid-state image sensing device capable of outputting a final signal of large S/N ratio by outputting the signal from a pixel with an inverting amplifier. It is another object of the present invention to provide a solid-state image sensing device, having an inverting-amplification structure, capable of removing noise components and outputting an image signal in high S/N ratio and a method of controlling the solid-state image sensing device. A solid-state image sensing device of the type considered herein, such as known from United States Patent US-A-5354980, comprises: a plurality of pixels, each of which includes: photoelectric conversion means for converting incoming light into an electric signal; a first transistor arranged to receive, at an input terminal, the electric signal from said photoelectric conversion means and to output an amplified signal corresponding to the received electric signal; and a second transistor for selecting one of said plurality of pixels from which a signal of said first transistor thereof is to be outputted; and an output line arranged for receiving and outputting respective output signals from said first transistors included in respective ones of a plurality of said plurality of pixels. The solid-state image sensing device of the present invention is characterised in that each of said plurality of pixels further includes: a third transistor which bypasses said second transistor and is connected between the input terminal of said first transistor and said output line, and is arranged to reset the input terminal of said first transistor to the potential of said output line when said third transistor is turned on, wherein said first transistor is arranged to inverse-amplify the electric signal from said photoelectric conversion means and to output the inverse-amplified signal to said output line, and said second transistor is connected in series with said first transistor. Such a solid state image sensing device may be used in combination with a transfer unit and a memory cell unit and controlled to output an image signal by either method defined in claims 15 and 16 appended hereto. Other features and advantages of the present invention will be apparent from the following description taken in conjunction with the accompanying drawings, in which like reference characters designate the same or similar parts throughout the figures thereof. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. Fig. 1 is a circuit diagram of a solid-state image sensing device according to a first embodiment of the present invention; Fig. 2 is a timing chart for explaining a method of controlling the solid-state image sensing device of the present invention; Fig. 3 is a graph showing input-output characteristic of an inverting amplifier for explaining a reset voltage of a pixel of the present invention; Fig. 4 is a circuit diagram of a solid-state image sensing device according to a second embodiment of the present invention; Fig. 5 is a timing chart for showing an operation of the solid-state image sensing device according to the second embodiment; Fig. 6 is an explanatory view showing a flow of signals according to the second embodiment of the present invention; Fig. 7 is a circuit diagram of a solid-state image sensing device according to a third embodiment of the present invention; Fig. 8 is a timing chart of pulses showing an operation of the solid-state image sensing device according to the third embodiment; and Fig. 9 is an explanatory view showing a flow of signals according to the third embodiment of the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described in detail in accordance with the accompanying drawings. <First Embodiment> Fig. 1 is an equivalent circuit diagram of a solid-state image sensing device of a first embodiment including a pixel and its peripherals. In Fig. 1, reference numeral 1 denotes a unit pixel; 2, a photodiode; 3, a MOS transistor which receives photo-electric charge from the photodiode 2 in the gate and outputs a signal from the drain; 4, a MOS transistor for transferring a signal charge from the photodiode 2 to the gate of the MOS transistor 3; 5, a MOS transistor used for resetting a voltage at the gate of the MOS transistor 3 to the voltage of an output line 7; and 6, a MOS transistor for selecting and scanning a pixel to be outputted. The aforesaid photodiode 2, the MOS transistors 3, 4, 5, and 6 configure the pixel 1. Further, in Fig. 1, reference numeral 7 denotes a vertical output line (referred as "output line", hereinafter) and reference numeral 8 denotes a MOS transistor which forms an inverting amplifier together with the MOS transistor 3. The drain and gate of the MOS transistor 8 are connected to a power supply voltage source, and the source is connected to the output line 7. Further, reference numeral 9 denotes a capacitor which is charged to an offset voltage of a pixel; 10, a capacitor which is charged to a voltage of an image signal component (referred as "true image signal", hereinafter), which corresponds to an amplified photo-electric charge, plus an offset voltage (the total signal is referred as "image signal", hereinafter) from the pixel; 11, a MOS transistor for transferring the offset output; 12, a MOS transistor for transferring the image signal; 13 and 14, MOS transistors for transferring charges stored in the capacitors 9 and 10 to horizontal output lines 15 and 16, respectively; 17 a differential amplifier for subtracting the offset signal from the image signal; and 18, an output terminal of the differential amplifier 17. Further, TX, R, S, T1 and T2 denote control pulses fed to the gates of the MOS transistors 4, 5, 6, 11 and 12, respectively, and H is a control pulse fed to the gates of the MOS transistors 13 and 14. V DD denotes the voltage of the power supply. The circuit shown in Fig. 1 is a simplified circuit illustration of the solid-state image sensing device, and a plurality of sets of the elements denoted by reference numerals 7, 8, 9, 10, 11, 12, 13, 14 are arranged in parallel, and a plurality of pixels such as the pixel 1 connect to each output line in parallel. In the aforesaid manner, several hundred-thousands of pixels are arranged in both the vertical and horizontal directions. Fig. 3 is a graph showing an input-output characteristic of the inverting amplifier configured with the MOS transistors 3 and 8. A voltage at the gate of the MOS transistor 3 is reset through the MOS transistor 5, and specifically, it is set at a voltage where an input voltage of the inverting amplifier equals to the output voltage of itself (reset voltage). An operation of the solid-state image sensing device according to the first embodiment will be described below. The solid-state image sensing device shown in Fig. 1 is driven at the pulse timing shown in Fig. 2. First, the control pulse S becomes High and a pixel from which a signal is to be outputted is selected. Then, the control pulse R becomes High and the MOS transistor 5 turns ON, thereby the gate of the MOS transistor 3 is reset to the voltage of the output line 7. At the same time, the control pulse T1 becomes High and the MOS transistor 11 turns ON. After the pulse R becomes Low, the capacitor 9 is charged to an offset voltage corresponding to the reset voltage applied on the gate of the transistor 3 through the output line 7. Next, the control pulse T1 becomes Low, thereby completing a reset process. Thereafter, the control pulse TX becomes High to turn the MOS transistor 4 ON, and photo-electric charge converted by the photodiode 2 is transferred to the gate of the MOS transistor 3. Since the control pulse S is kept High, the voltage at the drain of the MOS transistor 3 changes depending upon the photo-electric charge applied to the gate. Since the MOS transistor 8 connected to the output line 7 and the power supply voltage source V DD configures a pull-up power source, the MOS transistor 3 performs as if it amplifies the gate voltage (note, the proportional constant is negative in the range where the input voltage and the output voltage of the MOS transistor 3 has a proportional relationship) and outputs the amplified signal to the output line 7. As a result, a voltage representing the sum of the offset voltage and the amplified voltage of the photo-electric charge applied to the gate (i.e., an image signal) appears on the output line 7. At the same time, the control pulse T2 becomes High to turn on the MOS transistor 12, thus the capacitor 10 is charged to the sum voltage. Thereafter, the control pulse S becomes Low, the MOS transistor 6 turns OFF. Then, the control pulse H becomes High, the MOS transistors 13 and 14 turn ON, and the charge stored in the capacitor 9 in accordance with the offset voltage and the charge stored in the capacitor 10 in accordance with the image signal (sum voltage) are outputted to the horizontal output lines 15 and 16. Then, the difference between the voltages on the output lines 15 and 16 is taken and amplified, thus the offset voltage is canceled. Finally, a true image signal which is the amplified photo-electric charge is outputted from the output terminal 18. In the first embodiment of the present invention, the change in output voltage at the drain of the MOS transistor 3 from the reset voltage to the voltage obtained after the photo-electric charge, applied to the gate of the MOS transistor 3, is negative, and the polarity of the output signal is opposite to the polarity of the input signal, namely the output signal is negative, differing from an output from a conventional solid-state image sensing device. However, since the gain of the pixel can be greater than 1., it is possible to reduce the drop of the S/N ratio of the image signal output from the MOS transistor to noises originated by circuits, such as the differential amplifier. Furthermore, it is unnecessary to set the High level of the driving pulses to higher than the voltage of the power supply. Therefore, it is possible to realise a solid-state image sensing device of low-voltage driving type by configuring with the MOS transistors having low-voltage driving structures. Further, since the power supply line (at voltage V DD ) does not run through a pixel, which is different from a conventional solid-state image sensing device, difficulty in designing fine pixels is reduced. Since it is possible to widen an aperture area comparing to the conventional solid-state image sensing device, it is also possible to increase the S/N ratio with the wider aperture area, thereby obtaining an image signal of high quality. In the first embodiment as described above, an operation of a pixel which outputs photo-electric charge from a photodiode is explained. However, a plurality of pixels are arranged in line, in practice, when configuring a line sensor, and each vertical output line of each pixel is scanned sequentially to obtain image signal of a single line. Further, when configuring an area sensor, a plurality of pixels are arranged both vertically and horizontally, and each horizontal line and each vertical line are scanned sequentially to obtain image signals of a two dimensional image. According to the first embodiment of the present invention as described above, an output from a pixel is obtained from the drain of a MOS transistor which configures a part of an inverting amplifier capable of outputting a signal which is inputted to the drain of the MOS transistor. Accordingly, it is possible to obtain the output in higher voltage level comparing to the conventional image sensing device, therefore it is effective to prevent drop of the S/N ratio. Furthermore, since the power supply line does not pass through a pixel as well as the number of MOS transistors used in a pixel is reduced, it becomes easier to manufacture a solid-state image sensing device with finer pixels with wide aperture. As a result, the S/N ratio increases. <Second Embodiment> In the second embodiment, a solid-state image sensing device having an inverting amplifier, such as the one explained in the first embodiment, and a method of controlling the solid-state image sensing device capable of removing noises, such as noise from a differential amplifier, and outputting a true image signal, corresponding to a photo-electric charge, containing less noises is described. Fig. 4 is an equivalent circuit diagram of a solid-state image sensing device according to the second embodiment, and Fig. 5 is a timing chart showing timing for operating the solid-state image sensing device. Note, Fig. 4 shows an example having a sensor cell unit, a transfer unit and a memory cell unit, however, a plurality of each of these units can be provided. Further, only one common output line is shown in Fig. 4 for the sake of simplicity. Referring to Fig. 4, a sensor cell unit includes a photodiode D and n channel MOS transistors M 11 to M 13 , and outputs an inverted signal (gain is -1). An n channel MOS transistor M 14 for applying a predetermined voltage to the sensor cell unit and an n channel MOS transistor M 15 for applying a reset voltage V RS are connected to the common output line L. The MOS transistors M 11 , M 12 , M 14 , M 15 turn ON and OFF in accordance with control pulses PS1, SL1, L1 and RS, respectively. In the sensor cell unit, the MOS transistor M 11 and the MOS transistor M 15 are turned ON, first, and charges remained in the photodiode D and the gate of the MOS transistor M 13 are reset. Next, the MOS transistor M 11 and the MOS transistor M 15 are turned OFF, and the MOS transistor M 12 and the MOS transistor M 14 are turned ON, and noise (offset voltage) is read out. Then, photo-electric charge is stored in the photodiode D and the gate of the MOS transistor M 13 , thereafter, a current corresponding to the charge stored in the gate of the MOS transistor M 13 flows and an image signal is read out. The transfer unit has n channel MOS transistor 24 which controls to conduct to the common output line L or not, a capacitor C T connected to the common output line L (a terminal of the capacitor C T connected to the common output line L is called "terminal A", hereinafter), a p channel MOS transistor M 23 connected to the terminal of the capacitor C T other than the terminal A (this terminal is called "terminal B", hereinafter), n channel MOS transistors M 21 and M 22 as an amplifier (a MOS type source follower in the third embodiment) for outputting a signal in response to the voltage at the terminal B of the capacitor C T , and n channel transistor M 25 for controlling signal transfer to the memory cell unit. A fixed voltage V G is applied to the n channel MOS transistor M 22 , and the MOS transistors M 23 , M 24 , and M 25 are turned ON and OFF in response to control pulses GR, FB and FT, respectively. In the transfer unit, voltages at terminals A and B of the capacitor C T are controlled to perform operations, such as inverting operation and addition, on an input signal. The configuration of the memory cell unit is the same as that of the sensor cell unit except the photodiode D in the sensor cell unit which is replaced with a capacitor C S in the memory cell. More specifically, the memory cell unit has the capacitor C S , n channel MOS transistors M 31 , M 32 and M 33 , and outputs an inverted signal (gain is -1) . Further, an n channel MOS transistor M 34 is provided in the common output line L for applying a predetermined voltage to the memory cell unit . The MOS transistors M 31 , M 32 and M 34 turn ON and OFF in response to control pulses PS2, SL2 and L2, respectively. The memory cell unit reads a stored signal and is reset in the same manner as the sensor cell unit operates. An image signal read from the memory cell unit is selected by a shift register or a decoder, and outputted to an output line. Flow of a signal upon operating the aforesaid solid-state image sensing device will be briefly described with reference to Fig. 6. Note, periods referred by (S1) to (S6) in the timing chart of Fig. 5 correspond to the following operations referred by (S1) to (S6). (S1) Noise N S of the sensor cell unit (referred as "sensor cell noise", hereinafter) is read out just after resetting the sensor cell, and transferred to the transfer unit. (S2) The sensor cell noise N S is inverted in the transfer unit, then noise N T of the transfer unit (referred as "transfer noises", hereinafter) is added and the total noise, (-N S + N T ), and inputted to the memory cell unit. (S3) After storing photo-electric converted charge, an inverted signal (sensor signal), -S, outputted in correspondence with the stored charge is added to the sensor cell noise N S , then a signal (-S + N S ) is outputted to the transfer unit. In the transfer unit, the input signal is inverted to (S - N S ) and stored. (S4) The noise (-N S + N T ) inputted to the memory cell unit is inverted to (N S - N T ), and noise of the memory cell unit (referred as "memory cell noise", hereinafter) is added, then the total noise (N S - N T + N M ) is outputted to the transfer unit. In the transfer unit, the noise (N S - N T + N M ) is added to the signal (S - N S ), thus the total signal becomes (S - N T + N M ). (S5) The transfer noise N T is added to the signal (S - N T + N M ), then the resultant signal (S + N M ) is inputted to the memory cell. (S6) The memory cell noise N M is added to the inverse of the input signal (S + N M ), namely, (-S - N M ). As a result, the sensor signal -S is outputted. Next, the above operations (S1) to (S6) are explained in more detail with reference to Figs. 4 and 5. First, the control pulses RS and PS1 become High to reset the sensor cell unit. Next, after the control pulse PS1 becomes Low, the control pulses GR, FT and PS2 become High. At this time, the voltage at the terminal A of the capacitor C T is set to V RS , and the voltage at the terminal B of the capacitor C T is set to V GR . Then, after the control pulse RS becomes Low, the control pulses SL1 and L1 become High, thus the sensor cell noise N S after the reset operation is outputted from the sensor cell unit to the common output line L (The sensor cell noise is read out as N S , thereby the voltage of the common output line L becomes V RS + N S , in this case). Thereafter, the control pulse GR becomes Low, to make the terminal B of the capacitor C T floating. Then, the control pulse RS becomes High, and the voltage of the common output line L changes to V RS . Since the change of voltage at the terminal A of the capacitor C T is -N S , the voltage at the terminal B of the capacitor C T also changes from the V GR by -N S . As a result, an inverted sensor cell noise -N S is transferred to the memory cell unit. However, since the transfer noise N T is added to the inverted sensor cell noise -N S , the total noise (-N S + N T ) is inputted to the memory cell unit as a result. The above operation corresponds to (S1) and (S2). After photo-electric charge is stored in the sensor cell unit (the common output line L is reset to the voltage V RS at this time), the control pulse GR becomes High, and the voltage at the terminal B of the capacitor C T becomes V GR . When the control pulses SL1 and L1 become High, a signal (-S + N S ), which is the sensor signal -S added with a sensor cell noise N S , is read out from the sensor cell unit. Thereby, the voltage of the common output line changes from the V RS to V RS + (-S + N S ). Further, the control pulse GR becomes Low to make the terminal B of the capacitor C T floating. Next, the control pulse RS becomes High. The voltage at the terminal A of the capacitor C T of the transfer unit becomes V RS accordingly, and is changed by - (-S + N S ). As a result, the voltage at the terminal B changes by the same amount -(-S + N S ), thus the voltage becomes V GR -(-S + N S ). Thereafter, the control pulse RS becomes Low. The above operation corresponds to (S3). Next, the control pulses FB, SL2 and L2 become High, and the noise (-N S + N T ) stored in the memory cell unit is inverted to the signal (N S - N T ), then the memory cell noise N M is added to it, and the total noise (N S - N T + N M ) is outputted from the memory cell unit to the terminal A of the capacitor C T of the transfer unit. Upon transferring the signal (N S - N T + N M ), the voltage at the terminal A of the capacitor C T of the transfer unit changes by (N S - N T + N M ), thereby the voltage at the terminal B of the capacitor C T also changes by the same amount. As a result, the voltage at the terminal B of the capacitor C T becomes V GR - (-S + N S ) + (N S - N T + N M ) = V GR + S - N T + N M . This is the aforesaid operation (S4). Next, the control pulses FT and PS2 become High, and the signal (S - N T + N M ) is transmitted from the transfer unit to the memory cell unit. Upon transferring the signal (S - N T + N M ), since the transfer noise N T is added to the signal, a signal (S + N M ) is inputted to the memory cell unit. This is the operation (S5). Thereafter, the control pulses SL2 and L2 become High, and the inverse of the input signal (S + N M ) is read out from the memory cell unit. Upon reading the signal, the memory cell noise N M is added to the inverted signal (-S - N M ) of the input signal (S + N M ). Consequently, the sensor signal -S without noise components is outputted. This is the operation (S6). According to the second embodiment as described above, not only fixed pattern noises of a sensor but also random noises which changes in each reset operation of the sensor can be removed, thereby outputting a signal in high S/N ratio. <Third Embodiment> The third embodiment provides a solid-state image sensing device having an inverting amplifier, such as the one explained in the second embodiment, and also a method capable of removing noise components from an image signal outputted from memory cells and a signal outputted from sensor cells during a charge storage period, which is used for controlling the charge storage period. Fig. 7 is an equivalent circuit diagram of a solid-state image sensing device according to the third embodiment, and Fig. 8 is a timing chart showing timing of operating the solid-state image sensing device. Note, Fig. 7 shows an example having a sensor cell unit, a transfer unit and a memory cell unit, however, a plurality of each of these units may be provided. Further, only one common output line is shown in Fig. 7 for the sake of simplicity. As shown in Fig. 7, a circuit configuration of the fourth embodiment is that an n channel MOS transistor M 26 for controlling signal transmission to the sensor cell unit and an n channel MOS transistor M 27 for controlling signal transmission from the sensor cell unit to the capacitor C T are added to the transfer unit shown in Fig. 4. The configurations of the other parts of the transfer unit, the sensor cell unit and the memory cell unit are the same as those of the solid-state image sensing device shown in Fig. 4. Note, the n channel MOS transistors, M 24 , M 25 , M 26 and M 27 turn ON and OFF in response to control pulses FB2, FT2, FT1 and FB1, respectively. In the following, a flow of a signal upon operating the aforesaid solid-state image sensing device will be briefly described with reference to Fig. 9. Note, periods referred by (S11) to (S110) in the timing chart of Fig. 8 correspond to the following operations referred by (S11) to (S110). (S11) Noise N S of the sensor cell unit (sensor cell noise) is read out, and sent to the transfer unit. (S12) The noise N T of the transfer unit (transfer noise) is added and the total noise (N S + N T ) is inputted to the sensor cell unit. (S13) In the sensor cell unit, the sensor cell noise N S is added to an inverse of the input signal, -(N S + N T ), then the noise -N T is sent to the transfer unit. (S14) In the transfer unit, the input signal -N T is inverted, and the transfer noise N T is added to it, then the sum of the noises, 2N T , is sent to the memory cell unit. (S15) The sensor cell unit is then in the photo-electric charge storage period (the noise N S + N T still remains in the sensor cell unit), and an inverted signal, -S 1 , corresponding to the stored charge in the sensor cell unit (first sensor signal) is read out in the middle of the photo-electric charge storage period. The first sensor signal -S 1 and the inverse of the remaining noise (N S + N T ) and the sensor cell noise N S are added. Consequently, the signal (-S 1 - N T ) is sent to the transfer unit. (S16) In the transfer unit, the noise N T is added to the input signal (-S 1 - N T ) and the resultant signal becomes -S 1 , and this signal -S 1 is outputted as an image signal obtained during the photo-electric charge storage operation. This signal can be used for determining a charge storage period for a cell in an automatic focus sensor, for example. (S17) In the sensor cell unit, photo-electric charge is further stored, and an inverted signal, -S 2 , (second sensor signal) corresponding to the stored charge in the sensor cell unit is read out after the photo-electric charge storage period. The second sensor signal -S 2 and the inverse of the remaining noise (N S + N T ) and the sensor cell noise N S is added, and sent to the transfer unit. The output signal here is (-S 2 - N T ). (S18) The noise N M of the memory cell unit (memory cell noise) is added to the inverse of the input signal -2N T , then the total noise (-2N T + N M ) is transferred to the transfer unit. (S19) In the transfer unit, the signal (-S 2 - N T ) is subtracted from the total noise (-2N T + N M ), and the transfer noise N T is added to the difference. Accordingly, the resultant signal (S 2 + N M ) is inputted to the memory cell unit. (S110) The memory cell noise N M is added to the inverse of the input signal (S 2 + N M ), namely, (-S 2 - N M ). As a result, the second sensor signal - S 2 is outputted. This signal is an image signal. Next, the above operations (S11) to (S110) are explained in more detail with reference to Figs. 8 and 9. First, the control pulses RS and PS1 become High to reset the sensor cell unit. Next, after the control pulse PS1 becomes Low, the control pulse GR becomes High. At this time, FB1 and PB2 are kept High. Under this condition, the voltage at the terminal A of the capacitor C T is set to V RS , and the voltage at the terminal B of the capacitor C T is set to V GR . Then, after the control pulses GR and RS become Low, the control pulses SL1 and L1 become High, thereby noise of the sensor cell after the reset operation is outputted from the sensor cell unit to the common output line L (The sensor cell noise is read out as N S in this case). The above operation corresponds to (S11). Since the voltage of the common output line L changes by N S , the voltage at the terminal B of the capacitor C T also changes by N S when it is floated. Thereafter, the control pulses FB1, SL1 and L1 become Low, the control pulse FT1 becomes High, then the control pulse PS1 becomes High, and the sensor cell noise N S is transferred from the transfer unit to the sensor cell unit. Upon transferring the sensor cell noise N S , the transfer noise N T is added to it, thus the total noise (N S + N T ) is inputted to the sensor cell unit as a result. The above operation corresponds to (S12). Next, the control pulses FB1 and FT2 become High, then the control pulses GR, SL1 and L1 become High, the inverse of the total noise signal (N S + N T ), namely - (N S + N T ), is outputted from the sensor cell to the transfer unit. Upon outputting the total noise, the sensor cell noise N S of the sensor cell is added, thus the noise -N T is actually inputted to the transfer unit. Under this condition, the voltage at the terminal A of the capacitor C T in the transfer unit changes by -N T while the voltage at the terminal B of the capacitor C T is fixed to V GR . Further, the control pulse GR becomes Low to make the terminal B of the capacitor C T is floated. The above operation corresponds to (S13). Next, the control pulse GR becomes low to make the terminal B of the capacitor C T floating and the control pulses RS and PS2 become High, the voltage at the terminal A of the capacitor C T becomes V RS , namely the voltage changes by N T . Accordingly, the terminal B of the capacitor C T also changes by N T , thereby the signal N T is transmitted to the memory cell unit. However, since the transfer noise N T is added to it, the total noise 2N T is actually inputted to the memory cell unit. This operation corresponds to (S14). Thereafter, the sensor cell unit starts storing photo-electric charge, and a signal corresponding to photo-electric charge stored in the sensor cell unit is outputted in the following manner during photo-electric charge storage operation. First, the control pulse GR becomes High (at this time, the control pulse RS is kept High), the voltage at the terminal A of the capacitor C T becomes V RS and the voltage at the terminal B of the capacitor C T becomes V GR . Thereafter, the control pulse GR becomes Low to make the terminal B of the capacitor C T floating. Then, when the control pulses SL1 and L1 become High, a signal (-S 1 - N T ), which is a first sensor signal -S 1 plus the inverted remaining noise (N S + N T ) plus the sensor cell noise N S , is sent from the sensor cell unit to the transfer unit. This operation corresponds to (S15). Since the voltage at the terminal A of the capacitor C T of the transfer unit changes by (-S 1 - N T ), the voltage at the terminal B of the capacitor C T also changes by the same amount and becomes V GR + (-S 1 - N T ). When this signal is transferred from the transfer unit, the transfer noise N T is added to it, thereby the first sensor signal -S 1 is outputted from an OUT2 terminal of the transfer unit. This operation corresponds to (S16). Next, the sensor cell unit further stores photo-electric charge. When the control pulses SL1, L1, GR and FB2 become High after completing the photo-electric charge storage operation, the voltage at the terminal B of the capacitor C T is fixed at V GR , and the voltage at the terminal A of the capacitor C T changes by (-S 2 - N T ) from V RS . Note, the signal (-S 2 - N T ) is that a second sensor signal -S 2 plus the inverted remaining noise (N S + N T ) plus the sensor cell noise N S . This corresponds to (S17). When the control pulses SL2 and L2 become High, a signal (-2N T + N M ), which is an inverted noise -2N T plus the memory cell noise N M , is sent to the terminal A of the capacitor C T of the transfer unit (at this time, the terminal B of the capacitor C T of the transfer unit is floating). This operation corresponds to (S18). Accordingly, the voltage at the terminal A of the capacitor C T becomes - (-S 2 - N T ) + (-2N T + N M ) = S 2 - N T + N M . As a result, the voltage at the terminal B of the capacitor C T also changes by (S 2 - N T + N M ). When the control pulses FT2 and PS2 become High, this signal (S 2 - N T + N M ) is transferred from the transfer unit to the memory cell unit. At this time, the transfer noise N T is added to it, thereby a signal (S 2 + N M ) is actually inputted to the memory cell unit. This operation corresponds to (S19). Thereafter, the control pulses SL2 and L2 become High, then a signal is read out from the memory cell unit. Upon reading the signal, the memory cell noise N M is added to the inverted input signal (-S 2 - N M ). Consequently, the second sensor signal -S 2 without noise components is outputted. This is the operation (S110). According to the third embodiment as described above, random noise which is added in the reset operation is removed in operation (S19), thereby it is possible to output a signal -S 2 in high S/N ratio having no sensor random noise. According to the third embodiment as described above, it is possible to remove noise components generated in the sensor cell unit, the memory cell unit and the transfer unit, thereby outputting a signal -S 2 in high S/N ratio. Further, according to the second and third embodiments, a solid-state image sensing device can be configured with transistors, thereby it is possible to provide an inexpensive solid-state image sensing device manufactured by using a simple manufacturing process. As many apparently widely different embodiments of the present invention can be made without departing from the scope thereof, it is to be understood that the invention is not limited to the specific embodiments thereof except as defined in the appended claims.

Claims: A solid-state image sensing device comprising: a plurality of pixels (1), each of which includes: photoelectric conversion means (2, D), for converting incoming light into an electric signal; a first transistor (3, M 13 ) arranged to receive, at an input terminal, the electric signal from said photoelectric conversion means and to output an amplified signal corresponding to the received electric signal; and a second transistor (6, M 12 ) for selecting one of said plurality of pixels from which a signal of said first transistor thereof is to be outputted, and an output line (7, L) arranged for receiving and outputting respective output signals from respective ones of said first transistors included in respective ones of a plurality of said plurality of pixels, characterised in that each of said plurality of pixels further includes: a third transistor (5, M 11 ) which bypasses said second transistor and is connected between the input terminal of said first transistor and said output line, and is arranged to reset the input terminal of said first transistor to the potential of said output line when said third transistor is turned on, wherein said first transistor is arranged to inverse-amplify the electric signal from said photoelectric conversion means and to output the inverse-amplified signal to said output line, and said second transistor is connected in series with said first transistor. A solid-state image sensing device according to claim 1, further comprising a fourth transistor (8, M 14 ) which forms an inverting-amplification means together with said first transistor and acts as a load of said inverting-amplification means, wherein said fourth transistor is commonly provided for all the first transistors included in said plurality of pixels that are connected to said output line. A solid-state image sensing device according to either one of claims 1 or 2, wherein said third transistor (5, M 11 ) is arranged to apply a reset level to the input terminal of said first transistor, and further comprising noise removal means (9, 10, 17, M 21 to M 25 , C T , M 31 to M 34 , C S ) for removing a noise component included in an electric signal from said photoelectric conversion means outputted via said first transistor using a signal outputted from said first transistor when the reset level is applied. A solid-state image sensing device according to claim 3, including control means for controlling said second and third transistors, wherein said control means is arranged to cause the input terminal of said first transistor to be reset to the reset level before performing inverse-amplification on the electric signal from said photoelectric conversion means. A solid-state image sensing device according to claim 3, wherein said noise removal means includes: a first storage means (9) for storing a signal outputted from said first transistor when the input terminal of said first transistor is reset to the reset level; a second storage means (10) for storing the inverse-amplified signal, outputted from said first transistor, corresponding to the electric signal from said photoelectric conversion means; and a differential means (17) for outputting a difference between the signal stored in said first storage means and the signal stored in said second storage means. A solid-state image sensing device according to claim 3, wherein said noise removal means includes: memory means having: a capacitor (C S ) for accumulating a signal; and a fifth transistor (M 33 ) for inverse-amplifying the accumulated signal and outputting an inverse-amplified signal to said output line; and processing means (M 21 to M 25 , C T ) for processing the signals from said plurality of pixels and said memory means, and outputting the signals to said output line, wherein said noise removal means is arranged to remove a noise component of the amplified signal, outputted from said first transistor, corresponding to the electric signal from said photoelectric conversion means using said memory means and said processing means. A solid-state image sensing device according to claim 6 depending from claim 2, wherein said inverting-amplification means (M 13 , M 14 ), said memory means (M 31 to M 33 , C S ) and said processing means (M 21 to M 27 , C T ) comprise MOS transistors. A solid-state image sensing device according to either of claims 6 or 7, wherein said memory means (M 31 to M 33 , C S ) is arranged to invert a signal outputted from said processing means (M 21 to M 27 , C T ), add an offset component (N M ) of said fifth transistor, then output the added signal as an image signal (-S) from which an offset component (N S ) of said first transistor, the offset component of said fifth transistor and an offset component (N T ) of said processing means are removed. A solid-state image sensing device according to any of claims 6 to 8, wherein said processing means includes a capacitor (C T ), and is arranged to operate an input signal by changing voltages at both terminals of the capacitor. A solid-state image sensing device according to claim 8, depending from claim 2, further comprising a switching means (M 14 , M 15 ), connected between the capacitor (C T ) and said inverting amplification means (M 13 , M 14 ), for controlling one terminal of the capacitor to be in a floating state or to have a fixed voltage. A solid-state image sensing device according to any of claims 6 to 10, depending from claim 2, wherein said processing means comprises: first transfer means for inverting polarity of an input signal from said inverting-amplification means (M 13 , M 14 ) and outputting it after adding the offset component of said processing means, and second transfer means for inverting an input signal from said inverting-amplification means, adding the inverted signal to a signal inputted from said memory means (M 31 to M 33 , C S ), and outputting the added signal after adding the offset component of said processing means. A solid-state image sensing device according to any of claims 6 to 10, wherein said processing means comprises: first transfer means for outputting a signal inputted from said inverting-amplification means (M 13 , M 14 ) after adding the offset component of said processing means; second transfer means for inverting polarity of a signal input from said inverting-amplification means and outputting a signal obtained by adding the offset component of said processing means to the input signal; and third transfer means for inverting an input signal from said inverting-amplification means, adding the inverted signal to a signal inputted from said memory means (M 31 to M 33 , C S ), and outputting the added signal after adding the offset component of said processing means. The solid-state image sensing device according to claim 12, wherein said first transfer means is arranged to output the added signal as an image signal (-S 1 ) from which the offset component of said first transistor, the offset component of said fifth transistor, and the offset component of said processing means are removed, and said memory means (M 31 to M 33 , C S ) is arranged to invert a signal inputted from said third transfer means, add the offset component of said fifth transistor to the input signal, and output the added signal as an image signal (-S 2 ) from which the offset component of said first transistor, the offset component of said fifth transistor, and the offset component of said processing means are removed. The solid-state image sensing device according to claim 13, wherein the image signal (-S 1 ) outputted from said first transfer means (M 21 to M 27 , C T ) corresponds to a photoelectric signal obtained in the middle of storage operation by said photoelectric conversion means (D), and the image signal (-S 2 ) outputted from said memory means (M 31 to M 33 , C S ) corresponds to photoelectric signal obtained after completing the storage operation by said photoelectric conversion means. A method controlling a solid-state image sensing device having a sensor cell unit, a transfer unit, a memory cell unit and outputting an image signal after removing a first noise (N S ) which is an offset component of the sensor cell unit, second noise (N T ) which is an offset component of the transfer unit, and third noise (N M ) which is an offset component of the memory cell, said method comprising: a first output step ( S1 ) of outputting the first noise of the sensor cell unit to the transfer unit; a second output step (S2) of inverting the first noise outputted at said first output step and outputting a signal to the memory cell unit after adding the second noise to the inverted first noise; a photoelectric conversion step of photoelectric converting incoming light into electric charge; a third output step (S3) of inverting and amplifying the electric charge obtained at said photoelectric conversion step, adding the first noise, and outputting the resultant signal to the transfer unit; a fourth output step (S4) of inverting the signal outputted at said second output step, adding the third noise to the inverted signal, and outputting the resultant signal to the transfer unit; a fifth output step (S5) of inverting the signal outputted at said third output step, adding the signal outputted at said fourth output step to the signal outputted at said third output step and the second noise to the inverted signal, and outputting the resultant signal to the memory cell unit; and a sixth output step (S6) of inverting the signal outputted at said fifth output step, adding the third noise, and outputting the resultant signal. A method of controlling a solid-state image sensing device having a sensor cell unit, a transfer unit, a memory cell unit and outputting an image signal after removing a first noise (N S ) which is an offset component of the sensor cell unit, second noise (N T ) which is an offset component of the transfer unit, and third noise (N M ) which is an offset component of the memory cell, said method comprising: a first output step (S11) of outputting the first noise of the sensor cell to the transfer unit; a second output step (S12) of adding the second noise to the first noise outputted at said first output step and outputting the resultant signal to the sensor cell unit; a third output step (S13) of storing the signal outputted at said second step, inverting the signal, adding the first noise to the inverted signal, and outputting the resultant signal to the transfer unit; a fourth output step (S14) of inverting the signal outputted at said third output step, adding the second noise to the inverted signal, and outputting the resultant signal to the memory cell unit; a first photoelectric conversion step of photoelectric converting incoming light into electric charge in the sensor cell unit; a fifth output step (S15) of inverting and amplifying the electric charge obtained at said first photoelectric conversion step in the sensor cell unit, adding the stored signal outputted at said second output step and the first noise to the inverted and amplified signal, and outputting the resultant signal to the transfer unit; a sixth output step (S16) of adding the second noise to the signal outputted at said fifth output step, and outputting the resultant signal as an image signal; a second photoelectric conversion step of photoelectric converting incoming light into electric charge in the sensor cell unit; a seventh output step (S17) of inverting and amplifying the charge obtained at said second photoelectric conversion step in the sensor cell unit, adding the stored signal outputted at said second output step and the first noise to the inverted and amplified signal, and outputting the resultant signal to the transfer unit; an eighth output step (S18) of inverting the signal outputted at said fourth output step, adding the third noise to the inverted signal, and outputting the resultant signal to the transfer unit; a ninth output step (S19) of inverting the signal outputted at said seventh output step, adding the signal outputted at said eighth output step and the second noise to the inverted signal, and outputting the resultant signal to the memory cell unit; and a tenth output step (S110) of inverting the signal outputted at said ninth output step, adding the third noise to the inverted signal, and outputting the resultant signal as an image signal. The method of controlling a solid-state image sensing device according to claim 16, wherein the signal outputted at said sixth output step (S16) is an image signal corresponding to the electric charge obtained in the middle of photoelectric charge storage operation by photoelectric conversion means and the signal outputted at said tenth output step (S110) is an image signal corresponding to the electric charge obtained after completing the photoelectric charge storage operation by the photoelectric conversion means.

Inventors: SHINOHARA MAHITO, TAKAHASHI HIDEKAZU, SHINOHARA, MAHITO, TAKAHASHI, HIDEKAZU, SHINOHARA, MAHITO, CANON K.K., TAKAHASHI, HIDEKAZU, CANON K.K.
Applicants: CANON KK, CANON KABUSHIKI KAISHA
Application year: 1996
Main classification: H04N3
IPC codes: H04N3