Charge coupled device with high charge transfer efficiency

Abstract: In a charge coupled device including a semiconductor substrate (1) having a semiconductor region (2'-1, 2-2, ··· , 3-1, 3-2, ···), a plurality of nonactive barrier electrodes (E0', E0), a plurality of first electrodes (E1', E1) and a plurality of second electrodes (E2) arranged between the nonactive barrier electrodes, an outermost one (E0') of the nonactive barrier electrodes is electrically isolated from the others (E0) of the nonactive barrier electrodes.

Description: The present invention relates to a charge coupled device. A prior art charge coupled device according to the preamble of claim 1 includes a semiconductor substrate having a semiconductor region, a plurality of nonactive barrier electrodes, a plurality of first electrodes and a plurality of second electrodes arranged between the nonactive barrier electrodes. Also, a floating diffusion region is provided as an output portion (see: JP-A-6-314706). This will be explained later in detail. In the above-described prior art charge coupled device, however, the width of the floating diffusion region is smaller than the width of the semiconductor region, to enhance the sensitivity for detection of signal charge. Further, in order to obtain a full amount of signal charge in the direction of the signal flow, the outermost one of the first electrodes is long. As a result, the efficiency of transfer of charge in the direction of the signal flow is reduced. It is an object of the present invention to provide a charge coupled device having a high charge transfer efficiency. This object is achieved by a charge coupled device as defined in claim 1; the remaining claims are related to further developments of the invention. According to the present invention, in a charge coupled device including a semiconductor substrate having a semiconductor region, a plurality of nonactive barrier electrodes, a plurality of first electrodes and a plurality of second electrodes arranged between the nonactive barrier electrodes, an outermost one of the nonactive barrier electrodes is electrically isolated from the others of the nonactive barrier electrodes. When a first voltage is applied to the outermost nonactive barrier electrode and a second voltage different from the first voltage is applied to the other nonactive barrier electrode, the direction of transfer of signal charge is clearly determined. The present invention will be more clearly understood from the description as set forth below, as compared with the prior art, with reference to the accompanying drawings, wherein: Fig. 1A is a cross-sectional view illustrating a prior art charge coupled device; Fig. 1B is a plan view of the device of Fig. 1A; Figs. 2A and 2B are timing diagrams showing the voltages applied to the device of Figs. 1A and 1B; Figs. 3A, 3B and 3C are potential diagrams for explaining the operation of the device of Figs. 1A and 1B; Figs. 4A and 4B are enlarged potential diagrams of Fig. 3A; Fig. 5A is a cross-sectional view illustrating an embodiment of the charge coupled device according to the present invention; Fig. 5B is a plan view of the device of Fig. 5A; Figs. 6A and 6B are timing diagrams showing the voltages applied to the device of Figs. 5A and 5B; Figs. 7A, 7B and 7C are potential diagrams for explaining the operation of the device of Figs. 5A and 5B; Figs. 8A and 8B are enlarged potential diagrams of Fig. 7A; Fig. 9 is a cross-sectional view illustrating a modification of the device of Fig. 5A; Fig. 10 is a cross-sectional view illustrating another modification of the device of Fig. 5A; and Figs. 11A and 11B are timing diagrams showing the voltages applied to the device of Fig 10. Before the description of the preferred embodiment, a prior art charge coupled device will be explained with reference to Figs. 1A, 1B, 2A, 2B, 3A, 3B, 3C, 4A and 4B. Fig. 1A is a cross-sectional view illustrating a prior art buried channel charge coupled device, and Fig. 1B is a plan view of Fig. 1A. Note that Fig. 1A is a cross-sectional view taken along the line A-A of Fig. 1B (see: JP-A-6-314706). In Fig. 1A, reference numeral 1 designates a P-type semiconductor substrate on which N-type semiconductor regions 2-1, 2-2, ···, and N--type semiconductor regions 3-1, 3-2, ··· therebetween are formed. Also, an N + -type semiconductor region 4 is formed as a floating diffusion region on the semiconductor substrate 1 adjacent to the outermost N-type semiconductor region 2-1. Further, an N-type semiconductor region 5, an N + -type semiconductor region 6 for receiving a reference voltage V R , and a grounded P + -type semiconductor region 7 serving as an isolation region are formed on the semiconductor substrate 1. Note that the floating diffusion region 4 is connected to a source follower 8 which generates an output voltage V out . As illustrated in Figs. 1A and 1B, electrodes E0 for receiving a constant voltage V M are formed via an insulating layer (not shown) on half of each of the N-type semiconductor regions 2-1, 2-2, ···. Also, electrodes E1 for receiving a pulse voltage  1 are formed via an insulating layer (not shown) on half of each of the N-type semiconductor regions 2-1, 2-3, ··· and on the N - -type semiconductor regions 3-1, 3-3, ···. Further, electrodes E2 for receiving a pulse voltage  2 are formed via an insulating layer (not shown) on half of each of the N-type semiconductor regions 2-2, 2-4, ··· and on the N - -type semiconductor regions 3-2, 3-4, ···. Further, an electrode E3 for receiving a reset voltage  R is formed via an insulating layer (not shown) on the N-type semiconductor region 4. The operation of the buried channel charge coupled device of Figs. 1A and 1B is explained with reference to Figs. 2A and 2B and Figs. 3A, 3B and 3C. The pulse voltages  1 and  2 are changed as shown in Fig. 2A to carry out a two-phase operation. In this case, V H is a high level of the pulse voltages  1 and  2 and V L is a low level of the pulse voltages  1 and  2 . Also, the voltage V M applied to the electrodes E0 is between V H and V L , and the electrodes E0 serve as nonactive barrier electrodes. Further, the reset voltage  R applied to the electrode E3 is changed as shown in Fig. 2B. That is, the potential at the N + -type semiconductor region 4 is the same as that at the N + -type semiconductor region 6 at each two-phase operation. First, in a state I where the pulse voltages  1 and  2 are V H and V L , respectively, the potential within the device is shown in Fig. 3A. That is, the potential wells within the regions 3-2, 2-2, 3-1 and 2-1 induced by the pulse voltages  1 and  2 are deeper in the direction of the signal flow. As a result, signal charge Q 1 is stored in the potential well of the N-type semiconductor region 2-1. Similarly, signal charge Q 2 is stored in the potential well of the N-type semiconductor region 2-3. Next, the control enters a state II where the pulse voltages  1 and  2 are V L and V H , respectivly. The potential within the device is shown in Fig. 3B. That is, the potential wells within the regions 3-1, 2-1 and 4 are deeper in the direction of the signal flow. As a result, the signal charge Q 1 is transferred from the potential well of the N-type semiconductor region 2-1 to the potential well of the N-type semiconductor region 4. Similarly, the signal charge Q 2 is transferred from the potential well of the N-type semiconductor region 2-3 to the potential well of the N-type semiconductor region 2-2, and signal charge Q 3 is transferred from the potential well of the N-type semiconductor region 2-5 (not shown) to the potential well of the N-type semiconductor region 2-4. In this state, an impedance transformation is performed upon the signal charge Q 1 at the N + -type semiconductor region (floating diffusion region) 4 by the source follower 8, to generate the output voltage V out represented by V out = Q 1 / C · G where C is a capacitance of the floating diffusion region 4, and G is a voltage gain of the source follower 8. Next, the control enters a state III where the reset voltage  R is high, the potential at the N + -type semiconductor region 4 is again the same as that at the N + -type semiconductor region 6 to prepare for the detection of the next signal charge as shown in Fig. 3C. The above-mentioned process is repeated to sequentially generate signal charges as the output voltage V out . In the above-described prior art buried channel charge coupled device, a width W' of the N + -type semiconductor region (floating diffusion region) 4 is smaller than a width W of the semiconductor regions 3-1, 2-2, 3-2, 2-3, 3-3, .., to enhance the sensitivity for detection of signal charge. In this case, however, in order to obtain a full amount of signal charge in the direction of the signal flow, the maximum storage amount of charge by the shaded well S1 of the N-type semiconductor region 2-1 should be equalized with that by the shaded well S2 of the N-type semiconductor region 2-2. That is, the area of the shaded well S1 should be the same as that of the shaded well S2. As a result, the length L10 of the shaded well S1 is longer than the length L20 of the shaded well S2, and accordingly, the length L1 of the outermost electrode E1 is longer than the length L2 of the outermost electrode E2. That is, L1 > L2 This reduces the efficiency of transfer of charge in the direction of the signal flow. Particularly, as shown in Fig. 4A, when the amount of signal charge A is small, the large length L10 of the shaded well S1 of the N-type semiconductor region 2-1 reduces the efficiency of transfer of charge in the direction of the signal flow. Note that, as shown in Fig. 4B, even when excess signal charge C in addition to large signal charge B is stored in the potential wells beneath the electrode E1 (L1), half of the signal charge C may be transferred in the opposite direction of the signal flow, which may adversely affect the efficiency of transfer of charge in the direction of the signal flow. Fig. 5A is a cross-sectional view illustrating an embodiment of the charge coupled device according to the present invention, and Fig. 5B is a plan view of Fig. 5B. Note that Fig. 5A is a cross-sectional view taken along the line A-A of Fig. 5B. In Figs. 5A and 5B, the outermost electrode of the electrodes E0 of Figs. 1A and 1B denoted by E0' is electrically isolated from the other electrodes E0, and a voltage V M ', which is different from the voltage V M , is applied to the electrode E0'. Also, the outermost N-type semiconductor region 2-1 of Figs. 1A and 1B is replaced by an N-type semiconductor region 2'-1 whose length L2' is smaller than the length L1 of the outermost N-type semiconductor region 2-1 of Figs. 1A and 1B, and accordingly, the outermost electrode E1 of Figs. 1A and 1B is replaced by an electrode E1' whose length L1' is smaller than the length L1 of the electrode E1. For example, the length L1' of the electrode E1 is L1' ≒ L2 In Figs. 5A and 5B, the electrode E0' also serves as a nonactive barrier electrode. However, as shown in Fig. 6A, the voltage V M ' applied to the electrode E0' is higher than the voltage V M applied to the electrodes E0, so that the potential well within the region 2'-1 beneath the electrode E0' is deeper than the potential well within the regions 2-2, 2-3, ··· beneath the electrodes E0. The transfer operation of the device of Figs. 5A' and 5B is carried out by changing the pulse voltages  1 and  2 and the reset voltage  R as shown in Figs. 6A and 6B. First, in a state I where the pulse voltages  1 and  2 are V H and V L , respectively, the potential within the device is shown in Fig. 7A. That is, the potential wells within the regions 3-2, 2-2, 3-1 and 2'-1 induced by the pulse voltages  1 and  2 are deeper in the direction of the signal flow. As a result, signal charge Q 1 is stored in the potential well of the N-type semiconductor region 2-1. Similarly, signal charge Q 2 is stored in the potential well of the N-type semiconductor region 2-3. Next, the control enters a state II where the pulse voltages  1 and  2 are V L and V H , respectively, the potential within the device is shown in Fig. 7B, That is, the potential wells within the regions 3-1, 2'-1 and 4 are deeper in the direction of the signal flow. As a result, the signal charge Q 1 is transferred from the potential well of the N-type semiconductor region 2-1 to the potential well of the N-type semiconductor region 4. In this case, since the length L1' of the electrode E1' can be reduced, the efficiency of transfer of charge can be enhanced. This will be explained later in detail. Similarly, the signal charge Q 2 is transferred from the potential well of the N-type semiconductor region 2-3 to the potential well of the N-type semiconductor region 2-2, and signal charge Q 3 is transferred from the potential well of the N-type semiconductor region 2-5 (not shown) to the potential well of the N-type semiconductor region 2-4. In this state, an impedance transformation is performed upon the signal charge Q 1 at the N + -type semiconductor region (floating diffusion region) 4 by the source follower 8, to generate the output voltage V out . Next, the control enters a state III where the reset voltage  R is made high, the potential at the N + -type semiconductor region 4 is again the same as that at the N + -type semiconductor region 6 to prepare for the detection of the next signal charge as shown in Fig. 7C. The above-mentioned process is repeated to sequentially generate signal charges as the output voltage V out . Particularly, as shown in Fig. 8A, when the amount of signal charge A is small, the small length L10' of the potential well of the N-type semiconductor region 2'-1 beneath the electrode E1' enhances the efficiency of transfer of charge in the direction of the signal flow. On the other hand, as shown in Fig. 8B, when excess signal charge C in addition to large signal charge B is stored in the potential wells beneath the electrode E1 (L1'), region 2'-1, all of the signal charge C may be transferred in the direction of the signal flow, since the potential well beneath the electrode E0' is deeper than the potential well beneath the electrode E0. This contributes to the enhancement of the efficiency of transfer of charge in the direction of the signal flow. In Fig. 5A, the regions 2'-1, 2-2, 2-3, 2-4, ··· are denoted by N, and the regions 3-1, 3-2, 3-3, ··· are denoted by N - . Note that, if the regions 2'-1, 2-2, 2-3, 2-4, ··· are denoted by N + ,the regions 3-1, 3-2, 3-3, ··· can be denoted by N. That is, if the concentration of N-type impurity of the regions 2'-2, 2-2, 2-3, 2-4, ··· is larger than that of N-type impurity of the regions 3-1, 3-2, 3-3, 3-4, ···, the direction of the signal flow can be determined. Also, the present invention can be applied to a surface channel charge coupled device as illustrated in Fig. 9. In this case, the regions 2'-1, 2-2, 2-3, 2-4, ··· , and 3-1, 3-2, 3-3, 3-4, ··· are of a P-type. Further, the concentration of P-type impurity of the regions 2'-2, 2-2, 2-3, 2-4, ··· is smaller than that of P-type impurity of the regions 3-1, 3-2, 3-3, 3-4, ···, the direction of the signal flow can be determined. Further, the present invention can be applied to' a P-channel type buried channel charge coupled device as illustrated in Fig. 10, where the polarity of conductivity is reversed, so that holes are transferred. In this case, the pulse voltages  1 and  2 and the reset voltage  R are changed as shown in Figs. 11A and 11B. As explained hereinabove, according to the present invention, since the direction of the signal flow can be clearly determined and the length of the outermost electrode can be reduced, the efficiency of transfer of charge can be enhanced.

Claims: A charge coupled device comprising: a semiconductor substrate (1) having a semiconductor region (2'-1, 2-2, ..., 3-1, 3-2, ..., 4) thereon; a plurality of first electrodes (E0', E0) formed over said semiconductor region; a plurality of second electrodes (E1', E1) formed over said semiconductor region, each of second electrodes being arranged between two of said first electrodes; and a plurality of third electrodes (E2) formed over said semiconductor region, each of said third electrodes being arranged between two of said first electrodes, and between two of said second electrodes, characterized in that an outermost one (E0') of said first electrodes is electrically isolated from the others of said first electrodes. The device as set forth in claim 1, wherein said semiconductor region comprises: a plurality of first semiconductor regions (2'-1, 2-2, ...) formed on said semiconductor substrate; a plurality of second semiconductor regions (3-1, 3-2, ...) formed on said semiconductor substrate, each of said second semiconductor regions being arranged between two adjacent ones of said first semiconductor regions; and a third semiconductor region (4) formed on said semiconductor substrate and adjacent to an outermost one (2'-1) of said first semiconductor regions, each of said first electrodes (E0', E0) being formed over a first part of one of said first semiconductor regions, each of said second electrodes (E1', E1, E2) being formed over a second part of one of said first semiconductor regions and one of said second semiconductor regions. The device as set forth in claim 2, wherein a first voltage (V M ') is applied to the outermost one (E0') of said first electrodes and a second voltage (V M ) different from said first voltage is applied to the others of said first electrodes, so that a potential well within said first semiconductor regions beneath the outermost one of said first electrodes is deeper than potential wells within said first semiconductor regions beneath the others of said first electrodes. The device as set forth in claim 2, wherein conductivity types of said first, second and third semiconductor regions are opposite to a conductivity type of said semiconductor substrate. The device as set forth in claim 2, wherein conductivity types of said first and second semiconductor regions are the same as a conductivity type of said semiconductor substrate, and a conductivity type of said third semiconductor region is opposite to the conductivity type of said semiconductor substrate. The device as set forth in claim 2, wherein every two of said second electrodes are operated by two opposite phase voltages. The device as set forth in claim 1, wherein said first electrodes are nonactive barrier electrodes, said nonactive barrier electrodes receiving voltages such that said semiconductor region beneath said first electrodes passes signal charge therethrough and stores no signal charge. The device as set forth in claim 1, wherein the others of said first electrodes are connected to each other.

Inventors: NAKASHIBA YASUTAKA, NAKASHIBA, YASUTAKA, NAKASHIBA, YASUTAKA, C/O NEC CORPORATION
Applicants: NIPPON ELECTRIC CO, NEC CORPORATION
Application year: 1996
Main classification: G11C19
IPC codes: H01L29, G11C19, H01L21